1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */ 4 /* Copyright 2019 Collabora ltd. */ 5 #include <linux/bitfield.h> 6 #include <linux/bitmap.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #include "panfrost_device.h" 16 #include "panfrost_features.h" 17 #include "panfrost_issues.h" 18 #include "panfrost_gpu.h" 19 #include "panfrost_perfcnt.h" 20 #include "panfrost_regs.h" 21 22 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data) 23 { 24 struct panfrost_device *pfdev = data; 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); 27 28 if (!state) 29 return IRQ_NONE; 30 31 if (state & GPU_IRQ_MASK_ERROR) { 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); 34 35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", 36 fault_status & 0xFF, panfrost_exception_name(pfdev, fault_status), 37 address); 38 39 if (state & GPU_IRQ_MULTIPLE_FAULT) 40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); 41 42 gpu_write(pfdev, GPU_INT_MASK, 0); 43 } 44 45 if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED) 46 panfrost_perfcnt_sample_done(pfdev); 47 48 if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED) 49 panfrost_perfcnt_clean_cache_done(pfdev); 50 51 gpu_write(pfdev, GPU_INT_CLEAR, state); 52 53 return IRQ_HANDLED; 54 } 55 56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) 57 { 58 int ret; 59 u32 val; 60 61 gpu_write(pfdev, GPU_INT_MASK, 0); 62 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); 63 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); 64 65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, 66 val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); 67 68 if (ret) { 69 dev_err(pfdev->dev, "gpu soft reset timed out\n"); 70 return ret; 71 } 72 73 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); 74 gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); 75 76 return 0; 77 } 78 79 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) 80 { 81 u32 quirks = 0; 82 83 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) || 84 panfrost_has_hw_issue(pfdev, HW_ISSUE_11035)) 85 quirks |= SC_LS_PAUSEBUFFER_DISABLE; 86 87 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327)) 88 quirks |= SC_SDC_DISABLE_OQ_DISCARD; 89 90 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797)) 91 quirks |= SC_ENABLE_TEXGRD_FLAGS; 92 93 if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) { 94 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */ 95 quirks |= SC_LS_ATTR_CHECK_DISABLE; 96 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */ 97 quirks |= SC_LS_ALLOW_ATTR_TYPES; 98 } 99 100 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING)) 101 quirks |= SC_TLS_HASH_ENABLE; 102 103 if (quirks) 104 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); 105 106 107 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); 108 109 /* Set tiler clock gate override if required */ 110 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953)) 111 quirks |= TC_CLOCK_GATE_OVERRIDE; 112 113 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); 114 115 116 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); 117 118 /* Limit read & write ID width for AXI */ 119 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG)) 120 quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS | 121 L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES); 122 else 123 quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS | 124 L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES); 125 126 gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks); 127 128 quirks = 0; 129 if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) && 130 pfdev->features.revision >= 0x2000) 131 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT; 132 else if (panfrost_model_eq(pfdev, 0x6000) && 133 pfdev->features.coherency_features == COHERENCY_ACE) 134 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) << 135 JM_FORCE_COHERENCY_FEATURES_SHIFT; 136 137 if (quirks) 138 gpu_write(pfdev, GPU_JM_CONFIG, quirks); 139 } 140 141 #define MAX_HW_REVS 6 142 143 struct panfrost_model { 144 const char *name; 145 u32 id; 146 u32 id_mask; 147 u64 features; 148 u64 issues; 149 struct { 150 u32 revision; 151 u64 issues; 152 } revs[MAX_HW_REVS]; 153 }; 154 155 #define GPU_MODEL(_name, _id, ...) \ 156 {\ 157 .name = __stringify(_name), \ 158 .id = _id, \ 159 .features = hw_features_##_name, \ 160 .issues = hw_issues_##_name, \ 161 .revs = { __VA_ARGS__ }, \ 162 } 163 164 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \ 165 {\ 166 .revision = (_rev) << 12 | (_p) << 4 | (_s), \ 167 .issues = hw_issues_##name##_r##_rev##p##_p##stat, \ 168 } 169 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, ) 170 171 static const struct panfrost_model gpu_models[] = { 172 /* T60x has an oddball version */ 173 GPU_MODEL(t600, 0x600, 174 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)), 175 GPU_MODEL(t620, 0x620, 176 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)), 177 GPU_MODEL(t720, 0x720), 178 GPU_MODEL(t760, 0x750, 179 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1), 180 GPU_REV_EXT(t760, 0, 1, 0, _50rel0), 181 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)), 182 GPU_MODEL(t820, 0x820), 183 GPU_MODEL(t830, 0x830), 184 GPU_MODEL(t860, 0x860), 185 GPU_MODEL(t880, 0x880), 186 187 GPU_MODEL(g71, 0x6000, 188 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)), 189 GPU_MODEL(g72, 0x6001), 190 GPU_MODEL(g51, 0x7000), 191 GPU_MODEL(g76, 0x7001), 192 GPU_MODEL(g52, 0x7002), 193 GPU_MODEL(g31, 0x7003, 194 GPU_REV(g31, 1, 0)), 195 }; 196 197 static void panfrost_gpu_init_features(struct panfrost_device *pfdev) 198 { 199 u32 gpu_id, num_js, major, minor, status, rev; 200 const char *name = "unknown"; 201 u64 hw_feat = 0; 202 u64 hw_issues = hw_issues_all; 203 const struct panfrost_model *model; 204 int i; 205 206 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); 207 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); 208 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); 209 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); 210 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES); 211 pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES); 212 pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS); 213 pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE); 214 pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE); 215 pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES); 216 for (i = 0; i < 4; i++) 217 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i)); 218 219 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); 220 221 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); 222 num_js = hweight32(pfdev->features.js_present); 223 for (i = 0; i < num_js; i++) 224 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i)); 225 226 pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO); 227 pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32; 228 229 pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO); 230 pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32; 231 232 pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO); 233 pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32; 234 pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present); 235 236 pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO); 237 pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32; 238 239 pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC); 240 241 gpu_id = gpu_read(pfdev, GPU_ID); 242 pfdev->features.revision = gpu_id & 0xffff; 243 pfdev->features.id = gpu_id >> 16; 244 245 /* The T60x has an oddball ID value. Fix it up to the standard Midgard 246 * format so we (and userspace) don't have to special case it. 247 */ 248 if (pfdev->features.id == 0x6956) 249 pfdev->features.id = 0x0600; 250 251 major = (pfdev->features.revision >> 12) & 0xf; 252 minor = (pfdev->features.revision >> 4) & 0xff; 253 status = pfdev->features.revision & 0xf; 254 rev = pfdev->features.revision; 255 256 gpu_id = pfdev->features.id; 257 258 for (model = gpu_models; model->name; model++) { 259 int best = -1; 260 261 if (!panfrost_model_eq(pfdev, model->id)) 262 continue; 263 264 name = model->name; 265 hw_feat = model->features; 266 hw_issues |= model->issues; 267 for (i = 0; i < MAX_HW_REVS; i++) { 268 if (model->revs[i].revision == rev) { 269 best = i; 270 break; 271 } else if (model->revs[i].revision == (rev & ~0xf)) 272 best = i; 273 } 274 275 if (best >= 0) 276 hw_issues |= model->revs[best].issues; 277 278 break; 279 } 280 281 bitmap_from_u64(pfdev->features.hw_features, hw_feat); 282 bitmap_from_u64(pfdev->features.hw_issues, hw_issues); 283 284 dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x", 285 name, gpu_id, major, minor, status); 286 dev_info(pfdev->dev, "features: %64pb, issues: %64pb", 287 pfdev->features.hw_features, 288 pfdev->features.hw_issues); 289 290 dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x", 291 pfdev->features.l2_features, 292 pfdev->features.core_features, 293 pfdev->features.tiler_features, 294 pfdev->features.mem_features, 295 pfdev->features.mmu_features, 296 pfdev->features.as_present, 297 pfdev->features.js_present); 298 299 dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx", 300 pfdev->features.shader_present, pfdev->features.l2_present); 301 } 302 303 void panfrost_gpu_power_on(struct panfrost_device *pfdev) 304 { 305 int ret; 306 u32 val; 307 308 /* Just turn on everything for now */ 309 gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present); 310 ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, 311 val, val == pfdev->features.l2_present, 100, 1000); 312 if (ret) 313 dev_err(pfdev->dev, "error powering up gpu L2"); 314 315 gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present); 316 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, 317 val, val == pfdev->features.shader_present, 100, 1000); 318 if (ret) 319 dev_err(pfdev->dev, "error powering up gpu shader"); 320 321 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present); 322 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO, 323 val, val == pfdev->features.tiler_present, 100, 1000); 324 if (ret) 325 dev_err(pfdev->dev, "error powering up gpu tiler"); 326 } 327 328 void panfrost_gpu_power_off(struct panfrost_device *pfdev) 329 { 330 gpu_write(pfdev, TILER_PWROFF_LO, 0); 331 gpu_write(pfdev, SHADER_PWROFF_LO, 0); 332 gpu_write(pfdev, L2_PWROFF_LO, 0); 333 } 334 335 int panfrost_gpu_init(struct panfrost_device *pfdev) 336 { 337 int err, irq; 338 339 err = panfrost_gpu_soft_reset(pfdev); 340 if (err) 341 return err; 342 343 panfrost_gpu_init_features(pfdev); 344 345 dma_set_mask_and_coherent(pfdev->dev, 346 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features))); 347 348 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu"); 349 if (irq <= 0) 350 return -ENODEV; 351 352 err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler, 353 IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev); 354 if (err) { 355 dev_err(pfdev->dev, "failed to request gpu irq"); 356 return err; 357 } 358 359 panfrost_gpu_init_quirks(pfdev); 360 panfrost_gpu_power_on(pfdev); 361 362 return 0; 363 } 364 365 void panfrost_gpu_fini(struct panfrost_device *pfdev) 366 { 367 panfrost_gpu_power_off(pfdev); 368 } 369 370 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev) 371 { 372 u32 flush_id; 373 374 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) { 375 /* Flush reduction only makes sense when the GPU is kept powered on between jobs */ 376 if (pm_runtime_get_if_in_use(pfdev->dev)) { 377 flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID); 378 pm_runtime_put(pfdev->dev); 379 return flush_id; 380 } 381 } 382 383 return 0; 384 } 385