1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 5 #include <linux/clk.h> 6 #include <linux/reset.h> 7 #include <linux/platform_device.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/regulator/consumer.h> 10 11 #include "panfrost_device.h" 12 #include "panfrost_devfreq.h" 13 #include "panfrost_features.h" 14 #include "panfrost_gpu.h" 15 #include "panfrost_job.h" 16 #include "panfrost_mmu.h" 17 18 static int panfrost_reset_init(struct panfrost_device *pfdev) 19 { 20 int err; 21 22 pfdev->rstc = devm_reset_control_array_get(pfdev->dev, false, true); 23 if (IS_ERR(pfdev->rstc)) { 24 dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc)); 25 return PTR_ERR(pfdev->rstc); 26 } 27 28 err = reset_control_deassert(pfdev->rstc); 29 if (err) 30 return err; 31 32 return 0; 33 } 34 35 static void panfrost_reset_fini(struct panfrost_device *pfdev) 36 { 37 reset_control_assert(pfdev->rstc); 38 } 39 40 static int panfrost_clk_init(struct panfrost_device *pfdev) 41 { 42 int err; 43 unsigned long rate; 44 45 pfdev->clock = devm_clk_get(pfdev->dev, NULL); 46 if (IS_ERR(pfdev->clock)) { 47 dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock)); 48 return PTR_ERR(pfdev->clock); 49 } 50 51 rate = clk_get_rate(pfdev->clock); 52 dev_info(pfdev->dev, "clock rate = %lu\n", rate); 53 54 err = clk_prepare_enable(pfdev->clock); 55 if (err) 56 return err; 57 58 return 0; 59 } 60 61 static void panfrost_clk_fini(struct panfrost_device *pfdev) 62 { 63 clk_disable_unprepare(pfdev->clock); 64 } 65 66 static int panfrost_regulator_init(struct panfrost_device *pfdev) 67 { 68 int ret; 69 70 pfdev->regulator = devm_regulator_get_optional(pfdev->dev, "mali"); 71 if (IS_ERR(pfdev->regulator)) { 72 ret = PTR_ERR(pfdev->regulator); 73 pfdev->regulator = NULL; 74 if (ret == -ENODEV) 75 return 0; 76 dev_err(pfdev->dev, "failed to get regulator: %d\n", ret); 77 return ret; 78 } 79 80 ret = regulator_enable(pfdev->regulator); 81 if (ret < 0) { 82 dev_err(pfdev->dev, "failed to enable regulator: %d\n", ret); 83 return ret; 84 } 85 86 return 0; 87 } 88 89 static void panfrost_regulator_fini(struct panfrost_device *pfdev) 90 { 91 if (pfdev->regulator) 92 regulator_disable(pfdev->regulator); 93 } 94 95 int panfrost_device_init(struct panfrost_device *pfdev) 96 { 97 int err; 98 struct resource *res; 99 100 mutex_init(&pfdev->sched_lock); 101 mutex_init(&pfdev->reset_lock); 102 INIT_LIST_HEAD(&pfdev->scheduled_jobs); 103 104 spin_lock_init(&pfdev->hwaccess_lock); 105 106 err = panfrost_clk_init(pfdev); 107 if (err) { 108 dev_err(pfdev->dev, "clk init failed %d\n", err); 109 return err; 110 } 111 112 err = panfrost_regulator_init(pfdev); 113 if (err) { 114 dev_err(pfdev->dev, "regulator init failed %d\n", err); 115 goto err_out0; 116 } 117 118 err = panfrost_reset_init(pfdev); 119 if (err) { 120 dev_err(pfdev->dev, "reset init failed %d\n", err); 121 goto err_out1; 122 } 123 124 res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0); 125 pfdev->iomem = devm_ioremap_resource(pfdev->dev, res); 126 if (IS_ERR(pfdev->iomem)) { 127 dev_err(pfdev->dev, "failed to ioremap iomem\n"); 128 err = PTR_ERR(pfdev->iomem); 129 goto err_out2; 130 } 131 132 err = panfrost_gpu_init(pfdev); 133 if (err) 134 goto err_out2; 135 136 err = panfrost_mmu_init(pfdev); 137 if (err) 138 goto err_out3; 139 140 err = panfrost_job_init(pfdev); 141 if (err) 142 goto err_out4; 143 144 /* runtime PM will wake us up later */ 145 panfrost_gpu_power_off(pfdev); 146 147 pm_runtime_set_active(pfdev->dev); 148 pm_runtime_get_sync(pfdev->dev); 149 pm_runtime_mark_last_busy(pfdev->dev); 150 pm_runtime_put_autosuspend(pfdev->dev); 151 152 return 0; 153 err_out4: 154 panfrost_mmu_fini(pfdev); 155 err_out3: 156 panfrost_gpu_fini(pfdev); 157 err_out2: 158 panfrost_reset_fini(pfdev); 159 err_out1: 160 panfrost_regulator_fini(pfdev); 161 err_out0: 162 panfrost_clk_fini(pfdev); 163 return err; 164 } 165 166 void panfrost_device_fini(struct panfrost_device *pfdev) 167 { 168 panfrost_job_fini(pfdev); 169 panfrost_mmu_fini(pfdev); 170 panfrost_gpu_fini(pfdev); 171 panfrost_reset_fini(pfdev); 172 panfrost_regulator_fini(pfdev); 173 panfrost_clk_fini(pfdev); 174 } 175 176 const char *panfrost_exception_name(struct panfrost_device *pfdev, u32 exception_code) 177 { 178 switch (exception_code) { 179 /* Non-Fault Status code */ 180 case 0x00: return "NOT_STARTED/IDLE/OK"; 181 case 0x01: return "DONE"; 182 case 0x02: return "INTERRUPTED"; 183 case 0x03: return "STOPPED"; 184 case 0x04: return "TERMINATED"; 185 case 0x08: return "ACTIVE"; 186 /* Job exceptions */ 187 case 0x40: return "JOB_CONFIG_FAULT"; 188 case 0x41: return "JOB_POWER_FAULT"; 189 case 0x42: return "JOB_READ_FAULT"; 190 case 0x43: return "JOB_WRITE_FAULT"; 191 case 0x44: return "JOB_AFFINITY_FAULT"; 192 case 0x48: return "JOB_BUS_FAULT"; 193 case 0x50: return "INSTR_INVALID_PC"; 194 case 0x51: return "INSTR_INVALID_ENC"; 195 case 0x52: return "INSTR_TYPE_MISMATCH"; 196 case 0x53: return "INSTR_OPERAND_FAULT"; 197 case 0x54: return "INSTR_TLS_FAULT"; 198 case 0x55: return "INSTR_BARRIER_FAULT"; 199 case 0x56: return "INSTR_ALIGN_FAULT"; 200 case 0x58: return "DATA_INVALID_FAULT"; 201 case 0x59: return "TILE_RANGE_FAULT"; 202 case 0x5A: return "ADDR_RANGE_FAULT"; 203 case 0x60: return "OUT_OF_MEMORY"; 204 /* GPU exceptions */ 205 case 0x80: return "DELAYED_BUS_FAULT"; 206 case 0x88: return "SHAREABILITY_FAULT"; 207 /* MMU exceptions */ 208 case 0xC1: return "TRANSLATION_FAULT_LEVEL1"; 209 case 0xC2: return "TRANSLATION_FAULT_LEVEL2"; 210 case 0xC3: return "TRANSLATION_FAULT_LEVEL3"; 211 case 0xC4: return "TRANSLATION_FAULT_LEVEL4"; 212 case 0xC8: return "PERMISSION_FAULT"; 213 case 0xC9 ... 0xCF: return "PERMISSION_FAULT"; 214 case 0xD1: return "TRANSTAB_BUS_FAULT_LEVEL1"; 215 case 0xD2: return "TRANSTAB_BUS_FAULT_LEVEL2"; 216 case 0xD3: return "TRANSTAB_BUS_FAULT_LEVEL3"; 217 case 0xD4: return "TRANSTAB_BUS_FAULT_LEVEL4"; 218 case 0xD8: return "ACCESS_FLAG"; 219 case 0xD9 ... 0xDF: return "ACCESS_FLAG"; 220 case 0xE0 ... 0xE7: return "ADDRESS_SIZE_FAULT"; 221 case 0xE8 ... 0xEF: return "MEMORY_ATTRIBUTES_FAULT"; 222 } 223 224 return "UNKNOWN"; 225 } 226 227 #ifdef CONFIG_PM 228 int panfrost_device_resume(struct device *dev) 229 { 230 struct platform_device *pdev = to_platform_device(dev); 231 struct panfrost_device *pfdev = platform_get_drvdata(pdev); 232 233 panfrost_gpu_soft_reset(pfdev); 234 235 /* TODO: Re-enable all other address spaces */ 236 panfrost_gpu_power_on(pfdev); 237 panfrost_mmu_enable(pfdev, 0); 238 panfrost_job_enable_interrupts(pfdev); 239 panfrost_devfreq_resume(pfdev); 240 241 return 0; 242 } 243 244 int panfrost_device_suspend(struct device *dev) 245 { 246 struct platform_device *pdev = to_platform_device(dev); 247 struct panfrost_device *pfdev = platform_get_drvdata(pdev); 248 249 if (!panfrost_job_is_idle(pfdev)) 250 return -EBUSY; 251 252 panfrost_devfreq_suspend(pfdev); 253 panfrost_gpu_power_off(pfdev); 254 255 return 0; 256 } 257 #endif 258