1c7f66d32SHarigovindan P // SPDX-License-Identifier: GPL-2.0 2c7f66d32SHarigovindan P /* 3c7f66d32SHarigovindan P * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4c7f66d32SHarigovindan P */ 5c7f66d32SHarigovindan P 6c7f66d32SHarigovindan P #include <linux/delay.h> 7c7f66d32SHarigovindan P #include <linux/module.h> 8c7f66d32SHarigovindan P #include <linux/of_device.h> 9c7f66d32SHarigovindan P #include <linux/gpio/consumer.h> 10c7f66d32SHarigovindan P #include <linux/regulator/consumer.h> 11c7f66d32SHarigovindan P 12c7f66d32SHarigovindan P #include <video/mipi_display.h> 13c7f66d32SHarigovindan P 14c7f66d32SHarigovindan P #include <drm/drm_mipi_dsi.h> 15c7f66d32SHarigovindan P #include <drm/drm_modes.h> 16c7f66d32SHarigovindan P #include <drm/drm_panel.h> 17c7f66d32SHarigovindan P #include <drm/drm_print.h> 18c7f66d32SHarigovindan P 19c7f66d32SHarigovindan P struct visionox_rm69299 { 20c7f66d32SHarigovindan P struct drm_panel panel; 21c7f66d32SHarigovindan P struct regulator_bulk_data supplies[2]; 22c7f66d32SHarigovindan P struct gpio_desc *reset_gpio; 23c7f66d32SHarigovindan P struct mipi_dsi_device *dsi; 24c7f66d32SHarigovindan P bool prepared; 25c7f66d32SHarigovindan P bool enabled; 26c7f66d32SHarigovindan P }; 27c7f66d32SHarigovindan P 28c7f66d32SHarigovindan P static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel) 29c7f66d32SHarigovindan P { 30c7f66d32SHarigovindan P return container_of(panel, struct visionox_rm69299, panel); 31c7f66d32SHarigovindan P } 32c7f66d32SHarigovindan P 33c7f66d32SHarigovindan P static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx) 34c7f66d32SHarigovindan P { 35c7f66d32SHarigovindan P int ret; 36c7f66d32SHarigovindan P 37c7f66d32SHarigovindan P ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 38c7f66d32SHarigovindan P if (ret < 0) 39c7f66d32SHarigovindan P return ret; 40c7f66d32SHarigovindan P 41c7f66d32SHarigovindan P /* 42c7f66d32SHarigovindan P * Reset sequence of visionox panel requires the panel to be 43c7f66d32SHarigovindan P * out of reset for 10ms, followed by being held in reset 44c7f66d32SHarigovindan P * for 10ms and then out again 45c7f66d32SHarigovindan P */ 46c7f66d32SHarigovindan P gpiod_set_value(ctx->reset_gpio, 1); 47c7f66d32SHarigovindan P usleep_range(10000, 20000); 48c7f66d32SHarigovindan P gpiod_set_value(ctx->reset_gpio, 0); 49c7f66d32SHarigovindan P usleep_range(10000, 20000); 50c7f66d32SHarigovindan P gpiod_set_value(ctx->reset_gpio, 1); 51c7f66d32SHarigovindan P usleep_range(10000, 20000); 52c7f66d32SHarigovindan P 53c7f66d32SHarigovindan P return 0; 54c7f66d32SHarigovindan P } 55c7f66d32SHarigovindan P 56c7f66d32SHarigovindan P static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx) 57c7f66d32SHarigovindan P { 58c7f66d32SHarigovindan P gpiod_set_value(ctx->reset_gpio, 0); 59c7f66d32SHarigovindan P 60c7f66d32SHarigovindan P return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 61c7f66d32SHarigovindan P } 62c7f66d32SHarigovindan P 63c7f66d32SHarigovindan P static int visionox_rm69299_unprepare(struct drm_panel *panel) 64c7f66d32SHarigovindan P { 65c7f66d32SHarigovindan P struct visionox_rm69299 *ctx = panel_to_ctx(panel); 66c7f66d32SHarigovindan P int ret; 67c7f66d32SHarigovindan P 68c7f66d32SHarigovindan P ctx->dsi->mode_flags = 0; 69c7f66d32SHarigovindan P 70c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); 71c7f66d32SHarigovindan P if (ret < 0) 72c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 73c7f66d32SHarigovindan P "set_display_off cmd failed ret = %d\n", ret); 74c7f66d32SHarigovindan P 75c7f66d32SHarigovindan P /* 120ms delay required here as per DCS spec */ 76c7f66d32SHarigovindan P msleep(120); 77c7f66d32SHarigovindan P 78c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0); 79c7f66d32SHarigovindan P if (ret < 0) { 80c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 81c7f66d32SHarigovindan P "enter_sleep cmd failed ret = %d\n", ret); 82c7f66d32SHarigovindan P } 83c7f66d32SHarigovindan P 84c7f66d32SHarigovindan P ret = visionox_rm69299_power_off(ctx); 85c7f66d32SHarigovindan P 86c7f66d32SHarigovindan P ctx->prepared = false; 87c7f66d32SHarigovindan P return ret; 88c7f66d32SHarigovindan P } 89c7f66d32SHarigovindan P 90c7f66d32SHarigovindan P static int visionox_rm69299_prepare(struct drm_panel *panel) 91c7f66d32SHarigovindan P { 92c7f66d32SHarigovindan P struct visionox_rm69299 *ctx = panel_to_ctx(panel); 93c7f66d32SHarigovindan P int ret; 94c7f66d32SHarigovindan P 95c7f66d32SHarigovindan P if (ctx->prepared) 96c7f66d32SHarigovindan P return 0; 97c7f66d32SHarigovindan P 98c7f66d32SHarigovindan P ret = visionox_rm69299_power_on(ctx); 99c7f66d32SHarigovindan P if (ret < 0) 100c7f66d32SHarigovindan P return ret; 101c7f66d32SHarigovindan P 102c7f66d32SHarigovindan P ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; 103c7f66d32SHarigovindan P 104c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xfe, 0x00 }, 2); 105c7f66d32SHarigovindan P if (ret < 0) { 106c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 107c7f66d32SHarigovindan P "cmd set tx 0 failed, ret = %d\n", ret); 108c7f66d32SHarigovindan P goto power_off; 109c7f66d32SHarigovindan P } 110c7f66d32SHarigovindan P 111c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xc2, 0x08 }, 2); 112c7f66d32SHarigovindan P if (ret < 0) { 113c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 114c7f66d32SHarigovindan P "cmd set tx 1 failed, ret = %d\n", ret); 115c7f66d32SHarigovindan P goto power_off; 116c7f66d32SHarigovindan P } 117c7f66d32SHarigovindan P 118c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x35, 0x00 }, 2); 119c7f66d32SHarigovindan P if (ret < 0) { 120c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 121c7f66d32SHarigovindan P "cmd set tx 2 failed, ret = %d\n", ret); 122c7f66d32SHarigovindan P goto power_off; 123c7f66d32SHarigovindan P } 124c7f66d32SHarigovindan P 125c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x51, 0xff }, 2); 126c7f66d32SHarigovindan P if (ret < 0) { 127c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 128c7f66d32SHarigovindan P "cmd set tx 3 failed, ret = %d\n", ret); 129c7f66d32SHarigovindan P goto power_off; 130c7f66d32SHarigovindan P } 131c7f66d32SHarigovindan P 132c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); 133c7f66d32SHarigovindan P if (ret < 0) { 134c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 135c7f66d32SHarigovindan P "exit_sleep_mode cmd failed ret = %d\n", ret); 136c7f66d32SHarigovindan P goto power_off; 137c7f66d32SHarigovindan P } 138c7f66d32SHarigovindan P 139c7f66d32SHarigovindan P /* Per DSI spec wait 120ms after sending exit sleep DCS command */ 140c7f66d32SHarigovindan P msleep(120); 141c7f66d32SHarigovindan P 142c7f66d32SHarigovindan P ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); 143c7f66d32SHarigovindan P if (ret < 0) { 144c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 145c7f66d32SHarigovindan P "set_display_on cmd failed ret = %d\n", ret); 146c7f66d32SHarigovindan P goto power_off; 147c7f66d32SHarigovindan P } 148c7f66d32SHarigovindan P 149c7f66d32SHarigovindan P /* Per DSI spec wait 120ms after sending set_display_on DCS command */ 150c7f66d32SHarigovindan P msleep(120); 151c7f66d32SHarigovindan P 152c7f66d32SHarigovindan P ctx->prepared = true; 153c7f66d32SHarigovindan P 154c7f66d32SHarigovindan P return 0; 155c7f66d32SHarigovindan P 156c7f66d32SHarigovindan P power_off: 157c7f66d32SHarigovindan P return ret; 158c7f66d32SHarigovindan P } 159c7f66d32SHarigovindan P 160c7f66d32SHarigovindan P static const struct drm_display_mode visionox_rm69299_1080x2248_60hz = { 161c7f66d32SHarigovindan P .name = "1080x2248", 162c7f66d32SHarigovindan P .clock = 158695, 163c7f66d32SHarigovindan P .hdisplay = 1080, 164c7f66d32SHarigovindan P .hsync_start = 1080 + 26, 165c7f66d32SHarigovindan P .hsync_end = 1080 + 26 + 2, 166c7f66d32SHarigovindan P .htotal = 1080 + 26 + 2 + 36, 167c7f66d32SHarigovindan P .vdisplay = 2248, 168c7f66d32SHarigovindan P .vsync_start = 2248 + 56, 169c7f66d32SHarigovindan P .vsync_end = 2248 + 56 + 4, 170c7f66d32SHarigovindan P .vtotal = 2248 + 56 + 4 + 4, 171c7f66d32SHarigovindan P .vrefresh = 60, 172c7f66d32SHarigovindan P .flags = 0, 173c7f66d32SHarigovindan P }; 174c7f66d32SHarigovindan P 175c7f66d32SHarigovindan P static int visionox_rm69299_get_modes(struct drm_panel *panel, 176c7f66d32SHarigovindan P struct drm_connector *connector) 177c7f66d32SHarigovindan P { 178c7f66d32SHarigovindan P struct visionox_rm69299 *ctx = panel_to_ctx(panel); 179c7f66d32SHarigovindan P struct drm_display_mode *mode; 180c7f66d32SHarigovindan P 181c7f66d32SHarigovindan P mode = drm_mode_create(connector->dev); 182c7f66d32SHarigovindan P if (!mode) { 183c7f66d32SHarigovindan P DRM_DEV_ERROR(ctx->panel.dev, 184c7f66d32SHarigovindan P "failed to create a new display mode\n"); 185c7f66d32SHarigovindan P return 0; 186c7f66d32SHarigovindan P } 187c7f66d32SHarigovindan P 188c7f66d32SHarigovindan P connector->display_info.width_mm = 74; 189c7f66d32SHarigovindan P connector->display_info.height_mm = 131; 190c7f66d32SHarigovindan P drm_mode_copy(mode, &visionox_rm69299_1080x2248_60hz); 191c7f66d32SHarigovindan P mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 192c7f66d32SHarigovindan P drm_mode_probed_add(connector, mode); 193c7f66d32SHarigovindan P 194c7f66d32SHarigovindan P return 1; 195c7f66d32SHarigovindan P } 196c7f66d32SHarigovindan P 197c7f66d32SHarigovindan P static const struct drm_panel_funcs visionox_rm69299_drm_funcs = { 198c7f66d32SHarigovindan P .unprepare = visionox_rm69299_unprepare, 199c7f66d32SHarigovindan P .prepare = visionox_rm69299_prepare, 200c7f66d32SHarigovindan P .get_modes = visionox_rm69299_get_modes, 201c7f66d32SHarigovindan P }; 202c7f66d32SHarigovindan P 203c7f66d32SHarigovindan P static int visionox_rm69299_probe(struct mipi_dsi_device *dsi) 204c7f66d32SHarigovindan P { 205c7f66d32SHarigovindan P struct device *dev = &dsi->dev; 206c7f66d32SHarigovindan P struct visionox_rm69299 *ctx; 207c7f66d32SHarigovindan P int ret; 208c7f66d32SHarigovindan P 209c7f66d32SHarigovindan P ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 210c7f66d32SHarigovindan P if (!ctx) 211c7f66d32SHarigovindan P return -ENOMEM; 212c7f66d32SHarigovindan P 213c7f66d32SHarigovindan P mipi_dsi_set_drvdata(dsi, ctx); 214c7f66d32SHarigovindan P 215c7f66d32SHarigovindan P ctx->panel.dev = dev; 216c7f66d32SHarigovindan P ctx->dsi = dsi; 217c7f66d32SHarigovindan P 218c7f66d32SHarigovindan P ctx->supplies[0].supply = "vdda"; 219c7f66d32SHarigovindan P ctx->supplies[1].supply = "vdd3p3"; 220c7f66d32SHarigovindan P 221c7f66d32SHarigovindan P ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies), 222c7f66d32SHarigovindan P ctx->supplies); 223c7f66d32SHarigovindan P if (ret < 0) 224c7f66d32SHarigovindan P return ret; 225c7f66d32SHarigovindan P 226c7f66d32SHarigovindan P ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev, 227c7f66d32SHarigovindan P "reset", GPIOD_OUT_LOW); 228c7f66d32SHarigovindan P if (IS_ERR(ctx->reset_gpio)) { 229c7f66d32SHarigovindan P DRM_DEV_ERROR(dev, "cannot get reset gpio %ld\n", 230c7f66d32SHarigovindan P PTR_ERR(ctx->reset_gpio)); 231c7f66d32SHarigovindan P return PTR_ERR(ctx->reset_gpio); 232c7f66d32SHarigovindan P } 233c7f66d32SHarigovindan P 234c7f66d32SHarigovindan P drm_panel_init(&ctx->panel, dev, &visionox_rm69299_drm_funcs, 235c7f66d32SHarigovindan P DRM_MODE_CONNECTOR_DSI); 236c7f66d32SHarigovindan P ctx->panel.dev = dev; 237c7f66d32SHarigovindan P ctx->panel.funcs = &visionox_rm69299_drm_funcs; 238c7f66d32SHarigovindan P drm_panel_add(&ctx->panel); 239c7f66d32SHarigovindan P 240c7f66d32SHarigovindan P dsi->lanes = 4; 241c7f66d32SHarigovindan P dsi->format = MIPI_DSI_FMT_RGB888; 242c7f66d32SHarigovindan P dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | 243c7f66d32SHarigovindan P MIPI_DSI_CLOCK_NON_CONTINUOUS; 244c7f66d32SHarigovindan P ret = mipi_dsi_attach(dsi); 245c7f66d32SHarigovindan P if (ret < 0) { 246c7f66d32SHarigovindan P DRM_DEV_ERROR(dev, "dsi attach failed ret = %d\n", ret); 247c7f66d32SHarigovindan P goto err_dsi_attach; 248c7f66d32SHarigovindan P } 249c7f66d32SHarigovindan P 250c7f66d32SHarigovindan P ret = regulator_set_load(ctx->supplies[0].consumer, 32000); 251c7f66d32SHarigovindan P if (ret) { 252c7f66d32SHarigovindan P DRM_DEV_ERROR(dev, 253c7f66d32SHarigovindan P "regulator set load failed for vdda supply ret = %d\n", 254c7f66d32SHarigovindan P ret); 255c7f66d32SHarigovindan P goto err_set_load; 256c7f66d32SHarigovindan P } 257c7f66d32SHarigovindan P 258c7f66d32SHarigovindan P ret = regulator_set_load(ctx->supplies[1].consumer, 13200); 259c7f66d32SHarigovindan P if (ret) { 260c7f66d32SHarigovindan P DRM_DEV_ERROR(dev, 261c7f66d32SHarigovindan P "regulator set load failed for vdd3p3 supply ret = %d\n", 262c7f66d32SHarigovindan P ret); 263c7f66d32SHarigovindan P goto err_set_load; 264c7f66d32SHarigovindan P } 265c7f66d32SHarigovindan P 266c7f66d32SHarigovindan P return 0; 267c7f66d32SHarigovindan P 268c7f66d32SHarigovindan P err_set_load: 269c7f66d32SHarigovindan P mipi_dsi_detach(dsi); 270c7f66d32SHarigovindan P err_dsi_attach: 271c7f66d32SHarigovindan P drm_panel_remove(&ctx->panel); 272c7f66d32SHarigovindan P return ret; 273c7f66d32SHarigovindan P } 274c7f66d32SHarigovindan P 275c7f66d32SHarigovindan P static int visionox_rm69299_remove(struct mipi_dsi_device *dsi) 276c7f66d32SHarigovindan P { 277c7f66d32SHarigovindan P struct visionox_rm69299 *ctx = mipi_dsi_get_drvdata(dsi); 278c7f66d32SHarigovindan P 279c7f66d32SHarigovindan P mipi_dsi_detach(ctx->dsi); 280c7f66d32SHarigovindan P mipi_dsi_device_unregister(ctx->dsi); 281c7f66d32SHarigovindan P 282c7f66d32SHarigovindan P drm_panel_remove(&ctx->panel); 283c7f66d32SHarigovindan P return 0; 284c7f66d32SHarigovindan P } 285c7f66d32SHarigovindan P 286c7f66d32SHarigovindan P static const struct of_device_id visionox_rm69299_of_match[] = { 287c7f66d32SHarigovindan P { .compatible = "visionox,rm69299-1080p-display", }, 288c7f66d32SHarigovindan P { /* sentinel */ } 289c7f66d32SHarigovindan P }; 290c7f66d32SHarigovindan P MODULE_DEVICE_TABLE(of, visionox_rm69299_of_match); 291c7f66d32SHarigovindan P 292c7f66d32SHarigovindan P static struct mipi_dsi_driver visionox_rm69299_driver = { 293c7f66d32SHarigovindan P .driver = { 294c7f66d32SHarigovindan P .name = "panel-visionox-rm69299", 295c7f66d32SHarigovindan P .of_match_table = visionox_rm69299_of_match, 296c7f66d32SHarigovindan P }, 297c7f66d32SHarigovindan P .probe = visionox_rm69299_probe, 298c7f66d32SHarigovindan P .remove = visionox_rm69299_remove, 299c7f66d32SHarigovindan P }; 300c7f66d32SHarigovindan P module_mipi_dsi_driver(visionox_rm69299_driver); 301c7f66d32SHarigovindan P 302c7f66d32SHarigovindan P MODULE_DESCRIPTION("Visionox RM69299 DSI Panel Driver"); 303