1c7f66d32SHarigovindan P // SPDX-License-Identifier: GPL-2.0
2c7f66d32SHarigovindan P /*
3c7f66d32SHarigovindan P  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4c7f66d32SHarigovindan P  */
5c7f66d32SHarigovindan P 
6c7f66d32SHarigovindan P #include <linux/delay.h>
7c7f66d32SHarigovindan P #include <linux/module.h>
8*722d4f06SRob Herring #include <linux/mod_devicetable.h>
9c7f66d32SHarigovindan P #include <linux/gpio/consumer.h>
10c7f66d32SHarigovindan P #include <linux/regulator/consumer.h>
11c7f66d32SHarigovindan P 
12c7f66d32SHarigovindan P #include <video/mipi_display.h>
13c7f66d32SHarigovindan P 
14c7f66d32SHarigovindan P #include <drm/drm_mipi_dsi.h>
15c7f66d32SHarigovindan P #include <drm/drm_modes.h>
16c7f66d32SHarigovindan P #include <drm/drm_panel.h>
17c7f66d32SHarigovindan P 
18c7f66d32SHarigovindan P struct visionox_rm69299 {
19c7f66d32SHarigovindan P 	struct drm_panel panel;
20c7f66d32SHarigovindan P 	struct regulator_bulk_data supplies[2];
21c7f66d32SHarigovindan P 	struct gpio_desc *reset_gpio;
22c7f66d32SHarigovindan P 	struct mipi_dsi_device *dsi;
23c7f66d32SHarigovindan P 	bool prepared;
24c7f66d32SHarigovindan P 	bool enabled;
25c7f66d32SHarigovindan P };
26c7f66d32SHarigovindan P 
panel_to_ctx(struct drm_panel * panel)27c7f66d32SHarigovindan P static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel)
28c7f66d32SHarigovindan P {
29c7f66d32SHarigovindan P 	return container_of(panel, struct visionox_rm69299, panel);
30c7f66d32SHarigovindan P }
31c7f66d32SHarigovindan P 
visionox_rm69299_power_on(struct visionox_rm69299 * ctx)32c7f66d32SHarigovindan P static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx)
33c7f66d32SHarigovindan P {
34c7f66d32SHarigovindan P 	int ret;
35c7f66d32SHarigovindan P 
36c7f66d32SHarigovindan P 	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
37c7f66d32SHarigovindan P 	if (ret < 0)
38c7f66d32SHarigovindan P 		return ret;
39c7f66d32SHarigovindan P 
40c7f66d32SHarigovindan P 	/*
41c7f66d32SHarigovindan P 	 * Reset sequence of visionox panel requires the panel to be
42c7f66d32SHarigovindan P 	 * out of reset for 10ms, followed by being held in reset
43c7f66d32SHarigovindan P 	 * for 10ms and then out again
44c7f66d32SHarigovindan P 	 */
45c7f66d32SHarigovindan P 	gpiod_set_value(ctx->reset_gpio, 1);
46c7f66d32SHarigovindan P 	usleep_range(10000, 20000);
47c7f66d32SHarigovindan P 	gpiod_set_value(ctx->reset_gpio, 0);
48c7f66d32SHarigovindan P 	usleep_range(10000, 20000);
49c7f66d32SHarigovindan P 	gpiod_set_value(ctx->reset_gpio, 1);
50c7f66d32SHarigovindan P 	usleep_range(10000, 20000);
51c7f66d32SHarigovindan P 
52c7f66d32SHarigovindan P 	return 0;
53c7f66d32SHarigovindan P }
54c7f66d32SHarigovindan P 
visionox_rm69299_power_off(struct visionox_rm69299 * ctx)55c7f66d32SHarigovindan P static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx)
56c7f66d32SHarigovindan P {
57c7f66d32SHarigovindan P 	gpiod_set_value(ctx->reset_gpio, 0);
58c7f66d32SHarigovindan P 
59c7f66d32SHarigovindan P 	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
60c7f66d32SHarigovindan P }
61c7f66d32SHarigovindan P 
visionox_rm69299_unprepare(struct drm_panel * panel)62c7f66d32SHarigovindan P static int visionox_rm69299_unprepare(struct drm_panel *panel)
63c7f66d32SHarigovindan P {
64c7f66d32SHarigovindan P 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
65c7f66d32SHarigovindan P 	int ret;
66c7f66d32SHarigovindan P 
67c7f66d32SHarigovindan P 	ctx->dsi->mode_flags = 0;
68c7f66d32SHarigovindan P 
69c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
70c7f66d32SHarigovindan P 	if (ret < 0)
71a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "set_display_off cmd failed ret = %d\n", ret);
72c7f66d32SHarigovindan P 
73c7f66d32SHarigovindan P 	/* 120ms delay required here as per DCS spec */
74c7f66d32SHarigovindan P 	msleep(120);
75c7f66d32SHarigovindan P 
76c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0);
77c7f66d32SHarigovindan P 	if (ret < 0) {
78a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "enter_sleep cmd failed ret = %d\n", ret);
79c7f66d32SHarigovindan P 	}
80c7f66d32SHarigovindan P 
81c7f66d32SHarigovindan P 	ret = visionox_rm69299_power_off(ctx);
82c7f66d32SHarigovindan P 
83c7f66d32SHarigovindan P 	ctx->prepared = false;
84c7f66d32SHarigovindan P 	return ret;
85c7f66d32SHarigovindan P }
86c7f66d32SHarigovindan P 
visionox_rm69299_prepare(struct drm_panel * panel)87c7f66d32SHarigovindan P static int visionox_rm69299_prepare(struct drm_panel *panel)
88c7f66d32SHarigovindan P {
89c7f66d32SHarigovindan P 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
90c7f66d32SHarigovindan P 	int ret;
91c7f66d32SHarigovindan P 
92c7f66d32SHarigovindan P 	if (ctx->prepared)
93c7f66d32SHarigovindan P 		return 0;
94c7f66d32SHarigovindan P 
95c7f66d32SHarigovindan P 	ret = visionox_rm69299_power_on(ctx);
96c7f66d32SHarigovindan P 	if (ret < 0)
97c7f66d32SHarigovindan P 		return ret;
98c7f66d32SHarigovindan P 
99c7f66d32SHarigovindan P 	ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
100c7f66d32SHarigovindan P 
101c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xfe, 0x00 }, 2);
102c7f66d32SHarigovindan P 	if (ret < 0) {
103a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "cmd set tx 0 failed, ret = %d\n", ret);
104c7f66d32SHarigovindan P 		goto power_off;
105c7f66d32SHarigovindan P 	}
106c7f66d32SHarigovindan P 
107c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xc2, 0x08 }, 2);
108c7f66d32SHarigovindan P 	if (ret < 0) {
109a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "cmd set tx 1 failed, ret = %d\n", ret);
110c7f66d32SHarigovindan P 		goto power_off;
111c7f66d32SHarigovindan P 	}
112c7f66d32SHarigovindan P 
113c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x35, 0x00 }, 2);
114c7f66d32SHarigovindan P 	if (ret < 0) {
115a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "cmd set tx 2 failed, ret = %d\n", ret);
116c7f66d32SHarigovindan P 		goto power_off;
117c7f66d32SHarigovindan P 	}
118c7f66d32SHarigovindan P 
119c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x51, 0xff }, 2);
120c7f66d32SHarigovindan P 	if (ret < 0) {
121a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "cmd set tx 3 failed, ret = %d\n", ret);
122c7f66d32SHarigovindan P 		goto power_off;
123c7f66d32SHarigovindan P 	}
124c7f66d32SHarigovindan P 
125c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
126c7f66d32SHarigovindan P 	if (ret < 0) {
127a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "exit_sleep_mode cmd failed ret = %d\n", ret);
128c7f66d32SHarigovindan P 		goto power_off;
129c7f66d32SHarigovindan P 	}
130c7f66d32SHarigovindan P 
131c7f66d32SHarigovindan P 	/* Per DSI spec wait 120ms after sending exit sleep DCS command */
132c7f66d32SHarigovindan P 	msleep(120);
133c7f66d32SHarigovindan P 
134c7f66d32SHarigovindan P 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
135c7f66d32SHarigovindan P 	if (ret < 0) {
136a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "set_display_on cmd failed ret = %d\n", ret);
137c7f66d32SHarigovindan P 		goto power_off;
138c7f66d32SHarigovindan P 	}
139c7f66d32SHarigovindan P 
140c7f66d32SHarigovindan P 	/* Per DSI spec wait 120ms after sending set_display_on DCS command */
141c7f66d32SHarigovindan P 	msleep(120);
142c7f66d32SHarigovindan P 
143c7f66d32SHarigovindan P 	ctx->prepared = true;
144c7f66d32SHarigovindan P 
145c7f66d32SHarigovindan P 	return 0;
146c7f66d32SHarigovindan P 
147c7f66d32SHarigovindan P power_off:
148c7f66d32SHarigovindan P 	return ret;
149c7f66d32SHarigovindan P }
150c7f66d32SHarigovindan P 
151c7f66d32SHarigovindan P static const struct drm_display_mode visionox_rm69299_1080x2248_60hz = {
152c7f66d32SHarigovindan P 	.name = "1080x2248",
153c7f66d32SHarigovindan P 	.clock = 158695,
154c7f66d32SHarigovindan P 	.hdisplay = 1080,
155c7f66d32SHarigovindan P 	.hsync_start = 1080 + 26,
156c7f66d32SHarigovindan P 	.hsync_end = 1080 + 26 + 2,
157c7f66d32SHarigovindan P 	.htotal = 1080 + 26 + 2 + 36,
158c7f66d32SHarigovindan P 	.vdisplay = 2248,
159c7f66d32SHarigovindan P 	.vsync_start = 2248 + 56,
160c7f66d32SHarigovindan P 	.vsync_end = 2248 + 56 + 4,
161c7f66d32SHarigovindan P 	.vtotal = 2248 + 56 + 4 + 4,
162c7f66d32SHarigovindan P 	.flags = 0,
163c7f66d32SHarigovindan P };
164c7f66d32SHarigovindan P 
visionox_rm69299_get_modes(struct drm_panel * panel,struct drm_connector * connector)165c7f66d32SHarigovindan P static int visionox_rm69299_get_modes(struct drm_panel *panel,
166c7f66d32SHarigovindan P 				      struct drm_connector *connector)
167c7f66d32SHarigovindan P {
168c7f66d32SHarigovindan P 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
169c7f66d32SHarigovindan P 	struct drm_display_mode *mode;
170c7f66d32SHarigovindan P 
171ec5d4a72SVille Syrjälä 	mode = drm_mode_duplicate(connector->dev,
172ec5d4a72SVille Syrjälä 				  &visionox_rm69299_1080x2248_60hz);
173c7f66d32SHarigovindan P 	if (!mode) {
174a25b6b27SSam Ravnborg 		dev_err(ctx->panel.dev, "failed to create a new display mode\n");
175c7f66d32SHarigovindan P 		return 0;
176c7f66d32SHarigovindan P 	}
177c7f66d32SHarigovindan P 
178c7f66d32SHarigovindan P 	connector->display_info.width_mm = 74;
179c7f66d32SHarigovindan P 	connector->display_info.height_mm = 131;
180c7f66d32SHarigovindan P 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
181c7f66d32SHarigovindan P 	drm_mode_probed_add(connector, mode);
182c7f66d32SHarigovindan P 
183c7f66d32SHarigovindan P 	return 1;
184c7f66d32SHarigovindan P }
185c7f66d32SHarigovindan P 
186c7f66d32SHarigovindan P static const struct drm_panel_funcs visionox_rm69299_drm_funcs = {
187c7f66d32SHarigovindan P 	.unprepare = visionox_rm69299_unprepare,
188c7f66d32SHarigovindan P 	.prepare = visionox_rm69299_prepare,
189c7f66d32SHarigovindan P 	.get_modes = visionox_rm69299_get_modes,
190c7f66d32SHarigovindan P };
191c7f66d32SHarigovindan P 
visionox_rm69299_probe(struct mipi_dsi_device * dsi)192c7f66d32SHarigovindan P static int visionox_rm69299_probe(struct mipi_dsi_device *dsi)
193c7f66d32SHarigovindan P {
194c7f66d32SHarigovindan P 	struct device *dev = &dsi->dev;
195c7f66d32SHarigovindan P 	struct visionox_rm69299 *ctx;
196c7f66d32SHarigovindan P 	int ret;
197c7f66d32SHarigovindan P 
198c7f66d32SHarigovindan P 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
199c7f66d32SHarigovindan P 	if (!ctx)
200c7f66d32SHarigovindan P 		return -ENOMEM;
201c7f66d32SHarigovindan P 
202c7f66d32SHarigovindan P 	mipi_dsi_set_drvdata(dsi, ctx);
203c7f66d32SHarigovindan P 
204c7f66d32SHarigovindan P 	ctx->panel.dev = dev;
205c7f66d32SHarigovindan P 	ctx->dsi = dsi;
206c7f66d32SHarigovindan P 
207c7f66d32SHarigovindan P 	ctx->supplies[0].supply = "vdda";
208c7f66d32SHarigovindan P 	ctx->supplies[1].supply = "vdd3p3";
209c7f66d32SHarigovindan P 
210c7f66d32SHarigovindan P 	ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies),
211c7f66d32SHarigovindan P 				      ctx->supplies);
212c7f66d32SHarigovindan P 	if (ret < 0)
213c7f66d32SHarigovindan P 		return ret;
214c7f66d32SHarigovindan P 
215c7f66d32SHarigovindan P 	ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev,
216c7f66d32SHarigovindan P 					 "reset", GPIOD_OUT_LOW);
217c7f66d32SHarigovindan P 	if (IS_ERR(ctx->reset_gpio)) {
218a25b6b27SSam Ravnborg 		dev_err(dev, "cannot get reset gpio %ld\n", PTR_ERR(ctx->reset_gpio));
219c7f66d32SHarigovindan P 		return PTR_ERR(ctx->reset_gpio);
220c7f66d32SHarigovindan P 	}
221c7f66d32SHarigovindan P 
222c7f66d32SHarigovindan P 	drm_panel_init(&ctx->panel, dev, &visionox_rm69299_drm_funcs,
223c7f66d32SHarigovindan P 		       DRM_MODE_CONNECTOR_DSI);
224c7f66d32SHarigovindan P 	ctx->panel.dev = dev;
225c7f66d32SHarigovindan P 	ctx->panel.funcs = &visionox_rm69299_drm_funcs;
226c7f66d32SHarigovindan P 	drm_panel_add(&ctx->panel);
227c7f66d32SHarigovindan P 
228c7f66d32SHarigovindan P 	dsi->lanes = 4;
229c7f66d32SHarigovindan P 	dsi->format = MIPI_DSI_FMT_RGB888;
230c7f66d32SHarigovindan P 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
231c7f66d32SHarigovindan P 			  MIPI_DSI_CLOCK_NON_CONTINUOUS;
232c7f66d32SHarigovindan P 	ret = mipi_dsi_attach(dsi);
233c7f66d32SHarigovindan P 	if (ret < 0) {
234a25b6b27SSam Ravnborg 		dev_err(dev, "dsi attach failed ret = %d\n", ret);
235c7f66d32SHarigovindan P 		goto err_dsi_attach;
236c7f66d32SHarigovindan P 	}
237c7f66d32SHarigovindan P 
238c7f66d32SHarigovindan P 	ret = regulator_set_load(ctx->supplies[0].consumer, 32000);
239c7f66d32SHarigovindan P 	if (ret) {
240a25b6b27SSam Ravnborg 		dev_err(dev, "regulator set load failed for vdda supply ret = %d\n", ret);
241c7f66d32SHarigovindan P 		goto err_set_load;
242c7f66d32SHarigovindan P 	}
243c7f66d32SHarigovindan P 
244c7f66d32SHarigovindan P 	ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
245c7f66d32SHarigovindan P 	if (ret) {
246a25b6b27SSam Ravnborg 		dev_err(dev, "regulator set load failed for vdd3p3 supply ret = %d\n", ret);
247c7f66d32SHarigovindan P 		goto err_set_load;
248c7f66d32SHarigovindan P 	}
249c7f66d32SHarigovindan P 
250c7f66d32SHarigovindan P 	return 0;
251c7f66d32SHarigovindan P 
252c7f66d32SHarigovindan P err_set_load:
253c7f66d32SHarigovindan P 	mipi_dsi_detach(dsi);
254c7f66d32SHarigovindan P err_dsi_attach:
255c7f66d32SHarigovindan P 	drm_panel_remove(&ctx->panel);
256c7f66d32SHarigovindan P 	return ret;
257c7f66d32SHarigovindan P }
258c7f66d32SHarigovindan P 
visionox_rm69299_remove(struct mipi_dsi_device * dsi)25979abca2bSUwe Kleine-König static void visionox_rm69299_remove(struct mipi_dsi_device *dsi)
260c7f66d32SHarigovindan P {
261c7f66d32SHarigovindan P 	struct visionox_rm69299 *ctx = mipi_dsi_get_drvdata(dsi);
262c7f66d32SHarigovindan P 
263c7f66d32SHarigovindan P 	mipi_dsi_detach(ctx->dsi);
264c7f66d32SHarigovindan P 	drm_panel_remove(&ctx->panel);
265c7f66d32SHarigovindan P }
266c7f66d32SHarigovindan P 
267c7f66d32SHarigovindan P static const struct of_device_id visionox_rm69299_of_match[] = {
268c7f66d32SHarigovindan P 	{ .compatible = "visionox,rm69299-1080p-display", },
269c7f66d32SHarigovindan P 	{ /* sentinel */ }
270c7f66d32SHarigovindan P };
271c7f66d32SHarigovindan P MODULE_DEVICE_TABLE(of, visionox_rm69299_of_match);
272c7f66d32SHarigovindan P 
273c7f66d32SHarigovindan P static struct mipi_dsi_driver visionox_rm69299_driver = {
274c7f66d32SHarigovindan P 	.driver = {
275c7f66d32SHarigovindan P 		.name = "panel-visionox-rm69299",
276c7f66d32SHarigovindan P 		.of_match_table = visionox_rm69299_of_match,
277c7f66d32SHarigovindan P 	},
278c7f66d32SHarigovindan P 	.probe = visionox_rm69299_probe,
279c7f66d32SHarigovindan P 	.remove = visionox_rm69299_remove,
280c7f66d32SHarigovindan P };
281c7f66d32SHarigovindan P module_mipi_dsi_driver(visionox_rm69299_driver);
282c7f66d32SHarigovindan P 
283c7f66d32SHarigovindan P MODULE_DESCRIPTION("Visionox RM69299 DSI Panel Driver");
284e41b49b7SRandy Dunlap MODULE_LICENSE("GPL v2");
285