1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019, Amarula Solutions. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 #include <drm/drm_modes.h> 9 #include <drm/drm_panel.h> 10 11 #include <linux/bitfield.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <video/mipi_display.h> 19 20 /* Command2 BKx selection command */ 21 #define DSI_CMD2BKX_SEL 0xFF 22 #define DSI_CMD1 0 23 #define DSI_CMD2 BIT(4) 24 #define DSI_CMD2BK_MASK GENMASK(3, 0) 25 26 /* Command2, BK0 commands */ 27 #define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */ 28 #define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */ 29 #define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */ 30 #define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */ 31 #define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */ 32 33 /* Command2, BK1 commands */ 34 #define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */ 35 #define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */ 36 #define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */ 37 #define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */ 38 #define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */ 39 #define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */ 40 #define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */ 41 #define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */ 42 #define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */ 43 #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */ 44 45 /* Command2, BK0 bytes */ 46 #define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) 47 #define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) 48 #define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) 49 #define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) 50 #define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) 51 #define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) 52 #define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) 53 #define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) 54 #define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) 55 #define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) 56 #define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) 57 #define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) 58 #define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) 59 #define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) 60 #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) 61 #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) 62 #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) 63 #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) 64 #define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) 65 #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) 66 #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) 67 #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) 68 #define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) 69 #define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) 70 #define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) 71 72 /* Command2, BK1 bytes */ 73 #define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0) 74 #define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0) 75 #define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) 76 #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) 77 #define DSI_CMD2_BK1_VGLS_ONES BIT(6) 78 #define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0) 79 #define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) 80 #define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) 81 #define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) 82 #define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) 83 #define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) 84 #define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) 85 #define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) 86 #define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) 87 #define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) 88 #define DSI_CMD2_BK1_MIPISET1_ONES BIT(7) 89 #define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3) 90 91 #define CFIELD_PREP(_mask, _val) \ 92 (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) 93 94 enum op_bias { 95 OP_BIAS_OFF = 0, 96 OP_BIAS_MIN, 97 OP_BIAS_MIDDLE, 98 OP_BIAS_MAX 99 }; 100 101 struct st7701; 102 103 struct st7701_panel_desc { 104 const struct drm_display_mode *mode; 105 unsigned int lanes; 106 enum mipi_dsi_pixel_format format; 107 unsigned int panel_sleep_delay; 108 109 /* TFT matrix driver configuration, panel specific. */ 110 const u8 pv_gamma[16]; /* Positive voltage gamma control */ 111 const u8 nv_gamma[16]; /* Negative voltage gamma control */ 112 const u8 nlinv; /* Inversion selection */ 113 const u32 vop_uv; /* Vop in uV */ 114 const u32 vcom_uv; /* Vcom in uV */ 115 const u16 vgh_mv; /* Vgh in mV */ 116 const s16 vgl_mv; /* Vgl in mV */ 117 const u16 avdd_mv; /* Avdd in mV */ 118 const s16 avcl_mv; /* Avcl in mV */ 119 const enum op_bias gamma_op_bias; 120 const enum op_bias input_op_bias; 121 const enum op_bias output_op_bias; 122 const u16 t2d_ns; /* T2D in ns */ 123 const u16 t3d_ns; /* T3D in ns */ 124 const bool eot_en; 125 126 /* GIP sequence, fully custom and undocumented. */ 127 void (*gip_sequence)(struct st7701 *st7701); 128 }; 129 130 struct st7701 { 131 struct drm_panel panel; 132 struct mipi_dsi_device *dsi; 133 const struct st7701_panel_desc *desc; 134 135 struct regulator_bulk_data supplies[2]; 136 struct gpio_desc *reset; 137 unsigned int sleep_delay; 138 }; 139 140 static inline struct st7701 *panel_to_st7701(struct drm_panel *panel) 141 { 142 return container_of(panel, struct st7701, panel); 143 } 144 145 static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, 146 size_t len) 147 { 148 return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len); 149 } 150 151 #define ST7701_DSI(st7701, seq...) \ 152 { \ 153 const u8 d[] = { seq }; \ 154 st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \ 155 } 156 157 static u8 st7701_vgls_map(struct st7701 *st7701) 158 { 159 const struct st7701_panel_desc *desc = st7701->desc; 160 struct { 161 s32 vgl; 162 u8 val; 163 } map[16] = { 164 { -7060, 0x0 }, { -7470, 0x1 }, 165 { -7910, 0x2 }, { -8140, 0x3 }, 166 { -8650, 0x4 }, { -8920, 0x5 }, 167 { -9210, 0x6 }, { -9510, 0x7 }, 168 { -9830, 0x8 }, { -10170, 0x9 }, 169 { -10530, 0xa }, { -10910, 0xb }, 170 { -11310, 0xc }, { -11730, 0xd }, 171 { -12200, 0xe }, { -12690, 0xf } 172 }; 173 int i; 174 175 for (i = 0; i < ARRAY_SIZE(map); i++) 176 if (desc->vgl_mv == map[i].vgl) 177 return map[i].val; 178 179 return 0; 180 } 181 182 static void st7701_switch_cmd_bkx(struct st7701 *st7701, bool cmd2, u8 bkx) 183 { 184 u8 val; 185 186 if (cmd2) 187 val = DSI_CMD2 | FIELD_PREP(DSI_CMD2BK_MASK, bkx); 188 else 189 val = DSI_CMD1; 190 191 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val); 192 } 193 194 static void st7701_init_sequence(struct st7701 *st7701) 195 { 196 const struct st7701_panel_desc *desc = st7701->desc; 197 const struct drm_display_mode *mode = desc->mode; 198 const u8 linecount8 = mode->vdisplay / 8; 199 const u8 linecountrem2 = (mode->vdisplay % 8) / 2; 200 201 ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); 202 203 /* We need to wait 5ms before sending new commands */ 204 msleep(5); 205 206 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); 207 208 msleep(st7701->sleep_delay); 209 210 /* Command2, BK0 */ 211 st7701_switch_cmd_bkx(st7701, true, 0); 212 213 mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL, 214 desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); 215 mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, 216 desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); 217 /* 218 * Vertical line count configuration: 219 * Line[6:0]: select number of vertical lines of the TFT matrix in 220 * multiples of 8 lines 221 * LDE_EN: enable sub-8-line granularity line count 222 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected 223 * using Line[6:0] 224 * 225 * Total number of vertical lines: 226 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) 227 */ 228 ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, 229 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | 230 (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), 231 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); 232 ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, 233 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, 234 mode->vtotal - mode->vsync_end), 235 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, 236 mode->vsync_start - mode->vdisplay)); 237 /* 238 * Horizontal pixel count configuration: 239 * PCLK = 512 + (RTNI[4:0] * 16) 240 * The PCLK is number of pixel clock per line, which matches 241 * mode htotal. The minimum is 512 PCLK. 242 */ 243 ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, 244 DSI_CMD2_BK0_INVSEL_ONES_MASK | 245 FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), 246 FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, 247 (clamp((u32)mode->htotal, 512U, 1008U) - 512) / 16)); 248 249 /* Command2, BK1 */ 250 st7701_switch_cmd_bkx(st7701, true, 1); 251 252 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ 253 ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, 254 FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK, 255 DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500))); 256 257 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ 258 ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, 259 FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK, 260 DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500))); 261 262 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ 263 ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, 264 FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK, 265 DIV_ROUND_CLOSEST(clamp(desc->vgh_mv, 266 (u16)11500, 267 (u16)17000) - 11500, 268 500))); 269 270 ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL); 271 272 /* Vgl is non-linear */ 273 ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, 274 DSI_CMD2_BK1_VGLS_ONES | 275 FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); 276 277 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, 278 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK, 279 desc->gamma_op_bias) | 280 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK, 281 desc->input_op_bias) | 282 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK, 283 desc->output_op_bias)); 284 285 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ 286 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, 287 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, 288 DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | 289 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, 290 DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); 291 292 /* T2D = 0.2us * T2D[3:0] */ 293 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, 294 DSI_CMD2_BK1_SPD1_ONES_MASK | 295 FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK, 296 DIV_ROUND_CLOSEST(desc->t2d_ns, 200))); 297 298 /* T3D = 4us + (0.8us * T3D[3:0]) */ 299 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, 300 DSI_CMD2_BK1_SPD2_ONES_MASK | 301 FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK, 302 DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800))); 303 304 ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, 305 DSI_CMD2_BK1_MIPISET1_ONES | 306 (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); 307 } 308 309 static void ts8550b_gip_sequence(struct st7701 *st7701) 310 { 311 /** 312 * ST7701_SPEC_V1.2 is unable to provide enough information above this 313 * specific command sequence, so grab the same from vendor BSP driver. 314 */ 315 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); 316 ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, 317 0x00, 0x00, 0x44, 0x44); 318 ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, 319 0x00, 0x65, 0x00, 0x67, 0x00, 0x00); 320 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); 321 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); 322 ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, 323 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0); 324 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); 325 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); 326 ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, 327 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0); 328 ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); 329 ST7701_DSI(st7701, 0xEC, 0x00, 0x00); 330 ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, 331 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); 332 } 333 334 static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701) 335 { 336 ST7701_DSI(st7701, 0xEE, 0x42); 337 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); 338 339 ST7701_DSI(st7701, 0xE1, 340 0x04, 0xA0, 0x06, 0xA0, 341 0x05, 0xA0, 0x07, 0xA0, 342 0x00, 0x44, 0x44); 343 ST7701_DSI(st7701, 0xE2, 344 0x00, 0x00, 0x00, 0x00, 345 0x00, 0x00, 0x00, 0x00, 346 0x00, 0x00, 0x00, 0x00); 347 ST7701_DSI(st7701, 0xE3, 348 0x00, 0x00, 0x22, 0x22); 349 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); 350 ST7701_DSI(st7701, 0xE5, 351 0x0C, 0x90, 0xA0, 0xA0, 352 0x0E, 0x92, 0xA0, 0xA0, 353 0x08, 0x8C, 0xA0, 0xA0, 354 0x0A, 0x8E, 0xA0, 0xA0); 355 ST7701_DSI(st7701, 0xE6, 356 0x00, 0x00, 0x22, 0x22); 357 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); 358 ST7701_DSI(st7701, 0xE8, 359 0x0D, 0x91, 0xA0, 0xA0, 360 0x0F, 0x93, 0xA0, 0xA0, 361 0x09, 0x8D, 0xA0, 0xA0, 362 0x0B, 0x8F, 0xA0, 0xA0); 363 ST7701_DSI(st7701, 0xEB, 364 0x00, 0x00, 0xE4, 0xE4, 365 0x44, 0x00, 0x00); 366 ST7701_DSI(st7701, 0xED, 367 0xFF, 0xF5, 0x47, 0x6F, 368 0x0B, 0xA1, 0xAB, 0xFF, 369 0xFF, 0xBA, 0x1A, 0xB0, 370 0xF6, 0x74, 0x5F, 0xFF); 371 ST7701_DSI(st7701, 0xEF, 372 0x08, 0x08, 0x08, 0x40, 373 0x3F, 0x64); 374 375 st7701_switch_cmd_bkx(st7701, false, 0); 376 377 st7701_switch_cmd_bkx(st7701, true, 3); 378 ST7701_DSI(st7701, 0xE6, 0x7C); 379 ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); 380 381 st7701_switch_cmd_bkx(st7701, false, 0); 382 ST7701_DSI(st7701, 0x11); 383 msleep(120); 384 385 st7701_switch_cmd_bkx(st7701, true, 3); 386 ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); 387 msleep(10); 388 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 389 390 st7701_switch_cmd_bkx(st7701, false, 0); 391 ST7701_DSI(st7701, 0x11); 392 msleep(120); 393 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 394 395 st7701_switch_cmd_bkx(st7701, false, 0); 396 397 ST7701_DSI(st7701, 0x3A, 0x70); 398 } 399 400 static int st7701_prepare(struct drm_panel *panel) 401 { 402 struct st7701 *st7701 = panel_to_st7701(panel); 403 int ret; 404 405 gpiod_set_value(st7701->reset, 0); 406 407 ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies), 408 st7701->supplies); 409 if (ret < 0) 410 return ret; 411 msleep(20); 412 413 gpiod_set_value(st7701->reset, 1); 414 msleep(150); 415 416 st7701_init_sequence(st7701); 417 418 if (st7701->desc->gip_sequence) 419 st7701->desc->gip_sequence(st7701); 420 421 /* Disable Command2 */ 422 st7701_switch_cmd_bkx(st7701, false, 0); 423 424 return 0; 425 } 426 427 static int st7701_enable(struct drm_panel *panel) 428 { 429 struct st7701 *st7701 = panel_to_st7701(panel); 430 431 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); 432 433 return 0; 434 } 435 436 static int st7701_disable(struct drm_panel *panel) 437 { 438 struct st7701 *st7701 = panel_to_st7701(panel); 439 440 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); 441 442 return 0; 443 } 444 445 static int st7701_unprepare(struct drm_panel *panel) 446 { 447 struct st7701 *st7701 = panel_to_st7701(panel); 448 449 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); 450 451 msleep(st7701->sleep_delay); 452 453 gpiod_set_value(st7701->reset, 0); 454 455 /** 456 * During the Resetting period, the display will be blanked 457 * (The display is entering blanking sequence, which maximum 458 * time is 120 ms, when Reset Starts in Sleep Out –mode. The 459 * display remains the blank state in Sleep In –mode.) and 460 * then return to Default condition for Hardware Reset. 461 * 462 * So we need wait sleep_delay time to make sure reset completed. 463 */ 464 msleep(st7701->sleep_delay); 465 466 regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies); 467 468 return 0; 469 } 470 471 static int st7701_get_modes(struct drm_panel *panel, 472 struct drm_connector *connector) 473 { 474 struct st7701 *st7701 = panel_to_st7701(panel); 475 const struct drm_display_mode *desc_mode = st7701->desc->mode; 476 struct drm_display_mode *mode; 477 478 mode = drm_mode_duplicate(connector->dev, desc_mode); 479 if (!mode) { 480 dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n", 481 desc_mode->hdisplay, desc_mode->vdisplay, 482 drm_mode_vrefresh(desc_mode)); 483 return -ENOMEM; 484 } 485 486 drm_mode_set_name(mode); 487 drm_mode_probed_add(connector, mode); 488 489 connector->display_info.width_mm = desc_mode->width_mm; 490 connector->display_info.height_mm = desc_mode->height_mm; 491 492 return 1; 493 } 494 495 static const struct drm_panel_funcs st7701_funcs = { 496 .disable = st7701_disable, 497 .unprepare = st7701_unprepare, 498 .prepare = st7701_prepare, 499 .enable = st7701_enable, 500 .get_modes = st7701_get_modes, 501 }; 502 503 static const struct drm_display_mode ts8550b_mode = { 504 .clock = 27500, 505 506 .hdisplay = 480, 507 .hsync_start = 480 + 38, 508 .hsync_end = 480 + 38 + 12, 509 .htotal = 480 + 38 + 12 + 12, 510 511 .vdisplay = 854, 512 .vsync_start = 854 + 18, 513 .vsync_end = 854 + 18 + 8, 514 .vtotal = 854 + 18 + 8 + 4, 515 516 .width_mm = 69, 517 .height_mm = 139, 518 519 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 520 }; 521 522 static const struct st7701_panel_desc ts8550b_desc = { 523 .mode = &ts8550b_mode, 524 .lanes = 2, 525 .format = MIPI_DSI_FMT_RGB888, 526 .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ 527 528 .pv_gamma = { 529 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 530 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 531 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 532 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), 533 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 534 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), 535 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), 536 537 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 538 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 539 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), 540 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), 541 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 542 543 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 544 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), 545 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 546 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 547 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 548 549 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), 550 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 551 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), 552 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 553 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), 554 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 555 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 556 }, 557 .nv_gamma = { 558 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 559 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 560 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 561 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), 562 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | 563 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), 564 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), 565 566 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 567 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), 568 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), 569 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), 570 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 571 572 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 573 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), 574 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 575 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 576 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), 577 578 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 579 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 580 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), 581 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 582 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), 583 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 584 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 585 }, 586 .nlinv = 7, 587 .vop_uv = 4400000, 588 .vcom_uv = 337500, 589 .vgh_mv = 15000, 590 .vgl_mv = -9510, 591 .avdd_mv = 6600, 592 .avcl_mv = -4400, 593 .gamma_op_bias = OP_BIAS_MAX, 594 .input_op_bias = OP_BIAS_MIN, 595 .output_op_bias = OP_BIAS_MIN, 596 .t2d_ns = 1600, 597 .t3d_ns = 10400, 598 .eot_en = true, 599 .gip_sequence = ts8550b_gip_sequence, 600 }; 601 602 static const struct drm_display_mode dmt028vghmcmi_1a_mode = { 603 .clock = 22325, 604 605 .hdisplay = 480, 606 .hsync_start = 480 + 40, 607 .hsync_end = 480 + 40 + 4, 608 .htotal = 480 + 40 + 4 + 20, 609 610 .vdisplay = 640, 611 .vsync_start = 640 + 2, 612 .vsync_end = 640 + 2 + 40, 613 .vtotal = 640 + 2 + 40 + 16, 614 615 .width_mm = 56, 616 .height_mm = 78, 617 618 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 619 620 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 621 }; 622 623 static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = { 624 .mode = &dmt028vghmcmi_1a_mode, 625 .lanes = 2, 626 .format = MIPI_DSI_FMT_RGB888, 627 .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */ 628 629 .pv_gamma = { 630 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 631 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 632 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 633 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), 634 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 635 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), 636 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), 637 638 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 639 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 640 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 641 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), 642 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 643 644 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), 645 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), 646 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 647 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 648 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), 649 650 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 651 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 652 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), 653 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 654 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 655 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 656 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 657 }, 658 .nv_gamma = { 659 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 660 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 661 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 662 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), 663 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 664 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), 665 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), 666 667 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 668 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 669 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 670 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), 671 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 672 673 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 674 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), 675 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), 676 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 677 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 678 679 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), 680 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 681 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), 682 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 683 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 684 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 685 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 686 }, 687 .nlinv = 1, 688 .vop_uv = 4800000, 689 .vcom_uv = 1650000, 690 .vgh_mv = 15000, 691 .vgl_mv = -10170, 692 .avdd_mv = 6600, 693 .avcl_mv = -4400, 694 .gamma_op_bias = OP_BIAS_MIDDLE, 695 .input_op_bias = OP_BIAS_MIN, 696 .output_op_bias = OP_BIAS_MIN, 697 .t2d_ns = 1600, 698 .t3d_ns = 10400, 699 .eot_en = true, 700 .gip_sequence = dmt028vghmcmi_1a_gip_sequence, 701 }; 702 703 static int st7701_dsi_probe(struct mipi_dsi_device *dsi) 704 { 705 const struct st7701_panel_desc *desc; 706 struct st7701 *st7701; 707 int ret; 708 709 st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); 710 if (!st7701) 711 return -ENOMEM; 712 713 desc = of_device_get_match_data(&dsi->dev); 714 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 715 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 716 dsi->format = desc->format; 717 dsi->lanes = desc->lanes; 718 719 st7701->supplies[0].supply = "VCC"; 720 st7701->supplies[1].supply = "IOVCC"; 721 722 ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), 723 st7701->supplies); 724 if (ret < 0) 725 return ret; 726 727 st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); 728 if (IS_ERR(st7701->reset)) { 729 dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); 730 return PTR_ERR(st7701->reset); 731 } 732 733 drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs, 734 DRM_MODE_CONNECTOR_DSI); 735 736 /** 737 * Once sleep out has been issued, ST7701 IC required to wait 120ms 738 * before initiating new commands. 739 * 740 * On top of that some panels might need an extra delay to wait, so 741 * add panel specific delay for those cases. As now this panel specific 742 * delay information is referenced from those panel BSP driver, example 743 * ts8550b and there is no valid documentation for that. 744 */ 745 st7701->sleep_delay = 120 + desc->panel_sleep_delay; 746 747 ret = drm_panel_of_backlight(&st7701->panel); 748 if (ret) 749 return ret; 750 751 drm_panel_add(&st7701->panel); 752 753 mipi_dsi_set_drvdata(dsi, st7701); 754 st7701->dsi = dsi; 755 st7701->desc = desc; 756 757 ret = mipi_dsi_attach(dsi); 758 if (ret) 759 goto err_attach; 760 761 return 0; 762 763 err_attach: 764 drm_panel_remove(&st7701->panel); 765 return ret; 766 } 767 768 static void st7701_dsi_remove(struct mipi_dsi_device *dsi) 769 { 770 struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); 771 772 mipi_dsi_detach(dsi); 773 drm_panel_remove(&st7701->panel); 774 } 775 776 static const struct of_device_id st7701_of_match[] = { 777 { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, 778 { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, 779 { } 780 }; 781 MODULE_DEVICE_TABLE(of, st7701_of_match); 782 783 static struct mipi_dsi_driver st7701_dsi_driver = { 784 .probe = st7701_dsi_probe, 785 .remove = st7701_dsi_remove, 786 .driver = { 787 .name = "st7701", 788 .of_match_table = st7701_of_match, 789 }, 790 }; 791 module_mipi_dsi_driver(st7701_dsi_driver); 792 793 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 794 MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver"); 795 MODULE_LICENSE("GPL"); 796