1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019, Amarula Solutions. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 */ 6 7 #include <drm/drm_mipi_dsi.h> 8 #include <drm/drm_modes.h> 9 #include <drm/drm_panel.h> 10 11 #include <linux/bitfield.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <video/mipi_display.h> 19 20 /* Command2 BKx selection command */ 21 #define DSI_CMD2BKX_SEL 0xFF 22 23 /* Command2, BK0 commands */ 24 #define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */ 25 #define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */ 26 #define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */ 27 #define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */ 28 #define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */ 29 30 /* Command2, BK1 commands */ 31 #define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */ 32 #define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */ 33 #define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */ 34 #define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */ 35 #define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */ 36 #define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */ 37 #define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */ 38 #define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */ 39 #define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */ 40 #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */ 41 42 /* 43 * Command2 with BK function selection. 44 * 45 * BIT[4].....CN2 46 * BIT[1:0]...BKXSEL 47 * 1:00 = CMD2BK0, Command2 BK0 48 * 1:01 = CMD2BK1, Command2 BK1 49 * 1:11 = CMD2BK3, Command2 BK3 50 * 0:00 = Command2 disable 51 */ 52 #define DSI_CMD2BK0_SEL 0x10 53 #define DSI_CMD2BK1_SEL 0x11 54 #define DSI_CMD2BK3_SEL 0x13 55 #define DSI_CMD2BKX_SEL_NONE 0x00 56 57 /* Command2, BK0 bytes */ 58 #define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) 59 #define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) 60 #define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) 61 #define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) 62 #define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) 63 #define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) 64 #define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) 65 #define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) 66 #define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) 67 #define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) 68 #define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) 69 #define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) 70 #define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) 71 #define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) 72 #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) 73 #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) 74 #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) 75 #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) 76 #define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) 77 #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) 78 #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) 79 #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) 80 #define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) 81 #define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) 82 #define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) 83 84 /* Command2, BK1 bytes */ 85 #define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0) 86 #define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0) 87 #define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) 88 #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) 89 #define DSI_CMD2_BK1_VGLS_ONES BIT(6) 90 #define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0) 91 #define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) 92 #define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) 93 #define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) 94 #define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) 95 #define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) 96 #define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) 97 #define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) 98 #define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) 99 #define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) 100 #define DSI_CMD2_BK1_MIPISET1_ONES BIT(7) 101 #define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3) 102 103 #define CFIELD_PREP(_mask, _val) \ 104 (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) 105 106 enum op_bias { 107 OP_BIAS_OFF = 0, 108 OP_BIAS_MIN, 109 OP_BIAS_MIDDLE, 110 OP_BIAS_MAX 111 }; 112 113 struct st7701; 114 115 struct st7701_panel_desc { 116 const struct drm_display_mode *mode; 117 unsigned int lanes; 118 enum mipi_dsi_pixel_format format; 119 unsigned int panel_sleep_delay; 120 121 /* TFT matrix driver configuration, panel specific. */ 122 const u8 pv_gamma[16]; /* Positive voltage gamma control */ 123 const u8 nv_gamma[16]; /* Negative voltage gamma control */ 124 const u8 nlinv; /* Inversion selection */ 125 const u32 vop_uv; /* Vop in uV */ 126 const u32 vcom_uv; /* Vcom in uV */ 127 const u16 vgh_mv; /* Vgh in mV */ 128 const s16 vgl_mv; /* Vgl in mV */ 129 const u16 avdd_mv; /* Avdd in mV */ 130 const s16 avcl_mv; /* Avcl in mV */ 131 const enum op_bias gamma_op_bias; 132 const enum op_bias input_op_bias; 133 const enum op_bias output_op_bias; 134 const u16 t2d_ns; /* T2D in ns */ 135 const u16 t3d_ns; /* T3D in ns */ 136 const bool eot_en; 137 138 /* GIP sequence, fully custom and undocumented. */ 139 void (*gip_sequence)(struct st7701 *st7701); 140 }; 141 142 struct st7701 { 143 struct drm_panel panel; 144 struct mipi_dsi_device *dsi; 145 const struct st7701_panel_desc *desc; 146 147 struct regulator_bulk_data supplies[2]; 148 struct gpio_desc *reset; 149 unsigned int sleep_delay; 150 }; 151 152 static inline struct st7701 *panel_to_st7701(struct drm_panel *panel) 153 { 154 return container_of(panel, struct st7701, panel); 155 } 156 157 static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, 158 size_t len) 159 { 160 return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len); 161 } 162 163 #define ST7701_DSI(st7701, seq...) \ 164 { \ 165 const u8 d[] = { seq }; \ 166 st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \ 167 } 168 169 static u8 st7701_vgls_map(struct st7701 *st7701) 170 { 171 const struct st7701_panel_desc *desc = st7701->desc; 172 struct { 173 s32 vgl; 174 u8 val; 175 } map[16] = { 176 { -7060, 0x0 }, { -7470, 0x1 }, 177 { -7910, 0x2 }, { -8140, 0x3 }, 178 { -8650, 0x4 }, { -8920, 0x5 }, 179 { -9210, 0x6 }, { -9510, 0x7 }, 180 { -9830, 0x8 }, { -10170, 0x9 }, 181 { -10530, 0xa }, { -10910, 0xb }, 182 { -11310, 0xc }, { -11730, 0xd }, 183 { -12200, 0xe }, { -12690, 0xf } 184 }; 185 int i; 186 187 for (i = 0; i < ARRAY_SIZE(map); i++) 188 if (desc->vgl_mv == map[i].vgl) 189 return map[i].val; 190 191 return 0; 192 } 193 194 static void st7701_init_sequence(struct st7701 *st7701) 195 { 196 const struct st7701_panel_desc *desc = st7701->desc; 197 const struct drm_display_mode *mode = desc->mode; 198 const u8 linecount8 = mode->vdisplay / 8; 199 const u8 linecountrem2 = (mode->vdisplay % 8) / 2; 200 201 ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); 202 203 /* We need to wait 5ms before sending new commands */ 204 msleep(5); 205 206 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); 207 208 msleep(st7701->sleep_delay); 209 210 /* Command2, BK0 */ 211 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 212 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL); 213 mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL, 214 desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); 215 mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, 216 desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); 217 /* 218 * Vertical line count configuration: 219 * Line[6:0]: select number of vertical lines of the TFT matrix in 220 * multiples of 8 lines 221 * LDE_EN: enable sub-8-line granularity line count 222 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected 223 * using Line[6:0] 224 * 225 * Total number of vertical lines: 226 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) 227 */ 228 ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, 229 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | 230 (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), 231 FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); 232 ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, 233 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, 234 mode->vtotal - mode->vsync_end), 235 FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, 236 mode->vsync_start - mode->vdisplay)); 237 /* 238 * Horizontal pixel count configuration: 239 * PCLK = 512 + (RTNI[4:0] * 16) 240 * The PCLK is number of pixel clock per line, which matches 241 * mode htotal. The minimum is 512 PCLK. 242 */ 243 ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, 244 DSI_CMD2_BK0_INVSEL_ONES_MASK | 245 FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), 246 FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, 247 DIV_ROUND_UP(mode->htotal, 16))); 248 249 /* Command2, BK1 */ 250 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 251 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL); 252 253 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ 254 ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, 255 FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK, 256 DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500))); 257 258 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ 259 ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, 260 FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK, 261 DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500))); 262 263 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ 264 ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, 265 FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK, 266 DIV_ROUND_CLOSEST(clamp(desc->vgh_mv, 267 (u16)11500, 268 (u16)17000) - 11500, 269 500))); 270 271 ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL); 272 273 /* Vgl is non-linear */ 274 ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, 275 DSI_CMD2_BK1_VGLS_ONES | 276 FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); 277 278 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, 279 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK, 280 desc->gamma_op_bias) | 281 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK, 282 desc->input_op_bias) | 283 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK, 284 desc->output_op_bias)); 285 286 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ 287 ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, 288 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, 289 DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | 290 FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, 291 DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200))); 292 293 /* T2D = 0.2us * T2D[3:0] */ 294 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, 295 DSI_CMD2_BK1_SPD1_ONES_MASK | 296 FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK, 297 DIV_ROUND_CLOSEST(desc->t2d_ns, 200))); 298 299 /* T3D = 4us + (0.8us * T3D[3:0]) */ 300 ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, 301 DSI_CMD2_BK1_SPD2_ONES_MASK | 302 FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK, 303 DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800))); 304 305 ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, 306 DSI_CMD2_BK1_MIPISET1_ONES | 307 (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); 308 } 309 310 static void ts8550b_gip_sequence(struct st7701 *st7701) 311 { 312 /** 313 * ST7701_SPEC_V1.2 is unable to provide enough information above this 314 * specific command sequence, so grab the same from vendor BSP driver. 315 */ 316 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); 317 ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, 318 0x00, 0x00, 0x44, 0x44); 319 ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, 320 0x00, 0x65, 0x00, 0x67, 0x00, 0x00); 321 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); 322 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); 323 ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, 324 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0); 325 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); 326 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); 327 ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, 328 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0); 329 ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); 330 ST7701_DSI(st7701, 0xEC, 0x00, 0x00); 331 ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, 332 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); 333 } 334 335 static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701) 336 { 337 ST7701_DSI(st7701, 0xEE, 0x42); 338 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); 339 340 ST7701_DSI(st7701, 0xE1, 341 0x04, 0xA0, 0x06, 0xA0, 342 0x05, 0xA0, 0x07, 0xA0, 343 0x00, 0x44, 0x44); 344 ST7701_DSI(st7701, 0xE2, 345 0x00, 0x00, 0x00, 0x00, 346 0x00, 0x00, 0x00, 0x00, 347 0x00, 0x00, 0x00, 0x00); 348 ST7701_DSI(st7701, 0xE3, 349 0x00, 0x00, 0x22, 0x22); 350 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); 351 ST7701_DSI(st7701, 0xE5, 352 0x0C, 0x90, 0xA0, 0xA0, 353 0x0E, 0x92, 0xA0, 0xA0, 354 0x08, 0x8C, 0xA0, 0xA0, 355 0x0A, 0x8E, 0xA0, 0xA0); 356 ST7701_DSI(st7701, 0xE6, 357 0x00, 0x00, 0x22, 0x22); 358 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); 359 ST7701_DSI(st7701, 0xE8, 360 0x0D, 0x91, 0xA0, 0xA0, 361 0x0F, 0x93, 0xA0, 0xA0, 362 0x09, 0x8D, 0xA0, 0xA0, 363 0x0B, 0x8F, 0xA0, 0xA0); 364 ST7701_DSI(st7701, 0xEB, 365 0x00, 0x00, 0xE4, 0xE4, 366 0x44, 0x00, 0x00); 367 ST7701_DSI(st7701, 0xED, 368 0xFF, 0xF5, 0x47, 0x6F, 369 0x0B, 0xA1, 0xAB, 0xFF, 370 0xFF, 0xBA, 0x1A, 0xB0, 371 0xF6, 0x74, 0x5F, 0xFF); 372 ST7701_DSI(st7701, 0xEF, 373 0x08, 0x08, 0x08, 0x40, 374 0x3F, 0x64); 375 376 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 377 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 378 379 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 380 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); 381 ST7701_DSI(st7701, 0xE6, 0x7C); 382 ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); 383 384 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 385 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 386 ST7701_DSI(st7701, 0x11); 387 msleep(120); 388 389 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 390 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); 391 ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); 392 msleep(10); 393 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 394 395 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 396 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 397 ST7701_DSI(st7701, 0x11); 398 msleep(120); 399 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); 400 401 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 402 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 403 404 ST7701_DSI(st7701, 0x3A, 0x70); 405 } 406 407 static int st7701_prepare(struct drm_panel *panel) 408 { 409 struct st7701 *st7701 = panel_to_st7701(panel); 410 int ret; 411 412 gpiod_set_value(st7701->reset, 0); 413 414 ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies), 415 st7701->supplies); 416 if (ret < 0) 417 return ret; 418 msleep(20); 419 420 gpiod_set_value(st7701->reset, 1); 421 msleep(150); 422 423 st7701_init_sequence(st7701); 424 425 if (st7701->desc->gip_sequence) 426 st7701->desc->gip_sequence(st7701); 427 428 /* Disable Command2 */ 429 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 430 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); 431 432 return 0; 433 } 434 435 static int st7701_enable(struct drm_panel *panel) 436 { 437 struct st7701 *st7701 = panel_to_st7701(panel); 438 439 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); 440 441 return 0; 442 } 443 444 static int st7701_disable(struct drm_panel *panel) 445 { 446 struct st7701 *st7701 = panel_to_st7701(panel); 447 448 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); 449 450 return 0; 451 } 452 453 static int st7701_unprepare(struct drm_panel *panel) 454 { 455 struct st7701 *st7701 = panel_to_st7701(panel); 456 457 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); 458 459 msleep(st7701->sleep_delay); 460 461 gpiod_set_value(st7701->reset, 0); 462 463 /** 464 * During the Resetting period, the display will be blanked 465 * (The display is entering blanking sequence, which maximum 466 * time is 120 ms, when Reset Starts in Sleep Out –mode. The 467 * display remains the blank state in Sleep In –mode.) and 468 * then return to Default condition for Hardware Reset. 469 * 470 * So we need wait sleep_delay time to make sure reset completed. 471 */ 472 msleep(st7701->sleep_delay); 473 474 regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies); 475 476 return 0; 477 } 478 479 static int st7701_get_modes(struct drm_panel *panel, 480 struct drm_connector *connector) 481 { 482 struct st7701 *st7701 = panel_to_st7701(panel); 483 const struct drm_display_mode *desc_mode = st7701->desc->mode; 484 struct drm_display_mode *mode; 485 486 mode = drm_mode_duplicate(connector->dev, desc_mode); 487 if (!mode) { 488 dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n", 489 desc_mode->hdisplay, desc_mode->vdisplay, 490 drm_mode_vrefresh(desc_mode)); 491 return -ENOMEM; 492 } 493 494 drm_mode_set_name(mode); 495 drm_mode_probed_add(connector, mode); 496 497 connector->display_info.width_mm = desc_mode->width_mm; 498 connector->display_info.height_mm = desc_mode->height_mm; 499 500 return 1; 501 } 502 503 static const struct drm_panel_funcs st7701_funcs = { 504 .disable = st7701_disable, 505 .unprepare = st7701_unprepare, 506 .prepare = st7701_prepare, 507 .enable = st7701_enable, 508 .get_modes = st7701_get_modes, 509 }; 510 511 static const struct drm_display_mode ts8550b_mode = { 512 .clock = 27500, 513 514 .hdisplay = 480, 515 .hsync_start = 480 + 38, 516 .hsync_end = 480 + 38 + 12, 517 .htotal = 480 + 38 + 12 + 12, 518 519 .vdisplay = 854, 520 .vsync_start = 854 + 18, 521 .vsync_end = 854 + 18 + 8, 522 .vtotal = 854 + 18 + 8 + 4, 523 524 .width_mm = 69, 525 .height_mm = 139, 526 527 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 528 }; 529 530 static const struct st7701_panel_desc ts8550b_desc = { 531 .mode = &ts8550b_mode, 532 .lanes = 2, 533 .format = MIPI_DSI_FMT_RGB888, 534 .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ 535 536 .pv_gamma = { 537 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 538 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 539 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 540 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), 541 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 542 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), 543 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), 544 545 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 546 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 547 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), 548 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), 549 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 550 551 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 552 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), 553 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 554 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 555 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 556 557 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), 558 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 559 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), 560 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 561 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), 562 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 563 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 564 }, 565 .nv_gamma = { 566 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 567 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 568 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 569 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), 570 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | 571 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), 572 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), 573 574 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 575 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), 576 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), 577 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), 578 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 579 580 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 581 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), 582 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 583 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 584 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), 585 586 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 587 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 588 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), 589 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 590 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), 591 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 592 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 593 }, 594 .nlinv = 7, 595 .vop_uv = 4400000, 596 .vcom_uv = 337500, 597 .vgh_mv = 15000, 598 .vgl_mv = -9510, 599 .avdd_mv = 6600, 600 .avcl_mv = -4400, 601 .gamma_op_bias = OP_BIAS_MAX, 602 .input_op_bias = OP_BIAS_MIN, 603 .output_op_bias = OP_BIAS_MIN, 604 .t2d_ns = 1600, 605 .t3d_ns = 10400, 606 .eot_en = true, 607 .gip_sequence = ts8550b_gip_sequence, 608 }; 609 610 static const struct drm_display_mode dmt028vghmcmi_1a_mode = { 611 .clock = 22325, 612 613 .hdisplay = 480, 614 .hsync_start = 480 + 40, 615 .hsync_end = 480 + 40 + 4, 616 .htotal = 480 + 40 + 4 + 20, 617 618 .vdisplay = 640, 619 .vsync_start = 640 + 2, 620 .vsync_end = 640 + 2 + 40, 621 .vtotal = 640 + 2 + 40 + 16, 622 623 .width_mm = 56, 624 .height_mm = 78, 625 626 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 627 628 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 629 }; 630 631 static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = { 632 .mode = &dmt028vghmcmi_1a_mode, 633 .lanes = 2, 634 .format = MIPI_DSI_FMT_RGB888, 635 .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */ 636 637 .pv_gamma = { 638 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 639 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 640 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 641 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), 642 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 643 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), 644 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), 645 646 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 647 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 648 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 649 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), 650 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 651 652 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), 653 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), 654 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 655 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 656 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), 657 658 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 659 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 660 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), 661 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 662 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 663 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 664 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 665 }, 666 .nv_gamma = { 667 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 668 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 669 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 670 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), 671 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 672 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), 673 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), 674 675 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 676 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 677 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 678 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), 679 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 680 681 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 682 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), 683 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), 684 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 685 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 686 687 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), 688 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 689 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), 690 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 691 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 692 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 693 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 694 }, 695 .nlinv = 1, 696 .vop_uv = 4800000, 697 .vcom_uv = 1650000, 698 .vgh_mv = 15000, 699 .vgl_mv = -10170, 700 .avdd_mv = 6600, 701 .avcl_mv = -4400, 702 .gamma_op_bias = OP_BIAS_MIDDLE, 703 .input_op_bias = OP_BIAS_MIN, 704 .output_op_bias = OP_BIAS_MIN, 705 .t2d_ns = 1600, 706 .t3d_ns = 10400, 707 .eot_en = true, 708 .gip_sequence = dmt028vghmcmi_1a_gip_sequence, 709 }; 710 711 static int st7701_dsi_probe(struct mipi_dsi_device *dsi) 712 { 713 const struct st7701_panel_desc *desc; 714 struct st7701 *st7701; 715 int ret; 716 717 st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); 718 if (!st7701) 719 return -ENOMEM; 720 721 desc = of_device_get_match_data(&dsi->dev); 722 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 723 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 724 dsi->format = desc->format; 725 dsi->lanes = desc->lanes; 726 727 st7701->supplies[0].supply = "VCC"; 728 st7701->supplies[1].supply = "IOVCC"; 729 730 ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), 731 st7701->supplies); 732 if (ret < 0) 733 return ret; 734 735 st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); 736 if (IS_ERR(st7701->reset)) { 737 dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); 738 return PTR_ERR(st7701->reset); 739 } 740 741 drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs, 742 DRM_MODE_CONNECTOR_DSI); 743 744 /** 745 * Once sleep out has been issued, ST7701 IC required to wait 120ms 746 * before initiating new commands. 747 * 748 * On top of that some panels might need an extra delay to wait, so 749 * add panel specific delay for those cases. As now this panel specific 750 * delay information is referenced from those panel BSP driver, example 751 * ts8550b and there is no valid documentation for that. 752 */ 753 st7701->sleep_delay = 120 + desc->panel_sleep_delay; 754 755 ret = drm_panel_of_backlight(&st7701->panel); 756 if (ret) 757 return ret; 758 759 drm_panel_add(&st7701->panel); 760 761 mipi_dsi_set_drvdata(dsi, st7701); 762 st7701->dsi = dsi; 763 st7701->desc = desc; 764 765 return mipi_dsi_attach(dsi); 766 } 767 768 static void st7701_dsi_remove(struct mipi_dsi_device *dsi) 769 { 770 struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); 771 772 mipi_dsi_detach(dsi); 773 drm_panel_remove(&st7701->panel); 774 } 775 776 static const struct of_device_id st7701_of_match[] = { 777 { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, 778 { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, 779 { } 780 }; 781 MODULE_DEVICE_TABLE(of, st7701_of_match); 782 783 static struct mipi_dsi_driver st7701_dsi_driver = { 784 .probe = st7701_dsi_probe, 785 .remove = st7701_dsi_remove, 786 .driver = { 787 .name = "st7701", 788 .of_match_table = st7701_of_match, 789 }, 790 }; 791 module_mipi_dsi_driver(st7701_dsi_driver); 792 793 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 794 MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver"); 795 MODULE_LICENSE("GPL"); 796