1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2019, Amarula Solutions.
4  * Author: Jagan Teki <jagan@amarulasolutions.com>
5  */
6 
7 #include <drm/drm_mipi_dsi.h>
8 #include <drm/drm_modes.h>
9 #include <drm/drm_panel.h>
10 
11 #include <linux/bitfield.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/regulator/consumer.h>
17 
18 #include <video/mipi_display.h>
19 
20 /* Command2 BKx selection command */
21 #define DSI_CMD2BKX_SEL			0xFF
22 #define DSI_CMD1			0
23 #define DSI_CMD2			BIT(4)
24 #define DSI_CMD2BK_MASK			GENMASK(3, 0)
25 
26 /* Command2, BK0 commands */
27 #define DSI_CMD2_BK0_PVGAMCTRL		0xB0 /* Positive Voltage Gamma Control */
28 #define DSI_CMD2_BK0_NVGAMCTRL		0xB1 /* Negative Voltage Gamma Control */
29 #define DSI_CMD2_BK0_LNESET		0xC0 /* Display Line setting */
30 #define DSI_CMD2_BK0_PORCTRL		0xC1 /* Porch control */
31 #define DSI_CMD2_BK0_INVSEL		0xC2 /* Inversion selection, Frame Rate Control */
32 
33 /* Command2, BK1 commands */
34 #define DSI_CMD2_BK1_VRHS		0xB0 /* Vop amplitude setting */
35 #define DSI_CMD2_BK1_VCOM		0xB1 /* VCOM amplitude setting */
36 #define DSI_CMD2_BK1_VGHSS		0xB2 /* VGH Voltage setting */
37 #define DSI_CMD2_BK1_TESTCMD		0xB3 /* TEST Command Setting */
38 #define DSI_CMD2_BK1_VGLS		0xB5 /* VGL Voltage setting */
39 #define DSI_CMD2_BK1_PWCTLR1		0xB7 /* Power Control 1 */
40 #define DSI_CMD2_BK1_PWCTLR2		0xB8 /* Power Control 2 */
41 #define DSI_CMD2_BK1_SPD1		0xC1 /* Source pre_drive timing set1 */
42 #define DSI_CMD2_BK1_SPD2		0xC2 /* Source EQ2 Setting */
43 #define DSI_CMD2_BK1_MIPISET1		0xD0 /* MIPI Setting 1 */
44 
45 /* Command2, BK0 bytes */
46 #define DSI_CMD2_BK0_GAMCTRL_AJ_MASK	GENMASK(7, 6)
47 #define DSI_CMD2_BK0_GAMCTRL_VC0_MASK	GENMASK(3, 0)
48 #define DSI_CMD2_BK0_GAMCTRL_VC4_MASK	GENMASK(5, 0)
49 #define DSI_CMD2_BK0_GAMCTRL_VC8_MASK	GENMASK(5, 0)
50 #define DSI_CMD2_BK0_GAMCTRL_VC16_MASK	GENMASK(4, 0)
51 #define DSI_CMD2_BK0_GAMCTRL_VC24_MASK	GENMASK(4, 0)
52 #define DSI_CMD2_BK0_GAMCTRL_VC52_MASK	GENMASK(3, 0)
53 #define DSI_CMD2_BK0_GAMCTRL_VC80_MASK	GENMASK(5, 0)
54 #define DSI_CMD2_BK0_GAMCTRL_VC108_MASK	GENMASK(3, 0)
55 #define DSI_CMD2_BK0_GAMCTRL_VC147_MASK	GENMASK(3, 0)
56 #define DSI_CMD2_BK0_GAMCTRL_VC175_MASK	GENMASK(5, 0)
57 #define DSI_CMD2_BK0_GAMCTRL_VC203_MASK	GENMASK(3, 0)
58 #define DSI_CMD2_BK0_GAMCTRL_VC231_MASK	GENMASK(4, 0)
59 #define DSI_CMD2_BK0_GAMCTRL_VC239_MASK	GENMASK(4, 0)
60 #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK	GENMASK(5, 0)
61 #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK	GENMASK(5, 0)
62 #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK	GENMASK(4, 0)
63 #define DSI_CMD2_BK0_LNESET_LINE_MASK	GENMASK(6, 0)
64 #define DSI_CMD2_BK0_LNESET_LDE_EN	BIT(7)
65 #define DSI_CMD2_BK0_LNESET_LINEDELTA	GENMASK(1, 0)
66 #define DSI_CMD2_BK0_PORCTRL_VBP_MASK	GENMASK(7, 0)
67 #define DSI_CMD2_BK0_PORCTRL_VFP_MASK	GENMASK(7, 0)
68 #define DSI_CMD2_BK0_INVSEL_ONES_MASK	GENMASK(5, 4)
69 #define DSI_CMD2_BK0_INVSEL_NLINV_MASK	GENMASK(2, 0)
70 #define DSI_CMD2_BK0_INVSEL_RTNI_MASK	GENMASK(4, 0)
71 
72 /* Command2, BK1 bytes */
73 #define DSI_CMD2_BK1_VRHA_MASK		GENMASK(7, 0)
74 #define DSI_CMD2_BK1_VCOM_MASK		GENMASK(7, 0)
75 #define DSI_CMD2_BK1_VGHSS_MASK		GENMASK(3, 0)
76 #define DSI_CMD2_BK1_TESTCMD_VAL	BIT(7)
77 #define DSI_CMD2_BK1_VGLS_ONES		BIT(6)
78 #define DSI_CMD2_BK1_VGLS_MASK		GENMASK(3, 0)
79 #define DSI_CMD2_BK1_PWRCTRL1_AP_MASK	GENMASK(7, 6)
80 #define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK	GENMASK(3, 2)
81 #define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK	GENMASK(1, 0)
82 #define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK	GENMASK(5, 4)
83 #define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK	GENMASK(1, 0)
84 #define DSI_CMD2_BK1_SPD1_ONES_MASK	GENMASK(6, 4)
85 #define DSI_CMD2_BK1_SPD1_T2D_MASK	GENMASK(3, 0)
86 #define DSI_CMD2_BK1_SPD2_ONES_MASK	GENMASK(6, 4)
87 #define DSI_CMD2_BK1_SPD2_T3D_MASK	GENMASK(3, 0)
88 #define DSI_CMD2_BK1_MIPISET1_ONES	BIT(7)
89 #define DSI_CMD2_BK1_MIPISET1_EOT_EN	BIT(3)
90 
91 #define CFIELD_PREP(_mask, _val)					\
92 	(((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
93 
94 enum op_bias {
95 	OP_BIAS_OFF = 0,
96 	OP_BIAS_MIN,
97 	OP_BIAS_MIDDLE,
98 	OP_BIAS_MAX
99 };
100 
101 struct st7701;
102 
103 struct st7701_panel_desc {
104 	const struct drm_display_mode *mode;
105 	unsigned int lanes;
106 	enum mipi_dsi_pixel_format format;
107 	unsigned int panel_sleep_delay;
108 
109 	/* TFT matrix driver configuration, panel specific. */
110 	const u8	pv_gamma[16];	/* Positive voltage gamma control */
111 	const u8	nv_gamma[16];	/* Negative voltage gamma control */
112 	const u8	nlinv;		/* Inversion selection */
113 	const u32	vop_uv;		/* Vop in uV */
114 	const u32	vcom_uv;	/* Vcom in uV */
115 	const u16	vgh_mv;		/* Vgh in mV */
116 	const s16	vgl_mv;		/* Vgl in mV */
117 	const u16	avdd_mv;	/* Avdd in mV */
118 	const s16	avcl_mv;	/* Avcl in mV */
119 	const enum op_bias	gamma_op_bias;
120 	const enum op_bias	input_op_bias;
121 	const enum op_bias	output_op_bias;
122 	const u16	t2d_ns;		/* T2D in ns */
123 	const u16	t3d_ns;		/* T3D in ns */
124 	const bool	eot_en;
125 
126 	/* GIP sequence, fully custom and undocumented. */
127 	void		(*gip_sequence)(struct st7701 *st7701);
128 };
129 
130 struct st7701 {
131 	struct drm_panel panel;
132 	struct mipi_dsi_device *dsi;
133 	const struct st7701_panel_desc *desc;
134 
135 	struct regulator_bulk_data supplies[2];
136 	struct gpio_desc *reset;
137 	unsigned int sleep_delay;
138 	enum drm_panel_orientation orientation;
139 };
140 
141 static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
142 {
143 	return container_of(panel, struct st7701, panel);
144 }
145 
146 static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
147 				   size_t len)
148 {
149 	return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
150 }
151 
152 #define ST7701_DSI(st7701, seq...)				\
153 	{							\
154 		const u8 d[] = { seq };				\
155 		st7701_dsi_write(st7701, d, ARRAY_SIZE(d));	\
156 	}
157 
158 static u8 st7701_vgls_map(struct st7701 *st7701)
159 {
160 	const struct st7701_panel_desc *desc = st7701->desc;
161 	struct {
162 		s32	vgl;
163 		u8	val;
164 	} map[16] = {
165 		{ -7060, 0x0 }, { -7470, 0x1 },
166 		{ -7910, 0x2 }, { -8140, 0x3 },
167 		{ -8650, 0x4 }, { -8920, 0x5 },
168 		{ -9210, 0x6 }, { -9510, 0x7 },
169 		{ -9830, 0x8 }, { -10170, 0x9 },
170 		{ -10530, 0xa }, { -10910, 0xb },
171 		{ -11310, 0xc }, { -11730, 0xd },
172 		{ -12200, 0xe }, { -12690, 0xf }
173 	};
174 	int i;
175 
176 	for (i = 0; i < ARRAY_SIZE(map); i++)
177 		if (desc->vgl_mv == map[i].vgl)
178 			return map[i].val;
179 
180 	return 0;
181 }
182 
183 static void st7701_switch_cmd_bkx(struct st7701 *st7701, bool cmd2, u8 bkx)
184 {
185 	u8 val;
186 
187 	if (cmd2)
188 		val = DSI_CMD2 | FIELD_PREP(DSI_CMD2BK_MASK, bkx);
189 	else
190 		val = DSI_CMD1;
191 
192 	ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);
193 }
194 
195 static void st7701_init_sequence(struct st7701 *st7701)
196 {
197 	const struct st7701_panel_desc *desc = st7701->desc;
198 	const struct drm_display_mode *mode = desc->mode;
199 	const u8 linecount8 = mode->vdisplay / 8;
200 	const u8 linecountrem2 = (mode->vdisplay % 8) / 2;
201 
202 	ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
203 
204 	/* We need to wait 5ms before sending new commands */
205 	msleep(5);
206 
207 	ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
208 
209 	msleep(st7701->sleep_delay);
210 
211 	/* Command2, BK0 */
212 	st7701_switch_cmd_bkx(st7701, true, 0);
213 
214 	mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL,
215 			   desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma));
216 	mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL,
217 			   desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma));
218 	/*
219 	 * Vertical line count configuration:
220 	 * Line[6:0]: select number of vertical lines of the TFT matrix in
221 	 *            multiples of 8 lines
222 	 * LDE_EN: enable sub-8-line granularity line count
223 	 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected
224 	 *                  using Line[6:0]
225 	 *
226 	 * Total number of vertical lines:
227 	 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)
228 	 */
229 	ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
230 		   FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) |
231 		   (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0),
232 		   FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2));
233 	ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
234 		   FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK,
235 			      mode->vtotal - mode->vsync_end),
236 		   FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK,
237 			      mode->vsync_start - mode->vdisplay));
238 	/*
239 	 * Horizontal pixel count configuration:
240 	 * PCLK = 512 + (RTNI[4:0] * 16)
241 	 * The PCLK is number of pixel clock per line, which matches
242 	 * mode htotal. The minimum is 512 PCLK.
243 	 */
244 	ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
245 		   DSI_CMD2_BK0_INVSEL_ONES_MASK |
246 		   FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv),
247 		   FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK,
248 			      (clamp((u32)mode->htotal, 512U, 1008U) - 512) / 16));
249 
250 	/* Command2, BK1 */
251 	st7701_switch_cmd_bkx(st7701, true, 1);
252 
253 	/* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */
254 	ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS,
255 		   FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK,
256 			      DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500)));
257 
258 	/* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */
259 	ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM,
260 		   FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK,
261 			      DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500)));
262 
263 	/* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */
264 	ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS,
265 		   FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK,
266 			      DIV_ROUND_CLOSEST(clamp(desc->vgh_mv,
267 						      (u16)11500,
268 						      (u16)17000) - 11500,
269 						500)));
270 
271 	ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
272 
273 	/* Vgl is non-linear */
274 	ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS,
275 		   DSI_CMD2_BK1_VGLS_ONES |
276 		   FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701)));
277 
278 	ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1,
279 		   FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK,
280 			      desc->gamma_op_bias) |
281 		   FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK,
282 			      desc->input_op_bias) |
283 		   FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK,
284 			      desc->output_op_bias));
285 
286 	/* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */
287 	ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2,
288 		   FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK,
289 			      DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) |
290 		   FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK,
291 			      DIV_ROUND_CLOSEST(-4400 + desc->avcl_mv, 200)));
292 
293 	/* T2D = 0.2us * T2D[3:0] */
294 	ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1,
295 		   DSI_CMD2_BK1_SPD1_ONES_MASK |
296 		   FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK,
297 			      DIV_ROUND_CLOSEST(desc->t2d_ns, 200)));
298 
299 	/* T3D = 4us + (0.8us * T3D[3:0]) */
300 	ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2,
301 		   DSI_CMD2_BK1_SPD2_ONES_MASK |
302 		   FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK,
303 			      DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800)));
304 
305 	ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1,
306 		   DSI_CMD2_BK1_MIPISET1_ONES |
307 		   (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0));
308 }
309 
310 static void ts8550b_gip_sequence(struct st7701 *st7701)
311 {
312 	/**
313 	 * ST7701_SPEC_V1.2 is unable to provide enough information above this
314 	 * specific command sequence, so grab the same from vendor BSP driver.
315 	 */
316 	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
317 	ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
318 		   0x00, 0x00, 0x44, 0x44);
319 	ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
320 		   0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
321 	ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
322 	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
323 	ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
324 		   0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
325 	ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
326 	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
327 	ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
328 		   0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
329 	ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
330 	ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
331 	ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
332 		   0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
333 }
334 
335 static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701)
336 {
337 	ST7701_DSI(st7701, 0xEE, 0x42);
338 	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
339 
340 	ST7701_DSI(st7701, 0xE1,
341 		   0x04, 0xA0, 0x06, 0xA0,
342 			   0x05, 0xA0, 0x07, 0xA0,
343 			   0x00, 0x44, 0x44);
344 	ST7701_DSI(st7701, 0xE2,
345 		   0x00, 0x00, 0x00, 0x00,
346 			   0x00, 0x00, 0x00, 0x00,
347 			   0x00, 0x00, 0x00, 0x00);
348 	ST7701_DSI(st7701, 0xE3,
349 		   0x00, 0x00, 0x22, 0x22);
350 	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
351 	ST7701_DSI(st7701, 0xE5,
352 		   0x0C, 0x90, 0xA0, 0xA0,
353 			   0x0E, 0x92, 0xA0, 0xA0,
354 			   0x08, 0x8C, 0xA0, 0xA0,
355 			   0x0A, 0x8E, 0xA0, 0xA0);
356 	ST7701_DSI(st7701, 0xE6,
357 		   0x00, 0x00, 0x22, 0x22);
358 	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
359 	ST7701_DSI(st7701, 0xE8,
360 		   0x0D, 0x91, 0xA0, 0xA0,
361 			   0x0F, 0x93, 0xA0, 0xA0,
362 			   0x09, 0x8D, 0xA0, 0xA0,
363 			   0x0B, 0x8F, 0xA0, 0xA0);
364 	ST7701_DSI(st7701, 0xEB,
365 		   0x00, 0x00, 0xE4, 0xE4,
366 			   0x44, 0x00, 0x00);
367 	ST7701_DSI(st7701, 0xED,
368 		   0xFF, 0xF5, 0x47, 0x6F,
369 			   0x0B, 0xA1, 0xAB, 0xFF,
370 			   0xFF, 0xBA, 0x1A, 0xB0,
371 			   0xF6, 0x74, 0x5F, 0xFF);
372 	ST7701_DSI(st7701, 0xEF,
373 		   0x08, 0x08, 0x08, 0x40,
374 			   0x3F, 0x64);
375 
376 	st7701_switch_cmd_bkx(st7701, false, 0);
377 
378 	st7701_switch_cmd_bkx(st7701, true, 3);
379 	ST7701_DSI(st7701, 0xE6, 0x7C);
380 	ST7701_DSI(st7701, 0xE8, 0x00, 0x0E);
381 
382 	st7701_switch_cmd_bkx(st7701, false, 0);
383 	ST7701_DSI(st7701, 0x11);
384 	msleep(120);
385 
386 	st7701_switch_cmd_bkx(st7701, true, 3);
387 	ST7701_DSI(st7701, 0xE8, 0x00, 0x0C);
388 	msleep(10);
389 	ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
390 
391 	st7701_switch_cmd_bkx(st7701, false, 0);
392 	ST7701_DSI(st7701, 0x11);
393 	msleep(120);
394 	ST7701_DSI(st7701, 0xE8, 0x00, 0x00);
395 
396 	st7701_switch_cmd_bkx(st7701, false, 0);
397 
398 	ST7701_DSI(st7701, 0x3A, 0x70);
399 }
400 
401 static void kd50t048a_gip_sequence(struct st7701 *st7701)
402 {
403 	/**
404 	 * ST7701_SPEC_V1.2 is unable to provide enough information above this
405 	 * specific command sequence, so grab the same from vendor BSP driver.
406 	 */
407 	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
408 	ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
409 		   0x00, 0x00, 0x33, 0x33);
410 	ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
411 		   0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
412 	ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
413 	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
414 	ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
415 		   0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);
416 	ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
417 	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
418 	ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
419 		   0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);
420 	ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
421 	ST7701_DSI(st7701, 0xEC, 0x02, 0x01);
422 	ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
423 		   0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);
424 }
425 
426 static int st7701_prepare(struct drm_panel *panel)
427 {
428 	struct st7701 *st7701 = panel_to_st7701(panel);
429 	int ret;
430 
431 	gpiod_set_value(st7701->reset, 0);
432 
433 	ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies),
434 				    st7701->supplies);
435 	if (ret < 0)
436 		return ret;
437 	msleep(20);
438 
439 	gpiod_set_value(st7701->reset, 1);
440 	msleep(150);
441 
442 	st7701_init_sequence(st7701);
443 
444 	if (st7701->desc->gip_sequence)
445 		st7701->desc->gip_sequence(st7701);
446 
447 	/* Disable Command2 */
448 	st7701_switch_cmd_bkx(st7701, false, 0);
449 
450 	return 0;
451 }
452 
453 static int st7701_enable(struct drm_panel *panel)
454 {
455 	struct st7701 *st7701 = panel_to_st7701(panel);
456 
457 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
458 
459 	return 0;
460 }
461 
462 static int st7701_disable(struct drm_panel *panel)
463 {
464 	struct st7701 *st7701 = panel_to_st7701(panel);
465 
466 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
467 
468 	return 0;
469 }
470 
471 static int st7701_unprepare(struct drm_panel *panel)
472 {
473 	struct st7701 *st7701 = panel_to_st7701(panel);
474 
475 	ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
476 
477 	msleep(st7701->sleep_delay);
478 
479 	gpiod_set_value(st7701->reset, 0);
480 
481 	/**
482 	 * During the Resetting period, the display will be blanked
483 	 * (The display is entering blanking sequence, which maximum
484 	 * time is 120 ms, when Reset Starts in Sleep Out –mode. The
485 	 * display remains the blank state in Sleep In –mode.) and
486 	 * then return to Default condition for Hardware Reset.
487 	 *
488 	 * So we need wait sleep_delay time to make sure reset completed.
489 	 */
490 	msleep(st7701->sleep_delay);
491 
492 	regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies);
493 
494 	return 0;
495 }
496 
497 static int st7701_get_modes(struct drm_panel *panel,
498 			    struct drm_connector *connector)
499 {
500 	struct st7701 *st7701 = panel_to_st7701(panel);
501 	const struct drm_display_mode *desc_mode = st7701->desc->mode;
502 	struct drm_display_mode *mode;
503 
504 	mode = drm_mode_duplicate(connector->dev, desc_mode);
505 	if (!mode) {
506 		dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
507 			desc_mode->hdisplay, desc_mode->vdisplay,
508 			drm_mode_vrefresh(desc_mode));
509 		return -ENOMEM;
510 	}
511 
512 	drm_mode_set_name(mode);
513 	drm_mode_probed_add(connector, mode);
514 
515 	connector->display_info.width_mm = desc_mode->width_mm;
516 	connector->display_info.height_mm = desc_mode->height_mm;
517 
518 	/*
519 	 * TODO: Remove once all drm drivers call
520 	 * drm_connector_set_orientation_from_panel()
521 	 */
522 	drm_connector_set_panel_orientation(connector, st7701->orientation);
523 
524 	return 1;
525 }
526 
527 static enum drm_panel_orientation st7701_get_orientation(struct drm_panel *panel)
528 {
529 	struct st7701 *st7701 = panel_to_st7701(panel);
530 
531 	return st7701->orientation;
532 }
533 
534 static const struct drm_panel_funcs st7701_funcs = {
535 	.disable	= st7701_disable,
536 	.unprepare	= st7701_unprepare,
537 	.prepare	= st7701_prepare,
538 	.enable		= st7701_enable,
539 	.get_modes	= st7701_get_modes,
540 	.get_orientation = st7701_get_orientation,
541 };
542 
543 static const struct drm_display_mode ts8550b_mode = {
544 	.clock		= 27500,
545 
546 	.hdisplay	= 480,
547 	.hsync_start	= 480 + 38,
548 	.hsync_end	= 480 + 38 + 12,
549 	.htotal		= 480 + 38 + 12 + 12,
550 
551 	.vdisplay	= 854,
552 	.vsync_start	= 854 + 18,
553 	.vsync_end	= 854 + 18 + 8,
554 	.vtotal		= 854 + 18 + 8 + 4,
555 
556 	.width_mm	= 69,
557 	.height_mm	= 139,
558 
559 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
560 };
561 
562 static const struct st7701_panel_desc ts8550b_desc = {
563 	.mode = &ts8550b_mode,
564 	.lanes = 2,
565 	.format = MIPI_DSI_FMT_RGB888,
566 	.panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
567 
568 	.pv_gamma = {
569 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
570 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
571 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
572 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
573 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
574 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
575 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
576 
577 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
578 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
579 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
580 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
581 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
582 
583 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
584 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
585 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
586 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
587 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
588 
589 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
590 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
591 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
592 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
593 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
594 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
595 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
596 	},
597 	.nv_gamma = {
598 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
599 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
600 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
601 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
602 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
603 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
604 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
605 
606 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
607 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
608 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
609 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
610 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
611 
612 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
613 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
614 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
615 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
616 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
617 
618 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
619 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
620 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
621 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
622 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
623 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
624 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
625 	},
626 	.nlinv = 7,
627 	.vop_uv = 4400000,
628 	.vcom_uv = 337500,
629 	.vgh_mv = 15000,
630 	.vgl_mv = -9510,
631 	.avdd_mv = 6600,
632 	.avcl_mv = -4400,
633 	.gamma_op_bias = OP_BIAS_MAX,
634 	.input_op_bias = OP_BIAS_MIN,
635 	.output_op_bias = OP_BIAS_MIN,
636 	.t2d_ns = 1600,
637 	.t3d_ns = 10400,
638 	.eot_en = true,
639 	.gip_sequence = ts8550b_gip_sequence,
640 };
641 
642 static const struct drm_display_mode dmt028vghmcmi_1a_mode = {
643 	.clock		= 22325,
644 
645 	.hdisplay	= 480,
646 	.hsync_start	= 480 + 40,
647 	.hsync_end	= 480 + 40 + 4,
648 	.htotal		= 480 + 40 + 4 + 20,
649 
650 	.vdisplay	= 640,
651 	.vsync_start	= 640 + 2,
652 	.vsync_end	= 640 + 2 + 40,
653 	.vtotal		= 640 + 2 + 40 + 16,
654 
655 	.width_mm	= 56,
656 	.height_mm	= 78,
657 
658 	.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
659 
660 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
661 };
662 
663 static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = {
664 	.mode = &dmt028vghmcmi_1a_mode,
665 	.lanes = 2,
666 	.format = MIPI_DSI_FMT_RGB888,
667 	.panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */
668 
669 	.pv_gamma = {
670 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
671 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
672 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
673 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
674 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
675 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
676 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
677 
678 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
679 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
680 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
681 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
682 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
683 
684 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
685 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
686 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
687 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
688 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
689 
690 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
691 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
692 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
693 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
694 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
695 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
696 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
697 	},
698 	.nv_gamma = {
699 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
700 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
701 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
702 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
703 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
704 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
705 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
706 
707 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
708 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
709 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
710 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
711 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
712 
713 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
714 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
715 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
716 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
717 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
718 
719 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
720 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
721 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
722 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
723 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
724 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
725 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
726 	},
727 	.nlinv = 1,
728 	.vop_uv = 4800000,
729 	.vcom_uv = 1650000,
730 	.vgh_mv = 15000,
731 	.vgl_mv = -10170,
732 	.avdd_mv = 6600,
733 	.avcl_mv = -4400,
734 	.gamma_op_bias = OP_BIAS_MIDDLE,
735 	.input_op_bias = OP_BIAS_MIN,
736 	.output_op_bias = OP_BIAS_MIN,
737 	.t2d_ns = 1600,
738 	.t3d_ns = 10400,
739 	.eot_en = true,
740 	.gip_sequence = dmt028vghmcmi_1a_gip_sequence,
741 };
742 
743 static const struct drm_display_mode kd50t048a_mode = {
744 	.clock          = 27500,
745 
746 	.hdisplay       = 480,
747 	.hsync_start    = 480 + 2,
748 	.hsync_end      = 480 + 2 + 10,
749 	.htotal         = 480 + 2 + 10 + 2,
750 
751 	.vdisplay       = 854,
752 	.vsync_start    = 854 + 2,
753 	.vsync_end      = 854 + 2 + 2,
754 	.vtotal         = 854 + 2 + 2 + 17,
755 
756 	.width_mm       = 69,
757 	.height_mm      = 139,
758 
759 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
760 };
761 
762 static const struct st7701_panel_desc kd50t048a_desc = {
763 	.mode = &kd50t048a_mode,
764 	.lanes = 2,
765 	.format = MIPI_DSI_FMT_RGB888,
766 	.panel_sleep_delay = 0,
767 
768 	.pv_gamma = {
769 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
770 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
771 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
772 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
773 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
774 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
775 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
776 
777 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
778 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
779 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
780 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
781 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
782 
783 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
784 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
785 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
786 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
787 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
788 
789 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
790 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
791 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
792 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
793 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
794 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
795 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
796 	},
797 	.nv_gamma = {
798 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
799 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
800 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
801 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
802 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
803 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
804 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
805 
806 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
807 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
808 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
809 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
810 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
811 
812 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
813 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
814 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
815 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
816 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
817 
818 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
819 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) |
820 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
821 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
822 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
823 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
824 		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
825 	},
826 	.nlinv = 1,
827 	.vop_uv = 4887500,
828 	.vcom_uv = 937500,
829 	.vgh_mv = 15000,
830 	.vgl_mv = -9510,
831 	.avdd_mv = 6600,
832 	.avcl_mv = -4400,
833 	.gamma_op_bias = OP_BIAS_MIDDLE,
834 	.input_op_bias = OP_BIAS_MIN,
835 	.output_op_bias = OP_BIAS_MIN,
836 	.t2d_ns = 1600,
837 	.t3d_ns = 10400,
838 	.eot_en = true,
839 	.gip_sequence = kd50t048a_gip_sequence,
840 };
841 
842 static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
843 {
844 	const struct st7701_panel_desc *desc;
845 	struct st7701 *st7701;
846 	int ret;
847 
848 	st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL);
849 	if (!st7701)
850 		return -ENOMEM;
851 
852 	desc = of_device_get_match_data(&dsi->dev);
853 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
854 			  MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
855 	dsi->format = desc->format;
856 	dsi->lanes = desc->lanes;
857 
858 	st7701->supplies[0].supply = "VCC";
859 	st7701->supplies[1].supply = "IOVCC";
860 
861 	ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies),
862 				      st7701->supplies);
863 	if (ret < 0)
864 		return ret;
865 
866 	st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
867 	if (IS_ERR(st7701->reset)) {
868 		dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
869 		return PTR_ERR(st7701->reset);
870 	}
871 
872 	ret = of_drm_get_panel_orientation(dsi->dev.of_node, &st7701->orientation);
873 	if (ret < 0)
874 		return dev_err_probe(&dsi->dev, ret, "Failed to get orientation\n");
875 
876 	drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
877 		       DRM_MODE_CONNECTOR_DSI);
878 
879 	/**
880 	 * Once sleep out has been issued, ST7701 IC required to wait 120ms
881 	 * before initiating new commands.
882 	 *
883 	 * On top of that some panels might need an extra delay to wait, so
884 	 * add panel specific delay for those cases. As now this panel specific
885 	 * delay information is referenced from those panel BSP driver, example
886 	 * ts8550b and there is no valid documentation for that.
887 	 */
888 	st7701->sleep_delay = 120 + desc->panel_sleep_delay;
889 
890 	ret = drm_panel_of_backlight(&st7701->panel);
891 	if (ret)
892 		return ret;
893 
894 	drm_panel_add(&st7701->panel);
895 
896 	mipi_dsi_set_drvdata(dsi, st7701);
897 	st7701->dsi = dsi;
898 	st7701->desc = desc;
899 
900 	ret = mipi_dsi_attach(dsi);
901 	if (ret)
902 		goto err_attach;
903 
904 	return 0;
905 
906 err_attach:
907 	drm_panel_remove(&st7701->panel);
908 	return ret;
909 }
910 
911 static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
912 {
913 	struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
914 
915 	mipi_dsi_detach(dsi);
916 	drm_panel_remove(&st7701->panel);
917 }
918 
919 static const struct of_device_id st7701_of_match[] = {
920 	{ .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },
921 	{ .compatible = "elida,kd50t048a", .data = &kd50t048a_desc },
922 	{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
923 	{ }
924 };
925 MODULE_DEVICE_TABLE(of, st7701_of_match);
926 
927 static struct mipi_dsi_driver st7701_dsi_driver = {
928 	.probe		= st7701_dsi_probe,
929 	.remove		= st7701_dsi_remove,
930 	.driver = {
931 		.name		= "st7701",
932 		.of_match_table	= st7701_of_match,
933 	},
934 };
935 module_mipi_dsi_driver(st7701_dsi_driver);
936 
937 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
938 MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
939 MODULE_LICENSE("GPL");
940