1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) 579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 580 "failed to request GPIO\n"); 581 582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 583 if (err) { 584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 585 return err; 586 } 587 588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 589 if (ddc) { 590 panel->ddc = of_find_i2c_adapter_by_node(ddc); 591 of_node_put(ddc); 592 593 if (!panel->ddc) 594 return -EPROBE_DEFER; 595 } 596 597 if (desc == &panel_dpi) { 598 /* Handle the generic panel-dpi binding */ 599 err = panel_dpi_probe(dev, panel); 600 if (err) 601 goto free_ddc; 602 desc = panel->desc; 603 } else { 604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 605 panel_simple_parse_panel_timing_node(dev, panel, &dt); 606 } 607 608 connector_type = desc->connector_type; 609 /* Catch common mistakes for panels. */ 610 switch (connector_type) { 611 case 0: 612 dev_warn(dev, "Specify missing connector_type\n"); 613 connector_type = DRM_MODE_CONNECTOR_DPI; 614 break; 615 case DRM_MODE_CONNECTOR_LVDS: 616 WARN_ON(desc->bus_flags & 617 ~(DRM_BUS_FLAG_DE_LOW | 618 DRM_BUS_FLAG_DE_HIGH | 619 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 620 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bpc != 6); 626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 628 desc->bpc != 8); 629 break; 630 case DRM_MODE_CONNECTOR_eDP: 631 dev_warn(dev, "eDP panels moved to panel-edp\n"); 632 err = -EINVAL; 633 goto free_ddc; 634 case DRM_MODE_CONNECTOR_DSI: 635 if (desc->bpc != 6 && desc->bpc != 8) 636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 637 break; 638 case DRM_MODE_CONNECTOR_DPI: 639 bus_flags = DRM_BUS_FLAG_DE_LOW | 640 DRM_BUS_FLAG_DE_HIGH | 641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 647 if (desc->bus_flags & ~bus_flags) 648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 649 if (!(desc->bus_flags & bus_flags)) 650 dev_warn(dev, "Specify missing bus_flags\n"); 651 if (desc->bus_format == 0) 652 dev_warn(dev, "Specify missing bus_format\n"); 653 if (desc->bpc != 6 && desc->bpc != 8) 654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 655 break; 656 default: 657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 658 connector_type = DRM_MODE_CONNECTOR_DPI; 659 break; 660 } 661 662 dev_set_drvdata(dev, panel); 663 664 /* 665 * We use runtime PM for prepare / unprepare since those power the panel 666 * on and off and those can be very slow operations. This is important 667 * to optimize powering the panel on briefly to read the EDID before 668 * fully enabling the panel. 669 */ 670 pm_runtime_enable(dev); 671 pm_runtime_set_autosuspend_delay(dev, 1000); 672 pm_runtime_use_autosuspend(dev); 673 674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 675 676 err = drm_panel_of_backlight(&panel->base); 677 if (err) { 678 dev_err_probe(dev, err, "Could not find backlight\n"); 679 goto disable_pm_runtime; 680 } 681 682 drm_panel_add(&panel->base); 683 684 return 0; 685 686 disable_pm_runtime: 687 pm_runtime_dont_use_autosuspend(dev); 688 pm_runtime_disable(dev); 689 free_ddc: 690 if (panel->ddc) 691 put_device(&panel->ddc->dev); 692 693 return err; 694 } 695 696 static void panel_simple_remove(struct device *dev) 697 { 698 struct panel_simple *panel = dev_get_drvdata(dev); 699 700 drm_panel_remove(&panel->base); 701 drm_panel_disable(&panel->base); 702 drm_panel_unprepare(&panel->base); 703 704 pm_runtime_dont_use_autosuspend(dev); 705 pm_runtime_disable(dev); 706 if (panel->ddc) 707 put_device(&panel->ddc->dev); 708 } 709 710 static void panel_simple_shutdown(struct device *dev) 711 { 712 struct panel_simple *panel = dev_get_drvdata(dev); 713 714 drm_panel_disable(&panel->base); 715 drm_panel_unprepare(&panel->base); 716 } 717 718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 719 .clock = 71100, 720 .hdisplay = 1280, 721 .hsync_start = 1280 + 40, 722 .hsync_end = 1280 + 40 + 80, 723 .htotal = 1280 + 40 + 80 + 40, 724 .vdisplay = 800, 725 .vsync_start = 800 + 3, 726 .vsync_end = 800 + 3 + 10, 727 .vtotal = 800 + 3 + 10 + 10, 728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 729 }; 730 731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 732 .modes = &ire_am_1280800n3tzqw_t00h_mode, 733 .num_modes = 1, 734 .bpc = 8, 735 .size = { 736 .width = 217, 737 .height = 136, 738 }, 739 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 742 }; 743 744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 745 .clock = 9000, 746 .hdisplay = 480, 747 .hsync_start = 480 + 2, 748 .hsync_end = 480 + 2 + 41, 749 .htotal = 480 + 2 + 41 + 2, 750 .vdisplay = 272, 751 .vsync_start = 272 + 2, 752 .vsync_end = 272 + 2 + 10, 753 .vtotal = 272 + 2 + 10 + 2, 754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 755 }; 756 757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 758 .modes = &ire_am_480272h3tmqw_t01h_mode, 759 .num_modes = 1, 760 .bpc = 8, 761 .size = { 762 .width = 105, 763 .height = 67, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 766 }; 767 768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 769 .clock = 33333, 770 .hdisplay = 800, 771 .hsync_start = 800 + 0, 772 .hsync_end = 800 + 0 + 255, 773 .htotal = 800 + 0 + 255 + 0, 774 .vdisplay = 480, 775 .vsync_start = 480 + 2, 776 .vsync_end = 480 + 2 + 45, 777 .vtotal = 480 + 2 + 45 + 0, 778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 779 }; 780 781 static const struct panel_desc ampire_am800480r3tmqwa1h = { 782 .modes = &ire_am800480r3tmqwa1h_mode, 783 .num_modes = 1, 784 .bpc = 6, 785 .size = { 786 .width = 152, 787 .height = 91, 788 }, 789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 790 }; 791 792 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 793 .pixelclock = { 34500000, 39600000, 50400000 }, 794 .hactive = { 800, 800, 800 }, 795 .hfront_porch = { 12, 112, 312 }, 796 .hback_porch = { 87, 87, 48 }, 797 .hsync_len = { 1, 1, 40 }, 798 .vactive = { 600, 600, 600 }, 799 .vfront_porch = { 1, 21, 61 }, 800 .vback_porch = { 38, 38, 19 }, 801 .vsync_len = { 1, 1, 20 }, 802 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 803 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 804 DISPLAY_FLAGS_SYNC_POSEDGE, 805 }; 806 807 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 808 .timings = &ire_am800600p5tmqw_tb8h_timing, 809 .num_timings = 1, 810 .bpc = 6, 811 .size = { 812 .width = 162, 813 .height = 122, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 817 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 818 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 819 .connector_type = DRM_MODE_CONNECTOR_DPI, 820 }; 821 822 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 823 .pixelclock = { 26400000, 33300000, 46800000 }, 824 .hactive = { 800, 800, 800 }, 825 .hfront_porch = { 16, 210, 354 }, 826 .hback_porch = { 45, 36, 6 }, 827 .hsync_len = { 1, 10, 40 }, 828 .vactive = { 480, 480, 480 }, 829 .vfront_porch = { 7, 22, 147 }, 830 .vback_porch = { 22, 13, 3 }, 831 .vsync_len = { 1, 10, 20 }, 832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 834 }; 835 836 static const struct panel_desc armadeus_st0700_adapt = { 837 .timings = &santek_st0700i5y_rbslw_f_timing, 838 .num_timings = 1, 839 .bpc = 6, 840 .size = { 841 .width = 154, 842 .height = 86, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 846 }; 847 848 static const struct drm_display_mode auo_b101aw03_mode = { 849 .clock = 51450, 850 .hdisplay = 1024, 851 .hsync_start = 1024 + 156, 852 .hsync_end = 1024 + 156 + 8, 853 .htotal = 1024 + 156 + 8 + 156, 854 .vdisplay = 600, 855 .vsync_start = 600 + 16, 856 .vsync_end = 600 + 16 + 6, 857 .vtotal = 600 + 16 + 6 + 16, 858 }; 859 860 static const struct panel_desc auo_b101aw03 = { 861 .modes = &auo_b101aw03_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 223, 866 .height = 125, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 869 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 871 }; 872 873 static const struct drm_display_mode auo_b101xtn01_mode = { 874 .clock = 72000, 875 .hdisplay = 1366, 876 .hsync_start = 1366 + 20, 877 .hsync_end = 1366 + 20 + 70, 878 .htotal = 1366 + 20 + 70, 879 .vdisplay = 768, 880 .vsync_start = 768 + 14, 881 .vsync_end = 768 + 14 + 42, 882 .vtotal = 768 + 14 + 42, 883 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 884 }; 885 886 static const struct panel_desc auo_b101xtn01 = { 887 .modes = &auo_b101xtn01_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 }; 895 896 static const struct display_timing auo_g070vvn01_timings = { 897 .pixelclock = { 33300000, 34209000, 45000000 }, 898 .hactive = { 800, 800, 800 }, 899 .hfront_porch = { 20, 40, 200 }, 900 .hback_porch = { 87, 40, 1 }, 901 .hsync_len = { 1, 48, 87 }, 902 .vactive = { 480, 480, 480 }, 903 .vfront_porch = { 5, 13, 200 }, 904 .vback_porch = { 31, 31, 29 }, 905 .vsync_len = { 1, 1, 3 }, 906 }; 907 908 static const struct panel_desc auo_g070vvn01 = { 909 .timings = &auo_g070vvn01_timings, 910 .num_timings = 1, 911 .bpc = 8, 912 .size = { 913 .width = 152, 914 .height = 91, 915 }, 916 .delay = { 917 .prepare = 200, 918 .enable = 50, 919 .disable = 50, 920 .unprepare = 1000, 921 }, 922 }; 923 924 static const struct drm_display_mode auo_g101evn010_mode = { 925 .clock = 68930, 926 .hdisplay = 1280, 927 .hsync_start = 1280 + 82, 928 .hsync_end = 1280 + 82 + 2, 929 .htotal = 1280 + 82 + 2 + 84, 930 .vdisplay = 800, 931 .vsync_start = 800 + 8, 932 .vsync_end = 800 + 8 + 2, 933 .vtotal = 800 + 8 + 2 + 6, 934 }; 935 936 static const struct panel_desc auo_g101evn010 = { 937 .modes = &auo_g101evn010_mode, 938 .num_modes = 1, 939 .bpc = 6, 940 .size = { 941 .width = 216, 942 .height = 135, 943 }, 944 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 946 }; 947 948 static const struct drm_display_mode auo_g104sn02_mode = { 949 .clock = 40000, 950 .hdisplay = 800, 951 .hsync_start = 800 + 40, 952 .hsync_end = 800 + 40 + 216, 953 .htotal = 800 + 40 + 216 + 128, 954 .vdisplay = 600, 955 .vsync_start = 600 + 10, 956 .vsync_end = 600 + 10 + 35, 957 .vtotal = 600 + 10 + 35 + 2, 958 }; 959 960 static const struct panel_desc auo_g104sn02 = { 961 .modes = &auo_g104sn02_mode, 962 .num_modes = 1, 963 .bpc = 8, 964 .size = { 965 .width = 211, 966 .height = 158, 967 }, 968 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 970 }; 971 972 static const struct drm_display_mode auo_g121ean01_mode = { 973 .clock = 66700, 974 .hdisplay = 1280, 975 .hsync_start = 1280 + 58, 976 .hsync_end = 1280 + 58 + 8, 977 .htotal = 1280 + 58 + 8 + 70, 978 .vdisplay = 800, 979 .vsync_start = 800 + 6, 980 .vsync_end = 800 + 6 + 4, 981 .vtotal = 800 + 6 + 4 + 10, 982 }; 983 984 static const struct panel_desc auo_g121ean01 = { 985 .modes = &auo_g121ean01_mode, 986 .num_modes = 1, 987 .bpc = 8, 988 .size = { 989 .width = 261, 990 .height = 163, 991 }, 992 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 993 .connector_type = DRM_MODE_CONNECTOR_LVDS, 994 }; 995 996 static const struct display_timing auo_g133han01_timings = { 997 .pixelclock = { 134000000, 141200000, 149000000 }, 998 .hactive = { 1920, 1920, 1920 }, 999 .hfront_porch = { 39, 58, 77 }, 1000 .hback_porch = { 59, 88, 117 }, 1001 .hsync_len = { 28, 42, 56 }, 1002 .vactive = { 1080, 1080, 1080 }, 1003 .vfront_porch = { 3, 8, 11 }, 1004 .vback_porch = { 5, 14, 19 }, 1005 .vsync_len = { 4, 14, 19 }, 1006 }; 1007 1008 static const struct panel_desc auo_g133han01 = { 1009 .timings = &auo_g133han01_timings, 1010 .num_timings = 1, 1011 .bpc = 8, 1012 .size = { 1013 .width = 293, 1014 .height = 165, 1015 }, 1016 .delay = { 1017 .prepare = 200, 1018 .enable = 50, 1019 .disable = 50, 1020 .unprepare = 1000, 1021 }, 1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1024 }; 1025 1026 static const struct drm_display_mode auo_g156xtn01_mode = { 1027 .clock = 76000, 1028 .hdisplay = 1366, 1029 .hsync_start = 1366 + 33, 1030 .hsync_end = 1366 + 33 + 67, 1031 .htotal = 1560, 1032 .vdisplay = 768, 1033 .vsync_start = 768 + 4, 1034 .vsync_end = 768 + 4 + 4, 1035 .vtotal = 806, 1036 }; 1037 1038 static const struct panel_desc auo_g156xtn01 = { 1039 .modes = &auo_g156xtn01_mode, 1040 .num_modes = 1, 1041 .bpc = 8, 1042 .size = { 1043 .width = 344, 1044 .height = 194, 1045 }, 1046 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1048 }; 1049 1050 static const struct display_timing auo_g185han01_timings = { 1051 .pixelclock = { 120000000, 144000000, 175000000 }, 1052 .hactive = { 1920, 1920, 1920 }, 1053 .hfront_porch = { 36, 120, 148 }, 1054 .hback_porch = { 24, 88, 108 }, 1055 .hsync_len = { 20, 48, 64 }, 1056 .vactive = { 1080, 1080, 1080 }, 1057 .vfront_porch = { 6, 10, 40 }, 1058 .vback_porch = { 2, 5, 20 }, 1059 .vsync_len = { 2, 5, 20 }, 1060 }; 1061 1062 static const struct panel_desc auo_g185han01 = { 1063 .timings = &auo_g185han01_timings, 1064 .num_timings = 1, 1065 .bpc = 8, 1066 .size = { 1067 .width = 409, 1068 .height = 230, 1069 }, 1070 .delay = { 1071 .prepare = 50, 1072 .enable = 200, 1073 .disable = 110, 1074 .unprepare = 1000, 1075 }, 1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1077 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1078 }; 1079 1080 static const struct display_timing auo_g190ean01_timings = { 1081 .pixelclock = { 90000000, 108000000, 135000000 }, 1082 .hactive = { 1280, 1280, 1280 }, 1083 .hfront_porch = { 126, 184, 1266 }, 1084 .hback_porch = { 84, 122, 844 }, 1085 .hsync_len = { 70, 102, 704 }, 1086 .vactive = { 1024, 1024, 1024 }, 1087 .vfront_porch = { 4, 26, 76 }, 1088 .vback_porch = { 2, 8, 25 }, 1089 .vsync_len = { 2, 8, 25 }, 1090 }; 1091 1092 static const struct panel_desc auo_g190ean01 = { 1093 .timings = &auo_g190ean01_timings, 1094 .num_timings = 1, 1095 .bpc = 8, 1096 .size = { 1097 .width = 376, 1098 .height = 301, 1099 }, 1100 .delay = { 1101 .prepare = 50, 1102 .enable = 200, 1103 .disable = 110, 1104 .unprepare = 1000, 1105 }, 1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1108 }; 1109 1110 static const struct display_timing auo_p320hvn03_timings = { 1111 .pixelclock = { 106000000, 148500000, 164000000 }, 1112 .hactive = { 1920, 1920, 1920 }, 1113 .hfront_porch = { 25, 50, 130 }, 1114 .hback_porch = { 25, 50, 130 }, 1115 .hsync_len = { 20, 40, 105 }, 1116 .vactive = { 1080, 1080, 1080 }, 1117 .vfront_porch = { 8, 17, 150 }, 1118 .vback_porch = { 8, 17, 150 }, 1119 .vsync_len = { 4, 11, 100 }, 1120 }; 1121 1122 static const struct panel_desc auo_p320hvn03 = { 1123 .timings = &auo_p320hvn03_timings, 1124 .num_timings = 1, 1125 .bpc = 8, 1126 .size = { 1127 .width = 698, 1128 .height = 393, 1129 }, 1130 .delay = { 1131 .prepare = 1, 1132 .enable = 450, 1133 .unprepare = 500, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct drm_display_mode auo_t215hvn01_mode = { 1140 .clock = 148800, 1141 .hdisplay = 1920, 1142 .hsync_start = 1920 + 88, 1143 .hsync_end = 1920 + 88 + 44, 1144 .htotal = 1920 + 88 + 44 + 148, 1145 .vdisplay = 1080, 1146 .vsync_start = 1080 + 4, 1147 .vsync_end = 1080 + 4 + 5, 1148 .vtotal = 1080 + 4 + 5 + 36, 1149 }; 1150 1151 static const struct panel_desc auo_t215hvn01 = { 1152 .modes = &auo_t215hvn01_mode, 1153 .num_modes = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 430, 1157 .height = 270, 1158 }, 1159 .delay = { 1160 .disable = 5, 1161 .unprepare = 1000, 1162 } 1163 }; 1164 1165 static const struct drm_display_mode avic_tm070ddh03_mode = { 1166 .clock = 51200, 1167 .hdisplay = 1024, 1168 .hsync_start = 1024 + 160, 1169 .hsync_end = 1024 + 160 + 4, 1170 .htotal = 1024 + 160 + 4 + 156, 1171 .vdisplay = 600, 1172 .vsync_start = 600 + 17, 1173 .vsync_end = 600 + 17 + 1, 1174 .vtotal = 600 + 17 + 1 + 17, 1175 }; 1176 1177 static const struct panel_desc avic_tm070ddh03 = { 1178 .modes = &avic_tm070ddh03_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 154, 1183 .height = 90, 1184 }, 1185 .delay = { 1186 .prepare = 20, 1187 .enable = 200, 1188 .disable = 200, 1189 }, 1190 }; 1191 1192 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1193 .clock = 30000, 1194 .hdisplay = 800, 1195 .hsync_start = 800 + 40, 1196 .hsync_end = 800 + 40 + 48, 1197 .htotal = 800 + 40 + 48 + 40, 1198 .vdisplay = 480, 1199 .vsync_start = 480 + 13, 1200 .vsync_end = 480 + 13 + 3, 1201 .vtotal = 480 + 13 + 3 + 29, 1202 }; 1203 1204 static const struct panel_desc bananapi_s070wv20_ct16 = { 1205 .modes = &bananapi_s070wv20_ct16_mode, 1206 .num_modes = 1, 1207 .bpc = 6, 1208 .size = { 1209 .width = 154, 1210 .height = 86, 1211 }, 1212 }; 1213 1214 static const struct drm_display_mode boe_hv070wsa_mode = { 1215 .clock = 42105, 1216 .hdisplay = 1024, 1217 .hsync_start = 1024 + 30, 1218 .hsync_end = 1024 + 30 + 30, 1219 .htotal = 1024 + 30 + 30 + 30, 1220 .vdisplay = 600, 1221 .vsync_start = 600 + 10, 1222 .vsync_end = 600 + 10 + 10, 1223 .vtotal = 600 + 10 + 10 + 10, 1224 }; 1225 1226 static const struct panel_desc boe_hv070wsa = { 1227 .modes = &boe_hv070wsa_mode, 1228 .num_modes = 1, 1229 .bpc = 8, 1230 .size = { 1231 .width = 154, 1232 .height = 90, 1233 }, 1234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1235 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1236 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1237 }; 1238 1239 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1240 .clock = 9000, 1241 .hdisplay = 480, 1242 .hsync_start = 480 + 5, 1243 .hsync_end = 480 + 5 + 5, 1244 .htotal = 480 + 5 + 5 + 40, 1245 .vdisplay = 272, 1246 .vsync_start = 272 + 8, 1247 .vsync_end = 272 + 8 + 8, 1248 .vtotal = 272 + 8 + 8 + 8, 1249 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1250 }; 1251 1252 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1253 .modes = &cdtech_s043wq26h_ct7_mode, 1254 .num_modes = 1, 1255 .bpc = 8, 1256 .size = { 1257 .width = 95, 1258 .height = 54, 1259 }, 1260 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1261 }; 1262 1263 /* S070PWS19HP-FC21 2017/04/22 */ 1264 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1265 .clock = 51200, 1266 .hdisplay = 1024, 1267 .hsync_start = 1024 + 160, 1268 .hsync_end = 1024 + 160 + 20, 1269 .htotal = 1024 + 160 + 20 + 140, 1270 .vdisplay = 600, 1271 .vsync_start = 600 + 12, 1272 .vsync_end = 600 + 12 + 3, 1273 .vtotal = 600 + 12 + 3 + 20, 1274 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1275 }; 1276 1277 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1278 .modes = &cdtech_s070pws19hp_fc21_mode, 1279 .num_modes = 1, 1280 .bpc = 6, 1281 .size = { 1282 .width = 154, 1283 .height = 86, 1284 }, 1285 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1286 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1287 .connector_type = DRM_MODE_CONNECTOR_DPI, 1288 }; 1289 1290 /* S070SWV29HG-DC44 2017/09/21 */ 1291 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1292 .clock = 33300, 1293 .hdisplay = 800, 1294 .hsync_start = 800 + 210, 1295 .hsync_end = 800 + 210 + 2, 1296 .htotal = 800 + 210 + 2 + 44, 1297 .vdisplay = 480, 1298 .vsync_start = 480 + 22, 1299 .vsync_end = 480 + 22 + 2, 1300 .vtotal = 480 + 22 + 2 + 21, 1301 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1302 }; 1303 1304 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1305 .modes = &cdtech_s070swv29hg_dc44_mode, 1306 .num_modes = 1, 1307 .bpc = 6, 1308 .size = { 1309 .width = 154, 1310 .height = 86, 1311 }, 1312 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1313 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1314 .connector_type = DRM_MODE_CONNECTOR_DPI, 1315 }; 1316 1317 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1318 .clock = 35000, 1319 .hdisplay = 800, 1320 .hsync_start = 800 + 40, 1321 .hsync_end = 800 + 40 + 40, 1322 .htotal = 800 + 40 + 40 + 48, 1323 .vdisplay = 480, 1324 .vsync_start = 480 + 29, 1325 .vsync_end = 480 + 29 + 13, 1326 .vtotal = 480 + 29 + 13 + 3, 1327 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1328 }; 1329 1330 static const struct panel_desc cdtech_s070wv95_ct16 = { 1331 .modes = &cdtech_s070wv95_ct16_mode, 1332 .num_modes = 1, 1333 .bpc = 8, 1334 .size = { 1335 .width = 154, 1336 .height = 85, 1337 }, 1338 }; 1339 1340 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1341 .pixelclock = { 68900000, 71100000, 73400000 }, 1342 .hactive = { 1280, 1280, 1280 }, 1343 .hfront_porch = { 65, 80, 95 }, 1344 .hback_porch = { 64, 79, 94 }, 1345 .hsync_len = { 1, 1, 1 }, 1346 .vactive = { 800, 800, 800 }, 1347 .vfront_porch = { 7, 11, 14 }, 1348 .vback_porch = { 7, 11, 14 }, 1349 .vsync_len = { 1, 1, 1 }, 1350 .flags = DISPLAY_FLAGS_DE_HIGH, 1351 }; 1352 1353 static const struct panel_desc chefree_ch101olhlwh_002 = { 1354 .timings = &chefree_ch101olhlwh_002_timing, 1355 .num_timings = 1, 1356 .bpc = 8, 1357 .size = { 1358 .width = 217, 1359 .height = 135, 1360 }, 1361 .delay = { 1362 .enable = 200, 1363 .disable = 200, 1364 }, 1365 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1366 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1367 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1368 }; 1369 1370 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1371 .clock = 66770, 1372 .hdisplay = 800, 1373 .hsync_start = 800 + 49, 1374 .hsync_end = 800 + 49 + 33, 1375 .htotal = 800 + 49 + 33 + 17, 1376 .vdisplay = 1280, 1377 .vsync_start = 1280 + 1, 1378 .vsync_end = 1280 + 1 + 7, 1379 .vtotal = 1280 + 1 + 7 + 15, 1380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1381 }; 1382 1383 static const struct panel_desc chunghwa_claa070wp03xg = { 1384 .modes = &chunghwa_claa070wp03xg_mode, 1385 .num_modes = 1, 1386 .bpc = 6, 1387 .size = { 1388 .width = 94, 1389 .height = 150, 1390 }, 1391 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1392 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1393 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1394 }; 1395 1396 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1397 .clock = 72070, 1398 .hdisplay = 1366, 1399 .hsync_start = 1366 + 58, 1400 .hsync_end = 1366 + 58 + 58, 1401 .htotal = 1366 + 58 + 58 + 58, 1402 .vdisplay = 768, 1403 .vsync_start = 768 + 4, 1404 .vsync_end = 768 + 4 + 4, 1405 .vtotal = 768 + 4 + 4 + 4, 1406 }; 1407 1408 static const struct panel_desc chunghwa_claa101wa01a = { 1409 .modes = &chunghwa_claa101wa01a_mode, 1410 .num_modes = 1, 1411 .bpc = 6, 1412 .size = { 1413 .width = 220, 1414 .height = 120, 1415 }, 1416 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1417 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1418 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1419 }; 1420 1421 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1422 .clock = 69300, 1423 .hdisplay = 1366, 1424 .hsync_start = 1366 + 48, 1425 .hsync_end = 1366 + 48 + 32, 1426 .htotal = 1366 + 48 + 32 + 20, 1427 .vdisplay = 768, 1428 .vsync_start = 768 + 16, 1429 .vsync_end = 768 + 16 + 8, 1430 .vtotal = 768 + 16 + 8 + 16, 1431 }; 1432 1433 static const struct panel_desc chunghwa_claa101wb01 = { 1434 .modes = &chunghwa_claa101wb01_mode, 1435 .num_modes = 1, 1436 .bpc = 6, 1437 .size = { 1438 .width = 223, 1439 .height = 125, 1440 }, 1441 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1443 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1444 }; 1445 1446 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1447 .pixelclock = { 5000000, 9000000, 12000000 }, 1448 .hactive = { 480, 480, 480 }, 1449 .hfront_porch = { 12, 12, 12 }, 1450 .hback_porch = { 12, 12, 12 }, 1451 .hsync_len = { 21, 21, 21 }, 1452 .vactive = { 272, 272, 272 }, 1453 .vfront_porch = { 4, 4, 4 }, 1454 .vback_porch = { 4, 4, 4 }, 1455 .vsync_len = { 8, 8, 8 }, 1456 }; 1457 1458 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1459 .timings = &dataimage_fg040346dsswbg04_timing, 1460 .num_timings = 1, 1461 .bpc = 8, 1462 .size = { 1463 .width = 95, 1464 .height = 54, 1465 }, 1466 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1467 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1468 .connector_type = DRM_MODE_CONNECTOR_DPI, 1469 }; 1470 1471 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1472 .pixelclock = { 68900000, 71110000, 73400000 }, 1473 .hactive = { 1280, 1280, 1280 }, 1474 .vactive = { 800, 800, 800 }, 1475 .hback_porch = { 100, 100, 100 }, 1476 .hfront_porch = { 100, 100, 100 }, 1477 .vback_porch = { 5, 5, 5 }, 1478 .vfront_porch = { 5, 5, 5 }, 1479 .hsync_len = { 24, 24, 24 }, 1480 .vsync_len = { 3, 3, 3 }, 1481 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1482 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1483 }; 1484 1485 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1486 .timings = &dataimage_fg1001l0dsswmg01_timing, 1487 .num_timings = 1, 1488 .bpc = 8, 1489 .size = { 1490 .width = 217, 1491 .height = 136, 1492 }, 1493 }; 1494 1495 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1496 .clock = 33260, 1497 .hdisplay = 800, 1498 .hsync_start = 800 + 40, 1499 .hsync_end = 800 + 40 + 128, 1500 .htotal = 800 + 40 + 128 + 88, 1501 .vdisplay = 480, 1502 .vsync_start = 480 + 10, 1503 .vsync_end = 480 + 10 + 2, 1504 .vtotal = 480 + 10 + 2 + 33, 1505 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1506 }; 1507 1508 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1509 .modes = &dataimage_scf0700c48ggu18_mode, 1510 .num_modes = 1, 1511 .bpc = 8, 1512 .size = { 1513 .width = 152, 1514 .height = 91, 1515 }, 1516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1518 }; 1519 1520 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1521 .pixelclock = { 45000000, 51200000, 57000000 }, 1522 .hactive = { 1024, 1024, 1024 }, 1523 .hfront_porch = { 100, 106, 113 }, 1524 .hback_porch = { 100, 106, 113 }, 1525 .hsync_len = { 100, 108, 114 }, 1526 .vactive = { 600, 600, 600 }, 1527 .vfront_porch = { 8, 11, 15 }, 1528 .vback_porch = { 8, 11, 15 }, 1529 .vsync_len = { 9, 13, 15 }, 1530 .flags = DISPLAY_FLAGS_DE_HIGH, 1531 }; 1532 1533 static const struct panel_desc dlc_dlc0700yzg_1 = { 1534 .timings = &dlc_dlc0700yzg_1_timing, 1535 .num_timings = 1, 1536 .bpc = 6, 1537 .size = { 1538 .width = 154, 1539 .height = 86, 1540 }, 1541 .delay = { 1542 .prepare = 30, 1543 .enable = 200, 1544 .disable = 200, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1548 }; 1549 1550 static const struct display_timing dlc_dlc1010gig_timing = { 1551 .pixelclock = { 68900000, 71100000, 73400000 }, 1552 .hactive = { 1280, 1280, 1280 }, 1553 .hfront_porch = { 43, 53, 63 }, 1554 .hback_porch = { 43, 53, 63 }, 1555 .hsync_len = { 44, 54, 64 }, 1556 .vactive = { 800, 800, 800 }, 1557 .vfront_porch = { 5, 8, 11 }, 1558 .vback_porch = { 5, 8, 11 }, 1559 .vsync_len = { 5, 7, 11 }, 1560 .flags = DISPLAY_FLAGS_DE_HIGH, 1561 }; 1562 1563 static const struct panel_desc dlc_dlc1010gig = { 1564 .timings = &dlc_dlc1010gig_timing, 1565 .num_timings = 1, 1566 .bpc = 8, 1567 .size = { 1568 .width = 216, 1569 .height = 135, 1570 }, 1571 .delay = { 1572 .prepare = 60, 1573 .enable = 150, 1574 .disable = 100, 1575 .unprepare = 60, 1576 }, 1577 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1579 }; 1580 1581 static const struct drm_display_mode edt_et035012dm6_mode = { 1582 .clock = 6500, 1583 .hdisplay = 320, 1584 .hsync_start = 320 + 20, 1585 .hsync_end = 320 + 20 + 30, 1586 .htotal = 320 + 20 + 68, 1587 .vdisplay = 240, 1588 .vsync_start = 240 + 4, 1589 .vsync_end = 240 + 4 + 4, 1590 .vtotal = 240 + 4 + 4 + 14, 1591 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1592 }; 1593 1594 static const struct panel_desc edt_et035012dm6 = { 1595 .modes = &edt_et035012dm6_mode, 1596 .num_modes = 1, 1597 .bpc = 8, 1598 .size = { 1599 .width = 70, 1600 .height = 52, 1601 }, 1602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1603 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1604 }; 1605 1606 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1607 .clock = 6520, 1608 .hdisplay = 320, 1609 .hsync_start = 320 + 20, 1610 .hsync_end = 320 + 20 + 68, 1611 .htotal = 320 + 20 + 68, 1612 .vdisplay = 240, 1613 .vsync_start = 240 + 4, 1614 .vsync_end = 240 + 4 + 18, 1615 .vtotal = 240 + 4 + 18, 1616 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1617 }; 1618 1619 static const struct panel_desc edt_etm0350g0dh6 = { 1620 .modes = &edt_etm0350g0dh6_mode, 1621 .num_modes = 1, 1622 .bpc = 6, 1623 .size = { 1624 .width = 70, 1625 .height = 53, 1626 }, 1627 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1628 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1629 .connector_type = DRM_MODE_CONNECTOR_DPI, 1630 }; 1631 1632 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1633 .clock = 10870, 1634 .hdisplay = 480, 1635 .hsync_start = 480 + 8, 1636 .hsync_end = 480 + 8 + 4, 1637 .htotal = 480 + 8 + 4 + 41, 1638 1639 /* 1640 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1641 * fb_align 1642 */ 1643 1644 .vdisplay = 288, 1645 .vsync_start = 288 + 2, 1646 .vsync_end = 288 + 2 + 4, 1647 .vtotal = 288 + 2 + 4 + 10, 1648 }; 1649 1650 static const struct panel_desc edt_etm043080dh6gp = { 1651 .modes = &edt_etm043080dh6gp_mode, 1652 .num_modes = 1, 1653 .bpc = 8, 1654 .size = { 1655 .width = 100, 1656 .height = 65, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1659 .connector_type = DRM_MODE_CONNECTOR_DPI, 1660 }; 1661 1662 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1663 .clock = 9000, 1664 .hdisplay = 480, 1665 .hsync_start = 480 + 2, 1666 .hsync_end = 480 + 2 + 41, 1667 .htotal = 480 + 2 + 41 + 2, 1668 .vdisplay = 272, 1669 .vsync_start = 272 + 2, 1670 .vsync_end = 272 + 2 + 10, 1671 .vtotal = 272 + 2 + 10 + 2, 1672 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1673 }; 1674 1675 static const struct panel_desc edt_etm0430g0dh6 = { 1676 .modes = &edt_etm0430g0dh6_mode, 1677 .num_modes = 1, 1678 .bpc = 6, 1679 .size = { 1680 .width = 95, 1681 .height = 54, 1682 }, 1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1685 .connector_type = DRM_MODE_CONNECTOR_DPI, 1686 }; 1687 1688 static const struct drm_display_mode edt_et057090dhu_mode = { 1689 .clock = 25175, 1690 .hdisplay = 640, 1691 .hsync_start = 640 + 16, 1692 .hsync_end = 640 + 16 + 30, 1693 .htotal = 640 + 16 + 30 + 114, 1694 .vdisplay = 480, 1695 .vsync_start = 480 + 10, 1696 .vsync_end = 480 + 10 + 3, 1697 .vtotal = 480 + 10 + 3 + 32, 1698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1699 }; 1700 1701 static const struct panel_desc edt_et057090dhu = { 1702 .modes = &edt_et057090dhu_mode, 1703 .num_modes = 1, 1704 .bpc = 6, 1705 .size = { 1706 .width = 115, 1707 .height = 86, 1708 }, 1709 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1710 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1711 .connector_type = DRM_MODE_CONNECTOR_DPI, 1712 }; 1713 1714 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1715 .clock = 33260, 1716 .hdisplay = 800, 1717 .hsync_start = 800 + 40, 1718 .hsync_end = 800 + 40 + 128, 1719 .htotal = 800 + 40 + 128 + 88, 1720 .vdisplay = 480, 1721 .vsync_start = 480 + 10, 1722 .vsync_end = 480 + 10 + 2, 1723 .vtotal = 480 + 10 + 2 + 33, 1724 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1725 }; 1726 1727 static const struct panel_desc edt_etm0700g0dh6 = { 1728 .modes = &edt_etm0700g0dh6_mode, 1729 .num_modes = 1, 1730 .bpc = 6, 1731 .size = { 1732 .width = 152, 1733 .height = 91, 1734 }, 1735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1736 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1737 .connector_type = DRM_MODE_CONNECTOR_DPI, 1738 }; 1739 1740 static const struct panel_desc edt_etm0700g0bdh6 = { 1741 .modes = &edt_etm0700g0dh6_mode, 1742 .num_modes = 1, 1743 .bpc = 6, 1744 .size = { 1745 .width = 152, 1746 .height = 91, 1747 }, 1748 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1750 .connector_type = DRM_MODE_CONNECTOR_DPI, 1751 }; 1752 1753 static const struct display_timing edt_etml0700y5dha_timing = { 1754 .pixelclock = { 40800000, 51200000, 67200000 }, 1755 .hactive = { 1024, 1024, 1024 }, 1756 .hfront_porch = { 30, 106, 125 }, 1757 .hback_porch = { 30, 106, 125 }, 1758 .hsync_len = { 30, 108, 126 }, 1759 .vactive = { 600, 600, 600 }, 1760 .vfront_porch = { 3, 12, 67}, 1761 .vback_porch = { 3, 12, 67 }, 1762 .vsync_len = { 4, 11, 66 }, 1763 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1764 DISPLAY_FLAGS_DE_HIGH, 1765 }; 1766 1767 static const struct panel_desc edt_etml0700y5dha = { 1768 .timings = &edt_etml0700y5dha_timing, 1769 .num_timings = 1, 1770 .bpc = 8, 1771 .size = { 1772 .width = 155, 1773 .height = 86, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1776 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1777 }; 1778 1779 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1780 .clock = 25175, 1781 .hdisplay = 640, 1782 .hsync_start = 640, 1783 .hsync_end = 640 + 16, 1784 .htotal = 640 + 16 + 30 + 114, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 3, 1788 .vtotal = 480 + 10 + 3 + 35, 1789 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1790 }; 1791 1792 static const struct panel_desc edt_etmv570g2dhu = { 1793 .modes = &edt_etmv570g2dhu_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 115, 1798 .height = 86, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct display_timing eink_vb3300_kca_timing = { 1806 .pixelclock = { 40000000, 40000000, 40000000 }, 1807 .hactive = { 334, 334, 334 }, 1808 .hfront_porch = { 1, 1, 1 }, 1809 .hback_porch = { 1, 1, 1 }, 1810 .hsync_len = { 1, 1, 1 }, 1811 .vactive = { 1405, 1405, 1405 }, 1812 .vfront_porch = { 1, 1, 1 }, 1813 .vback_porch = { 1, 1, 1 }, 1814 .vsync_len = { 1, 1, 1 }, 1815 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1816 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1817 }; 1818 1819 static const struct panel_desc eink_vb3300_kca = { 1820 .timings = &eink_vb3300_kca_timing, 1821 .num_timings = 1, 1822 .bpc = 6, 1823 .size = { 1824 .width = 157, 1825 .height = 209, 1826 }, 1827 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1829 .connector_type = DRM_MODE_CONNECTOR_DPI, 1830 }; 1831 1832 static const struct display_timing evervision_vgg804821_timing = { 1833 .pixelclock = { 27600000, 33300000, 50000000 }, 1834 .hactive = { 800, 800, 800 }, 1835 .hfront_porch = { 40, 66, 70 }, 1836 .hback_porch = { 40, 67, 70 }, 1837 .hsync_len = { 40, 67, 70 }, 1838 .vactive = { 480, 480, 480 }, 1839 .vfront_porch = { 6, 10, 10 }, 1840 .vback_porch = { 7, 11, 11 }, 1841 .vsync_len = { 7, 11, 11 }, 1842 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1843 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1844 DISPLAY_FLAGS_SYNC_NEGEDGE, 1845 }; 1846 1847 static const struct panel_desc evervision_vgg804821 = { 1848 .timings = &evervision_vgg804821_timing, 1849 .num_timings = 1, 1850 .bpc = 8, 1851 .size = { 1852 .width = 108, 1853 .height = 64, 1854 }, 1855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1856 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1857 }; 1858 1859 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1860 .clock = 32260, 1861 .hdisplay = 800, 1862 .hsync_start = 800 + 168, 1863 .hsync_end = 800 + 168 + 64, 1864 .htotal = 800 + 168 + 64 + 88, 1865 .vdisplay = 480, 1866 .vsync_start = 480 + 37, 1867 .vsync_end = 480 + 37 + 2, 1868 .vtotal = 480 + 37 + 2 + 8, 1869 }; 1870 1871 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1872 .modes = &foxlink_fl500wvr00_a0t_mode, 1873 .num_modes = 1, 1874 .bpc = 8, 1875 .size = { 1876 .width = 108, 1877 .height = 65, 1878 }, 1879 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1880 }; 1881 1882 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1883 { /* 60 Hz */ 1884 .clock = 6000, 1885 .hdisplay = 320, 1886 .hsync_start = 320 + 44, 1887 .hsync_end = 320 + 44 + 16, 1888 .htotal = 320 + 44 + 16 + 20, 1889 .vdisplay = 240, 1890 .vsync_start = 240 + 2, 1891 .vsync_end = 240 + 2 + 6, 1892 .vtotal = 240 + 2 + 6 + 2, 1893 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1894 }, 1895 { /* 50 Hz */ 1896 .clock = 5400, 1897 .hdisplay = 320, 1898 .hsync_start = 320 + 56, 1899 .hsync_end = 320 + 56 + 16, 1900 .htotal = 320 + 56 + 16 + 40, 1901 .vdisplay = 240, 1902 .vsync_start = 240 + 2, 1903 .vsync_end = 240 + 2 + 6, 1904 .vtotal = 240 + 2 + 6 + 2, 1905 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1906 }, 1907 }; 1908 1909 static const struct panel_desc frida_frd350h54004 = { 1910 .modes = frida_frd350h54004_modes, 1911 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1912 .bpc = 8, 1913 .size = { 1914 .width = 77, 1915 .height = 64, 1916 }, 1917 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1919 .connector_type = DRM_MODE_CONNECTOR_DPI, 1920 }; 1921 1922 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1923 .clock = 67185, 1924 .hdisplay = 800, 1925 .hsync_start = 800 + 20, 1926 .hsync_end = 800 + 20 + 24, 1927 .htotal = 800 + 20 + 24 + 20, 1928 .vdisplay = 1280, 1929 .vsync_start = 1280 + 4, 1930 .vsync_end = 1280 + 4 + 8, 1931 .vtotal = 1280 + 4 + 8 + 4, 1932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1933 }; 1934 1935 static const struct panel_desc friendlyarm_hd702e = { 1936 .modes = &friendlyarm_hd702e_mode, 1937 .num_modes = 1, 1938 .size = { 1939 .width = 94, 1940 .height = 151, 1941 }, 1942 }; 1943 1944 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1945 .clock = 9000, 1946 .hdisplay = 480, 1947 .hsync_start = 480 + 5, 1948 .hsync_end = 480 + 5 + 1, 1949 .htotal = 480 + 5 + 1 + 40, 1950 .vdisplay = 272, 1951 .vsync_start = 272 + 8, 1952 .vsync_end = 272 + 8 + 1, 1953 .vtotal = 272 + 8 + 1 + 8, 1954 }; 1955 1956 static const struct panel_desc giantplus_gpg482739qs5 = { 1957 .modes = &giantplus_gpg482739qs5_mode, 1958 .num_modes = 1, 1959 .bpc = 8, 1960 .size = { 1961 .width = 95, 1962 .height = 54, 1963 }, 1964 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1965 }; 1966 1967 static const struct display_timing giantplus_gpm940b0_timing = { 1968 .pixelclock = { 13500000, 27000000, 27500000 }, 1969 .hactive = { 320, 320, 320 }, 1970 .hfront_porch = { 14, 686, 718 }, 1971 .hback_porch = { 50, 70, 255 }, 1972 .hsync_len = { 1, 1, 1 }, 1973 .vactive = { 240, 240, 240 }, 1974 .vfront_porch = { 1, 1, 179 }, 1975 .vback_porch = { 1, 21, 31 }, 1976 .vsync_len = { 1, 1, 6 }, 1977 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1978 }; 1979 1980 static const struct panel_desc giantplus_gpm940b0 = { 1981 .timings = &giantplus_gpm940b0_timing, 1982 .num_timings = 1, 1983 .bpc = 8, 1984 .size = { 1985 .width = 60, 1986 .height = 45, 1987 }, 1988 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1989 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1990 }; 1991 1992 static const struct display_timing hannstar_hsd070pww1_timing = { 1993 .pixelclock = { 64300000, 71100000, 82000000 }, 1994 .hactive = { 1280, 1280, 1280 }, 1995 .hfront_porch = { 1, 1, 10 }, 1996 .hback_porch = { 1, 1, 10 }, 1997 /* 1998 * According to the data sheet, the minimum horizontal blanking interval 1999 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2000 * minimum working horizontal blanking interval to be 60 clocks. 2001 */ 2002 .hsync_len = { 58, 158, 661 }, 2003 .vactive = { 800, 800, 800 }, 2004 .vfront_porch = { 1, 1, 10 }, 2005 .vback_porch = { 1, 1, 10 }, 2006 .vsync_len = { 1, 21, 203 }, 2007 .flags = DISPLAY_FLAGS_DE_HIGH, 2008 }; 2009 2010 static const struct panel_desc hannstar_hsd070pww1 = { 2011 .timings = &hannstar_hsd070pww1_timing, 2012 .num_timings = 1, 2013 .bpc = 6, 2014 .size = { 2015 .width = 151, 2016 .height = 94, 2017 }, 2018 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2019 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2020 }; 2021 2022 static const struct display_timing hannstar_hsd100pxn1_timing = { 2023 .pixelclock = { 55000000, 65000000, 75000000 }, 2024 .hactive = { 1024, 1024, 1024 }, 2025 .hfront_porch = { 40, 40, 40 }, 2026 .hback_porch = { 220, 220, 220 }, 2027 .hsync_len = { 20, 60, 100 }, 2028 .vactive = { 768, 768, 768 }, 2029 .vfront_porch = { 7, 7, 7 }, 2030 .vback_porch = { 21, 21, 21 }, 2031 .vsync_len = { 10, 10, 10 }, 2032 .flags = DISPLAY_FLAGS_DE_HIGH, 2033 }; 2034 2035 static const struct panel_desc hannstar_hsd100pxn1 = { 2036 .timings = &hannstar_hsd100pxn1_timing, 2037 .num_timings = 1, 2038 .bpc = 6, 2039 .size = { 2040 .width = 203, 2041 .height = 152, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2044 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2045 }; 2046 2047 static const struct display_timing hannstar_hsd101pww2_timing = { 2048 .pixelclock = { 64300000, 71100000, 82000000 }, 2049 .hactive = { 1280, 1280, 1280 }, 2050 .hfront_porch = { 1, 1, 10 }, 2051 .hback_porch = { 1, 1, 10 }, 2052 .hsync_len = { 58, 158, 661 }, 2053 .vactive = { 800, 800, 800 }, 2054 .vfront_porch = { 1, 1, 10 }, 2055 .vback_porch = { 1, 1, 10 }, 2056 .vsync_len = { 1, 21, 203 }, 2057 .flags = DISPLAY_FLAGS_DE_HIGH, 2058 }; 2059 2060 static const struct panel_desc hannstar_hsd101pww2 = { 2061 .timings = &hannstar_hsd101pww2_timing, 2062 .num_timings = 1, 2063 .bpc = 8, 2064 .size = { 2065 .width = 217, 2066 .height = 136, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2069 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2070 }; 2071 2072 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2073 .clock = 33333, 2074 .hdisplay = 800, 2075 .hsync_start = 800 + 85, 2076 .hsync_end = 800 + 85 + 86, 2077 .htotal = 800 + 85 + 86 + 85, 2078 .vdisplay = 480, 2079 .vsync_start = 480 + 16, 2080 .vsync_end = 480 + 16 + 13, 2081 .vtotal = 480 + 16 + 13 + 16, 2082 }; 2083 2084 static const struct panel_desc hitachi_tx23d38vm0caa = { 2085 .modes = &hitachi_tx23d38vm0caa_mode, 2086 .num_modes = 1, 2087 .bpc = 6, 2088 .size = { 2089 .width = 195, 2090 .height = 117, 2091 }, 2092 .delay = { 2093 .enable = 160, 2094 .disable = 160, 2095 }, 2096 }; 2097 2098 static const struct drm_display_mode innolux_at043tn24_mode = { 2099 .clock = 9000, 2100 .hdisplay = 480, 2101 .hsync_start = 480 + 2, 2102 .hsync_end = 480 + 2 + 41, 2103 .htotal = 480 + 2 + 41 + 2, 2104 .vdisplay = 272, 2105 .vsync_start = 272 + 2, 2106 .vsync_end = 272 + 2 + 10, 2107 .vtotal = 272 + 2 + 10 + 2, 2108 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2109 }; 2110 2111 static const struct panel_desc innolux_at043tn24 = { 2112 .modes = &innolux_at043tn24_mode, 2113 .num_modes = 1, 2114 .bpc = 8, 2115 .size = { 2116 .width = 95, 2117 .height = 54, 2118 }, 2119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2120 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2121 }; 2122 2123 static const struct drm_display_mode innolux_at070tn92_mode = { 2124 .clock = 33333, 2125 .hdisplay = 800, 2126 .hsync_start = 800 + 210, 2127 .hsync_end = 800 + 210 + 20, 2128 .htotal = 800 + 210 + 20 + 46, 2129 .vdisplay = 480, 2130 .vsync_start = 480 + 22, 2131 .vsync_end = 480 + 22 + 10, 2132 .vtotal = 480 + 22 + 23 + 10, 2133 }; 2134 2135 static const struct panel_desc innolux_at070tn92 = { 2136 .modes = &innolux_at070tn92_mode, 2137 .num_modes = 1, 2138 .size = { 2139 .width = 154, 2140 .height = 86, 2141 }, 2142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2143 }; 2144 2145 static const struct display_timing innolux_g070y2_l01_timing = { 2146 .pixelclock = { 28000000, 29500000, 32000000 }, 2147 .hactive = { 800, 800, 800 }, 2148 .hfront_porch = { 61, 91, 141 }, 2149 .hback_porch = { 60, 90, 140 }, 2150 .hsync_len = { 12, 12, 12 }, 2151 .vactive = { 480, 480, 480 }, 2152 .vfront_porch = { 4, 9, 30 }, 2153 .vback_porch = { 4, 8, 28 }, 2154 .vsync_len = { 2, 2, 2 }, 2155 .flags = DISPLAY_FLAGS_DE_HIGH, 2156 }; 2157 2158 static const struct panel_desc innolux_g070y2_l01 = { 2159 .timings = &innolux_g070y2_l01_timing, 2160 .num_timings = 1, 2161 .bpc = 8, 2162 .size = { 2163 .width = 152, 2164 .height = 91, 2165 }, 2166 .delay = { 2167 .prepare = 10, 2168 .enable = 100, 2169 .disable = 100, 2170 .unprepare = 800, 2171 }, 2172 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2173 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2174 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2175 }; 2176 2177 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2178 .clock = 33333, 2179 .hdisplay = 800, 2180 .hsync_start = 800 + 210, 2181 .hsync_end = 800 + 210 + 20, 2182 .htotal = 800 + 210 + 20 + 46, 2183 .vdisplay = 480, 2184 .vsync_start = 480 + 22, 2185 .vsync_end = 480 + 22 + 10, 2186 .vtotal = 480 + 22 + 23 + 10, 2187 }; 2188 2189 static const struct panel_desc innolux_g070y2_t02 = { 2190 .modes = &innolux_g070y2_t02_mode, 2191 .num_modes = 1, 2192 .bpc = 8, 2193 .size = { 2194 .width = 152, 2195 .height = 92, 2196 }, 2197 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2198 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2199 .connector_type = DRM_MODE_CONNECTOR_DPI, 2200 }; 2201 2202 static const struct display_timing innolux_g101ice_l01_timing = { 2203 .pixelclock = { 60400000, 71100000, 74700000 }, 2204 .hactive = { 1280, 1280, 1280 }, 2205 .hfront_porch = { 41, 80, 100 }, 2206 .hback_porch = { 40, 79, 99 }, 2207 .hsync_len = { 1, 1, 1 }, 2208 .vactive = { 800, 800, 800 }, 2209 .vfront_porch = { 5, 11, 14 }, 2210 .vback_porch = { 4, 11, 14 }, 2211 .vsync_len = { 1, 1, 1 }, 2212 .flags = DISPLAY_FLAGS_DE_HIGH, 2213 }; 2214 2215 static const struct panel_desc innolux_g101ice_l01 = { 2216 .timings = &innolux_g101ice_l01_timing, 2217 .num_timings = 1, 2218 .bpc = 8, 2219 .size = { 2220 .width = 217, 2221 .height = 135, 2222 }, 2223 .delay = { 2224 .enable = 200, 2225 .disable = 200, 2226 }, 2227 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2228 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2229 }; 2230 2231 static const struct display_timing innolux_g121i1_l01_timing = { 2232 .pixelclock = { 67450000, 71000000, 74550000 }, 2233 .hactive = { 1280, 1280, 1280 }, 2234 .hfront_porch = { 40, 80, 160 }, 2235 .hback_porch = { 39, 79, 159 }, 2236 .hsync_len = { 1, 1, 1 }, 2237 .vactive = { 800, 800, 800 }, 2238 .vfront_porch = { 5, 11, 100 }, 2239 .vback_porch = { 4, 11, 99 }, 2240 .vsync_len = { 1, 1, 1 }, 2241 }; 2242 2243 static const struct panel_desc innolux_g121i1_l01 = { 2244 .timings = &innolux_g121i1_l01_timing, 2245 .num_timings = 1, 2246 .bpc = 6, 2247 .size = { 2248 .width = 261, 2249 .height = 163, 2250 }, 2251 .delay = { 2252 .enable = 200, 2253 .disable = 20, 2254 }, 2255 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2256 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2257 }; 2258 2259 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2260 .clock = 65000, 2261 .hdisplay = 1024, 2262 .hsync_start = 1024 + 0, 2263 .hsync_end = 1024 + 1, 2264 .htotal = 1024 + 0 + 1 + 320, 2265 .vdisplay = 768, 2266 .vsync_start = 768 + 38, 2267 .vsync_end = 768 + 38 + 1, 2268 .vtotal = 768 + 38 + 1 + 0, 2269 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2270 }; 2271 2272 static const struct panel_desc innolux_g121x1_l03 = { 2273 .modes = &innolux_g121x1_l03_mode, 2274 .num_modes = 1, 2275 .bpc = 6, 2276 .size = { 2277 .width = 246, 2278 .height = 185, 2279 }, 2280 .delay = { 2281 .enable = 200, 2282 .unprepare = 200, 2283 .disable = 400, 2284 }, 2285 }; 2286 2287 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2288 .clock = 69300, 2289 .hdisplay = 1366, 2290 .hsync_start = 1366 + 16, 2291 .hsync_end = 1366 + 16 + 34, 2292 .htotal = 1366 + 16 + 34 + 50, 2293 .vdisplay = 768, 2294 .vsync_start = 768 + 2, 2295 .vsync_end = 768 + 2 + 6, 2296 .vtotal = 768 + 2 + 6 + 12, 2297 }; 2298 2299 static const struct panel_desc innolux_n156bge_l21 = { 2300 .modes = &innolux_n156bge_l21_mode, 2301 .num_modes = 1, 2302 .bpc = 6, 2303 .size = { 2304 .width = 344, 2305 .height = 193, 2306 }, 2307 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2308 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2309 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2310 }; 2311 2312 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2313 .clock = 51501, 2314 .hdisplay = 1024, 2315 .hsync_start = 1024 + 128, 2316 .hsync_end = 1024 + 128 + 64, 2317 .htotal = 1024 + 128 + 64 + 128, 2318 .vdisplay = 600, 2319 .vsync_start = 600 + 16, 2320 .vsync_end = 600 + 16 + 4, 2321 .vtotal = 600 + 16 + 4 + 16, 2322 }; 2323 2324 static const struct panel_desc innolux_zj070na_01p = { 2325 .modes = &innolux_zj070na_01p_mode, 2326 .num_modes = 1, 2327 .bpc = 6, 2328 .size = { 2329 .width = 154, 2330 .height = 90, 2331 }, 2332 }; 2333 2334 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2335 .pixelclock = { 5580000, 5850000, 6200000 }, 2336 .hactive = { 320, 320, 320 }, 2337 .hfront_porch = { 30, 30, 30 }, 2338 .hback_porch = { 30, 30, 30 }, 2339 .hsync_len = { 1, 5, 17 }, 2340 .vactive = { 240, 240, 240 }, 2341 .vfront_porch = { 6, 6, 6 }, 2342 .vback_porch = { 5, 5, 5 }, 2343 .vsync_len = { 1, 2, 11 }, 2344 .flags = DISPLAY_FLAGS_DE_HIGH, 2345 }; 2346 2347 static const struct panel_desc koe_tx14d24vm1bpa = { 2348 .timings = &koe_tx14d24vm1bpa_timing, 2349 .num_timings = 1, 2350 .bpc = 6, 2351 .size = { 2352 .width = 115, 2353 .height = 86, 2354 }, 2355 }; 2356 2357 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2358 .pixelclock = { 151820000, 156720000, 159780000 }, 2359 .hactive = { 1920, 1920, 1920 }, 2360 .hfront_porch = { 105, 130, 142 }, 2361 .hback_porch = { 45, 70, 82 }, 2362 .hsync_len = { 30, 30, 30 }, 2363 .vactive = { 1200, 1200, 1200}, 2364 .vfront_porch = { 3, 5, 10 }, 2365 .vback_porch = { 2, 5, 10 }, 2366 .vsync_len = { 5, 5, 5 }, 2367 }; 2368 2369 static const struct panel_desc koe_tx26d202vm0bwa = { 2370 .timings = &koe_tx26d202vm0bwa_timing, 2371 .num_timings = 1, 2372 .bpc = 8, 2373 .size = { 2374 .width = 217, 2375 .height = 136, 2376 }, 2377 .delay = { 2378 .prepare = 1000, 2379 .enable = 1000, 2380 .unprepare = 1000, 2381 .disable = 1000, 2382 }, 2383 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2384 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2386 }; 2387 2388 static const struct display_timing koe_tx31d200vm0baa_timing = { 2389 .pixelclock = { 39600000, 43200000, 48000000 }, 2390 .hactive = { 1280, 1280, 1280 }, 2391 .hfront_porch = { 16, 36, 56 }, 2392 .hback_porch = { 16, 36, 56 }, 2393 .hsync_len = { 8, 8, 8 }, 2394 .vactive = { 480, 480, 480 }, 2395 .vfront_porch = { 6, 21, 33 }, 2396 .vback_porch = { 6, 21, 33 }, 2397 .vsync_len = { 8, 8, 8 }, 2398 .flags = DISPLAY_FLAGS_DE_HIGH, 2399 }; 2400 2401 static const struct panel_desc koe_tx31d200vm0baa = { 2402 .timings = &koe_tx31d200vm0baa_timing, 2403 .num_timings = 1, 2404 .bpc = 6, 2405 .size = { 2406 .width = 292, 2407 .height = 109, 2408 }, 2409 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2410 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2411 }; 2412 2413 static const struct display_timing kyo_tcg121xglp_timing = { 2414 .pixelclock = { 52000000, 65000000, 71000000 }, 2415 .hactive = { 1024, 1024, 1024 }, 2416 .hfront_porch = { 2, 2, 2 }, 2417 .hback_porch = { 2, 2, 2 }, 2418 .hsync_len = { 86, 124, 244 }, 2419 .vactive = { 768, 768, 768 }, 2420 .vfront_porch = { 2, 2, 2 }, 2421 .vback_porch = { 2, 2, 2 }, 2422 .vsync_len = { 6, 34, 73 }, 2423 .flags = DISPLAY_FLAGS_DE_HIGH, 2424 }; 2425 2426 static const struct panel_desc kyo_tcg121xglp = { 2427 .timings = &kyo_tcg121xglp_timing, 2428 .num_timings = 1, 2429 .bpc = 8, 2430 .size = { 2431 .width = 246, 2432 .height = 184, 2433 }, 2434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2435 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2436 }; 2437 2438 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2439 .clock = 7000, 2440 .hdisplay = 320, 2441 .hsync_start = 320 + 20, 2442 .hsync_end = 320 + 20 + 30, 2443 .htotal = 320 + 20 + 30 + 38, 2444 .vdisplay = 240, 2445 .vsync_start = 240 + 4, 2446 .vsync_end = 240 + 4 + 3, 2447 .vtotal = 240 + 4 + 3 + 15, 2448 }; 2449 2450 static const struct panel_desc lemaker_bl035_rgb_002 = { 2451 .modes = &lemaker_bl035_rgb_002_mode, 2452 .num_modes = 1, 2453 .size = { 2454 .width = 70, 2455 .height = 52, 2456 }, 2457 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2458 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2459 }; 2460 2461 static const struct drm_display_mode lg_lb070wv8_mode = { 2462 .clock = 33246, 2463 .hdisplay = 800, 2464 .hsync_start = 800 + 88, 2465 .hsync_end = 800 + 88 + 80, 2466 .htotal = 800 + 88 + 80 + 88, 2467 .vdisplay = 480, 2468 .vsync_start = 480 + 10, 2469 .vsync_end = 480 + 10 + 25, 2470 .vtotal = 480 + 10 + 25 + 10, 2471 }; 2472 2473 static const struct panel_desc lg_lb070wv8 = { 2474 .modes = &lg_lb070wv8_mode, 2475 .num_modes = 1, 2476 .bpc = 8, 2477 .size = { 2478 .width = 151, 2479 .height = 91, 2480 }, 2481 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2482 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2483 }; 2484 2485 static const struct display_timing logictechno_lt161010_2nh_timing = { 2486 .pixelclock = { 26400000, 33300000, 46800000 }, 2487 .hactive = { 800, 800, 800 }, 2488 .hfront_porch = { 16, 210, 354 }, 2489 .hback_porch = { 46, 46, 46 }, 2490 .hsync_len = { 1, 20, 40 }, 2491 .vactive = { 480, 480, 480 }, 2492 .vfront_porch = { 7, 22, 147 }, 2493 .vback_porch = { 23, 23, 23 }, 2494 .vsync_len = { 1, 10, 20 }, 2495 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2496 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2497 DISPLAY_FLAGS_SYNC_POSEDGE, 2498 }; 2499 2500 static const struct panel_desc logictechno_lt161010_2nh = { 2501 .timings = &logictechno_lt161010_2nh_timing, 2502 .num_timings = 1, 2503 .size = { 2504 .width = 154, 2505 .height = 86, 2506 }, 2507 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2508 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2509 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2510 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2511 .connector_type = DRM_MODE_CONNECTOR_DPI, 2512 }; 2513 2514 static const struct display_timing logictechno_lt170410_2whc_timing = { 2515 .pixelclock = { 68900000, 71100000, 73400000 }, 2516 .hactive = { 1280, 1280, 1280 }, 2517 .hfront_porch = { 23, 60, 71 }, 2518 .hback_porch = { 23, 60, 71 }, 2519 .hsync_len = { 15, 40, 47 }, 2520 .vactive = { 800, 800, 800 }, 2521 .vfront_porch = { 5, 7, 10 }, 2522 .vback_porch = { 5, 7, 10 }, 2523 .vsync_len = { 6, 9, 12 }, 2524 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2525 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2526 DISPLAY_FLAGS_SYNC_POSEDGE, 2527 }; 2528 2529 static const struct panel_desc logictechno_lt170410_2whc = { 2530 .timings = &logictechno_lt170410_2whc_timing, 2531 .num_timings = 1, 2532 .size = { 2533 .width = 217, 2534 .height = 136, 2535 }, 2536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2539 }; 2540 2541 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2542 .clock = 33000, 2543 .hdisplay = 800, 2544 .hsync_start = 800 + 112, 2545 .hsync_end = 800 + 112 + 3, 2546 .htotal = 800 + 112 + 3 + 85, 2547 .vdisplay = 480, 2548 .vsync_start = 480 + 38, 2549 .vsync_end = 480 + 38 + 3, 2550 .vtotal = 480 + 38 + 3 + 29, 2551 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2552 }; 2553 2554 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2555 .modes = &logictechno_lttd800480070_l2rt_mode, 2556 .num_modes = 1, 2557 .bpc = 8, 2558 .size = { 2559 .width = 154, 2560 .height = 86, 2561 }, 2562 .delay = { 2563 .prepare = 45, 2564 .enable = 100, 2565 .disable = 100, 2566 .unprepare = 45 2567 }, 2568 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2569 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2570 .connector_type = DRM_MODE_CONNECTOR_DPI, 2571 }; 2572 2573 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2574 .clock = 33000, 2575 .hdisplay = 800, 2576 .hsync_start = 800 + 154, 2577 .hsync_end = 800 + 154 + 3, 2578 .htotal = 800 + 154 + 3 + 43, 2579 .vdisplay = 480, 2580 .vsync_start = 480 + 47, 2581 .vsync_end = 480 + 47 + 3, 2582 .vtotal = 480 + 47 + 3 + 20, 2583 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2584 }; 2585 2586 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2587 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2588 .num_modes = 1, 2589 .bpc = 8, 2590 .size = { 2591 .width = 154, 2592 .height = 86, 2593 }, 2594 .delay = { 2595 .prepare = 45, 2596 .enable = 100, 2597 .disable = 100, 2598 .unprepare = 45 2599 }, 2600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2601 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2602 .connector_type = DRM_MODE_CONNECTOR_DPI, 2603 }; 2604 2605 static const struct drm_display_mode logicpd_type_28_mode = { 2606 .clock = 9107, 2607 .hdisplay = 480, 2608 .hsync_start = 480 + 3, 2609 .hsync_end = 480 + 3 + 42, 2610 .htotal = 480 + 3 + 42 + 2, 2611 2612 .vdisplay = 272, 2613 .vsync_start = 272 + 2, 2614 .vsync_end = 272 + 2 + 11, 2615 .vtotal = 272 + 2 + 11 + 3, 2616 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2617 }; 2618 2619 static const struct panel_desc logicpd_type_28 = { 2620 .modes = &logicpd_type_28_mode, 2621 .num_modes = 1, 2622 .bpc = 8, 2623 .size = { 2624 .width = 105, 2625 .height = 67, 2626 }, 2627 .delay = { 2628 .prepare = 200, 2629 .enable = 200, 2630 .unprepare = 200, 2631 .disable = 200, 2632 }, 2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2634 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2635 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2636 .connector_type = DRM_MODE_CONNECTOR_DPI, 2637 }; 2638 2639 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2640 .clock = 30400, 2641 .hdisplay = 800, 2642 .hsync_start = 800 + 0, 2643 .hsync_end = 800 + 1, 2644 .htotal = 800 + 0 + 1 + 160, 2645 .vdisplay = 480, 2646 .vsync_start = 480 + 0, 2647 .vsync_end = 480 + 48 + 1, 2648 .vtotal = 480 + 48 + 1 + 0, 2649 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2650 }; 2651 2652 static const struct panel_desc mitsubishi_aa070mc01 = { 2653 .modes = &mitsubishi_aa070mc01_mode, 2654 .num_modes = 1, 2655 .bpc = 8, 2656 .size = { 2657 .width = 152, 2658 .height = 91, 2659 }, 2660 2661 .delay = { 2662 .enable = 200, 2663 .unprepare = 200, 2664 .disable = 400, 2665 }, 2666 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2667 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2668 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2669 }; 2670 2671 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2672 .pixelclock = { 29000000, 33000000, 38000000 }, 2673 .hactive = { 800, 800, 800 }, 2674 .hfront_porch = { 180, 210, 240 }, 2675 .hback_porch = { 16, 16, 16 }, 2676 .hsync_len = { 30, 30, 30 }, 2677 .vactive = { 480, 480, 480 }, 2678 .vfront_porch = { 12, 22, 32 }, 2679 .vback_porch = { 10, 10, 10 }, 2680 .vsync_len = { 13, 13, 13 }, 2681 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2682 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2683 DISPLAY_FLAGS_SYNC_POSEDGE, 2684 }; 2685 2686 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2687 .timings = &multi_inno_mi0700s4t_6_timing, 2688 .num_timings = 1, 2689 .bpc = 8, 2690 .size = { 2691 .width = 154, 2692 .height = 86, 2693 }, 2694 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2695 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2696 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2697 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2698 .connector_type = DRM_MODE_CONNECTOR_DPI, 2699 }; 2700 2701 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2702 .pixelclock = { 32000000, 40000000, 50000000 }, 2703 .hactive = { 800, 800, 800 }, 2704 .hfront_porch = { 16, 210, 354 }, 2705 .hback_porch = { 6, 26, 45 }, 2706 .hsync_len = { 1, 20, 40 }, 2707 .vactive = { 600, 600, 600 }, 2708 .vfront_porch = { 1, 12, 77 }, 2709 .vback_porch = { 3, 13, 22 }, 2710 .vsync_len = { 1, 10, 20 }, 2711 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2712 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2713 DISPLAY_FLAGS_SYNC_POSEDGE, 2714 }; 2715 2716 static const struct panel_desc multi_inno_mi0800ft_9 = { 2717 .timings = &multi_inno_mi0800ft_9_timing, 2718 .num_timings = 1, 2719 .bpc = 8, 2720 .size = { 2721 .width = 162, 2722 .height = 122, 2723 }, 2724 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2725 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2726 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2727 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2728 .connector_type = DRM_MODE_CONNECTOR_DPI, 2729 }; 2730 2731 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2732 .pixelclock = { 68900000, 70000000, 73400000 }, 2733 .hactive = { 1280, 1280, 1280 }, 2734 .hfront_porch = { 30, 60, 71 }, 2735 .hback_porch = { 30, 60, 71 }, 2736 .hsync_len = { 10, 10, 48 }, 2737 .vactive = { 800, 800, 800 }, 2738 .vfront_porch = { 5, 10, 10 }, 2739 .vback_porch = { 5, 10, 10 }, 2740 .vsync_len = { 5, 6, 13 }, 2741 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2742 DISPLAY_FLAGS_DE_HIGH, 2743 }; 2744 2745 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2746 .timings = &multi_inno_mi1010ait_1cp_timing, 2747 .num_timings = 1, 2748 .bpc = 8, 2749 .size = { 2750 .width = 217, 2751 .height = 136, 2752 }, 2753 .delay = { 2754 .enable = 50, 2755 .disable = 50, 2756 }, 2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2758 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2760 }; 2761 2762 static const struct display_timing nec_nl12880bc20_05_timing = { 2763 .pixelclock = { 67000000, 71000000, 75000000 }, 2764 .hactive = { 1280, 1280, 1280 }, 2765 .hfront_porch = { 2, 30, 30 }, 2766 .hback_porch = { 6, 100, 100 }, 2767 .hsync_len = { 2, 30, 30 }, 2768 .vactive = { 800, 800, 800 }, 2769 .vfront_porch = { 5, 5, 5 }, 2770 .vback_porch = { 11, 11, 11 }, 2771 .vsync_len = { 7, 7, 7 }, 2772 }; 2773 2774 static const struct panel_desc nec_nl12880bc20_05 = { 2775 .timings = &nec_nl12880bc20_05_timing, 2776 .num_timings = 1, 2777 .bpc = 8, 2778 .size = { 2779 .width = 261, 2780 .height = 163, 2781 }, 2782 .delay = { 2783 .enable = 50, 2784 .disable = 50, 2785 }, 2786 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2787 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2788 }; 2789 2790 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2791 .clock = 10870, 2792 .hdisplay = 480, 2793 .hsync_start = 480 + 2, 2794 .hsync_end = 480 + 2 + 41, 2795 .htotal = 480 + 2 + 41 + 2, 2796 .vdisplay = 272, 2797 .vsync_start = 272 + 2, 2798 .vsync_end = 272 + 2 + 4, 2799 .vtotal = 272 + 2 + 4 + 2, 2800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2801 }; 2802 2803 static const struct panel_desc nec_nl4827hc19_05b = { 2804 .modes = &nec_nl4827hc19_05b_mode, 2805 .num_modes = 1, 2806 .bpc = 8, 2807 .size = { 2808 .width = 95, 2809 .height = 54, 2810 }, 2811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2812 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2813 }; 2814 2815 static const struct drm_display_mode netron_dy_e231732_mode = { 2816 .clock = 66000, 2817 .hdisplay = 1024, 2818 .hsync_start = 1024 + 160, 2819 .hsync_end = 1024 + 160 + 70, 2820 .htotal = 1024 + 160 + 70 + 90, 2821 .vdisplay = 600, 2822 .vsync_start = 600 + 127, 2823 .vsync_end = 600 + 127 + 20, 2824 .vtotal = 600 + 127 + 20 + 3, 2825 }; 2826 2827 static const struct panel_desc netron_dy_e231732 = { 2828 .modes = &netron_dy_e231732_mode, 2829 .num_modes = 1, 2830 .size = { 2831 .width = 154, 2832 .height = 87, 2833 }, 2834 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2835 }; 2836 2837 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2838 .clock = 9000, 2839 .hdisplay = 480, 2840 .hsync_start = 480 + 2, 2841 .hsync_end = 480 + 2 + 41, 2842 .htotal = 480 + 2 + 41 + 2, 2843 .vdisplay = 272, 2844 .vsync_start = 272 + 2, 2845 .vsync_end = 272 + 2 + 10, 2846 .vtotal = 272 + 2 + 10 + 2, 2847 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2848 }; 2849 2850 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2851 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2852 .num_modes = 1, 2853 .bpc = 8, 2854 .size = { 2855 .width = 95, 2856 .height = 54, 2857 }, 2858 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2860 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2861 .connector_type = DRM_MODE_CONNECTOR_DPI, 2862 }; 2863 2864 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2865 .pixelclock = { 130000000, 148350000, 163000000 }, 2866 .hactive = { 1920, 1920, 1920 }, 2867 .hfront_porch = { 80, 100, 100 }, 2868 .hback_porch = { 100, 120, 120 }, 2869 .hsync_len = { 50, 60, 60 }, 2870 .vactive = { 1080, 1080, 1080 }, 2871 .vfront_porch = { 12, 30, 30 }, 2872 .vback_porch = { 4, 10, 10 }, 2873 .vsync_len = { 4, 5, 5 }, 2874 }; 2875 2876 static const struct panel_desc nlt_nl192108ac18_02d = { 2877 .timings = &nlt_nl192108ac18_02d_timing, 2878 .num_timings = 1, 2879 .bpc = 8, 2880 .size = { 2881 .width = 344, 2882 .height = 194, 2883 }, 2884 .delay = { 2885 .unprepare = 500, 2886 }, 2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2888 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2889 }; 2890 2891 static const struct drm_display_mode nvd_9128_mode = { 2892 .clock = 29500, 2893 .hdisplay = 800, 2894 .hsync_start = 800 + 130, 2895 .hsync_end = 800 + 130 + 98, 2896 .htotal = 800 + 0 + 130 + 98, 2897 .vdisplay = 480, 2898 .vsync_start = 480 + 10, 2899 .vsync_end = 480 + 10 + 50, 2900 .vtotal = 480 + 0 + 10 + 50, 2901 }; 2902 2903 static const struct panel_desc nvd_9128 = { 2904 .modes = &nvd_9128_mode, 2905 .num_modes = 1, 2906 .bpc = 8, 2907 .size = { 2908 .width = 156, 2909 .height = 88, 2910 }, 2911 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2912 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2913 }; 2914 2915 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2916 .pixelclock = { 30000000, 30000000, 40000000 }, 2917 .hactive = { 800, 800, 800 }, 2918 .hfront_porch = { 40, 40, 40 }, 2919 .hback_porch = { 40, 40, 40 }, 2920 .hsync_len = { 1, 48, 48 }, 2921 .vactive = { 480, 480, 480 }, 2922 .vfront_porch = { 13, 13, 13 }, 2923 .vback_porch = { 29, 29, 29 }, 2924 .vsync_len = { 3, 3, 3 }, 2925 .flags = DISPLAY_FLAGS_DE_HIGH, 2926 }; 2927 2928 static const struct panel_desc okaya_rs800480t_7x0gp = { 2929 .timings = &okaya_rs800480t_7x0gp_timing, 2930 .num_timings = 1, 2931 .bpc = 6, 2932 .size = { 2933 .width = 154, 2934 .height = 87, 2935 }, 2936 .delay = { 2937 .prepare = 41, 2938 .enable = 50, 2939 .unprepare = 41, 2940 .disable = 50, 2941 }, 2942 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2943 }; 2944 2945 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2946 .clock = 9000, 2947 .hdisplay = 480, 2948 .hsync_start = 480 + 5, 2949 .hsync_end = 480 + 5 + 30, 2950 .htotal = 480 + 5 + 30 + 10, 2951 .vdisplay = 272, 2952 .vsync_start = 272 + 8, 2953 .vsync_end = 272 + 8 + 5, 2954 .vtotal = 272 + 8 + 5 + 3, 2955 }; 2956 2957 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2958 .modes = &olimex_lcd_olinuxino_43ts_mode, 2959 .num_modes = 1, 2960 .size = { 2961 .width = 95, 2962 .height = 54, 2963 }, 2964 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2965 }; 2966 2967 /* 2968 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2969 * pixel clocks, but this is the timing that was being used in the Adafruit 2970 * installation instructions. 2971 */ 2972 static const struct drm_display_mode ontat_yx700wv03_mode = { 2973 .clock = 29500, 2974 .hdisplay = 800, 2975 .hsync_start = 824, 2976 .hsync_end = 896, 2977 .htotal = 992, 2978 .vdisplay = 480, 2979 .vsync_start = 483, 2980 .vsync_end = 493, 2981 .vtotal = 500, 2982 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2983 }; 2984 2985 /* 2986 * Specification at: 2987 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2988 */ 2989 static const struct panel_desc ontat_yx700wv03 = { 2990 .modes = &ontat_yx700wv03_mode, 2991 .num_modes = 1, 2992 .bpc = 8, 2993 .size = { 2994 .width = 154, 2995 .height = 83, 2996 }, 2997 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2998 }; 2999 3000 static const struct drm_display_mode ortustech_com37h3m_mode = { 3001 .clock = 22230, 3002 .hdisplay = 480, 3003 .hsync_start = 480 + 40, 3004 .hsync_end = 480 + 40 + 10, 3005 .htotal = 480 + 40 + 10 + 40, 3006 .vdisplay = 640, 3007 .vsync_start = 640 + 4, 3008 .vsync_end = 640 + 4 + 2, 3009 .vtotal = 640 + 4 + 2 + 4, 3010 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3011 }; 3012 3013 static const struct panel_desc ortustech_com37h3m = { 3014 .modes = &ortustech_com37h3m_mode, 3015 .num_modes = 1, 3016 .bpc = 8, 3017 .size = { 3018 .width = 56, /* 56.16mm */ 3019 .height = 75, /* 74.88mm */ 3020 }, 3021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3023 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3024 }; 3025 3026 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3027 .clock = 25000, 3028 .hdisplay = 480, 3029 .hsync_start = 480 + 10, 3030 .hsync_end = 480 + 10 + 10, 3031 .htotal = 480 + 10 + 10 + 15, 3032 .vdisplay = 800, 3033 .vsync_start = 800 + 3, 3034 .vsync_end = 800 + 3 + 3, 3035 .vtotal = 800 + 3 + 3 + 3, 3036 }; 3037 3038 static const struct panel_desc ortustech_com43h4m85ulc = { 3039 .modes = &ortustech_com43h4m85ulc_mode, 3040 .num_modes = 1, 3041 .bpc = 6, 3042 .size = { 3043 .width = 56, 3044 .height = 93, 3045 }, 3046 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3047 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3048 .connector_type = DRM_MODE_CONNECTOR_DPI, 3049 }; 3050 3051 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3052 .clock = 33000, 3053 .hdisplay = 800, 3054 .hsync_start = 800 + 210, 3055 .hsync_end = 800 + 210 + 30, 3056 .htotal = 800 + 210 + 30 + 16, 3057 .vdisplay = 480, 3058 .vsync_start = 480 + 22, 3059 .vsync_end = 480 + 22 + 13, 3060 .vtotal = 480 + 22 + 13 + 10, 3061 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3062 }; 3063 3064 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3065 .modes = &osddisplays_osd070t1718_19ts_mode, 3066 .num_modes = 1, 3067 .bpc = 8, 3068 .size = { 3069 .width = 152, 3070 .height = 91, 3071 }, 3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3074 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3075 .connector_type = DRM_MODE_CONNECTOR_DPI, 3076 }; 3077 3078 static const struct drm_display_mode pda_91_00156_a0_mode = { 3079 .clock = 33300, 3080 .hdisplay = 800, 3081 .hsync_start = 800 + 1, 3082 .hsync_end = 800 + 1 + 64, 3083 .htotal = 800 + 1 + 64 + 64, 3084 .vdisplay = 480, 3085 .vsync_start = 480 + 1, 3086 .vsync_end = 480 + 1 + 23, 3087 .vtotal = 480 + 1 + 23 + 22, 3088 }; 3089 3090 static const struct panel_desc pda_91_00156_a0 = { 3091 .modes = &pda_91_00156_a0_mode, 3092 .num_modes = 1, 3093 .size = { 3094 .width = 152, 3095 .height = 91, 3096 }, 3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3098 }; 3099 3100 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3101 .clock = 24750, 3102 .hdisplay = 800, 3103 .hsync_start = 800 + 54, 3104 .hsync_end = 800 + 54 + 2, 3105 .htotal = 800 + 54 + 2 + 44, 3106 .vdisplay = 480, 3107 .vsync_start = 480 + 49, 3108 .vsync_end = 480 + 49 + 2, 3109 .vtotal = 480 + 49 + 2 + 22, 3110 }; 3111 3112 static const struct panel_desc powertip_ph800480t013_idf02 = { 3113 .modes = &powertip_ph800480t013_idf02_mode, 3114 .num_modes = 1, 3115 .size = { 3116 .width = 152, 3117 .height = 91, 3118 }, 3119 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3120 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3121 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3123 .connector_type = DRM_MODE_CONNECTOR_DPI, 3124 }; 3125 3126 static const struct drm_display_mode qd43003c0_40_mode = { 3127 .clock = 9000, 3128 .hdisplay = 480, 3129 .hsync_start = 480 + 8, 3130 .hsync_end = 480 + 8 + 4, 3131 .htotal = 480 + 8 + 4 + 39, 3132 .vdisplay = 272, 3133 .vsync_start = 272 + 4, 3134 .vsync_end = 272 + 4 + 10, 3135 .vtotal = 272 + 4 + 10 + 2, 3136 }; 3137 3138 static const struct panel_desc qd43003c0_40 = { 3139 .modes = &qd43003c0_40_mode, 3140 .num_modes = 1, 3141 .bpc = 8, 3142 .size = { 3143 .width = 95, 3144 .height = 53, 3145 }, 3146 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3147 }; 3148 3149 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3150 { /* 60 Hz */ 3151 .clock = 10800, 3152 .hdisplay = 480, 3153 .hsync_start = 480 + 77, 3154 .hsync_end = 480 + 77 + 41, 3155 .htotal = 480 + 77 + 41 + 2, 3156 .vdisplay = 272, 3157 .vsync_start = 272 + 16, 3158 .vsync_end = 272 + 16 + 10, 3159 .vtotal = 272 + 16 + 10 + 2, 3160 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3161 }, 3162 { /* 50 Hz */ 3163 .clock = 10800, 3164 .hdisplay = 480, 3165 .hsync_start = 480 + 17, 3166 .hsync_end = 480 + 17 + 41, 3167 .htotal = 480 + 17 + 41 + 2, 3168 .vdisplay = 272, 3169 .vsync_start = 272 + 116, 3170 .vsync_end = 272 + 116 + 10, 3171 .vtotal = 272 + 116 + 10 + 2, 3172 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3173 }, 3174 }; 3175 3176 static const struct panel_desc qishenglong_gopher2b_lcd = { 3177 .modes = qishenglong_gopher2b_lcd_modes, 3178 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3179 .bpc = 8, 3180 .size = { 3181 .width = 95, 3182 .height = 54, 3183 }, 3184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3185 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3186 .connector_type = DRM_MODE_CONNECTOR_DPI, 3187 }; 3188 3189 static const struct display_timing rocktech_rk070er9427_timing = { 3190 .pixelclock = { 26400000, 33300000, 46800000 }, 3191 .hactive = { 800, 800, 800 }, 3192 .hfront_porch = { 16, 210, 354 }, 3193 .hback_porch = { 46, 46, 46 }, 3194 .hsync_len = { 1, 1, 1 }, 3195 .vactive = { 480, 480, 480 }, 3196 .vfront_porch = { 7, 22, 147 }, 3197 .vback_porch = { 23, 23, 23 }, 3198 .vsync_len = { 1, 1, 1 }, 3199 .flags = DISPLAY_FLAGS_DE_HIGH, 3200 }; 3201 3202 static const struct panel_desc rocktech_rk070er9427 = { 3203 .timings = &rocktech_rk070er9427_timing, 3204 .num_timings = 1, 3205 .bpc = 6, 3206 .size = { 3207 .width = 154, 3208 .height = 86, 3209 }, 3210 .delay = { 3211 .prepare = 41, 3212 .enable = 50, 3213 .unprepare = 41, 3214 .disable = 50, 3215 }, 3216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3217 }; 3218 3219 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3220 .clock = 71100, 3221 .hdisplay = 1280, 3222 .hsync_start = 1280 + 48, 3223 .hsync_end = 1280 + 48 + 32, 3224 .htotal = 1280 + 48 + 32 + 80, 3225 .vdisplay = 800, 3226 .vsync_start = 800 + 2, 3227 .vsync_end = 800 + 2 + 5, 3228 .vtotal = 800 + 2 + 5 + 16, 3229 }; 3230 3231 static const struct panel_desc rocktech_rk101ii01d_ct = { 3232 .modes = &rocktech_rk101ii01d_ct_mode, 3233 .bpc = 8, 3234 .num_modes = 1, 3235 .size = { 3236 .width = 217, 3237 .height = 136, 3238 }, 3239 .delay = { 3240 .prepare = 50, 3241 .disable = 50, 3242 }, 3243 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3246 }; 3247 3248 static const struct display_timing samsung_ltl101al01_timing = { 3249 .pixelclock = { 66663000, 66663000, 66663000 }, 3250 .hactive = { 1280, 1280, 1280 }, 3251 .hfront_porch = { 18, 18, 18 }, 3252 .hback_porch = { 36, 36, 36 }, 3253 .hsync_len = { 16, 16, 16 }, 3254 .vactive = { 800, 800, 800 }, 3255 .vfront_porch = { 4, 4, 4 }, 3256 .vback_porch = { 16, 16, 16 }, 3257 .vsync_len = { 3, 3, 3 }, 3258 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3259 }; 3260 3261 static const struct panel_desc samsung_ltl101al01 = { 3262 .timings = &samsung_ltl101al01_timing, 3263 .num_timings = 1, 3264 .bpc = 8, 3265 .size = { 3266 .width = 217, 3267 .height = 135, 3268 }, 3269 .delay = { 3270 .prepare = 40, 3271 .enable = 300, 3272 .disable = 200, 3273 .unprepare = 600, 3274 }, 3275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3276 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3277 }; 3278 3279 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3280 .clock = 54030, 3281 .hdisplay = 1024, 3282 .hsync_start = 1024 + 24, 3283 .hsync_end = 1024 + 24 + 136, 3284 .htotal = 1024 + 24 + 136 + 160, 3285 .vdisplay = 600, 3286 .vsync_start = 600 + 3, 3287 .vsync_end = 600 + 3 + 6, 3288 .vtotal = 600 + 3 + 6 + 61, 3289 }; 3290 3291 static const struct panel_desc samsung_ltn101nt05 = { 3292 .modes = &samsung_ltn101nt05_mode, 3293 .num_modes = 1, 3294 .bpc = 6, 3295 .size = { 3296 .width = 223, 3297 .height = 125, 3298 }, 3299 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3300 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3301 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3302 }; 3303 3304 static const struct display_timing satoz_sat050at40h12r2_timing = { 3305 .pixelclock = {33300000, 33300000, 50000000}, 3306 .hactive = {800, 800, 800}, 3307 .hfront_porch = {16, 210, 354}, 3308 .hback_porch = {46, 46, 46}, 3309 .hsync_len = {1, 1, 40}, 3310 .vactive = {480, 480, 480}, 3311 .vfront_porch = {7, 22, 147}, 3312 .vback_porch = {23, 23, 23}, 3313 .vsync_len = {1, 1, 20}, 3314 }; 3315 3316 static const struct panel_desc satoz_sat050at40h12r2 = { 3317 .timings = &satoz_sat050at40h12r2_timing, 3318 .num_timings = 1, 3319 .bpc = 8, 3320 .size = { 3321 .width = 108, 3322 .height = 65, 3323 }, 3324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3326 }; 3327 3328 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3329 .clock = 33260, 3330 .hdisplay = 800, 3331 .hsync_start = 800 + 64, 3332 .hsync_end = 800 + 64 + 128, 3333 .htotal = 800 + 64 + 128 + 64, 3334 .vdisplay = 480, 3335 .vsync_start = 480 + 8, 3336 .vsync_end = 480 + 8 + 2, 3337 .vtotal = 480 + 8 + 2 + 35, 3338 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3339 }; 3340 3341 static const struct panel_desc sharp_lq070y3dg3b = { 3342 .modes = &sharp_lq070y3dg3b_mode, 3343 .num_modes = 1, 3344 .bpc = 8, 3345 .size = { 3346 .width = 152, /* 152.4mm */ 3347 .height = 91, /* 91.4mm */ 3348 }, 3349 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3350 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3351 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3352 }; 3353 3354 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3355 .clock = 5500, 3356 .hdisplay = 240, 3357 .hsync_start = 240 + 16, 3358 .hsync_end = 240 + 16 + 7, 3359 .htotal = 240 + 16 + 7 + 5, 3360 .vdisplay = 320, 3361 .vsync_start = 320 + 9, 3362 .vsync_end = 320 + 9 + 1, 3363 .vtotal = 320 + 9 + 1 + 7, 3364 }; 3365 3366 static const struct panel_desc sharp_lq035q7db03 = { 3367 .modes = &sharp_lq035q7db03_mode, 3368 .num_modes = 1, 3369 .bpc = 6, 3370 .size = { 3371 .width = 54, 3372 .height = 72, 3373 }, 3374 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3375 }; 3376 3377 static const struct display_timing sharp_lq101k1ly04_timing = { 3378 .pixelclock = { 60000000, 65000000, 80000000 }, 3379 .hactive = { 1280, 1280, 1280 }, 3380 .hfront_porch = { 20, 20, 20 }, 3381 .hback_porch = { 20, 20, 20 }, 3382 .hsync_len = { 10, 10, 10 }, 3383 .vactive = { 800, 800, 800 }, 3384 .vfront_porch = { 4, 4, 4 }, 3385 .vback_porch = { 4, 4, 4 }, 3386 .vsync_len = { 4, 4, 4 }, 3387 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3388 }; 3389 3390 static const struct panel_desc sharp_lq101k1ly04 = { 3391 .timings = &sharp_lq101k1ly04_timing, 3392 .num_timings = 1, 3393 .bpc = 8, 3394 .size = { 3395 .width = 217, 3396 .height = 136, 3397 }, 3398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3399 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3400 }; 3401 3402 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3403 { /* 50 Hz */ 3404 .clock = 3000, 3405 .hdisplay = 240, 3406 .hsync_start = 240 + 58, 3407 .hsync_end = 240 + 58 + 1, 3408 .htotal = 240 + 58 + 1 + 1, 3409 .vdisplay = 160, 3410 .vsync_start = 160 + 24, 3411 .vsync_end = 160 + 24 + 10, 3412 .vtotal = 160 + 24 + 10 + 6, 3413 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3414 }, 3415 { /* 60 Hz */ 3416 .clock = 3000, 3417 .hdisplay = 240, 3418 .hsync_start = 240 + 8, 3419 .hsync_end = 240 + 8 + 1, 3420 .htotal = 240 + 8 + 1 + 1, 3421 .vdisplay = 160, 3422 .vsync_start = 160 + 24, 3423 .vsync_end = 160 + 24 + 10, 3424 .vtotal = 160 + 24 + 10 + 6, 3425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3426 }, 3427 }; 3428 3429 static const struct panel_desc sharp_ls020b1dd01d = { 3430 .modes = sharp_ls020b1dd01d_modes, 3431 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3432 .bpc = 6, 3433 .size = { 3434 .width = 42, 3435 .height = 28, 3436 }, 3437 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3438 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3439 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3440 | DRM_BUS_FLAG_SHARP_SIGNALS, 3441 }; 3442 3443 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3444 .clock = 33300, 3445 .hdisplay = 800, 3446 .hsync_start = 800 + 1, 3447 .hsync_end = 800 + 1 + 64, 3448 .htotal = 800 + 1 + 64 + 64, 3449 .vdisplay = 480, 3450 .vsync_start = 480 + 1, 3451 .vsync_end = 480 + 1 + 23, 3452 .vtotal = 480 + 1 + 23 + 22, 3453 }; 3454 3455 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3456 .modes = &shelly_sca07010_bfn_lnn_mode, 3457 .num_modes = 1, 3458 .size = { 3459 .width = 152, 3460 .height = 91, 3461 }, 3462 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3463 }; 3464 3465 static const struct drm_display_mode starry_kr070pe2t_mode = { 3466 .clock = 33000, 3467 .hdisplay = 800, 3468 .hsync_start = 800 + 209, 3469 .hsync_end = 800 + 209 + 1, 3470 .htotal = 800 + 209 + 1 + 45, 3471 .vdisplay = 480, 3472 .vsync_start = 480 + 22, 3473 .vsync_end = 480 + 22 + 1, 3474 .vtotal = 480 + 22 + 1 + 22, 3475 }; 3476 3477 static const struct panel_desc starry_kr070pe2t = { 3478 .modes = &starry_kr070pe2t_mode, 3479 .num_modes = 1, 3480 .bpc = 8, 3481 .size = { 3482 .width = 152, 3483 .height = 86, 3484 }, 3485 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3486 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3487 .connector_type = DRM_MODE_CONNECTOR_DPI, 3488 }; 3489 3490 static const struct display_timing startek_kd070wvfpa_mode = { 3491 .pixelclock = { 25200000, 27200000, 30500000 }, 3492 .hactive = { 800, 800, 800 }, 3493 .hfront_porch = { 19, 44, 115 }, 3494 .hback_porch = { 5, 16, 101 }, 3495 .hsync_len = { 1, 2, 100 }, 3496 .vactive = { 480, 480, 480 }, 3497 .vfront_porch = { 5, 43, 67 }, 3498 .vback_porch = { 5, 5, 67 }, 3499 .vsync_len = { 1, 2, 66 }, 3500 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3501 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3502 DISPLAY_FLAGS_SYNC_POSEDGE, 3503 }; 3504 3505 static const struct panel_desc startek_kd070wvfpa = { 3506 .timings = &startek_kd070wvfpa_mode, 3507 .num_timings = 1, 3508 .bpc = 8, 3509 .size = { 3510 .width = 152, 3511 .height = 91, 3512 }, 3513 .delay = { 3514 .prepare = 20, 3515 .enable = 200, 3516 .disable = 200, 3517 }, 3518 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3519 .connector_type = DRM_MODE_CONNECTOR_DPI, 3520 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3521 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3522 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3523 }; 3524 3525 static const struct display_timing tsd_tst043015cmhx_timing = { 3526 .pixelclock = { 5000000, 9000000, 12000000 }, 3527 .hactive = { 480, 480, 480 }, 3528 .hfront_porch = { 4, 5, 65 }, 3529 .hback_porch = { 36, 40, 255 }, 3530 .hsync_len = { 1, 1, 1 }, 3531 .vactive = { 272, 272, 272 }, 3532 .vfront_porch = { 2, 8, 97 }, 3533 .vback_porch = { 3, 8, 31 }, 3534 .vsync_len = { 1, 1, 1 }, 3535 3536 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3537 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3538 }; 3539 3540 static const struct panel_desc tsd_tst043015cmhx = { 3541 .timings = &tsd_tst043015cmhx_timing, 3542 .num_timings = 1, 3543 .bpc = 8, 3544 .size = { 3545 .width = 105, 3546 .height = 67, 3547 }, 3548 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3549 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3550 }; 3551 3552 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3553 .clock = 30000, 3554 .hdisplay = 800, 3555 .hsync_start = 800 + 39, 3556 .hsync_end = 800 + 39 + 47, 3557 .htotal = 800 + 39 + 47 + 39, 3558 .vdisplay = 480, 3559 .vsync_start = 480 + 13, 3560 .vsync_end = 480 + 13 + 2, 3561 .vtotal = 480 + 13 + 2 + 29, 3562 }; 3563 3564 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3565 .modes = &tfc_s9700rtwv43tr_01b_mode, 3566 .num_modes = 1, 3567 .bpc = 8, 3568 .size = { 3569 .width = 155, 3570 .height = 90, 3571 }, 3572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3573 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3574 }; 3575 3576 static const struct display_timing tianma_tm070jdhg30_timing = { 3577 .pixelclock = { 62600000, 68200000, 78100000 }, 3578 .hactive = { 1280, 1280, 1280 }, 3579 .hfront_porch = { 15, 64, 159 }, 3580 .hback_porch = { 5, 5, 5 }, 3581 .hsync_len = { 1, 1, 256 }, 3582 .vactive = { 800, 800, 800 }, 3583 .vfront_porch = { 3, 40, 99 }, 3584 .vback_porch = { 2, 2, 2 }, 3585 .vsync_len = { 1, 1, 128 }, 3586 .flags = DISPLAY_FLAGS_DE_HIGH, 3587 }; 3588 3589 static const struct panel_desc tianma_tm070jdhg30 = { 3590 .timings = &tianma_tm070jdhg30_timing, 3591 .num_timings = 1, 3592 .bpc = 8, 3593 .size = { 3594 .width = 151, 3595 .height = 95, 3596 }, 3597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3598 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3599 }; 3600 3601 static const struct panel_desc tianma_tm070jvhg33 = { 3602 .timings = &tianma_tm070jdhg30_timing, 3603 .num_timings = 1, 3604 .bpc = 8, 3605 .size = { 3606 .width = 150, 3607 .height = 94, 3608 }, 3609 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3610 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3611 }; 3612 3613 static const struct display_timing tianma_tm070rvhg71_timing = { 3614 .pixelclock = { 27700000, 29200000, 39600000 }, 3615 .hactive = { 800, 800, 800 }, 3616 .hfront_porch = { 12, 40, 212 }, 3617 .hback_porch = { 88, 88, 88 }, 3618 .hsync_len = { 1, 1, 40 }, 3619 .vactive = { 480, 480, 480 }, 3620 .vfront_porch = { 1, 13, 88 }, 3621 .vback_porch = { 32, 32, 32 }, 3622 .vsync_len = { 1, 1, 3 }, 3623 .flags = DISPLAY_FLAGS_DE_HIGH, 3624 }; 3625 3626 static const struct panel_desc tianma_tm070rvhg71 = { 3627 .timings = &tianma_tm070rvhg71_timing, 3628 .num_timings = 1, 3629 .bpc = 8, 3630 .size = { 3631 .width = 154, 3632 .height = 86, 3633 }, 3634 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3635 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3636 }; 3637 3638 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3639 { 3640 .clock = 10000, 3641 .hdisplay = 320, 3642 .hsync_start = 320 + 50, 3643 .hsync_end = 320 + 50 + 6, 3644 .htotal = 320 + 50 + 6 + 38, 3645 .vdisplay = 240, 3646 .vsync_start = 240 + 3, 3647 .vsync_end = 240 + 3 + 1, 3648 .vtotal = 240 + 3 + 1 + 17, 3649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3650 }, 3651 }; 3652 3653 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3654 .modes = ti_nspire_cx_lcd_mode, 3655 .num_modes = 1, 3656 .bpc = 8, 3657 .size = { 3658 .width = 65, 3659 .height = 49, 3660 }, 3661 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3662 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3663 }; 3664 3665 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3666 { 3667 .clock = 10000, 3668 .hdisplay = 320, 3669 .hsync_start = 320 + 6, 3670 .hsync_end = 320 + 6 + 6, 3671 .htotal = 320 + 6 + 6 + 6, 3672 .vdisplay = 240, 3673 .vsync_start = 240 + 0, 3674 .vsync_end = 240 + 0 + 1, 3675 .vtotal = 240 + 0 + 1 + 0, 3676 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3677 }, 3678 }; 3679 3680 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3681 .modes = ti_nspire_classic_lcd_mode, 3682 .num_modes = 1, 3683 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3684 .bpc = 8, 3685 .size = { 3686 .width = 71, 3687 .height = 53, 3688 }, 3689 /* This is the grayscale bus format */ 3690 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3691 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3692 }; 3693 3694 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3695 .clock = 79500, 3696 .hdisplay = 1280, 3697 .hsync_start = 1280 + 192, 3698 .hsync_end = 1280 + 192 + 128, 3699 .htotal = 1280 + 192 + 128 + 64, 3700 .vdisplay = 768, 3701 .vsync_start = 768 + 20, 3702 .vsync_end = 768 + 20 + 7, 3703 .vtotal = 768 + 20 + 7 + 3, 3704 }; 3705 3706 static const struct panel_desc toshiba_lt089ac29000 = { 3707 .modes = &toshiba_lt089ac29000_mode, 3708 .num_modes = 1, 3709 .size = { 3710 .width = 194, 3711 .height = 116, 3712 }, 3713 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3714 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3715 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3716 }; 3717 3718 static const struct drm_display_mode tpk_f07a_0102_mode = { 3719 .clock = 33260, 3720 .hdisplay = 800, 3721 .hsync_start = 800 + 40, 3722 .hsync_end = 800 + 40 + 128, 3723 .htotal = 800 + 40 + 128 + 88, 3724 .vdisplay = 480, 3725 .vsync_start = 480 + 10, 3726 .vsync_end = 480 + 10 + 2, 3727 .vtotal = 480 + 10 + 2 + 33, 3728 }; 3729 3730 static const struct panel_desc tpk_f07a_0102 = { 3731 .modes = &tpk_f07a_0102_mode, 3732 .num_modes = 1, 3733 .size = { 3734 .width = 152, 3735 .height = 91, 3736 }, 3737 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3738 }; 3739 3740 static const struct drm_display_mode tpk_f10a_0102_mode = { 3741 .clock = 45000, 3742 .hdisplay = 1024, 3743 .hsync_start = 1024 + 176, 3744 .hsync_end = 1024 + 176 + 5, 3745 .htotal = 1024 + 176 + 5 + 88, 3746 .vdisplay = 600, 3747 .vsync_start = 600 + 20, 3748 .vsync_end = 600 + 20 + 5, 3749 .vtotal = 600 + 20 + 5 + 25, 3750 }; 3751 3752 static const struct panel_desc tpk_f10a_0102 = { 3753 .modes = &tpk_f10a_0102_mode, 3754 .num_modes = 1, 3755 .size = { 3756 .width = 223, 3757 .height = 125, 3758 }, 3759 }; 3760 3761 static const struct display_timing urt_umsh_8596md_timing = { 3762 .pixelclock = { 33260000, 33260000, 33260000 }, 3763 .hactive = { 800, 800, 800 }, 3764 .hfront_porch = { 41, 41, 41 }, 3765 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3766 .hsync_len = { 71, 128, 128 }, 3767 .vactive = { 480, 480, 480 }, 3768 .vfront_porch = { 10, 10, 10 }, 3769 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3770 .vsync_len = { 2, 2, 2 }, 3771 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3772 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3773 }; 3774 3775 static const struct panel_desc urt_umsh_8596md_lvds = { 3776 .timings = &urt_umsh_8596md_timing, 3777 .num_timings = 1, 3778 .bpc = 6, 3779 .size = { 3780 .width = 152, 3781 .height = 91, 3782 }, 3783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3785 }; 3786 3787 static const struct panel_desc urt_umsh_8596md_parallel = { 3788 .timings = &urt_umsh_8596md_timing, 3789 .num_timings = 1, 3790 .bpc = 6, 3791 .size = { 3792 .width = 152, 3793 .height = 91, 3794 }, 3795 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3796 }; 3797 3798 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3799 .clock = 60000, 3800 .hdisplay = 1024, 3801 .hsync_start = 1024 + 160, 3802 .hsync_end = 1024 + 160 + 100, 3803 .htotal = 1024 + 160 + 100 + 60, 3804 .vdisplay = 600, 3805 .vsync_start = 600 + 12, 3806 .vsync_end = 600 + 12 + 10, 3807 .vtotal = 600 + 12 + 10 + 13, 3808 }; 3809 3810 static const struct panel_desc vivax_tpc9150_panel = { 3811 .modes = &vivax_tpc9150_panel_mode, 3812 .num_modes = 1, 3813 .bpc = 6, 3814 .size = { 3815 .width = 200, 3816 .height = 115, 3817 }, 3818 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3819 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3821 }; 3822 3823 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3824 .clock = 33333, 3825 .hdisplay = 800, 3826 .hsync_start = 800 + 210, 3827 .hsync_end = 800 + 210 + 20, 3828 .htotal = 800 + 210 + 20 + 46, 3829 .vdisplay = 480, 3830 .vsync_start = 480 + 22, 3831 .vsync_end = 480 + 22 + 10, 3832 .vtotal = 480 + 22 + 10 + 23, 3833 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3834 }; 3835 3836 static const struct panel_desc vl050_8048nt_c01 = { 3837 .modes = &vl050_8048nt_c01_mode, 3838 .num_modes = 1, 3839 .bpc = 8, 3840 .size = { 3841 .width = 120, 3842 .height = 76, 3843 }, 3844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3846 }; 3847 3848 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3849 .clock = 6410, 3850 .hdisplay = 320, 3851 .hsync_start = 320 + 20, 3852 .hsync_end = 320 + 20 + 30, 3853 .htotal = 320 + 20 + 30 + 38, 3854 .vdisplay = 240, 3855 .vsync_start = 240 + 4, 3856 .vsync_end = 240 + 4 + 3, 3857 .vtotal = 240 + 4 + 3 + 15, 3858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3859 }; 3860 3861 static const struct panel_desc winstar_wf35ltiacd = { 3862 .modes = &winstar_wf35ltiacd_mode, 3863 .num_modes = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 70, 3867 .height = 53, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3870 }; 3871 3872 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3873 .clock = 51200, 3874 .hdisplay = 1024, 3875 .hsync_start = 1024 + 100, 3876 .hsync_end = 1024 + 100 + 100, 3877 .htotal = 1024 + 100 + 100 + 120, 3878 .vdisplay = 600, 3879 .vsync_start = 600 + 10, 3880 .vsync_end = 600 + 10 + 10, 3881 .vtotal = 600 + 10 + 10 + 15, 3882 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3883 }; 3884 3885 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3886 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3887 .num_modes = 1, 3888 .bpc = 8, 3889 .size = { 3890 .width = 154, 3891 .height = 90, 3892 }, 3893 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3896 }; 3897 3898 static const struct drm_display_mode arm_rtsm_mode[] = { 3899 { 3900 .clock = 65000, 3901 .hdisplay = 1024, 3902 .hsync_start = 1024 + 24, 3903 .hsync_end = 1024 + 24 + 136, 3904 .htotal = 1024 + 24 + 136 + 160, 3905 .vdisplay = 768, 3906 .vsync_start = 768 + 3, 3907 .vsync_end = 768 + 3 + 6, 3908 .vtotal = 768 + 3 + 6 + 29, 3909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3910 }, 3911 }; 3912 3913 static const struct panel_desc arm_rtsm = { 3914 .modes = arm_rtsm_mode, 3915 .num_modes = 1, 3916 .bpc = 8, 3917 .size = { 3918 .width = 400, 3919 .height = 300, 3920 }, 3921 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3922 }; 3923 3924 static const struct of_device_id platform_of_match[] = { 3925 { 3926 .compatible = "ampire,am-1280800n3tzqw-t00h", 3927 .data = &ire_am_1280800n3tzqw_t00h, 3928 }, { 3929 .compatible = "ampire,am-480272h3tmqw-t01h", 3930 .data = &ire_am_480272h3tmqw_t01h, 3931 }, { 3932 .compatible = "ampire,am800480r3tmqwa1h", 3933 .data = &ire_am800480r3tmqwa1h, 3934 }, { 3935 .compatible = "ampire,am800600p5tmqw-tb8h", 3936 .data = &ire_am800600p5tmqwtb8h, 3937 }, { 3938 .compatible = "arm,rtsm-display", 3939 .data = &arm_rtsm, 3940 }, { 3941 .compatible = "armadeus,st0700-adapt", 3942 .data = &armadeus_st0700_adapt, 3943 }, { 3944 .compatible = "auo,b101aw03", 3945 .data = &auo_b101aw03, 3946 }, { 3947 .compatible = "auo,b101xtn01", 3948 .data = &auo_b101xtn01, 3949 }, { 3950 .compatible = "auo,g070vvn01", 3951 .data = &auo_g070vvn01, 3952 }, { 3953 .compatible = "auo,g101evn010", 3954 .data = &auo_g101evn010, 3955 }, { 3956 .compatible = "auo,g104sn02", 3957 .data = &auo_g104sn02, 3958 }, { 3959 .compatible = "auo,g121ean01", 3960 .data = &auo_g121ean01, 3961 }, { 3962 .compatible = "auo,g133han01", 3963 .data = &auo_g133han01, 3964 }, { 3965 .compatible = "auo,g156xtn01", 3966 .data = &auo_g156xtn01, 3967 }, { 3968 .compatible = "auo,g185han01", 3969 .data = &auo_g185han01, 3970 }, { 3971 .compatible = "auo,g190ean01", 3972 .data = &auo_g190ean01, 3973 }, { 3974 .compatible = "auo,p320hvn03", 3975 .data = &auo_p320hvn03, 3976 }, { 3977 .compatible = "auo,t215hvn01", 3978 .data = &auo_t215hvn01, 3979 }, { 3980 .compatible = "avic,tm070ddh03", 3981 .data = &avic_tm070ddh03, 3982 }, { 3983 .compatible = "bananapi,s070wv20-ct16", 3984 .data = &bananapi_s070wv20_ct16, 3985 }, { 3986 .compatible = "boe,hv070wsa-100", 3987 .data = &boe_hv070wsa 3988 }, { 3989 .compatible = "cdtech,s043wq26h-ct7", 3990 .data = &cdtech_s043wq26h_ct7, 3991 }, { 3992 .compatible = "cdtech,s070pws19hp-fc21", 3993 .data = &cdtech_s070pws19hp_fc21, 3994 }, { 3995 .compatible = "cdtech,s070swv29hg-dc44", 3996 .data = &cdtech_s070swv29hg_dc44, 3997 }, { 3998 .compatible = "cdtech,s070wv95-ct16", 3999 .data = &cdtech_s070wv95_ct16, 4000 }, { 4001 .compatible = "chefree,ch101olhlwh-002", 4002 .data = &chefree_ch101olhlwh_002, 4003 }, { 4004 .compatible = "chunghwa,claa070wp03xg", 4005 .data = &chunghwa_claa070wp03xg, 4006 }, { 4007 .compatible = "chunghwa,claa101wa01a", 4008 .data = &chunghwa_claa101wa01a 4009 }, { 4010 .compatible = "chunghwa,claa101wb01", 4011 .data = &chunghwa_claa101wb01 4012 }, { 4013 .compatible = "dataimage,fg040346dsswbg04", 4014 .data = &dataimage_fg040346dsswbg04, 4015 }, { 4016 .compatible = "dataimage,fg1001l0dsswmg01", 4017 .data = &dataimage_fg1001l0dsswmg01, 4018 }, { 4019 .compatible = "dataimage,scf0700c48ggu18", 4020 .data = &dataimage_scf0700c48ggu18, 4021 }, { 4022 .compatible = "dlc,dlc0700yzg-1", 4023 .data = &dlc_dlc0700yzg_1, 4024 }, { 4025 .compatible = "dlc,dlc1010gig", 4026 .data = &dlc_dlc1010gig, 4027 }, { 4028 .compatible = "edt,et035012dm6", 4029 .data = &edt_et035012dm6, 4030 }, { 4031 .compatible = "edt,etm0350g0dh6", 4032 .data = &edt_etm0350g0dh6, 4033 }, { 4034 .compatible = "edt,etm043080dh6gp", 4035 .data = &edt_etm043080dh6gp, 4036 }, { 4037 .compatible = "edt,etm0430g0dh6", 4038 .data = &edt_etm0430g0dh6, 4039 }, { 4040 .compatible = "edt,et057090dhu", 4041 .data = &edt_et057090dhu, 4042 }, { 4043 .compatible = "edt,et070080dh6", 4044 .data = &edt_etm0700g0dh6, 4045 }, { 4046 .compatible = "edt,etm0700g0dh6", 4047 .data = &edt_etm0700g0dh6, 4048 }, { 4049 .compatible = "edt,etm0700g0bdh6", 4050 .data = &edt_etm0700g0bdh6, 4051 }, { 4052 .compatible = "edt,etm0700g0edh6", 4053 .data = &edt_etm0700g0bdh6, 4054 }, { 4055 .compatible = "edt,etml0700y5dha", 4056 .data = &edt_etml0700y5dha, 4057 }, { 4058 .compatible = "edt,etmv570g2dhu", 4059 .data = &edt_etmv570g2dhu, 4060 }, { 4061 .compatible = "eink,vb3300-kca", 4062 .data = &eink_vb3300_kca, 4063 }, { 4064 .compatible = "evervision,vgg804821", 4065 .data = &evervision_vgg804821, 4066 }, { 4067 .compatible = "foxlink,fl500wvr00-a0t", 4068 .data = &foxlink_fl500wvr00_a0t, 4069 }, { 4070 .compatible = "frida,frd350h54004", 4071 .data = &frida_frd350h54004, 4072 }, { 4073 .compatible = "friendlyarm,hd702e", 4074 .data = &friendlyarm_hd702e, 4075 }, { 4076 .compatible = "giantplus,gpg482739qs5", 4077 .data = &giantplus_gpg482739qs5 4078 }, { 4079 .compatible = "giantplus,gpm940b0", 4080 .data = &giantplus_gpm940b0, 4081 }, { 4082 .compatible = "hannstar,hsd070pww1", 4083 .data = &hannstar_hsd070pww1, 4084 }, { 4085 .compatible = "hannstar,hsd100pxn1", 4086 .data = &hannstar_hsd100pxn1, 4087 }, { 4088 .compatible = "hannstar,hsd101pww2", 4089 .data = &hannstar_hsd101pww2, 4090 }, { 4091 .compatible = "hit,tx23d38vm0caa", 4092 .data = &hitachi_tx23d38vm0caa 4093 }, { 4094 .compatible = "innolux,at043tn24", 4095 .data = &innolux_at043tn24, 4096 }, { 4097 .compatible = "innolux,at070tn92", 4098 .data = &innolux_at070tn92, 4099 }, { 4100 .compatible = "innolux,g070y2-l01", 4101 .data = &innolux_g070y2_l01, 4102 }, { 4103 .compatible = "innolux,g070y2-t02", 4104 .data = &innolux_g070y2_t02, 4105 }, { 4106 .compatible = "innolux,g101ice-l01", 4107 .data = &innolux_g101ice_l01 4108 }, { 4109 .compatible = "innolux,g121i1-l01", 4110 .data = &innolux_g121i1_l01 4111 }, { 4112 .compatible = "innolux,g121x1-l03", 4113 .data = &innolux_g121x1_l03, 4114 }, { 4115 .compatible = "innolux,n156bge-l21", 4116 .data = &innolux_n156bge_l21, 4117 }, { 4118 .compatible = "innolux,zj070na-01p", 4119 .data = &innolux_zj070na_01p, 4120 }, { 4121 .compatible = "koe,tx14d24vm1bpa", 4122 .data = &koe_tx14d24vm1bpa, 4123 }, { 4124 .compatible = "koe,tx26d202vm0bwa", 4125 .data = &koe_tx26d202vm0bwa, 4126 }, { 4127 .compatible = "koe,tx31d200vm0baa", 4128 .data = &koe_tx31d200vm0baa, 4129 }, { 4130 .compatible = "kyo,tcg121xglp", 4131 .data = &kyo_tcg121xglp, 4132 }, { 4133 .compatible = "lemaker,bl035-rgb-002", 4134 .data = &lemaker_bl035_rgb_002, 4135 }, { 4136 .compatible = "lg,lb070wv8", 4137 .data = &lg_lb070wv8, 4138 }, { 4139 .compatible = "logicpd,type28", 4140 .data = &logicpd_type_28, 4141 }, { 4142 .compatible = "logictechno,lt161010-2nhc", 4143 .data = &logictechno_lt161010_2nh, 4144 }, { 4145 .compatible = "logictechno,lt161010-2nhr", 4146 .data = &logictechno_lt161010_2nh, 4147 }, { 4148 .compatible = "logictechno,lt170410-2whc", 4149 .data = &logictechno_lt170410_2whc, 4150 }, { 4151 .compatible = "logictechno,lttd800480070-l2rt", 4152 .data = &logictechno_lttd800480070_l2rt, 4153 }, { 4154 .compatible = "logictechno,lttd800480070-l6wh-rt", 4155 .data = &logictechno_lttd800480070_l6wh_rt, 4156 }, { 4157 .compatible = "mitsubishi,aa070mc01-ca1", 4158 .data = &mitsubishi_aa070mc01, 4159 }, { 4160 .compatible = "multi-inno,mi0700s4t-6", 4161 .data = &multi_inno_mi0700s4t_6, 4162 }, { 4163 .compatible = "multi-inno,mi0800ft-9", 4164 .data = &multi_inno_mi0800ft_9, 4165 }, { 4166 .compatible = "multi-inno,mi1010ait-1cp", 4167 .data = &multi_inno_mi1010ait_1cp, 4168 }, { 4169 .compatible = "nec,nl12880bc20-05", 4170 .data = &nec_nl12880bc20_05, 4171 }, { 4172 .compatible = "nec,nl4827hc19-05b", 4173 .data = &nec_nl4827hc19_05b, 4174 }, { 4175 .compatible = "netron-dy,e231732", 4176 .data = &netron_dy_e231732, 4177 }, { 4178 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4179 .data = &newhaven_nhd_43_480272ef_atxl, 4180 }, { 4181 .compatible = "nlt,nl192108ac18-02d", 4182 .data = &nlt_nl192108ac18_02d, 4183 }, { 4184 .compatible = "nvd,9128", 4185 .data = &nvd_9128, 4186 }, { 4187 .compatible = "okaya,rs800480t-7x0gp", 4188 .data = &okaya_rs800480t_7x0gp, 4189 }, { 4190 .compatible = "olimex,lcd-olinuxino-43-ts", 4191 .data = &olimex_lcd_olinuxino_43ts, 4192 }, { 4193 .compatible = "ontat,yx700wv03", 4194 .data = &ontat_yx700wv03, 4195 }, { 4196 .compatible = "ortustech,com37h3m05dtc", 4197 .data = &ortustech_com37h3m, 4198 }, { 4199 .compatible = "ortustech,com37h3m99dtc", 4200 .data = &ortustech_com37h3m, 4201 }, { 4202 .compatible = "ortustech,com43h4m85ulc", 4203 .data = &ortustech_com43h4m85ulc, 4204 }, { 4205 .compatible = "osddisplays,osd070t1718-19ts", 4206 .data = &osddisplays_osd070t1718_19ts, 4207 }, { 4208 .compatible = "pda,91-00156-a0", 4209 .data = &pda_91_00156_a0, 4210 }, { 4211 .compatible = "powertip,ph800480t013-idf02", 4212 .data = &powertip_ph800480t013_idf02, 4213 }, { 4214 .compatible = "qiaodian,qd43003c0-40", 4215 .data = &qd43003c0_40, 4216 }, { 4217 .compatible = "qishenglong,gopher2b-lcd", 4218 .data = &qishenglong_gopher2b_lcd, 4219 }, { 4220 .compatible = "rocktech,rk070er9427", 4221 .data = &rocktech_rk070er9427, 4222 }, { 4223 .compatible = "rocktech,rk101ii01d-ct", 4224 .data = &rocktech_rk101ii01d_ct, 4225 }, { 4226 .compatible = "samsung,ltl101al01", 4227 .data = &samsung_ltl101al01, 4228 }, { 4229 .compatible = "samsung,ltn101nt05", 4230 .data = &samsung_ltn101nt05, 4231 }, { 4232 .compatible = "satoz,sat050at40h12r2", 4233 .data = &satoz_sat050at40h12r2, 4234 }, { 4235 .compatible = "sharp,lq035q7db03", 4236 .data = &sharp_lq035q7db03, 4237 }, { 4238 .compatible = "sharp,lq070y3dg3b", 4239 .data = &sharp_lq070y3dg3b, 4240 }, { 4241 .compatible = "sharp,lq101k1ly04", 4242 .data = &sharp_lq101k1ly04, 4243 }, { 4244 .compatible = "sharp,ls020b1dd01d", 4245 .data = &sharp_ls020b1dd01d, 4246 }, { 4247 .compatible = "shelly,sca07010-bfn-lnn", 4248 .data = &shelly_sca07010_bfn_lnn, 4249 }, { 4250 .compatible = "starry,kr070pe2t", 4251 .data = &starry_kr070pe2t, 4252 }, { 4253 .compatible = "startek,kd070wvfpa", 4254 .data = &startek_kd070wvfpa, 4255 }, { 4256 .compatible = "team-source-display,tst043015cmhx", 4257 .data = &tsd_tst043015cmhx, 4258 }, { 4259 .compatible = "tfc,s9700rtwv43tr-01b", 4260 .data = &tfc_s9700rtwv43tr_01b, 4261 }, { 4262 .compatible = "tianma,tm070jdhg30", 4263 .data = &tianma_tm070jdhg30, 4264 }, { 4265 .compatible = "tianma,tm070jvhg33", 4266 .data = &tianma_tm070jvhg33, 4267 }, { 4268 .compatible = "tianma,tm070rvhg71", 4269 .data = &tianma_tm070rvhg71, 4270 }, { 4271 .compatible = "ti,nspire-cx-lcd-panel", 4272 .data = &ti_nspire_cx_lcd_panel, 4273 }, { 4274 .compatible = "ti,nspire-classic-lcd-panel", 4275 .data = &ti_nspire_classic_lcd_panel, 4276 }, { 4277 .compatible = "toshiba,lt089ac29000", 4278 .data = &toshiba_lt089ac29000, 4279 }, { 4280 .compatible = "tpk,f07a-0102", 4281 .data = &tpk_f07a_0102, 4282 }, { 4283 .compatible = "tpk,f10a-0102", 4284 .data = &tpk_f10a_0102, 4285 }, { 4286 .compatible = "urt,umsh-8596md-t", 4287 .data = &urt_umsh_8596md_parallel, 4288 }, { 4289 .compatible = "urt,umsh-8596md-1t", 4290 .data = &urt_umsh_8596md_parallel, 4291 }, { 4292 .compatible = "urt,umsh-8596md-7t", 4293 .data = &urt_umsh_8596md_parallel, 4294 }, { 4295 .compatible = "urt,umsh-8596md-11t", 4296 .data = &urt_umsh_8596md_lvds, 4297 }, { 4298 .compatible = "urt,umsh-8596md-19t", 4299 .data = &urt_umsh_8596md_lvds, 4300 }, { 4301 .compatible = "urt,umsh-8596md-20t", 4302 .data = &urt_umsh_8596md_parallel, 4303 }, { 4304 .compatible = "vivax,tpc9150-panel", 4305 .data = &vivax_tpc9150_panel, 4306 }, { 4307 .compatible = "vxt,vl050-8048nt-c01", 4308 .data = &vl050_8048nt_c01, 4309 }, { 4310 .compatible = "winstar,wf35ltiacd", 4311 .data = &winstar_wf35ltiacd, 4312 }, { 4313 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4314 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4315 }, { 4316 /* Must be the last entry */ 4317 .compatible = "panel-dpi", 4318 .data = &panel_dpi, 4319 }, { 4320 /* sentinel */ 4321 } 4322 }; 4323 MODULE_DEVICE_TABLE(of, platform_of_match); 4324 4325 static int panel_simple_platform_probe(struct platform_device *pdev) 4326 { 4327 const struct of_device_id *id; 4328 4329 id = of_match_node(platform_of_match, pdev->dev.of_node); 4330 if (!id) 4331 return -ENODEV; 4332 4333 return panel_simple_probe(&pdev->dev, id->data); 4334 } 4335 4336 static int panel_simple_platform_remove(struct platform_device *pdev) 4337 { 4338 panel_simple_remove(&pdev->dev); 4339 4340 return 0; 4341 } 4342 4343 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4344 { 4345 panel_simple_shutdown(&pdev->dev); 4346 } 4347 4348 static const struct dev_pm_ops panel_simple_pm_ops = { 4349 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4350 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4351 pm_runtime_force_resume) 4352 }; 4353 4354 static struct platform_driver panel_simple_platform_driver = { 4355 .driver = { 4356 .name = "panel-simple", 4357 .of_match_table = platform_of_match, 4358 .pm = &panel_simple_pm_ops, 4359 }, 4360 .probe = panel_simple_platform_probe, 4361 .remove = panel_simple_platform_remove, 4362 .shutdown = panel_simple_platform_shutdown, 4363 }; 4364 4365 struct panel_desc_dsi { 4366 struct panel_desc desc; 4367 4368 unsigned long flags; 4369 enum mipi_dsi_pixel_format format; 4370 unsigned int lanes; 4371 }; 4372 4373 static const struct drm_display_mode auo_b080uan01_mode = { 4374 .clock = 154500, 4375 .hdisplay = 1200, 4376 .hsync_start = 1200 + 62, 4377 .hsync_end = 1200 + 62 + 4, 4378 .htotal = 1200 + 62 + 4 + 62, 4379 .vdisplay = 1920, 4380 .vsync_start = 1920 + 9, 4381 .vsync_end = 1920 + 9 + 2, 4382 .vtotal = 1920 + 9 + 2 + 8, 4383 }; 4384 4385 static const struct panel_desc_dsi auo_b080uan01 = { 4386 .desc = { 4387 .modes = &auo_b080uan01_mode, 4388 .num_modes = 1, 4389 .bpc = 8, 4390 .size = { 4391 .width = 108, 4392 .height = 272, 4393 }, 4394 .connector_type = DRM_MODE_CONNECTOR_DSI, 4395 }, 4396 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4397 .format = MIPI_DSI_FMT_RGB888, 4398 .lanes = 4, 4399 }; 4400 4401 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4402 .clock = 160000, 4403 .hdisplay = 1200, 4404 .hsync_start = 1200 + 120, 4405 .hsync_end = 1200 + 120 + 20, 4406 .htotal = 1200 + 120 + 20 + 21, 4407 .vdisplay = 1920, 4408 .vsync_start = 1920 + 21, 4409 .vsync_end = 1920 + 21 + 3, 4410 .vtotal = 1920 + 21 + 3 + 18, 4411 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4412 }; 4413 4414 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4415 .desc = { 4416 .modes = &boe_tv080wum_nl0_mode, 4417 .num_modes = 1, 4418 .size = { 4419 .width = 107, 4420 .height = 172, 4421 }, 4422 .connector_type = DRM_MODE_CONNECTOR_DSI, 4423 }, 4424 .flags = MIPI_DSI_MODE_VIDEO | 4425 MIPI_DSI_MODE_VIDEO_BURST | 4426 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4427 .format = MIPI_DSI_FMT_RGB888, 4428 .lanes = 4, 4429 }; 4430 4431 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4432 .clock = 71000, 4433 .hdisplay = 800, 4434 .hsync_start = 800 + 32, 4435 .hsync_end = 800 + 32 + 1, 4436 .htotal = 800 + 32 + 1 + 57, 4437 .vdisplay = 1280, 4438 .vsync_start = 1280 + 28, 4439 .vsync_end = 1280 + 28 + 1, 4440 .vtotal = 1280 + 28 + 1 + 14, 4441 }; 4442 4443 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4444 .desc = { 4445 .modes = &lg_ld070wx3_sl01_mode, 4446 .num_modes = 1, 4447 .bpc = 8, 4448 .size = { 4449 .width = 94, 4450 .height = 151, 4451 }, 4452 .connector_type = DRM_MODE_CONNECTOR_DSI, 4453 }, 4454 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4455 .format = MIPI_DSI_FMT_RGB888, 4456 .lanes = 4, 4457 }; 4458 4459 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4460 .clock = 67000, 4461 .hdisplay = 720, 4462 .hsync_start = 720 + 12, 4463 .hsync_end = 720 + 12 + 4, 4464 .htotal = 720 + 12 + 4 + 112, 4465 .vdisplay = 1280, 4466 .vsync_start = 1280 + 8, 4467 .vsync_end = 1280 + 8 + 4, 4468 .vtotal = 1280 + 8 + 4 + 12, 4469 }; 4470 4471 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4472 .desc = { 4473 .modes = &lg_lh500wx1_sd03_mode, 4474 .num_modes = 1, 4475 .bpc = 8, 4476 .size = { 4477 .width = 62, 4478 .height = 110, 4479 }, 4480 .connector_type = DRM_MODE_CONNECTOR_DSI, 4481 }, 4482 .flags = MIPI_DSI_MODE_VIDEO, 4483 .format = MIPI_DSI_FMT_RGB888, 4484 .lanes = 4, 4485 }; 4486 4487 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4488 .clock = 157200, 4489 .hdisplay = 1920, 4490 .hsync_start = 1920 + 154, 4491 .hsync_end = 1920 + 154 + 16, 4492 .htotal = 1920 + 154 + 16 + 32, 4493 .vdisplay = 1200, 4494 .vsync_start = 1200 + 17, 4495 .vsync_end = 1200 + 17 + 2, 4496 .vtotal = 1200 + 17 + 2 + 16, 4497 }; 4498 4499 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4500 .desc = { 4501 .modes = &panasonic_vvx10f004b00_mode, 4502 .num_modes = 1, 4503 .bpc = 8, 4504 .size = { 4505 .width = 217, 4506 .height = 136, 4507 }, 4508 .connector_type = DRM_MODE_CONNECTOR_DSI, 4509 }, 4510 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4511 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4512 .format = MIPI_DSI_FMT_RGB888, 4513 .lanes = 4, 4514 }; 4515 4516 static const struct drm_display_mode lg_acx467akm_7_mode = { 4517 .clock = 150000, 4518 .hdisplay = 1080, 4519 .hsync_start = 1080 + 2, 4520 .hsync_end = 1080 + 2 + 2, 4521 .htotal = 1080 + 2 + 2 + 2, 4522 .vdisplay = 1920, 4523 .vsync_start = 1920 + 2, 4524 .vsync_end = 1920 + 2 + 2, 4525 .vtotal = 1920 + 2 + 2 + 2, 4526 }; 4527 4528 static const struct panel_desc_dsi lg_acx467akm_7 = { 4529 .desc = { 4530 .modes = &lg_acx467akm_7_mode, 4531 .num_modes = 1, 4532 .bpc = 8, 4533 .size = { 4534 .width = 62, 4535 .height = 110, 4536 }, 4537 .connector_type = DRM_MODE_CONNECTOR_DSI, 4538 }, 4539 .flags = 0, 4540 .format = MIPI_DSI_FMT_RGB888, 4541 .lanes = 4, 4542 }; 4543 4544 static const struct drm_display_mode osd101t2045_53ts_mode = { 4545 .clock = 154500, 4546 .hdisplay = 1920, 4547 .hsync_start = 1920 + 112, 4548 .hsync_end = 1920 + 112 + 16, 4549 .htotal = 1920 + 112 + 16 + 32, 4550 .vdisplay = 1200, 4551 .vsync_start = 1200 + 16, 4552 .vsync_end = 1200 + 16 + 2, 4553 .vtotal = 1200 + 16 + 2 + 16, 4554 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4555 }; 4556 4557 static const struct panel_desc_dsi osd101t2045_53ts = { 4558 .desc = { 4559 .modes = &osd101t2045_53ts_mode, 4560 .num_modes = 1, 4561 .bpc = 8, 4562 .size = { 4563 .width = 217, 4564 .height = 136, 4565 }, 4566 .connector_type = DRM_MODE_CONNECTOR_DSI, 4567 }, 4568 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4569 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4570 MIPI_DSI_MODE_NO_EOT_PACKET, 4571 .format = MIPI_DSI_FMT_RGB888, 4572 .lanes = 4, 4573 }; 4574 4575 static const struct of_device_id dsi_of_match[] = { 4576 { 4577 .compatible = "auo,b080uan01", 4578 .data = &auo_b080uan01 4579 }, { 4580 .compatible = "boe,tv080wum-nl0", 4581 .data = &boe_tv080wum_nl0 4582 }, { 4583 .compatible = "lg,ld070wx3-sl01", 4584 .data = &lg_ld070wx3_sl01 4585 }, { 4586 .compatible = "lg,lh500wx1-sd03", 4587 .data = &lg_lh500wx1_sd03 4588 }, { 4589 .compatible = "panasonic,vvx10f004b00", 4590 .data = &panasonic_vvx10f004b00 4591 }, { 4592 .compatible = "lg,acx467akm-7", 4593 .data = &lg_acx467akm_7 4594 }, { 4595 .compatible = "osddisplays,osd101t2045-53ts", 4596 .data = &osd101t2045_53ts 4597 }, { 4598 /* sentinel */ 4599 } 4600 }; 4601 MODULE_DEVICE_TABLE(of, dsi_of_match); 4602 4603 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4604 { 4605 const struct panel_desc_dsi *desc; 4606 const struct of_device_id *id; 4607 int err; 4608 4609 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4610 if (!id) 4611 return -ENODEV; 4612 4613 desc = id->data; 4614 4615 err = panel_simple_probe(&dsi->dev, &desc->desc); 4616 if (err < 0) 4617 return err; 4618 4619 dsi->mode_flags = desc->flags; 4620 dsi->format = desc->format; 4621 dsi->lanes = desc->lanes; 4622 4623 err = mipi_dsi_attach(dsi); 4624 if (err) { 4625 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4626 4627 drm_panel_remove(&panel->base); 4628 } 4629 4630 return err; 4631 } 4632 4633 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4634 { 4635 int err; 4636 4637 err = mipi_dsi_detach(dsi); 4638 if (err < 0) 4639 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4640 4641 panel_simple_remove(&dsi->dev); 4642 } 4643 4644 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4645 { 4646 panel_simple_shutdown(&dsi->dev); 4647 } 4648 4649 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4650 .driver = { 4651 .name = "panel-simple-dsi", 4652 .of_match_table = dsi_of_match, 4653 .pm = &panel_simple_pm_ops, 4654 }, 4655 .probe = panel_simple_dsi_probe, 4656 .remove = panel_simple_dsi_remove, 4657 .shutdown = panel_simple_dsi_shutdown, 4658 }; 4659 4660 static int __init panel_simple_init(void) 4661 { 4662 int err; 4663 4664 err = platform_driver_register(&panel_simple_platform_driver); 4665 if (err < 0) 4666 return err; 4667 4668 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4669 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4670 if (err < 0) 4671 goto err_did_platform_register; 4672 } 4673 4674 return 0; 4675 4676 err_did_platform_register: 4677 platform_driver_unregister(&panel_simple_platform_driver); 4678 4679 return err; 4680 } 4681 module_init(panel_simple_init); 4682 4683 static void __exit panel_simple_exit(void) 4684 { 4685 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4686 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4687 4688 platform_driver_unregister(&panel_simple_platform_driver); 4689 } 4690 module_exit(panel_simple_exit); 4691 4692 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4693 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4694 MODULE_LICENSE("GPL and additional rights"); 4695