1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_panel.h> 41 42 /** 43 * struct panel_desc - Describes a simple panel. 44 */ 45 struct panel_desc { 46 /** 47 * @modes: Pointer to array of fixed modes appropriate for this panel. 48 * 49 * If only one mode then this can just be the address of the mode. 50 * NOTE: cannot be used with "timings" and also if this is specified 51 * then you cannot override the mode in the device tree. 52 */ 53 const struct drm_display_mode *modes; 54 55 /** @num_modes: Number of elements in modes array. */ 56 unsigned int num_modes; 57 58 /** 59 * @timings: Pointer to array of display timings 60 * 61 * NOTE: cannot be used with "modes" and also these will be used to 62 * validate a device tree override if one is present. 63 */ 64 const struct display_timing *timings; 65 66 /** @num_timings: Number of elements in timings array. */ 67 unsigned int num_timings; 68 69 /** @bpc: Bits per color. */ 70 unsigned int bpc; 71 72 /** @size: Structure containing the physical size of this panel. */ 73 struct { 74 /** 75 * @size.width: Width (in mm) of the active display area. 76 */ 77 unsigned int width; 78 79 /** 80 * @size.height: Height (in mm) of the active display area. 81 */ 82 unsigned int height; 83 } size; 84 85 /** @delay: Structure containing various delay values for this panel. */ 86 struct { 87 /** 88 * @delay.prepare: Time for the panel to become ready. 89 * 90 * The time (in milliseconds) that it takes for the panel to 91 * become ready and start receiving video data 92 */ 93 unsigned int prepare; 94 95 /** 96 * @delay.enable: Time for the panel to display a valid frame. 97 * 98 * The time (in milliseconds) that it takes for the panel to 99 * display the first valid frame after starting to receive 100 * video data. 101 */ 102 unsigned int enable; 103 104 /** 105 * @delay.disable: Time for the panel to turn the display off. 106 * 107 * The time (in milliseconds) that it takes for the panel to 108 * turn the display off (no content is visible). 109 */ 110 unsigned int disable; 111 112 /** 113 * @delay.unprepare: Time to power down completely. 114 * 115 * The time (in milliseconds) that it takes for the panel 116 * to power itself down completely. 117 * 118 * This time is used to prevent a future "prepare" from 119 * starting until at least this many milliseconds has passed. 120 * If at prepare time less time has passed since unprepare 121 * finished, the driver waits for the remaining time. 122 */ 123 unsigned int unprepare; 124 } delay; 125 126 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 127 u32 bus_format; 128 129 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 130 u32 bus_flags; 131 132 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 133 int connector_type; 134 }; 135 136 struct panel_simple { 137 struct drm_panel base; 138 bool enabled; 139 140 bool prepared; 141 142 ktime_t prepared_time; 143 ktime_t unprepared_time; 144 145 const struct panel_desc *desc; 146 147 struct regulator *supply; 148 struct i2c_adapter *ddc; 149 150 struct gpio_desc *enable_gpio; 151 152 struct edid *edid; 153 154 struct drm_display_mode override_mode; 155 156 enum drm_panel_orientation orientation; 157 }; 158 159 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 160 { 161 return container_of(panel, struct panel_simple, base); 162 } 163 164 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 165 struct drm_connector *connector) 166 { 167 struct drm_display_mode *mode; 168 unsigned int i, num = 0; 169 170 for (i = 0; i < panel->desc->num_timings; i++) { 171 const struct display_timing *dt = &panel->desc->timings[i]; 172 struct videomode vm; 173 174 videomode_from_timing(dt, &vm); 175 mode = drm_mode_create(connector->dev); 176 if (!mode) { 177 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 178 dt->hactive.typ, dt->vactive.typ); 179 continue; 180 } 181 182 drm_display_mode_from_videomode(&vm, mode); 183 184 mode->type |= DRM_MODE_TYPE_DRIVER; 185 186 if (panel->desc->num_timings == 1) 187 mode->type |= DRM_MODE_TYPE_PREFERRED; 188 189 drm_mode_probed_add(connector, mode); 190 num++; 191 } 192 193 return num; 194 } 195 196 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 197 struct drm_connector *connector) 198 { 199 struct drm_display_mode *mode; 200 unsigned int i, num = 0; 201 202 for (i = 0; i < panel->desc->num_modes; i++) { 203 const struct drm_display_mode *m = &panel->desc->modes[i]; 204 205 mode = drm_mode_duplicate(connector->dev, m); 206 if (!mode) { 207 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 208 m->hdisplay, m->vdisplay, 209 drm_mode_vrefresh(m)); 210 continue; 211 } 212 213 mode->type |= DRM_MODE_TYPE_DRIVER; 214 215 if (panel->desc->num_modes == 1) 216 mode->type |= DRM_MODE_TYPE_PREFERRED; 217 218 drm_mode_set_name(mode); 219 220 drm_mode_probed_add(connector, mode); 221 num++; 222 } 223 224 return num; 225 } 226 227 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 228 struct drm_connector *connector) 229 { 230 struct drm_display_mode *mode; 231 bool has_override = panel->override_mode.type; 232 unsigned int num = 0; 233 234 if (!panel->desc) 235 return 0; 236 237 if (has_override) { 238 mode = drm_mode_duplicate(connector->dev, 239 &panel->override_mode); 240 if (mode) { 241 drm_mode_probed_add(connector, mode); 242 num = 1; 243 } else { 244 dev_err(panel->base.dev, "failed to add override mode\n"); 245 } 246 } 247 248 /* Only add timings if override was not there or failed to validate */ 249 if (num == 0 && panel->desc->num_timings) 250 num = panel_simple_get_timings_modes(panel, connector); 251 252 /* 253 * Only add fixed modes if timings/override added no mode. 254 * 255 * We should only ever have either the display timings specified 256 * or a fixed mode. Anything else is rather bogus. 257 */ 258 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 259 if (num == 0) 260 num = panel_simple_get_display_modes(panel, connector); 261 262 connector->display_info.bpc = panel->desc->bpc; 263 connector->display_info.width_mm = panel->desc->size.width; 264 connector->display_info.height_mm = panel->desc->size.height; 265 if (panel->desc->bus_format) 266 drm_display_info_set_bus_formats(&connector->display_info, 267 &panel->desc->bus_format, 1); 268 connector->display_info.bus_flags = panel->desc->bus_flags; 269 270 return num; 271 } 272 273 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 274 { 275 ktime_t now_ktime, min_ktime; 276 277 if (!min_ms) 278 return; 279 280 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 281 now_ktime = ktime_get(); 282 283 if (ktime_before(now_ktime, min_ktime)) 284 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 285 } 286 287 static int panel_simple_disable(struct drm_panel *panel) 288 { 289 struct panel_simple *p = to_panel_simple(panel); 290 291 if (!p->enabled) 292 return 0; 293 294 if (p->desc->delay.disable) 295 msleep(p->desc->delay.disable); 296 297 p->enabled = false; 298 299 return 0; 300 } 301 302 static int panel_simple_suspend(struct device *dev) 303 { 304 struct panel_simple *p = dev_get_drvdata(dev); 305 306 gpiod_set_value_cansleep(p->enable_gpio, 0); 307 regulator_disable(p->supply); 308 p->unprepared_time = ktime_get(); 309 310 kfree(p->edid); 311 p->edid = NULL; 312 313 return 0; 314 } 315 316 static int panel_simple_unprepare(struct drm_panel *panel) 317 { 318 struct panel_simple *p = to_panel_simple(panel); 319 int ret; 320 321 /* Unpreparing when already unprepared is a no-op */ 322 if (!p->prepared) 323 return 0; 324 325 pm_runtime_mark_last_busy(panel->dev); 326 ret = pm_runtime_put_autosuspend(panel->dev); 327 if (ret < 0) 328 return ret; 329 p->prepared = false; 330 331 return 0; 332 } 333 334 static int panel_simple_resume(struct device *dev) 335 { 336 struct panel_simple *p = dev_get_drvdata(dev); 337 int err; 338 339 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 340 341 err = regulator_enable(p->supply); 342 if (err < 0) { 343 dev_err(dev, "failed to enable supply: %d\n", err); 344 return err; 345 } 346 347 gpiod_set_value_cansleep(p->enable_gpio, 1); 348 349 if (p->desc->delay.prepare) 350 msleep(p->desc->delay.prepare); 351 352 p->prepared_time = ktime_get(); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 554 { 555 struct panel_simple *panel; 556 struct display_timing dt; 557 struct device_node *ddc; 558 int connector_type; 559 u32 bus_flags; 560 int err; 561 562 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 563 if (!panel) 564 return -ENOMEM; 565 566 panel->enabled = false; 567 panel->prepared_time = 0; 568 panel->desc = desc; 569 570 panel->supply = devm_regulator_get(dev, "power"); 571 if (IS_ERR(panel->supply)) 572 return PTR_ERR(panel->supply); 573 574 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 575 GPIOD_OUT_LOW); 576 if (IS_ERR(panel->enable_gpio)) { 577 err = PTR_ERR(panel->enable_gpio); 578 if (err != -EPROBE_DEFER) 579 dev_err(dev, "failed to request GPIO: %d\n", err); 580 return err; 581 } 582 583 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 584 if (err) { 585 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 586 return err; 587 } 588 589 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 590 if (ddc) { 591 panel->ddc = of_find_i2c_adapter_by_node(ddc); 592 of_node_put(ddc); 593 594 if (!panel->ddc) 595 return -EPROBE_DEFER; 596 } 597 598 if (desc == &panel_dpi) { 599 /* Handle the generic panel-dpi binding */ 600 err = panel_dpi_probe(dev, panel); 601 if (err) 602 goto free_ddc; 603 desc = panel->desc; 604 } else { 605 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 606 panel_simple_parse_panel_timing_node(dev, panel, &dt); 607 } 608 609 connector_type = desc->connector_type; 610 /* Catch common mistakes for panels. */ 611 switch (connector_type) { 612 case 0: 613 dev_warn(dev, "Specify missing connector_type\n"); 614 connector_type = DRM_MODE_CONNECTOR_DPI; 615 break; 616 case DRM_MODE_CONNECTOR_LVDS: 617 WARN_ON(desc->bus_flags & 618 ~(DRM_BUS_FLAG_DE_LOW | 619 DRM_BUS_FLAG_DE_HIGH | 620 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 621 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 622 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 624 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 625 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 626 desc->bpc != 6); 627 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 628 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 629 desc->bpc != 8); 630 break; 631 case DRM_MODE_CONNECTOR_eDP: 632 dev_warn(dev, "eDP panels moved to panel-edp\n"); 633 err = -EINVAL; 634 goto free_ddc; 635 case DRM_MODE_CONNECTOR_DSI: 636 if (desc->bpc != 6 && desc->bpc != 8) 637 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 638 break; 639 case DRM_MODE_CONNECTOR_DPI: 640 bus_flags = DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 643 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 644 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 645 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 646 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 647 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 648 if (desc->bus_flags & ~bus_flags) 649 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 650 if (!(desc->bus_flags & bus_flags)) 651 dev_warn(dev, "Specify missing bus_flags\n"); 652 if (desc->bus_format == 0) 653 dev_warn(dev, "Specify missing bus_format\n"); 654 if (desc->bpc != 6 && desc->bpc != 8) 655 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 656 break; 657 default: 658 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 659 connector_type = DRM_MODE_CONNECTOR_DPI; 660 break; 661 } 662 663 dev_set_drvdata(dev, panel); 664 665 /* 666 * We use runtime PM for prepare / unprepare since those power the panel 667 * on and off and those can be very slow operations. This is important 668 * to optimize powering the panel on briefly to read the EDID before 669 * fully enabling the panel. 670 */ 671 pm_runtime_enable(dev); 672 pm_runtime_set_autosuspend_delay(dev, 1000); 673 pm_runtime_use_autosuspend(dev); 674 675 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 676 677 err = drm_panel_of_backlight(&panel->base); 678 if (err) { 679 dev_err_probe(dev, err, "Could not find backlight\n"); 680 goto disable_pm_runtime; 681 } 682 683 drm_panel_add(&panel->base); 684 685 return 0; 686 687 disable_pm_runtime: 688 pm_runtime_dont_use_autosuspend(dev); 689 pm_runtime_disable(dev); 690 free_ddc: 691 if (panel->ddc) 692 put_device(&panel->ddc->dev); 693 694 return err; 695 } 696 697 static int panel_simple_remove(struct device *dev) 698 { 699 struct panel_simple *panel = dev_get_drvdata(dev); 700 701 drm_panel_remove(&panel->base); 702 drm_panel_disable(&panel->base); 703 drm_panel_unprepare(&panel->base); 704 705 pm_runtime_dont_use_autosuspend(dev); 706 pm_runtime_disable(dev); 707 if (panel->ddc) 708 put_device(&panel->ddc->dev); 709 710 return 0; 711 } 712 713 static void panel_simple_shutdown(struct device *dev) 714 { 715 struct panel_simple *panel = dev_get_drvdata(dev); 716 717 drm_panel_disable(&panel->base); 718 drm_panel_unprepare(&panel->base); 719 } 720 721 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 722 .clock = 71100, 723 .hdisplay = 1280, 724 .hsync_start = 1280 + 40, 725 .hsync_end = 1280 + 40 + 80, 726 .htotal = 1280 + 40 + 80 + 40, 727 .vdisplay = 800, 728 .vsync_start = 800 + 3, 729 .vsync_end = 800 + 3 + 10, 730 .vtotal = 800 + 3 + 10 + 10, 731 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 732 }; 733 734 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 735 .modes = &ire_am_1280800n3tzqw_t00h_mode, 736 .num_modes = 1, 737 .bpc = 8, 738 .size = { 739 .width = 217, 740 .height = 136, 741 }, 742 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 744 .connector_type = DRM_MODE_CONNECTOR_LVDS, 745 }; 746 747 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 748 .clock = 9000, 749 .hdisplay = 480, 750 .hsync_start = 480 + 2, 751 .hsync_end = 480 + 2 + 41, 752 .htotal = 480 + 2 + 41 + 2, 753 .vdisplay = 272, 754 .vsync_start = 272 + 2, 755 .vsync_end = 272 + 2 + 10, 756 .vtotal = 272 + 2 + 10 + 2, 757 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 758 }; 759 760 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 761 .modes = &ire_am_480272h3tmqw_t01h_mode, 762 .num_modes = 1, 763 .bpc = 8, 764 .size = { 765 .width = 105, 766 .height = 67, 767 }, 768 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 769 }; 770 771 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 772 .clock = 33333, 773 .hdisplay = 800, 774 .hsync_start = 800 + 0, 775 .hsync_end = 800 + 0 + 255, 776 .htotal = 800 + 0 + 255 + 0, 777 .vdisplay = 480, 778 .vsync_start = 480 + 2, 779 .vsync_end = 480 + 2 + 45, 780 .vtotal = 480 + 2 + 45 + 0, 781 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 782 }; 783 784 static const struct panel_desc ampire_am800480r3tmqwa1h = { 785 .modes = &ire_am800480r3tmqwa1h_mode, 786 .num_modes = 1, 787 .bpc = 6, 788 .size = { 789 .width = 152, 790 .height = 91, 791 }, 792 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 793 }; 794 795 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 796 .pixelclock = { 34500000, 39600000, 50400000 }, 797 .hactive = { 800, 800, 800 }, 798 .hfront_porch = { 12, 112, 312 }, 799 .hback_porch = { 87, 87, 48 }, 800 .hsync_len = { 1, 1, 40 }, 801 .vactive = { 600, 600, 600 }, 802 .vfront_porch = { 1, 21, 61 }, 803 .vback_porch = { 38, 38, 19 }, 804 .vsync_len = { 1, 1, 20 }, 805 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 806 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 807 DISPLAY_FLAGS_SYNC_POSEDGE, 808 }; 809 810 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 811 .timings = &ire_am800600p5tmqw_tb8h_timing, 812 .num_timings = 1, 813 .bpc = 6, 814 .size = { 815 .width = 162, 816 .height = 122, 817 }, 818 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 820 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 821 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 822 .connector_type = DRM_MODE_CONNECTOR_DPI, 823 }; 824 825 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 826 .pixelclock = { 26400000, 33300000, 46800000 }, 827 .hactive = { 800, 800, 800 }, 828 .hfront_porch = { 16, 210, 354 }, 829 .hback_porch = { 45, 36, 6 }, 830 .hsync_len = { 1, 10, 40 }, 831 .vactive = { 480, 480, 480 }, 832 .vfront_porch = { 7, 22, 147 }, 833 .vback_porch = { 22, 13, 3 }, 834 .vsync_len = { 1, 10, 20 }, 835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 837 }; 838 839 static const struct panel_desc armadeus_st0700_adapt = { 840 .timings = &santek_st0700i5y_rbslw_f_timing, 841 .num_timings = 1, 842 .bpc = 6, 843 .size = { 844 .width = 154, 845 .height = 86, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 849 }; 850 851 static const struct drm_display_mode auo_b101aw03_mode = { 852 .clock = 51450, 853 .hdisplay = 1024, 854 .hsync_start = 1024 + 156, 855 .hsync_end = 1024 + 156 + 8, 856 .htotal = 1024 + 156 + 8 + 156, 857 .vdisplay = 600, 858 .vsync_start = 600 + 16, 859 .vsync_end = 600 + 16 + 6, 860 .vtotal = 600 + 16 + 6 + 16, 861 }; 862 863 static const struct panel_desc auo_b101aw03 = { 864 .modes = &auo_b101aw03_mode, 865 .num_modes = 1, 866 .bpc = 6, 867 .size = { 868 .width = 223, 869 .height = 125, 870 }, 871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 872 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 873 .connector_type = DRM_MODE_CONNECTOR_LVDS, 874 }; 875 876 static const struct drm_display_mode auo_b101xtn01_mode = { 877 .clock = 72000, 878 .hdisplay = 1366, 879 .hsync_start = 1366 + 20, 880 .hsync_end = 1366 + 20 + 70, 881 .htotal = 1366 + 20 + 70, 882 .vdisplay = 768, 883 .vsync_start = 768 + 14, 884 .vsync_end = 768 + 14 + 42, 885 .vtotal = 768 + 14 + 42, 886 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 887 }; 888 889 static const struct panel_desc auo_b101xtn01 = { 890 .modes = &auo_b101xtn01_mode, 891 .num_modes = 1, 892 .bpc = 6, 893 .size = { 894 .width = 223, 895 .height = 125, 896 }, 897 }; 898 899 static const struct display_timing auo_g070vvn01_timings = { 900 .pixelclock = { 33300000, 34209000, 45000000 }, 901 .hactive = { 800, 800, 800 }, 902 .hfront_porch = { 20, 40, 200 }, 903 .hback_porch = { 87, 40, 1 }, 904 .hsync_len = { 1, 48, 87 }, 905 .vactive = { 480, 480, 480 }, 906 .vfront_porch = { 5, 13, 200 }, 907 .vback_porch = { 31, 31, 29 }, 908 .vsync_len = { 1, 1, 3 }, 909 }; 910 911 static const struct panel_desc auo_g070vvn01 = { 912 .timings = &auo_g070vvn01_timings, 913 .num_timings = 1, 914 .bpc = 8, 915 .size = { 916 .width = 152, 917 .height = 91, 918 }, 919 .delay = { 920 .prepare = 200, 921 .enable = 50, 922 .disable = 50, 923 .unprepare = 1000, 924 }, 925 }; 926 927 static const struct drm_display_mode auo_g101evn010_mode = { 928 .clock = 68930, 929 .hdisplay = 1280, 930 .hsync_start = 1280 + 82, 931 .hsync_end = 1280 + 82 + 2, 932 .htotal = 1280 + 82 + 2 + 84, 933 .vdisplay = 800, 934 .vsync_start = 800 + 8, 935 .vsync_end = 800 + 8 + 2, 936 .vtotal = 800 + 8 + 2 + 6, 937 }; 938 939 static const struct panel_desc auo_g101evn010 = { 940 .modes = &auo_g101evn010_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 216, 945 .height = 135, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .connector_type = DRM_MODE_CONNECTOR_LVDS, 949 }; 950 951 static const struct drm_display_mode auo_g104sn02_mode = { 952 .clock = 40000, 953 .hdisplay = 800, 954 .hsync_start = 800 + 40, 955 .hsync_end = 800 + 40 + 216, 956 .htotal = 800 + 40 + 216 + 128, 957 .vdisplay = 600, 958 .vsync_start = 600 + 10, 959 .vsync_end = 600 + 10 + 35, 960 .vtotal = 600 + 10 + 35 + 2, 961 }; 962 963 static const struct panel_desc auo_g104sn02 = { 964 .modes = &auo_g104sn02_mode, 965 .num_modes = 1, 966 .bpc = 8, 967 .size = { 968 .width = 211, 969 .height = 158, 970 }, 971 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 972 .connector_type = DRM_MODE_CONNECTOR_LVDS, 973 }; 974 975 static const struct drm_display_mode auo_g121ean01_mode = { 976 .clock = 66700, 977 .hdisplay = 1280, 978 .hsync_start = 1280 + 58, 979 .hsync_end = 1280 + 58 + 8, 980 .htotal = 1280 + 58 + 8 + 70, 981 .vdisplay = 800, 982 .vsync_start = 800 + 6, 983 .vsync_end = 800 + 6 + 4, 984 .vtotal = 800 + 6 + 4 + 10, 985 }; 986 987 static const struct panel_desc auo_g121ean01 = { 988 .modes = &auo_g121ean01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 261, 993 .height = 163, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g133han01_timings = { 1000 .pixelclock = { 134000000, 141200000, 149000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 39, 58, 77 }, 1003 .hback_porch = { 59, 88, 117 }, 1004 .hsync_len = { 28, 42, 56 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 3, 8, 11 }, 1007 .vback_porch = { 5, 14, 19 }, 1008 .vsync_len = { 4, 14, 19 }, 1009 }; 1010 1011 static const struct panel_desc auo_g133han01 = { 1012 .timings = &auo_g133han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 293, 1017 .height = 165, 1018 }, 1019 .delay = { 1020 .prepare = 200, 1021 .enable = 50, 1022 .disable = 50, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct drm_display_mode auo_g156xtn01_mode = { 1030 .clock = 76000, 1031 .hdisplay = 1366, 1032 .hsync_start = 1366 + 33, 1033 .hsync_end = 1366 + 33 + 67, 1034 .htotal = 1560, 1035 .vdisplay = 768, 1036 .vsync_start = 768 + 4, 1037 .vsync_end = 768 + 4 + 4, 1038 .vtotal = 806, 1039 }; 1040 1041 static const struct panel_desc auo_g156xtn01 = { 1042 .modes = &auo_g156xtn01_mode, 1043 .num_modes = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 344, 1047 .height = 194, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1051 }; 1052 1053 static const struct display_timing auo_g185han01_timings = { 1054 .pixelclock = { 120000000, 144000000, 175000000 }, 1055 .hactive = { 1920, 1920, 1920 }, 1056 .hfront_porch = { 36, 120, 148 }, 1057 .hback_porch = { 24, 88, 108 }, 1058 .hsync_len = { 20, 48, 64 }, 1059 .vactive = { 1080, 1080, 1080 }, 1060 .vfront_porch = { 6, 10, 40 }, 1061 .vback_porch = { 2, 5, 20 }, 1062 .vsync_len = { 2, 5, 20 }, 1063 }; 1064 1065 static const struct panel_desc auo_g185han01 = { 1066 .timings = &auo_g185han01_timings, 1067 .num_timings = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 409, 1071 .height = 230, 1072 }, 1073 .delay = { 1074 .prepare = 50, 1075 .enable = 200, 1076 .disable = 110, 1077 .unprepare = 1000, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g190ean01_timings = { 1084 .pixelclock = { 90000000, 108000000, 135000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 126, 184, 1266 }, 1087 .hback_porch = { 84, 122, 844 }, 1088 .hsync_len = { 70, 102, 704 }, 1089 .vactive = { 1024, 1024, 1024 }, 1090 .vfront_porch = { 4, 26, 76 }, 1091 .vback_porch = { 2, 8, 25 }, 1092 .vsync_len = { 2, 8, 25 }, 1093 }; 1094 1095 static const struct panel_desc auo_g190ean01 = { 1096 .timings = &auo_g190ean01_timings, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 376, 1101 .height = 301, 1102 }, 1103 .delay = { 1104 .prepare = 50, 1105 .enable = 200, 1106 .disable = 110, 1107 .unprepare = 1000, 1108 }, 1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1111 }; 1112 1113 static const struct display_timing auo_p320hvn03_timings = { 1114 .pixelclock = { 106000000, 148500000, 164000000 }, 1115 .hactive = { 1920, 1920, 1920 }, 1116 .hfront_porch = { 25, 50, 130 }, 1117 .hback_porch = { 25, 50, 130 }, 1118 .hsync_len = { 20, 40, 105 }, 1119 .vactive = { 1080, 1080, 1080 }, 1120 .vfront_porch = { 8, 17, 150 }, 1121 .vback_porch = { 8, 17, 150 }, 1122 .vsync_len = { 4, 11, 100 }, 1123 }; 1124 1125 static const struct panel_desc auo_p320hvn03 = { 1126 .timings = &auo_p320hvn03_timings, 1127 .num_timings = 1, 1128 .bpc = 8, 1129 .size = { 1130 .width = 698, 1131 .height = 393, 1132 }, 1133 .delay = { 1134 .prepare = 1, 1135 .enable = 450, 1136 .unprepare = 500, 1137 }, 1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1139 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1140 }; 1141 1142 static const struct drm_display_mode auo_t215hvn01_mode = { 1143 .clock = 148800, 1144 .hdisplay = 1920, 1145 .hsync_start = 1920 + 88, 1146 .hsync_end = 1920 + 88 + 44, 1147 .htotal = 1920 + 88 + 44 + 148, 1148 .vdisplay = 1080, 1149 .vsync_start = 1080 + 4, 1150 .vsync_end = 1080 + 4 + 5, 1151 .vtotal = 1080 + 4 + 5 + 36, 1152 }; 1153 1154 static const struct panel_desc auo_t215hvn01 = { 1155 .modes = &auo_t215hvn01_mode, 1156 .num_modes = 1, 1157 .bpc = 8, 1158 .size = { 1159 .width = 430, 1160 .height = 270, 1161 }, 1162 .delay = { 1163 .disable = 5, 1164 .unprepare = 1000, 1165 } 1166 }; 1167 1168 static const struct drm_display_mode avic_tm070ddh03_mode = { 1169 .clock = 51200, 1170 .hdisplay = 1024, 1171 .hsync_start = 1024 + 160, 1172 .hsync_end = 1024 + 160 + 4, 1173 .htotal = 1024 + 160 + 4 + 156, 1174 .vdisplay = 600, 1175 .vsync_start = 600 + 17, 1176 .vsync_end = 600 + 17 + 1, 1177 .vtotal = 600 + 17 + 1 + 17, 1178 }; 1179 1180 static const struct panel_desc avic_tm070ddh03 = { 1181 .modes = &avic_tm070ddh03_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 154, 1186 .height = 90, 1187 }, 1188 .delay = { 1189 .prepare = 20, 1190 .enable = 200, 1191 .disable = 200, 1192 }, 1193 }; 1194 1195 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1196 .clock = 30000, 1197 .hdisplay = 800, 1198 .hsync_start = 800 + 40, 1199 .hsync_end = 800 + 40 + 48, 1200 .htotal = 800 + 40 + 48 + 40, 1201 .vdisplay = 480, 1202 .vsync_start = 480 + 13, 1203 .vsync_end = 480 + 13 + 3, 1204 .vtotal = 480 + 13 + 3 + 29, 1205 }; 1206 1207 static const struct panel_desc bananapi_s070wv20_ct16 = { 1208 .modes = &bananapi_s070wv20_ct16_mode, 1209 .num_modes = 1, 1210 .bpc = 6, 1211 .size = { 1212 .width = 154, 1213 .height = 86, 1214 }, 1215 }; 1216 1217 static const struct drm_display_mode boe_hv070wsa_mode = { 1218 .clock = 42105, 1219 .hdisplay = 1024, 1220 .hsync_start = 1024 + 30, 1221 .hsync_end = 1024 + 30 + 30, 1222 .htotal = 1024 + 30 + 30 + 30, 1223 .vdisplay = 600, 1224 .vsync_start = 600 + 10, 1225 .vsync_end = 600 + 10 + 10, 1226 .vtotal = 600 + 10 + 10 + 10, 1227 }; 1228 1229 static const struct panel_desc boe_hv070wsa = { 1230 .modes = &boe_hv070wsa_mode, 1231 .num_modes = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 154, 1235 .height = 90, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1240 }; 1241 1242 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1243 .clock = 9000, 1244 .hdisplay = 480, 1245 .hsync_start = 480 + 5, 1246 .hsync_end = 480 + 5 + 5, 1247 .htotal = 480 + 5 + 5 + 40, 1248 .vdisplay = 272, 1249 .vsync_start = 272 + 8, 1250 .vsync_end = 272 + 8 + 8, 1251 .vtotal = 272 + 8 + 8 + 8, 1252 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1253 }; 1254 1255 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1256 .modes = &cdtech_s043wq26h_ct7_mode, 1257 .num_modes = 1, 1258 .bpc = 8, 1259 .size = { 1260 .width = 95, 1261 .height = 54, 1262 }, 1263 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1264 }; 1265 1266 /* S070PWS19HP-FC21 2017/04/22 */ 1267 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1268 .clock = 51200, 1269 .hdisplay = 1024, 1270 .hsync_start = 1024 + 160, 1271 .hsync_end = 1024 + 160 + 20, 1272 .htotal = 1024 + 160 + 20 + 140, 1273 .vdisplay = 600, 1274 .vsync_start = 600 + 12, 1275 .vsync_end = 600 + 12 + 3, 1276 .vtotal = 600 + 12 + 3 + 20, 1277 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1278 }; 1279 1280 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1281 .modes = &cdtech_s070pws19hp_fc21_mode, 1282 .num_modes = 1, 1283 .bpc = 6, 1284 .size = { 1285 .width = 154, 1286 .height = 86, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1289 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1290 .connector_type = DRM_MODE_CONNECTOR_DPI, 1291 }; 1292 1293 /* S070SWV29HG-DC44 2017/09/21 */ 1294 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1295 .clock = 33300, 1296 .hdisplay = 800, 1297 .hsync_start = 800 + 210, 1298 .hsync_end = 800 + 210 + 2, 1299 .htotal = 800 + 210 + 2 + 44, 1300 .vdisplay = 480, 1301 .vsync_start = 480 + 22, 1302 .vsync_end = 480 + 22 + 2, 1303 .vtotal = 480 + 22 + 2 + 21, 1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1305 }; 1306 1307 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1308 .modes = &cdtech_s070swv29hg_dc44_mode, 1309 .num_modes = 1, 1310 .bpc = 6, 1311 .size = { 1312 .width = 154, 1313 .height = 86, 1314 }, 1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1317 .connector_type = DRM_MODE_CONNECTOR_DPI, 1318 }; 1319 1320 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1321 .clock = 35000, 1322 .hdisplay = 800, 1323 .hsync_start = 800 + 40, 1324 .hsync_end = 800 + 40 + 40, 1325 .htotal = 800 + 40 + 40 + 48, 1326 .vdisplay = 480, 1327 .vsync_start = 480 + 29, 1328 .vsync_end = 480 + 29 + 13, 1329 .vtotal = 480 + 29 + 13 + 3, 1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1331 }; 1332 1333 static const struct panel_desc cdtech_s070wv95_ct16 = { 1334 .modes = &cdtech_s070wv95_ct16_mode, 1335 .num_modes = 1, 1336 .bpc = 8, 1337 .size = { 1338 .width = 154, 1339 .height = 85, 1340 }, 1341 }; 1342 1343 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1344 .pixelclock = { 68900000, 71100000, 73400000 }, 1345 .hactive = { 1280, 1280, 1280 }, 1346 .hfront_porch = { 65, 80, 95 }, 1347 .hback_porch = { 64, 79, 94 }, 1348 .hsync_len = { 1, 1, 1 }, 1349 .vactive = { 800, 800, 800 }, 1350 .vfront_porch = { 7, 11, 14 }, 1351 .vback_porch = { 7, 11, 14 }, 1352 .vsync_len = { 1, 1, 1 }, 1353 .flags = DISPLAY_FLAGS_DE_HIGH, 1354 }; 1355 1356 static const struct panel_desc chefree_ch101olhlwh_002 = { 1357 .timings = &chefree_ch101olhlwh_002_timing, 1358 .num_timings = 1, 1359 .bpc = 8, 1360 .size = { 1361 .width = 217, 1362 .height = 135, 1363 }, 1364 .delay = { 1365 .enable = 200, 1366 .disable = 200, 1367 }, 1368 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1371 }; 1372 1373 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1374 .clock = 66770, 1375 .hdisplay = 800, 1376 .hsync_start = 800 + 49, 1377 .hsync_end = 800 + 49 + 33, 1378 .htotal = 800 + 49 + 33 + 17, 1379 .vdisplay = 1280, 1380 .vsync_start = 1280 + 1, 1381 .vsync_end = 1280 + 1 + 7, 1382 .vtotal = 1280 + 1 + 7 + 15, 1383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1384 }; 1385 1386 static const struct panel_desc chunghwa_claa070wp03xg = { 1387 .modes = &chunghwa_claa070wp03xg_mode, 1388 .num_modes = 1, 1389 .bpc = 6, 1390 .size = { 1391 .width = 94, 1392 .height = 150, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1395 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1396 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1397 }; 1398 1399 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1400 .clock = 72070, 1401 .hdisplay = 1366, 1402 .hsync_start = 1366 + 58, 1403 .hsync_end = 1366 + 58 + 58, 1404 .htotal = 1366 + 58 + 58 + 58, 1405 .vdisplay = 768, 1406 .vsync_start = 768 + 4, 1407 .vsync_end = 768 + 4 + 4, 1408 .vtotal = 768 + 4 + 4 + 4, 1409 }; 1410 1411 static const struct panel_desc chunghwa_claa101wa01a = { 1412 .modes = &chunghwa_claa101wa01a_mode, 1413 .num_modes = 1, 1414 .bpc = 6, 1415 .size = { 1416 .width = 220, 1417 .height = 120, 1418 }, 1419 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1420 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1421 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1422 }; 1423 1424 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1425 .clock = 69300, 1426 .hdisplay = 1366, 1427 .hsync_start = 1366 + 48, 1428 .hsync_end = 1366 + 48 + 32, 1429 .htotal = 1366 + 48 + 32 + 20, 1430 .vdisplay = 768, 1431 .vsync_start = 768 + 16, 1432 .vsync_end = 768 + 16 + 8, 1433 .vtotal = 768 + 16 + 8 + 16, 1434 }; 1435 1436 static const struct panel_desc chunghwa_claa101wb01 = { 1437 .modes = &chunghwa_claa101wb01_mode, 1438 .num_modes = 1, 1439 .bpc = 6, 1440 .size = { 1441 .width = 223, 1442 .height = 125, 1443 }, 1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1446 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1447 }; 1448 1449 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1450 .pixelclock = { 5000000, 9000000, 12000000 }, 1451 .hactive = { 480, 480, 480 }, 1452 .hfront_porch = { 12, 12, 12 }, 1453 .hback_porch = { 12, 12, 12 }, 1454 .hsync_len = { 21, 21, 21 }, 1455 .vactive = { 272, 272, 272 }, 1456 .vfront_porch = { 4, 4, 4 }, 1457 .vback_porch = { 4, 4, 4 }, 1458 .vsync_len = { 8, 8, 8 }, 1459 }; 1460 1461 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1462 .timings = &dataimage_fg040346dsswbg04_timing, 1463 .num_timings = 1, 1464 .bpc = 8, 1465 .size = { 1466 .width = 95, 1467 .height = 54, 1468 }, 1469 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1470 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1471 .connector_type = DRM_MODE_CONNECTOR_DPI, 1472 }; 1473 1474 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1475 .pixelclock = { 68900000, 71110000, 73400000 }, 1476 .hactive = { 1280, 1280, 1280 }, 1477 .vactive = { 800, 800, 800 }, 1478 .hback_porch = { 100, 100, 100 }, 1479 .hfront_porch = { 100, 100, 100 }, 1480 .vback_porch = { 5, 5, 5 }, 1481 .vfront_porch = { 5, 5, 5 }, 1482 .hsync_len = { 24, 24, 24 }, 1483 .vsync_len = { 3, 3, 3 }, 1484 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1485 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1486 }; 1487 1488 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1489 .timings = &dataimage_fg1001l0dsswmg01_timing, 1490 .num_timings = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 217, 1494 .height = 136, 1495 }, 1496 }; 1497 1498 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1499 .clock = 33260, 1500 .hdisplay = 800, 1501 .hsync_start = 800 + 40, 1502 .hsync_end = 800 + 40 + 128, 1503 .htotal = 800 + 40 + 128 + 88, 1504 .vdisplay = 480, 1505 .vsync_start = 480 + 10, 1506 .vsync_end = 480 + 10 + 2, 1507 .vtotal = 480 + 10 + 2 + 33, 1508 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1509 }; 1510 1511 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1512 .modes = &dataimage_scf0700c48ggu18_mode, 1513 .num_modes = 1, 1514 .bpc = 8, 1515 .size = { 1516 .width = 152, 1517 .height = 91, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1521 }; 1522 1523 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1524 .pixelclock = { 45000000, 51200000, 57000000 }, 1525 .hactive = { 1024, 1024, 1024 }, 1526 .hfront_porch = { 100, 106, 113 }, 1527 .hback_porch = { 100, 106, 113 }, 1528 .hsync_len = { 100, 108, 114 }, 1529 .vactive = { 600, 600, 600 }, 1530 .vfront_porch = { 8, 11, 15 }, 1531 .vback_porch = { 8, 11, 15 }, 1532 .vsync_len = { 9, 13, 15 }, 1533 .flags = DISPLAY_FLAGS_DE_HIGH, 1534 }; 1535 1536 static const struct panel_desc dlc_dlc0700yzg_1 = { 1537 .timings = &dlc_dlc0700yzg_1_timing, 1538 .num_timings = 1, 1539 .bpc = 6, 1540 .size = { 1541 .width = 154, 1542 .height = 86, 1543 }, 1544 .delay = { 1545 .prepare = 30, 1546 .enable = 200, 1547 .disable = 200, 1548 }, 1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1551 }; 1552 1553 static const struct display_timing dlc_dlc1010gig_timing = { 1554 .pixelclock = { 68900000, 71100000, 73400000 }, 1555 .hactive = { 1280, 1280, 1280 }, 1556 .hfront_porch = { 43, 53, 63 }, 1557 .hback_porch = { 43, 53, 63 }, 1558 .hsync_len = { 44, 54, 64 }, 1559 .vactive = { 800, 800, 800 }, 1560 .vfront_porch = { 5, 8, 11 }, 1561 .vback_porch = { 5, 8, 11 }, 1562 .vsync_len = { 5, 7, 11 }, 1563 .flags = DISPLAY_FLAGS_DE_HIGH, 1564 }; 1565 1566 static const struct panel_desc dlc_dlc1010gig = { 1567 .timings = &dlc_dlc1010gig_timing, 1568 .num_timings = 1, 1569 .bpc = 8, 1570 .size = { 1571 .width = 216, 1572 .height = 135, 1573 }, 1574 .delay = { 1575 .prepare = 60, 1576 .enable = 150, 1577 .disable = 100, 1578 .unprepare = 60, 1579 }, 1580 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1581 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1582 }; 1583 1584 static const struct drm_display_mode edt_et035012dm6_mode = { 1585 .clock = 6500, 1586 .hdisplay = 320, 1587 .hsync_start = 320 + 20, 1588 .hsync_end = 320 + 20 + 30, 1589 .htotal = 320 + 20 + 68, 1590 .vdisplay = 240, 1591 .vsync_start = 240 + 4, 1592 .vsync_end = 240 + 4 + 4, 1593 .vtotal = 240 + 4 + 4 + 14, 1594 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1595 }; 1596 1597 static const struct panel_desc edt_et035012dm6 = { 1598 .modes = &edt_et035012dm6_mode, 1599 .num_modes = 1, 1600 .bpc = 8, 1601 .size = { 1602 .width = 70, 1603 .height = 52, 1604 }, 1605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1606 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1607 }; 1608 1609 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1610 .clock = 6520, 1611 .hdisplay = 320, 1612 .hsync_start = 320 + 20, 1613 .hsync_end = 320 + 20 + 68, 1614 .htotal = 320 + 20 + 68, 1615 .vdisplay = 240, 1616 .vsync_start = 240 + 4, 1617 .vsync_end = 240 + 4 + 18, 1618 .vtotal = 240 + 4 + 18, 1619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1620 }; 1621 1622 static const struct panel_desc edt_etm0350g0dh6 = { 1623 .modes = &edt_etm0350g0dh6_mode, 1624 .num_modes = 1, 1625 .bpc = 6, 1626 .size = { 1627 .width = 70, 1628 .height = 53, 1629 }, 1630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1632 .connector_type = DRM_MODE_CONNECTOR_DPI, 1633 }; 1634 1635 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1636 .clock = 10870, 1637 .hdisplay = 480, 1638 .hsync_start = 480 + 8, 1639 .hsync_end = 480 + 8 + 4, 1640 .htotal = 480 + 8 + 4 + 41, 1641 1642 /* 1643 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1644 * fb_align 1645 */ 1646 1647 .vdisplay = 288, 1648 .vsync_start = 288 + 2, 1649 .vsync_end = 288 + 2 + 4, 1650 .vtotal = 288 + 2 + 4 + 10, 1651 }; 1652 1653 static const struct panel_desc edt_etm043080dh6gp = { 1654 .modes = &edt_etm043080dh6gp_mode, 1655 .num_modes = 1, 1656 .bpc = 8, 1657 .size = { 1658 .width = 100, 1659 .height = 65, 1660 }, 1661 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1662 .connector_type = DRM_MODE_CONNECTOR_DPI, 1663 }; 1664 1665 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1666 .clock = 9000, 1667 .hdisplay = 480, 1668 .hsync_start = 480 + 2, 1669 .hsync_end = 480 + 2 + 41, 1670 .htotal = 480 + 2 + 41 + 2, 1671 .vdisplay = 272, 1672 .vsync_start = 272 + 2, 1673 .vsync_end = 272 + 2 + 10, 1674 .vtotal = 272 + 2 + 10 + 2, 1675 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1676 }; 1677 1678 static const struct panel_desc edt_etm0430g0dh6 = { 1679 .modes = &edt_etm0430g0dh6_mode, 1680 .num_modes = 1, 1681 .bpc = 6, 1682 .size = { 1683 .width = 95, 1684 .height = 54, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1687 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1688 .connector_type = DRM_MODE_CONNECTOR_DPI, 1689 }; 1690 1691 static const struct drm_display_mode edt_et057090dhu_mode = { 1692 .clock = 25175, 1693 .hdisplay = 640, 1694 .hsync_start = 640 + 16, 1695 .hsync_end = 640 + 16 + 30, 1696 .htotal = 640 + 16 + 30 + 114, 1697 .vdisplay = 480, 1698 .vsync_start = 480 + 10, 1699 .vsync_end = 480 + 10 + 3, 1700 .vtotal = 480 + 10 + 3 + 32, 1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1702 }; 1703 1704 static const struct panel_desc edt_et057090dhu = { 1705 .modes = &edt_et057090dhu_mode, 1706 .num_modes = 1, 1707 .bpc = 6, 1708 .size = { 1709 .width = 115, 1710 .height = 86, 1711 }, 1712 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1713 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1714 .connector_type = DRM_MODE_CONNECTOR_DPI, 1715 }; 1716 1717 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1718 .clock = 33260, 1719 .hdisplay = 800, 1720 .hsync_start = 800 + 40, 1721 .hsync_end = 800 + 40 + 128, 1722 .htotal = 800 + 40 + 128 + 88, 1723 .vdisplay = 480, 1724 .vsync_start = 480 + 10, 1725 .vsync_end = 480 + 10 + 2, 1726 .vtotal = 480 + 10 + 2 + 33, 1727 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1728 }; 1729 1730 static const struct panel_desc edt_etm0700g0dh6 = { 1731 .modes = &edt_etm0700g0dh6_mode, 1732 .num_modes = 1, 1733 .bpc = 6, 1734 .size = { 1735 .width = 152, 1736 .height = 91, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1740 .connector_type = DRM_MODE_CONNECTOR_DPI, 1741 }; 1742 1743 static const struct panel_desc edt_etm0700g0bdh6 = { 1744 .modes = &edt_etm0700g0dh6_mode, 1745 .num_modes = 1, 1746 .bpc = 6, 1747 .size = { 1748 .width = 152, 1749 .height = 91, 1750 }, 1751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1753 .connector_type = DRM_MODE_CONNECTOR_DPI, 1754 }; 1755 1756 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1757 .clock = 25175, 1758 .hdisplay = 640, 1759 .hsync_start = 640, 1760 .hsync_end = 640 + 16, 1761 .htotal = 640 + 16 + 30 + 114, 1762 .vdisplay = 480, 1763 .vsync_start = 480 + 10, 1764 .vsync_end = 480 + 10 + 3, 1765 .vtotal = 480 + 10 + 3 + 35, 1766 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1767 }; 1768 1769 static const struct panel_desc edt_etmv570g2dhu = { 1770 .modes = &edt_etmv570g2dhu_mode, 1771 .num_modes = 1, 1772 .bpc = 6, 1773 .size = { 1774 .width = 115, 1775 .height = 86, 1776 }, 1777 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1778 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1779 .connector_type = DRM_MODE_CONNECTOR_DPI, 1780 }; 1781 1782 static const struct display_timing eink_vb3300_kca_timing = { 1783 .pixelclock = { 40000000, 40000000, 40000000 }, 1784 .hactive = { 334, 334, 334 }, 1785 .hfront_porch = { 1, 1, 1 }, 1786 .hback_porch = { 1, 1, 1 }, 1787 .hsync_len = { 1, 1, 1 }, 1788 .vactive = { 1405, 1405, 1405 }, 1789 .vfront_porch = { 1, 1, 1 }, 1790 .vback_porch = { 1, 1, 1 }, 1791 .vsync_len = { 1, 1, 1 }, 1792 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1793 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1794 }; 1795 1796 static const struct panel_desc eink_vb3300_kca = { 1797 .timings = &eink_vb3300_kca_timing, 1798 .num_timings = 1, 1799 .bpc = 6, 1800 .size = { 1801 .width = 157, 1802 .height = 209, 1803 }, 1804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1806 .connector_type = DRM_MODE_CONNECTOR_DPI, 1807 }; 1808 1809 static const struct display_timing evervision_vgg804821_timing = { 1810 .pixelclock = { 27600000, 33300000, 50000000 }, 1811 .hactive = { 800, 800, 800 }, 1812 .hfront_porch = { 40, 66, 70 }, 1813 .hback_porch = { 40, 67, 70 }, 1814 .hsync_len = { 40, 67, 70 }, 1815 .vactive = { 480, 480, 480 }, 1816 .vfront_porch = { 6, 10, 10 }, 1817 .vback_porch = { 7, 11, 11 }, 1818 .vsync_len = { 7, 11, 11 }, 1819 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1820 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1821 DISPLAY_FLAGS_SYNC_NEGEDGE, 1822 }; 1823 1824 static const struct panel_desc evervision_vgg804821 = { 1825 .timings = &evervision_vgg804821_timing, 1826 .num_timings = 1, 1827 .bpc = 8, 1828 .size = { 1829 .width = 108, 1830 .height = 64, 1831 }, 1832 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1833 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1834 }; 1835 1836 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1837 .clock = 32260, 1838 .hdisplay = 800, 1839 .hsync_start = 800 + 168, 1840 .hsync_end = 800 + 168 + 64, 1841 .htotal = 800 + 168 + 64 + 88, 1842 .vdisplay = 480, 1843 .vsync_start = 480 + 37, 1844 .vsync_end = 480 + 37 + 2, 1845 .vtotal = 480 + 37 + 2 + 8, 1846 }; 1847 1848 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1849 .modes = &foxlink_fl500wvr00_a0t_mode, 1850 .num_modes = 1, 1851 .bpc = 8, 1852 .size = { 1853 .width = 108, 1854 .height = 65, 1855 }, 1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1857 }; 1858 1859 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1860 { /* 60 Hz */ 1861 .clock = 6000, 1862 .hdisplay = 320, 1863 .hsync_start = 320 + 44, 1864 .hsync_end = 320 + 44 + 16, 1865 .htotal = 320 + 44 + 16 + 20, 1866 .vdisplay = 240, 1867 .vsync_start = 240 + 2, 1868 .vsync_end = 240 + 2 + 6, 1869 .vtotal = 240 + 2 + 6 + 2, 1870 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1871 }, 1872 { /* 50 Hz */ 1873 .clock = 5400, 1874 .hdisplay = 320, 1875 .hsync_start = 320 + 56, 1876 .hsync_end = 320 + 56 + 16, 1877 .htotal = 320 + 56 + 16 + 40, 1878 .vdisplay = 240, 1879 .vsync_start = 240 + 2, 1880 .vsync_end = 240 + 2 + 6, 1881 .vtotal = 240 + 2 + 6 + 2, 1882 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1883 }, 1884 }; 1885 1886 static const struct panel_desc frida_frd350h54004 = { 1887 .modes = frida_frd350h54004_modes, 1888 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1889 .bpc = 8, 1890 .size = { 1891 .width = 77, 1892 .height = 64, 1893 }, 1894 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1896 .connector_type = DRM_MODE_CONNECTOR_DPI, 1897 }; 1898 1899 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1900 .clock = 67185, 1901 .hdisplay = 800, 1902 .hsync_start = 800 + 20, 1903 .hsync_end = 800 + 20 + 24, 1904 .htotal = 800 + 20 + 24 + 20, 1905 .vdisplay = 1280, 1906 .vsync_start = 1280 + 4, 1907 .vsync_end = 1280 + 4 + 8, 1908 .vtotal = 1280 + 4 + 8 + 4, 1909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1910 }; 1911 1912 static const struct panel_desc friendlyarm_hd702e = { 1913 .modes = &friendlyarm_hd702e_mode, 1914 .num_modes = 1, 1915 .size = { 1916 .width = 94, 1917 .height = 151, 1918 }, 1919 }; 1920 1921 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1922 .clock = 9000, 1923 .hdisplay = 480, 1924 .hsync_start = 480 + 5, 1925 .hsync_end = 480 + 5 + 1, 1926 .htotal = 480 + 5 + 1 + 40, 1927 .vdisplay = 272, 1928 .vsync_start = 272 + 8, 1929 .vsync_end = 272 + 8 + 1, 1930 .vtotal = 272 + 8 + 1 + 8, 1931 }; 1932 1933 static const struct panel_desc giantplus_gpg482739qs5 = { 1934 .modes = &giantplus_gpg482739qs5_mode, 1935 .num_modes = 1, 1936 .bpc = 8, 1937 .size = { 1938 .width = 95, 1939 .height = 54, 1940 }, 1941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1942 }; 1943 1944 static const struct display_timing giantplus_gpm940b0_timing = { 1945 .pixelclock = { 13500000, 27000000, 27500000 }, 1946 .hactive = { 320, 320, 320 }, 1947 .hfront_porch = { 14, 686, 718 }, 1948 .hback_porch = { 50, 70, 255 }, 1949 .hsync_len = { 1, 1, 1 }, 1950 .vactive = { 240, 240, 240 }, 1951 .vfront_porch = { 1, 1, 179 }, 1952 .vback_porch = { 1, 21, 31 }, 1953 .vsync_len = { 1, 1, 6 }, 1954 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1955 }; 1956 1957 static const struct panel_desc giantplus_gpm940b0 = { 1958 .timings = &giantplus_gpm940b0_timing, 1959 .num_timings = 1, 1960 .bpc = 8, 1961 .size = { 1962 .width = 60, 1963 .height = 45, 1964 }, 1965 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1966 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1967 }; 1968 1969 static const struct display_timing hannstar_hsd070pww1_timing = { 1970 .pixelclock = { 64300000, 71100000, 82000000 }, 1971 .hactive = { 1280, 1280, 1280 }, 1972 .hfront_porch = { 1, 1, 10 }, 1973 .hback_porch = { 1, 1, 10 }, 1974 /* 1975 * According to the data sheet, the minimum horizontal blanking interval 1976 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1977 * minimum working horizontal blanking interval to be 60 clocks. 1978 */ 1979 .hsync_len = { 58, 158, 661 }, 1980 .vactive = { 800, 800, 800 }, 1981 .vfront_porch = { 1, 1, 10 }, 1982 .vback_porch = { 1, 1, 10 }, 1983 .vsync_len = { 1, 21, 203 }, 1984 .flags = DISPLAY_FLAGS_DE_HIGH, 1985 }; 1986 1987 static const struct panel_desc hannstar_hsd070pww1 = { 1988 .timings = &hannstar_hsd070pww1_timing, 1989 .num_timings = 1, 1990 .bpc = 6, 1991 .size = { 1992 .width = 151, 1993 .height = 94, 1994 }, 1995 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1997 }; 1998 1999 static const struct display_timing hannstar_hsd100pxn1_timing = { 2000 .pixelclock = { 55000000, 65000000, 75000000 }, 2001 .hactive = { 1024, 1024, 1024 }, 2002 .hfront_porch = { 40, 40, 40 }, 2003 .hback_porch = { 220, 220, 220 }, 2004 .hsync_len = { 20, 60, 100 }, 2005 .vactive = { 768, 768, 768 }, 2006 .vfront_porch = { 7, 7, 7 }, 2007 .vback_porch = { 21, 21, 21 }, 2008 .vsync_len = { 10, 10, 10 }, 2009 .flags = DISPLAY_FLAGS_DE_HIGH, 2010 }; 2011 2012 static const struct panel_desc hannstar_hsd100pxn1 = { 2013 .timings = &hannstar_hsd100pxn1_timing, 2014 .num_timings = 1, 2015 .bpc = 6, 2016 .size = { 2017 .width = 203, 2018 .height = 152, 2019 }, 2020 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2021 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2022 }; 2023 2024 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2025 .clock = 33333, 2026 .hdisplay = 800, 2027 .hsync_start = 800 + 85, 2028 .hsync_end = 800 + 85 + 86, 2029 .htotal = 800 + 85 + 86 + 85, 2030 .vdisplay = 480, 2031 .vsync_start = 480 + 16, 2032 .vsync_end = 480 + 16 + 13, 2033 .vtotal = 480 + 16 + 13 + 16, 2034 }; 2035 2036 static const struct panel_desc hitachi_tx23d38vm0caa = { 2037 .modes = &hitachi_tx23d38vm0caa_mode, 2038 .num_modes = 1, 2039 .bpc = 6, 2040 .size = { 2041 .width = 195, 2042 .height = 117, 2043 }, 2044 .delay = { 2045 .enable = 160, 2046 .disable = 160, 2047 }, 2048 }; 2049 2050 static const struct drm_display_mode innolux_at043tn24_mode = { 2051 .clock = 9000, 2052 .hdisplay = 480, 2053 .hsync_start = 480 + 2, 2054 .hsync_end = 480 + 2 + 41, 2055 .htotal = 480 + 2 + 41 + 2, 2056 .vdisplay = 272, 2057 .vsync_start = 272 + 2, 2058 .vsync_end = 272 + 2 + 10, 2059 .vtotal = 272 + 2 + 10 + 2, 2060 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2061 }; 2062 2063 static const struct panel_desc innolux_at043tn24 = { 2064 .modes = &innolux_at043tn24_mode, 2065 .num_modes = 1, 2066 .bpc = 8, 2067 .size = { 2068 .width = 95, 2069 .height = 54, 2070 }, 2071 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2072 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2073 }; 2074 2075 static const struct drm_display_mode innolux_at070tn92_mode = { 2076 .clock = 33333, 2077 .hdisplay = 800, 2078 .hsync_start = 800 + 210, 2079 .hsync_end = 800 + 210 + 20, 2080 .htotal = 800 + 210 + 20 + 46, 2081 .vdisplay = 480, 2082 .vsync_start = 480 + 22, 2083 .vsync_end = 480 + 22 + 10, 2084 .vtotal = 480 + 22 + 23 + 10, 2085 }; 2086 2087 static const struct panel_desc innolux_at070tn92 = { 2088 .modes = &innolux_at070tn92_mode, 2089 .num_modes = 1, 2090 .size = { 2091 .width = 154, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2095 }; 2096 2097 static const struct display_timing innolux_g070y2_l01_timing = { 2098 .pixelclock = { 28000000, 29500000, 32000000 }, 2099 .hactive = { 800, 800, 800 }, 2100 .hfront_porch = { 61, 91, 141 }, 2101 .hback_porch = { 60, 90, 140 }, 2102 .hsync_len = { 12, 12, 12 }, 2103 .vactive = { 480, 480, 480 }, 2104 .vfront_porch = { 4, 9, 30 }, 2105 .vback_porch = { 4, 8, 28 }, 2106 .vsync_len = { 2, 2, 2 }, 2107 .flags = DISPLAY_FLAGS_DE_HIGH, 2108 }; 2109 2110 static const struct panel_desc innolux_g070y2_l01 = { 2111 .timings = &innolux_g070y2_l01_timing, 2112 .num_timings = 1, 2113 .bpc = 8, 2114 .size = { 2115 .width = 152, 2116 .height = 91, 2117 }, 2118 .delay = { 2119 .prepare = 10, 2120 .enable = 100, 2121 .disable = 100, 2122 .unprepare = 800, 2123 }, 2124 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2125 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2126 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2127 }; 2128 2129 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2130 .clock = 33333, 2131 .hdisplay = 800, 2132 .hsync_start = 800 + 210, 2133 .hsync_end = 800 + 210 + 20, 2134 .htotal = 800 + 210 + 20 + 46, 2135 .vdisplay = 480, 2136 .vsync_start = 480 + 22, 2137 .vsync_end = 480 + 22 + 10, 2138 .vtotal = 480 + 22 + 23 + 10, 2139 }; 2140 2141 static const struct panel_desc innolux_g070y2_t02 = { 2142 .modes = &innolux_g070y2_t02_mode, 2143 .num_modes = 1, 2144 .bpc = 8, 2145 .size = { 2146 .width = 152, 2147 .height = 92, 2148 }, 2149 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2151 .connector_type = DRM_MODE_CONNECTOR_DPI, 2152 }; 2153 2154 static const struct display_timing innolux_g101ice_l01_timing = { 2155 .pixelclock = { 60400000, 71100000, 74700000 }, 2156 .hactive = { 1280, 1280, 1280 }, 2157 .hfront_porch = { 41, 80, 100 }, 2158 .hback_porch = { 40, 79, 99 }, 2159 .hsync_len = { 1, 1, 1 }, 2160 .vactive = { 800, 800, 800 }, 2161 .vfront_porch = { 5, 11, 14 }, 2162 .vback_porch = { 4, 11, 14 }, 2163 .vsync_len = { 1, 1, 1 }, 2164 .flags = DISPLAY_FLAGS_DE_HIGH, 2165 }; 2166 2167 static const struct panel_desc innolux_g101ice_l01 = { 2168 .timings = &innolux_g101ice_l01_timing, 2169 .num_timings = 1, 2170 .bpc = 8, 2171 .size = { 2172 .width = 217, 2173 .height = 135, 2174 }, 2175 .delay = { 2176 .enable = 200, 2177 .disable = 200, 2178 }, 2179 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2180 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2181 }; 2182 2183 static const struct display_timing innolux_g121i1_l01_timing = { 2184 .pixelclock = { 67450000, 71000000, 74550000 }, 2185 .hactive = { 1280, 1280, 1280 }, 2186 .hfront_porch = { 40, 80, 160 }, 2187 .hback_porch = { 39, 79, 159 }, 2188 .hsync_len = { 1, 1, 1 }, 2189 .vactive = { 800, 800, 800 }, 2190 .vfront_porch = { 5, 11, 100 }, 2191 .vback_porch = { 4, 11, 99 }, 2192 .vsync_len = { 1, 1, 1 }, 2193 }; 2194 2195 static const struct panel_desc innolux_g121i1_l01 = { 2196 .timings = &innolux_g121i1_l01_timing, 2197 .num_timings = 1, 2198 .bpc = 6, 2199 .size = { 2200 .width = 261, 2201 .height = 163, 2202 }, 2203 .delay = { 2204 .enable = 200, 2205 .disable = 20, 2206 }, 2207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2208 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2209 }; 2210 2211 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2212 .clock = 65000, 2213 .hdisplay = 1024, 2214 .hsync_start = 1024 + 0, 2215 .hsync_end = 1024 + 1, 2216 .htotal = 1024 + 0 + 1 + 320, 2217 .vdisplay = 768, 2218 .vsync_start = 768 + 38, 2219 .vsync_end = 768 + 38 + 1, 2220 .vtotal = 768 + 38 + 1 + 0, 2221 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2222 }; 2223 2224 static const struct panel_desc innolux_g121x1_l03 = { 2225 .modes = &innolux_g121x1_l03_mode, 2226 .num_modes = 1, 2227 .bpc = 6, 2228 .size = { 2229 .width = 246, 2230 .height = 185, 2231 }, 2232 .delay = { 2233 .enable = 200, 2234 .unprepare = 200, 2235 .disable = 400, 2236 }, 2237 }; 2238 2239 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2240 .clock = 69300, 2241 .hdisplay = 1366, 2242 .hsync_start = 1366 + 16, 2243 .hsync_end = 1366 + 16 + 34, 2244 .htotal = 1366 + 16 + 34 + 50, 2245 .vdisplay = 768, 2246 .vsync_start = 768 + 2, 2247 .vsync_end = 768 + 2 + 6, 2248 .vtotal = 768 + 2 + 6 + 12, 2249 }; 2250 2251 static const struct panel_desc innolux_n156bge_l21 = { 2252 .modes = &innolux_n156bge_l21_mode, 2253 .num_modes = 1, 2254 .bpc = 6, 2255 .size = { 2256 .width = 344, 2257 .height = 193, 2258 }, 2259 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2260 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2261 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2262 }; 2263 2264 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2265 .clock = 51501, 2266 .hdisplay = 1024, 2267 .hsync_start = 1024 + 128, 2268 .hsync_end = 1024 + 128 + 64, 2269 .htotal = 1024 + 128 + 64 + 128, 2270 .vdisplay = 600, 2271 .vsync_start = 600 + 16, 2272 .vsync_end = 600 + 16 + 4, 2273 .vtotal = 600 + 16 + 4 + 16, 2274 }; 2275 2276 static const struct panel_desc innolux_zj070na_01p = { 2277 .modes = &innolux_zj070na_01p_mode, 2278 .num_modes = 1, 2279 .bpc = 6, 2280 .size = { 2281 .width = 154, 2282 .height = 90, 2283 }, 2284 }; 2285 2286 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2287 .pixelclock = { 5580000, 5850000, 6200000 }, 2288 .hactive = { 320, 320, 320 }, 2289 .hfront_porch = { 30, 30, 30 }, 2290 .hback_porch = { 30, 30, 30 }, 2291 .hsync_len = { 1, 5, 17 }, 2292 .vactive = { 240, 240, 240 }, 2293 .vfront_porch = { 6, 6, 6 }, 2294 .vback_porch = { 5, 5, 5 }, 2295 .vsync_len = { 1, 2, 11 }, 2296 .flags = DISPLAY_FLAGS_DE_HIGH, 2297 }; 2298 2299 static const struct panel_desc koe_tx14d24vm1bpa = { 2300 .timings = &koe_tx14d24vm1bpa_timing, 2301 .num_timings = 1, 2302 .bpc = 6, 2303 .size = { 2304 .width = 115, 2305 .height = 86, 2306 }, 2307 }; 2308 2309 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2310 .pixelclock = { 151820000, 156720000, 159780000 }, 2311 .hactive = { 1920, 1920, 1920 }, 2312 .hfront_porch = { 105, 130, 142 }, 2313 .hback_porch = { 45, 70, 82 }, 2314 .hsync_len = { 30, 30, 30 }, 2315 .vactive = { 1200, 1200, 1200}, 2316 .vfront_porch = { 3, 5, 10 }, 2317 .vback_porch = { 2, 5, 10 }, 2318 .vsync_len = { 5, 5, 5 }, 2319 }; 2320 2321 static const struct panel_desc koe_tx26d202vm0bwa = { 2322 .timings = &koe_tx26d202vm0bwa_timing, 2323 .num_timings = 1, 2324 .bpc = 8, 2325 .size = { 2326 .width = 217, 2327 .height = 136, 2328 }, 2329 .delay = { 2330 .prepare = 1000, 2331 .enable = 1000, 2332 .unprepare = 1000, 2333 .disable = 1000, 2334 }, 2335 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2336 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2337 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2338 }; 2339 2340 static const struct display_timing koe_tx31d200vm0baa_timing = { 2341 .pixelclock = { 39600000, 43200000, 48000000 }, 2342 .hactive = { 1280, 1280, 1280 }, 2343 .hfront_porch = { 16, 36, 56 }, 2344 .hback_porch = { 16, 36, 56 }, 2345 .hsync_len = { 8, 8, 8 }, 2346 .vactive = { 480, 480, 480 }, 2347 .vfront_porch = { 6, 21, 33 }, 2348 .vback_porch = { 6, 21, 33 }, 2349 .vsync_len = { 8, 8, 8 }, 2350 .flags = DISPLAY_FLAGS_DE_HIGH, 2351 }; 2352 2353 static const struct panel_desc koe_tx31d200vm0baa = { 2354 .timings = &koe_tx31d200vm0baa_timing, 2355 .num_timings = 1, 2356 .bpc = 6, 2357 .size = { 2358 .width = 292, 2359 .height = 109, 2360 }, 2361 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2362 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2363 }; 2364 2365 static const struct display_timing kyo_tcg121xglp_timing = { 2366 .pixelclock = { 52000000, 65000000, 71000000 }, 2367 .hactive = { 1024, 1024, 1024 }, 2368 .hfront_porch = { 2, 2, 2 }, 2369 .hback_porch = { 2, 2, 2 }, 2370 .hsync_len = { 86, 124, 244 }, 2371 .vactive = { 768, 768, 768 }, 2372 .vfront_porch = { 2, 2, 2 }, 2373 .vback_porch = { 2, 2, 2 }, 2374 .vsync_len = { 6, 34, 73 }, 2375 .flags = DISPLAY_FLAGS_DE_HIGH, 2376 }; 2377 2378 static const struct panel_desc kyo_tcg121xglp = { 2379 .timings = &kyo_tcg121xglp_timing, 2380 .num_timings = 1, 2381 .bpc = 8, 2382 .size = { 2383 .width = 246, 2384 .height = 184, 2385 }, 2386 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2387 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2388 }; 2389 2390 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2391 .clock = 7000, 2392 .hdisplay = 320, 2393 .hsync_start = 320 + 20, 2394 .hsync_end = 320 + 20 + 30, 2395 .htotal = 320 + 20 + 30 + 38, 2396 .vdisplay = 240, 2397 .vsync_start = 240 + 4, 2398 .vsync_end = 240 + 4 + 3, 2399 .vtotal = 240 + 4 + 3 + 15, 2400 }; 2401 2402 static const struct panel_desc lemaker_bl035_rgb_002 = { 2403 .modes = &lemaker_bl035_rgb_002_mode, 2404 .num_modes = 1, 2405 .size = { 2406 .width = 70, 2407 .height = 52, 2408 }, 2409 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2410 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2411 }; 2412 2413 static const struct drm_display_mode lg_lb070wv8_mode = { 2414 .clock = 33246, 2415 .hdisplay = 800, 2416 .hsync_start = 800 + 88, 2417 .hsync_end = 800 + 88 + 80, 2418 .htotal = 800 + 88 + 80 + 88, 2419 .vdisplay = 480, 2420 .vsync_start = 480 + 10, 2421 .vsync_end = 480 + 10 + 25, 2422 .vtotal = 480 + 10 + 25 + 10, 2423 }; 2424 2425 static const struct panel_desc lg_lb070wv8 = { 2426 .modes = &lg_lb070wv8_mode, 2427 .num_modes = 1, 2428 .bpc = 8, 2429 .size = { 2430 .width = 151, 2431 .height = 91, 2432 }, 2433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2434 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2435 }; 2436 2437 static const struct display_timing logictechno_lt161010_2nh_timing = { 2438 .pixelclock = { 26400000, 33300000, 46800000 }, 2439 .hactive = { 800, 800, 800 }, 2440 .hfront_porch = { 16, 210, 354 }, 2441 .hback_porch = { 46, 46, 46 }, 2442 .hsync_len = { 1, 20, 40 }, 2443 .vactive = { 480, 480, 480 }, 2444 .vfront_porch = { 7, 22, 147 }, 2445 .vback_porch = { 23, 23, 23 }, 2446 .vsync_len = { 1, 10, 20 }, 2447 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2448 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2449 DISPLAY_FLAGS_SYNC_POSEDGE, 2450 }; 2451 2452 static const struct panel_desc logictechno_lt161010_2nh = { 2453 .timings = &logictechno_lt161010_2nh_timing, 2454 .num_timings = 1, 2455 .size = { 2456 .width = 154, 2457 .height = 86, 2458 }, 2459 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2460 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2461 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2462 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2463 .connector_type = DRM_MODE_CONNECTOR_DPI, 2464 }; 2465 2466 static const struct display_timing logictechno_lt170410_2whc_timing = { 2467 .pixelclock = { 68900000, 71100000, 73400000 }, 2468 .hactive = { 1280, 1280, 1280 }, 2469 .hfront_porch = { 23, 60, 71 }, 2470 .hback_porch = { 23, 60, 71 }, 2471 .hsync_len = { 15, 40, 47 }, 2472 .vactive = { 800, 800, 800 }, 2473 .vfront_porch = { 5, 7, 10 }, 2474 .vback_porch = { 5, 7, 10 }, 2475 .vsync_len = { 6, 9, 12 }, 2476 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2477 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2478 DISPLAY_FLAGS_SYNC_POSEDGE, 2479 }; 2480 2481 static const struct panel_desc logictechno_lt170410_2whc = { 2482 .timings = &logictechno_lt170410_2whc_timing, 2483 .num_timings = 1, 2484 .size = { 2485 .width = 217, 2486 .height = 136, 2487 }, 2488 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2489 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2490 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2491 }; 2492 2493 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2494 .clock = 33000, 2495 .hdisplay = 800, 2496 .hsync_start = 800 + 112, 2497 .hsync_end = 800 + 112 + 3, 2498 .htotal = 800 + 112 + 3 + 85, 2499 .vdisplay = 480, 2500 .vsync_start = 480 + 38, 2501 .vsync_end = 480 + 38 + 3, 2502 .vtotal = 480 + 38 + 3 + 29, 2503 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2504 }; 2505 2506 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2507 .modes = &logictechno_lttd800480070_l2rt_mode, 2508 .num_modes = 1, 2509 .bpc = 8, 2510 .size = { 2511 .width = 154, 2512 .height = 86, 2513 }, 2514 .delay = { 2515 .prepare = 45, 2516 .enable = 100, 2517 .disable = 100, 2518 .unprepare = 45 2519 }, 2520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2521 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2522 .connector_type = DRM_MODE_CONNECTOR_DPI, 2523 }; 2524 2525 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2526 .clock = 33000, 2527 .hdisplay = 800, 2528 .hsync_start = 800 + 154, 2529 .hsync_end = 800 + 154 + 3, 2530 .htotal = 800 + 154 + 3 + 43, 2531 .vdisplay = 480, 2532 .vsync_start = 480 + 47, 2533 .vsync_end = 480 + 47 + 3, 2534 .vtotal = 480 + 47 + 3 + 20, 2535 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2536 }; 2537 2538 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2539 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2540 .num_modes = 1, 2541 .bpc = 8, 2542 .size = { 2543 .width = 154, 2544 .height = 86, 2545 }, 2546 .delay = { 2547 .prepare = 45, 2548 .enable = 100, 2549 .disable = 100, 2550 .unprepare = 45 2551 }, 2552 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2553 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2554 .connector_type = DRM_MODE_CONNECTOR_DPI, 2555 }; 2556 2557 static const struct drm_display_mode logicpd_type_28_mode = { 2558 .clock = 9107, 2559 .hdisplay = 480, 2560 .hsync_start = 480 + 3, 2561 .hsync_end = 480 + 3 + 42, 2562 .htotal = 480 + 3 + 42 + 2, 2563 2564 .vdisplay = 272, 2565 .vsync_start = 272 + 2, 2566 .vsync_end = 272 + 2 + 11, 2567 .vtotal = 272 + 2 + 11 + 3, 2568 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2569 }; 2570 2571 static const struct panel_desc logicpd_type_28 = { 2572 .modes = &logicpd_type_28_mode, 2573 .num_modes = 1, 2574 .bpc = 8, 2575 .size = { 2576 .width = 105, 2577 .height = 67, 2578 }, 2579 .delay = { 2580 .prepare = 200, 2581 .enable = 200, 2582 .unprepare = 200, 2583 .disable = 200, 2584 }, 2585 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2586 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2587 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2588 .connector_type = DRM_MODE_CONNECTOR_DPI, 2589 }; 2590 2591 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2592 .clock = 30400, 2593 .hdisplay = 800, 2594 .hsync_start = 800 + 0, 2595 .hsync_end = 800 + 1, 2596 .htotal = 800 + 0 + 1 + 160, 2597 .vdisplay = 480, 2598 .vsync_start = 480 + 0, 2599 .vsync_end = 480 + 48 + 1, 2600 .vtotal = 480 + 48 + 1 + 0, 2601 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2602 }; 2603 2604 static const struct panel_desc mitsubishi_aa070mc01 = { 2605 .modes = &mitsubishi_aa070mc01_mode, 2606 .num_modes = 1, 2607 .bpc = 8, 2608 .size = { 2609 .width = 152, 2610 .height = 91, 2611 }, 2612 2613 .delay = { 2614 .enable = 200, 2615 .unprepare = 200, 2616 .disable = 400, 2617 }, 2618 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2619 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2620 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2621 }; 2622 2623 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2624 .pixelclock = { 29000000, 33000000, 38000000 }, 2625 .hactive = { 800, 800, 800 }, 2626 .hfront_porch = { 180, 210, 240 }, 2627 .hback_porch = { 16, 16, 16 }, 2628 .hsync_len = { 30, 30, 30 }, 2629 .vactive = { 480, 480, 480 }, 2630 .vfront_porch = { 12, 22, 32 }, 2631 .vback_porch = { 10, 10, 10 }, 2632 .vsync_len = { 13, 13, 13 }, 2633 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2634 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2635 DISPLAY_FLAGS_SYNC_POSEDGE, 2636 }; 2637 2638 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2639 .timings = &multi_inno_mi0700s4t_6_timing, 2640 .num_timings = 1, 2641 .bpc = 8, 2642 .size = { 2643 .width = 154, 2644 .height = 86, 2645 }, 2646 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2647 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2648 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2649 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2650 .connector_type = DRM_MODE_CONNECTOR_DPI, 2651 }; 2652 2653 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2654 .pixelclock = { 68900000, 70000000, 73400000 }, 2655 .hactive = { 1280, 1280, 1280 }, 2656 .hfront_porch = { 30, 60, 71 }, 2657 .hback_porch = { 30, 60, 71 }, 2658 .hsync_len = { 10, 10, 48 }, 2659 .vactive = { 800, 800, 800 }, 2660 .vfront_porch = { 5, 10, 10 }, 2661 .vback_porch = { 5, 10, 10 }, 2662 .vsync_len = { 5, 6, 13 }, 2663 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2664 DISPLAY_FLAGS_DE_HIGH, 2665 }; 2666 2667 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2668 .timings = &multi_inno_mi1010ait_1cp_timing, 2669 .num_timings = 1, 2670 .bpc = 8, 2671 .size = { 2672 .width = 217, 2673 .height = 136, 2674 }, 2675 .delay = { 2676 .enable = 50, 2677 .disable = 50, 2678 }, 2679 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2680 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2681 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2682 }; 2683 2684 static const struct display_timing nec_nl12880bc20_05_timing = { 2685 .pixelclock = { 67000000, 71000000, 75000000 }, 2686 .hactive = { 1280, 1280, 1280 }, 2687 .hfront_porch = { 2, 30, 30 }, 2688 .hback_porch = { 6, 100, 100 }, 2689 .hsync_len = { 2, 30, 30 }, 2690 .vactive = { 800, 800, 800 }, 2691 .vfront_porch = { 5, 5, 5 }, 2692 .vback_porch = { 11, 11, 11 }, 2693 .vsync_len = { 7, 7, 7 }, 2694 }; 2695 2696 static const struct panel_desc nec_nl12880bc20_05 = { 2697 .timings = &nec_nl12880bc20_05_timing, 2698 .num_timings = 1, 2699 .bpc = 8, 2700 .size = { 2701 .width = 261, 2702 .height = 163, 2703 }, 2704 .delay = { 2705 .enable = 50, 2706 .disable = 50, 2707 }, 2708 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2709 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2710 }; 2711 2712 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2713 .clock = 10870, 2714 .hdisplay = 480, 2715 .hsync_start = 480 + 2, 2716 .hsync_end = 480 + 2 + 41, 2717 .htotal = 480 + 2 + 41 + 2, 2718 .vdisplay = 272, 2719 .vsync_start = 272 + 2, 2720 .vsync_end = 272 + 2 + 4, 2721 .vtotal = 272 + 2 + 4 + 2, 2722 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2723 }; 2724 2725 static const struct panel_desc nec_nl4827hc19_05b = { 2726 .modes = &nec_nl4827hc19_05b_mode, 2727 .num_modes = 1, 2728 .bpc = 8, 2729 .size = { 2730 .width = 95, 2731 .height = 54, 2732 }, 2733 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2734 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2735 }; 2736 2737 static const struct drm_display_mode netron_dy_e231732_mode = { 2738 .clock = 66000, 2739 .hdisplay = 1024, 2740 .hsync_start = 1024 + 160, 2741 .hsync_end = 1024 + 160 + 70, 2742 .htotal = 1024 + 160 + 70 + 90, 2743 .vdisplay = 600, 2744 .vsync_start = 600 + 127, 2745 .vsync_end = 600 + 127 + 20, 2746 .vtotal = 600 + 127 + 20 + 3, 2747 }; 2748 2749 static const struct panel_desc netron_dy_e231732 = { 2750 .modes = &netron_dy_e231732_mode, 2751 .num_modes = 1, 2752 .size = { 2753 .width = 154, 2754 .height = 87, 2755 }, 2756 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2757 }; 2758 2759 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2760 .clock = 9000, 2761 .hdisplay = 480, 2762 .hsync_start = 480 + 2, 2763 .hsync_end = 480 + 2 + 41, 2764 .htotal = 480 + 2 + 41 + 2, 2765 .vdisplay = 272, 2766 .vsync_start = 272 + 2, 2767 .vsync_end = 272 + 2 + 10, 2768 .vtotal = 272 + 2 + 10 + 2, 2769 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2770 }; 2771 2772 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2773 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2774 .num_modes = 1, 2775 .bpc = 8, 2776 .size = { 2777 .width = 95, 2778 .height = 54, 2779 }, 2780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2781 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2782 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2783 .connector_type = DRM_MODE_CONNECTOR_DPI, 2784 }; 2785 2786 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2787 .pixelclock = { 130000000, 148350000, 163000000 }, 2788 .hactive = { 1920, 1920, 1920 }, 2789 .hfront_porch = { 80, 100, 100 }, 2790 .hback_porch = { 100, 120, 120 }, 2791 .hsync_len = { 50, 60, 60 }, 2792 .vactive = { 1080, 1080, 1080 }, 2793 .vfront_porch = { 12, 30, 30 }, 2794 .vback_porch = { 4, 10, 10 }, 2795 .vsync_len = { 4, 5, 5 }, 2796 }; 2797 2798 static const struct panel_desc nlt_nl192108ac18_02d = { 2799 .timings = &nlt_nl192108ac18_02d_timing, 2800 .num_timings = 1, 2801 .bpc = 8, 2802 .size = { 2803 .width = 344, 2804 .height = 194, 2805 }, 2806 .delay = { 2807 .unprepare = 500, 2808 }, 2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2810 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2811 }; 2812 2813 static const struct drm_display_mode nvd_9128_mode = { 2814 .clock = 29500, 2815 .hdisplay = 800, 2816 .hsync_start = 800 + 130, 2817 .hsync_end = 800 + 130 + 98, 2818 .htotal = 800 + 0 + 130 + 98, 2819 .vdisplay = 480, 2820 .vsync_start = 480 + 10, 2821 .vsync_end = 480 + 10 + 50, 2822 .vtotal = 480 + 0 + 10 + 50, 2823 }; 2824 2825 static const struct panel_desc nvd_9128 = { 2826 .modes = &nvd_9128_mode, 2827 .num_modes = 1, 2828 .bpc = 8, 2829 .size = { 2830 .width = 156, 2831 .height = 88, 2832 }, 2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2834 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2835 }; 2836 2837 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2838 .pixelclock = { 30000000, 30000000, 40000000 }, 2839 .hactive = { 800, 800, 800 }, 2840 .hfront_porch = { 40, 40, 40 }, 2841 .hback_porch = { 40, 40, 40 }, 2842 .hsync_len = { 1, 48, 48 }, 2843 .vactive = { 480, 480, 480 }, 2844 .vfront_porch = { 13, 13, 13 }, 2845 .vback_porch = { 29, 29, 29 }, 2846 .vsync_len = { 3, 3, 3 }, 2847 .flags = DISPLAY_FLAGS_DE_HIGH, 2848 }; 2849 2850 static const struct panel_desc okaya_rs800480t_7x0gp = { 2851 .timings = &okaya_rs800480t_7x0gp_timing, 2852 .num_timings = 1, 2853 .bpc = 6, 2854 .size = { 2855 .width = 154, 2856 .height = 87, 2857 }, 2858 .delay = { 2859 .prepare = 41, 2860 .enable = 50, 2861 .unprepare = 41, 2862 .disable = 50, 2863 }, 2864 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2865 }; 2866 2867 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2868 .clock = 9000, 2869 .hdisplay = 480, 2870 .hsync_start = 480 + 5, 2871 .hsync_end = 480 + 5 + 30, 2872 .htotal = 480 + 5 + 30 + 10, 2873 .vdisplay = 272, 2874 .vsync_start = 272 + 8, 2875 .vsync_end = 272 + 8 + 5, 2876 .vtotal = 272 + 8 + 5 + 3, 2877 }; 2878 2879 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2880 .modes = &olimex_lcd_olinuxino_43ts_mode, 2881 .num_modes = 1, 2882 .size = { 2883 .width = 95, 2884 .height = 54, 2885 }, 2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2887 }; 2888 2889 /* 2890 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2891 * pixel clocks, but this is the timing that was being used in the Adafruit 2892 * installation instructions. 2893 */ 2894 static const struct drm_display_mode ontat_yx700wv03_mode = { 2895 .clock = 29500, 2896 .hdisplay = 800, 2897 .hsync_start = 824, 2898 .hsync_end = 896, 2899 .htotal = 992, 2900 .vdisplay = 480, 2901 .vsync_start = 483, 2902 .vsync_end = 493, 2903 .vtotal = 500, 2904 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2905 }; 2906 2907 /* 2908 * Specification at: 2909 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2910 */ 2911 static const struct panel_desc ontat_yx700wv03 = { 2912 .modes = &ontat_yx700wv03_mode, 2913 .num_modes = 1, 2914 .bpc = 8, 2915 .size = { 2916 .width = 154, 2917 .height = 83, 2918 }, 2919 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2920 }; 2921 2922 static const struct drm_display_mode ortustech_com37h3m_mode = { 2923 .clock = 22230, 2924 .hdisplay = 480, 2925 .hsync_start = 480 + 40, 2926 .hsync_end = 480 + 40 + 10, 2927 .htotal = 480 + 40 + 10 + 40, 2928 .vdisplay = 640, 2929 .vsync_start = 640 + 4, 2930 .vsync_end = 640 + 4 + 2, 2931 .vtotal = 640 + 4 + 2 + 4, 2932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2933 }; 2934 2935 static const struct panel_desc ortustech_com37h3m = { 2936 .modes = &ortustech_com37h3m_mode, 2937 .num_modes = 1, 2938 .bpc = 8, 2939 .size = { 2940 .width = 56, /* 56.16mm */ 2941 .height = 75, /* 74.88mm */ 2942 }, 2943 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2944 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2945 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2946 }; 2947 2948 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2949 .clock = 25000, 2950 .hdisplay = 480, 2951 .hsync_start = 480 + 10, 2952 .hsync_end = 480 + 10 + 10, 2953 .htotal = 480 + 10 + 10 + 15, 2954 .vdisplay = 800, 2955 .vsync_start = 800 + 3, 2956 .vsync_end = 800 + 3 + 3, 2957 .vtotal = 800 + 3 + 3 + 3, 2958 }; 2959 2960 static const struct panel_desc ortustech_com43h4m85ulc = { 2961 .modes = &ortustech_com43h4m85ulc_mode, 2962 .num_modes = 1, 2963 .bpc = 6, 2964 .size = { 2965 .width = 56, 2966 .height = 93, 2967 }, 2968 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2969 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2970 .connector_type = DRM_MODE_CONNECTOR_DPI, 2971 }; 2972 2973 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2974 .clock = 33000, 2975 .hdisplay = 800, 2976 .hsync_start = 800 + 210, 2977 .hsync_end = 800 + 210 + 30, 2978 .htotal = 800 + 210 + 30 + 16, 2979 .vdisplay = 480, 2980 .vsync_start = 480 + 22, 2981 .vsync_end = 480 + 22 + 13, 2982 .vtotal = 480 + 22 + 13 + 10, 2983 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2984 }; 2985 2986 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2987 .modes = &osddisplays_osd070t1718_19ts_mode, 2988 .num_modes = 1, 2989 .bpc = 8, 2990 .size = { 2991 .width = 152, 2992 .height = 91, 2993 }, 2994 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2995 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2996 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2997 .connector_type = DRM_MODE_CONNECTOR_DPI, 2998 }; 2999 3000 static const struct drm_display_mode pda_91_00156_a0_mode = { 3001 .clock = 33300, 3002 .hdisplay = 800, 3003 .hsync_start = 800 + 1, 3004 .hsync_end = 800 + 1 + 64, 3005 .htotal = 800 + 1 + 64 + 64, 3006 .vdisplay = 480, 3007 .vsync_start = 480 + 1, 3008 .vsync_end = 480 + 1 + 23, 3009 .vtotal = 480 + 1 + 23 + 22, 3010 }; 3011 3012 static const struct panel_desc pda_91_00156_a0 = { 3013 .modes = &pda_91_00156_a0_mode, 3014 .num_modes = 1, 3015 .size = { 3016 .width = 152, 3017 .height = 91, 3018 }, 3019 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3020 }; 3021 3022 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3023 .clock = 24750, 3024 .hdisplay = 800, 3025 .hsync_start = 800 + 54, 3026 .hsync_end = 800 + 54 + 2, 3027 .htotal = 800 + 54 + 2 + 44, 3028 .vdisplay = 480, 3029 .vsync_start = 480 + 49, 3030 .vsync_end = 480 + 49 + 2, 3031 .vtotal = 480 + 49 + 2 + 22, 3032 }; 3033 3034 static const struct panel_desc powertip_ph800480t013_idf02 = { 3035 .modes = &powertip_ph800480t013_idf02_mode, 3036 .num_modes = 1, 3037 .size = { 3038 .width = 152, 3039 .height = 91, 3040 }, 3041 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3042 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3043 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3045 .connector_type = DRM_MODE_CONNECTOR_DPI, 3046 }; 3047 3048 static const struct drm_display_mode qd43003c0_40_mode = { 3049 .clock = 9000, 3050 .hdisplay = 480, 3051 .hsync_start = 480 + 8, 3052 .hsync_end = 480 + 8 + 4, 3053 .htotal = 480 + 8 + 4 + 39, 3054 .vdisplay = 272, 3055 .vsync_start = 272 + 4, 3056 .vsync_end = 272 + 4 + 10, 3057 .vtotal = 272 + 4 + 10 + 2, 3058 }; 3059 3060 static const struct panel_desc qd43003c0_40 = { 3061 .modes = &qd43003c0_40_mode, 3062 .num_modes = 1, 3063 .bpc = 8, 3064 .size = { 3065 .width = 95, 3066 .height = 53, 3067 }, 3068 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3069 }; 3070 3071 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3072 { /* 60 Hz */ 3073 .clock = 10800, 3074 .hdisplay = 480, 3075 .hsync_start = 480 + 77, 3076 .hsync_end = 480 + 77 + 41, 3077 .htotal = 480 + 77 + 41 + 2, 3078 .vdisplay = 272, 3079 .vsync_start = 272 + 16, 3080 .vsync_end = 272 + 16 + 10, 3081 .vtotal = 272 + 16 + 10 + 2, 3082 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3083 }, 3084 { /* 50 Hz */ 3085 .clock = 10800, 3086 .hdisplay = 480, 3087 .hsync_start = 480 + 17, 3088 .hsync_end = 480 + 17 + 41, 3089 .htotal = 480 + 17 + 41 + 2, 3090 .vdisplay = 272, 3091 .vsync_start = 272 + 116, 3092 .vsync_end = 272 + 116 + 10, 3093 .vtotal = 272 + 116 + 10 + 2, 3094 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3095 }, 3096 }; 3097 3098 static const struct panel_desc qishenglong_gopher2b_lcd = { 3099 .modes = qishenglong_gopher2b_lcd_modes, 3100 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3101 .bpc = 8, 3102 .size = { 3103 .width = 95, 3104 .height = 54, 3105 }, 3106 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3107 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3108 .connector_type = DRM_MODE_CONNECTOR_DPI, 3109 }; 3110 3111 static const struct display_timing rocktech_rk070er9427_timing = { 3112 .pixelclock = { 26400000, 33300000, 46800000 }, 3113 .hactive = { 800, 800, 800 }, 3114 .hfront_porch = { 16, 210, 354 }, 3115 .hback_porch = { 46, 46, 46 }, 3116 .hsync_len = { 1, 1, 1 }, 3117 .vactive = { 480, 480, 480 }, 3118 .vfront_porch = { 7, 22, 147 }, 3119 .vback_porch = { 23, 23, 23 }, 3120 .vsync_len = { 1, 1, 1 }, 3121 .flags = DISPLAY_FLAGS_DE_HIGH, 3122 }; 3123 3124 static const struct panel_desc rocktech_rk070er9427 = { 3125 .timings = &rocktech_rk070er9427_timing, 3126 .num_timings = 1, 3127 .bpc = 6, 3128 .size = { 3129 .width = 154, 3130 .height = 86, 3131 }, 3132 .delay = { 3133 .prepare = 41, 3134 .enable = 50, 3135 .unprepare = 41, 3136 .disable = 50, 3137 }, 3138 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3139 }; 3140 3141 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3142 .clock = 71100, 3143 .hdisplay = 1280, 3144 .hsync_start = 1280 + 48, 3145 .hsync_end = 1280 + 48 + 32, 3146 .htotal = 1280 + 48 + 32 + 80, 3147 .vdisplay = 800, 3148 .vsync_start = 800 + 2, 3149 .vsync_end = 800 + 2 + 5, 3150 .vtotal = 800 + 2 + 5 + 16, 3151 }; 3152 3153 static const struct panel_desc rocktech_rk101ii01d_ct = { 3154 .modes = &rocktech_rk101ii01d_ct_mode, 3155 .bpc = 8, 3156 .num_modes = 1, 3157 .size = { 3158 .width = 217, 3159 .height = 136, 3160 }, 3161 .delay = { 3162 .prepare = 50, 3163 .disable = 50, 3164 }, 3165 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3166 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3167 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3168 }; 3169 3170 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3171 .clock = 54030, 3172 .hdisplay = 1024, 3173 .hsync_start = 1024 + 24, 3174 .hsync_end = 1024 + 24 + 136, 3175 .htotal = 1024 + 24 + 136 + 160, 3176 .vdisplay = 600, 3177 .vsync_start = 600 + 3, 3178 .vsync_end = 600 + 3 + 6, 3179 .vtotal = 600 + 3 + 6 + 61, 3180 }; 3181 3182 static const struct panel_desc samsung_ltn101nt05 = { 3183 .modes = &samsung_ltn101nt05_mode, 3184 .num_modes = 1, 3185 .bpc = 6, 3186 .size = { 3187 .width = 223, 3188 .height = 125, 3189 }, 3190 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3191 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3192 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3193 }; 3194 3195 static const struct display_timing satoz_sat050at40h12r2_timing = { 3196 .pixelclock = {33300000, 33300000, 50000000}, 3197 .hactive = {800, 800, 800}, 3198 .hfront_porch = {16, 210, 354}, 3199 .hback_porch = {46, 46, 46}, 3200 .hsync_len = {1, 1, 40}, 3201 .vactive = {480, 480, 480}, 3202 .vfront_porch = {7, 22, 147}, 3203 .vback_porch = {23, 23, 23}, 3204 .vsync_len = {1, 1, 20}, 3205 }; 3206 3207 static const struct panel_desc satoz_sat050at40h12r2 = { 3208 .timings = &satoz_sat050at40h12r2_timing, 3209 .num_timings = 1, 3210 .bpc = 8, 3211 .size = { 3212 .width = 108, 3213 .height = 65, 3214 }, 3215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3216 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3217 }; 3218 3219 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3220 .clock = 33260, 3221 .hdisplay = 800, 3222 .hsync_start = 800 + 64, 3223 .hsync_end = 800 + 64 + 128, 3224 .htotal = 800 + 64 + 128 + 64, 3225 .vdisplay = 480, 3226 .vsync_start = 480 + 8, 3227 .vsync_end = 480 + 8 + 2, 3228 .vtotal = 480 + 8 + 2 + 35, 3229 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3230 }; 3231 3232 static const struct panel_desc sharp_lq070y3dg3b = { 3233 .modes = &sharp_lq070y3dg3b_mode, 3234 .num_modes = 1, 3235 .bpc = 8, 3236 .size = { 3237 .width = 152, /* 152.4mm */ 3238 .height = 91, /* 91.4mm */ 3239 }, 3240 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3241 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3242 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3243 }; 3244 3245 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3246 .clock = 5500, 3247 .hdisplay = 240, 3248 .hsync_start = 240 + 16, 3249 .hsync_end = 240 + 16 + 7, 3250 .htotal = 240 + 16 + 7 + 5, 3251 .vdisplay = 320, 3252 .vsync_start = 320 + 9, 3253 .vsync_end = 320 + 9 + 1, 3254 .vtotal = 320 + 9 + 1 + 7, 3255 }; 3256 3257 static const struct panel_desc sharp_lq035q7db03 = { 3258 .modes = &sharp_lq035q7db03_mode, 3259 .num_modes = 1, 3260 .bpc = 6, 3261 .size = { 3262 .width = 54, 3263 .height = 72, 3264 }, 3265 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3266 }; 3267 3268 static const struct display_timing sharp_lq101k1ly04_timing = { 3269 .pixelclock = { 60000000, 65000000, 80000000 }, 3270 .hactive = { 1280, 1280, 1280 }, 3271 .hfront_porch = { 20, 20, 20 }, 3272 .hback_porch = { 20, 20, 20 }, 3273 .hsync_len = { 10, 10, 10 }, 3274 .vactive = { 800, 800, 800 }, 3275 .vfront_porch = { 4, 4, 4 }, 3276 .vback_porch = { 4, 4, 4 }, 3277 .vsync_len = { 4, 4, 4 }, 3278 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3279 }; 3280 3281 static const struct panel_desc sharp_lq101k1ly04 = { 3282 .timings = &sharp_lq101k1ly04_timing, 3283 .num_timings = 1, 3284 .bpc = 8, 3285 .size = { 3286 .width = 217, 3287 .height = 136, 3288 }, 3289 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3290 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3291 }; 3292 3293 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3294 { /* 50 Hz */ 3295 .clock = 3000, 3296 .hdisplay = 240, 3297 .hsync_start = 240 + 58, 3298 .hsync_end = 240 + 58 + 1, 3299 .htotal = 240 + 58 + 1 + 1, 3300 .vdisplay = 160, 3301 .vsync_start = 160 + 24, 3302 .vsync_end = 160 + 24 + 10, 3303 .vtotal = 160 + 24 + 10 + 6, 3304 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3305 }, 3306 { /* 60 Hz */ 3307 .clock = 3000, 3308 .hdisplay = 240, 3309 .hsync_start = 240 + 8, 3310 .hsync_end = 240 + 8 + 1, 3311 .htotal = 240 + 8 + 1 + 1, 3312 .vdisplay = 160, 3313 .vsync_start = 160 + 24, 3314 .vsync_end = 160 + 24 + 10, 3315 .vtotal = 160 + 24 + 10 + 6, 3316 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3317 }, 3318 }; 3319 3320 static const struct panel_desc sharp_ls020b1dd01d = { 3321 .modes = sharp_ls020b1dd01d_modes, 3322 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3323 .bpc = 6, 3324 .size = { 3325 .width = 42, 3326 .height = 28, 3327 }, 3328 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3329 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3330 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3331 | DRM_BUS_FLAG_SHARP_SIGNALS, 3332 }; 3333 3334 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3335 .clock = 33300, 3336 .hdisplay = 800, 3337 .hsync_start = 800 + 1, 3338 .hsync_end = 800 + 1 + 64, 3339 .htotal = 800 + 1 + 64 + 64, 3340 .vdisplay = 480, 3341 .vsync_start = 480 + 1, 3342 .vsync_end = 480 + 1 + 23, 3343 .vtotal = 480 + 1 + 23 + 22, 3344 }; 3345 3346 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3347 .modes = &shelly_sca07010_bfn_lnn_mode, 3348 .num_modes = 1, 3349 .size = { 3350 .width = 152, 3351 .height = 91, 3352 }, 3353 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3354 }; 3355 3356 static const struct drm_display_mode starry_kr070pe2t_mode = { 3357 .clock = 33000, 3358 .hdisplay = 800, 3359 .hsync_start = 800 + 209, 3360 .hsync_end = 800 + 209 + 1, 3361 .htotal = 800 + 209 + 1 + 45, 3362 .vdisplay = 480, 3363 .vsync_start = 480 + 22, 3364 .vsync_end = 480 + 22 + 1, 3365 .vtotal = 480 + 22 + 1 + 22, 3366 }; 3367 3368 static const struct panel_desc starry_kr070pe2t = { 3369 .modes = &starry_kr070pe2t_mode, 3370 .num_modes = 1, 3371 .bpc = 8, 3372 .size = { 3373 .width = 152, 3374 .height = 86, 3375 }, 3376 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3378 .connector_type = DRM_MODE_CONNECTOR_DPI, 3379 }; 3380 3381 static const struct display_timing startek_kd070wvfpa_mode = { 3382 .pixelclock = { 25200000, 27200000, 30500000 }, 3383 .hactive = { 800, 800, 800 }, 3384 .hfront_porch = { 19, 44, 115 }, 3385 .hback_porch = { 5, 16, 101 }, 3386 .hsync_len = { 1, 2, 100 }, 3387 .vactive = { 480, 480, 480 }, 3388 .vfront_porch = { 5, 43, 67 }, 3389 .vback_porch = { 5, 5, 67 }, 3390 .vsync_len = { 1, 2, 66 }, 3391 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3392 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3393 DISPLAY_FLAGS_SYNC_POSEDGE, 3394 }; 3395 3396 static const struct panel_desc startek_kd070wvfpa = { 3397 .timings = &startek_kd070wvfpa_mode, 3398 .num_timings = 1, 3399 .bpc = 8, 3400 .size = { 3401 .width = 152, 3402 .height = 91, 3403 }, 3404 .delay = { 3405 .prepare = 20, 3406 .enable = 200, 3407 .disable = 200, 3408 }, 3409 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3410 .connector_type = DRM_MODE_CONNECTOR_DPI, 3411 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3412 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3413 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3414 }; 3415 3416 static const struct display_timing tsd_tst043015cmhx_timing = { 3417 .pixelclock = { 5000000, 9000000, 12000000 }, 3418 .hactive = { 480, 480, 480 }, 3419 .hfront_porch = { 4, 5, 65 }, 3420 .hback_porch = { 36, 40, 255 }, 3421 .hsync_len = { 1, 1, 1 }, 3422 .vactive = { 272, 272, 272 }, 3423 .vfront_porch = { 2, 8, 97 }, 3424 .vback_porch = { 3, 8, 31 }, 3425 .vsync_len = { 1, 1, 1 }, 3426 3427 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3428 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3429 }; 3430 3431 static const struct panel_desc tsd_tst043015cmhx = { 3432 .timings = &tsd_tst043015cmhx_timing, 3433 .num_timings = 1, 3434 .bpc = 8, 3435 .size = { 3436 .width = 105, 3437 .height = 67, 3438 }, 3439 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3440 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3441 }; 3442 3443 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3444 .clock = 30000, 3445 .hdisplay = 800, 3446 .hsync_start = 800 + 39, 3447 .hsync_end = 800 + 39 + 47, 3448 .htotal = 800 + 39 + 47 + 39, 3449 .vdisplay = 480, 3450 .vsync_start = 480 + 13, 3451 .vsync_end = 480 + 13 + 2, 3452 .vtotal = 480 + 13 + 2 + 29, 3453 }; 3454 3455 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3456 .modes = &tfc_s9700rtwv43tr_01b_mode, 3457 .num_modes = 1, 3458 .bpc = 8, 3459 .size = { 3460 .width = 155, 3461 .height = 90, 3462 }, 3463 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3464 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3465 }; 3466 3467 static const struct display_timing tianma_tm070jdhg30_timing = { 3468 .pixelclock = { 62600000, 68200000, 78100000 }, 3469 .hactive = { 1280, 1280, 1280 }, 3470 .hfront_porch = { 15, 64, 159 }, 3471 .hback_porch = { 5, 5, 5 }, 3472 .hsync_len = { 1, 1, 256 }, 3473 .vactive = { 800, 800, 800 }, 3474 .vfront_porch = { 3, 40, 99 }, 3475 .vback_porch = { 2, 2, 2 }, 3476 .vsync_len = { 1, 1, 128 }, 3477 .flags = DISPLAY_FLAGS_DE_HIGH, 3478 }; 3479 3480 static const struct panel_desc tianma_tm070jdhg30 = { 3481 .timings = &tianma_tm070jdhg30_timing, 3482 .num_timings = 1, 3483 .bpc = 8, 3484 .size = { 3485 .width = 151, 3486 .height = 95, 3487 }, 3488 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3489 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3490 }; 3491 3492 static const struct panel_desc tianma_tm070jvhg33 = { 3493 .timings = &tianma_tm070jdhg30_timing, 3494 .num_timings = 1, 3495 .bpc = 8, 3496 .size = { 3497 .width = 150, 3498 .height = 94, 3499 }, 3500 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3501 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3502 }; 3503 3504 static const struct display_timing tianma_tm070rvhg71_timing = { 3505 .pixelclock = { 27700000, 29200000, 39600000 }, 3506 .hactive = { 800, 800, 800 }, 3507 .hfront_porch = { 12, 40, 212 }, 3508 .hback_porch = { 88, 88, 88 }, 3509 .hsync_len = { 1, 1, 40 }, 3510 .vactive = { 480, 480, 480 }, 3511 .vfront_porch = { 1, 13, 88 }, 3512 .vback_porch = { 32, 32, 32 }, 3513 .vsync_len = { 1, 1, 3 }, 3514 .flags = DISPLAY_FLAGS_DE_HIGH, 3515 }; 3516 3517 static const struct panel_desc tianma_tm070rvhg71 = { 3518 .timings = &tianma_tm070rvhg71_timing, 3519 .num_timings = 1, 3520 .bpc = 8, 3521 .size = { 3522 .width = 154, 3523 .height = 86, 3524 }, 3525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3526 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3527 }; 3528 3529 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3530 { 3531 .clock = 10000, 3532 .hdisplay = 320, 3533 .hsync_start = 320 + 50, 3534 .hsync_end = 320 + 50 + 6, 3535 .htotal = 320 + 50 + 6 + 38, 3536 .vdisplay = 240, 3537 .vsync_start = 240 + 3, 3538 .vsync_end = 240 + 3 + 1, 3539 .vtotal = 240 + 3 + 1 + 17, 3540 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3541 }, 3542 }; 3543 3544 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3545 .modes = ti_nspire_cx_lcd_mode, 3546 .num_modes = 1, 3547 .bpc = 8, 3548 .size = { 3549 .width = 65, 3550 .height = 49, 3551 }, 3552 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3553 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3554 }; 3555 3556 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3557 { 3558 .clock = 10000, 3559 .hdisplay = 320, 3560 .hsync_start = 320 + 6, 3561 .hsync_end = 320 + 6 + 6, 3562 .htotal = 320 + 6 + 6 + 6, 3563 .vdisplay = 240, 3564 .vsync_start = 240 + 0, 3565 .vsync_end = 240 + 0 + 1, 3566 .vtotal = 240 + 0 + 1 + 0, 3567 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3568 }, 3569 }; 3570 3571 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3572 .modes = ti_nspire_classic_lcd_mode, 3573 .num_modes = 1, 3574 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3575 .bpc = 8, 3576 .size = { 3577 .width = 71, 3578 .height = 53, 3579 }, 3580 /* This is the grayscale bus format */ 3581 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3582 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3583 }; 3584 3585 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3586 .clock = 79500, 3587 .hdisplay = 1280, 3588 .hsync_start = 1280 + 192, 3589 .hsync_end = 1280 + 192 + 128, 3590 .htotal = 1280 + 192 + 128 + 64, 3591 .vdisplay = 768, 3592 .vsync_start = 768 + 20, 3593 .vsync_end = 768 + 20 + 7, 3594 .vtotal = 768 + 20 + 7 + 3, 3595 }; 3596 3597 static const struct panel_desc toshiba_lt089ac29000 = { 3598 .modes = &toshiba_lt089ac29000_mode, 3599 .num_modes = 1, 3600 .size = { 3601 .width = 194, 3602 .height = 116, 3603 }, 3604 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3605 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3606 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3607 }; 3608 3609 static const struct drm_display_mode tpk_f07a_0102_mode = { 3610 .clock = 33260, 3611 .hdisplay = 800, 3612 .hsync_start = 800 + 40, 3613 .hsync_end = 800 + 40 + 128, 3614 .htotal = 800 + 40 + 128 + 88, 3615 .vdisplay = 480, 3616 .vsync_start = 480 + 10, 3617 .vsync_end = 480 + 10 + 2, 3618 .vtotal = 480 + 10 + 2 + 33, 3619 }; 3620 3621 static const struct panel_desc tpk_f07a_0102 = { 3622 .modes = &tpk_f07a_0102_mode, 3623 .num_modes = 1, 3624 .size = { 3625 .width = 152, 3626 .height = 91, 3627 }, 3628 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3629 }; 3630 3631 static const struct drm_display_mode tpk_f10a_0102_mode = { 3632 .clock = 45000, 3633 .hdisplay = 1024, 3634 .hsync_start = 1024 + 176, 3635 .hsync_end = 1024 + 176 + 5, 3636 .htotal = 1024 + 176 + 5 + 88, 3637 .vdisplay = 600, 3638 .vsync_start = 600 + 20, 3639 .vsync_end = 600 + 20 + 5, 3640 .vtotal = 600 + 20 + 5 + 25, 3641 }; 3642 3643 static const struct panel_desc tpk_f10a_0102 = { 3644 .modes = &tpk_f10a_0102_mode, 3645 .num_modes = 1, 3646 .size = { 3647 .width = 223, 3648 .height = 125, 3649 }, 3650 }; 3651 3652 static const struct display_timing urt_umsh_8596md_timing = { 3653 .pixelclock = { 33260000, 33260000, 33260000 }, 3654 .hactive = { 800, 800, 800 }, 3655 .hfront_porch = { 41, 41, 41 }, 3656 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3657 .hsync_len = { 71, 128, 128 }, 3658 .vactive = { 480, 480, 480 }, 3659 .vfront_porch = { 10, 10, 10 }, 3660 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3661 .vsync_len = { 2, 2, 2 }, 3662 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3663 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3664 }; 3665 3666 static const struct panel_desc urt_umsh_8596md_lvds = { 3667 .timings = &urt_umsh_8596md_timing, 3668 .num_timings = 1, 3669 .bpc = 6, 3670 .size = { 3671 .width = 152, 3672 .height = 91, 3673 }, 3674 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3675 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3676 }; 3677 3678 static const struct panel_desc urt_umsh_8596md_parallel = { 3679 .timings = &urt_umsh_8596md_timing, 3680 .num_timings = 1, 3681 .bpc = 6, 3682 .size = { 3683 .width = 152, 3684 .height = 91, 3685 }, 3686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3687 }; 3688 3689 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3690 .clock = 60000, 3691 .hdisplay = 1024, 3692 .hsync_start = 1024 + 160, 3693 .hsync_end = 1024 + 160 + 100, 3694 .htotal = 1024 + 160 + 100 + 60, 3695 .vdisplay = 600, 3696 .vsync_start = 600 + 12, 3697 .vsync_end = 600 + 12 + 10, 3698 .vtotal = 600 + 12 + 10 + 13, 3699 }; 3700 3701 static const struct panel_desc vivax_tpc9150_panel = { 3702 .modes = &vivax_tpc9150_panel_mode, 3703 .num_modes = 1, 3704 .bpc = 6, 3705 .size = { 3706 .width = 200, 3707 .height = 115, 3708 }, 3709 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3710 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3711 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3712 }; 3713 3714 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3715 .clock = 33333, 3716 .hdisplay = 800, 3717 .hsync_start = 800 + 210, 3718 .hsync_end = 800 + 210 + 20, 3719 .htotal = 800 + 210 + 20 + 46, 3720 .vdisplay = 480, 3721 .vsync_start = 480 + 22, 3722 .vsync_end = 480 + 22 + 10, 3723 .vtotal = 480 + 22 + 10 + 23, 3724 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3725 }; 3726 3727 static const struct panel_desc vl050_8048nt_c01 = { 3728 .modes = &vl050_8048nt_c01_mode, 3729 .num_modes = 1, 3730 .bpc = 8, 3731 .size = { 3732 .width = 120, 3733 .height = 76, 3734 }, 3735 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3736 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3737 }; 3738 3739 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3740 .clock = 6410, 3741 .hdisplay = 320, 3742 .hsync_start = 320 + 20, 3743 .hsync_end = 320 + 20 + 30, 3744 .htotal = 320 + 20 + 30 + 38, 3745 .vdisplay = 240, 3746 .vsync_start = 240 + 4, 3747 .vsync_end = 240 + 4 + 3, 3748 .vtotal = 240 + 4 + 3 + 15, 3749 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3750 }; 3751 3752 static const struct panel_desc winstar_wf35ltiacd = { 3753 .modes = &winstar_wf35ltiacd_mode, 3754 .num_modes = 1, 3755 .bpc = 8, 3756 .size = { 3757 .width = 70, 3758 .height = 53, 3759 }, 3760 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3761 }; 3762 3763 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3764 .clock = 51200, 3765 .hdisplay = 1024, 3766 .hsync_start = 1024 + 100, 3767 .hsync_end = 1024 + 100 + 100, 3768 .htotal = 1024 + 100 + 100 + 120, 3769 .vdisplay = 600, 3770 .vsync_start = 600 + 10, 3771 .vsync_end = 600 + 10 + 10, 3772 .vtotal = 600 + 10 + 10 + 15, 3773 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3774 }; 3775 3776 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3777 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3778 .num_modes = 1, 3779 .bpc = 8, 3780 .size = { 3781 .width = 154, 3782 .height = 90, 3783 }, 3784 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3785 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3787 }; 3788 3789 static const struct drm_display_mode arm_rtsm_mode[] = { 3790 { 3791 .clock = 65000, 3792 .hdisplay = 1024, 3793 .hsync_start = 1024 + 24, 3794 .hsync_end = 1024 + 24 + 136, 3795 .htotal = 1024 + 24 + 136 + 160, 3796 .vdisplay = 768, 3797 .vsync_start = 768 + 3, 3798 .vsync_end = 768 + 3 + 6, 3799 .vtotal = 768 + 3 + 6 + 29, 3800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3801 }, 3802 }; 3803 3804 static const struct panel_desc arm_rtsm = { 3805 .modes = arm_rtsm_mode, 3806 .num_modes = 1, 3807 .bpc = 8, 3808 .size = { 3809 .width = 400, 3810 .height = 300, 3811 }, 3812 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3813 }; 3814 3815 static const struct of_device_id platform_of_match[] = { 3816 { 3817 .compatible = "ampire,am-1280800n3tzqw-t00h", 3818 .data = &ire_am_1280800n3tzqw_t00h, 3819 }, { 3820 .compatible = "ampire,am-480272h3tmqw-t01h", 3821 .data = &ire_am_480272h3tmqw_t01h, 3822 }, { 3823 .compatible = "ampire,am800480r3tmqwa1h", 3824 .data = &ire_am800480r3tmqwa1h, 3825 }, { 3826 .compatible = "ampire,am800600p5tmqw-tb8h", 3827 .data = &ire_am800600p5tmqwtb8h, 3828 }, { 3829 .compatible = "arm,rtsm-display", 3830 .data = &arm_rtsm, 3831 }, { 3832 .compatible = "armadeus,st0700-adapt", 3833 .data = &armadeus_st0700_adapt, 3834 }, { 3835 .compatible = "auo,b101aw03", 3836 .data = &auo_b101aw03, 3837 }, { 3838 .compatible = "auo,b101xtn01", 3839 .data = &auo_b101xtn01, 3840 }, { 3841 .compatible = "auo,g070vvn01", 3842 .data = &auo_g070vvn01, 3843 }, { 3844 .compatible = "auo,g101evn010", 3845 .data = &auo_g101evn010, 3846 }, { 3847 .compatible = "auo,g104sn02", 3848 .data = &auo_g104sn02, 3849 }, { 3850 .compatible = "auo,g121ean01", 3851 .data = &auo_g121ean01, 3852 }, { 3853 .compatible = "auo,g133han01", 3854 .data = &auo_g133han01, 3855 }, { 3856 .compatible = "auo,g156xtn01", 3857 .data = &auo_g156xtn01, 3858 }, { 3859 .compatible = "auo,g185han01", 3860 .data = &auo_g185han01, 3861 }, { 3862 .compatible = "auo,g190ean01", 3863 .data = &auo_g190ean01, 3864 }, { 3865 .compatible = "auo,p320hvn03", 3866 .data = &auo_p320hvn03, 3867 }, { 3868 .compatible = "auo,t215hvn01", 3869 .data = &auo_t215hvn01, 3870 }, { 3871 .compatible = "avic,tm070ddh03", 3872 .data = &avic_tm070ddh03, 3873 }, { 3874 .compatible = "bananapi,s070wv20-ct16", 3875 .data = &bananapi_s070wv20_ct16, 3876 }, { 3877 .compatible = "boe,hv070wsa-100", 3878 .data = &boe_hv070wsa 3879 }, { 3880 .compatible = "cdtech,s043wq26h-ct7", 3881 .data = &cdtech_s043wq26h_ct7, 3882 }, { 3883 .compatible = "cdtech,s070pws19hp-fc21", 3884 .data = &cdtech_s070pws19hp_fc21, 3885 }, { 3886 .compatible = "cdtech,s070swv29hg-dc44", 3887 .data = &cdtech_s070swv29hg_dc44, 3888 }, { 3889 .compatible = "cdtech,s070wv95-ct16", 3890 .data = &cdtech_s070wv95_ct16, 3891 }, { 3892 .compatible = "chefree,ch101olhlwh-002", 3893 .data = &chefree_ch101olhlwh_002, 3894 }, { 3895 .compatible = "chunghwa,claa070wp03xg", 3896 .data = &chunghwa_claa070wp03xg, 3897 }, { 3898 .compatible = "chunghwa,claa101wa01a", 3899 .data = &chunghwa_claa101wa01a 3900 }, { 3901 .compatible = "chunghwa,claa101wb01", 3902 .data = &chunghwa_claa101wb01 3903 }, { 3904 .compatible = "dataimage,fg040346dsswbg04", 3905 .data = &dataimage_fg040346dsswbg04, 3906 }, { 3907 .compatible = "dataimage,fg1001l0dsswmg01", 3908 .data = &dataimage_fg1001l0dsswmg01, 3909 }, { 3910 .compatible = "dataimage,scf0700c48ggu18", 3911 .data = &dataimage_scf0700c48ggu18, 3912 }, { 3913 .compatible = "dlc,dlc0700yzg-1", 3914 .data = &dlc_dlc0700yzg_1, 3915 }, { 3916 .compatible = "dlc,dlc1010gig", 3917 .data = &dlc_dlc1010gig, 3918 }, { 3919 .compatible = "edt,et035012dm6", 3920 .data = &edt_et035012dm6, 3921 }, { 3922 .compatible = "edt,etm0350g0dh6", 3923 .data = &edt_etm0350g0dh6, 3924 }, { 3925 .compatible = "edt,etm043080dh6gp", 3926 .data = &edt_etm043080dh6gp, 3927 }, { 3928 .compatible = "edt,etm0430g0dh6", 3929 .data = &edt_etm0430g0dh6, 3930 }, { 3931 .compatible = "edt,et057090dhu", 3932 .data = &edt_et057090dhu, 3933 }, { 3934 .compatible = "edt,et070080dh6", 3935 .data = &edt_etm0700g0dh6, 3936 }, { 3937 .compatible = "edt,etm0700g0dh6", 3938 .data = &edt_etm0700g0dh6, 3939 }, { 3940 .compatible = "edt,etm0700g0bdh6", 3941 .data = &edt_etm0700g0bdh6, 3942 }, { 3943 .compatible = "edt,etm0700g0edh6", 3944 .data = &edt_etm0700g0bdh6, 3945 }, { 3946 .compatible = "edt,etmv570g2dhu", 3947 .data = &edt_etmv570g2dhu, 3948 }, { 3949 .compatible = "eink,vb3300-kca", 3950 .data = &eink_vb3300_kca, 3951 }, { 3952 .compatible = "evervision,vgg804821", 3953 .data = &evervision_vgg804821, 3954 }, { 3955 .compatible = "foxlink,fl500wvr00-a0t", 3956 .data = &foxlink_fl500wvr00_a0t, 3957 }, { 3958 .compatible = "frida,frd350h54004", 3959 .data = &frida_frd350h54004, 3960 }, { 3961 .compatible = "friendlyarm,hd702e", 3962 .data = &friendlyarm_hd702e, 3963 }, { 3964 .compatible = "giantplus,gpg482739qs5", 3965 .data = &giantplus_gpg482739qs5 3966 }, { 3967 .compatible = "giantplus,gpm940b0", 3968 .data = &giantplus_gpm940b0, 3969 }, { 3970 .compatible = "hannstar,hsd070pww1", 3971 .data = &hannstar_hsd070pww1, 3972 }, { 3973 .compatible = "hannstar,hsd100pxn1", 3974 .data = &hannstar_hsd100pxn1, 3975 }, { 3976 .compatible = "hit,tx23d38vm0caa", 3977 .data = &hitachi_tx23d38vm0caa 3978 }, { 3979 .compatible = "innolux,at043tn24", 3980 .data = &innolux_at043tn24, 3981 }, { 3982 .compatible = "innolux,at070tn92", 3983 .data = &innolux_at070tn92, 3984 }, { 3985 .compatible = "innolux,g070y2-l01", 3986 .data = &innolux_g070y2_l01, 3987 }, { 3988 .compatible = "innolux,g070y2-t02", 3989 .data = &innolux_g070y2_t02, 3990 }, { 3991 .compatible = "innolux,g101ice-l01", 3992 .data = &innolux_g101ice_l01 3993 }, { 3994 .compatible = "innolux,g121i1-l01", 3995 .data = &innolux_g121i1_l01 3996 }, { 3997 .compatible = "innolux,g121x1-l03", 3998 .data = &innolux_g121x1_l03, 3999 }, { 4000 .compatible = "innolux,n156bge-l21", 4001 .data = &innolux_n156bge_l21, 4002 }, { 4003 .compatible = "innolux,zj070na-01p", 4004 .data = &innolux_zj070na_01p, 4005 }, { 4006 .compatible = "koe,tx14d24vm1bpa", 4007 .data = &koe_tx14d24vm1bpa, 4008 }, { 4009 .compatible = "koe,tx26d202vm0bwa", 4010 .data = &koe_tx26d202vm0bwa, 4011 }, { 4012 .compatible = "koe,tx31d200vm0baa", 4013 .data = &koe_tx31d200vm0baa, 4014 }, { 4015 .compatible = "kyo,tcg121xglp", 4016 .data = &kyo_tcg121xglp, 4017 }, { 4018 .compatible = "lemaker,bl035-rgb-002", 4019 .data = &lemaker_bl035_rgb_002, 4020 }, { 4021 .compatible = "lg,lb070wv8", 4022 .data = &lg_lb070wv8, 4023 }, { 4024 .compatible = "logicpd,type28", 4025 .data = &logicpd_type_28, 4026 }, { 4027 .compatible = "logictechno,lt161010-2nhc", 4028 .data = &logictechno_lt161010_2nh, 4029 }, { 4030 .compatible = "logictechno,lt161010-2nhr", 4031 .data = &logictechno_lt161010_2nh, 4032 }, { 4033 .compatible = "logictechno,lt170410-2whc", 4034 .data = &logictechno_lt170410_2whc, 4035 }, { 4036 .compatible = "logictechno,lttd800480070-l2rt", 4037 .data = &logictechno_lttd800480070_l2rt, 4038 }, { 4039 .compatible = "logictechno,lttd800480070-l6wh-rt", 4040 .data = &logictechno_lttd800480070_l6wh_rt, 4041 }, { 4042 .compatible = "mitsubishi,aa070mc01-ca1", 4043 .data = &mitsubishi_aa070mc01, 4044 }, { 4045 .compatible = "multi-inno,mi0700s4t-6", 4046 .data = &multi_inno_mi0700s4t_6, 4047 }, { 4048 .compatible = "multi-inno,mi1010ait-1cp", 4049 .data = &multi_inno_mi1010ait_1cp, 4050 }, { 4051 .compatible = "nec,nl12880bc20-05", 4052 .data = &nec_nl12880bc20_05, 4053 }, { 4054 .compatible = "nec,nl4827hc19-05b", 4055 .data = &nec_nl4827hc19_05b, 4056 }, { 4057 .compatible = "netron-dy,e231732", 4058 .data = &netron_dy_e231732, 4059 }, { 4060 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4061 .data = &newhaven_nhd_43_480272ef_atxl, 4062 }, { 4063 .compatible = "nlt,nl192108ac18-02d", 4064 .data = &nlt_nl192108ac18_02d, 4065 }, { 4066 .compatible = "nvd,9128", 4067 .data = &nvd_9128, 4068 }, { 4069 .compatible = "okaya,rs800480t-7x0gp", 4070 .data = &okaya_rs800480t_7x0gp, 4071 }, { 4072 .compatible = "olimex,lcd-olinuxino-43-ts", 4073 .data = &olimex_lcd_olinuxino_43ts, 4074 }, { 4075 .compatible = "ontat,yx700wv03", 4076 .data = &ontat_yx700wv03, 4077 }, { 4078 .compatible = "ortustech,com37h3m05dtc", 4079 .data = &ortustech_com37h3m, 4080 }, { 4081 .compatible = "ortustech,com37h3m99dtc", 4082 .data = &ortustech_com37h3m, 4083 }, { 4084 .compatible = "ortustech,com43h4m85ulc", 4085 .data = &ortustech_com43h4m85ulc, 4086 }, { 4087 .compatible = "osddisplays,osd070t1718-19ts", 4088 .data = &osddisplays_osd070t1718_19ts, 4089 }, { 4090 .compatible = "pda,91-00156-a0", 4091 .data = &pda_91_00156_a0, 4092 }, { 4093 .compatible = "powertip,ph800480t013-idf02", 4094 .data = &powertip_ph800480t013_idf02, 4095 }, { 4096 .compatible = "qiaodian,qd43003c0-40", 4097 .data = &qd43003c0_40, 4098 }, { 4099 .compatible = "qishenglong,gopher2b-lcd", 4100 .data = &qishenglong_gopher2b_lcd, 4101 }, { 4102 .compatible = "rocktech,rk070er9427", 4103 .data = &rocktech_rk070er9427, 4104 }, { 4105 .compatible = "rocktech,rk101ii01d-ct", 4106 .data = &rocktech_rk101ii01d_ct, 4107 }, { 4108 .compatible = "samsung,ltn101nt05", 4109 .data = &samsung_ltn101nt05, 4110 }, { 4111 .compatible = "satoz,sat050at40h12r2", 4112 .data = &satoz_sat050at40h12r2, 4113 }, { 4114 .compatible = "sharp,lq035q7db03", 4115 .data = &sharp_lq035q7db03, 4116 }, { 4117 .compatible = "sharp,lq070y3dg3b", 4118 .data = &sharp_lq070y3dg3b, 4119 }, { 4120 .compatible = "sharp,lq101k1ly04", 4121 .data = &sharp_lq101k1ly04, 4122 }, { 4123 .compatible = "sharp,ls020b1dd01d", 4124 .data = &sharp_ls020b1dd01d, 4125 }, { 4126 .compatible = "shelly,sca07010-bfn-lnn", 4127 .data = &shelly_sca07010_bfn_lnn, 4128 }, { 4129 .compatible = "starry,kr070pe2t", 4130 .data = &starry_kr070pe2t, 4131 }, { 4132 .compatible = "startek,kd070wvfpa", 4133 .data = &startek_kd070wvfpa, 4134 }, { 4135 .compatible = "team-source-display,tst043015cmhx", 4136 .data = &tsd_tst043015cmhx, 4137 }, { 4138 .compatible = "tfc,s9700rtwv43tr-01b", 4139 .data = &tfc_s9700rtwv43tr_01b, 4140 }, { 4141 .compatible = "tianma,tm070jdhg30", 4142 .data = &tianma_tm070jdhg30, 4143 }, { 4144 .compatible = "tianma,tm070jvhg33", 4145 .data = &tianma_tm070jvhg33, 4146 }, { 4147 .compatible = "tianma,tm070rvhg71", 4148 .data = &tianma_tm070rvhg71, 4149 }, { 4150 .compatible = "ti,nspire-cx-lcd-panel", 4151 .data = &ti_nspire_cx_lcd_panel, 4152 }, { 4153 .compatible = "ti,nspire-classic-lcd-panel", 4154 .data = &ti_nspire_classic_lcd_panel, 4155 }, { 4156 .compatible = "toshiba,lt089ac29000", 4157 .data = &toshiba_lt089ac29000, 4158 }, { 4159 .compatible = "tpk,f07a-0102", 4160 .data = &tpk_f07a_0102, 4161 }, { 4162 .compatible = "tpk,f10a-0102", 4163 .data = &tpk_f10a_0102, 4164 }, { 4165 .compatible = "urt,umsh-8596md-t", 4166 .data = &urt_umsh_8596md_parallel, 4167 }, { 4168 .compatible = "urt,umsh-8596md-1t", 4169 .data = &urt_umsh_8596md_parallel, 4170 }, { 4171 .compatible = "urt,umsh-8596md-7t", 4172 .data = &urt_umsh_8596md_parallel, 4173 }, { 4174 .compatible = "urt,umsh-8596md-11t", 4175 .data = &urt_umsh_8596md_lvds, 4176 }, { 4177 .compatible = "urt,umsh-8596md-19t", 4178 .data = &urt_umsh_8596md_lvds, 4179 }, { 4180 .compatible = "urt,umsh-8596md-20t", 4181 .data = &urt_umsh_8596md_parallel, 4182 }, { 4183 .compatible = "vivax,tpc9150-panel", 4184 .data = &vivax_tpc9150_panel, 4185 }, { 4186 .compatible = "vxt,vl050-8048nt-c01", 4187 .data = &vl050_8048nt_c01, 4188 }, { 4189 .compatible = "winstar,wf35ltiacd", 4190 .data = &winstar_wf35ltiacd, 4191 }, { 4192 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4193 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4194 }, { 4195 /* Must be the last entry */ 4196 .compatible = "panel-dpi", 4197 .data = &panel_dpi, 4198 }, { 4199 /* sentinel */ 4200 } 4201 }; 4202 MODULE_DEVICE_TABLE(of, platform_of_match); 4203 4204 static int panel_simple_platform_probe(struct platform_device *pdev) 4205 { 4206 const struct of_device_id *id; 4207 4208 id = of_match_node(platform_of_match, pdev->dev.of_node); 4209 if (!id) 4210 return -ENODEV; 4211 4212 return panel_simple_probe(&pdev->dev, id->data); 4213 } 4214 4215 static int panel_simple_platform_remove(struct platform_device *pdev) 4216 { 4217 return panel_simple_remove(&pdev->dev); 4218 } 4219 4220 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4221 { 4222 panel_simple_shutdown(&pdev->dev); 4223 } 4224 4225 static const struct dev_pm_ops panel_simple_pm_ops = { 4226 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4227 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4228 pm_runtime_force_resume) 4229 }; 4230 4231 static struct platform_driver panel_simple_platform_driver = { 4232 .driver = { 4233 .name = "panel-simple", 4234 .of_match_table = platform_of_match, 4235 .pm = &panel_simple_pm_ops, 4236 }, 4237 .probe = panel_simple_platform_probe, 4238 .remove = panel_simple_platform_remove, 4239 .shutdown = panel_simple_platform_shutdown, 4240 }; 4241 4242 struct panel_desc_dsi { 4243 struct panel_desc desc; 4244 4245 unsigned long flags; 4246 enum mipi_dsi_pixel_format format; 4247 unsigned int lanes; 4248 }; 4249 4250 static const struct drm_display_mode auo_b080uan01_mode = { 4251 .clock = 154500, 4252 .hdisplay = 1200, 4253 .hsync_start = 1200 + 62, 4254 .hsync_end = 1200 + 62 + 4, 4255 .htotal = 1200 + 62 + 4 + 62, 4256 .vdisplay = 1920, 4257 .vsync_start = 1920 + 9, 4258 .vsync_end = 1920 + 9 + 2, 4259 .vtotal = 1920 + 9 + 2 + 8, 4260 }; 4261 4262 static const struct panel_desc_dsi auo_b080uan01 = { 4263 .desc = { 4264 .modes = &auo_b080uan01_mode, 4265 .num_modes = 1, 4266 .bpc = 8, 4267 .size = { 4268 .width = 108, 4269 .height = 272, 4270 }, 4271 .connector_type = DRM_MODE_CONNECTOR_DSI, 4272 }, 4273 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4274 .format = MIPI_DSI_FMT_RGB888, 4275 .lanes = 4, 4276 }; 4277 4278 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4279 .clock = 160000, 4280 .hdisplay = 1200, 4281 .hsync_start = 1200 + 120, 4282 .hsync_end = 1200 + 120 + 20, 4283 .htotal = 1200 + 120 + 20 + 21, 4284 .vdisplay = 1920, 4285 .vsync_start = 1920 + 21, 4286 .vsync_end = 1920 + 21 + 3, 4287 .vtotal = 1920 + 21 + 3 + 18, 4288 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4289 }; 4290 4291 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4292 .desc = { 4293 .modes = &boe_tv080wum_nl0_mode, 4294 .num_modes = 1, 4295 .size = { 4296 .width = 107, 4297 .height = 172, 4298 }, 4299 .connector_type = DRM_MODE_CONNECTOR_DSI, 4300 }, 4301 .flags = MIPI_DSI_MODE_VIDEO | 4302 MIPI_DSI_MODE_VIDEO_BURST | 4303 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4304 .format = MIPI_DSI_FMT_RGB888, 4305 .lanes = 4, 4306 }; 4307 4308 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4309 .clock = 71000, 4310 .hdisplay = 800, 4311 .hsync_start = 800 + 32, 4312 .hsync_end = 800 + 32 + 1, 4313 .htotal = 800 + 32 + 1 + 57, 4314 .vdisplay = 1280, 4315 .vsync_start = 1280 + 28, 4316 .vsync_end = 1280 + 28 + 1, 4317 .vtotal = 1280 + 28 + 1 + 14, 4318 }; 4319 4320 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4321 .desc = { 4322 .modes = &lg_ld070wx3_sl01_mode, 4323 .num_modes = 1, 4324 .bpc = 8, 4325 .size = { 4326 .width = 94, 4327 .height = 151, 4328 }, 4329 .connector_type = DRM_MODE_CONNECTOR_DSI, 4330 }, 4331 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4332 .format = MIPI_DSI_FMT_RGB888, 4333 .lanes = 4, 4334 }; 4335 4336 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4337 .clock = 67000, 4338 .hdisplay = 720, 4339 .hsync_start = 720 + 12, 4340 .hsync_end = 720 + 12 + 4, 4341 .htotal = 720 + 12 + 4 + 112, 4342 .vdisplay = 1280, 4343 .vsync_start = 1280 + 8, 4344 .vsync_end = 1280 + 8 + 4, 4345 .vtotal = 1280 + 8 + 4 + 12, 4346 }; 4347 4348 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4349 .desc = { 4350 .modes = &lg_lh500wx1_sd03_mode, 4351 .num_modes = 1, 4352 .bpc = 8, 4353 .size = { 4354 .width = 62, 4355 .height = 110, 4356 }, 4357 .connector_type = DRM_MODE_CONNECTOR_DSI, 4358 }, 4359 .flags = MIPI_DSI_MODE_VIDEO, 4360 .format = MIPI_DSI_FMT_RGB888, 4361 .lanes = 4, 4362 }; 4363 4364 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4365 .clock = 157200, 4366 .hdisplay = 1920, 4367 .hsync_start = 1920 + 154, 4368 .hsync_end = 1920 + 154 + 16, 4369 .htotal = 1920 + 154 + 16 + 32, 4370 .vdisplay = 1200, 4371 .vsync_start = 1200 + 17, 4372 .vsync_end = 1200 + 17 + 2, 4373 .vtotal = 1200 + 17 + 2 + 16, 4374 }; 4375 4376 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4377 .desc = { 4378 .modes = &panasonic_vvx10f004b00_mode, 4379 .num_modes = 1, 4380 .bpc = 8, 4381 .size = { 4382 .width = 217, 4383 .height = 136, 4384 }, 4385 .connector_type = DRM_MODE_CONNECTOR_DSI, 4386 }, 4387 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4388 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4389 .format = MIPI_DSI_FMT_RGB888, 4390 .lanes = 4, 4391 }; 4392 4393 static const struct drm_display_mode lg_acx467akm_7_mode = { 4394 .clock = 150000, 4395 .hdisplay = 1080, 4396 .hsync_start = 1080 + 2, 4397 .hsync_end = 1080 + 2 + 2, 4398 .htotal = 1080 + 2 + 2 + 2, 4399 .vdisplay = 1920, 4400 .vsync_start = 1920 + 2, 4401 .vsync_end = 1920 + 2 + 2, 4402 .vtotal = 1920 + 2 + 2 + 2, 4403 }; 4404 4405 static const struct panel_desc_dsi lg_acx467akm_7 = { 4406 .desc = { 4407 .modes = &lg_acx467akm_7_mode, 4408 .num_modes = 1, 4409 .bpc = 8, 4410 .size = { 4411 .width = 62, 4412 .height = 110, 4413 }, 4414 .connector_type = DRM_MODE_CONNECTOR_DSI, 4415 }, 4416 .flags = 0, 4417 .format = MIPI_DSI_FMT_RGB888, 4418 .lanes = 4, 4419 }; 4420 4421 static const struct drm_display_mode osd101t2045_53ts_mode = { 4422 .clock = 154500, 4423 .hdisplay = 1920, 4424 .hsync_start = 1920 + 112, 4425 .hsync_end = 1920 + 112 + 16, 4426 .htotal = 1920 + 112 + 16 + 32, 4427 .vdisplay = 1200, 4428 .vsync_start = 1200 + 16, 4429 .vsync_end = 1200 + 16 + 2, 4430 .vtotal = 1200 + 16 + 2 + 16, 4431 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4432 }; 4433 4434 static const struct panel_desc_dsi osd101t2045_53ts = { 4435 .desc = { 4436 .modes = &osd101t2045_53ts_mode, 4437 .num_modes = 1, 4438 .bpc = 8, 4439 .size = { 4440 .width = 217, 4441 .height = 136, 4442 }, 4443 .connector_type = DRM_MODE_CONNECTOR_DSI, 4444 }, 4445 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4446 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4447 MIPI_DSI_MODE_NO_EOT_PACKET, 4448 .format = MIPI_DSI_FMT_RGB888, 4449 .lanes = 4, 4450 }; 4451 4452 static const struct of_device_id dsi_of_match[] = { 4453 { 4454 .compatible = "auo,b080uan01", 4455 .data = &auo_b080uan01 4456 }, { 4457 .compatible = "boe,tv080wum-nl0", 4458 .data = &boe_tv080wum_nl0 4459 }, { 4460 .compatible = "lg,ld070wx3-sl01", 4461 .data = &lg_ld070wx3_sl01 4462 }, { 4463 .compatible = "lg,lh500wx1-sd03", 4464 .data = &lg_lh500wx1_sd03 4465 }, { 4466 .compatible = "panasonic,vvx10f004b00", 4467 .data = &panasonic_vvx10f004b00 4468 }, { 4469 .compatible = "lg,acx467akm-7", 4470 .data = &lg_acx467akm_7 4471 }, { 4472 .compatible = "osddisplays,osd101t2045-53ts", 4473 .data = &osd101t2045_53ts 4474 }, { 4475 /* sentinel */ 4476 } 4477 }; 4478 MODULE_DEVICE_TABLE(of, dsi_of_match); 4479 4480 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4481 { 4482 const struct panel_desc_dsi *desc; 4483 const struct of_device_id *id; 4484 int err; 4485 4486 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4487 if (!id) 4488 return -ENODEV; 4489 4490 desc = id->data; 4491 4492 err = panel_simple_probe(&dsi->dev, &desc->desc); 4493 if (err < 0) 4494 return err; 4495 4496 dsi->mode_flags = desc->flags; 4497 dsi->format = desc->format; 4498 dsi->lanes = desc->lanes; 4499 4500 err = mipi_dsi_attach(dsi); 4501 if (err) { 4502 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4503 4504 drm_panel_remove(&panel->base); 4505 } 4506 4507 return err; 4508 } 4509 4510 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4511 { 4512 int err; 4513 4514 err = mipi_dsi_detach(dsi); 4515 if (err < 0) 4516 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4517 4518 return panel_simple_remove(&dsi->dev); 4519 } 4520 4521 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4522 { 4523 panel_simple_shutdown(&dsi->dev); 4524 } 4525 4526 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4527 .driver = { 4528 .name = "panel-simple-dsi", 4529 .of_match_table = dsi_of_match, 4530 .pm = &panel_simple_pm_ops, 4531 }, 4532 .probe = panel_simple_dsi_probe, 4533 .remove = panel_simple_dsi_remove, 4534 .shutdown = panel_simple_dsi_shutdown, 4535 }; 4536 4537 static int __init panel_simple_init(void) 4538 { 4539 int err; 4540 4541 err = platform_driver_register(&panel_simple_platform_driver); 4542 if (err < 0) 4543 return err; 4544 4545 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4546 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4547 if (err < 0) 4548 goto err_did_platform_register; 4549 } 4550 4551 return 0; 4552 4553 err_did_platform_register: 4554 platform_driver_unregister(&panel_simple_platform_driver); 4555 4556 return err; 4557 } 4558 module_init(panel_simple_init); 4559 4560 static void __exit panel_simple_exit(void) 4561 { 4562 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4563 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4564 4565 platform_driver_unregister(&panel_simple_platform_driver); 4566 } 4567 module_exit(panel_simple_exit); 4568 4569 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4570 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4571 MODULE_LICENSE("GPL and additional rights"); 4572