1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get_boottime(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) 579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 580 "failed to request GPIO\n"); 581 582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 583 if (err) { 584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 585 return err; 586 } 587 588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 589 if (ddc) { 590 panel->ddc = of_find_i2c_adapter_by_node(ddc); 591 of_node_put(ddc); 592 593 if (!panel->ddc) 594 return -EPROBE_DEFER; 595 } 596 597 if (desc == &panel_dpi) { 598 /* Handle the generic panel-dpi binding */ 599 err = panel_dpi_probe(dev, panel); 600 if (err) 601 goto free_ddc; 602 desc = panel->desc; 603 } else { 604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 605 panel_simple_parse_panel_timing_node(dev, panel, &dt); 606 } 607 608 connector_type = desc->connector_type; 609 /* Catch common mistakes for panels. */ 610 switch (connector_type) { 611 case 0: 612 dev_warn(dev, "Specify missing connector_type\n"); 613 connector_type = DRM_MODE_CONNECTOR_DPI; 614 break; 615 case DRM_MODE_CONNECTOR_LVDS: 616 WARN_ON(desc->bus_flags & 617 ~(DRM_BUS_FLAG_DE_LOW | 618 DRM_BUS_FLAG_DE_HIGH | 619 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 620 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bpc != 6); 626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 628 desc->bpc != 8); 629 break; 630 case DRM_MODE_CONNECTOR_eDP: 631 dev_warn(dev, "eDP panels moved to panel-edp\n"); 632 err = -EINVAL; 633 goto free_ddc; 634 case DRM_MODE_CONNECTOR_DSI: 635 if (desc->bpc != 6 && desc->bpc != 8) 636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 637 break; 638 case DRM_MODE_CONNECTOR_DPI: 639 bus_flags = DRM_BUS_FLAG_DE_LOW | 640 DRM_BUS_FLAG_DE_HIGH | 641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 647 if (desc->bus_flags & ~bus_flags) 648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 649 if (!(desc->bus_flags & bus_flags)) 650 dev_warn(dev, "Specify missing bus_flags\n"); 651 if (desc->bus_format == 0) 652 dev_warn(dev, "Specify missing bus_format\n"); 653 if (desc->bpc != 6 && desc->bpc != 8) 654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 655 break; 656 default: 657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 658 connector_type = DRM_MODE_CONNECTOR_DPI; 659 break; 660 } 661 662 dev_set_drvdata(dev, panel); 663 664 /* 665 * We use runtime PM for prepare / unprepare since those power the panel 666 * on and off and those can be very slow operations. This is important 667 * to optimize powering the panel on briefly to read the EDID before 668 * fully enabling the panel. 669 */ 670 pm_runtime_enable(dev); 671 pm_runtime_set_autosuspend_delay(dev, 1000); 672 pm_runtime_use_autosuspend(dev); 673 674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 675 676 err = drm_panel_of_backlight(&panel->base); 677 if (err) { 678 dev_err_probe(dev, err, "Could not find backlight\n"); 679 goto disable_pm_runtime; 680 } 681 682 drm_panel_add(&panel->base); 683 684 return 0; 685 686 disable_pm_runtime: 687 pm_runtime_dont_use_autosuspend(dev); 688 pm_runtime_disable(dev); 689 free_ddc: 690 if (panel->ddc) 691 put_device(&panel->ddc->dev); 692 693 return err; 694 } 695 696 static void panel_simple_remove(struct device *dev) 697 { 698 struct panel_simple *panel = dev_get_drvdata(dev); 699 700 drm_panel_remove(&panel->base); 701 drm_panel_disable(&panel->base); 702 drm_panel_unprepare(&panel->base); 703 704 pm_runtime_dont_use_autosuspend(dev); 705 pm_runtime_disable(dev); 706 if (panel->ddc) 707 put_device(&panel->ddc->dev); 708 } 709 710 static void panel_simple_shutdown(struct device *dev) 711 { 712 struct panel_simple *panel = dev_get_drvdata(dev); 713 714 drm_panel_disable(&panel->base); 715 drm_panel_unprepare(&panel->base); 716 } 717 718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 719 .clock = 71100, 720 .hdisplay = 1280, 721 .hsync_start = 1280 + 40, 722 .hsync_end = 1280 + 40 + 80, 723 .htotal = 1280 + 40 + 80 + 40, 724 .vdisplay = 800, 725 .vsync_start = 800 + 3, 726 .vsync_end = 800 + 3 + 10, 727 .vtotal = 800 + 3 + 10 + 10, 728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 729 }; 730 731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 732 .modes = &ire_am_1280800n3tzqw_t00h_mode, 733 .num_modes = 1, 734 .bpc = 8, 735 .size = { 736 .width = 217, 737 .height = 136, 738 }, 739 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 742 }; 743 744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 745 .clock = 9000, 746 .hdisplay = 480, 747 .hsync_start = 480 + 2, 748 .hsync_end = 480 + 2 + 41, 749 .htotal = 480 + 2 + 41 + 2, 750 .vdisplay = 272, 751 .vsync_start = 272 + 2, 752 .vsync_end = 272 + 2 + 10, 753 .vtotal = 272 + 2 + 10 + 2, 754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 755 }; 756 757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 758 .modes = &ire_am_480272h3tmqw_t01h_mode, 759 .num_modes = 1, 760 .bpc = 8, 761 .size = { 762 .width = 99, 763 .height = 58, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 766 }; 767 768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 769 .clock = 33333, 770 .hdisplay = 800, 771 .hsync_start = 800 + 0, 772 .hsync_end = 800 + 0 + 255, 773 .htotal = 800 + 0 + 255 + 0, 774 .vdisplay = 480, 775 .vsync_start = 480 + 2, 776 .vsync_end = 480 + 2 + 45, 777 .vtotal = 480 + 2 + 45 + 0, 778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 779 }; 780 781 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 782 .pixelclock = { 29930000, 33260000, 36590000 }, 783 .hactive = { 800, 800, 800 }, 784 .hfront_porch = { 1, 40, 168 }, 785 .hback_porch = { 88, 88, 88 }, 786 .hsync_len = { 1, 128, 128 }, 787 .vactive = { 480, 480, 480 }, 788 .vfront_porch = { 1, 35, 37 }, 789 .vback_porch = { 8, 8, 8 }, 790 .vsync_len = { 1, 2, 2 }, 791 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 792 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 793 DISPLAY_FLAGS_SYNC_POSEDGE, 794 }; 795 796 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 797 .timings = &ire_am_800480l1tmqw_t00h_timing, 798 .num_timings = 1, 799 .bpc = 8, 800 .size = { 801 .width = 111, 802 .height = 67, 803 }, 804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 806 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 807 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 808 .connector_type = DRM_MODE_CONNECTOR_DPI, 809 }; 810 811 static const struct panel_desc ampire_am800480r3tmqwa1h = { 812 .modes = &ire_am800480r3tmqwa1h_mode, 813 .num_modes = 1, 814 .bpc = 6, 815 .size = { 816 .width = 152, 817 .height = 91, 818 }, 819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 820 }; 821 822 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 823 .pixelclock = { 34500000, 39600000, 50400000 }, 824 .hactive = { 800, 800, 800 }, 825 .hfront_porch = { 12, 112, 312 }, 826 .hback_porch = { 87, 87, 48 }, 827 .hsync_len = { 1, 1, 40 }, 828 .vactive = { 600, 600, 600 }, 829 .vfront_porch = { 1, 21, 61 }, 830 .vback_porch = { 38, 38, 19 }, 831 .vsync_len = { 1, 1, 20 }, 832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 834 DISPLAY_FLAGS_SYNC_POSEDGE, 835 }; 836 837 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 838 .timings = &ire_am800600p5tmqw_tb8h_timing, 839 .num_timings = 1, 840 .bpc = 6, 841 .size = { 842 .width = 162, 843 .height = 122, 844 }, 845 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 846 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 847 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 848 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 849 .connector_type = DRM_MODE_CONNECTOR_DPI, 850 }; 851 852 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 853 .pixelclock = { 26400000, 33300000, 46800000 }, 854 .hactive = { 800, 800, 800 }, 855 .hfront_porch = { 16, 210, 354 }, 856 .hback_porch = { 45, 36, 6 }, 857 .hsync_len = { 1, 10, 40 }, 858 .vactive = { 480, 480, 480 }, 859 .vfront_porch = { 7, 22, 147 }, 860 .vback_porch = { 22, 13, 3 }, 861 .vsync_len = { 1, 10, 20 }, 862 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 863 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 864 }; 865 866 static const struct panel_desc armadeus_st0700_adapt = { 867 .timings = &santek_st0700i5y_rbslw_f_timing, 868 .num_timings = 1, 869 .bpc = 6, 870 .size = { 871 .width = 154, 872 .height = 86, 873 }, 874 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 875 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 876 }; 877 878 static const struct drm_display_mode auo_b101aw03_mode = { 879 .clock = 51450, 880 .hdisplay = 1024, 881 .hsync_start = 1024 + 156, 882 .hsync_end = 1024 + 156 + 8, 883 .htotal = 1024 + 156 + 8 + 156, 884 .vdisplay = 600, 885 .vsync_start = 600 + 16, 886 .vsync_end = 600 + 16 + 6, 887 .vtotal = 600 + 16 + 6 + 16, 888 }; 889 890 static const struct panel_desc auo_b101aw03 = { 891 .modes = &auo_b101aw03_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 223, 896 .height = 125, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 899 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 900 .connector_type = DRM_MODE_CONNECTOR_LVDS, 901 }; 902 903 static const struct drm_display_mode auo_b101xtn01_mode = { 904 .clock = 72000, 905 .hdisplay = 1366, 906 .hsync_start = 1366 + 20, 907 .hsync_end = 1366 + 20 + 70, 908 .htotal = 1366 + 20 + 70, 909 .vdisplay = 768, 910 .vsync_start = 768 + 14, 911 .vsync_end = 768 + 14 + 42, 912 .vtotal = 768 + 14 + 42, 913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 914 }; 915 916 static const struct panel_desc auo_b101xtn01 = { 917 .modes = &auo_b101xtn01_mode, 918 .num_modes = 1, 919 .bpc = 6, 920 .size = { 921 .width = 223, 922 .height = 125, 923 }, 924 }; 925 926 static const struct display_timing auo_g070vvn01_timings = { 927 .pixelclock = { 33300000, 34209000, 45000000 }, 928 .hactive = { 800, 800, 800 }, 929 .hfront_porch = { 20, 40, 200 }, 930 .hback_porch = { 87, 40, 1 }, 931 .hsync_len = { 1, 48, 87 }, 932 .vactive = { 480, 480, 480 }, 933 .vfront_porch = { 5, 13, 200 }, 934 .vback_porch = { 31, 31, 29 }, 935 .vsync_len = { 1, 1, 3 }, 936 }; 937 938 static const struct panel_desc auo_g070vvn01 = { 939 .timings = &auo_g070vvn01_timings, 940 .num_timings = 1, 941 .bpc = 8, 942 .size = { 943 .width = 152, 944 .height = 91, 945 }, 946 .delay = { 947 .prepare = 200, 948 .enable = 50, 949 .disable = 50, 950 .unprepare = 1000, 951 }, 952 }; 953 954 static const struct drm_display_mode auo_g101evn010_mode = { 955 .clock = 68930, 956 .hdisplay = 1280, 957 .hsync_start = 1280 + 82, 958 .hsync_end = 1280 + 82 + 2, 959 .htotal = 1280 + 82 + 2 + 84, 960 .vdisplay = 800, 961 .vsync_start = 800 + 8, 962 .vsync_end = 800 + 8 + 2, 963 .vtotal = 800 + 8 + 2 + 6, 964 }; 965 966 static const struct panel_desc auo_g101evn010 = { 967 .modes = &auo_g101evn010_mode, 968 .num_modes = 1, 969 .bpc = 6, 970 .size = { 971 .width = 216, 972 .height = 135, 973 }, 974 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 975 .connector_type = DRM_MODE_CONNECTOR_LVDS, 976 }; 977 978 static const struct drm_display_mode auo_g104sn02_mode = { 979 .clock = 40000, 980 .hdisplay = 800, 981 .hsync_start = 800 + 40, 982 .hsync_end = 800 + 40 + 216, 983 .htotal = 800 + 40 + 216 + 128, 984 .vdisplay = 600, 985 .vsync_start = 600 + 10, 986 .vsync_end = 600 + 10 + 35, 987 .vtotal = 600 + 10 + 35 + 2, 988 }; 989 990 static const struct panel_desc auo_g104sn02 = { 991 .modes = &auo_g104sn02_mode, 992 .num_modes = 1, 993 .bpc = 8, 994 .size = { 995 .width = 211, 996 .height = 158, 997 }, 998 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 999 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1000 }; 1001 1002 static const struct drm_display_mode auo_g121ean01_mode = { 1003 .clock = 66700, 1004 .hdisplay = 1280, 1005 .hsync_start = 1280 + 58, 1006 .hsync_end = 1280 + 58 + 8, 1007 .htotal = 1280 + 58 + 8 + 70, 1008 .vdisplay = 800, 1009 .vsync_start = 800 + 6, 1010 .vsync_end = 800 + 6 + 4, 1011 .vtotal = 800 + 6 + 4 + 10, 1012 }; 1013 1014 static const struct panel_desc auo_g121ean01 = { 1015 .modes = &auo_g121ean01_mode, 1016 .num_modes = 1, 1017 .bpc = 8, 1018 .size = { 1019 .width = 261, 1020 .height = 163, 1021 }, 1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1024 }; 1025 1026 static const struct display_timing auo_g133han01_timings = { 1027 .pixelclock = { 134000000, 141200000, 149000000 }, 1028 .hactive = { 1920, 1920, 1920 }, 1029 .hfront_porch = { 39, 58, 77 }, 1030 .hback_porch = { 59, 88, 117 }, 1031 .hsync_len = { 28, 42, 56 }, 1032 .vactive = { 1080, 1080, 1080 }, 1033 .vfront_porch = { 3, 8, 11 }, 1034 .vback_porch = { 5, 14, 19 }, 1035 .vsync_len = { 4, 14, 19 }, 1036 }; 1037 1038 static const struct panel_desc auo_g133han01 = { 1039 .timings = &auo_g133han01_timings, 1040 .num_timings = 1, 1041 .bpc = 8, 1042 .size = { 1043 .width = 293, 1044 .height = 165, 1045 }, 1046 .delay = { 1047 .prepare = 200, 1048 .enable = 50, 1049 .disable = 50, 1050 .unprepare = 1000, 1051 }, 1052 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1053 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1054 }; 1055 1056 static const struct drm_display_mode auo_g156xtn01_mode = { 1057 .clock = 76000, 1058 .hdisplay = 1366, 1059 .hsync_start = 1366 + 33, 1060 .hsync_end = 1366 + 33 + 67, 1061 .htotal = 1560, 1062 .vdisplay = 768, 1063 .vsync_start = 768 + 4, 1064 .vsync_end = 768 + 4 + 4, 1065 .vtotal = 806, 1066 }; 1067 1068 static const struct panel_desc auo_g156xtn01 = { 1069 .modes = &auo_g156xtn01_mode, 1070 .num_modes = 1, 1071 .bpc = 8, 1072 .size = { 1073 .width = 344, 1074 .height = 194, 1075 }, 1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1077 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1078 }; 1079 1080 static const struct display_timing auo_g185han01_timings = { 1081 .pixelclock = { 120000000, 144000000, 175000000 }, 1082 .hactive = { 1920, 1920, 1920 }, 1083 .hfront_porch = { 36, 120, 148 }, 1084 .hback_porch = { 24, 88, 108 }, 1085 .hsync_len = { 20, 48, 64 }, 1086 .vactive = { 1080, 1080, 1080 }, 1087 .vfront_porch = { 6, 10, 40 }, 1088 .vback_porch = { 2, 5, 20 }, 1089 .vsync_len = { 2, 5, 20 }, 1090 }; 1091 1092 static const struct panel_desc auo_g185han01 = { 1093 .timings = &auo_g185han01_timings, 1094 .num_timings = 1, 1095 .bpc = 8, 1096 .size = { 1097 .width = 409, 1098 .height = 230, 1099 }, 1100 .delay = { 1101 .prepare = 50, 1102 .enable = 200, 1103 .disable = 110, 1104 .unprepare = 1000, 1105 }, 1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1108 }; 1109 1110 static const struct display_timing auo_g190ean01_timings = { 1111 .pixelclock = { 90000000, 108000000, 135000000 }, 1112 .hactive = { 1280, 1280, 1280 }, 1113 .hfront_porch = { 126, 184, 1266 }, 1114 .hback_porch = { 84, 122, 844 }, 1115 .hsync_len = { 70, 102, 704 }, 1116 .vactive = { 1024, 1024, 1024 }, 1117 .vfront_porch = { 4, 26, 76 }, 1118 .vback_porch = { 2, 8, 25 }, 1119 .vsync_len = { 2, 8, 25 }, 1120 }; 1121 1122 static const struct panel_desc auo_g190ean01 = { 1123 .timings = &auo_g190ean01_timings, 1124 .num_timings = 1, 1125 .bpc = 8, 1126 .size = { 1127 .width = 376, 1128 .height = 301, 1129 }, 1130 .delay = { 1131 .prepare = 50, 1132 .enable = 200, 1133 .disable = 110, 1134 .unprepare = 1000, 1135 }, 1136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1137 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1138 }; 1139 1140 static const struct display_timing auo_p320hvn03_timings = { 1141 .pixelclock = { 106000000, 148500000, 164000000 }, 1142 .hactive = { 1920, 1920, 1920 }, 1143 .hfront_porch = { 25, 50, 130 }, 1144 .hback_porch = { 25, 50, 130 }, 1145 .hsync_len = { 20, 40, 105 }, 1146 .vactive = { 1080, 1080, 1080 }, 1147 .vfront_porch = { 8, 17, 150 }, 1148 .vback_porch = { 8, 17, 150 }, 1149 .vsync_len = { 4, 11, 100 }, 1150 }; 1151 1152 static const struct panel_desc auo_p320hvn03 = { 1153 .timings = &auo_p320hvn03_timings, 1154 .num_timings = 1, 1155 .bpc = 8, 1156 .size = { 1157 .width = 698, 1158 .height = 393, 1159 }, 1160 .delay = { 1161 .prepare = 1, 1162 .enable = 450, 1163 .unprepare = 500, 1164 }, 1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1167 }; 1168 1169 static const struct drm_display_mode auo_t215hvn01_mode = { 1170 .clock = 148800, 1171 .hdisplay = 1920, 1172 .hsync_start = 1920 + 88, 1173 .hsync_end = 1920 + 88 + 44, 1174 .htotal = 1920 + 88 + 44 + 148, 1175 .vdisplay = 1080, 1176 .vsync_start = 1080 + 4, 1177 .vsync_end = 1080 + 4 + 5, 1178 .vtotal = 1080 + 4 + 5 + 36, 1179 }; 1180 1181 static const struct panel_desc auo_t215hvn01 = { 1182 .modes = &auo_t215hvn01_mode, 1183 .num_modes = 1, 1184 .bpc = 8, 1185 .size = { 1186 .width = 430, 1187 .height = 270, 1188 }, 1189 .delay = { 1190 .disable = 5, 1191 .unprepare = 1000, 1192 } 1193 }; 1194 1195 static const struct drm_display_mode avic_tm070ddh03_mode = { 1196 .clock = 51200, 1197 .hdisplay = 1024, 1198 .hsync_start = 1024 + 160, 1199 .hsync_end = 1024 + 160 + 4, 1200 .htotal = 1024 + 160 + 4 + 156, 1201 .vdisplay = 600, 1202 .vsync_start = 600 + 17, 1203 .vsync_end = 600 + 17 + 1, 1204 .vtotal = 600 + 17 + 1 + 17, 1205 }; 1206 1207 static const struct panel_desc avic_tm070ddh03 = { 1208 .modes = &avic_tm070ddh03_mode, 1209 .num_modes = 1, 1210 .bpc = 8, 1211 .size = { 1212 .width = 154, 1213 .height = 90, 1214 }, 1215 .delay = { 1216 .prepare = 20, 1217 .enable = 200, 1218 .disable = 200, 1219 }, 1220 }; 1221 1222 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1223 .clock = 30000, 1224 .hdisplay = 800, 1225 .hsync_start = 800 + 40, 1226 .hsync_end = 800 + 40 + 48, 1227 .htotal = 800 + 40 + 48 + 40, 1228 .vdisplay = 480, 1229 .vsync_start = 480 + 13, 1230 .vsync_end = 480 + 13 + 3, 1231 .vtotal = 480 + 13 + 3 + 29, 1232 }; 1233 1234 static const struct panel_desc bananapi_s070wv20_ct16 = { 1235 .modes = &bananapi_s070wv20_ct16_mode, 1236 .num_modes = 1, 1237 .bpc = 6, 1238 .size = { 1239 .width = 154, 1240 .height = 86, 1241 }, 1242 }; 1243 1244 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1245 .pixelclock = { 69922000, 71000000, 72293000 }, 1246 .hactive = { 1280, 1280, 1280 }, 1247 .hfront_porch = { 48, 48, 48 }, 1248 .hback_porch = { 80, 80, 80 }, 1249 .hsync_len = { 32, 32, 32 }, 1250 .vactive = { 800, 800, 800 }, 1251 .vfront_porch = { 3, 3, 3 }, 1252 .vback_porch = { 14, 14, 14 }, 1253 .vsync_len = { 6, 6, 6 }, 1254 }; 1255 1256 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1257 .timings = &boe_ev121wxm_n10_1850_timing, 1258 .num_timings = 1, 1259 .bpc = 8, 1260 .size = { 1261 .width = 261, 1262 .height = 163, 1263 }, 1264 .delay = { 1265 .prepare = 9, 1266 .enable = 300, 1267 .unprepare = 300, 1268 .disable = 560, 1269 }, 1270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1271 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1272 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1273 }; 1274 1275 static const struct drm_display_mode boe_hv070wsa_mode = { 1276 .clock = 42105, 1277 .hdisplay = 1024, 1278 .hsync_start = 1024 + 30, 1279 .hsync_end = 1024 + 30 + 30, 1280 .htotal = 1024 + 30 + 30 + 30, 1281 .vdisplay = 600, 1282 .vsync_start = 600 + 10, 1283 .vsync_end = 600 + 10 + 10, 1284 .vtotal = 600 + 10 + 10 + 10, 1285 }; 1286 1287 static const struct panel_desc boe_hv070wsa = { 1288 .modes = &boe_hv070wsa_mode, 1289 .num_modes = 1, 1290 .bpc = 8, 1291 .size = { 1292 .width = 154, 1293 .height = 90, 1294 }, 1295 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1296 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1297 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1298 }; 1299 1300 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1301 .clock = 9000, 1302 .hdisplay = 480, 1303 .hsync_start = 480 + 5, 1304 .hsync_end = 480 + 5 + 5, 1305 .htotal = 480 + 5 + 5 + 40, 1306 .vdisplay = 272, 1307 .vsync_start = 272 + 8, 1308 .vsync_end = 272 + 8 + 8, 1309 .vtotal = 272 + 8 + 8 + 8, 1310 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1311 }; 1312 1313 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1314 .modes = &cdtech_s043wq26h_ct7_mode, 1315 .num_modes = 1, 1316 .bpc = 8, 1317 .size = { 1318 .width = 95, 1319 .height = 54, 1320 }, 1321 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1322 }; 1323 1324 /* S070PWS19HP-FC21 2017/04/22 */ 1325 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1326 .clock = 51200, 1327 .hdisplay = 1024, 1328 .hsync_start = 1024 + 160, 1329 .hsync_end = 1024 + 160 + 20, 1330 .htotal = 1024 + 160 + 20 + 140, 1331 .vdisplay = 600, 1332 .vsync_start = 600 + 12, 1333 .vsync_end = 600 + 12 + 3, 1334 .vtotal = 600 + 12 + 3 + 20, 1335 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1336 }; 1337 1338 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1339 .modes = &cdtech_s070pws19hp_fc21_mode, 1340 .num_modes = 1, 1341 .bpc = 6, 1342 .size = { 1343 .width = 154, 1344 .height = 86, 1345 }, 1346 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1347 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1348 .connector_type = DRM_MODE_CONNECTOR_DPI, 1349 }; 1350 1351 /* S070SWV29HG-DC44 2017/09/21 */ 1352 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1353 .clock = 33300, 1354 .hdisplay = 800, 1355 .hsync_start = 800 + 210, 1356 .hsync_end = 800 + 210 + 2, 1357 .htotal = 800 + 210 + 2 + 44, 1358 .vdisplay = 480, 1359 .vsync_start = 480 + 22, 1360 .vsync_end = 480 + 22 + 2, 1361 .vtotal = 480 + 22 + 2 + 21, 1362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1363 }; 1364 1365 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1366 .modes = &cdtech_s070swv29hg_dc44_mode, 1367 .num_modes = 1, 1368 .bpc = 6, 1369 .size = { 1370 .width = 154, 1371 .height = 86, 1372 }, 1373 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1375 .connector_type = DRM_MODE_CONNECTOR_DPI, 1376 }; 1377 1378 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1379 .clock = 35000, 1380 .hdisplay = 800, 1381 .hsync_start = 800 + 40, 1382 .hsync_end = 800 + 40 + 40, 1383 .htotal = 800 + 40 + 40 + 48, 1384 .vdisplay = 480, 1385 .vsync_start = 480 + 29, 1386 .vsync_end = 480 + 29 + 13, 1387 .vtotal = 480 + 29 + 13 + 3, 1388 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1389 }; 1390 1391 static const struct panel_desc cdtech_s070wv95_ct16 = { 1392 .modes = &cdtech_s070wv95_ct16_mode, 1393 .num_modes = 1, 1394 .bpc = 8, 1395 .size = { 1396 .width = 154, 1397 .height = 85, 1398 }, 1399 }; 1400 1401 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1402 .pixelclock = { 68900000, 71100000, 73400000 }, 1403 .hactive = { 1280, 1280, 1280 }, 1404 .hfront_porch = { 65, 80, 95 }, 1405 .hback_porch = { 64, 79, 94 }, 1406 .hsync_len = { 1, 1, 1 }, 1407 .vactive = { 800, 800, 800 }, 1408 .vfront_porch = { 7, 11, 14 }, 1409 .vback_porch = { 7, 11, 14 }, 1410 .vsync_len = { 1, 1, 1 }, 1411 .flags = DISPLAY_FLAGS_DE_HIGH, 1412 }; 1413 1414 static const struct panel_desc chefree_ch101olhlwh_002 = { 1415 .timings = &chefree_ch101olhlwh_002_timing, 1416 .num_timings = 1, 1417 .bpc = 8, 1418 .size = { 1419 .width = 217, 1420 .height = 135, 1421 }, 1422 .delay = { 1423 .enable = 200, 1424 .disable = 200, 1425 }, 1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1427 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1428 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1429 }; 1430 1431 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1432 .clock = 66770, 1433 .hdisplay = 800, 1434 .hsync_start = 800 + 49, 1435 .hsync_end = 800 + 49 + 33, 1436 .htotal = 800 + 49 + 33 + 17, 1437 .vdisplay = 1280, 1438 .vsync_start = 1280 + 1, 1439 .vsync_end = 1280 + 1 + 7, 1440 .vtotal = 1280 + 1 + 7 + 15, 1441 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1442 }; 1443 1444 static const struct panel_desc chunghwa_claa070wp03xg = { 1445 .modes = &chunghwa_claa070wp03xg_mode, 1446 .num_modes = 1, 1447 .bpc = 6, 1448 .size = { 1449 .width = 94, 1450 .height = 150, 1451 }, 1452 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1453 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1454 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1455 }; 1456 1457 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1458 .clock = 72070, 1459 .hdisplay = 1366, 1460 .hsync_start = 1366 + 58, 1461 .hsync_end = 1366 + 58 + 58, 1462 .htotal = 1366 + 58 + 58 + 58, 1463 .vdisplay = 768, 1464 .vsync_start = 768 + 4, 1465 .vsync_end = 768 + 4 + 4, 1466 .vtotal = 768 + 4 + 4 + 4, 1467 }; 1468 1469 static const struct panel_desc chunghwa_claa101wa01a = { 1470 .modes = &chunghwa_claa101wa01a_mode, 1471 .num_modes = 1, 1472 .bpc = 6, 1473 .size = { 1474 .width = 220, 1475 .height = 120, 1476 }, 1477 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1478 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1480 }; 1481 1482 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1483 .clock = 69300, 1484 .hdisplay = 1366, 1485 .hsync_start = 1366 + 48, 1486 .hsync_end = 1366 + 48 + 32, 1487 .htotal = 1366 + 48 + 32 + 20, 1488 .vdisplay = 768, 1489 .vsync_start = 768 + 16, 1490 .vsync_end = 768 + 16 + 8, 1491 .vtotal = 768 + 16 + 8 + 16, 1492 }; 1493 1494 static const struct panel_desc chunghwa_claa101wb01 = { 1495 .modes = &chunghwa_claa101wb01_mode, 1496 .num_modes = 1, 1497 .bpc = 6, 1498 .size = { 1499 .width = 223, 1500 .height = 125, 1501 }, 1502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1503 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1504 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1505 }; 1506 1507 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1508 .pixelclock = { 5000000, 9000000, 12000000 }, 1509 .hactive = { 480, 480, 480 }, 1510 .hfront_porch = { 12, 12, 12 }, 1511 .hback_porch = { 12, 12, 12 }, 1512 .hsync_len = { 21, 21, 21 }, 1513 .vactive = { 272, 272, 272 }, 1514 .vfront_porch = { 4, 4, 4 }, 1515 .vback_porch = { 4, 4, 4 }, 1516 .vsync_len = { 8, 8, 8 }, 1517 }; 1518 1519 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1520 .timings = &dataimage_fg040346dsswbg04_timing, 1521 .num_timings = 1, 1522 .bpc = 8, 1523 .size = { 1524 .width = 95, 1525 .height = 54, 1526 }, 1527 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1528 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1529 .connector_type = DRM_MODE_CONNECTOR_DPI, 1530 }; 1531 1532 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1533 .pixelclock = { 68900000, 71110000, 73400000 }, 1534 .hactive = { 1280, 1280, 1280 }, 1535 .vactive = { 800, 800, 800 }, 1536 .hback_porch = { 100, 100, 100 }, 1537 .hfront_porch = { 100, 100, 100 }, 1538 .vback_porch = { 5, 5, 5 }, 1539 .vfront_porch = { 5, 5, 5 }, 1540 .hsync_len = { 24, 24, 24 }, 1541 .vsync_len = { 3, 3, 3 }, 1542 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1543 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1544 }; 1545 1546 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1547 .timings = &dataimage_fg1001l0dsswmg01_timing, 1548 .num_timings = 1, 1549 .bpc = 8, 1550 .size = { 1551 .width = 217, 1552 .height = 136, 1553 }, 1554 }; 1555 1556 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1557 .clock = 33260, 1558 .hdisplay = 800, 1559 .hsync_start = 800 + 40, 1560 .hsync_end = 800 + 40 + 128, 1561 .htotal = 800 + 40 + 128 + 88, 1562 .vdisplay = 480, 1563 .vsync_start = 480 + 10, 1564 .vsync_end = 480 + 10 + 2, 1565 .vtotal = 480 + 10 + 2 + 33, 1566 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1567 }; 1568 1569 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1570 .modes = &dataimage_scf0700c48ggu18_mode, 1571 .num_modes = 1, 1572 .bpc = 8, 1573 .size = { 1574 .width = 152, 1575 .height = 91, 1576 }, 1577 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1578 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1579 }; 1580 1581 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1582 .pixelclock = { 45000000, 51200000, 57000000 }, 1583 .hactive = { 1024, 1024, 1024 }, 1584 .hfront_porch = { 100, 106, 113 }, 1585 .hback_porch = { 100, 106, 113 }, 1586 .hsync_len = { 100, 108, 114 }, 1587 .vactive = { 600, 600, 600 }, 1588 .vfront_porch = { 8, 11, 15 }, 1589 .vback_porch = { 8, 11, 15 }, 1590 .vsync_len = { 9, 13, 15 }, 1591 .flags = DISPLAY_FLAGS_DE_HIGH, 1592 }; 1593 1594 static const struct panel_desc dlc_dlc0700yzg_1 = { 1595 .timings = &dlc_dlc0700yzg_1_timing, 1596 .num_timings = 1, 1597 .bpc = 6, 1598 .size = { 1599 .width = 154, 1600 .height = 86, 1601 }, 1602 .delay = { 1603 .prepare = 30, 1604 .enable = 200, 1605 .disable = 200, 1606 }, 1607 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1608 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1609 }; 1610 1611 static const struct display_timing dlc_dlc1010gig_timing = { 1612 .pixelclock = { 68900000, 71100000, 73400000 }, 1613 .hactive = { 1280, 1280, 1280 }, 1614 .hfront_porch = { 43, 53, 63 }, 1615 .hback_porch = { 43, 53, 63 }, 1616 .hsync_len = { 44, 54, 64 }, 1617 .vactive = { 800, 800, 800 }, 1618 .vfront_porch = { 5, 8, 11 }, 1619 .vback_porch = { 5, 8, 11 }, 1620 .vsync_len = { 5, 7, 11 }, 1621 .flags = DISPLAY_FLAGS_DE_HIGH, 1622 }; 1623 1624 static const struct panel_desc dlc_dlc1010gig = { 1625 .timings = &dlc_dlc1010gig_timing, 1626 .num_timings = 1, 1627 .bpc = 8, 1628 .size = { 1629 .width = 216, 1630 .height = 135, 1631 }, 1632 .delay = { 1633 .prepare = 60, 1634 .enable = 150, 1635 .disable = 100, 1636 .unprepare = 60, 1637 }, 1638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1639 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1640 }; 1641 1642 static const struct drm_display_mode edt_et035012dm6_mode = { 1643 .clock = 6500, 1644 .hdisplay = 320, 1645 .hsync_start = 320 + 20, 1646 .hsync_end = 320 + 20 + 30, 1647 .htotal = 320 + 20 + 68, 1648 .vdisplay = 240, 1649 .vsync_start = 240 + 4, 1650 .vsync_end = 240 + 4 + 4, 1651 .vtotal = 240 + 4 + 4 + 14, 1652 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1653 }; 1654 1655 static const struct panel_desc edt_et035012dm6 = { 1656 .modes = &edt_et035012dm6_mode, 1657 .num_modes = 1, 1658 .bpc = 8, 1659 .size = { 1660 .width = 70, 1661 .height = 52, 1662 }, 1663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1664 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1665 }; 1666 1667 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1668 .clock = 6520, 1669 .hdisplay = 320, 1670 .hsync_start = 320 + 20, 1671 .hsync_end = 320 + 20 + 68, 1672 .htotal = 320 + 20 + 68, 1673 .vdisplay = 240, 1674 .vsync_start = 240 + 4, 1675 .vsync_end = 240 + 4 + 18, 1676 .vtotal = 240 + 4 + 18, 1677 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1678 }; 1679 1680 static const struct panel_desc edt_etm0350g0dh6 = { 1681 .modes = &edt_etm0350g0dh6_mode, 1682 .num_modes = 1, 1683 .bpc = 6, 1684 .size = { 1685 .width = 70, 1686 .height = 53, 1687 }, 1688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1690 .connector_type = DRM_MODE_CONNECTOR_DPI, 1691 }; 1692 1693 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1694 .clock = 10870, 1695 .hdisplay = 480, 1696 .hsync_start = 480 + 8, 1697 .hsync_end = 480 + 8 + 4, 1698 .htotal = 480 + 8 + 4 + 41, 1699 1700 /* 1701 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1702 * fb_align 1703 */ 1704 1705 .vdisplay = 288, 1706 .vsync_start = 288 + 2, 1707 .vsync_end = 288 + 2 + 4, 1708 .vtotal = 288 + 2 + 4 + 10, 1709 }; 1710 1711 static const struct panel_desc edt_etm043080dh6gp = { 1712 .modes = &edt_etm043080dh6gp_mode, 1713 .num_modes = 1, 1714 .bpc = 8, 1715 .size = { 1716 .width = 100, 1717 .height = 65, 1718 }, 1719 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1720 .connector_type = DRM_MODE_CONNECTOR_DPI, 1721 }; 1722 1723 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1724 .clock = 9000, 1725 .hdisplay = 480, 1726 .hsync_start = 480 + 2, 1727 .hsync_end = 480 + 2 + 41, 1728 .htotal = 480 + 2 + 41 + 2, 1729 .vdisplay = 272, 1730 .vsync_start = 272 + 2, 1731 .vsync_end = 272 + 2 + 10, 1732 .vtotal = 272 + 2 + 10 + 2, 1733 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1734 }; 1735 1736 static const struct panel_desc edt_etm0430g0dh6 = { 1737 .modes = &edt_etm0430g0dh6_mode, 1738 .num_modes = 1, 1739 .bpc = 6, 1740 .size = { 1741 .width = 95, 1742 .height = 54, 1743 }, 1744 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1745 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1746 .connector_type = DRM_MODE_CONNECTOR_DPI, 1747 }; 1748 1749 static const struct drm_display_mode edt_et057090dhu_mode = { 1750 .clock = 25175, 1751 .hdisplay = 640, 1752 .hsync_start = 640 + 16, 1753 .hsync_end = 640 + 16 + 30, 1754 .htotal = 640 + 16 + 30 + 114, 1755 .vdisplay = 480, 1756 .vsync_start = 480 + 10, 1757 .vsync_end = 480 + 10 + 3, 1758 .vtotal = 480 + 10 + 3 + 32, 1759 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1760 }; 1761 1762 static const struct panel_desc edt_et057090dhu = { 1763 .modes = &edt_et057090dhu_mode, 1764 .num_modes = 1, 1765 .bpc = 6, 1766 .size = { 1767 .width = 115, 1768 .height = 86, 1769 }, 1770 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1772 .connector_type = DRM_MODE_CONNECTOR_DPI, 1773 }; 1774 1775 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1776 .clock = 33260, 1777 .hdisplay = 800, 1778 .hsync_start = 800 + 40, 1779 .hsync_end = 800 + 40 + 128, 1780 .htotal = 800 + 40 + 128 + 88, 1781 .vdisplay = 480, 1782 .vsync_start = 480 + 10, 1783 .vsync_end = 480 + 10 + 2, 1784 .vtotal = 480 + 10 + 2 + 33, 1785 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1786 }; 1787 1788 static const struct panel_desc edt_etm0700g0dh6 = { 1789 .modes = &edt_etm0700g0dh6_mode, 1790 .num_modes = 1, 1791 .bpc = 6, 1792 .size = { 1793 .width = 152, 1794 .height = 91, 1795 }, 1796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1797 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1798 .connector_type = DRM_MODE_CONNECTOR_DPI, 1799 }; 1800 1801 static const struct panel_desc edt_etm0700g0bdh6 = { 1802 .modes = &edt_etm0700g0dh6_mode, 1803 .num_modes = 1, 1804 .bpc = 6, 1805 .size = { 1806 .width = 152, 1807 .height = 91, 1808 }, 1809 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1810 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1811 .connector_type = DRM_MODE_CONNECTOR_DPI, 1812 }; 1813 1814 static const struct display_timing edt_etml0700y5dha_timing = { 1815 .pixelclock = { 40800000, 51200000, 67200000 }, 1816 .hactive = { 1024, 1024, 1024 }, 1817 .hfront_porch = { 30, 106, 125 }, 1818 .hback_porch = { 30, 106, 125 }, 1819 .hsync_len = { 30, 108, 126 }, 1820 .vactive = { 600, 600, 600 }, 1821 .vfront_porch = { 3, 12, 67}, 1822 .vback_porch = { 3, 12, 67 }, 1823 .vsync_len = { 4, 11, 66 }, 1824 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1825 DISPLAY_FLAGS_DE_HIGH, 1826 }; 1827 1828 static const struct panel_desc edt_etml0700y5dha = { 1829 .timings = &edt_etml0700y5dha_timing, 1830 .num_timings = 1, 1831 .bpc = 8, 1832 .size = { 1833 .width = 155, 1834 .height = 86, 1835 }, 1836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1837 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1838 }; 1839 1840 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1841 .clock = 25175, 1842 .hdisplay = 640, 1843 .hsync_start = 640, 1844 .hsync_end = 640 + 16, 1845 .htotal = 640 + 16 + 30 + 114, 1846 .vdisplay = 480, 1847 .vsync_start = 480 + 10, 1848 .vsync_end = 480 + 10 + 3, 1849 .vtotal = 480 + 10 + 3 + 35, 1850 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1851 }; 1852 1853 static const struct panel_desc edt_etmv570g2dhu = { 1854 .modes = &edt_etmv570g2dhu_mode, 1855 .num_modes = 1, 1856 .bpc = 6, 1857 .size = { 1858 .width = 115, 1859 .height = 86, 1860 }, 1861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1862 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1863 .connector_type = DRM_MODE_CONNECTOR_DPI, 1864 }; 1865 1866 static const struct display_timing eink_vb3300_kca_timing = { 1867 .pixelclock = { 40000000, 40000000, 40000000 }, 1868 .hactive = { 334, 334, 334 }, 1869 .hfront_porch = { 1, 1, 1 }, 1870 .hback_porch = { 1, 1, 1 }, 1871 .hsync_len = { 1, 1, 1 }, 1872 .vactive = { 1405, 1405, 1405 }, 1873 .vfront_porch = { 1, 1, 1 }, 1874 .vback_porch = { 1, 1, 1 }, 1875 .vsync_len = { 1, 1, 1 }, 1876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1878 }; 1879 1880 static const struct panel_desc eink_vb3300_kca = { 1881 .timings = &eink_vb3300_kca_timing, 1882 .num_timings = 1, 1883 .bpc = 6, 1884 .size = { 1885 .width = 157, 1886 .height = 209, 1887 }, 1888 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1890 .connector_type = DRM_MODE_CONNECTOR_DPI, 1891 }; 1892 1893 static const struct display_timing evervision_vgg804821_timing = { 1894 .pixelclock = { 27600000, 33300000, 50000000 }, 1895 .hactive = { 800, 800, 800 }, 1896 .hfront_porch = { 40, 66, 70 }, 1897 .hback_porch = { 40, 67, 70 }, 1898 .hsync_len = { 40, 67, 70 }, 1899 .vactive = { 480, 480, 480 }, 1900 .vfront_porch = { 6, 10, 10 }, 1901 .vback_porch = { 7, 11, 11 }, 1902 .vsync_len = { 7, 11, 11 }, 1903 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1904 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1905 DISPLAY_FLAGS_SYNC_NEGEDGE, 1906 }; 1907 1908 static const struct panel_desc evervision_vgg804821 = { 1909 .timings = &evervision_vgg804821_timing, 1910 .num_timings = 1, 1911 .bpc = 8, 1912 .size = { 1913 .width = 108, 1914 .height = 64, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1918 }; 1919 1920 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1921 .clock = 32260, 1922 .hdisplay = 800, 1923 .hsync_start = 800 + 168, 1924 .hsync_end = 800 + 168 + 64, 1925 .htotal = 800 + 168 + 64 + 88, 1926 .vdisplay = 480, 1927 .vsync_start = 480 + 37, 1928 .vsync_end = 480 + 37 + 2, 1929 .vtotal = 480 + 37 + 2 + 8, 1930 }; 1931 1932 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1933 .modes = &foxlink_fl500wvr00_a0t_mode, 1934 .num_modes = 1, 1935 .bpc = 8, 1936 .size = { 1937 .width = 108, 1938 .height = 65, 1939 }, 1940 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1941 }; 1942 1943 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1944 { /* 60 Hz */ 1945 .clock = 6000, 1946 .hdisplay = 320, 1947 .hsync_start = 320 + 44, 1948 .hsync_end = 320 + 44 + 16, 1949 .htotal = 320 + 44 + 16 + 20, 1950 .vdisplay = 240, 1951 .vsync_start = 240 + 2, 1952 .vsync_end = 240 + 2 + 6, 1953 .vtotal = 240 + 2 + 6 + 2, 1954 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1955 }, 1956 { /* 50 Hz */ 1957 .clock = 5400, 1958 .hdisplay = 320, 1959 .hsync_start = 320 + 56, 1960 .hsync_end = 320 + 56 + 16, 1961 .htotal = 320 + 56 + 16 + 40, 1962 .vdisplay = 240, 1963 .vsync_start = 240 + 2, 1964 .vsync_end = 240 + 2 + 6, 1965 .vtotal = 240 + 2 + 6 + 2, 1966 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1967 }, 1968 }; 1969 1970 static const struct panel_desc frida_frd350h54004 = { 1971 .modes = frida_frd350h54004_modes, 1972 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1973 .bpc = 8, 1974 .size = { 1975 .width = 77, 1976 .height = 64, 1977 }, 1978 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1980 .connector_type = DRM_MODE_CONNECTOR_DPI, 1981 }; 1982 1983 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1984 .clock = 67185, 1985 .hdisplay = 800, 1986 .hsync_start = 800 + 20, 1987 .hsync_end = 800 + 20 + 24, 1988 .htotal = 800 + 20 + 24 + 20, 1989 .vdisplay = 1280, 1990 .vsync_start = 1280 + 4, 1991 .vsync_end = 1280 + 4 + 8, 1992 .vtotal = 1280 + 4 + 8 + 4, 1993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1994 }; 1995 1996 static const struct panel_desc friendlyarm_hd702e = { 1997 .modes = &friendlyarm_hd702e_mode, 1998 .num_modes = 1, 1999 .size = { 2000 .width = 94, 2001 .height = 151, 2002 }, 2003 }; 2004 2005 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2006 .clock = 9000, 2007 .hdisplay = 480, 2008 .hsync_start = 480 + 5, 2009 .hsync_end = 480 + 5 + 1, 2010 .htotal = 480 + 5 + 1 + 40, 2011 .vdisplay = 272, 2012 .vsync_start = 272 + 8, 2013 .vsync_end = 272 + 8 + 1, 2014 .vtotal = 272 + 8 + 1 + 8, 2015 }; 2016 2017 static const struct panel_desc giantplus_gpg482739qs5 = { 2018 .modes = &giantplus_gpg482739qs5_mode, 2019 .num_modes = 1, 2020 .bpc = 8, 2021 .size = { 2022 .width = 95, 2023 .height = 54, 2024 }, 2025 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2026 }; 2027 2028 static const struct display_timing giantplus_gpm940b0_timing = { 2029 .pixelclock = { 13500000, 27000000, 27500000 }, 2030 .hactive = { 320, 320, 320 }, 2031 .hfront_porch = { 14, 686, 718 }, 2032 .hback_porch = { 50, 70, 255 }, 2033 .hsync_len = { 1, 1, 1 }, 2034 .vactive = { 240, 240, 240 }, 2035 .vfront_porch = { 1, 1, 179 }, 2036 .vback_porch = { 1, 21, 31 }, 2037 .vsync_len = { 1, 1, 6 }, 2038 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2039 }; 2040 2041 static const struct panel_desc giantplus_gpm940b0 = { 2042 .timings = &giantplus_gpm940b0_timing, 2043 .num_timings = 1, 2044 .bpc = 8, 2045 .size = { 2046 .width = 60, 2047 .height = 45, 2048 }, 2049 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2050 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2051 }; 2052 2053 static const struct display_timing hannstar_hsd070pww1_timing = { 2054 .pixelclock = { 64300000, 71100000, 82000000 }, 2055 .hactive = { 1280, 1280, 1280 }, 2056 .hfront_porch = { 1, 1, 10 }, 2057 .hback_porch = { 1, 1, 10 }, 2058 /* 2059 * According to the data sheet, the minimum horizontal blanking interval 2060 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2061 * minimum working horizontal blanking interval to be 60 clocks. 2062 */ 2063 .hsync_len = { 58, 158, 661 }, 2064 .vactive = { 800, 800, 800 }, 2065 .vfront_porch = { 1, 1, 10 }, 2066 .vback_porch = { 1, 1, 10 }, 2067 .vsync_len = { 1, 21, 203 }, 2068 .flags = DISPLAY_FLAGS_DE_HIGH, 2069 }; 2070 2071 static const struct panel_desc hannstar_hsd070pww1 = { 2072 .timings = &hannstar_hsd070pww1_timing, 2073 .num_timings = 1, 2074 .bpc = 6, 2075 .size = { 2076 .width = 151, 2077 .height = 94, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2081 }; 2082 2083 static const struct display_timing hannstar_hsd100pxn1_timing = { 2084 .pixelclock = { 55000000, 65000000, 75000000 }, 2085 .hactive = { 1024, 1024, 1024 }, 2086 .hfront_porch = { 40, 40, 40 }, 2087 .hback_porch = { 220, 220, 220 }, 2088 .hsync_len = { 20, 60, 100 }, 2089 .vactive = { 768, 768, 768 }, 2090 .vfront_porch = { 7, 7, 7 }, 2091 .vback_porch = { 21, 21, 21 }, 2092 .vsync_len = { 10, 10, 10 }, 2093 .flags = DISPLAY_FLAGS_DE_HIGH, 2094 }; 2095 2096 static const struct panel_desc hannstar_hsd100pxn1 = { 2097 .timings = &hannstar_hsd100pxn1_timing, 2098 .num_timings = 1, 2099 .bpc = 6, 2100 .size = { 2101 .width = 203, 2102 .height = 152, 2103 }, 2104 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2106 }; 2107 2108 static const struct display_timing hannstar_hsd101pww2_timing = { 2109 .pixelclock = { 64300000, 71100000, 82000000 }, 2110 .hactive = { 1280, 1280, 1280 }, 2111 .hfront_porch = { 1, 1, 10 }, 2112 .hback_porch = { 1, 1, 10 }, 2113 .hsync_len = { 58, 158, 661 }, 2114 .vactive = { 800, 800, 800 }, 2115 .vfront_porch = { 1, 1, 10 }, 2116 .vback_porch = { 1, 1, 10 }, 2117 .vsync_len = { 1, 21, 203 }, 2118 .flags = DISPLAY_FLAGS_DE_HIGH, 2119 }; 2120 2121 static const struct panel_desc hannstar_hsd101pww2 = { 2122 .timings = &hannstar_hsd101pww2_timing, 2123 .num_timings = 1, 2124 .bpc = 8, 2125 .size = { 2126 .width = 217, 2127 .height = 136, 2128 }, 2129 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2130 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2131 }; 2132 2133 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2134 .clock = 33333, 2135 .hdisplay = 800, 2136 .hsync_start = 800 + 85, 2137 .hsync_end = 800 + 85 + 86, 2138 .htotal = 800 + 85 + 86 + 85, 2139 .vdisplay = 480, 2140 .vsync_start = 480 + 16, 2141 .vsync_end = 480 + 16 + 13, 2142 .vtotal = 480 + 16 + 13 + 16, 2143 }; 2144 2145 static const struct panel_desc hitachi_tx23d38vm0caa = { 2146 .modes = &hitachi_tx23d38vm0caa_mode, 2147 .num_modes = 1, 2148 .bpc = 6, 2149 .size = { 2150 .width = 195, 2151 .height = 117, 2152 }, 2153 .delay = { 2154 .enable = 160, 2155 .disable = 160, 2156 }, 2157 }; 2158 2159 static const struct drm_display_mode innolux_at043tn24_mode = { 2160 .clock = 9000, 2161 .hdisplay = 480, 2162 .hsync_start = 480 + 2, 2163 .hsync_end = 480 + 2 + 41, 2164 .htotal = 480 + 2 + 41 + 2, 2165 .vdisplay = 272, 2166 .vsync_start = 272 + 2, 2167 .vsync_end = 272 + 2 + 10, 2168 .vtotal = 272 + 2 + 10 + 2, 2169 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2170 }; 2171 2172 static const struct panel_desc innolux_at043tn24 = { 2173 .modes = &innolux_at043tn24_mode, 2174 .num_modes = 1, 2175 .bpc = 8, 2176 .size = { 2177 .width = 95, 2178 .height = 54, 2179 }, 2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2181 .connector_type = DRM_MODE_CONNECTOR_DPI, 2182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2183 }; 2184 2185 static const struct drm_display_mode innolux_at070tn92_mode = { 2186 .clock = 33333, 2187 .hdisplay = 800, 2188 .hsync_start = 800 + 210, 2189 .hsync_end = 800 + 210 + 20, 2190 .htotal = 800 + 210 + 20 + 46, 2191 .vdisplay = 480, 2192 .vsync_start = 480 + 22, 2193 .vsync_end = 480 + 22 + 10, 2194 .vtotal = 480 + 22 + 23 + 10, 2195 }; 2196 2197 static const struct panel_desc innolux_at070tn92 = { 2198 .modes = &innolux_at070tn92_mode, 2199 .num_modes = 1, 2200 .size = { 2201 .width = 154, 2202 .height = 86, 2203 }, 2204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2205 }; 2206 2207 static const struct display_timing innolux_g070ace_l01_timing = { 2208 .pixelclock = { 25200000, 35000000, 35700000 }, 2209 .hactive = { 800, 800, 800 }, 2210 .hfront_porch = { 30, 32, 87 }, 2211 .hback_porch = { 30, 32, 87 }, 2212 .hsync_len = { 1, 1, 1 }, 2213 .vactive = { 480, 480, 480 }, 2214 .vfront_porch = { 3, 3, 3 }, 2215 .vback_porch = { 13, 13, 13 }, 2216 .vsync_len = { 1, 1, 4 }, 2217 .flags = DISPLAY_FLAGS_DE_HIGH, 2218 }; 2219 2220 static const struct panel_desc innolux_g070ace_l01 = { 2221 .timings = &innolux_g070ace_l01_timing, 2222 .num_timings = 1, 2223 .bpc = 8, 2224 .size = { 2225 .width = 152, 2226 .height = 91, 2227 }, 2228 .delay = { 2229 .prepare = 10, 2230 .enable = 50, 2231 .disable = 50, 2232 .unprepare = 500, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2235 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2236 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2237 }; 2238 2239 static const struct display_timing innolux_g070y2_l01_timing = { 2240 .pixelclock = { 28000000, 29500000, 32000000 }, 2241 .hactive = { 800, 800, 800 }, 2242 .hfront_porch = { 61, 91, 141 }, 2243 .hback_porch = { 60, 90, 140 }, 2244 .hsync_len = { 12, 12, 12 }, 2245 .vactive = { 480, 480, 480 }, 2246 .vfront_porch = { 4, 9, 30 }, 2247 .vback_porch = { 4, 8, 28 }, 2248 .vsync_len = { 2, 2, 2 }, 2249 .flags = DISPLAY_FLAGS_DE_HIGH, 2250 }; 2251 2252 static const struct panel_desc innolux_g070y2_l01 = { 2253 .timings = &innolux_g070y2_l01_timing, 2254 .num_timings = 1, 2255 .bpc = 8, 2256 .size = { 2257 .width = 152, 2258 .height = 91, 2259 }, 2260 .delay = { 2261 .prepare = 10, 2262 .enable = 100, 2263 .disable = 100, 2264 .unprepare = 800, 2265 }, 2266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2267 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2269 }; 2270 2271 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2272 .clock = 33333, 2273 .hdisplay = 800, 2274 .hsync_start = 800 + 210, 2275 .hsync_end = 800 + 210 + 20, 2276 .htotal = 800 + 210 + 20 + 46, 2277 .vdisplay = 480, 2278 .vsync_start = 480 + 22, 2279 .vsync_end = 480 + 22 + 10, 2280 .vtotal = 480 + 22 + 23 + 10, 2281 }; 2282 2283 static const struct panel_desc innolux_g070y2_t02 = { 2284 .modes = &innolux_g070y2_t02_mode, 2285 .num_modes = 1, 2286 .bpc = 8, 2287 .size = { 2288 .width = 152, 2289 .height = 92, 2290 }, 2291 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2292 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2293 .connector_type = DRM_MODE_CONNECTOR_DPI, 2294 }; 2295 2296 static const struct display_timing innolux_g101ice_l01_timing = { 2297 .pixelclock = { 60400000, 71100000, 74700000 }, 2298 .hactive = { 1280, 1280, 1280 }, 2299 .hfront_porch = { 41, 80, 100 }, 2300 .hback_porch = { 40, 79, 99 }, 2301 .hsync_len = { 1, 1, 1 }, 2302 .vactive = { 800, 800, 800 }, 2303 .vfront_porch = { 5, 11, 14 }, 2304 .vback_porch = { 4, 11, 14 }, 2305 .vsync_len = { 1, 1, 1 }, 2306 .flags = DISPLAY_FLAGS_DE_HIGH, 2307 }; 2308 2309 static const struct panel_desc innolux_g101ice_l01 = { 2310 .timings = &innolux_g101ice_l01_timing, 2311 .num_timings = 1, 2312 .bpc = 8, 2313 .size = { 2314 .width = 217, 2315 .height = 135, 2316 }, 2317 .delay = { 2318 .enable = 200, 2319 .disable = 200, 2320 }, 2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2322 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2323 }; 2324 2325 static const struct display_timing innolux_g121i1_l01_timing = { 2326 .pixelclock = { 67450000, 71000000, 74550000 }, 2327 .hactive = { 1280, 1280, 1280 }, 2328 .hfront_porch = { 40, 80, 160 }, 2329 .hback_porch = { 39, 79, 159 }, 2330 .hsync_len = { 1, 1, 1 }, 2331 .vactive = { 800, 800, 800 }, 2332 .vfront_porch = { 5, 11, 100 }, 2333 .vback_porch = { 4, 11, 99 }, 2334 .vsync_len = { 1, 1, 1 }, 2335 }; 2336 2337 static const struct panel_desc innolux_g121i1_l01 = { 2338 .timings = &innolux_g121i1_l01_timing, 2339 .num_timings = 1, 2340 .bpc = 6, 2341 .size = { 2342 .width = 261, 2343 .height = 163, 2344 }, 2345 .delay = { 2346 .enable = 200, 2347 .disable = 20, 2348 }, 2349 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2350 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2351 }; 2352 2353 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2354 .clock = 65000, 2355 .hdisplay = 1024, 2356 .hsync_start = 1024 + 0, 2357 .hsync_end = 1024 + 1, 2358 .htotal = 1024 + 0 + 1 + 320, 2359 .vdisplay = 768, 2360 .vsync_start = 768 + 38, 2361 .vsync_end = 768 + 38 + 1, 2362 .vtotal = 768 + 38 + 1 + 0, 2363 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2364 }; 2365 2366 static const struct panel_desc innolux_g121x1_l03 = { 2367 .modes = &innolux_g121x1_l03_mode, 2368 .num_modes = 1, 2369 .bpc = 6, 2370 .size = { 2371 .width = 246, 2372 .height = 185, 2373 }, 2374 .delay = { 2375 .enable = 200, 2376 .unprepare = 200, 2377 .disable = 400, 2378 }, 2379 }; 2380 2381 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2382 .clock = 69300, 2383 .hdisplay = 1366, 2384 .hsync_start = 1366 + 16, 2385 .hsync_end = 1366 + 16 + 34, 2386 .htotal = 1366 + 16 + 34 + 50, 2387 .vdisplay = 768, 2388 .vsync_start = 768 + 2, 2389 .vsync_end = 768 + 2 + 6, 2390 .vtotal = 768 + 2 + 6 + 12, 2391 }; 2392 2393 static const struct panel_desc innolux_n156bge_l21 = { 2394 .modes = &innolux_n156bge_l21_mode, 2395 .num_modes = 1, 2396 .bpc = 6, 2397 .size = { 2398 .width = 344, 2399 .height = 193, 2400 }, 2401 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2402 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2403 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2404 }; 2405 2406 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2407 .clock = 51501, 2408 .hdisplay = 1024, 2409 .hsync_start = 1024 + 128, 2410 .hsync_end = 1024 + 128 + 64, 2411 .htotal = 1024 + 128 + 64 + 128, 2412 .vdisplay = 600, 2413 .vsync_start = 600 + 16, 2414 .vsync_end = 600 + 16 + 4, 2415 .vtotal = 600 + 16 + 4 + 16, 2416 }; 2417 2418 static const struct panel_desc innolux_zj070na_01p = { 2419 .modes = &innolux_zj070na_01p_mode, 2420 .num_modes = 1, 2421 .bpc = 6, 2422 .size = { 2423 .width = 154, 2424 .height = 90, 2425 }, 2426 }; 2427 2428 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2429 .pixelclock = { 5580000, 5850000, 6200000 }, 2430 .hactive = { 320, 320, 320 }, 2431 .hfront_porch = { 30, 30, 30 }, 2432 .hback_porch = { 30, 30, 30 }, 2433 .hsync_len = { 1, 5, 17 }, 2434 .vactive = { 240, 240, 240 }, 2435 .vfront_porch = { 6, 6, 6 }, 2436 .vback_porch = { 5, 5, 5 }, 2437 .vsync_len = { 1, 2, 11 }, 2438 .flags = DISPLAY_FLAGS_DE_HIGH, 2439 }; 2440 2441 static const struct panel_desc koe_tx14d24vm1bpa = { 2442 .timings = &koe_tx14d24vm1bpa_timing, 2443 .num_timings = 1, 2444 .bpc = 6, 2445 .size = { 2446 .width = 115, 2447 .height = 86, 2448 }, 2449 }; 2450 2451 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2452 .pixelclock = { 151820000, 156720000, 159780000 }, 2453 .hactive = { 1920, 1920, 1920 }, 2454 .hfront_porch = { 105, 130, 142 }, 2455 .hback_porch = { 45, 70, 82 }, 2456 .hsync_len = { 30, 30, 30 }, 2457 .vactive = { 1200, 1200, 1200}, 2458 .vfront_porch = { 3, 5, 10 }, 2459 .vback_porch = { 2, 5, 10 }, 2460 .vsync_len = { 5, 5, 5 }, 2461 }; 2462 2463 static const struct panel_desc koe_tx26d202vm0bwa = { 2464 .timings = &koe_tx26d202vm0bwa_timing, 2465 .num_timings = 1, 2466 .bpc = 8, 2467 .size = { 2468 .width = 217, 2469 .height = 136, 2470 }, 2471 .delay = { 2472 .prepare = 1000, 2473 .enable = 1000, 2474 .unprepare = 1000, 2475 .disable = 1000, 2476 }, 2477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2478 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2480 }; 2481 2482 static const struct display_timing koe_tx31d200vm0baa_timing = { 2483 .pixelclock = { 39600000, 43200000, 48000000 }, 2484 .hactive = { 1280, 1280, 1280 }, 2485 .hfront_porch = { 16, 36, 56 }, 2486 .hback_porch = { 16, 36, 56 }, 2487 .hsync_len = { 8, 8, 8 }, 2488 .vactive = { 480, 480, 480 }, 2489 .vfront_porch = { 6, 21, 33 }, 2490 .vback_porch = { 6, 21, 33 }, 2491 .vsync_len = { 8, 8, 8 }, 2492 .flags = DISPLAY_FLAGS_DE_HIGH, 2493 }; 2494 2495 static const struct panel_desc koe_tx31d200vm0baa = { 2496 .timings = &koe_tx31d200vm0baa_timing, 2497 .num_timings = 1, 2498 .bpc = 6, 2499 .size = { 2500 .width = 292, 2501 .height = 109, 2502 }, 2503 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2504 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2505 }; 2506 2507 static const struct display_timing kyo_tcg121xglp_timing = { 2508 .pixelclock = { 52000000, 65000000, 71000000 }, 2509 .hactive = { 1024, 1024, 1024 }, 2510 .hfront_porch = { 2, 2, 2 }, 2511 .hback_porch = { 2, 2, 2 }, 2512 .hsync_len = { 86, 124, 244 }, 2513 .vactive = { 768, 768, 768 }, 2514 .vfront_porch = { 2, 2, 2 }, 2515 .vback_porch = { 2, 2, 2 }, 2516 .vsync_len = { 6, 34, 73 }, 2517 .flags = DISPLAY_FLAGS_DE_HIGH, 2518 }; 2519 2520 static const struct panel_desc kyo_tcg121xglp = { 2521 .timings = &kyo_tcg121xglp_timing, 2522 .num_timings = 1, 2523 .bpc = 8, 2524 .size = { 2525 .width = 246, 2526 .height = 184, 2527 }, 2528 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2529 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2530 }; 2531 2532 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2533 .clock = 7000, 2534 .hdisplay = 320, 2535 .hsync_start = 320 + 20, 2536 .hsync_end = 320 + 20 + 30, 2537 .htotal = 320 + 20 + 30 + 38, 2538 .vdisplay = 240, 2539 .vsync_start = 240 + 4, 2540 .vsync_end = 240 + 4 + 3, 2541 .vtotal = 240 + 4 + 3 + 15, 2542 }; 2543 2544 static const struct panel_desc lemaker_bl035_rgb_002 = { 2545 .modes = &lemaker_bl035_rgb_002_mode, 2546 .num_modes = 1, 2547 .size = { 2548 .width = 70, 2549 .height = 52, 2550 }, 2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2552 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2553 }; 2554 2555 static const struct drm_display_mode lg_lb070wv8_mode = { 2556 .clock = 33246, 2557 .hdisplay = 800, 2558 .hsync_start = 800 + 88, 2559 .hsync_end = 800 + 88 + 80, 2560 .htotal = 800 + 88 + 80 + 88, 2561 .vdisplay = 480, 2562 .vsync_start = 480 + 10, 2563 .vsync_end = 480 + 10 + 25, 2564 .vtotal = 480 + 10 + 25 + 10, 2565 }; 2566 2567 static const struct panel_desc lg_lb070wv8 = { 2568 .modes = &lg_lb070wv8_mode, 2569 .num_modes = 1, 2570 .bpc = 8, 2571 .size = { 2572 .width = 151, 2573 .height = 91, 2574 }, 2575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2577 }; 2578 2579 static const struct display_timing logictechno_lt161010_2nh_timing = { 2580 .pixelclock = { 26400000, 33300000, 46800000 }, 2581 .hactive = { 800, 800, 800 }, 2582 .hfront_porch = { 16, 210, 354 }, 2583 .hback_porch = { 46, 46, 46 }, 2584 .hsync_len = { 1, 20, 40 }, 2585 .vactive = { 480, 480, 480 }, 2586 .vfront_porch = { 7, 22, 147 }, 2587 .vback_porch = { 23, 23, 23 }, 2588 .vsync_len = { 1, 10, 20 }, 2589 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2590 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2591 DISPLAY_FLAGS_SYNC_POSEDGE, 2592 }; 2593 2594 static const struct panel_desc logictechno_lt161010_2nh = { 2595 .timings = &logictechno_lt161010_2nh_timing, 2596 .num_timings = 1, 2597 .bpc = 6, 2598 .size = { 2599 .width = 154, 2600 .height = 86, 2601 }, 2602 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2603 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2604 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2606 .connector_type = DRM_MODE_CONNECTOR_DPI, 2607 }; 2608 2609 static const struct display_timing logictechno_lt170410_2whc_timing = { 2610 .pixelclock = { 68900000, 71100000, 73400000 }, 2611 .hactive = { 1280, 1280, 1280 }, 2612 .hfront_porch = { 23, 60, 71 }, 2613 .hback_porch = { 23, 60, 71 }, 2614 .hsync_len = { 15, 40, 47 }, 2615 .vactive = { 800, 800, 800 }, 2616 .vfront_porch = { 5, 7, 10 }, 2617 .vback_porch = { 5, 7, 10 }, 2618 .vsync_len = { 6, 9, 12 }, 2619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2620 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2621 DISPLAY_FLAGS_SYNC_POSEDGE, 2622 }; 2623 2624 static const struct panel_desc logictechno_lt170410_2whc = { 2625 .timings = &logictechno_lt170410_2whc_timing, 2626 .num_timings = 1, 2627 .bpc = 8, 2628 .size = { 2629 .width = 217, 2630 .height = 136, 2631 }, 2632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2633 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2634 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2635 }; 2636 2637 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2638 .clock = 33000, 2639 .hdisplay = 800, 2640 .hsync_start = 800 + 112, 2641 .hsync_end = 800 + 112 + 3, 2642 .htotal = 800 + 112 + 3 + 85, 2643 .vdisplay = 480, 2644 .vsync_start = 480 + 38, 2645 .vsync_end = 480 + 38 + 3, 2646 .vtotal = 480 + 38 + 3 + 29, 2647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2648 }; 2649 2650 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2651 .modes = &logictechno_lttd800480070_l2rt_mode, 2652 .num_modes = 1, 2653 .bpc = 8, 2654 .size = { 2655 .width = 154, 2656 .height = 86, 2657 }, 2658 .delay = { 2659 .prepare = 45, 2660 .enable = 100, 2661 .disable = 100, 2662 .unprepare = 45 2663 }, 2664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2665 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2666 .connector_type = DRM_MODE_CONNECTOR_DPI, 2667 }; 2668 2669 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2670 .clock = 33000, 2671 .hdisplay = 800, 2672 .hsync_start = 800 + 154, 2673 .hsync_end = 800 + 154 + 3, 2674 .htotal = 800 + 154 + 3 + 43, 2675 .vdisplay = 480, 2676 .vsync_start = 480 + 47, 2677 .vsync_end = 480 + 47 + 3, 2678 .vtotal = 480 + 47 + 3 + 20, 2679 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2680 }; 2681 2682 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2683 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2684 .num_modes = 1, 2685 .bpc = 8, 2686 .size = { 2687 .width = 154, 2688 .height = 86, 2689 }, 2690 .delay = { 2691 .prepare = 45, 2692 .enable = 100, 2693 .disable = 100, 2694 .unprepare = 45 2695 }, 2696 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2697 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2698 .connector_type = DRM_MODE_CONNECTOR_DPI, 2699 }; 2700 2701 static const struct drm_display_mode logicpd_type_28_mode = { 2702 .clock = 9107, 2703 .hdisplay = 480, 2704 .hsync_start = 480 + 3, 2705 .hsync_end = 480 + 3 + 42, 2706 .htotal = 480 + 3 + 42 + 2, 2707 2708 .vdisplay = 272, 2709 .vsync_start = 272 + 2, 2710 .vsync_end = 272 + 2 + 11, 2711 .vtotal = 272 + 2 + 11 + 3, 2712 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2713 }; 2714 2715 static const struct panel_desc logicpd_type_28 = { 2716 .modes = &logicpd_type_28_mode, 2717 .num_modes = 1, 2718 .bpc = 8, 2719 .size = { 2720 .width = 105, 2721 .height = 67, 2722 }, 2723 .delay = { 2724 .prepare = 200, 2725 .enable = 200, 2726 .unprepare = 200, 2727 .disable = 200, 2728 }, 2729 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2730 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2731 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2732 .connector_type = DRM_MODE_CONNECTOR_DPI, 2733 }; 2734 2735 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2736 .clock = 30400, 2737 .hdisplay = 800, 2738 .hsync_start = 800 + 0, 2739 .hsync_end = 800 + 1, 2740 .htotal = 800 + 0 + 1 + 160, 2741 .vdisplay = 480, 2742 .vsync_start = 480 + 0, 2743 .vsync_end = 480 + 48 + 1, 2744 .vtotal = 480 + 48 + 1 + 0, 2745 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2746 }; 2747 2748 static const struct panel_desc mitsubishi_aa070mc01 = { 2749 .modes = &mitsubishi_aa070mc01_mode, 2750 .num_modes = 1, 2751 .bpc = 8, 2752 .size = { 2753 .width = 152, 2754 .height = 91, 2755 }, 2756 2757 .delay = { 2758 .enable = 200, 2759 .unprepare = 200, 2760 .disable = 400, 2761 }, 2762 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2763 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2764 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2765 }; 2766 2767 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2768 .pixelclock = { 29000000, 33000000, 38000000 }, 2769 .hactive = { 800, 800, 800 }, 2770 .hfront_porch = { 180, 210, 240 }, 2771 .hback_porch = { 16, 16, 16 }, 2772 .hsync_len = { 30, 30, 30 }, 2773 .vactive = { 480, 480, 480 }, 2774 .vfront_porch = { 12, 22, 32 }, 2775 .vback_porch = { 10, 10, 10 }, 2776 .vsync_len = { 13, 13, 13 }, 2777 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2778 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2779 DISPLAY_FLAGS_SYNC_POSEDGE, 2780 }; 2781 2782 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2783 .timings = &multi_inno_mi0700s4t_6_timing, 2784 .num_timings = 1, 2785 .bpc = 8, 2786 .size = { 2787 .width = 154, 2788 .height = 86, 2789 }, 2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2792 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2793 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2794 .connector_type = DRM_MODE_CONNECTOR_DPI, 2795 }; 2796 2797 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2798 .pixelclock = { 32000000, 40000000, 50000000 }, 2799 .hactive = { 800, 800, 800 }, 2800 .hfront_porch = { 16, 210, 354 }, 2801 .hback_porch = { 6, 26, 45 }, 2802 .hsync_len = { 1, 20, 40 }, 2803 .vactive = { 600, 600, 600 }, 2804 .vfront_porch = { 1, 12, 77 }, 2805 .vback_porch = { 3, 13, 22 }, 2806 .vsync_len = { 1, 10, 20 }, 2807 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2808 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2809 DISPLAY_FLAGS_SYNC_POSEDGE, 2810 }; 2811 2812 static const struct panel_desc multi_inno_mi0800ft_9 = { 2813 .timings = &multi_inno_mi0800ft_9_timing, 2814 .num_timings = 1, 2815 .bpc = 8, 2816 .size = { 2817 .width = 162, 2818 .height = 122, 2819 }, 2820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2821 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2822 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2823 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2824 .connector_type = DRM_MODE_CONNECTOR_DPI, 2825 }; 2826 2827 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2828 .pixelclock = { 68900000, 70000000, 73400000 }, 2829 .hactive = { 1280, 1280, 1280 }, 2830 .hfront_porch = { 30, 60, 71 }, 2831 .hback_porch = { 30, 60, 71 }, 2832 .hsync_len = { 10, 10, 48 }, 2833 .vactive = { 800, 800, 800 }, 2834 .vfront_porch = { 5, 10, 10 }, 2835 .vback_porch = { 5, 10, 10 }, 2836 .vsync_len = { 5, 6, 13 }, 2837 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2838 DISPLAY_FLAGS_DE_HIGH, 2839 }; 2840 2841 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2842 .timings = &multi_inno_mi1010ait_1cp_timing, 2843 .num_timings = 1, 2844 .bpc = 8, 2845 .size = { 2846 .width = 217, 2847 .height = 136, 2848 }, 2849 .delay = { 2850 .enable = 50, 2851 .disable = 50, 2852 }, 2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2854 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2855 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2856 }; 2857 2858 static const struct display_timing nec_nl12880bc20_05_timing = { 2859 .pixelclock = { 67000000, 71000000, 75000000 }, 2860 .hactive = { 1280, 1280, 1280 }, 2861 .hfront_porch = { 2, 30, 30 }, 2862 .hback_porch = { 6, 100, 100 }, 2863 .hsync_len = { 2, 30, 30 }, 2864 .vactive = { 800, 800, 800 }, 2865 .vfront_porch = { 5, 5, 5 }, 2866 .vback_porch = { 11, 11, 11 }, 2867 .vsync_len = { 7, 7, 7 }, 2868 }; 2869 2870 static const struct panel_desc nec_nl12880bc20_05 = { 2871 .timings = &nec_nl12880bc20_05_timing, 2872 .num_timings = 1, 2873 .bpc = 8, 2874 .size = { 2875 .width = 261, 2876 .height = 163, 2877 }, 2878 .delay = { 2879 .enable = 50, 2880 .disable = 50, 2881 }, 2882 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2883 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2884 }; 2885 2886 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2887 .clock = 10870, 2888 .hdisplay = 480, 2889 .hsync_start = 480 + 2, 2890 .hsync_end = 480 + 2 + 41, 2891 .htotal = 480 + 2 + 41 + 2, 2892 .vdisplay = 272, 2893 .vsync_start = 272 + 2, 2894 .vsync_end = 272 + 2 + 4, 2895 .vtotal = 272 + 2 + 4 + 2, 2896 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2897 }; 2898 2899 static const struct panel_desc nec_nl4827hc19_05b = { 2900 .modes = &nec_nl4827hc19_05b_mode, 2901 .num_modes = 1, 2902 .bpc = 8, 2903 .size = { 2904 .width = 95, 2905 .height = 54, 2906 }, 2907 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2908 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2909 }; 2910 2911 static const struct drm_display_mode netron_dy_e231732_mode = { 2912 .clock = 66000, 2913 .hdisplay = 1024, 2914 .hsync_start = 1024 + 160, 2915 .hsync_end = 1024 + 160 + 70, 2916 .htotal = 1024 + 160 + 70 + 90, 2917 .vdisplay = 600, 2918 .vsync_start = 600 + 127, 2919 .vsync_end = 600 + 127 + 20, 2920 .vtotal = 600 + 127 + 20 + 3, 2921 }; 2922 2923 static const struct panel_desc netron_dy_e231732 = { 2924 .modes = &netron_dy_e231732_mode, 2925 .num_modes = 1, 2926 .size = { 2927 .width = 154, 2928 .height = 87, 2929 }, 2930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2931 }; 2932 2933 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2934 .clock = 9000, 2935 .hdisplay = 480, 2936 .hsync_start = 480 + 2, 2937 .hsync_end = 480 + 2 + 41, 2938 .htotal = 480 + 2 + 41 + 2, 2939 .vdisplay = 272, 2940 .vsync_start = 272 + 2, 2941 .vsync_end = 272 + 2 + 10, 2942 .vtotal = 272 + 2 + 10 + 2, 2943 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2944 }; 2945 2946 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2947 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2948 .num_modes = 1, 2949 .bpc = 8, 2950 .size = { 2951 .width = 95, 2952 .height = 54, 2953 }, 2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2956 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2957 .connector_type = DRM_MODE_CONNECTOR_DPI, 2958 }; 2959 2960 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2961 .pixelclock = { 130000000, 148350000, 163000000 }, 2962 .hactive = { 1920, 1920, 1920 }, 2963 .hfront_porch = { 80, 100, 100 }, 2964 .hback_porch = { 100, 120, 120 }, 2965 .hsync_len = { 50, 60, 60 }, 2966 .vactive = { 1080, 1080, 1080 }, 2967 .vfront_porch = { 12, 30, 30 }, 2968 .vback_porch = { 4, 10, 10 }, 2969 .vsync_len = { 4, 5, 5 }, 2970 }; 2971 2972 static const struct panel_desc nlt_nl192108ac18_02d = { 2973 .timings = &nlt_nl192108ac18_02d_timing, 2974 .num_timings = 1, 2975 .bpc = 8, 2976 .size = { 2977 .width = 344, 2978 .height = 194, 2979 }, 2980 .delay = { 2981 .unprepare = 500, 2982 }, 2983 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2984 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2985 }; 2986 2987 static const struct drm_display_mode nvd_9128_mode = { 2988 .clock = 29500, 2989 .hdisplay = 800, 2990 .hsync_start = 800 + 130, 2991 .hsync_end = 800 + 130 + 98, 2992 .htotal = 800 + 0 + 130 + 98, 2993 .vdisplay = 480, 2994 .vsync_start = 480 + 10, 2995 .vsync_end = 480 + 10 + 50, 2996 .vtotal = 480 + 0 + 10 + 50, 2997 }; 2998 2999 static const struct panel_desc nvd_9128 = { 3000 .modes = &nvd_9128_mode, 3001 .num_modes = 1, 3002 .bpc = 8, 3003 .size = { 3004 .width = 156, 3005 .height = 88, 3006 }, 3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3009 }; 3010 3011 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3012 .pixelclock = { 30000000, 30000000, 40000000 }, 3013 .hactive = { 800, 800, 800 }, 3014 .hfront_porch = { 40, 40, 40 }, 3015 .hback_porch = { 40, 40, 40 }, 3016 .hsync_len = { 1, 48, 48 }, 3017 .vactive = { 480, 480, 480 }, 3018 .vfront_porch = { 13, 13, 13 }, 3019 .vback_porch = { 29, 29, 29 }, 3020 .vsync_len = { 3, 3, 3 }, 3021 .flags = DISPLAY_FLAGS_DE_HIGH, 3022 }; 3023 3024 static const struct panel_desc okaya_rs800480t_7x0gp = { 3025 .timings = &okaya_rs800480t_7x0gp_timing, 3026 .num_timings = 1, 3027 .bpc = 6, 3028 .size = { 3029 .width = 154, 3030 .height = 87, 3031 }, 3032 .delay = { 3033 .prepare = 41, 3034 .enable = 50, 3035 .unprepare = 41, 3036 .disable = 50, 3037 }, 3038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3039 }; 3040 3041 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3042 .clock = 9000, 3043 .hdisplay = 480, 3044 .hsync_start = 480 + 5, 3045 .hsync_end = 480 + 5 + 30, 3046 .htotal = 480 + 5 + 30 + 10, 3047 .vdisplay = 272, 3048 .vsync_start = 272 + 8, 3049 .vsync_end = 272 + 8 + 5, 3050 .vtotal = 272 + 8 + 5 + 3, 3051 }; 3052 3053 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3054 .modes = &olimex_lcd_olinuxino_43ts_mode, 3055 .num_modes = 1, 3056 .size = { 3057 .width = 95, 3058 .height = 54, 3059 }, 3060 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3061 }; 3062 3063 /* 3064 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3065 * pixel clocks, but this is the timing that was being used in the Adafruit 3066 * installation instructions. 3067 */ 3068 static const struct drm_display_mode ontat_yx700wv03_mode = { 3069 .clock = 29500, 3070 .hdisplay = 800, 3071 .hsync_start = 824, 3072 .hsync_end = 896, 3073 .htotal = 992, 3074 .vdisplay = 480, 3075 .vsync_start = 483, 3076 .vsync_end = 493, 3077 .vtotal = 500, 3078 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3079 }; 3080 3081 /* 3082 * Specification at: 3083 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3084 */ 3085 static const struct panel_desc ontat_yx700wv03 = { 3086 .modes = &ontat_yx700wv03_mode, 3087 .num_modes = 1, 3088 .bpc = 8, 3089 .size = { 3090 .width = 154, 3091 .height = 83, 3092 }, 3093 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3094 }; 3095 3096 static const struct drm_display_mode ortustech_com37h3m_mode = { 3097 .clock = 22230, 3098 .hdisplay = 480, 3099 .hsync_start = 480 + 40, 3100 .hsync_end = 480 + 40 + 10, 3101 .htotal = 480 + 40 + 10 + 40, 3102 .vdisplay = 640, 3103 .vsync_start = 640 + 4, 3104 .vsync_end = 640 + 4 + 2, 3105 .vtotal = 640 + 4 + 2 + 4, 3106 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3107 }; 3108 3109 static const struct panel_desc ortustech_com37h3m = { 3110 .modes = &ortustech_com37h3m_mode, 3111 .num_modes = 1, 3112 .bpc = 8, 3113 .size = { 3114 .width = 56, /* 56.16mm */ 3115 .height = 75, /* 74.88mm */ 3116 }, 3117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3118 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3119 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3120 }; 3121 3122 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3123 .clock = 25000, 3124 .hdisplay = 480, 3125 .hsync_start = 480 + 10, 3126 .hsync_end = 480 + 10 + 10, 3127 .htotal = 480 + 10 + 10 + 15, 3128 .vdisplay = 800, 3129 .vsync_start = 800 + 3, 3130 .vsync_end = 800 + 3 + 3, 3131 .vtotal = 800 + 3 + 3 + 3, 3132 }; 3133 3134 static const struct panel_desc ortustech_com43h4m85ulc = { 3135 .modes = &ortustech_com43h4m85ulc_mode, 3136 .num_modes = 1, 3137 .bpc = 6, 3138 .size = { 3139 .width = 56, 3140 .height = 93, 3141 }, 3142 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3143 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3144 .connector_type = DRM_MODE_CONNECTOR_DPI, 3145 }; 3146 3147 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3148 .clock = 33000, 3149 .hdisplay = 800, 3150 .hsync_start = 800 + 210, 3151 .hsync_end = 800 + 210 + 30, 3152 .htotal = 800 + 210 + 30 + 16, 3153 .vdisplay = 480, 3154 .vsync_start = 480 + 22, 3155 .vsync_end = 480 + 22 + 13, 3156 .vtotal = 480 + 22 + 13 + 10, 3157 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3158 }; 3159 3160 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3161 .modes = &osddisplays_osd070t1718_19ts_mode, 3162 .num_modes = 1, 3163 .bpc = 8, 3164 .size = { 3165 .width = 152, 3166 .height = 91, 3167 }, 3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3169 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3170 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3171 .connector_type = DRM_MODE_CONNECTOR_DPI, 3172 }; 3173 3174 static const struct drm_display_mode pda_91_00156_a0_mode = { 3175 .clock = 33300, 3176 .hdisplay = 800, 3177 .hsync_start = 800 + 1, 3178 .hsync_end = 800 + 1 + 64, 3179 .htotal = 800 + 1 + 64 + 64, 3180 .vdisplay = 480, 3181 .vsync_start = 480 + 1, 3182 .vsync_end = 480 + 1 + 23, 3183 .vtotal = 480 + 1 + 23 + 22, 3184 }; 3185 3186 static const struct panel_desc pda_91_00156_a0 = { 3187 .modes = &pda_91_00156_a0_mode, 3188 .num_modes = 1, 3189 .size = { 3190 .width = 152, 3191 .height = 91, 3192 }, 3193 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3194 }; 3195 3196 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3197 .clock = 24750, 3198 .hdisplay = 800, 3199 .hsync_start = 800 + 54, 3200 .hsync_end = 800 + 54 + 2, 3201 .htotal = 800 + 54 + 2 + 44, 3202 .vdisplay = 480, 3203 .vsync_start = 480 + 49, 3204 .vsync_end = 480 + 49 + 2, 3205 .vtotal = 480 + 49 + 2 + 22, 3206 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3207 }; 3208 3209 static const struct panel_desc powertip_ph800480t013_idf02 = { 3210 .modes = &powertip_ph800480t013_idf02_mode, 3211 .num_modes = 1, 3212 .size = { 3213 .width = 152, 3214 .height = 91, 3215 }, 3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3217 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3218 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3220 .connector_type = DRM_MODE_CONNECTOR_DPI, 3221 }; 3222 3223 static const struct drm_display_mode qd43003c0_40_mode = { 3224 .clock = 9000, 3225 .hdisplay = 480, 3226 .hsync_start = 480 + 8, 3227 .hsync_end = 480 + 8 + 4, 3228 .htotal = 480 + 8 + 4 + 39, 3229 .vdisplay = 272, 3230 .vsync_start = 272 + 4, 3231 .vsync_end = 272 + 4 + 10, 3232 .vtotal = 272 + 4 + 10 + 2, 3233 }; 3234 3235 static const struct panel_desc qd43003c0_40 = { 3236 .modes = &qd43003c0_40_mode, 3237 .num_modes = 1, 3238 .bpc = 8, 3239 .size = { 3240 .width = 95, 3241 .height = 53, 3242 }, 3243 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3244 }; 3245 3246 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3247 { /* 60 Hz */ 3248 .clock = 10800, 3249 .hdisplay = 480, 3250 .hsync_start = 480 + 77, 3251 .hsync_end = 480 + 77 + 41, 3252 .htotal = 480 + 77 + 41 + 2, 3253 .vdisplay = 272, 3254 .vsync_start = 272 + 16, 3255 .vsync_end = 272 + 16 + 10, 3256 .vtotal = 272 + 16 + 10 + 2, 3257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3258 }, 3259 { /* 50 Hz */ 3260 .clock = 10800, 3261 .hdisplay = 480, 3262 .hsync_start = 480 + 17, 3263 .hsync_end = 480 + 17 + 41, 3264 .htotal = 480 + 17 + 41 + 2, 3265 .vdisplay = 272, 3266 .vsync_start = 272 + 116, 3267 .vsync_end = 272 + 116 + 10, 3268 .vtotal = 272 + 116 + 10 + 2, 3269 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3270 }, 3271 }; 3272 3273 static const struct panel_desc qishenglong_gopher2b_lcd = { 3274 .modes = qishenglong_gopher2b_lcd_modes, 3275 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3276 .bpc = 8, 3277 .size = { 3278 .width = 95, 3279 .height = 54, 3280 }, 3281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3283 .connector_type = DRM_MODE_CONNECTOR_DPI, 3284 }; 3285 3286 static const struct display_timing rocktech_rk043fn48h_timing = { 3287 .pixelclock = { 6000000, 9000000, 12000000 }, 3288 .hactive = { 480, 480, 480 }, 3289 .hback_porch = { 8, 43, 43 }, 3290 .hfront_porch = { 2, 8, 8 }, 3291 .hsync_len = { 1, 1, 1 }, 3292 .vactive = { 272, 272, 272 }, 3293 .vback_porch = { 2, 12, 12 }, 3294 .vfront_porch = { 1, 4, 4 }, 3295 .vsync_len = { 1, 10, 10 }, 3296 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3297 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3298 }; 3299 3300 static const struct panel_desc rocktech_rk043fn48h = { 3301 .timings = &rocktech_rk043fn48h_timing, 3302 .num_timings = 1, 3303 .bpc = 8, 3304 .size = { 3305 .width = 95, 3306 .height = 54, 3307 }, 3308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3309 .connector_type = DRM_MODE_CONNECTOR_DPI, 3310 }; 3311 3312 static const struct display_timing rocktech_rk070er9427_timing = { 3313 .pixelclock = { 26400000, 33300000, 46800000 }, 3314 .hactive = { 800, 800, 800 }, 3315 .hfront_porch = { 16, 210, 354 }, 3316 .hback_porch = { 46, 46, 46 }, 3317 .hsync_len = { 1, 1, 1 }, 3318 .vactive = { 480, 480, 480 }, 3319 .vfront_porch = { 7, 22, 147 }, 3320 .vback_porch = { 23, 23, 23 }, 3321 .vsync_len = { 1, 1, 1 }, 3322 .flags = DISPLAY_FLAGS_DE_HIGH, 3323 }; 3324 3325 static const struct panel_desc rocktech_rk070er9427 = { 3326 .timings = &rocktech_rk070er9427_timing, 3327 .num_timings = 1, 3328 .bpc = 6, 3329 .size = { 3330 .width = 154, 3331 .height = 86, 3332 }, 3333 .delay = { 3334 .prepare = 41, 3335 .enable = 50, 3336 .unprepare = 41, 3337 .disable = 50, 3338 }, 3339 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3340 }; 3341 3342 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3343 .clock = 71100, 3344 .hdisplay = 1280, 3345 .hsync_start = 1280 + 48, 3346 .hsync_end = 1280 + 48 + 32, 3347 .htotal = 1280 + 48 + 32 + 80, 3348 .vdisplay = 800, 3349 .vsync_start = 800 + 2, 3350 .vsync_end = 800 + 2 + 5, 3351 .vtotal = 800 + 2 + 5 + 16, 3352 }; 3353 3354 static const struct panel_desc rocktech_rk101ii01d_ct = { 3355 .modes = &rocktech_rk101ii01d_ct_mode, 3356 .bpc = 8, 3357 .num_modes = 1, 3358 .size = { 3359 .width = 217, 3360 .height = 136, 3361 }, 3362 .delay = { 3363 .prepare = 50, 3364 .disable = 50, 3365 }, 3366 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3368 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3369 }; 3370 3371 static const struct display_timing samsung_ltl101al01_timing = { 3372 .pixelclock = { 66663000, 66663000, 66663000 }, 3373 .hactive = { 1280, 1280, 1280 }, 3374 .hfront_porch = { 18, 18, 18 }, 3375 .hback_porch = { 36, 36, 36 }, 3376 .hsync_len = { 16, 16, 16 }, 3377 .vactive = { 800, 800, 800 }, 3378 .vfront_porch = { 4, 4, 4 }, 3379 .vback_porch = { 16, 16, 16 }, 3380 .vsync_len = { 3, 3, 3 }, 3381 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3382 }; 3383 3384 static const struct panel_desc samsung_ltl101al01 = { 3385 .timings = &samsung_ltl101al01_timing, 3386 .num_timings = 1, 3387 .bpc = 8, 3388 .size = { 3389 .width = 217, 3390 .height = 135, 3391 }, 3392 .delay = { 3393 .prepare = 40, 3394 .enable = 300, 3395 .disable = 200, 3396 .unprepare = 600, 3397 }, 3398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3399 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3400 }; 3401 3402 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3403 .clock = 54030, 3404 .hdisplay = 1024, 3405 .hsync_start = 1024 + 24, 3406 .hsync_end = 1024 + 24 + 136, 3407 .htotal = 1024 + 24 + 136 + 160, 3408 .vdisplay = 600, 3409 .vsync_start = 600 + 3, 3410 .vsync_end = 600 + 3 + 6, 3411 .vtotal = 600 + 3 + 6 + 61, 3412 }; 3413 3414 static const struct panel_desc samsung_ltn101nt05 = { 3415 .modes = &samsung_ltn101nt05_mode, 3416 .num_modes = 1, 3417 .bpc = 6, 3418 .size = { 3419 .width = 223, 3420 .height = 125, 3421 }, 3422 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3425 }; 3426 3427 static const struct display_timing satoz_sat050at40h12r2_timing = { 3428 .pixelclock = {33300000, 33300000, 50000000}, 3429 .hactive = {800, 800, 800}, 3430 .hfront_porch = {16, 210, 354}, 3431 .hback_porch = {46, 46, 46}, 3432 .hsync_len = {1, 1, 40}, 3433 .vactive = {480, 480, 480}, 3434 .vfront_porch = {7, 22, 147}, 3435 .vback_porch = {23, 23, 23}, 3436 .vsync_len = {1, 1, 20}, 3437 }; 3438 3439 static const struct panel_desc satoz_sat050at40h12r2 = { 3440 .timings = &satoz_sat050at40h12r2_timing, 3441 .num_timings = 1, 3442 .bpc = 8, 3443 .size = { 3444 .width = 108, 3445 .height = 65, 3446 }, 3447 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3448 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3449 }; 3450 3451 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3452 .clock = 33260, 3453 .hdisplay = 800, 3454 .hsync_start = 800 + 64, 3455 .hsync_end = 800 + 64 + 128, 3456 .htotal = 800 + 64 + 128 + 64, 3457 .vdisplay = 480, 3458 .vsync_start = 480 + 8, 3459 .vsync_end = 480 + 8 + 2, 3460 .vtotal = 480 + 8 + 2 + 35, 3461 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3462 }; 3463 3464 static const struct panel_desc sharp_lq070y3dg3b = { 3465 .modes = &sharp_lq070y3dg3b_mode, 3466 .num_modes = 1, 3467 .bpc = 8, 3468 .size = { 3469 .width = 152, /* 152.4mm */ 3470 .height = 91, /* 91.4mm */ 3471 }, 3472 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3473 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3474 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3475 }; 3476 3477 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3478 .clock = 5500, 3479 .hdisplay = 240, 3480 .hsync_start = 240 + 16, 3481 .hsync_end = 240 + 16 + 7, 3482 .htotal = 240 + 16 + 7 + 5, 3483 .vdisplay = 320, 3484 .vsync_start = 320 + 9, 3485 .vsync_end = 320 + 9 + 1, 3486 .vtotal = 320 + 9 + 1 + 7, 3487 }; 3488 3489 static const struct panel_desc sharp_lq035q7db03 = { 3490 .modes = &sharp_lq035q7db03_mode, 3491 .num_modes = 1, 3492 .bpc = 6, 3493 .size = { 3494 .width = 54, 3495 .height = 72, 3496 }, 3497 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3498 }; 3499 3500 static const struct display_timing sharp_lq101k1ly04_timing = { 3501 .pixelclock = { 60000000, 65000000, 80000000 }, 3502 .hactive = { 1280, 1280, 1280 }, 3503 .hfront_porch = { 20, 20, 20 }, 3504 .hback_porch = { 20, 20, 20 }, 3505 .hsync_len = { 10, 10, 10 }, 3506 .vactive = { 800, 800, 800 }, 3507 .vfront_porch = { 4, 4, 4 }, 3508 .vback_porch = { 4, 4, 4 }, 3509 .vsync_len = { 4, 4, 4 }, 3510 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3511 }; 3512 3513 static const struct panel_desc sharp_lq101k1ly04 = { 3514 .timings = &sharp_lq101k1ly04_timing, 3515 .num_timings = 1, 3516 .bpc = 8, 3517 .size = { 3518 .width = 217, 3519 .height = 136, 3520 }, 3521 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3522 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3523 }; 3524 3525 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3526 { /* 50 Hz */ 3527 .clock = 3000, 3528 .hdisplay = 240, 3529 .hsync_start = 240 + 58, 3530 .hsync_end = 240 + 58 + 1, 3531 .htotal = 240 + 58 + 1 + 1, 3532 .vdisplay = 160, 3533 .vsync_start = 160 + 24, 3534 .vsync_end = 160 + 24 + 10, 3535 .vtotal = 160 + 24 + 10 + 6, 3536 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3537 }, 3538 { /* 60 Hz */ 3539 .clock = 3000, 3540 .hdisplay = 240, 3541 .hsync_start = 240 + 8, 3542 .hsync_end = 240 + 8 + 1, 3543 .htotal = 240 + 8 + 1 + 1, 3544 .vdisplay = 160, 3545 .vsync_start = 160 + 24, 3546 .vsync_end = 160 + 24 + 10, 3547 .vtotal = 160 + 24 + 10 + 6, 3548 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3549 }, 3550 }; 3551 3552 static const struct panel_desc sharp_ls020b1dd01d = { 3553 .modes = sharp_ls020b1dd01d_modes, 3554 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3555 .bpc = 6, 3556 .size = { 3557 .width = 42, 3558 .height = 28, 3559 }, 3560 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3561 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3562 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3563 | DRM_BUS_FLAG_SHARP_SIGNALS, 3564 }; 3565 3566 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3567 .clock = 33300, 3568 .hdisplay = 800, 3569 .hsync_start = 800 + 1, 3570 .hsync_end = 800 + 1 + 64, 3571 .htotal = 800 + 1 + 64 + 64, 3572 .vdisplay = 480, 3573 .vsync_start = 480 + 1, 3574 .vsync_end = 480 + 1 + 23, 3575 .vtotal = 480 + 1 + 23 + 22, 3576 }; 3577 3578 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3579 .modes = &shelly_sca07010_bfn_lnn_mode, 3580 .num_modes = 1, 3581 .size = { 3582 .width = 152, 3583 .height = 91, 3584 }, 3585 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3586 }; 3587 3588 static const struct drm_display_mode starry_kr070pe2t_mode = { 3589 .clock = 33000, 3590 .hdisplay = 800, 3591 .hsync_start = 800 + 209, 3592 .hsync_end = 800 + 209 + 1, 3593 .htotal = 800 + 209 + 1 + 45, 3594 .vdisplay = 480, 3595 .vsync_start = 480 + 22, 3596 .vsync_end = 480 + 22 + 1, 3597 .vtotal = 480 + 22 + 1 + 22, 3598 }; 3599 3600 static const struct panel_desc starry_kr070pe2t = { 3601 .modes = &starry_kr070pe2t_mode, 3602 .num_modes = 1, 3603 .bpc = 8, 3604 .size = { 3605 .width = 152, 3606 .height = 86, 3607 }, 3608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3609 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3610 .connector_type = DRM_MODE_CONNECTOR_DPI, 3611 }; 3612 3613 static const struct display_timing startek_kd070wvfpa_mode = { 3614 .pixelclock = { 25200000, 27200000, 30500000 }, 3615 .hactive = { 800, 800, 800 }, 3616 .hfront_porch = { 19, 44, 115 }, 3617 .hback_porch = { 5, 16, 101 }, 3618 .hsync_len = { 1, 2, 100 }, 3619 .vactive = { 480, 480, 480 }, 3620 .vfront_porch = { 5, 43, 67 }, 3621 .vback_porch = { 5, 5, 67 }, 3622 .vsync_len = { 1, 2, 66 }, 3623 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3624 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3625 DISPLAY_FLAGS_SYNC_POSEDGE, 3626 }; 3627 3628 static const struct panel_desc startek_kd070wvfpa = { 3629 .timings = &startek_kd070wvfpa_mode, 3630 .num_timings = 1, 3631 .bpc = 8, 3632 .size = { 3633 .width = 152, 3634 .height = 91, 3635 }, 3636 .delay = { 3637 .prepare = 20, 3638 .enable = 200, 3639 .disable = 200, 3640 }, 3641 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3642 .connector_type = DRM_MODE_CONNECTOR_DPI, 3643 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3644 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3645 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3646 }; 3647 3648 static const struct display_timing tsd_tst043015cmhx_timing = { 3649 .pixelclock = { 5000000, 9000000, 12000000 }, 3650 .hactive = { 480, 480, 480 }, 3651 .hfront_porch = { 4, 5, 65 }, 3652 .hback_porch = { 36, 40, 255 }, 3653 .hsync_len = { 1, 1, 1 }, 3654 .vactive = { 272, 272, 272 }, 3655 .vfront_porch = { 2, 8, 97 }, 3656 .vback_porch = { 3, 8, 31 }, 3657 .vsync_len = { 1, 1, 1 }, 3658 3659 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3660 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3661 }; 3662 3663 static const struct panel_desc tsd_tst043015cmhx = { 3664 .timings = &tsd_tst043015cmhx_timing, 3665 .num_timings = 1, 3666 .bpc = 8, 3667 .size = { 3668 .width = 105, 3669 .height = 67, 3670 }, 3671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3672 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3673 }; 3674 3675 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3676 .clock = 30000, 3677 .hdisplay = 800, 3678 .hsync_start = 800 + 39, 3679 .hsync_end = 800 + 39 + 47, 3680 .htotal = 800 + 39 + 47 + 39, 3681 .vdisplay = 480, 3682 .vsync_start = 480 + 13, 3683 .vsync_end = 480 + 13 + 2, 3684 .vtotal = 480 + 13 + 2 + 29, 3685 }; 3686 3687 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3688 .modes = &tfc_s9700rtwv43tr_01b_mode, 3689 .num_modes = 1, 3690 .bpc = 8, 3691 .size = { 3692 .width = 155, 3693 .height = 90, 3694 }, 3695 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3696 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3697 }; 3698 3699 static const struct display_timing tianma_tm070jdhg30_timing = { 3700 .pixelclock = { 62600000, 68200000, 78100000 }, 3701 .hactive = { 1280, 1280, 1280 }, 3702 .hfront_porch = { 15, 64, 159 }, 3703 .hback_porch = { 5, 5, 5 }, 3704 .hsync_len = { 1, 1, 256 }, 3705 .vactive = { 800, 800, 800 }, 3706 .vfront_porch = { 3, 40, 99 }, 3707 .vback_porch = { 2, 2, 2 }, 3708 .vsync_len = { 1, 1, 128 }, 3709 .flags = DISPLAY_FLAGS_DE_HIGH, 3710 }; 3711 3712 static const struct panel_desc tianma_tm070jdhg30 = { 3713 .timings = &tianma_tm070jdhg30_timing, 3714 .num_timings = 1, 3715 .bpc = 8, 3716 .size = { 3717 .width = 151, 3718 .height = 95, 3719 }, 3720 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3721 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3722 }; 3723 3724 static const struct panel_desc tianma_tm070jvhg33 = { 3725 .timings = &tianma_tm070jdhg30_timing, 3726 .num_timings = 1, 3727 .bpc = 8, 3728 .size = { 3729 .width = 150, 3730 .height = 94, 3731 }, 3732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3733 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3734 }; 3735 3736 static const struct display_timing tianma_tm070rvhg71_timing = { 3737 .pixelclock = { 27700000, 29200000, 39600000 }, 3738 .hactive = { 800, 800, 800 }, 3739 .hfront_porch = { 12, 40, 212 }, 3740 .hback_porch = { 88, 88, 88 }, 3741 .hsync_len = { 1, 1, 40 }, 3742 .vactive = { 480, 480, 480 }, 3743 .vfront_porch = { 1, 13, 88 }, 3744 .vback_porch = { 32, 32, 32 }, 3745 .vsync_len = { 1, 1, 3 }, 3746 .flags = DISPLAY_FLAGS_DE_HIGH, 3747 }; 3748 3749 static const struct panel_desc tianma_tm070rvhg71 = { 3750 .timings = &tianma_tm070rvhg71_timing, 3751 .num_timings = 1, 3752 .bpc = 8, 3753 .size = { 3754 .width = 154, 3755 .height = 86, 3756 }, 3757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3758 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3759 }; 3760 3761 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3762 { 3763 .clock = 10000, 3764 .hdisplay = 320, 3765 .hsync_start = 320 + 50, 3766 .hsync_end = 320 + 50 + 6, 3767 .htotal = 320 + 50 + 6 + 38, 3768 .vdisplay = 240, 3769 .vsync_start = 240 + 3, 3770 .vsync_end = 240 + 3 + 1, 3771 .vtotal = 240 + 3 + 1 + 17, 3772 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3773 }, 3774 }; 3775 3776 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3777 .modes = ti_nspire_cx_lcd_mode, 3778 .num_modes = 1, 3779 .bpc = 8, 3780 .size = { 3781 .width = 65, 3782 .height = 49, 3783 }, 3784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3785 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3786 }; 3787 3788 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3789 { 3790 .clock = 10000, 3791 .hdisplay = 320, 3792 .hsync_start = 320 + 6, 3793 .hsync_end = 320 + 6 + 6, 3794 .htotal = 320 + 6 + 6 + 6, 3795 .vdisplay = 240, 3796 .vsync_start = 240 + 0, 3797 .vsync_end = 240 + 0 + 1, 3798 .vtotal = 240 + 0 + 1 + 0, 3799 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3800 }, 3801 }; 3802 3803 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3804 .modes = ti_nspire_classic_lcd_mode, 3805 .num_modes = 1, 3806 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3807 .bpc = 8, 3808 .size = { 3809 .width = 71, 3810 .height = 53, 3811 }, 3812 /* This is the grayscale bus format */ 3813 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3814 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3815 }; 3816 3817 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3818 .clock = 79500, 3819 .hdisplay = 1280, 3820 .hsync_start = 1280 + 192, 3821 .hsync_end = 1280 + 192 + 128, 3822 .htotal = 1280 + 192 + 128 + 64, 3823 .vdisplay = 768, 3824 .vsync_start = 768 + 20, 3825 .vsync_end = 768 + 20 + 7, 3826 .vtotal = 768 + 20 + 7 + 3, 3827 }; 3828 3829 static const struct panel_desc toshiba_lt089ac29000 = { 3830 .modes = &toshiba_lt089ac29000_mode, 3831 .num_modes = 1, 3832 .size = { 3833 .width = 194, 3834 .height = 116, 3835 }, 3836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3838 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3839 }; 3840 3841 static const struct drm_display_mode tpk_f07a_0102_mode = { 3842 .clock = 33260, 3843 .hdisplay = 800, 3844 .hsync_start = 800 + 40, 3845 .hsync_end = 800 + 40 + 128, 3846 .htotal = 800 + 40 + 128 + 88, 3847 .vdisplay = 480, 3848 .vsync_start = 480 + 10, 3849 .vsync_end = 480 + 10 + 2, 3850 .vtotal = 480 + 10 + 2 + 33, 3851 }; 3852 3853 static const struct panel_desc tpk_f07a_0102 = { 3854 .modes = &tpk_f07a_0102_mode, 3855 .num_modes = 1, 3856 .size = { 3857 .width = 152, 3858 .height = 91, 3859 }, 3860 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3861 }; 3862 3863 static const struct drm_display_mode tpk_f10a_0102_mode = { 3864 .clock = 45000, 3865 .hdisplay = 1024, 3866 .hsync_start = 1024 + 176, 3867 .hsync_end = 1024 + 176 + 5, 3868 .htotal = 1024 + 176 + 5 + 88, 3869 .vdisplay = 600, 3870 .vsync_start = 600 + 20, 3871 .vsync_end = 600 + 20 + 5, 3872 .vtotal = 600 + 20 + 5 + 25, 3873 }; 3874 3875 static const struct panel_desc tpk_f10a_0102 = { 3876 .modes = &tpk_f10a_0102_mode, 3877 .num_modes = 1, 3878 .size = { 3879 .width = 223, 3880 .height = 125, 3881 }, 3882 }; 3883 3884 static const struct display_timing urt_umsh_8596md_timing = { 3885 .pixelclock = { 33260000, 33260000, 33260000 }, 3886 .hactive = { 800, 800, 800 }, 3887 .hfront_porch = { 41, 41, 41 }, 3888 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3889 .hsync_len = { 71, 128, 128 }, 3890 .vactive = { 480, 480, 480 }, 3891 .vfront_porch = { 10, 10, 10 }, 3892 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3893 .vsync_len = { 2, 2, 2 }, 3894 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3895 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3896 }; 3897 3898 static const struct panel_desc urt_umsh_8596md_lvds = { 3899 .timings = &urt_umsh_8596md_timing, 3900 .num_timings = 1, 3901 .bpc = 6, 3902 .size = { 3903 .width = 152, 3904 .height = 91, 3905 }, 3906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3908 }; 3909 3910 static const struct panel_desc urt_umsh_8596md_parallel = { 3911 .timings = &urt_umsh_8596md_timing, 3912 .num_timings = 1, 3913 .bpc = 6, 3914 .size = { 3915 .width = 152, 3916 .height = 91, 3917 }, 3918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3919 }; 3920 3921 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3922 .clock = 60000, 3923 .hdisplay = 1024, 3924 .hsync_start = 1024 + 160, 3925 .hsync_end = 1024 + 160 + 100, 3926 .htotal = 1024 + 160 + 100 + 60, 3927 .vdisplay = 600, 3928 .vsync_start = 600 + 12, 3929 .vsync_end = 600 + 12 + 10, 3930 .vtotal = 600 + 12 + 10 + 13, 3931 }; 3932 3933 static const struct panel_desc vivax_tpc9150_panel = { 3934 .modes = &vivax_tpc9150_panel_mode, 3935 .num_modes = 1, 3936 .bpc = 6, 3937 .size = { 3938 .width = 200, 3939 .height = 115, 3940 }, 3941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3942 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3943 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3944 }; 3945 3946 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3947 .clock = 33333, 3948 .hdisplay = 800, 3949 .hsync_start = 800 + 210, 3950 .hsync_end = 800 + 210 + 20, 3951 .htotal = 800 + 210 + 20 + 46, 3952 .vdisplay = 480, 3953 .vsync_start = 480 + 22, 3954 .vsync_end = 480 + 22 + 10, 3955 .vtotal = 480 + 22 + 10 + 23, 3956 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3957 }; 3958 3959 static const struct panel_desc vl050_8048nt_c01 = { 3960 .modes = &vl050_8048nt_c01_mode, 3961 .num_modes = 1, 3962 .bpc = 8, 3963 .size = { 3964 .width = 120, 3965 .height = 76, 3966 }, 3967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3969 }; 3970 3971 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3972 .clock = 6410, 3973 .hdisplay = 320, 3974 .hsync_start = 320 + 20, 3975 .hsync_end = 320 + 20 + 30, 3976 .htotal = 320 + 20 + 30 + 38, 3977 .vdisplay = 240, 3978 .vsync_start = 240 + 4, 3979 .vsync_end = 240 + 4 + 3, 3980 .vtotal = 240 + 4 + 3 + 15, 3981 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3982 }; 3983 3984 static const struct panel_desc winstar_wf35ltiacd = { 3985 .modes = &winstar_wf35ltiacd_mode, 3986 .num_modes = 1, 3987 .bpc = 8, 3988 .size = { 3989 .width = 70, 3990 .height = 53, 3991 }, 3992 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3993 }; 3994 3995 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3996 .clock = 51200, 3997 .hdisplay = 1024, 3998 .hsync_start = 1024 + 100, 3999 .hsync_end = 1024 + 100 + 100, 4000 .htotal = 1024 + 100 + 100 + 120, 4001 .vdisplay = 600, 4002 .vsync_start = 600 + 10, 4003 .vsync_end = 600 + 10 + 10, 4004 .vtotal = 600 + 10 + 10 + 15, 4005 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4006 }; 4007 4008 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4009 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4010 .num_modes = 1, 4011 .bpc = 8, 4012 .size = { 4013 .width = 154, 4014 .height = 90, 4015 }, 4016 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4017 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4018 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4019 }; 4020 4021 static const struct drm_display_mode arm_rtsm_mode[] = { 4022 { 4023 .clock = 65000, 4024 .hdisplay = 1024, 4025 .hsync_start = 1024 + 24, 4026 .hsync_end = 1024 + 24 + 136, 4027 .htotal = 1024 + 24 + 136 + 160, 4028 .vdisplay = 768, 4029 .vsync_start = 768 + 3, 4030 .vsync_end = 768 + 3 + 6, 4031 .vtotal = 768 + 3 + 6 + 29, 4032 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4033 }, 4034 }; 4035 4036 static const struct panel_desc arm_rtsm = { 4037 .modes = arm_rtsm_mode, 4038 .num_modes = 1, 4039 .bpc = 8, 4040 .size = { 4041 .width = 400, 4042 .height = 300, 4043 }, 4044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4045 }; 4046 4047 static const struct of_device_id platform_of_match[] = { 4048 { 4049 .compatible = "ampire,am-1280800n3tzqw-t00h", 4050 .data = &ire_am_1280800n3tzqw_t00h, 4051 }, { 4052 .compatible = "ampire,am-480272h3tmqw-t01h", 4053 .data = &ire_am_480272h3tmqw_t01h, 4054 }, { 4055 .compatible = "ampire,am-800480l1tmqw-t00h", 4056 .data = &ire_am_800480l1tmqw_t00h, 4057 }, { 4058 .compatible = "ampire,am800480r3tmqwa1h", 4059 .data = &ire_am800480r3tmqwa1h, 4060 }, { 4061 .compatible = "ampire,am800600p5tmqw-tb8h", 4062 .data = &ire_am800600p5tmqwtb8h, 4063 }, { 4064 .compatible = "arm,rtsm-display", 4065 .data = &arm_rtsm, 4066 }, { 4067 .compatible = "armadeus,st0700-adapt", 4068 .data = &armadeus_st0700_adapt, 4069 }, { 4070 .compatible = "auo,b101aw03", 4071 .data = &auo_b101aw03, 4072 }, { 4073 .compatible = "auo,b101xtn01", 4074 .data = &auo_b101xtn01, 4075 }, { 4076 .compatible = "auo,g070vvn01", 4077 .data = &auo_g070vvn01, 4078 }, { 4079 .compatible = "auo,g101evn010", 4080 .data = &auo_g101evn010, 4081 }, { 4082 .compatible = "auo,g104sn02", 4083 .data = &auo_g104sn02, 4084 }, { 4085 .compatible = "auo,g121ean01", 4086 .data = &auo_g121ean01, 4087 }, { 4088 .compatible = "auo,g133han01", 4089 .data = &auo_g133han01, 4090 }, { 4091 .compatible = "auo,g156xtn01", 4092 .data = &auo_g156xtn01, 4093 }, { 4094 .compatible = "auo,g185han01", 4095 .data = &auo_g185han01, 4096 }, { 4097 .compatible = "auo,g190ean01", 4098 .data = &auo_g190ean01, 4099 }, { 4100 .compatible = "auo,p320hvn03", 4101 .data = &auo_p320hvn03, 4102 }, { 4103 .compatible = "auo,t215hvn01", 4104 .data = &auo_t215hvn01, 4105 }, { 4106 .compatible = "avic,tm070ddh03", 4107 .data = &avic_tm070ddh03, 4108 }, { 4109 .compatible = "bananapi,s070wv20-ct16", 4110 .data = &bananapi_s070wv20_ct16, 4111 }, { 4112 .compatible = "boe,ev121wxm-n10-1850", 4113 .data = &boe_ev121wxm_n10_1850, 4114 }, { 4115 .compatible = "boe,hv070wsa-100", 4116 .data = &boe_hv070wsa 4117 }, { 4118 .compatible = "cdtech,s043wq26h-ct7", 4119 .data = &cdtech_s043wq26h_ct7, 4120 }, { 4121 .compatible = "cdtech,s070pws19hp-fc21", 4122 .data = &cdtech_s070pws19hp_fc21, 4123 }, { 4124 .compatible = "cdtech,s070swv29hg-dc44", 4125 .data = &cdtech_s070swv29hg_dc44, 4126 }, { 4127 .compatible = "cdtech,s070wv95-ct16", 4128 .data = &cdtech_s070wv95_ct16, 4129 }, { 4130 .compatible = "chefree,ch101olhlwh-002", 4131 .data = &chefree_ch101olhlwh_002, 4132 }, { 4133 .compatible = "chunghwa,claa070wp03xg", 4134 .data = &chunghwa_claa070wp03xg, 4135 }, { 4136 .compatible = "chunghwa,claa101wa01a", 4137 .data = &chunghwa_claa101wa01a 4138 }, { 4139 .compatible = "chunghwa,claa101wb01", 4140 .data = &chunghwa_claa101wb01 4141 }, { 4142 .compatible = "dataimage,fg040346dsswbg04", 4143 .data = &dataimage_fg040346dsswbg04, 4144 }, { 4145 .compatible = "dataimage,fg1001l0dsswmg01", 4146 .data = &dataimage_fg1001l0dsswmg01, 4147 }, { 4148 .compatible = "dataimage,scf0700c48ggu18", 4149 .data = &dataimage_scf0700c48ggu18, 4150 }, { 4151 .compatible = "dlc,dlc0700yzg-1", 4152 .data = &dlc_dlc0700yzg_1, 4153 }, { 4154 .compatible = "dlc,dlc1010gig", 4155 .data = &dlc_dlc1010gig, 4156 }, { 4157 .compatible = "edt,et035012dm6", 4158 .data = &edt_et035012dm6, 4159 }, { 4160 .compatible = "edt,etm0350g0dh6", 4161 .data = &edt_etm0350g0dh6, 4162 }, { 4163 .compatible = "edt,etm043080dh6gp", 4164 .data = &edt_etm043080dh6gp, 4165 }, { 4166 .compatible = "edt,etm0430g0dh6", 4167 .data = &edt_etm0430g0dh6, 4168 }, { 4169 .compatible = "edt,et057090dhu", 4170 .data = &edt_et057090dhu, 4171 }, { 4172 .compatible = "edt,et070080dh6", 4173 .data = &edt_etm0700g0dh6, 4174 }, { 4175 .compatible = "edt,etm0700g0dh6", 4176 .data = &edt_etm0700g0dh6, 4177 }, { 4178 .compatible = "edt,etm0700g0bdh6", 4179 .data = &edt_etm0700g0bdh6, 4180 }, { 4181 .compatible = "edt,etm0700g0edh6", 4182 .data = &edt_etm0700g0bdh6, 4183 }, { 4184 .compatible = "edt,etml0700y5dha", 4185 .data = &edt_etml0700y5dha, 4186 }, { 4187 .compatible = "edt,etmv570g2dhu", 4188 .data = &edt_etmv570g2dhu, 4189 }, { 4190 .compatible = "eink,vb3300-kca", 4191 .data = &eink_vb3300_kca, 4192 }, { 4193 .compatible = "evervision,vgg804821", 4194 .data = &evervision_vgg804821, 4195 }, { 4196 .compatible = "foxlink,fl500wvr00-a0t", 4197 .data = &foxlink_fl500wvr00_a0t, 4198 }, { 4199 .compatible = "frida,frd350h54004", 4200 .data = &frida_frd350h54004, 4201 }, { 4202 .compatible = "friendlyarm,hd702e", 4203 .data = &friendlyarm_hd702e, 4204 }, { 4205 .compatible = "giantplus,gpg482739qs5", 4206 .data = &giantplus_gpg482739qs5 4207 }, { 4208 .compatible = "giantplus,gpm940b0", 4209 .data = &giantplus_gpm940b0, 4210 }, { 4211 .compatible = "hannstar,hsd070pww1", 4212 .data = &hannstar_hsd070pww1, 4213 }, { 4214 .compatible = "hannstar,hsd100pxn1", 4215 .data = &hannstar_hsd100pxn1, 4216 }, { 4217 .compatible = "hannstar,hsd101pww2", 4218 .data = &hannstar_hsd101pww2, 4219 }, { 4220 .compatible = "hit,tx23d38vm0caa", 4221 .data = &hitachi_tx23d38vm0caa 4222 }, { 4223 .compatible = "innolux,at043tn24", 4224 .data = &innolux_at043tn24, 4225 }, { 4226 .compatible = "innolux,at070tn92", 4227 .data = &innolux_at070tn92, 4228 }, { 4229 .compatible = "innolux,g070ace-l01", 4230 .data = &innolux_g070ace_l01, 4231 }, { 4232 .compatible = "innolux,g070y2-l01", 4233 .data = &innolux_g070y2_l01, 4234 }, { 4235 .compatible = "innolux,g070y2-t02", 4236 .data = &innolux_g070y2_t02, 4237 }, { 4238 .compatible = "innolux,g101ice-l01", 4239 .data = &innolux_g101ice_l01 4240 }, { 4241 .compatible = "innolux,g121i1-l01", 4242 .data = &innolux_g121i1_l01 4243 }, { 4244 .compatible = "innolux,g121x1-l03", 4245 .data = &innolux_g121x1_l03, 4246 }, { 4247 .compatible = "innolux,n156bge-l21", 4248 .data = &innolux_n156bge_l21, 4249 }, { 4250 .compatible = "innolux,zj070na-01p", 4251 .data = &innolux_zj070na_01p, 4252 }, { 4253 .compatible = "koe,tx14d24vm1bpa", 4254 .data = &koe_tx14d24vm1bpa, 4255 }, { 4256 .compatible = "koe,tx26d202vm0bwa", 4257 .data = &koe_tx26d202vm0bwa, 4258 }, { 4259 .compatible = "koe,tx31d200vm0baa", 4260 .data = &koe_tx31d200vm0baa, 4261 }, { 4262 .compatible = "kyo,tcg121xglp", 4263 .data = &kyo_tcg121xglp, 4264 }, { 4265 .compatible = "lemaker,bl035-rgb-002", 4266 .data = &lemaker_bl035_rgb_002, 4267 }, { 4268 .compatible = "lg,lb070wv8", 4269 .data = &lg_lb070wv8, 4270 }, { 4271 .compatible = "logicpd,type28", 4272 .data = &logicpd_type_28, 4273 }, { 4274 .compatible = "logictechno,lt161010-2nhc", 4275 .data = &logictechno_lt161010_2nh, 4276 }, { 4277 .compatible = "logictechno,lt161010-2nhr", 4278 .data = &logictechno_lt161010_2nh, 4279 }, { 4280 .compatible = "logictechno,lt170410-2whc", 4281 .data = &logictechno_lt170410_2whc, 4282 }, { 4283 .compatible = "logictechno,lttd800480070-l2rt", 4284 .data = &logictechno_lttd800480070_l2rt, 4285 }, { 4286 .compatible = "logictechno,lttd800480070-l6wh-rt", 4287 .data = &logictechno_lttd800480070_l6wh_rt, 4288 }, { 4289 .compatible = "mitsubishi,aa070mc01-ca1", 4290 .data = &mitsubishi_aa070mc01, 4291 }, { 4292 .compatible = "multi-inno,mi0700s4t-6", 4293 .data = &multi_inno_mi0700s4t_6, 4294 }, { 4295 .compatible = "multi-inno,mi0800ft-9", 4296 .data = &multi_inno_mi0800ft_9, 4297 }, { 4298 .compatible = "multi-inno,mi1010ait-1cp", 4299 .data = &multi_inno_mi1010ait_1cp, 4300 }, { 4301 .compatible = "nec,nl12880bc20-05", 4302 .data = &nec_nl12880bc20_05, 4303 }, { 4304 .compatible = "nec,nl4827hc19-05b", 4305 .data = &nec_nl4827hc19_05b, 4306 }, { 4307 .compatible = "netron-dy,e231732", 4308 .data = &netron_dy_e231732, 4309 }, { 4310 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4311 .data = &newhaven_nhd_43_480272ef_atxl, 4312 }, { 4313 .compatible = "nlt,nl192108ac18-02d", 4314 .data = &nlt_nl192108ac18_02d, 4315 }, { 4316 .compatible = "nvd,9128", 4317 .data = &nvd_9128, 4318 }, { 4319 .compatible = "okaya,rs800480t-7x0gp", 4320 .data = &okaya_rs800480t_7x0gp, 4321 }, { 4322 .compatible = "olimex,lcd-olinuxino-43-ts", 4323 .data = &olimex_lcd_olinuxino_43ts, 4324 }, { 4325 .compatible = "ontat,yx700wv03", 4326 .data = &ontat_yx700wv03, 4327 }, { 4328 .compatible = "ortustech,com37h3m05dtc", 4329 .data = &ortustech_com37h3m, 4330 }, { 4331 .compatible = "ortustech,com37h3m99dtc", 4332 .data = &ortustech_com37h3m, 4333 }, { 4334 .compatible = "ortustech,com43h4m85ulc", 4335 .data = &ortustech_com43h4m85ulc, 4336 }, { 4337 .compatible = "osddisplays,osd070t1718-19ts", 4338 .data = &osddisplays_osd070t1718_19ts, 4339 }, { 4340 .compatible = "pda,91-00156-a0", 4341 .data = &pda_91_00156_a0, 4342 }, { 4343 .compatible = "powertip,ph800480t013-idf02", 4344 .data = &powertip_ph800480t013_idf02, 4345 }, { 4346 .compatible = "qiaodian,qd43003c0-40", 4347 .data = &qd43003c0_40, 4348 }, { 4349 .compatible = "qishenglong,gopher2b-lcd", 4350 .data = &qishenglong_gopher2b_lcd, 4351 }, { 4352 .compatible = "rocktech,rk043fn48h", 4353 .data = &rocktech_rk043fn48h, 4354 }, { 4355 .compatible = "rocktech,rk070er9427", 4356 .data = &rocktech_rk070er9427, 4357 }, { 4358 .compatible = "rocktech,rk101ii01d-ct", 4359 .data = &rocktech_rk101ii01d_ct, 4360 }, { 4361 .compatible = "samsung,ltl101al01", 4362 .data = &samsung_ltl101al01, 4363 }, { 4364 .compatible = "samsung,ltn101nt05", 4365 .data = &samsung_ltn101nt05, 4366 }, { 4367 .compatible = "satoz,sat050at40h12r2", 4368 .data = &satoz_sat050at40h12r2, 4369 }, { 4370 .compatible = "sharp,lq035q7db03", 4371 .data = &sharp_lq035q7db03, 4372 }, { 4373 .compatible = "sharp,lq070y3dg3b", 4374 .data = &sharp_lq070y3dg3b, 4375 }, { 4376 .compatible = "sharp,lq101k1ly04", 4377 .data = &sharp_lq101k1ly04, 4378 }, { 4379 .compatible = "sharp,ls020b1dd01d", 4380 .data = &sharp_ls020b1dd01d, 4381 }, { 4382 .compatible = "shelly,sca07010-bfn-lnn", 4383 .data = &shelly_sca07010_bfn_lnn, 4384 }, { 4385 .compatible = "starry,kr070pe2t", 4386 .data = &starry_kr070pe2t, 4387 }, { 4388 .compatible = "startek,kd070wvfpa", 4389 .data = &startek_kd070wvfpa, 4390 }, { 4391 .compatible = "team-source-display,tst043015cmhx", 4392 .data = &tsd_tst043015cmhx, 4393 }, { 4394 .compatible = "tfc,s9700rtwv43tr-01b", 4395 .data = &tfc_s9700rtwv43tr_01b, 4396 }, { 4397 .compatible = "tianma,tm070jdhg30", 4398 .data = &tianma_tm070jdhg30, 4399 }, { 4400 .compatible = "tianma,tm070jvhg33", 4401 .data = &tianma_tm070jvhg33, 4402 }, { 4403 .compatible = "tianma,tm070rvhg71", 4404 .data = &tianma_tm070rvhg71, 4405 }, { 4406 .compatible = "ti,nspire-cx-lcd-panel", 4407 .data = &ti_nspire_cx_lcd_panel, 4408 }, { 4409 .compatible = "ti,nspire-classic-lcd-panel", 4410 .data = &ti_nspire_classic_lcd_panel, 4411 }, { 4412 .compatible = "toshiba,lt089ac29000", 4413 .data = &toshiba_lt089ac29000, 4414 }, { 4415 .compatible = "tpk,f07a-0102", 4416 .data = &tpk_f07a_0102, 4417 }, { 4418 .compatible = "tpk,f10a-0102", 4419 .data = &tpk_f10a_0102, 4420 }, { 4421 .compatible = "urt,umsh-8596md-t", 4422 .data = &urt_umsh_8596md_parallel, 4423 }, { 4424 .compatible = "urt,umsh-8596md-1t", 4425 .data = &urt_umsh_8596md_parallel, 4426 }, { 4427 .compatible = "urt,umsh-8596md-7t", 4428 .data = &urt_umsh_8596md_parallel, 4429 }, { 4430 .compatible = "urt,umsh-8596md-11t", 4431 .data = &urt_umsh_8596md_lvds, 4432 }, { 4433 .compatible = "urt,umsh-8596md-19t", 4434 .data = &urt_umsh_8596md_lvds, 4435 }, { 4436 .compatible = "urt,umsh-8596md-20t", 4437 .data = &urt_umsh_8596md_parallel, 4438 }, { 4439 .compatible = "vivax,tpc9150-panel", 4440 .data = &vivax_tpc9150_panel, 4441 }, { 4442 .compatible = "vxt,vl050-8048nt-c01", 4443 .data = &vl050_8048nt_c01, 4444 }, { 4445 .compatible = "winstar,wf35ltiacd", 4446 .data = &winstar_wf35ltiacd, 4447 }, { 4448 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4449 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4450 }, { 4451 /* Must be the last entry */ 4452 .compatible = "panel-dpi", 4453 .data = &panel_dpi, 4454 }, { 4455 /* sentinel */ 4456 } 4457 }; 4458 MODULE_DEVICE_TABLE(of, platform_of_match); 4459 4460 static int panel_simple_platform_probe(struct platform_device *pdev) 4461 { 4462 const struct of_device_id *id; 4463 4464 id = of_match_node(platform_of_match, pdev->dev.of_node); 4465 if (!id) 4466 return -ENODEV; 4467 4468 return panel_simple_probe(&pdev->dev, id->data); 4469 } 4470 4471 static int panel_simple_platform_remove(struct platform_device *pdev) 4472 { 4473 panel_simple_remove(&pdev->dev); 4474 4475 return 0; 4476 } 4477 4478 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4479 { 4480 panel_simple_shutdown(&pdev->dev); 4481 } 4482 4483 static const struct dev_pm_ops panel_simple_pm_ops = { 4484 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4485 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4486 pm_runtime_force_resume) 4487 }; 4488 4489 static struct platform_driver panel_simple_platform_driver = { 4490 .driver = { 4491 .name = "panel-simple", 4492 .of_match_table = platform_of_match, 4493 .pm = &panel_simple_pm_ops, 4494 }, 4495 .probe = panel_simple_platform_probe, 4496 .remove = panel_simple_platform_remove, 4497 .shutdown = panel_simple_platform_shutdown, 4498 }; 4499 4500 struct panel_desc_dsi { 4501 struct panel_desc desc; 4502 4503 unsigned long flags; 4504 enum mipi_dsi_pixel_format format; 4505 unsigned int lanes; 4506 }; 4507 4508 static const struct drm_display_mode auo_b080uan01_mode = { 4509 .clock = 154500, 4510 .hdisplay = 1200, 4511 .hsync_start = 1200 + 62, 4512 .hsync_end = 1200 + 62 + 4, 4513 .htotal = 1200 + 62 + 4 + 62, 4514 .vdisplay = 1920, 4515 .vsync_start = 1920 + 9, 4516 .vsync_end = 1920 + 9 + 2, 4517 .vtotal = 1920 + 9 + 2 + 8, 4518 }; 4519 4520 static const struct panel_desc_dsi auo_b080uan01 = { 4521 .desc = { 4522 .modes = &auo_b080uan01_mode, 4523 .num_modes = 1, 4524 .bpc = 8, 4525 .size = { 4526 .width = 108, 4527 .height = 272, 4528 }, 4529 .connector_type = DRM_MODE_CONNECTOR_DSI, 4530 }, 4531 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4532 .format = MIPI_DSI_FMT_RGB888, 4533 .lanes = 4, 4534 }; 4535 4536 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4537 .clock = 160000, 4538 .hdisplay = 1200, 4539 .hsync_start = 1200 + 120, 4540 .hsync_end = 1200 + 120 + 20, 4541 .htotal = 1200 + 120 + 20 + 21, 4542 .vdisplay = 1920, 4543 .vsync_start = 1920 + 21, 4544 .vsync_end = 1920 + 21 + 3, 4545 .vtotal = 1920 + 21 + 3 + 18, 4546 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4547 }; 4548 4549 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4550 .desc = { 4551 .modes = &boe_tv080wum_nl0_mode, 4552 .num_modes = 1, 4553 .size = { 4554 .width = 107, 4555 .height = 172, 4556 }, 4557 .connector_type = DRM_MODE_CONNECTOR_DSI, 4558 }, 4559 .flags = MIPI_DSI_MODE_VIDEO | 4560 MIPI_DSI_MODE_VIDEO_BURST | 4561 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4562 .format = MIPI_DSI_FMT_RGB888, 4563 .lanes = 4, 4564 }; 4565 4566 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4567 .clock = 71000, 4568 .hdisplay = 800, 4569 .hsync_start = 800 + 32, 4570 .hsync_end = 800 + 32 + 1, 4571 .htotal = 800 + 32 + 1 + 57, 4572 .vdisplay = 1280, 4573 .vsync_start = 1280 + 28, 4574 .vsync_end = 1280 + 28 + 1, 4575 .vtotal = 1280 + 28 + 1 + 14, 4576 }; 4577 4578 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4579 .desc = { 4580 .modes = &lg_ld070wx3_sl01_mode, 4581 .num_modes = 1, 4582 .bpc = 8, 4583 .size = { 4584 .width = 94, 4585 .height = 151, 4586 }, 4587 .connector_type = DRM_MODE_CONNECTOR_DSI, 4588 }, 4589 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4590 .format = MIPI_DSI_FMT_RGB888, 4591 .lanes = 4, 4592 }; 4593 4594 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4595 .clock = 67000, 4596 .hdisplay = 720, 4597 .hsync_start = 720 + 12, 4598 .hsync_end = 720 + 12 + 4, 4599 .htotal = 720 + 12 + 4 + 112, 4600 .vdisplay = 1280, 4601 .vsync_start = 1280 + 8, 4602 .vsync_end = 1280 + 8 + 4, 4603 .vtotal = 1280 + 8 + 4 + 12, 4604 }; 4605 4606 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4607 .desc = { 4608 .modes = &lg_lh500wx1_sd03_mode, 4609 .num_modes = 1, 4610 .bpc = 8, 4611 .size = { 4612 .width = 62, 4613 .height = 110, 4614 }, 4615 .connector_type = DRM_MODE_CONNECTOR_DSI, 4616 }, 4617 .flags = MIPI_DSI_MODE_VIDEO, 4618 .format = MIPI_DSI_FMT_RGB888, 4619 .lanes = 4, 4620 }; 4621 4622 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4623 .clock = 157200, 4624 .hdisplay = 1920, 4625 .hsync_start = 1920 + 154, 4626 .hsync_end = 1920 + 154 + 16, 4627 .htotal = 1920 + 154 + 16 + 32, 4628 .vdisplay = 1200, 4629 .vsync_start = 1200 + 17, 4630 .vsync_end = 1200 + 17 + 2, 4631 .vtotal = 1200 + 17 + 2 + 16, 4632 }; 4633 4634 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4635 .desc = { 4636 .modes = &panasonic_vvx10f004b00_mode, 4637 .num_modes = 1, 4638 .bpc = 8, 4639 .size = { 4640 .width = 217, 4641 .height = 136, 4642 }, 4643 .connector_type = DRM_MODE_CONNECTOR_DSI, 4644 }, 4645 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4646 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4647 .format = MIPI_DSI_FMT_RGB888, 4648 .lanes = 4, 4649 }; 4650 4651 static const struct drm_display_mode lg_acx467akm_7_mode = { 4652 .clock = 150000, 4653 .hdisplay = 1080, 4654 .hsync_start = 1080 + 2, 4655 .hsync_end = 1080 + 2 + 2, 4656 .htotal = 1080 + 2 + 2 + 2, 4657 .vdisplay = 1920, 4658 .vsync_start = 1920 + 2, 4659 .vsync_end = 1920 + 2 + 2, 4660 .vtotal = 1920 + 2 + 2 + 2, 4661 }; 4662 4663 static const struct panel_desc_dsi lg_acx467akm_7 = { 4664 .desc = { 4665 .modes = &lg_acx467akm_7_mode, 4666 .num_modes = 1, 4667 .bpc = 8, 4668 .size = { 4669 .width = 62, 4670 .height = 110, 4671 }, 4672 .connector_type = DRM_MODE_CONNECTOR_DSI, 4673 }, 4674 .flags = 0, 4675 .format = MIPI_DSI_FMT_RGB888, 4676 .lanes = 4, 4677 }; 4678 4679 static const struct drm_display_mode osd101t2045_53ts_mode = { 4680 .clock = 154500, 4681 .hdisplay = 1920, 4682 .hsync_start = 1920 + 112, 4683 .hsync_end = 1920 + 112 + 16, 4684 .htotal = 1920 + 112 + 16 + 32, 4685 .vdisplay = 1200, 4686 .vsync_start = 1200 + 16, 4687 .vsync_end = 1200 + 16 + 2, 4688 .vtotal = 1200 + 16 + 2 + 16, 4689 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4690 }; 4691 4692 static const struct panel_desc_dsi osd101t2045_53ts = { 4693 .desc = { 4694 .modes = &osd101t2045_53ts_mode, 4695 .num_modes = 1, 4696 .bpc = 8, 4697 .size = { 4698 .width = 217, 4699 .height = 136, 4700 }, 4701 .connector_type = DRM_MODE_CONNECTOR_DSI, 4702 }, 4703 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4704 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4705 MIPI_DSI_MODE_NO_EOT_PACKET, 4706 .format = MIPI_DSI_FMT_RGB888, 4707 .lanes = 4, 4708 }; 4709 4710 static const struct of_device_id dsi_of_match[] = { 4711 { 4712 .compatible = "auo,b080uan01", 4713 .data = &auo_b080uan01 4714 }, { 4715 .compatible = "boe,tv080wum-nl0", 4716 .data = &boe_tv080wum_nl0 4717 }, { 4718 .compatible = "lg,ld070wx3-sl01", 4719 .data = &lg_ld070wx3_sl01 4720 }, { 4721 .compatible = "lg,lh500wx1-sd03", 4722 .data = &lg_lh500wx1_sd03 4723 }, { 4724 .compatible = "panasonic,vvx10f004b00", 4725 .data = &panasonic_vvx10f004b00 4726 }, { 4727 .compatible = "lg,acx467akm-7", 4728 .data = &lg_acx467akm_7 4729 }, { 4730 .compatible = "osddisplays,osd101t2045-53ts", 4731 .data = &osd101t2045_53ts 4732 }, { 4733 /* sentinel */ 4734 } 4735 }; 4736 MODULE_DEVICE_TABLE(of, dsi_of_match); 4737 4738 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4739 { 4740 const struct panel_desc_dsi *desc; 4741 const struct of_device_id *id; 4742 int err; 4743 4744 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4745 if (!id) 4746 return -ENODEV; 4747 4748 desc = id->data; 4749 4750 err = panel_simple_probe(&dsi->dev, &desc->desc); 4751 if (err < 0) 4752 return err; 4753 4754 dsi->mode_flags = desc->flags; 4755 dsi->format = desc->format; 4756 dsi->lanes = desc->lanes; 4757 4758 err = mipi_dsi_attach(dsi); 4759 if (err) { 4760 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4761 4762 drm_panel_remove(&panel->base); 4763 } 4764 4765 return err; 4766 } 4767 4768 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4769 { 4770 int err; 4771 4772 err = mipi_dsi_detach(dsi); 4773 if (err < 0) 4774 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4775 4776 panel_simple_remove(&dsi->dev); 4777 } 4778 4779 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4780 { 4781 panel_simple_shutdown(&dsi->dev); 4782 } 4783 4784 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4785 .driver = { 4786 .name = "panel-simple-dsi", 4787 .of_match_table = dsi_of_match, 4788 .pm = &panel_simple_pm_ops, 4789 }, 4790 .probe = panel_simple_dsi_probe, 4791 .remove = panel_simple_dsi_remove, 4792 .shutdown = panel_simple_dsi_shutdown, 4793 }; 4794 4795 static int __init panel_simple_init(void) 4796 { 4797 int err; 4798 4799 err = platform_driver_register(&panel_simple_platform_driver); 4800 if (err < 0) 4801 return err; 4802 4803 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4804 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4805 if (err < 0) 4806 goto err_did_platform_register; 4807 } 4808 4809 return 0; 4810 4811 err_did_platform_register: 4812 platform_driver_unregister(&panel_simple_platform_driver); 4813 4814 return err; 4815 } 4816 module_init(panel_simple_init); 4817 4818 static void __exit panel_simple_exit(void) 4819 { 4820 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4821 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4822 4823 platform_driver_unregister(&panel_simple_platform_driver); 4824 } 4825 module_exit(panel_simple_exit); 4826 4827 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4828 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4829 MODULE_LICENSE("GPL and additional rights"); 4830