1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/delay.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct backlight_device *backlight; 109 struct regulator *supply; 110 struct i2c_adapter *ddc; 111 112 struct gpio_desc *enable_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel) 123 { 124 struct drm_connector *connector = panel->base.connector; 125 struct drm_device *drm = panel->base.drm; 126 struct drm_display_mode *mode; 127 unsigned int i, num = 0; 128 129 for (i = 0; i < panel->desc->num_timings; i++) { 130 const struct display_timing *dt = &panel->desc->timings[i]; 131 struct videomode vm; 132 133 videomode_from_timing(dt, &vm); 134 mode = drm_mode_create(drm); 135 if (!mode) { 136 dev_err(drm->dev, "failed to add mode %ux%u\n", 137 dt->hactive.typ, dt->vactive.typ); 138 continue; 139 } 140 141 drm_display_mode_from_videomode(&vm, mode); 142 143 mode->type |= DRM_MODE_TYPE_DRIVER; 144 145 if (panel->desc->num_timings == 1) 146 mode->type |= DRM_MODE_TYPE_PREFERRED; 147 148 drm_mode_probed_add(connector, mode); 149 num++; 150 } 151 152 return num; 153 } 154 155 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel) 156 { 157 struct drm_connector *connector = panel->base.connector; 158 struct drm_device *drm = panel->base.drm; 159 struct drm_display_mode *mode; 160 unsigned int i, num = 0; 161 162 for (i = 0; i < panel->desc->num_modes; i++) { 163 const struct drm_display_mode *m = &panel->desc->modes[i]; 164 165 mode = drm_mode_duplicate(drm, m); 166 if (!mode) { 167 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 168 m->hdisplay, m->vdisplay, m->vrefresh); 169 continue; 170 } 171 172 mode->type |= DRM_MODE_TYPE_DRIVER; 173 174 if (panel->desc->num_modes == 1) 175 mode->type |= DRM_MODE_TYPE_PREFERRED; 176 177 drm_mode_set_name(mode); 178 179 drm_mode_probed_add(connector, mode); 180 num++; 181 } 182 183 return num; 184 } 185 186 static int panel_simple_get_non_edid_modes(struct panel_simple *panel) 187 { 188 struct drm_connector *connector = panel->base.connector; 189 struct drm_device *drm = panel->base.drm; 190 struct drm_display_mode *mode; 191 bool has_override = panel->override_mode.type; 192 unsigned int num = 0; 193 194 if (!panel->desc) 195 return 0; 196 197 if (has_override) { 198 mode = drm_mode_duplicate(drm, &panel->override_mode); 199 if (mode) { 200 drm_mode_probed_add(connector, mode); 201 num = 1; 202 } else { 203 dev_err(drm->dev, "failed to add override mode\n"); 204 } 205 } 206 207 /* Only add timings if override was not there or failed to validate */ 208 if (num == 0 && panel->desc->num_timings) 209 num = panel_simple_get_timings_modes(panel); 210 211 /* 212 * Only add fixed modes if timings/override added no mode. 213 * 214 * We should only ever have either the display timings specified 215 * or a fixed mode. Anything else is rather bogus. 216 */ 217 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 218 if (num == 0) 219 num = panel_simple_get_display_modes(panel); 220 221 connector->display_info.bpc = panel->desc->bpc; 222 connector->display_info.width_mm = panel->desc->size.width; 223 connector->display_info.height_mm = panel->desc->size.height; 224 if (panel->desc->bus_format) 225 drm_display_info_set_bus_formats(&connector->display_info, 226 &panel->desc->bus_format, 1); 227 connector->display_info.bus_flags = panel->desc->bus_flags; 228 229 return num; 230 } 231 232 static int panel_simple_disable(struct drm_panel *panel) 233 { 234 struct panel_simple *p = to_panel_simple(panel); 235 236 if (!p->enabled) 237 return 0; 238 239 if (p->backlight) { 240 p->backlight->props.power = FB_BLANK_POWERDOWN; 241 p->backlight->props.state |= BL_CORE_FBBLANK; 242 backlight_update_status(p->backlight); 243 } 244 245 if (p->desc->delay.disable) 246 msleep(p->desc->delay.disable); 247 248 p->enabled = false; 249 250 return 0; 251 } 252 253 static int panel_simple_unprepare(struct drm_panel *panel) 254 { 255 struct panel_simple *p = to_panel_simple(panel); 256 257 if (!p->prepared) 258 return 0; 259 260 gpiod_set_value_cansleep(p->enable_gpio, 0); 261 262 regulator_disable(p->supply); 263 264 if (p->desc->delay.unprepare) 265 msleep(p->desc->delay.unprepare); 266 267 p->prepared = false; 268 269 return 0; 270 } 271 272 static int panel_simple_prepare(struct drm_panel *panel) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int delay; 276 int err; 277 278 if (p->prepared) 279 return 0; 280 281 err = regulator_enable(p->supply); 282 if (err < 0) { 283 dev_err(panel->dev, "failed to enable supply: %d\n", err); 284 return err; 285 } 286 287 gpiod_set_value_cansleep(p->enable_gpio, 1); 288 289 delay = p->desc->delay.prepare; 290 if (p->no_hpd) 291 delay += p->desc->delay.hpd_absent_delay; 292 if (delay) 293 msleep(delay); 294 295 p->prepared = true; 296 297 return 0; 298 } 299 300 static int panel_simple_enable(struct drm_panel *panel) 301 { 302 struct panel_simple *p = to_panel_simple(panel); 303 304 if (p->enabled) 305 return 0; 306 307 if (p->desc->delay.enable) 308 msleep(p->desc->delay.enable); 309 310 if (p->backlight) { 311 p->backlight->props.state &= ~BL_CORE_FBBLANK; 312 p->backlight->props.power = FB_BLANK_UNBLANK; 313 backlight_update_status(p->backlight); 314 } 315 316 p->enabled = true; 317 318 return 0; 319 } 320 321 static int panel_simple_get_modes(struct drm_panel *panel) 322 { 323 struct panel_simple *p = to_panel_simple(panel); 324 int num = 0; 325 326 /* probe EDID if a DDC bus is available */ 327 if (p->ddc) { 328 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 329 drm_connector_update_edid_property(panel->connector, edid); 330 if (edid) { 331 num += drm_add_edid_modes(panel->connector, edid); 332 kfree(edid); 333 } 334 } 335 336 /* add hard-coded panel modes */ 337 num += panel_simple_get_non_edid_modes(p); 338 339 return num; 340 } 341 342 static int panel_simple_get_timings(struct drm_panel *panel, 343 unsigned int num_timings, 344 struct display_timing *timings) 345 { 346 struct panel_simple *p = to_panel_simple(panel); 347 unsigned int i; 348 349 if (p->desc->num_timings < num_timings) 350 num_timings = p->desc->num_timings; 351 352 if (timings) 353 for (i = 0; i < num_timings; i++) 354 timings[i] = p->desc->timings[i]; 355 356 return p->desc->num_timings; 357 } 358 359 static const struct drm_panel_funcs panel_simple_funcs = { 360 .disable = panel_simple_disable, 361 .unprepare = panel_simple_unprepare, 362 .prepare = panel_simple_prepare, 363 .enable = panel_simple_enable, 364 .get_modes = panel_simple_get_modes, 365 .get_timings = panel_simple_get_timings, 366 }; 367 368 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 369 (to_check->field.typ >= bounds->field.min && \ 370 to_check->field.typ <= bounds->field.max) 371 static void panel_simple_parse_panel_timing_node(struct device *dev, 372 struct panel_simple *panel, 373 const struct display_timing *ot) 374 { 375 const struct panel_desc *desc = panel->desc; 376 struct videomode vm; 377 unsigned int i; 378 379 if (WARN_ON(desc->num_modes)) { 380 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 381 return; 382 } 383 if (WARN_ON(!desc->num_timings)) { 384 dev_err(dev, "Reject override mode: no timings specified\n"); 385 return; 386 } 387 388 for (i = 0; i < panel->desc->num_timings; i++) { 389 const struct display_timing *dt = &panel->desc->timings[i]; 390 391 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 392 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 393 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 394 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 395 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 396 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 397 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 398 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 399 continue; 400 401 if (ot->flags != dt->flags) 402 continue; 403 404 videomode_from_timing(ot, &vm); 405 drm_display_mode_from_videomode(&vm, &panel->override_mode); 406 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 407 DRM_MODE_TYPE_PREFERRED; 408 break; 409 } 410 411 if (WARN_ON(!panel->override_mode.type)) 412 dev_err(dev, "Reject override mode: No display_timing found\n"); 413 } 414 415 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 416 { 417 struct device_node *backlight, *ddc; 418 struct panel_simple *panel; 419 struct display_timing dt; 420 int err; 421 422 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 423 if (!panel) 424 return -ENOMEM; 425 426 panel->enabled = false; 427 panel->prepared = false; 428 panel->desc = desc; 429 430 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 431 432 panel->supply = devm_regulator_get(dev, "power"); 433 if (IS_ERR(panel->supply)) 434 return PTR_ERR(panel->supply); 435 436 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 437 GPIOD_OUT_LOW); 438 if (IS_ERR(panel->enable_gpio)) { 439 err = PTR_ERR(panel->enable_gpio); 440 if (err != -EPROBE_DEFER) 441 dev_err(dev, "failed to request GPIO: %d\n", err); 442 return err; 443 } 444 445 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 446 if (backlight) { 447 panel->backlight = of_find_backlight_by_node(backlight); 448 of_node_put(backlight); 449 450 if (!panel->backlight) 451 return -EPROBE_DEFER; 452 } 453 454 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 455 if (ddc) { 456 panel->ddc = of_find_i2c_adapter_by_node(ddc); 457 of_node_put(ddc); 458 459 if (!panel->ddc) { 460 err = -EPROBE_DEFER; 461 goto free_backlight; 462 } 463 } 464 465 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 466 panel_simple_parse_panel_timing_node(dev, panel, &dt); 467 468 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 469 desc->connector_type); 470 471 err = drm_panel_add(&panel->base); 472 if (err < 0) 473 goto free_ddc; 474 475 dev_set_drvdata(dev, panel); 476 477 return 0; 478 479 free_ddc: 480 if (panel->ddc) 481 put_device(&panel->ddc->dev); 482 free_backlight: 483 if (panel->backlight) 484 put_device(&panel->backlight->dev); 485 486 return err; 487 } 488 489 static int panel_simple_remove(struct device *dev) 490 { 491 struct panel_simple *panel = dev_get_drvdata(dev); 492 493 drm_panel_remove(&panel->base); 494 495 panel_simple_disable(&panel->base); 496 panel_simple_unprepare(&panel->base); 497 498 if (panel->ddc) 499 put_device(&panel->ddc->dev); 500 501 if (panel->backlight) 502 put_device(&panel->backlight->dev); 503 504 return 0; 505 } 506 507 static void panel_simple_shutdown(struct device *dev) 508 { 509 struct panel_simple *panel = dev_get_drvdata(dev); 510 511 panel_simple_disable(&panel->base); 512 panel_simple_unprepare(&panel->base); 513 } 514 515 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 516 .clock = 9000, 517 .hdisplay = 480, 518 .hsync_start = 480 + 2, 519 .hsync_end = 480 + 2 + 41, 520 .htotal = 480 + 2 + 41 + 2, 521 .vdisplay = 272, 522 .vsync_start = 272 + 2, 523 .vsync_end = 272 + 2 + 10, 524 .vtotal = 272 + 2 + 10 + 2, 525 .vrefresh = 60, 526 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 527 }; 528 529 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 530 .modes = &ire_am_480272h3tmqw_t01h_mode, 531 .num_modes = 1, 532 .bpc = 8, 533 .size = { 534 .width = 105, 535 .height = 67, 536 }, 537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 538 }; 539 540 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 541 .clock = 33333, 542 .hdisplay = 800, 543 .hsync_start = 800 + 0, 544 .hsync_end = 800 + 0 + 255, 545 .htotal = 800 + 0 + 255 + 0, 546 .vdisplay = 480, 547 .vsync_start = 480 + 2, 548 .vsync_end = 480 + 2 + 45, 549 .vtotal = 480 + 2 + 45 + 0, 550 .vrefresh = 60, 551 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 552 }; 553 554 static const struct panel_desc ampire_am800480r3tmqwa1h = { 555 .modes = &ire_am800480r3tmqwa1h_mode, 556 .num_modes = 1, 557 .bpc = 6, 558 .size = { 559 .width = 152, 560 .height = 91, 561 }, 562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 563 }; 564 565 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 566 .pixelclock = { 26400000, 33300000, 46800000 }, 567 .hactive = { 800, 800, 800 }, 568 .hfront_porch = { 16, 210, 354 }, 569 .hback_porch = { 45, 36, 6 }, 570 .hsync_len = { 1, 10, 40 }, 571 .vactive = { 480, 480, 480 }, 572 .vfront_porch = { 7, 22, 147 }, 573 .vback_porch = { 22, 13, 3 }, 574 .vsync_len = { 1, 10, 20 }, 575 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 576 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 577 }; 578 579 static const struct panel_desc armadeus_st0700_adapt = { 580 .timings = &santek_st0700i5y_rbslw_f_timing, 581 .num_timings = 1, 582 .bpc = 6, 583 .size = { 584 .width = 154, 585 .height = 86, 586 }, 587 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 589 }; 590 591 static const struct drm_display_mode auo_b101aw03_mode = { 592 .clock = 51450, 593 .hdisplay = 1024, 594 .hsync_start = 1024 + 156, 595 .hsync_end = 1024 + 156 + 8, 596 .htotal = 1024 + 156 + 8 + 156, 597 .vdisplay = 600, 598 .vsync_start = 600 + 16, 599 .vsync_end = 600 + 16 + 6, 600 .vtotal = 600 + 16 + 6 + 16, 601 .vrefresh = 60, 602 }; 603 604 static const struct panel_desc auo_b101aw03 = { 605 .modes = &auo_b101aw03_mode, 606 .num_modes = 1, 607 .bpc = 6, 608 .size = { 609 .width = 223, 610 .height = 125, 611 }, 612 }; 613 614 static const struct display_timing auo_b101ean01_timing = { 615 .pixelclock = { 65300000, 72500000, 75000000 }, 616 .hactive = { 1280, 1280, 1280 }, 617 .hfront_porch = { 18, 119, 119 }, 618 .hback_porch = { 21, 21, 21 }, 619 .hsync_len = { 32, 32, 32 }, 620 .vactive = { 800, 800, 800 }, 621 .vfront_porch = { 4, 4, 4 }, 622 .vback_porch = { 8, 8, 8 }, 623 .vsync_len = { 18, 20, 20 }, 624 }; 625 626 static const struct panel_desc auo_b101ean01 = { 627 .timings = &auo_b101ean01_timing, 628 .num_timings = 1, 629 .bpc = 6, 630 .size = { 631 .width = 217, 632 .height = 136, 633 }, 634 }; 635 636 static const struct drm_display_mode auo_b101xtn01_mode = { 637 .clock = 72000, 638 .hdisplay = 1366, 639 .hsync_start = 1366 + 20, 640 .hsync_end = 1366 + 20 + 70, 641 .htotal = 1366 + 20 + 70, 642 .vdisplay = 768, 643 .vsync_start = 768 + 14, 644 .vsync_end = 768 + 14 + 42, 645 .vtotal = 768 + 14 + 42, 646 .vrefresh = 60, 647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 648 }; 649 650 static const struct panel_desc auo_b101xtn01 = { 651 .modes = &auo_b101xtn01_mode, 652 .num_modes = 1, 653 .bpc = 6, 654 .size = { 655 .width = 223, 656 .height = 125, 657 }, 658 }; 659 660 static const struct drm_display_mode auo_b116xw03_mode = { 661 .clock = 70589, 662 .hdisplay = 1366, 663 .hsync_start = 1366 + 40, 664 .hsync_end = 1366 + 40 + 40, 665 .htotal = 1366 + 40 + 40 + 32, 666 .vdisplay = 768, 667 .vsync_start = 768 + 10, 668 .vsync_end = 768 + 10 + 12, 669 .vtotal = 768 + 10 + 12 + 6, 670 .vrefresh = 60, 671 }; 672 673 static const struct panel_desc auo_b116xw03 = { 674 .modes = &auo_b116xw03_mode, 675 .num_modes = 1, 676 .bpc = 6, 677 .size = { 678 .width = 256, 679 .height = 144, 680 }, 681 }; 682 683 static const struct drm_display_mode auo_b133xtn01_mode = { 684 .clock = 69500, 685 .hdisplay = 1366, 686 .hsync_start = 1366 + 48, 687 .hsync_end = 1366 + 48 + 32, 688 .htotal = 1366 + 48 + 32 + 20, 689 .vdisplay = 768, 690 .vsync_start = 768 + 3, 691 .vsync_end = 768 + 3 + 6, 692 .vtotal = 768 + 3 + 6 + 13, 693 .vrefresh = 60, 694 }; 695 696 static const struct panel_desc auo_b133xtn01 = { 697 .modes = &auo_b133xtn01_mode, 698 .num_modes = 1, 699 .bpc = 6, 700 .size = { 701 .width = 293, 702 .height = 165, 703 }, 704 }; 705 706 static const struct drm_display_mode auo_b133htn01_mode = { 707 .clock = 150660, 708 .hdisplay = 1920, 709 .hsync_start = 1920 + 172, 710 .hsync_end = 1920 + 172 + 80, 711 .htotal = 1920 + 172 + 80 + 60, 712 .vdisplay = 1080, 713 .vsync_start = 1080 + 25, 714 .vsync_end = 1080 + 25 + 10, 715 .vtotal = 1080 + 25 + 10 + 10, 716 .vrefresh = 60, 717 }; 718 719 static const struct panel_desc auo_b133htn01 = { 720 .modes = &auo_b133htn01_mode, 721 .num_modes = 1, 722 .bpc = 6, 723 .size = { 724 .width = 293, 725 .height = 165, 726 }, 727 .delay = { 728 .prepare = 105, 729 .enable = 20, 730 .unprepare = 50, 731 }, 732 }; 733 734 static const struct display_timing auo_g070vvn01_timings = { 735 .pixelclock = { 33300000, 34209000, 45000000 }, 736 .hactive = { 800, 800, 800 }, 737 .hfront_porch = { 20, 40, 200 }, 738 .hback_porch = { 87, 40, 1 }, 739 .hsync_len = { 1, 48, 87 }, 740 .vactive = { 480, 480, 480 }, 741 .vfront_porch = { 5, 13, 200 }, 742 .vback_porch = { 31, 31, 29 }, 743 .vsync_len = { 1, 1, 3 }, 744 }; 745 746 static const struct panel_desc auo_g070vvn01 = { 747 .timings = &auo_g070vvn01_timings, 748 .num_timings = 1, 749 .bpc = 8, 750 .size = { 751 .width = 152, 752 .height = 91, 753 }, 754 .delay = { 755 .prepare = 200, 756 .enable = 50, 757 .disable = 50, 758 .unprepare = 1000, 759 }, 760 }; 761 762 static const struct drm_display_mode auo_g101evn010_mode = { 763 .clock = 68930, 764 .hdisplay = 1280, 765 .hsync_start = 1280 + 82, 766 .hsync_end = 1280 + 82 + 2, 767 .htotal = 1280 + 82 + 2 + 84, 768 .vdisplay = 800, 769 .vsync_start = 800 + 8, 770 .vsync_end = 800 + 8 + 2, 771 .vtotal = 800 + 8 + 2 + 6, 772 .vrefresh = 60, 773 }; 774 775 static const struct panel_desc auo_g101evn010 = { 776 .modes = &auo_g101evn010_mode, 777 .num_modes = 1, 778 .bpc = 6, 779 .size = { 780 .width = 216, 781 .height = 135, 782 }, 783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 784 }; 785 786 static const struct drm_display_mode auo_g104sn02_mode = { 787 .clock = 40000, 788 .hdisplay = 800, 789 .hsync_start = 800 + 40, 790 .hsync_end = 800 + 40 + 216, 791 .htotal = 800 + 40 + 216 + 128, 792 .vdisplay = 600, 793 .vsync_start = 600 + 10, 794 .vsync_end = 600 + 10 + 35, 795 .vtotal = 600 + 10 + 35 + 2, 796 .vrefresh = 60, 797 }; 798 799 static const struct panel_desc auo_g104sn02 = { 800 .modes = &auo_g104sn02_mode, 801 .num_modes = 1, 802 .bpc = 8, 803 .size = { 804 .width = 211, 805 .height = 158, 806 }, 807 }; 808 809 static const struct display_timing auo_g133han01_timings = { 810 .pixelclock = { 134000000, 141200000, 149000000 }, 811 .hactive = { 1920, 1920, 1920 }, 812 .hfront_porch = { 39, 58, 77 }, 813 .hback_porch = { 59, 88, 117 }, 814 .hsync_len = { 28, 42, 56 }, 815 .vactive = { 1080, 1080, 1080 }, 816 .vfront_porch = { 3, 8, 11 }, 817 .vback_porch = { 5, 14, 19 }, 818 .vsync_len = { 4, 14, 19 }, 819 }; 820 821 static const struct panel_desc auo_g133han01 = { 822 .timings = &auo_g133han01_timings, 823 .num_timings = 1, 824 .bpc = 8, 825 .size = { 826 .width = 293, 827 .height = 165, 828 }, 829 .delay = { 830 .prepare = 200, 831 .enable = 50, 832 .disable = 50, 833 .unprepare = 1000, 834 }, 835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 836 .connector_type = DRM_MODE_CONNECTOR_LVDS, 837 }; 838 839 static const struct display_timing auo_g185han01_timings = { 840 .pixelclock = { 120000000, 144000000, 175000000 }, 841 .hactive = { 1920, 1920, 1920 }, 842 .hfront_porch = { 36, 120, 148 }, 843 .hback_porch = { 24, 88, 108 }, 844 .hsync_len = { 20, 48, 64 }, 845 .vactive = { 1080, 1080, 1080 }, 846 .vfront_porch = { 6, 10, 40 }, 847 .vback_porch = { 2, 5, 20 }, 848 .vsync_len = { 2, 5, 20 }, 849 }; 850 851 static const struct panel_desc auo_g185han01 = { 852 .timings = &auo_g185han01_timings, 853 .num_timings = 1, 854 .bpc = 8, 855 .size = { 856 .width = 409, 857 .height = 230, 858 }, 859 .delay = { 860 .prepare = 50, 861 .enable = 200, 862 .disable = 110, 863 .unprepare = 1000, 864 }, 865 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 866 .connector_type = DRM_MODE_CONNECTOR_LVDS, 867 }; 868 869 static const struct display_timing auo_p320hvn03_timings = { 870 .pixelclock = { 106000000, 148500000, 164000000 }, 871 .hactive = { 1920, 1920, 1920 }, 872 .hfront_porch = { 25, 50, 130 }, 873 .hback_porch = { 25, 50, 130 }, 874 .hsync_len = { 20, 40, 105 }, 875 .vactive = { 1080, 1080, 1080 }, 876 .vfront_porch = { 8, 17, 150 }, 877 .vback_porch = { 8, 17, 150 }, 878 .vsync_len = { 4, 11, 100 }, 879 }; 880 881 static const struct panel_desc auo_p320hvn03 = { 882 .timings = &auo_p320hvn03_timings, 883 .num_timings = 1, 884 .bpc = 8, 885 .size = { 886 .width = 698, 887 .height = 393, 888 }, 889 .delay = { 890 .prepare = 1, 891 .enable = 450, 892 .unprepare = 500, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 896 }; 897 898 static const struct drm_display_mode auo_t215hvn01_mode = { 899 .clock = 148800, 900 .hdisplay = 1920, 901 .hsync_start = 1920 + 88, 902 .hsync_end = 1920 + 88 + 44, 903 .htotal = 1920 + 88 + 44 + 148, 904 .vdisplay = 1080, 905 .vsync_start = 1080 + 4, 906 .vsync_end = 1080 + 4 + 5, 907 .vtotal = 1080 + 4 + 5 + 36, 908 .vrefresh = 60, 909 }; 910 911 static const struct panel_desc auo_t215hvn01 = { 912 .modes = &auo_t215hvn01_mode, 913 .num_modes = 1, 914 .bpc = 8, 915 .size = { 916 .width = 430, 917 .height = 270, 918 }, 919 .delay = { 920 .disable = 5, 921 .unprepare = 1000, 922 } 923 }; 924 925 static const struct drm_display_mode avic_tm070ddh03_mode = { 926 .clock = 51200, 927 .hdisplay = 1024, 928 .hsync_start = 1024 + 160, 929 .hsync_end = 1024 + 160 + 4, 930 .htotal = 1024 + 160 + 4 + 156, 931 .vdisplay = 600, 932 .vsync_start = 600 + 17, 933 .vsync_end = 600 + 17 + 1, 934 .vtotal = 600 + 17 + 1 + 17, 935 .vrefresh = 60, 936 }; 937 938 static const struct panel_desc avic_tm070ddh03 = { 939 .modes = &avic_tm070ddh03_mode, 940 .num_modes = 1, 941 .bpc = 8, 942 .size = { 943 .width = 154, 944 .height = 90, 945 }, 946 .delay = { 947 .prepare = 20, 948 .enable = 200, 949 .disable = 200, 950 }, 951 }; 952 953 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 954 .clock = 30000, 955 .hdisplay = 800, 956 .hsync_start = 800 + 40, 957 .hsync_end = 800 + 40 + 48, 958 .htotal = 800 + 40 + 48 + 40, 959 .vdisplay = 480, 960 .vsync_start = 480 + 13, 961 .vsync_end = 480 + 13 + 3, 962 .vtotal = 480 + 13 + 3 + 29, 963 }; 964 965 static const struct panel_desc bananapi_s070wv20_ct16 = { 966 .modes = &bananapi_s070wv20_ct16_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 154, 971 .height = 86, 972 }, 973 }; 974 975 static const struct drm_display_mode boe_hv070wsa_mode = { 976 .clock = 42105, 977 .hdisplay = 1024, 978 .hsync_start = 1024 + 30, 979 .hsync_end = 1024 + 30 + 30, 980 .htotal = 1024 + 30 + 30 + 30, 981 .vdisplay = 600, 982 .vsync_start = 600 + 10, 983 .vsync_end = 600 + 10 + 10, 984 .vtotal = 600 + 10 + 10 + 10, 985 .vrefresh = 60, 986 }; 987 988 static const struct panel_desc boe_hv070wsa = { 989 .modes = &boe_hv070wsa_mode, 990 .num_modes = 1, 991 .size = { 992 .width = 154, 993 .height = 90, 994 }, 995 }; 996 997 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 998 { 999 .clock = 71900, 1000 .hdisplay = 1280, 1001 .hsync_start = 1280 + 48, 1002 .hsync_end = 1280 + 48 + 32, 1003 .htotal = 1280 + 48 + 32 + 80, 1004 .vdisplay = 800, 1005 .vsync_start = 800 + 3, 1006 .vsync_end = 800 + 3 + 5, 1007 .vtotal = 800 + 3 + 5 + 24, 1008 .vrefresh = 60, 1009 }, 1010 { 1011 .clock = 57500, 1012 .hdisplay = 1280, 1013 .hsync_start = 1280 + 48, 1014 .hsync_end = 1280 + 48 + 32, 1015 .htotal = 1280 + 48 + 32 + 80, 1016 .vdisplay = 800, 1017 .vsync_start = 800 + 3, 1018 .vsync_end = 800 + 3 + 5, 1019 .vtotal = 800 + 3 + 5 + 24, 1020 .vrefresh = 48, 1021 }, 1022 }; 1023 1024 static const struct panel_desc boe_nv101wxmn51 = { 1025 .modes = boe_nv101wxmn51_modes, 1026 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1027 .bpc = 8, 1028 .size = { 1029 .width = 217, 1030 .height = 136, 1031 }, 1032 .delay = { 1033 .prepare = 210, 1034 .enable = 50, 1035 .unprepare = 160, 1036 }, 1037 }; 1038 1039 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1040 .clock = 9000, 1041 .hdisplay = 480, 1042 .hsync_start = 480 + 5, 1043 .hsync_end = 480 + 5 + 5, 1044 .htotal = 480 + 5 + 5 + 40, 1045 .vdisplay = 272, 1046 .vsync_start = 272 + 8, 1047 .vsync_end = 272 + 8 + 8, 1048 .vtotal = 272 + 8 + 8 + 8, 1049 .vrefresh = 60, 1050 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1051 }; 1052 1053 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1054 .modes = &cdtech_s043wq26h_ct7_mode, 1055 .num_modes = 1, 1056 .bpc = 8, 1057 .size = { 1058 .width = 95, 1059 .height = 54, 1060 }, 1061 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1062 }; 1063 1064 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1065 .clock = 35000, 1066 .hdisplay = 800, 1067 .hsync_start = 800 + 40, 1068 .hsync_end = 800 + 40 + 40, 1069 .htotal = 800 + 40 + 40 + 48, 1070 .vdisplay = 480, 1071 .vsync_start = 480 + 29, 1072 .vsync_end = 480 + 29 + 13, 1073 .vtotal = 480 + 29 + 13 + 3, 1074 .vrefresh = 60, 1075 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1076 }; 1077 1078 static const struct panel_desc cdtech_s070wv95_ct16 = { 1079 .modes = &cdtech_s070wv95_ct16_mode, 1080 .num_modes = 1, 1081 .bpc = 8, 1082 .size = { 1083 .width = 154, 1084 .height = 85, 1085 }, 1086 }; 1087 1088 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1089 .clock = 66770, 1090 .hdisplay = 800, 1091 .hsync_start = 800 + 49, 1092 .hsync_end = 800 + 49 + 33, 1093 .htotal = 800 + 49 + 33 + 17, 1094 .vdisplay = 1280, 1095 .vsync_start = 1280 + 1, 1096 .vsync_end = 1280 + 1 + 7, 1097 .vtotal = 1280 + 1 + 7 + 15, 1098 .vrefresh = 60, 1099 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1100 }; 1101 1102 static const struct panel_desc chunghwa_claa070wp03xg = { 1103 .modes = &chunghwa_claa070wp03xg_mode, 1104 .num_modes = 1, 1105 .bpc = 6, 1106 .size = { 1107 .width = 94, 1108 .height = 150, 1109 }, 1110 }; 1111 1112 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1113 .clock = 72070, 1114 .hdisplay = 1366, 1115 .hsync_start = 1366 + 58, 1116 .hsync_end = 1366 + 58 + 58, 1117 .htotal = 1366 + 58 + 58 + 58, 1118 .vdisplay = 768, 1119 .vsync_start = 768 + 4, 1120 .vsync_end = 768 + 4 + 4, 1121 .vtotal = 768 + 4 + 4 + 4, 1122 .vrefresh = 60, 1123 }; 1124 1125 static const struct panel_desc chunghwa_claa101wa01a = { 1126 .modes = &chunghwa_claa101wa01a_mode, 1127 .num_modes = 1, 1128 .bpc = 6, 1129 .size = { 1130 .width = 220, 1131 .height = 120, 1132 }, 1133 }; 1134 1135 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1136 .clock = 69300, 1137 .hdisplay = 1366, 1138 .hsync_start = 1366 + 48, 1139 .hsync_end = 1366 + 48 + 32, 1140 .htotal = 1366 + 48 + 32 + 20, 1141 .vdisplay = 768, 1142 .vsync_start = 768 + 16, 1143 .vsync_end = 768 + 16 + 8, 1144 .vtotal = 768 + 16 + 8 + 16, 1145 .vrefresh = 60, 1146 }; 1147 1148 static const struct panel_desc chunghwa_claa101wb01 = { 1149 .modes = &chunghwa_claa101wb01_mode, 1150 .num_modes = 1, 1151 .bpc = 6, 1152 .size = { 1153 .width = 223, 1154 .height = 125, 1155 }, 1156 }; 1157 1158 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1159 .clock = 33260, 1160 .hdisplay = 800, 1161 .hsync_start = 800 + 40, 1162 .hsync_end = 800 + 40 + 128, 1163 .htotal = 800 + 40 + 128 + 88, 1164 .vdisplay = 480, 1165 .vsync_start = 480 + 10, 1166 .vsync_end = 480 + 10 + 2, 1167 .vtotal = 480 + 10 + 2 + 33, 1168 .vrefresh = 60, 1169 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1170 }; 1171 1172 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1173 .modes = &dataimage_scf0700c48ggu18_mode, 1174 .num_modes = 1, 1175 .bpc = 8, 1176 .size = { 1177 .width = 152, 1178 .height = 91, 1179 }, 1180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1181 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1182 }; 1183 1184 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1185 .pixelclock = { 45000000, 51200000, 57000000 }, 1186 .hactive = { 1024, 1024, 1024 }, 1187 .hfront_porch = { 100, 106, 113 }, 1188 .hback_porch = { 100, 106, 113 }, 1189 .hsync_len = { 100, 108, 114 }, 1190 .vactive = { 600, 600, 600 }, 1191 .vfront_porch = { 8, 11, 15 }, 1192 .vback_porch = { 8, 11, 15 }, 1193 .vsync_len = { 9, 13, 15 }, 1194 .flags = DISPLAY_FLAGS_DE_HIGH, 1195 }; 1196 1197 static const struct panel_desc dlc_dlc0700yzg_1 = { 1198 .timings = &dlc_dlc0700yzg_1_timing, 1199 .num_timings = 1, 1200 .bpc = 6, 1201 .size = { 1202 .width = 154, 1203 .height = 86, 1204 }, 1205 .delay = { 1206 .prepare = 30, 1207 .enable = 200, 1208 .disable = 200, 1209 }, 1210 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1211 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1212 }; 1213 1214 static const struct display_timing dlc_dlc1010gig_timing = { 1215 .pixelclock = { 68900000, 71100000, 73400000 }, 1216 .hactive = { 1280, 1280, 1280 }, 1217 .hfront_porch = { 43, 53, 63 }, 1218 .hback_porch = { 43, 53, 63 }, 1219 .hsync_len = { 44, 54, 64 }, 1220 .vactive = { 800, 800, 800 }, 1221 .vfront_porch = { 5, 8, 11 }, 1222 .vback_porch = { 5, 8, 11 }, 1223 .vsync_len = { 5, 7, 11 }, 1224 .flags = DISPLAY_FLAGS_DE_HIGH, 1225 }; 1226 1227 static const struct panel_desc dlc_dlc1010gig = { 1228 .timings = &dlc_dlc1010gig_timing, 1229 .num_timings = 1, 1230 .bpc = 8, 1231 .size = { 1232 .width = 216, 1233 .height = 135, 1234 }, 1235 .delay = { 1236 .prepare = 60, 1237 .enable = 150, 1238 .disable = 100, 1239 .unprepare = 60, 1240 }, 1241 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1242 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1243 }; 1244 1245 static const struct drm_display_mode edt_et035012dm6_mode = { 1246 .clock = 6500, 1247 .hdisplay = 320, 1248 .hsync_start = 320 + 20, 1249 .hsync_end = 320 + 20 + 30, 1250 .htotal = 320 + 20 + 68, 1251 .vdisplay = 240, 1252 .vsync_start = 240 + 4, 1253 .vsync_end = 240 + 4 + 4, 1254 .vtotal = 240 + 4 + 4 + 14, 1255 .vrefresh = 60, 1256 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1257 }; 1258 1259 static const struct panel_desc edt_et035012dm6 = { 1260 .modes = &edt_et035012dm6_mode, 1261 .num_modes = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 70, 1265 .height = 52, 1266 }, 1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1268 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1269 }; 1270 1271 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1272 .clock = 9000, 1273 .hdisplay = 480, 1274 .hsync_start = 480 + 2, 1275 .hsync_end = 480 + 2 + 41, 1276 .htotal = 480 + 2 + 41 + 2, 1277 .vdisplay = 272, 1278 .vsync_start = 272 + 2, 1279 .vsync_end = 272 + 2 + 10, 1280 .vtotal = 272 + 2 + 10 + 2, 1281 .vrefresh = 60, 1282 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1283 }; 1284 1285 static const struct panel_desc edt_etm0430g0dh6 = { 1286 .modes = &edt_etm0430g0dh6_mode, 1287 .num_modes = 1, 1288 .bpc = 6, 1289 .size = { 1290 .width = 95, 1291 .height = 54, 1292 }, 1293 }; 1294 1295 static const struct drm_display_mode edt_et057090dhu_mode = { 1296 .clock = 25175, 1297 .hdisplay = 640, 1298 .hsync_start = 640 + 16, 1299 .hsync_end = 640 + 16 + 30, 1300 .htotal = 640 + 16 + 30 + 114, 1301 .vdisplay = 480, 1302 .vsync_start = 480 + 10, 1303 .vsync_end = 480 + 10 + 3, 1304 .vtotal = 480 + 10 + 3 + 32, 1305 .vrefresh = 60, 1306 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1307 }; 1308 1309 static const struct panel_desc edt_et057090dhu = { 1310 .modes = &edt_et057090dhu_mode, 1311 .num_modes = 1, 1312 .bpc = 6, 1313 .size = { 1314 .width = 115, 1315 .height = 86, 1316 }, 1317 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1319 }; 1320 1321 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1322 .clock = 33260, 1323 .hdisplay = 800, 1324 .hsync_start = 800 + 40, 1325 .hsync_end = 800 + 40 + 128, 1326 .htotal = 800 + 40 + 128 + 88, 1327 .vdisplay = 480, 1328 .vsync_start = 480 + 10, 1329 .vsync_end = 480 + 10 + 2, 1330 .vtotal = 480 + 10 + 2 + 33, 1331 .vrefresh = 60, 1332 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1333 }; 1334 1335 static const struct panel_desc edt_etm0700g0dh6 = { 1336 .modes = &edt_etm0700g0dh6_mode, 1337 .num_modes = 1, 1338 .bpc = 6, 1339 .size = { 1340 .width = 152, 1341 .height = 91, 1342 }, 1343 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1344 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1345 }; 1346 1347 static const struct panel_desc edt_etm0700g0bdh6 = { 1348 .modes = &edt_etm0700g0dh6_mode, 1349 .num_modes = 1, 1350 .bpc = 6, 1351 .size = { 1352 .width = 152, 1353 .height = 91, 1354 }, 1355 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1356 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1357 }; 1358 1359 static const struct display_timing evervision_vgg804821_timing = { 1360 .pixelclock = { 27600000, 33300000, 50000000 }, 1361 .hactive = { 800, 800, 800 }, 1362 .hfront_porch = { 40, 66, 70 }, 1363 .hback_porch = { 40, 67, 70 }, 1364 .hsync_len = { 40, 67, 70 }, 1365 .vactive = { 480, 480, 480 }, 1366 .vfront_porch = { 6, 10, 10 }, 1367 .vback_porch = { 7, 11, 11 }, 1368 .vsync_len = { 7, 11, 11 }, 1369 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1370 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1371 DISPLAY_FLAGS_SYNC_NEGEDGE, 1372 }; 1373 1374 static const struct panel_desc evervision_vgg804821 = { 1375 .timings = &evervision_vgg804821_timing, 1376 .num_timings = 1, 1377 .bpc = 8, 1378 .size = { 1379 .width = 108, 1380 .height = 64, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1384 }; 1385 1386 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1387 .clock = 32260, 1388 .hdisplay = 800, 1389 .hsync_start = 800 + 168, 1390 .hsync_end = 800 + 168 + 64, 1391 .htotal = 800 + 168 + 64 + 88, 1392 .vdisplay = 480, 1393 .vsync_start = 480 + 37, 1394 .vsync_end = 480 + 37 + 2, 1395 .vtotal = 480 + 37 + 2 + 8, 1396 .vrefresh = 60, 1397 }; 1398 1399 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1400 .modes = &foxlink_fl500wvr00_a0t_mode, 1401 .num_modes = 1, 1402 .bpc = 8, 1403 .size = { 1404 .width = 108, 1405 .height = 65, 1406 }, 1407 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1408 }; 1409 1410 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1411 .clock = 67185, 1412 .hdisplay = 800, 1413 .hsync_start = 800 + 20, 1414 .hsync_end = 800 + 20 + 24, 1415 .htotal = 800 + 20 + 24 + 20, 1416 .vdisplay = 1280, 1417 .vsync_start = 1280 + 4, 1418 .vsync_end = 1280 + 4 + 8, 1419 .vtotal = 1280 + 4 + 8 + 4, 1420 .vrefresh = 60, 1421 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1422 }; 1423 1424 static const struct panel_desc friendlyarm_hd702e = { 1425 .modes = &friendlyarm_hd702e_mode, 1426 .num_modes = 1, 1427 .size = { 1428 .width = 94, 1429 .height = 151, 1430 }, 1431 }; 1432 1433 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1434 .clock = 9000, 1435 .hdisplay = 480, 1436 .hsync_start = 480 + 5, 1437 .hsync_end = 480 + 5 + 1, 1438 .htotal = 480 + 5 + 1 + 40, 1439 .vdisplay = 272, 1440 .vsync_start = 272 + 8, 1441 .vsync_end = 272 + 8 + 1, 1442 .vtotal = 272 + 8 + 1 + 8, 1443 .vrefresh = 60, 1444 }; 1445 1446 static const struct panel_desc giantplus_gpg482739qs5 = { 1447 .modes = &giantplus_gpg482739qs5_mode, 1448 .num_modes = 1, 1449 .bpc = 8, 1450 .size = { 1451 .width = 95, 1452 .height = 54, 1453 }, 1454 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1455 }; 1456 1457 static const struct display_timing giantplus_gpm940b0_timing = { 1458 .pixelclock = { 13500000, 27000000, 27500000 }, 1459 .hactive = { 320, 320, 320 }, 1460 .hfront_porch = { 14, 686, 718 }, 1461 .hback_porch = { 50, 70, 255 }, 1462 .hsync_len = { 1, 1, 1 }, 1463 .vactive = { 240, 240, 240 }, 1464 .vfront_porch = { 1, 1, 179 }, 1465 .vback_porch = { 1, 21, 31 }, 1466 .vsync_len = { 1, 1, 6 }, 1467 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1468 }; 1469 1470 static const struct panel_desc giantplus_gpm940b0 = { 1471 .timings = &giantplus_gpm940b0_timing, 1472 .num_timings = 1, 1473 .bpc = 8, 1474 .size = { 1475 .width = 60, 1476 .height = 45, 1477 }, 1478 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1479 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1480 }; 1481 1482 static const struct display_timing hannstar_hsd070pww1_timing = { 1483 .pixelclock = { 64300000, 71100000, 82000000 }, 1484 .hactive = { 1280, 1280, 1280 }, 1485 .hfront_porch = { 1, 1, 10 }, 1486 .hback_porch = { 1, 1, 10 }, 1487 /* 1488 * According to the data sheet, the minimum horizontal blanking interval 1489 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1490 * minimum working horizontal blanking interval to be 60 clocks. 1491 */ 1492 .hsync_len = { 58, 158, 661 }, 1493 .vactive = { 800, 800, 800 }, 1494 .vfront_porch = { 1, 1, 10 }, 1495 .vback_porch = { 1, 1, 10 }, 1496 .vsync_len = { 1, 21, 203 }, 1497 .flags = DISPLAY_FLAGS_DE_HIGH, 1498 }; 1499 1500 static const struct panel_desc hannstar_hsd070pww1 = { 1501 .timings = &hannstar_hsd070pww1_timing, 1502 .num_timings = 1, 1503 .bpc = 6, 1504 .size = { 1505 .width = 151, 1506 .height = 94, 1507 }, 1508 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510 }; 1511 1512 static const struct display_timing hannstar_hsd100pxn1_timing = { 1513 .pixelclock = { 55000000, 65000000, 75000000 }, 1514 .hactive = { 1024, 1024, 1024 }, 1515 .hfront_porch = { 40, 40, 40 }, 1516 .hback_porch = { 220, 220, 220 }, 1517 .hsync_len = { 20, 60, 100 }, 1518 .vactive = { 768, 768, 768 }, 1519 .vfront_porch = { 7, 7, 7 }, 1520 .vback_porch = { 21, 21, 21 }, 1521 .vsync_len = { 10, 10, 10 }, 1522 .flags = DISPLAY_FLAGS_DE_HIGH, 1523 }; 1524 1525 static const struct panel_desc hannstar_hsd100pxn1 = { 1526 .timings = &hannstar_hsd100pxn1_timing, 1527 .num_timings = 1, 1528 .bpc = 6, 1529 .size = { 1530 .width = 203, 1531 .height = 152, 1532 }, 1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535 }; 1536 1537 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1538 .clock = 33333, 1539 .hdisplay = 800, 1540 .hsync_start = 800 + 85, 1541 .hsync_end = 800 + 85 + 86, 1542 .htotal = 800 + 85 + 86 + 85, 1543 .vdisplay = 480, 1544 .vsync_start = 480 + 16, 1545 .vsync_end = 480 + 16 + 13, 1546 .vtotal = 480 + 16 + 13 + 16, 1547 .vrefresh = 60, 1548 }; 1549 1550 static const struct panel_desc hitachi_tx23d38vm0caa = { 1551 .modes = &hitachi_tx23d38vm0caa_mode, 1552 .num_modes = 1, 1553 .bpc = 6, 1554 .size = { 1555 .width = 195, 1556 .height = 117, 1557 }, 1558 .delay = { 1559 .enable = 160, 1560 .disable = 160, 1561 }, 1562 }; 1563 1564 static const struct drm_display_mode innolux_at043tn24_mode = { 1565 .clock = 9000, 1566 .hdisplay = 480, 1567 .hsync_start = 480 + 2, 1568 .hsync_end = 480 + 2 + 41, 1569 .htotal = 480 + 2 + 41 + 2, 1570 .vdisplay = 272, 1571 .vsync_start = 272 + 2, 1572 .vsync_end = 272 + 2 + 10, 1573 .vtotal = 272 + 2 + 10 + 2, 1574 .vrefresh = 60, 1575 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1576 }; 1577 1578 static const struct panel_desc innolux_at043tn24 = { 1579 .modes = &innolux_at043tn24_mode, 1580 .num_modes = 1, 1581 .bpc = 8, 1582 .size = { 1583 .width = 95, 1584 .height = 54, 1585 }, 1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1588 }; 1589 1590 static const struct drm_display_mode innolux_at070tn92_mode = { 1591 .clock = 33333, 1592 .hdisplay = 800, 1593 .hsync_start = 800 + 210, 1594 .hsync_end = 800 + 210 + 20, 1595 .htotal = 800 + 210 + 20 + 46, 1596 .vdisplay = 480, 1597 .vsync_start = 480 + 22, 1598 .vsync_end = 480 + 22 + 10, 1599 .vtotal = 480 + 22 + 23 + 10, 1600 .vrefresh = 60, 1601 }; 1602 1603 static const struct panel_desc innolux_at070tn92 = { 1604 .modes = &innolux_at070tn92_mode, 1605 .num_modes = 1, 1606 .size = { 1607 .width = 154, 1608 .height = 86, 1609 }, 1610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1611 }; 1612 1613 static const struct display_timing innolux_g070y2_l01_timing = { 1614 .pixelclock = { 28000000, 29500000, 32000000 }, 1615 .hactive = { 800, 800, 800 }, 1616 .hfront_porch = { 61, 91, 141 }, 1617 .hback_porch = { 60, 90, 140 }, 1618 .hsync_len = { 12, 12, 12 }, 1619 .vactive = { 480, 480, 480 }, 1620 .vfront_porch = { 4, 9, 30 }, 1621 .vback_porch = { 4, 8, 28 }, 1622 .vsync_len = { 2, 2, 2 }, 1623 .flags = DISPLAY_FLAGS_DE_HIGH, 1624 }; 1625 1626 static const struct panel_desc innolux_g070y2_l01 = { 1627 .timings = &innolux_g070y2_l01_timing, 1628 .num_timings = 1, 1629 .bpc = 6, 1630 .size = { 1631 .width = 152, 1632 .height = 91, 1633 }, 1634 .delay = { 1635 .prepare = 10, 1636 .enable = 100, 1637 .disable = 100, 1638 .unprepare = 800, 1639 }, 1640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1642 }; 1643 1644 static const struct display_timing innolux_g101ice_l01_timing = { 1645 .pixelclock = { 60400000, 71100000, 74700000 }, 1646 .hactive = { 1280, 1280, 1280 }, 1647 .hfront_porch = { 41, 80, 100 }, 1648 .hback_porch = { 40, 79, 99 }, 1649 .hsync_len = { 1, 1, 1 }, 1650 .vactive = { 800, 800, 800 }, 1651 .vfront_porch = { 5, 11, 14 }, 1652 .vback_porch = { 4, 11, 14 }, 1653 .vsync_len = { 1, 1, 1 }, 1654 .flags = DISPLAY_FLAGS_DE_HIGH, 1655 }; 1656 1657 static const struct panel_desc innolux_g101ice_l01 = { 1658 .timings = &innolux_g101ice_l01_timing, 1659 .num_timings = 1, 1660 .bpc = 8, 1661 .size = { 1662 .width = 217, 1663 .height = 135, 1664 }, 1665 .delay = { 1666 .enable = 200, 1667 .disable = 200, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1670 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1671 }; 1672 1673 static const struct display_timing innolux_g121i1_l01_timing = { 1674 .pixelclock = { 67450000, 71000000, 74550000 }, 1675 .hactive = { 1280, 1280, 1280 }, 1676 .hfront_porch = { 40, 80, 160 }, 1677 .hback_porch = { 39, 79, 159 }, 1678 .hsync_len = { 1, 1, 1 }, 1679 .vactive = { 800, 800, 800 }, 1680 .vfront_porch = { 5, 11, 100 }, 1681 .vback_porch = { 4, 11, 99 }, 1682 .vsync_len = { 1, 1, 1 }, 1683 }; 1684 1685 static const struct panel_desc innolux_g121i1_l01 = { 1686 .timings = &innolux_g121i1_l01_timing, 1687 .num_timings = 1, 1688 .bpc = 6, 1689 .size = { 1690 .width = 261, 1691 .height = 163, 1692 }, 1693 .delay = { 1694 .enable = 200, 1695 .disable = 20, 1696 }, 1697 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1698 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1699 }; 1700 1701 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1702 .clock = 65000, 1703 .hdisplay = 1024, 1704 .hsync_start = 1024 + 0, 1705 .hsync_end = 1024 + 1, 1706 .htotal = 1024 + 0 + 1 + 320, 1707 .vdisplay = 768, 1708 .vsync_start = 768 + 38, 1709 .vsync_end = 768 + 38 + 1, 1710 .vtotal = 768 + 38 + 1 + 0, 1711 .vrefresh = 60, 1712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1713 }; 1714 1715 static const struct panel_desc innolux_g121x1_l03 = { 1716 .modes = &innolux_g121x1_l03_mode, 1717 .num_modes = 1, 1718 .bpc = 6, 1719 .size = { 1720 .width = 246, 1721 .height = 185, 1722 }, 1723 .delay = { 1724 .enable = 200, 1725 .unprepare = 200, 1726 .disable = 400, 1727 }, 1728 }; 1729 1730 /* 1731 * Datasheet specifies that at 60 Hz refresh rate: 1732 * - total horizontal time: { 1506, 1592, 1716 } 1733 * - total vertical time: { 788, 800, 868 } 1734 * 1735 * ...but doesn't go into exactly how that should be split into a front 1736 * porch, back porch, or sync length. For now we'll leave a single setting 1737 * here which allows a bit of tweaking of the pixel clock at the expense of 1738 * refresh rate. 1739 */ 1740 static const struct display_timing innolux_n116bge_timing = { 1741 .pixelclock = { 72600000, 76420000, 80240000 }, 1742 .hactive = { 1366, 1366, 1366 }, 1743 .hfront_porch = { 136, 136, 136 }, 1744 .hback_porch = { 60, 60, 60 }, 1745 .hsync_len = { 30, 30, 30 }, 1746 .vactive = { 768, 768, 768 }, 1747 .vfront_porch = { 8, 8, 8 }, 1748 .vback_porch = { 12, 12, 12 }, 1749 .vsync_len = { 12, 12, 12 }, 1750 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 1751 }; 1752 1753 static const struct panel_desc innolux_n116bge = { 1754 .timings = &innolux_n116bge_timing, 1755 .num_timings = 1, 1756 .bpc = 6, 1757 .size = { 1758 .width = 256, 1759 .height = 144, 1760 }, 1761 }; 1762 1763 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1764 .clock = 69300, 1765 .hdisplay = 1366, 1766 .hsync_start = 1366 + 16, 1767 .hsync_end = 1366 + 16 + 34, 1768 .htotal = 1366 + 16 + 34 + 50, 1769 .vdisplay = 768, 1770 .vsync_start = 768 + 2, 1771 .vsync_end = 768 + 2 + 6, 1772 .vtotal = 768 + 2 + 6 + 12, 1773 .vrefresh = 60, 1774 }; 1775 1776 static const struct panel_desc innolux_n156bge_l21 = { 1777 .modes = &innolux_n156bge_l21_mode, 1778 .num_modes = 1, 1779 .bpc = 6, 1780 .size = { 1781 .width = 344, 1782 .height = 193, 1783 }, 1784 }; 1785 1786 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1787 .clock = 206016, 1788 .hdisplay = 2160, 1789 .hsync_start = 2160 + 48, 1790 .hsync_end = 2160 + 48 + 32, 1791 .htotal = 2160 + 48 + 32 + 80, 1792 .vdisplay = 1440, 1793 .vsync_start = 1440 + 3, 1794 .vsync_end = 1440 + 3 + 10, 1795 .vtotal = 1440 + 3 + 10 + 27, 1796 .vrefresh = 60, 1797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1798 }; 1799 1800 static const struct panel_desc innolux_p120zdg_bf1 = { 1801 .modes = &innolux_p120zdg_bf1_mode, 1802 .num_modes = 1, 1803 .bpc = 8, 1804 .size = { 1805 .width = 254, 1806 .height = 169, 1807 }, 1808 .delay = { 1809 .hpd_absent_delay = 200, 1810 .unprepare = 500, 1811 }, 1812 }; 1813 1814 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1815 .clock = 51501, 1816 .hdisplay = 1024, 1817 .hsync_start = 1024 + 128, 1818 .hsync_end = 1024 + 128 + 64, 1819 .htotal = 1024 + 128 + 64 + 128, 1820 .vdisplay = 600, 1821 .vsync_start = 600 + 16, 1822 .vsync_end = 600 + 16 + 4, 1823 .vtotal = 600 + 16 + 4 + 16, 1824 .vrefresh = 60, 1825 }; 1826 1827 static const struct panel_desc innolux_zj070na_01p = { 1828 .modes = &innolux_zj070na_01p_mode, 1829 .num_modes = 1, 1830 .bpc = 6, 1831 .size = { 1832 .width = 154, 1833 .height = 90, 1834 }, 1835 }; 1836 1837 static const struct display_timing koe_tx14d24vm1bpa_timing = { 1838 .pixelclock = { 5580000, 5850000, 6200000 }, 1839 .hactive = { 320, 320, 320 }, 1840 .hfront_porch = { 30, 30, 30 }, 1841 .hback_porch = { 30, 30, 30 }, 1842 .hsync_len = { 1, 5, 17 }, 1843 .vactive = { 240, 240, 240 }, 1844 .vfront_porch = { 6, 6, 6 }, 1845 .vback_porch = { 5, 5, 5 }, 1846 .vsync_len = { 1, 2, 11 }, 1847 .flags = DISPLAY_FLAGS_DE_HIGH, 1848 }; 1849 1850 static const struct panel_desc koe_tx14d24vm1bpa = { 1851 .timings = &koe_tx14d24vm1bpa_timing, 1852 .num_timings = 1, 1853 .bpc = 6, 1854 .size = { 1855 .width = 115, 1856 .height = 86, 1857 }, 1858 }; 1859 1860 static const struct display_timing koe_tx31d200vm0baa_timing = { 1861 .pixelclock = { 39600000, 43200000, 48000000 }, 1862 .hactive = { 1280, 1280, 1280 }, 1863 .hfront_porch = { 16, 36, 56 }, 1864 .hback_porch = { 16, 36, 56 }, 1865 .hsync_len = { 8, 8, 8 }, 1866 .vactive = { 480, 480, 480 }, 1867 .vfront_porch = { 6, 21, 33 }, 1868 .vback_porch = { 6, 21, 33 }, 1869 .vsync_len = { 8, 8, 8 }, 1870 .flags = DISPLAY_FLAGS_DE_HIGH, 1871 }; 1872 1873 static const struct panel_desc koe_tx31d200vm0baa = { 1874 .timings = &koe_tx31d200vm0baa_timing, 1875 .num_timings = 1, 1876 .bpc = 6, 1877 .size = { 1878 .width = 292, 1879 .height = 109, 1880 }, 1881 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1883 }; 1884 1885 static const struct display_timing kyo_tcg121xglp_timing = { 1886 .pixelclock = { 52000000, 65000000, 71000000 }, 1887 .hactive = { 1024, 1024, 1024 }, 1888 .hfront_porch = { 2, 2, 2 }, 1889 .hback_porch = { 2, 2, 2 }, 1890 .hsync_len = { 86, 124, 244 }, 1891 .vactive = { 768, 768, 768 }, 1892 .vfront_porch = { 2, 2, 2 }, 1893 .vback_porch = { 2, 2, 2 }, 1894 .vsync_len = { 6, 34, 73 }, 1895 .flags = DISPLAY_FLAGS_DE_HIGH, 1896 }; 1897 1898 static const struct panel_desc kyo_tcg121xglp = { 1899 .timings = &kyo_tcg121xglp_timing, 1900 .num_timings = 1, 1901 .bpc = 8, 1902 .size = { 1903 .width = 246, 1904 .height = 184, 1905 }, 1906 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1908 }; 1909 1910 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 1911 .clock = 7000, 1912 .hdisplay = 320, 1913 .hsync_start = 320 + 20, 1914 .hsync_end = 320 + 20 + 30, 1915 .htotal = 320 + 20 + 30 + 38, 1916 .vdisplay = 240, 1917 .vsync_start = 240 + 4, 1918 .vsync_end = 240 + 4 + 3, 1919 .vtotal = 240 + 4 + 3 + 15, 1920 .vrefresh = 60, 1921 }; 1922 1923 static const struct panel_desc lemaker_bl035_rgb_002 = { 1924 .modes = &lemaker_bl035_rgb_002_mode, 1925 .num_modes = 1, 1926 .size = { 1927 .width = 70, 1928 .height = 52, 1929 }, 1930 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1931 .bus_flags = DRM_BUS_FLAG_DE_LOW, 1932 }; 1933 1934 static const struct drm_display_mode lg_lb070wv8_mode = { 1935 .clock = 33246, 1936 .hdisplay = 800, 1937 .hsync_start = 800 + 88, 1938 .hsync_end = 800 + 88 + 80, 1939 .htotal = 800 + 88 + 80 + 88, 1940 .vdisplay = 480, 1941 .vsync_start = 480 + 10, 1942 .vsync_end = 480 + 10 + 25, 1943 .vtotal = 480 + 10 + 25 + 10, 1944 .vrefresh = 60, 1945 }; 1946 1947 static const struct panel_desc lg_lb070wv8 = { 1948 .modes = &lg_lb070wv8_mode, 1949 .num_modes = 1, 1950 .bpc = 16, 1951 .size = { 1952 .width = 151, 1953 .height = 91, 1954 }, 1955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1956 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1957 }; 1958 1959 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1960 .clock = 200000, 1961 .hdisplay = 1536, 1962 .hsync_start = 1536 + 12, 1963 .hsync_end = 1536 + 12 + 16, 1964 .htotal = 1536 + 12 + 16 + 48, 1965 .vdisplay = 2048, 1966 .vsync_start = 2048 + 8, 1967 .vsync_end = 2048 + 8 + 4, 1968 .vtotal = 2048 + 8 + 4 + 8, 1969 .vrefresh = 60, 1970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1971 }; 1972 1973 static const struct panel_desc lg_lp079qx1_sp0v = { 1974 .modes = &lg_lp079qx1_sp0v_mode, 1975 .num_modes = 1, 1976 .size = { 1977 .width = 129, 1978 .height = 171, 1979 }, 1980 }; 1981 1982 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1983 .clock = 205210, 1984 .hdisplay = 2048, 1985 .hsync_start = 2048 + 150, 1986 .hsync_end = 2048 + 150 + 5, 1987 .htotal = 2048 + 150 + 5 + 5, 1988 .vdisplay = 1536, 1989 .vsync_start = 1536 + 3, 1990 .vsync_end = 1536 + 3 + 1, 1991 .vtotal = 1536 + 3 + 1 + 9, 1992 .vrefresh = 60, 1993 }; 1994 1995 static const struct panel_desc lg_lp097qx1_spa1 = { 1996 .modes = &lg_lp097qx1_spa1_mode, 1997 .num_modes = 1, 1998 .size = { 1999 .width = 208, 2000 .height = 147, 2001 }, 2002 }; 2003 2004 static const struct drm_display_mode lg_lp120up1_mode = { 2005 .clock = 162300, 2006 .hdisplay = 1920, 2007 .hsync_start = 1920 + 40, 2008 .hsync_end = 1920 + 40 + 40, 2009 .htotal = 1920 + 40 + 40+ 80, 2010 .vdisplay = 1280, 2011 .vsync_start = 1280 + 4, 2012 .vsync_end = 1280 + 4 + 4, 2013 .vtotal = 1280 + 4 + 4 + 12, 2014 .vrefresh = 60, 2015 }; 2016 2017 static const struct panel_desc lg_lp120up1 = { 2018 .modes = &lg_lp120up1_mode, 2019 .num_modes = 1, 2020 .bpc = 8, 2021 .size = { 2022 .width = 267, 2023 .height = 183, 2024 }, 2025 }; 2026 2027 static const struct drm_display_mode lg_lp129qe_mode = { 2028 .clock = 285250, 2029 .hdisplay = 2560, 2030 .hsync_start = 2560 + 48, 2031 .hsync_end = 2560 + 48 + 32, 2032 .htotal = 2560 + 48 + 32 + 80, 2033 .vdisplay = 1700, 2034 .vsync_start = 1700 + 3, 2035 .vsync_end = 1700 + 3 + 10, 2036 .vtotal = 1700 + 3 + 10 + 36, 2037 .vrefresh = 60, 2038 }; 2039 2040 static const struct panel_desc lg_lp129qe = { 2041 .modes = &lg_lp129qe_mode, 2042 .num_modes = 1, 2043 .bpc = 8, 2044 .size = { 2045 .width = 272, 2046 .height = 181, 2047 }, 2048 }; 2049 2050 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2051 .clock = 30400, 2052 .hdisplay = 800, 2053 .hsync_start = 800 + 0, 2054 .hsync_end = 800 + 1, 2055 .htotal = 800 + 0 + 1 + 160, 2056 .vdisplay = 480, 2057 .vsync_start = 480 + 0, 2058 .vsync_end = 480 + 48 + 1, 2059 .vtotal = 480 + 48 + 1 + 0, 2060 .vrefresh = 60, 2061 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2062 }; 2063 2064 static const struct panel_desc mitsubishi_aa070mc01 = { 2065 .modes = &mitsubishi_aa070mc01_mode, 2066 .num_modes = 1, 2067 .bpc = 8, 2068 .size = { 2069 .width = 152, 2070 .height = 91, 2071 }, 2072 2073 .delay = { 2074 .enable = 200, 2075 .unprepare = 200, 2076 .disable = 400, 2077 }, 2078 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2079 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2081 }; 2082 2083 static const struct display_timing nec_nl12880bc20_05_timing = { 2084 .pixelclock = { 67000000, 71000000, 75000000 }, 2085 .hactive = { 1280, 1280, 1280 }, 2086 .hfront_porch = { 2, 30, 30 }, 2087 .hback_porch = { 6, 100, 100 }, 2088 .hsync_len = { 2, 30, 30 }, 2089 .vactive = { 800, 800, 800 }, 2090 .vfront_porch = { 5, 5, 5 }, 2091 .vback_porch = { 11, 11, 11 }, 2092 .vsync_len = { 7, 7, 7 }, 2093 }; 2094 2095 static const struct panel_desc nec_nl12880bc20_05 = { 2096 .timings = &nec_nl12880bc20_05_timing, 2097 .num_timings = 1, 2098 .bpc = 8, 2099 .size = { 2100 .width = 261, 2101 .height = 163, 2102 }, 2103 .delay = { 2104 .enable = 50, 2105 .disable = 50, 2106 }, 2107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2108 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2109 }; 2110 2111 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2112 .clock = 10870, 2113 .hdisplay = 480, 2114 .hsync_start = 480 + 2, 2115 .hsync_end = 480 + 2 + 41, 2116 .htotal = 480 + 2 + 41 + 2, 2117 .vdisplay = 272, 2118 .vsync_start = 272 + 2, 2119 .vsync_end = 272 + 2 + 4, 2120 .vtotal = 272 + 2 + 4 + 2, 2121 .vrefresh = 74, 2122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2123 }; 2124 2125 static const struct panel_desc nec_nl4827hc19_05b = { 2126 .modes = &nec_nl4827hc19_05b_mode, 2127 .num_modes = 1, 2128 .bpc = 8, 2129 .size = { 2130 .width = 95, 2131 .height = 54, 2132 }, 2133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2134 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2135 }; 2136 2137 static const struct drm_display_mode netron_dy_e231732_mode = { 2138 .clock = 66000, 2139 .hdisplay = 1024, 2140 .hsync_start = 1024 + 160, 2141 .hsync_end = 1024 + 160 + 70, 2142 .htotal = 1024 + 160 + 70 + 90, 2143 .vdisplay = 600, 2144 .vsync_start = 600 + 127, 2145 .vsync_end = 600 + 127 + 20, 2146 .vtotal = 600 + 127 + 20 + 3, 2147 .vrefresh = 60, 2148 }; 2149 2150 static const struct panel_desc netron_dy_e231732 = { 2151 .modes = &netron_dy_e231732_mode, 2152 .num_modes = 1, 2153 .size = { 2154 .width = 154, 2155 .height = 87, 2156 }, 2157 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2158 }; 2159 2160 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2161 .clock = 9000, 2162 .hdisplay = 480, 2163 .hsync_start = 480 + 2, 2164 .hsync_end = 480 + 2 + 41, 2165 .htotal = 480 + 2 + 41 + 2, 2166 .vdisplay = 272, 2167 .vsync_start = 272 + 2, 2168 .vsync_end = 272 + 2 + 10, 2169 .vtotal = 272 + 2 + 10 + 2, 2170 .vrefresh = 60, 2171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2172 }; 2173 2174 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2175 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2176 .num_modes = 1, 2177 .bpc = 8, 2178 .size = { 2179 .width = 95, 2180 .height = 54, 2181 }, 2182 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2184 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2185 }; 2186 2187 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2188 .pixelclock = { 130000000, 148350000, 163000000 }, 2189 .hactive = { 1920, 1920, 1920 }, 2190 .hfront_porch = { 80, 100, 100 }, 2191 .hback_porch = { 100, 120, 120 }, 2192 .hsync_len = { 50, 60, 60 }, 2193 .vactive = { 1080, 1080, 1080 }, 2194 .vfront_porch = { 12, 30, 30 }, 2195 .vback_porch = { 4, 10, 10 }, 2196 .vsync_len = { 4, 5, 5 }, 2197 }; 2198 2199 static const struct panel_desc nlt_nl192108ac18_02d = { 2200 .timings = &nlt_nl192108ac18_02d_timing, 2201 .num_timings = 1, 2202 .bpc = 8, 2203 .size = { 2204 .width = 344, 2205 .height = 194, 2206 }, 2207 .delay = { 2208 .unprepare = 500, 2209 }, 2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2211 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2212 }; 2213 2214 static const struct drm_display_mode nvd_9128_mode = { 2215 .clock = 29500, 2216 .hdisplay = 800, 2217 .hsync_start = 800 + 130, 2218 .hsync_end = 800 + 130 + 98, 2219 .htotal = 800 + 0 + 130 + 98, 2220 .vdisplay = 480, 2221 .vsync_start = 480 + 10, 2222 .vsync_end = 480 + 10 + 50, 2223 .vtotal = 480 + 0 + 10 + 50, 2224 }; 2225 2226 static const struct panel_desc nvd_9128 = { 2227 .modes = &nvd_9128_mode, 2228 .num_modes = 1, 2229 .bpc = 8, 2230 .size = { 2231 .width = 156, 2232 .height = 88, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2235 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2236 }; 2237 2238 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2239 .pixelclock = { 30000000, 30000000, 40000000 }, 2240 .hactive = { 800, 800, 800 }, 2241 .hfront_porch = { 40, 40, 40 }, 2242 .hback_porch = { 40, 40, 40 }, 2243 .hsync_len = { 1, 48, 48 }, 2244 .vactive = { 480, 480, 480 }, 2245 .vfront_porch = { 13, 13, 13 }, 2246 .vback_porch = { 29, 29, 29 }, 2247 .vsync_len = { 3, 3, 3 }, 2248 .flags = DISPLAY_FLAGS_DE_HIGH, 2249 }; 2250 2251 static const struct panel_desc okaya_rs800480t_7x0gp = { 2252 .timings = &okaya_rs800480t_7x0gp_timing, 2253 .num_timings = 1, 2254 .bpc = 6, 2255 .size = { 2256 .width = 154, 2257 .height = 87, 2258 }, 2259 .delay = { 2260 .prepare = 41, 2261 .enable = 50, 2262 .unprepare = 41, 2263 .disable = 50, 2264 }, 2265 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2266 }; 2267 2268 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2269 .clock = 9000, 2270 .hdisplay = 480, 2271 .hsync_start = 480 + 5, 2272 .hsync_end = 480 + 5 + 30, 2273 .htotal = 480 + 5 + 30 + 10, 2274 .vdisplay = 272, 2275 .vsync_start = 272 + 8, 2276 .vsync_end = 272 + 8 + 5, 2277 .vtotal = 272 + 8 + 5 + 3, 2278 .vrefresh = 60, 2279 }; 2280 2281 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2282 .modes = &olimex_lcd_olinuxino_43ts_mode, 2283 .num_modes = 1, 2284 .size = { 2285 .width = 95, 2286 .height = 54, 2287 }, 2288 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2289 }; 2290 2291 /* 2292 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2293 * pixel clocks, but this is the timing that was being used in the Adafruit 2294 * installation instructions. 2295 */ 2296 static const struct drm_display_mode ontat_yx700wv03_mode = { 2297 .clock = 29500, 2298 .hdisplay = 800, 2299 .hsync_start = 824, 2300 .hsync_end = 896, 2301 .htotal = 992, 2302 .vdisplay = 480, 2303 .vsync_start = 483, 2304 .vsync_end = 493, 2305 .vtotal = 500, 2306 .vrefresh = 60, 2307 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2308 }; 2309 2310 /* 2311 * Specification at: 2312 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2313 */ 2314 static const struct panel_desc ontat_yx700wv03 = { 2315 .modes = &ontat_yx700wv03_mode, 2316 .num_modes = 1, 2317 .bpc = 8, 2318 .size = { 2319 .width = 154, 2320 .height = 83, 2321 }, 2322 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2323 }; 2324 2325 static const struct drm_display_mode ortustech_com37h3m_mode = { 2326 .clock = 22153, 2327 .hdisplay = 480, 2328 .hsync_start = 480 + 8, 2329 .hsync_end = 480 + 8 + 10, 2330 .htotal = 480 + 8 + 10 + 10, 2331 .vdisplay = 640, 2332 .vsync_start = 640 + 4, 2333 .vsync_end = 640 + 4 + 3, 2334 .vtotal = 640 + 4 + 3 + 4, 2335 .vrefresh = 60, 2336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2337 }; 2338 2339 static const struct panel_desc ortustech_com37h3m = { 2340 .modes = &ortustech_com37h3m_mode, 2341 .num_modes = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 56, /* 56.16mm */ 2345 .height = 75, /* 74.88mm */ 2346 }, 2347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2348 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2349 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2350 }; 2351 2352 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2353 .clock = 25000, 2354 .hdisplay = 480, 2355 .hsync_start = 480 + 10, 2356 .hsync_end = 480 + 10 + 10, 2357 .htotal = 480 + 10 + 10 + 15, 2358 .vdisplay = 800, 2359 .vsync_start = 800 + 3, 2360 .vsync_end = 800 + 3 + 3, 2361 .vtotal = 800 + 3 + 3 + 3, 2362 .vrefresh = 60, 2363 }; 2364 2365 static const struct panel_desc ortustech_com43h4m85ulc = { 2366 .modes = &ortustech_com43h4m85ulc_mode, 2367 .num_modes = 1, 2368 .bpc = 8, 2369 .size = { 2370 .width = 56, 2371 .height = 93, 2372 }, 2373 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2375 }; 2376 2377 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2378 .clock = 33000, 2379 .hdisplay = 800, 2380 .hsync_start = 800 + 210, 2381 .hsync_end = 800 + 210 + 30, 2382 .htotal = 800 + 210 + 30 + 16, 2383 .vdisplay = 480, 2384 .vsync_start = 480 + 22, 2385 .vsync_end = 480 + 22 + 13, 2386 .vtotal = 480 + 22 + 13 + 10, 2387 .vrefresh = 60, 2388 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2389 }; 2390 2391 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2392 .modes = &osddisplays_osd070t1718_19ts_mode, 2393 .num_modes = 1, 2394 .bpc = 8, 2395 .size = { 2396 .width = 152, 2397 .height = 91, 2398 }, 2399 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2400 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2401 .connector_type = DRM_MODE_CONNECTOR_DPI, 2402 }; 2403 2404 static const struct drm_display_mode pda_91_00156_a0_mode = { 2405 .clock = 33300, 2406 .hdisplay = 800, 2407 .hsync_start = 800 + 1, 2408 .hsync_end = 800 + 1 + 64, 2409 .htotal = 800 + 1 + 64 + 64, 2410 .vdisplay = 480, 2411 .vsync_start = 480 + 1, 2412 .vsync_end = 480 + 1 + 23, 2413 .vtotal = 480 + 1 + 23 + 22, 2414 .vrefresh = 60, 2415 }; 2416 2417 static const struct panel_desc pda_91_00156_a0 = { 2418 .modes = &pda_91_00156_a0_mode, 2419 .num_modes = 1, 2420 .size = { 2421 .width = 152, 2422 .height = 91, 2423 }, 2424 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2425 }; 2426 2427 2428 static const struct drm_display_mode qd43003c0_40_mode = { 2429 .clock = 9000, 2430 .hdisplay = 480, 2431 .hsync_start = 480 + 8, 2432 .hsync_end = 480 + 8 + 4, 2433 .htotal = 480 + 8 + 4 + 39, 2434 .vdisplay = 272, 2435 .vsync_start = 272 + 4, 2436 .vsync_end = 272 + 4 + 10, 2437 .vtotal = 272 + 4 + 10 + 2, 2438 .vrefresh = 60, 2439 }; 2440 2441 static const struct panel_desc qd43003c0_40 = { 2442 .modes = &qd43003c0_40_mode, 2443 .num_modes = 1, 2444 .bpc = 8, 2445 .size = { 2446 .width = 95, 2447 .height = 53, 2448 }, 2449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2450 }; 2451 2452 static const struct display_timing rocktech_rk070er9427_timing = { 2453 .pixelclock = { 26400000, 33300000, 46800000 }, 2454 .hactive = { 800, 800, 800 }, 2455 .hfront_porch = { 16, 210, 354 }, 2456 .hback_porch = { 46, 46, 46 }, 2457 .hsync_len = { 1, 1, 1 }, 2458 .vactive = { 480, 480, 480 }, 2459 .vfront_porch = { 7, 22, 147 }, 2460 .vback_porch = { 23, 23, 23 }, 2461 .vsync_len = { 1, 1, 1 }, 2462 .flags = DISPLAY_FLAGS_DE_HIGH, 2463 }; 2464 2465 static const struct panel_desc rocktech_rk070er9427 = { 2466 .timings = &rocktech_rk070er9427_timing, 2467 .num_timings = 1, 2468 .bpc = 6, 2469 .size = { 2470 .width = 154, 2471 .height = 86, 2472 }, 2473 .delay = { 2474 .prepare = 41, 2475 .enable = 50, 2476 .unprepare = 41, 2477 .disable = 50, 2478 }, 2479 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2480 }; 2481 2482 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2483 .clock = 271560, 2484 .hdisplay = 2560, 2485 .hsync_start = 2560 + 48, 2486 .hsync_end = 2560 + 48 + 32, 2487 .htotal = 2560 + 48 + 32 + 80, 2488 .vdisplay = 1600, 2489 .vsync_start = 1600 + 2, 2490 .vsync_end = 1600 + 2 + 5, 2491 .vtotal = 1600 + 2 + 5 + 57, 2492 .vrefresh = 60, 2493 }; 2494 2495 static const struct panel_desc samsung_lsn122dl01_c01 = { 2496 .modes = &samsung_lsn122dl01_c01_mode, 2497 .num_modes = 1, 2498 .size = { 2499 .width = 263, 2500 .height = 164, 2501 }, 2502 }; 2503 2504 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2505 .clock = 54030, 2506 .hdisplay = 1024, 2507 .hsync_start = 1024 + 24, 2508 .hsync_end = 1024 + 24 + 136, 2509 .htotal = 1024 + 24 + 136 + 160, 2510 .vdisplay = 600, 2511 .vsync_start = 600 + 3, 2512 .vsync_end = 600 + 3 + 6, 2513 .vtotal = 600 + 3 + 6 + 61, 2514 .vrefresh = 60, 2515 }; 2516 2517 static const struct panel_desc samsung_ltn101nt05 = { 2518 .modes = &samsung_ltn101nt05_mode, 2519 .num_modes = 1, 2520 .bpc = 6, 2521 .size = { 2522 .width = 223, 2523 .height = 125, 2524 }, 2525 }; 2526 2527 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2528 .clock = 76300, 2529 .hdisplay = 1366, 2530 .hsync_start = 1366 + 64, 2531 .hsync_end = 1366 + 64 + 48, 2532 .htotal = 1366 + 64 + 48 + 128, 2533 .vdisplay = 768, 2534 .vsync_start = 768 + 2, 2535 .vsync_end = 768 + 2 + 5, 2536 .vtotal = 768 + 2 + 5 + 17, 2537 .vrefresh = 60, 2538 }; 2539 2540 static const struct panel_desc samsung_ltn140at29_301 = { 2541 .modes = &samsung_ltn140at29_301_mode, 2542 .num_modes = 1, 2543 .bpc = 6, 2544 .size = { 2545 .width = 320, 2546 .height = 187, 2547 }, 2548 }; 2549 2550 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 2551 .clock = 168480, 2552 .hdisplay = 1920, 2553 .hsync_start = 1920 + 48, 2554 .hsync_end = 1920 + 48 + 32, 2555 .htotal = 1920 + 48 + 32 + 80, 2556 .vdisplay = 1280, 2557 .vsync_start = 1280 + 3, 2558 .vsync_end = 1280 + 3 + 10, 2559 .vtotal = 1280 + 3 + 10 + 57, 2560 .vrefresh = 60, 2561 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2562 }; 2563 2564 static const struct panel_desc sharp_ld_d5116z01b = { 2565 .modes = &sharp_ld_d5116z01b_mode, 2566 .num_modes = 1, 2567 .bpc = 8, 2568 .size = { 2569 .width = 260, 2570 .height = 120, 2571 }, 2572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2573 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2574 }; 2575 2576 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 2577 .clock = 33260, 2578 .hdisplay = 800, 2579 .hsync_start = 800 + 64, 2580 .hsync_end = 800 + 64 + 128, 2581 .htotal = 800 + 64 + 128 + 64, 2582 .vdisplay = 480, 2583 .vsync_start = 480 + 8, 2584 .vsync_end = 480 + 8 + 2, 2585 .vtotal = 480 + 8 + 2 + 35, 2586 .vrefresh = 60, 2587 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2588 }; 2589 2590 static const struct panel_desc sharp_lq070y3dg3b = { 2591 .modes = &sharp_lq070y3dg3b_mode, 2592 .num_modes = 1, 2593 .bpc = 8, 2594 .size = { 2595 .width = 152, /* 152.4mm */ 2596 .height = 91, /* 91.4mm */ 2597 }, 2598 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2599 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2600 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2601 }; 2602 2603 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2604 .clock = 5500, 2605 .hdisplay = 240, 2606 .hsync_start = 240 + 16, 2607 .hsync_end = 240 + 16 + 7, 2608 .htotal = 240 + 16 + 7 + 5, 2609 .vdisplay = 320, 2610 .vsync_start = 320 + 9, 2611 .vsync_end = 320 + 9 + 1, 2612 .vtotal = 320 + 9 + 1 + 7, 2613 .vrefresh = 60, 2614 }; 2615 2616 static const struct panel_desc sharp_lq035q7db03 = { 2617 .modes = &sharp_lq035q7db03_mode, 2618 .num_modes = 1, 2619 .bpc = 6, 2620 .size = { 2621 .width = 54, 2622 .height = 72, 2623 }, 2624 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2625 }; 2626 2627 static const struct display_timing sharp_lq101k1ly04_timing = { 2628 .pixelclock = { 60000000, 65000000, 80000000 }, 2629 .hactive = { 1280, 1280, 1280 }, 2630 .hfront_porch = { 20, 20, 20 }, 2631 .hback_porch = { 20, 20, 20 }, 2632 .hsync_len = { 10, 10, 10 }, 2633 .vactive = { 800, 800, 800 }, 2634 .vfront_porch = { 4, 4, 4 }, 2635 .vback_porch = { 4, 4, 4 }, 2636 .vsync_len = { 4, 4, 4 }, 2637 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2638 }; 2639 2640 static const struct panel_desc sharp_lq101k1ly04 = { 2641 .timings = &sharp_lq101k1ly04_timing, 2642 .num_timings = 1, 2643 .bpc = 8, 2644 .size = { 2645 .width = 217, 2646 .height = 136, 2647 }, 2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2649 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2650 }; 2651 2652 static const struct display_timing sharp_lq123p1jx31_timing = { 2653 .pixelclock = { 252750000, 252750000, 266604720 }, 2654 .hactive = { 2400, 2400, 2400 }, 2655 .hfront_porch = { 48, 48, 48 }, 2656 .hback_porch = { 80, 80, 84 }, 2657 .hsync_len = { 32, 32, 32 }, 2658 .vactive = { 1600, 1600, 1600 }, 2659 .vfront_porch = { 3, 3, 3 }, 2660 .vback_porch = { 33, 33, 120 }, 2661 .vsync_len = { 10, 10, 10 }, 2662 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2663 }; 2664 2665 static const struct panel_desc sharp_lq123p1jx31 = { 2666 .timings = &sharp_lq123p1jx31_timing, 2667 .num_timings = 1, 2668 .bpc = 8, 2669 .size = { 2670 .width = 259, 2671 .height = 173, 2672 }, 2673 .delay = { 2674 .prepare = 110, 2675 .enable = 50, 2676 .unprepare = 550, 2677 }, 2678 }; 2679 2680 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2681 .clock = 71100, 2682 .hdisplay = 1024, 2683 .hsync_start = 1024 + 168, 2684 .hsync_end = 1024 + 168 + 64, 2685 .htotal = 1024 + 168 + 64 + 88, 2686 .vdisplay = 768, 2687 .vsync_start = 768 + 37, 2688 .vsync_end = 768 + 37 + 2, 2689 .vtotal = 768 + 37 + 2 + 8, 2690 .vrefresh = 60, 2691 }; 2692 2693 static const struct panel_desc sharp_lq150x1lg11 = { 2694 .modes = &sharp_lq150x1lg11_mode, 2695 .num_modes = 1, 2696 .bpc = 6, 2697 .size = { 2698 .width = 304, 2699 .height = 228, 2700 }, 2701 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2702 }; 2703 2704 static const struct display_timing sharp_ls020b1dd01d_timing = { 2705 .pixelclock = { 2000000, 4200000, 5000000 }, 2706 .hactive = { 240, 240, 240 }, 2707 .hfront_porch = { 66, 66, 66 }, 2708 .hback_porch = { 1, 1, 1 }, 2709 .hsync_len = { 1, 1, 1 }, 2710 .vactive = { 160, 160, 160 }, 2711 .vfront_porch = { 52, 52, 52 }, 2712 .vback_porch = { 6, 6, 6 }, 2713 .vsync_len = { 10, 10, 10 }, 2714 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 2715 }; 2716 2717 static const struct panel_desc sharp_ls020b1dd01d = { 2718 .timings = &sharp_ls020b1dd01d_timing, 2719 .num_timings = 1, 2720 .bpc = 6, 2721 .size = { 2722 .width = 42, 2723 .height = 28, 2724 }, 2725 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH 2727 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 2728 | DRM_BUS_FLAG_SHARP_SIGNALS, 2729 }; 2730 2731 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2732 .clock = 33300, 2733 .hdisplay = 800, 2734 .hsync_start = 800 + 1, 2735 .hsync_end = 800 + 1 + 64, 2736 .htotal = 800 + 1 + 64 + 64, 2737 .vdisplay = 480, 2738 .vsync_start = 480 + 1, 2739 .vsync_end = 480 + 1 + 23, 2740 .vtotal = 480 + 1 + 23 + 22, 2741 .vrefresh = 60, 2742 }; 2743 2744 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2745 .modes = &shelly_sca07010_bfn_lnn_mode, 2746 .num_modes = 1, 2747 .size = { 2748 .width = 152, 2749 .height = 91, 2750 }, 2751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2752 }; 2753 2754 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2755 .clock = 147000, 2756 .hdisplay = 1920, 2757 .hsync_start = 1920 + 16, 2758 .hsync_end = 1920 + 16 + 16, 2759 .htotal = 1920 + 16 + 16 + 32, 2760 .vdisplay = 1200, 2761 .vsync_start = 1200 + 15, 2762 .vsync_end = 1200 + 15 + 2, 2763 .vtotal = 1200 + 15 + 2 + 18, 2764 .vrefresh = 60, 2765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2766 }; 2767 2768 static const struct panel_desc starry_kr122ea0sra = { 2769 .modes = &starry_kr122ea0sra_mode, 2770 .num_modes = 1, 2771 .size = { 2772 .width = 263, 2773 .height = 164, 2774 }, 2775 .delay = { 2776 .prepare = 10 + 200, 2777 .enable = 50, 2778 .unprepare = 10 + 500, 2779 }, 2780 }; 2781 2782 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 2783 .clock = 30000, 2784 .hdisplay = 800, 2785 .hsync_start = 800 + 39, 2786 .hsync_end = 800 + 39 + 47, 2787 .htotal = 800 + 39 + 47 + 39, 2788 .vdisplay = 480, 2789 .vsync_start = 480 + 13, 2790 .vsync_end = 480 + 13 + 2, 2791 .vtotal = 480 + 13 + 2 + 29, 2792 .vrefresh = 62, 2793 }; 2794 2795 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 2796 .modes = &tfc_s9700rtwv43tr_01b_mode, 2797 .num_modes = 1, 2798 .bpc = 8, 2799 .size = { 2800 .width = 155, 2801 .height = 90, 2802 }, 2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 2805 }; 2806 2807 static const struct display_timing tianma_tm070jdhg30_timing = { 2808 .pixelclock = { 62600000, 68200000, 78100000 }, 2809 .hactive = { 1280, 1280, 1280 }, 2810 .hfront_porch = { 15, 64, 159 }, 2811 .hback_porch = { 5, 5, 5 }, 2812 .hsync_len = { 1, 1, 256 }, 2813 .vactive = { 800, 800, 800 }, 2814 .vfront_porch = { 3, 40, 99 }, 2815 .vback_porch = { 2, 2, 2 }, 2816 .vsync_len = { 1, 1, 128 }, 2817 .flags = DISPLAY_FLAGS_DE_HIGH, 2818 }; 2819 2820 static const struct panel_desc tianma_tm070jdhg30 = { 2821 .timings = &tianma_tm070jdhg30_timing, 2822 .num_timings = 1, 2823 .bpc = 8, 2824 .size = { 2825 .width = 151, 2826 .height = 95, 2827 }, 2828 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2829 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2830 }; 2831 2832 static const struct display_timing tianma_tm070rvhg71_timing = { 2833 .pixelclock = { 27700000, 29200000, 39600000 }, 2834 .hactive = { 800, 800, 800 }, 2835 .hfront_porch = { 12, 40, 212 }, 2836 .hback_porch = { 88, 88, 88 }, 2837 .hsync_len = { 1, 1, 40 }, 2838 .vactive = { 480, 480, 480 }, 2839 .vfront_porch = { 1, 13, 88 }, 2840 .vback_porch = { 32, 32, 32 }, 2841 .vsync_len = { 1, 1, 3 }, 2842 .flags = DISPLAY_FLAGS_DE_HIGH, 2843 }; 2844 2845 static const struct panel_desc tianma_tm070rvhg71 = { 2846 .timings = &tianma_tm070rvhg71_timing, 2847 .num_timings = 1, 2848 .bpc = 8, 2849 .size = { 2850 .width = 154, 2851 .height = 86, 2852 }, 2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2854 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2855 }; 2856 2857 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 2858 { 2859 .clock = 10000, 2860 .hdisplay = 320, 2861 .hsync_start = 320 + 50, 2862 .hsync_end = 320 + 50 + 6, 2863 .htotal = 320 + 50 + 6 + 38, 2864 .vdisplay = 240, 2865 .vsync_start = 240 + 3, 2866 .vsync_end = 240 + 3 + 1, 2867 .vtotal = 240 + 3 + 1 + 17, 2868 .vrefresh = 60, 2869 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2870 }, 2871 }; 2872 2873 static const struct panel_desc ti_nspire_cx_lcd_panel = { 2874 .modes = ti_nspire_cx_lcd_mode, 2875 .num_modes = 1, 2876 .bpc = 8, 2877 .size = { 2878 .width = 65, 2879 .height = 49, 2880 }, 2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2882 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 2883 }; 2884 2885 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 2886 { 2887 .clock = 10000, 2888 .hdisplay = 320, 2889 .hsync_start = 320 + 6, 2890 .hsync_end = 320 + 6 + 6, 2891 .htotal = 320 + 6 + 6 + 6, 2892 .vdisplay = 240, 2893 .vsync_start = 240 + 0, 2894 .vsync_end = 240 + 0 + 1, 2895 .vtotal = 240 + 0 + 1 + 0, 2896 .vrefresh = 60, 2897 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2898 }, 2899 }; 2900 2901 static const struct panel_desc ti_nspire_classic_lcd_panel = { 2902 .modes = ti_nspire_classic_lcd_mode, 2903 .num_modes = 1, 2904 /* The grayscale panel has 8 bit for the color .. Y (black) */ 2905 .bpc = 8, 2906 .size = { 2907 .width = 71, 2908 .height = 53, 2909 }, 2910 /* This is the grayscale bus format */ 2911 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 2912 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 2913 }; 2914 2915 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 2916 .clock = 79500, 2917 .hdisplay = 1280, 2918 .hsync_start = 1280 + 192, 2919 .hsync_end = 1280 + 192 + 128, 2920 .htotal = 1280 + 192 + 128 + 64, 2921 .vdisplay = 768, 2922 .vsync_start = 768 + 20, 2923 .vsync_end = 768 + 20 + 7, 2924 .vtotal = 768 + 20 + 7 + 3, 2925 .vrefresh = 60, 2926 }; 2927 2928 static const struct panel_desc toshiba_lt089ac29000 = { 2929 .modes = &toshiba_lt089ac29000_mode, 2930 .num_modes = 1, 2931 .size = { 2932 .width = 194, 2933 .height = 116, 2934 }, 2935 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2937 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2938 }; 2939 2940 static const struct drm_display_mode tpk_f07a_0102_mode = { 2941 .clock = 33260, 2942 .hdisplay = 800, 2943 .hsync_start = 800 + 40, 2944 .hsync_end = 800 + 40 + 128, 2945 .htotal = 800 + 40 + 128 + 88, 2946 .vdisplay = 480, 2947 .vsync_start = 480 + 10, 2948 .vsync_end = 480 + 10 + 2, 2949 .vtotal = 480 + 10 + 2 + 33, 2950 .vrefresh = 60, 2951 }; 2952 2953 static const struct panel_desc tpk_f07a_0102 = { 2954 .modes = &tpk_f07a_0102_mode, 2955 .num_modes = 1, 2956 .size = { 2957 .width = 152, 2958 .height = 91, 2959 }, 2960 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2961 }; 2962 2963 static const struct drm_display_mode tpk_f10a_0102_mode = { 2964 .clock = 45000, 2965 .hdisplay = 1024, 2966 .hsync_start = 1024 + 176, 2967 .hsync_end = 1024 + 176 + 5, 2968 .htotal = 1024 + 176 + 5 + 88, 2969 .vdisplay = 600, 2970 .vsync_start = 600 + 20, 2971 .vsync_end = 600 + 20 + 5, 2972 .vtotal = 600 + 20 + 5 + 25, 2973 .vrefresh = 60, 2974 }; 2975 2976 static const struct panel_desc tpk_f10a_0102 = { 2977 .modes = &tpk_f10a_0102_mode, 2978 .num_modes = 1, 2979 .size = { 2980 .width = 223, 2981 .height = 125, 2982 }, 2983 }; 2984 2985 static const struct display_timing urt_umsh_8596md_timing = { 2986 .pixelclock = { 33260000, 33260000, 33260000 }, 2987 .hactive = { 800, 800, 800 }, 2988 .hfront_porch = { 41, 41, 41 }, 2989 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 2990 .hsync_len = { 71, 128, 128 }, 2991 .vactive = { 480, 480, 480 }, 2992 .vfront_porch = { 10, 10, 10 }, 2993 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 2994 .vsync_len = { 2, 2, 2 }, 2995 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2996 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2997 }; 2998 2999 static const struct panel_desc urt_umsh_8596md_lvds = { 3000 .timings = &urt_umsh_8596md_timing, 3001 .num_timings = 1, 3002 .bpc = 6, 3003 .size = { 3004 .width = 152, 3005 .height = 91, 3006 }, 3007 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3009 }; 3010 3011 static const struct panel_desc urt_umsh_8596md_parallel = { 3012 .timings = &urt_umsh_8596md_timing, 3013 .num_timings = 1, 3014 .bpc = 6, 3015 .size = { 3016 .width = 152, 3017 .height = 91, 3018 }, 3019 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3020 }; 3021 3022 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3023 .clock = 33333, 3024 .hdisplay = 800, 3025 .hsync_start = 800 + 210, 3026 .hsync_end = 800 + 210 + 20, 3027 .htotal = 800 + 210 + 20 + 46, 3028 .vdisplay = 480, 3029 .vsync_start = 480 + 22, 3030 .vsync_end = 480 + 22 + 10, 3031 .vtotal = 480 + 22 + 10 + 23, 3032 .vrefresh = 60, 3033 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3034 }; 3035 3036 static const struct panel_desc vl050_8048nt_c01 = { 3037 .modes = &vl050_8048nt_c01_mode, 3038 .num_modes = 1, 3039 .bpc = 8, 3040 .size = { 3041 .width = 120, 3042 .height = 76, 3043 }, 3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3045 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3046 }; 3047 3048 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3049 .clock = 6410, 3050 .hdisplay = 320, 3051 .hsync_start = 320 + 20, 3052 .hsync_end = 320 + 20 + 30, 3053 .htotal = 320 + 20 + 30 + 38, 3054 .vdisplay = 240, 3055 .vsync_start = 240 + 4, 3056 .vsync_end = 240 + 4 + 3, 3057 .vtotal = 240 + 4 + 3 + 15, 3058 .vrefresh = 60, 3059 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3060 }; 3061 3062 static const struct panel_desc winstar_wf35ltiacd = { 3063 .modes = &winstar_wf35ltiacd_mode, 3064 .num_modes = 1, 3065 .bpc = 8, 3066 .size = { 3067 .width = 70, 3068 .height = 53, 3069 }, 3070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3071 }; 3072 3073 static const struct drm_display_mode arm_rtsm_mode[] = { 3074 { 3075 .clock = 65000, 3076 .hdisplay = 1024, 3077 .hsync_start = 1024 + 24, 3078 .hsync_end = 1024 + 24 + 136, 3079 .htotal = 1024 + 24 + 136 + 160, 3080 .vdisplay = 768, 3081 .vsync_start = 768 + 3, 3082 .vsync_end = 768 + 3 + 6, 3083 .vtotal = 768 + 3 + 6 + 29, 3084 .vrefresh = 60, 3085 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3086 }, 3087 }; 3088 3089 static const struct panel_desc arm_rtsm = { 3090 .modes = arm_rtsm_mode, 3091 .num_modes = 1, 3092 .bpc = 8, 3093 .size = { 3094 .width = 400, 3095 .height = 300, 3096 }, 3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3098 }; 3099 3100 static const struct of_device_id platform_of_match[] = { 3101 { 3102 .compatible = "ampire,am-480272h3tmqw-t01h", 3103 .data = &ire_am_480272h3tmqw_t01h, 3104 }, { 3105 .compatible = "ampire,am800480r3tmqwa1h", 3106 .data = &ire_am800480r3tmqwa1h, 3107 }, { 3108 .compatible = "arm,rtsm-display", 3109 .data = &arm_rtsm, 3110 }, { 3111 .compatible = "armadeus,st0700-adapt", 3112 .data = &armadeus_st0700_adapt, 3113 }, { 3114 .compatible = "auo,b101aw03", 3115 .data = &auo_b101aw03, 3116 }, { 3117 .compatible = "auo,b101ean01", 3118 .data = &auo_b101ean01, 3119 }, { 3120 .compatible = "auo,b101xtn01", 3121 .data = &auo_b101xtn01, 3122 }, { 3123 .compatible = "auo,b116xw03", 3124 .data = &auo_b116xw03, 3125 }, { 3126 .compatible = "auo,b133htn01", 3127 .data = &auo_b133htn01, 3128 }, { 3129 .compatible = "auo,b133xtn01", 3130 .data = &auo_b133xtn01, 3131 }, { 3132 .compatible = "auo,g070vvn01", 3133 .data = &auo_g070vvn01, 3134 }, { 3135 .compatible = "auo,g101evn010", 3136 .data = &auo_g101evn010, 3137 }, { 3138 .compatible = "auo,g104sn02", 3139 .data = &auo_g104sn02, 3140 }, { 3141 .compatible = "auo,g133han01", 3142 .data = &auo_g133han01, 3143 }, { 3144 .compatible = "auo,g185han01", 3145 .data = &auo_g185han01, 3146 }, { 3147 .compatible = "auo,p320hvn03", 3148 .data = &auo_p320hvn03, 3149 }, { 3150 .compatible = "auo,t215hvn01", 3151 .data = &auo_t215hvn01, 3152 }, { 3153 .compatible = "avic,tm070ddh03", 3154 .data = &avic_tm070ddh03, 3155 }, { 3156 .compatible = "bananapi,s070wv20-ct16", 3157 .data = &bananapi_s070wv20_ct16, 3158 }, { 3159 .compatible = "boe,hv070wsa-100", 3160 .data = &boe_hv070wsa 3161 }, { 3162 .compatible = "boe,nv101wxmn51", 3163 .data = &boe_nv101wxmn51, 3164 }, { 3165 .compatible = "cdtech,s043wq26h-ct7", 3166 .data = &cdtech_s043wq26h_ct7, 3167 }, { 3168 .compatible = "cdtech,s070wv95-ct16", 3169 .data = &cdtech_s070wv95_ct16, 3170 }, { 3171 .compatible = "chunghwa,claa070wp03xg", 3172 .data = &chunghwa_claa070wp03xg, 3173 }, { 3174 .compatible = "chunghwa,claa101wa01a", 3175 .data = &chunghwa_claa101wa01a 3176 }, { 3177 .compatible = "chunghwa,claa101wb01", 3178 .data = &chunghwa_claa101wb01 3179 }, { 3180 .compatible = "dataimage,scf0700c48ggu18", 3181 .data = &dataimage_scf0700c48ggu18, 3182 }, { 3183 .compatible = "dlc,dlc0700yzg-1", 3184 .data = &dlc_dlc0700yzg_1, 3185 }, { 3186 .compatible = "dlc,dlc1010gig", 3187 .data = &dlc_dlc1010gig, 3188 }, { 3189 .compatible = "edt,et035012dm6", 3190 .data = &edt_et035012dm6, 3191 }, { 3192 .compatible = "edt,etm0430g0dh6", 3193 .data = &edt_etm0430g0dh6, 3194 }, { 3195 .compatible = "edt,et057090dhu", 3196 .data = &edt_et057090dhu, 3197 }, { 3198 .compatible = "edt,et070080dh6", 3199 .data = &edt_etm0700g0dh6, 3200 }, { 3201 .compatible = "edt,etm0700g0dh6", 3202 .data = &edt_etm0700g0dh6, 3203 }, { 3204 .compatible = "edt,etm0700g0bdh6", 3205 .data = &edt_etm0700g0bdh6, 3206 }, { 3207 .compatible = "edt,etm0700g0edh6", 3208 .data = &edt_etm0700g0bdh6, 3209 }, { 3210 .compatible = "evervision,vgg804821", 3211 .data = &evervision_vgg804821, 3212 }, { 3213 .compatible = "foxlink,fl500wvr00-a0t", 3214 .data = &foxlink_fl500wvr00_a0t, 3215 }, { 3216 .compatible = "friendlyarm,hd702e", 3217 .data = &friendlyarm_hd702e, 3218 }, { 3219 .compatible = "giantplus,gpg482739qs5", 3220 .data = &giantplus_gpg482739qs5 3221 }, { 3222 .compatible = "giantplus,gpm940b0", 3223 .data = &giantplus_gpm940b0, 3224 }, { 3225 .compatible = "hannstar,hsd070pww1", 3226 .data = &hannstar_hsd070pww1, 3227 }, { 3228 .compatible = "hannstar,hsd100pxn1", 3229 .data = &hannstar_hsd100pxn1, 3230 }, { 3231 .compatible = "hit,tx23d38vm0caa", 3232 .data = &hitachi_tx23d38vm0caa 3233 }, { 3234 .compatible = "innolux,at043tn24", 3235 .data = &innolux_at043tn24, 3236 }, { 3237 .compatible = "innolux,at070tn92", 3238 .data = &innolux_at070tn92, 3239 }, { 3240 .compatible = "innolux,g070y2-l01", 3241 .data = &innolux_g070y2_l01, 3242 }, { 3243 .compatible = "innolux,g101ice-l01", 3244 .data = &innolux_g101ice_l01 3245 }, { 3246 .compatible = "innolux,g121i1-l01", 3247 .data = &innolux_g121i1_l01 3248 }, { 3249 .compatible = "innolux,g121x1-l03", 3250 .data = &innolux_g121x1_l03, 3251 }, { 3252 .compatible = "innolux,n116bge", 3253 .data = &innolux_n116bge, 3254 }, { 3255 .compatible = "innolux,n156bge-l21", 3256 .data = &innolux_n156bge_l21, 3257 }, { 3258 .compatible = "innolux,p120zdg-bf1", 3259 .data = &innolux_p120zdg_bf1, 3260 }, { 3261 .compatible = "innolux,zj070na-01p", 3262 .data = &innolux_zj070na_01p, 3263 }, { 3264 .compatible = "koe,tx14d24vm1bpa", 3265 .data = &koe_tx14d24vm1bpa, 3266 }, { 3267 .compatible = "koe,tx31d200vm0baa", 3268 .data = &koe_tx31d200vm0baa, 3269 }, { 3270 .compatible = "kyo,tcg121xglp", 3271 .data = &kyo_tcg121xglp, 3272 }, { 3273 .compatible = "lemaker,bl035-rgb-002", 3274 .data = &lemaker_bl035_rgb_002, 3275 }, { 3276 .compatible = "lg,lb070wv8", 3277 .data = &lg_lb070wv8, 3278 }, { 3279 .compatible = "lg,lp079qx1-sp0v", 3280 .data = &lg_lp079qx1_sp0v, 3281 }, { 3282 .compatible = "lg,lp097qx1-spa1", 3283 .data = &lg_lp097qx1_spa1, 3284 }, { 3285 .compatible = "lg,lp120up1", 3286 .data = &lg_lp120up1, 3287 }, { 3288 .compatible = "lg,lp129qe", 3289 .data = &lg_lp129qe, 3290 }, { 3291 .compatible = "mitsubishi,aa070mc01-ca1", 3292 .data = &mitsubishi_aa070mc01, 3293 }, { 3294 .compatible = "nec,nl12880bc20-05", 3295 .data = &nec_nl12880bc20_05, 3296 }, { 3297 .compatible = "nec,nl4827hc19-05b", 3298 .data = &nec_nl4827hc19_05b, 3299 }, { 3300 .compatible = "netron-dy,e231732", 3301 .data = &netron_dy_e231732, 3302 }, { 3303 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3304 .data = &newhaven_nhd_43_480272ef_atxl, 3305 }, { 3306 .compatible = "nlt,nl192108ac18-02d", 3307 .data = &nlt_nl192108ac18_02d, 3308 }, { 3309 .compatible = "nvd,9128", 3310 .data = &nvd_9128, 3311 }, { 3312 .compatible = "okaya,rs800480t-7x0gp", 3313 .data = &okaya_rs800480t_7x0gp, 3314 }, { 3315 .compatible = "olimex,lcd-olinuxino-43-ts", 3316 .data = &olimex_lcd_olinuxino_43ts, 3317 }, { 3318 .compatible = "ontat,yx700wv03", 3319 .data = &ontat_yx700wv03, 3320 }, { 3321 .compatible = "ortustech,com37h3m05dtc", 3322 .data = &ortustech_com37h3m, 3323 }, { 3324 .compatible = "ortustech,com37h3m99dtc", 3325 .data = &ortustech_com37h3m, 3326 }, { 3327 .compatible = "ortustech,com43h4m85ulc", 3328 .data = &ortustech_com43h4m85ulc, 3329 }, { 3330 .compatible = "osddisplays,osd070t1718-19ts", 3331 .data = &osddisplays_osd070t1718_19ts, 3332 }, { 3333 .compatible = "pda,91-00156-a0", 3334 .data = &pda_91_00156_a0, 3335 }, { 3336 .compatible = "qiaodian,qd43003c0-40", 3337 .data = &qd43003c0_40, 3338 }, { 3339 .compatible = "rocktech,rk070er9427", 3340 .data = &rocktech_rk070er9427, 3341 }, { 3342 .compatible = "samsung,lsn122dl01-c01", 3343 .data = &samsung_lsn122dl01_c01, 3344 }, { 3345 .compatible = "samsung,ltn101nt05", 3346 .data = &samsung_ltn101nt05, 3347 }, { 3348 .compatible = "samsung,ltn140at29-301", 3349 .data = &samsung_ltn140at29_301, 3350 }, { 3351 .compatible = "sharp,ld-d5116z01b", 3352 .data = &sharp_ld_d5116z01b, 3353 }, { 3354 .compatible = "sharp,lq035q7db03", 3355 .data = &sharp_lq035q7db03, 3356 }, { 3357 .compatible = "sharp,lq070y3dg3b", 3358 .data = &sharp_lq070y3dg3b, 3359 }, { 3360 .compatible = "sharp,lq101k1ly04", 3361 .data = &sharp_lq101k1ly04, 3362 }, { 3363 .compatible = "sharp,lq123p1jx31", 3364 .data = &sharp_lq123p1jx31, 3365 }, { 3366 .compatible = "sharp,lq150x1lg11", 3367 .data = &sharp_lq150x1lg11, 3368 }, { 3369 .compatible = "sharp,ls020b1dd01d", 3370 .data = &sharp_ls020b1dd01d, 3371 }, { 3372 .compatible = "shelly,sca07010-bfn-lnn", 3373 .data = &shelly_sca07010_bfn_lnn, 3374 }, { 3375 .compatible = "starry,kr122ea0sra", 3376 .data = &starry_kr122ea0sra, 3377 }, { 3378 .compatible = "tfc,s9700rtwv43tr-01b", 3379 .data = &tfc_s9700rtwv43tr_01b, 3380 }, { 3381 .compatible = "tianma,tm070jdhg30", 3382 .data = &tianma_tm070jdhg30, 3383 }, { 3384 .compatible = "tianma,tm070rvhg71", 3385 .data = &tianma_tm070rvhg71, 3386 }, { 3387 .compatible = "ti,nspire-cx-lcd-panel", 3388 .data = &ti_nspire_cx_lcd_panel, 3389 }, { 3390 .compatible = "ti,nspire-classic-lcd-panel", 3391 .data = &ti_nspire_classic_lcd_panel, 3392 }, { 3393 .compatible = "toshiba,lt089ac29000", 3394 .data = &toshiba_lt089ac29000, 3395 }, { 3396 .compatible = "tpk,f07a-0102", 3397 .data = &tpk_f07a_0102, 3398 }, { 3399 .compatible = "tpk,f10a-0102", 3400 .data = &tpk_f10a_0102, 3401 }, { 3402 .compatible = "urt,umsh-8596md-t", 3403 .data = &urt_umsh_8596md_parallel, 3404 }, { 3405 .compatible = "urt,umsh-8596md-1t", 3406 .data = &urt_umsh_8596md_parallel, 3407 }, { 3408 .compatible = "urt,umsh-8596md-7t", 3409 .data = &urt_umsh_8596md_parallel, 3410 }, { 3411 .compatible = "urt,umsh-8596md-11t", 3412 .data = &urt_umsh_8596md_lvds, 3413 }, { 3414 .compatible = "urt,umsh-8596md-19t", 3415 .data = &urt_umsh_8596md_lvds, 3416 }, { 3417 .compatible = "urt,umsh-8596md-20t", 3418 .data = &urt_umsh_8596md_parallel, 3419 }, { 3420 .compatible = "vxt,vl050-8048nt-c01", 3421 .data = &vl050_8048nt_c01, 3422 }, { 3423 .compatible = "winstar,wf35ltiacd", 3424 .data = &winstar_wf35ltiacd, 3425 }, { 3426 /* sentinel */ 3427 } 3428 }; 3429 MODULE_DEVICE_TABLE(of, platform_of_match); 3430 3431 static int panel_simple_platform_probe(struct platform_device *pdev) 3432 { 3433 const struct of_device_id *id; 3434 3435 id = of_match_node(platform_of_match, pdev->dev.of_node); 3436 if (!id) 3437 return -ENODEV; 3438 3439 return panel_simple_probe(&pdev->dev, id->data); 3440 } 3441 3442 static int panel_simple_platform_remove(struct platform_device *pdev) 3443 { 3444 return panel_simple_remove(&pdev->dev); 3445 } 3446 3447 static void panel_simple_platform_shutdown(struct platform_device *pdev) 3448 { 3449 panel_simple_shutdown(&pdev->dev); 3450 } 3451 3452 static struct platform_driver panel_simple_platform_driver = { 3453 .driver = { 3454 .name = "panel-simple", 3455 .of_match_table = platform_of_match, 3456 }, 3457 .probe = panel_simple_platform_probe, 3458 .remove = panel_simple_platform_remove, 3459 .shutdown = panel_simple_platform_shutdown, 3460 }; 3461 3462 struct panel_desc_dsi { 3463 struct panel_desc desc; 3464 3465 unsigned long flags; 3466 enum mipi_dsi_pixel_format format; 3467 unsigned int lanes; 3468 }; 3469 3470 static const struct drm_display_mode auo_b080uan01_mode = { 3471 .clock = 154500, 3472 .hdisplay = 1200, 3473 .hsync_start = 1200 + 62, 3474 .hsync_end = 1200 + 62 + 4, 3475 .htotal = 1200 + 62 + 4 + 62, 3476 .vdisplay = 1920, 3477 .vsync_start = 1920 + 9, 3478 .vsync_end = 1920 + 9 + 2, 3479 .vtotal = 1920 + 9 + 2 + 8, 3480 .vrefresh = 60, 3481 }; 3482 3483 static const struct panel_desc_dsi auo_b080uan01 = { 3484 .desc = { 3485 .modes = &auo_b080uan01_mode, 3486 .num_modes = 1, 3487 .bpc = 8, 3488 .size = { 3489 .width = 108, 3490 .height = 272, 3491 }, 3492 }, 3493 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3494 .format = MIPI_DSI_FMT_RGB888, 3495 .lanes = 4, 3496 }; 3497 3498 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 3499 .clock = 160000, 3500 .hdisplay = 1200, 3501 .hsync_start = 1200 + 120, 3502 .hsync_end = 1200 + 120 + 20, 3503 .htotal = 1200 + 120 + 20 + 21, 3504 .vdisplay = 1920, 3505 .vsync_start = 1920 + 21, 3506 .vsync_end = 1920 + 21 + 3, 3507 .vtotal = 1920 + 21 + 3 + 18, 3508 .vrefresh = 60, 3509 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3510 }; 3511 3512 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 3513 .desc = { 3514 .modes = &boe_tv080wum_nl0_mode, 3515 .num_modes = 1, 3516 .size = { 3517 .width = 107, 3518 .height = 172, 3519 }, 3520 }, 3521 .flags = MIPI_DSI_MODE_VIDEO | 3522 MIPI_DSI_MODE_VIDEO_BURST | 3523 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 3524 .format = MIPI_DSI_FMT_RGB888, 3525 .lanes = 4, 3526 }; 3527 3528 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 3529 .clock = 71000, 3530 .hdisplay = 800, 3531 .hsync_start = 800 + 32, 3532 .hsync_end = 800 + 32 + 1, 3533 .htotal = 800 + 32 + 1 + 57, 3534 .vdisplay = 1280, 3535 .vsync_start = 1280 + 28, 3536 .vsync_end = 1280 + 28 + 1, 3537 .vtotal = 1280 + 28 + 1 + 14, 3538 .vrefresh = 60, 3539 }; 3540 3541 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 3542 .desc = { 3543 .modes = &lg_ld070wx3_sl01_mode, 3544 .num_modes = 1, 3545 .bpc = 8, 3546 .size = { 3547 .width = 94, 3548 .height = 151, 3549 }, 3550 }, 3551 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3552 .format = MIPI_DSI_FMT_RGB888, 3553 .lanes = 4, 3554 }; 3555 3556 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 3557 .clock = 67000, 3558 .hdisplay = 720, 3559 .hsync_start = 720 + 12, 3560 .hsync_end = 720 + 12 + 4, 3561 .htotal = 720 + 12 + 4 + 112, 3562 .vdisplay = 1280, 3563 .vsync_start = 1280 + 8, 3564 .vsync_end = 1280 + 8 + 4, 3565 .vtotal = 1280 + 8 + 4 + 12, 3566 .vrefresh = 60, 3567 }; 3568 3569 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 3570 .desc = { 3571 .modes = &lg_lh500wx1_sd03_mode, 3572 .num_modes = 1, 3573 .bpc = 8, 3574 .size = { 3575 .width = 62, 3576 .height = 110, 3577 }, 3578 }, 3579 .flags = MIPI_DSI_MODE_VIDEO, 3580 .format = MIPI_DSI_FMT_RGB888, 3581 .lanes = 4, 3582 }; 3583 3584 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 3585 .clock = 157200, 3586 .hdisplay = 1920, 3587 .hsync_start = 1920 + 154, 3588 .hsync_end = 1920 + 154 + 16, 3589 .htotal = 1920 + 154 + 16 + 32, 3590 .vdisplay = 1200, 3591 .vsync_start = 1200 + 17, 3592 .vsync_end = 1200 + 17 + 2, 3593 .vtotal = 1200 + 17 + 2 + 16, 3594 .vrefresh = 60, 3595 }; 3596 3597 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 3598 .desc = { 3599 .modes = &panasonic_vvx10f004b00_mode, 3600 .num_modes = 1, 3601 .bpc = 8, 3602 .size = { 3603 .width = 217, 3604 .height = 136, 3605 }, 3606 }, 3607 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3608 MIPI_DSI_CLOCK_NON_CONTINUOUS, 3609 .format = MIPI_DSI_FMT_RGB888, 3610 .lanes = 4, 3611 }; 3612 3613 static const struct drm_display_mode lg_acx467akm_7_mode = { 3614 .clock = 150000, 3615 .hdisplay = 1080, 3616 .hsync_start = 1080 + 2, 3617 .hsync_end = 1080 + 2 + 2, 3618 .htotal = 1080 + 2 + 2 + 2, 3619 .vdisplay = 1920, 3620 .vsync_start = 1920 + 2, 3621 .vsync_end = 1920 + 2 + 2, 3622 .vtotal = 1920 + 2 + 2 + 2, 3623 .vrefresh = 60, 3624 }; 3625 3626 static const struct panel_desc_dsi lg_acx467akm_7 = { 3627 .desc = { 3628 .modes = &lg_acx467akm_7_mode, 3629 .num_modes = 1, 3630 .bpc = 8, 3631 .size = { 3632 .width = 62, 3633 .height = 110, 3634 }, 3635 }, 3636 .flags = 0, 3637 .format = MIPI_DSI_FMT_RGB888, 3638 .lanes = 4, 3639 }; 3640 3641 static const struct drm_display_mode osd101t2045_53ts_mode = { 3642 .clock = 154500, 3643 .hdisplay = 1920, 3644 .hsync_start = 1920 + 112, 3645 .hsync_end = 1920 + 112 + 16, 3646 .htotal = 1920 + 112 + 16 + 32, 3647 .vdisplay = 1200, 3648 .vsync_start = 1200 + 16, 3649 .vsync_end = 1200 + 16 + 2, 3650 .vtotal = 1200 + 16 + 2 + 16, 3651 .vrefresh = 60, 3652 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3653 }; 3654 3655 static const struct panel_desc_dsi osd101t2045_53ts = { 3656 .desc = { 3657 .modes = &osd101t2045_53ts_mode, 3658 .num_modes = 1, 3659 .bpc = 8, 3660 .size = { 3661 .width = 217, 3662 .height = 136, 3663 }, 3664 }, 3665 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 3666 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3667 MIPI_DSI_MODE_EOT_PACKET, 3668 .format = MIPI_DSI_FMT_RGB888, 3669 .lanes = 4, 3670 }; 3671 3672 static const struct of_device_id dsi_of_match[] = { 3673 { 3674 .compatible = "auo,b080uan01", 3675 .data = &auo_b080uan01 3676 }, { 3677 .compatible = "boe,tv080wum-nl0", 3678 .data = &boe_tv080wum_nl0 3679 }, { 3680 .compatible = "lg,ld070wx3-sl01", 3681 .data = &lg_ld070wx3_sl01 3682 }, { 3683 .compatible = "lg,lh500wx1-sd03", 3684 .data = &lg_lh500wx1_sd03 3685 }, { 3686 .compatible = "panasonic,vvx10f004b00", 3687 .data = &panasonic_vvx10f004b00 3688 }, { 3689 .compatible = "lg,acx467akm-7", 3690 .data = &lg_acx467akm_7 3691 }, { 3692 .compatible = "osddisplays,osd101t2045-53ts", 3693 .data = &osd101t2045_53ts 3694 }, { 3695 /* sentinel */ 3696 } 3697 }; 3698 MODULE_DEVICE_TABLE(of, dsi_of_match); 3699 3700 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 3701 { 3702 const struct panel_desc_dsi *desc; 3703 const struct of_device_id *id; 3704 int err; 3705 3706 id = of_match_node(dsi_of_match, dsi->dev.of_node); 3707 if (!id) 3708 return -ENODEV; 3709 3710 desc = id->data; 3711 3712 err = panel_simple_probe(&dsi->dev, &desc->desc); 3713 if (err < 0) 3714 return err; 3715 3716 dsi->mode_flags = desc->flags; 3717 dsi->format = desc->format; 3718 dsi->lanes = desc->lanes; 3719 3720 err = mipi_dsi_attach(dsi); 3721 if (err) { 3722 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 3723 3724 drm_panel_remove(&panel->base); 3725 } 3726 3727 return err; 3728 } 3729 3730 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 3731 { 3732 int err; 3733 3734 err = mipi_dsi_detach(dsi); 3735 if (err < 0) 3736 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 3737 3738 return panel_simple_remove(&dsi->dev); 3739 } 3740 3741 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 3742 { 3743 panel_simple_shutdown(&dsi->dev); 3744 } 3745 3746 static struct mipi_dsi_driver panel_simple_dsi_driver = { 3747 .driver = { 3748 .name = "panel-simple-dsi", 3749 .of_match_table = dsi_of_match, 3750 }, 3751 .probe = panel_simple_dsi_probe, 3752 .remove = panel_simple_dsi_remove, 3753 .shutdown = panel_simple_dsi_shutdown, 3754 }; 3755 3756 static int __init panel_simple_init(void) 3757 { 3758 int err; 3759 3760 err = platform_driver_register(&panel_simple_platform_driver); 3761 if (err < 0) 3762 return err; 3763 3764 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 3765 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 3766 if (err < 0) 3767 return err; 3768 } 3769 3770 return 0; 3771 } 3772 module_init(panel_simple_init); 3773 3774 static void __exit panel_simple_exit(void) 3775 { 3776 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 3777 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 3778 3779 platform_driver_unregister(&panel_simple_platform_driver); 3780 } 3781 module_exit(panel_simple_exit); 3782 3783 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 3784 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 3785 MODULE_LICENSE("GPL and additional rights"); 3786