1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_timings == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 if (p->enable_gpio) 191 gpiod_set_value_cansleep(p->enable_gpio, 0); 192 193 regulator_disable(p->supply); 194 195 if (p->desc->delay.unprepare) 196 msleep(p->desc->delay.unprepare); 197 198 p->prepared = false; 199 200 return 0; 201 } 202 203 static int panel_simple_prepare(struct drm_panel *panel) 204 { 205 struct panel_simple *p = to_panel_simple(panel); 206 int err; 207 208 if (p->prepared) 209 return 0; 210 211 err = regulator_enable(p->supply); 212 if (err < 0) { 213 dev_err(panel->dev, "failed to enable supply: %d\n", err); 214 return err; 215 } 216 217 if (p->enable_gpio) 218 gpiod_set_value_cansleep(p->enable_gpio, 1); 219 220 if (p->desc->delay.prepare) 221 msleep(p->desc->delay.prepare); 222 223 p->prepared = true; 224 225 return 0; 226 } 227 228 static int panel_simple_enable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (p->enabled) 233 return 0; 234 235 if (p->desc->delay.enable) 236 msleep(p->desc->delay.enable); 237 238 if (p->backlight) { 239 p->backlight->props.state &= ~BL_CORE_FBBLANK; 240 p->backlight->props.power = FB_BLANK_UNBLANK; 241 backlight_update_status(p->backlight); 242 } 243 244 p->enabled = true; 245 246 return 0; 247 } 248 249 static int panel_simple_get_modes(struct drm_panel *panel) 250 { 251 struct panel_simple *p = to_panel_simple(panel); 252 int num = 0; 253 254 /* probe EDID if a DDC bus is available */ 255 if (p->ddc) { 256 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 257 drm_mode_connector_update_edid_property(panel->connector, edid); 258 if (edid) { 259 num += drm_add_edid_modes(panel->connector, edid); 260 kfree(edid); 261 } 262 } 263 264 /* add hard-coded panel modes */ 265 num += panel_simple_get_fixed_modes(p); 266 267 return num; 268 } 269 270 static int panel_simple_get_timings(struct drm_panel *panel, 271 unsigned int num_timings, 272 struct display_timing *timings) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int i; 276 277 if (p->desc->num_timings < num_timings) 278 num_timings = p->desc->num_timings; 279 280 if (timings) 281 for (i = 0; i < num_timings; i++) 282 timings[i] = p->desc->timings[i]; 283 284 return p->desc->num_timings; 285 } 286 287 static const struct drm_panel_funcs panel_simple_funcs = { 288 .disable = panel_simple_disable, 289 .unprepare = panel_simple_unprepare, 290 .prepare = panel_simple_prepare, 291 .enable = panel_simple_enable, 292 .get_modes = panel_simple_get_modes, 293 .get_timings = panel_simple_get_timings, 294 }; 295 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 297 { 298 struct device_node *backlight, *ddc; 299 struct panel_simple *panel; 300 int err; 301 302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 303 if (!panel) 304 return -ENOMEM; 305 306 panel->enabled = false; 307 panel->prepared = false; 308 panel->desc = desc; 309 310 panel->supply = devm_regulator_get(dev, "power"); 311 if (IS_ERR(panel->supply)) 312 return PTR_ERR(panel->supply); 313 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 315 GPIOD_OUT_LOW); 316 if (IS_ERR(panel->enable_gpio)) { 317 err = PTR_ERR(panel->enable_gpio); 318 dev_err(dev, "failed to request GPIO: %d\n", err); 319 return err; 320 } 321 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 323 if (backlight) { 324 panel->backlight = of_find_backlight_by_node(backlight); 325 of_node_put(backlight); 326 327 if (!panel->backlight) 328 return -EPROBE_DEFER; 329 } 330 331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 332 if (ddc) { 333 panel->ddc = of_find_i2c_adapter_by_node(ddc); 334 of_node_put(ddc); 335 336 if (!panel->ddc) { 337 err = -EPROBE_DEFER; 338 goto free_backlight; 339 } 340 } 341 342 drm_panel_init(&panel->base); 343 panel->base.dev = dev; 344 panel->base.funcs = &panel_simple_funcs; 345 346 err = drm_panel_add(&panel->base); 347 if (err < 0) 348 goto free_ddc; 349 350 dev_set_drvdata(dev, panel); 351 352 return 0; 353 354 free_ddc: 355 if (panel->ddc) 356 put_device(&panel->ddc->dev); 357 free_backlight: 358 if (panel->backlight) 359 put_device(&panel->backlight->dev); 360 361 return err; 362 } 363 364 static int panel_simple_remove(struct device *dev) 365 { 366 struct panel_simple *panel = dev_get_drvdata(dev); 367 368 drm_panel_detach(&panel->base); 369 drm_panel_remove(&panel->base); 370 371 panel_simple_disable(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 390 .clock = 9000, 391 .hdisplay = 480, 392 .hsync_start = 480 + 2, 393 .hsync_end = 480 + 2 + 41, 394 .htotal = 480 + 2 + 41 + 2, 395 .vdisplay = 272, 396 .vsync_start = 272 + 2, 397 .vsync_end = 272 + 2 + 10, 398 .vtotal = 272 + 2 + 10 + 2, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 404 .modes = &ire_am_480272h3tmqw_t01h_mode, 405 .num_modes = 1, 406 .bpc = 8, 407 .size = { 408 .width = 105, 409 .height = 67, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 412 }; 413 414 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 415 .clock = 33333, 416 .hdisplay = 800, 417 .hsync_start = 800 + 0, 418 .hsync_end = 800 + 0 + 255, 419 .htotal = 800 + 0 + 255 + 0, 420 .vdisplay = 480, 421 .vsync_start = 480 + 2, 422 .vsync_end = 480 + 2 + 45, 423 .vtotal = 480 + 2 + 45 + 0, 424 .vrefresh = 60, 425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 426 }; 427 428 static const struct panel_desc ampire_am800480r3tmqwa1h = { 429 .modes = &ire_am800480r3tmqwa1h_mode, 430 .num_modes = 1, 431 .bpc = 6, 432 .size = { 433 .width = 152, 434 .height = 91, 435 }, 436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 437 }; 438 439 static const struct drm_display_mode auo_b101aw03_mode = { 440 .clock = 51450, 441 .hdisplay = 1024, 442 .hsync_start = 1024 + 156, 443 .hsync_end = 1024 + 156 + 8, 444 .htotal = 1024 + 156 + 8 + 156, 445 .vdisplay = 600, 446 .vsync_start = 600 + 16, 447 .vsync_end = 600 + 16 + 6, 448 .vtotal = 600 + 16 + 6 + 16, 449 .vrefresh = 60, 450 }; 451 452 static const struct panel_desc auo_b101aw03 = { 453 .modes = &auo_b101aw03_mode, 454 .num_modes = 1, 455 .bpc = 6, 456 .size = { 457 .width = 223, 458 .height = 125, 459 }, 460 }; 461 462 static const struct drm_display_mode auo_b101ean01_mode = { 463 .clock = 72500, 464 .hdisplay = 1280, 465 .hsync_start = 1280 + 119, 466 .hsync_end = 1280 + 119 + 32, 467 .htotal = 1280 + 119 + 32 + 21, 468 .vdisplay = 800, 469 .vsync_start = 800 + 4, 470 .vsync_end = 800 + 4 + 20, 471 .vtotal = 800 + 4 + 20 + 8, 472 .vrefresh = 60, 473 }; 474 475 static const struct panel_desc auo_b101ean01 = { 476 .modes = &auo_b101ean01_mode, 477 .num_modes = 1, 478 .bpc = 6, 479 .size = { 480 .width = 217, 481 .height = 136, 482 }, 483 }; 484 485 static const struct drm_display_mode auo_b101xtn01_mode = { 486 .clock = 72000, 487 .hdisplay = 1366, 488 .hsync_start = 1366 + 20, 489 .hsync_end = 1366 + 20 + 70, 490 .htotal = 1366 + 20 + 70, 491 .vdisplay = 768, 492 .vsync_start = 768 + 14, 493 .vsync_end = 768 + 14 + 42, 494 .vtotal = 768 + 14 + 42, 495 .vrefresh = 60, 496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 497 }; 498 499 static const struct panel_desc auo_b101xtn01 = { 500 .modes = &auo_b101xtn01_mode, 501 .num_modes = 1, 502 .bpc = 6, 503 .size = { 504 .width = 223, 505 .height = 125, 506 }, 507 }; 508 509 static const struct drm_display_mode auo_b116xw03_mode = { 510 .clock = 70589, 511 .hdisplay = 1366, 512 .hsync_start = 1366 + 40, 513 .hsync_end = 1366 + 40 + 40, 514 .htotal = 1366 + 40 + 40 + 32, 515 .vdisplay = 768, 516 .vsync_start = 768 + 10, 517 .vsync_end = 768 + 10 + 12, 518 .vtotal = 768 + 10 + 12 + 6, 519 .vrefresh = 60, 520 }; 521 522 static const struct panel_desc auo_b116xw03 = { 523 .modes = &auo_b116xw03_mode, 524 .num_modes = 1, 525 .bpc = 6, 526 .size = { 527 .width = 256, 528 .height = 144, 529 }, 530 }; 531 532 static const struct drm_display_mode auo_b133xtn01_mode = { 533 .clock = 69500, 534 .hdisplay = 1366, 535 .hsync_start = 1366 + 48, 536 .hsync_end = 1366 + 48 + 32, 537 .htotal = 1366 + 48 + 32 + 20, 538 .vdisplay = 768, 539 .vsync_start = 768 + 3, 540 .vsync_end = 768 + 3 + 6, 541 .vtotal = 768 + 3 + 6 + 13, 542 .vrefresh = 60, 543 }; 544 545 static const struct panel_desc auo_b133xtn01 = { 546 .modes = &auo_b133xtn01_mode, 547 .num_modes = 1, 548 .bpc = 6, 549 .size = { 550 .width = 293, 551 .height = 165, 552 }, 553 }; 554 555 static const struct drm_display_mode auo_b133htn01_mode = { 556 .clock = 150660, 557 .hdisplay = 1920, 558 .hsync_start = 1920 + 172, 559 .hsync_end = 1920 + 172 + 80, 560 .htotal = 1920 + 172 + 80 + 60, 561 .vdisplay = 1080, 562 .vsync_start = 1080 + 25, 563 .vsync_end = 1080 + 25 + 10, 564 .vtotal = 1080 + 25 + 10 + 10, 565 .vrefresh = 60, 566 }; 567 568 static const struct panel_desc auo_b133htn01 = { 569 .modes = &auo_b133htn01_mode, 570 .num_modes = 1, 571 .bpc = 6, 572 .size = { 573 .width = 293, 574 .height = 165, 575 }, 576 .delay = { 577 .prepare = 105, 578 .enable = 20, 579 .unprepare = 50, 580 }, 581 }; 582 583 static const struct display_timing auo_g133han01_timings = { 584 .pixelclock = { 134000000, 141200000, 149000000 }, 585 .hactive = { 1920, 1920, 1920 }, 586 .hfront_porch = { 39, 58, 77 }, 587 .hback_porch = { 59, 88, 117 }, 588 .hsync_len = { 28, 42, 56 }, 589 .vactive = { 1080, 1080, 1080 }, 590 .vfront_porch = { 3, 8, 11 }, 591 .vback_porch = { 5, 14, 19 }, 592 .vsync_len = { 4, 14, 19 }, 593 }; 594 595 static const struct panel_desc auo_g133han01 = { 596 .timings = &auo_g133han01_timings, 597 .num_timings = 1, 598 .bpc = 8, 599 .size = { 600 .width = 293, 601 .height = 165, 602 }, 603 .delay = { 604 .prepare = 200, 605 .enable = 50, 606 .disable = 50, 607 .unprepare = 1000, 608 }, 609 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 610 }; 611 612 static const struct display_timing auo_g185han01_timings = { 613 .pixelclock = { 120000000, 144000000, 175000000 }, 614 .hactive = { 1920, 1920, 1920 }, 615 .hfront_porch = { 18, 60, 74 }, 616 .hback_porch = { 12, 44, 54 }, 617 .hsync_len = { 10, 24, 32 }, 618 .vactive = { 1080, 1080, 1080 }, 619 .vfront_porch = { 6, 10, 40 }, 620 .vback_porch = { 2, 5, 20 }, 621 .vsync_len = { 2, 5, 20 }, 622 }; 623 624 static const struct panel_desc auo_g185han01 = { 625 .timings = &auo_g185han01_timings, 626 .num_timings = 1, 627 .bpc = 8, 628 .size = { 629 .width = 409, 630 .height = 230, 631 }, 632 .delay = { 633 .prepare = 50, 634 .enable = 200, 635 .disable = 110, 636 .unprepare = 1000, 637 }, 638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 639 }; 640 641 static const struct drm_display_mode auo_t215hvn01_mode = { 642 .clock = 148800, 643 .hdisplay = 1920, 644 .hsync_start = 1920 + 88, 645 .hsync_end = 1920 + 88 + 44, 646 .htotal = 1920 + 88 + 44 + 148, 647 .vdisplay = 1080, 648 .vsync_start = 1080 + 4, 649 .vsync_end = 1080 + 4 + 5, 650 .vtotal = 1080 + 4 + 5 + 36, 651 .vrefresh = 60, 652 }; 653 654 static const struct panel_desc auo_t215hvn01 = { 655 .modes = &auo_t215hvn01_mode, 656 .num_modes = 1, 657 .bpc = 8, 658 .size = { 659 .width = 430, 660 .height = 270, 661 }, 662 .delay = { 663 .disable = 5, 664 .unprepare = 1000, 665 } 666 }; 667 668 static const struct drm_display_mode avic_tm070ddh03_mode = { 669 .clock = 51200, 670 .hdisplay = 1024, 671 .hsync_start = 1024 + 160, 672 .hsync_end = 1024 + 160 + 4, 673 .htotal = 1024 + 160 + 4 + 156, 674 .vdisplay = 600, 675 .vsync_start = 600 + 17, 676 .vsync_end = 600 + 17 + 1, 677 .vtotal = 600 + 17 + 1 + 17, 678 .vrefresh = 60, 679 }; 680 681 static const struct panel_desc avic_tm070ddh03 = { 682 .modes = &avic_tm070ddh03_mode, 683 .num_modes = 1, 684 .bpc = 8, 685 .size = { 686 .width = 154, 687 .height = 90, 688 }, 689 .delay = { 690 .prepare = 20, 691 .enable = 200, 692 .disable = 200, 693 }, 694 }; 695 696 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 697 { 698 .clock = 71900, 699 .hdisplay = 1280, 700 .hsync_start = 1280 + 48, 701 .hsync_end = 1280 + 48 + 32, 702 .htotal = 1280 + 48 + 32 + 80, 703 .vdisplay = 800, 704 .vsync_start = 800 + 3, 705 .vsync_end = 800 + 3 + 5, 706 .vtotal = 800 + 3 + 5 + 24, 707 .vrefresh = 60, 708 }, 709 { 710 .clock = 57500, 711 .hdisplay = 1280, 712 .hsync_start = 1280 + 48, 713 .hsync_end = 1280 + 48 + 32, 714 .htotal = 1280 + 48 + 32 + 80, 715 .vdisplay = 800, 716 .vsync_start = 800 + 3, 717 .vsync_end = 800 + 3 + 5, 718 .vtotal = 800 + 3 + 5 + 24, 719 .vrefresh = 48, 720 }, 721 }; 722 723 static const struct panel_desc boe_nv101wxmn51 = { 724 .modes = boe_nv101wxmn51_modes, 725 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 726 .bpc = 8, 727 .size = { 728 .width = 217, 729 .height = 136, 730 }, 731 .delay = { 732 .prepare = 210, 733 .enable = 50, 734 .unprepare = 160, 735 }, 736 }; 737 738 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 739 .clock = 66770, 740 .hdisplay = 800, 741 .hsync_start = 800 + 49, 742 .hsync_end = 800 + 49 + 33, 743 .htotal = 800 + 49 + 33 + 17, 744 .vdisplay = 1280, 745 .vsync_start = 1280 + 1, 746 .vsync_end = 1280 + 1 + 7, 747 .vtotal = 1280 + 1 + 7 + 15, 748 .vrefresh = 60, 749 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 750 }; 751 752 static const struct panel_desc chunghwa_claa070wp03xg = { 753 .modes = &chunghwa_claa070wp03xg_mode, 754 .num_modes = 1, 755 .bpc = 6, 756 .size = { 757 .width = 94, 758 .height = 150, 759 }, 760 }; 761 762 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 763 .clock = 72070, 764 .hdisplay = 1366, 765 .hsync_start = 1366 + 58, 766 .hsync_end = 1366 + 58 + 58, 767 .htotal = 1366 + 58 + 58 + 58, 768 .vdisplay = 768, 769 .vsync_start = 768 + 4, 770 .vsync_end = 768 + 4 + 4, 771 .vtotal = 768 + 4 + 4 + 4, 772 .vrefresh = 60, 773 }; 774 775 static const struct panel_desc chunghwa_claa101wa01a = { 776 .modes = &chunghwa_claa101wa01a_mode, 777 .num_modes = 1, 778 .bpc = 6, 779 .size = { 780 .width = 220, 781 .height = 120, 782 }, 783 }; 784 785 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 786 .clock = 69300, 787 .hdisplay = 1366, 788 .hsync_start = 1366 + 48, 789 .hsync_end = 1366 + 48 + 32, 790 .htotal = 1366 + 48 + 32 + 20, 791 .vdisplay = 768, 792 .vsync_start = 768 + 16, 793 .vsync_end = 768 + 16 + 8, 794 .vtotal = 768 + 16 + 8 + 16, 795 .vrefresh = 60, 796 }; 797 798 static const struct panel_desc chunghwa_claa101wb01 = { 799 .modes = &chunghwa_claa101wb01_mode, 800 .num_modes = 1, 801 .bpc = 6, 802 .size = { 803 .width = 223, 804 .height = 125, 805 }, 806 }; 807 808 static const struct drm_display_mode edt_et057090dhu_mode = { 809 .clock = 25175, 810 .hdisplay = 640, 811 .hsync_start = 640 + 16, 812 .hsync_end = 640 + 16 + 30, 813 .htotal = 640 + 16 + 30 + 114, 814 .vdisplay = 480, 815 .vsync_start = 480 + 10, 816 .vsync_end = 480 + 10 + 3, 817 .vtotal = 480 + 10 + 3 + 32, 818 .vrefresh = 60, 819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 820 }; 821 822 static const struct panel_desc edt_et057090dhu = { 823 .modes = &edt_et057090dhu_mode, 824 .num_modes = 1, 825 .bpc = 6, 826 .size = { 827 .width = 115, 828 .height = 86, 829 }, 830 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 832 }; 833 834 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 835 .clock = 33260, 836 .hdisplay = 800, 837 .hsync_start = 800 + 40, 838 .hsync_end = 800 + 40 + 128, 839 .htotal = 800 + 40 + 128 + 88, 840 .vdisplay = 480, 841 .vsync_start = 480 + 10, 842 .vsync_end = 480 + 10 + 2, 843 .vtotal = 480 + 10 + 2 + 33, 844 .vrefresh = 60, 845 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 846 }; 847 848 static const struct panel_desc edt_etm0700g0dh6 = { 849 .modes = &edt_etm0700g0dh6_mode, 850 .num_modes = 1, 851 .bpc = 6, 852 .size = { 853 .width = 152, 854 .height = 91, 855 }, 856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 858 }; 859 860 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 861 .clock = 32260, 862 .hdisplay = 800, 863 .hsync_start = 800 + 168, 864 .hsync_end = 800 + 168 + 64, 865 .htotal = 800 + 168 + 64 + 88, 866 .vdisplay = 480, 867 .vsync_start = 480 + 37, 868 .vsync_end = 480 + 37 + 2, 869 .vtotal = 480 + 37 + 2 + 8, 870 .vrefresh = 60, 871 }; 872 873 static const struct panel_desc foxlink_fl500wvr00_a0t = { 874 .modes = &foxlink_fl500wvr00_a0t_mode, 875 .num_modes = 1, 876 .bpc = 8, 877 .size = { 878 .width = 108, 879 .height = 65, 880 }, 881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 882 }; 883 884 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 885 .clock = 9000, 886 .hdisplay = 480, 887 .hsync_start = 480 + 5, 888 .hsync_end = 480 + 5 + 1, 889 .htotal = 480 + 5 + 1 + 40, 890 .vdisplay = 272, 891 .vsync_start = 272 + 8, 892 .vsync_end = 272 + 8 + 1, 893 .vtotal = 272 + 8 + 1 + 8, 894 .vrefresh = 60, 895 }; 896 897 static const struct panel_desc giantplus_gpg482739qs5 = { 898 .modes = &giantplus_gpg482739qs5_mode, 899 .num_modes = 1, 900 .bpc = 8, 901 .size = { 902 .width = 95, 903 .height = 54, 904 }, 905 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 906 }; 907 908 static const struct display_timing hannstar_hsd070pww1_timing = { 909 .pixelclock = { 64300000, 71100000, 82000000 }, 910 .hactive = { 1280, 1280, 1280 }, 911 .hfront_porch = { 1, 1, 10 }, 912 .hback_porch = { 1, 1, 10 }, 913 /* 914 * According to the data sheet, the minimum horizontal blanking interval 915 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 916 * minimum working horizontal blanking interval to be 60 clocks. 917 */ 918 .hsync_len = { 58, 158, 661 }, 919 .vactive = { 800, 800, 800 }, 920 .vfront_porch = { 1, 1, 10 }, 921 .vback_porch = { 1, 1, 10 }, 922 .vsync_len = { 1, 21, 203 }, 923 .flags = DISPLAY_FLAGS_DE_HIGH, 924 }; 925 926 static const struct panel_desc hannstar_hsd070pww1 = { 927 .timings = &hannstar_hsd070pww1_timing, 928 .num_timings = 1, 929 .bpc = 6, 930 .size = { 931 .width = 151, 932 .height = 94, 933 }, 934 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 935 }; 936 937 static const struct display_timing hannstar_hsd100pxn1_timing = { 938 .pixelclock = { 55000000, 65000000, 75000000 }, 939 .hactive = { 1024, 1024, 1024 }, 940 .hfront_porch = { 40, 40, 40 }, 941 .hback_porch = { 220, 220, 220 }, 942 .hsync_len = { 20, 60, 100 }, 943 .vactive = { 768, 768, 768 }, 944 .vfront_porch = { 7, 7, 7 }, 945 .vback_porch = { 21, 21, 21 }, 946 .vsync_len = { 10, 10, 10 }, 947 .flags = DISPLAY_FLAGS_DE_HIGH, 948 }; 949 950 static const struct panel_desc hannstar_hsd100pxn1 = { 951 .timings = &hannstar_hsd100pxn1_timing, 952 .num_timings = 1, 953 .bpc = 6, 954 .size = { 955 .width = 203, 956 .height = 152, 957 }, 958 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 959 }; 960 961 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 962 .clock = 33333, 963 .hdisplay = 800, 964 .hsync_start = 800 + 85, 965 .hsync_end = 800 + 85 + 86, 966 .htotal = 800 + 85 + 86 + 85, 967 .vdisplay = 480, 968 .vsync_start = 480 + 16, 969 .vsync_end = 480 + 16 + 13, 970 .vtotal = 480 + 16 + 13 + 16, 971 .vrefresh = 60, 972 }; 973 974 static const struct panel_desc hitachi_tx23d38vm0caa = { 975 .modes = &hitachi_tx23d38vm0caa_mode, 976 .num_modes = 1, 977 .bpc = 6, 978 .size = { 979 .width = 195, 980 .height = 117, 981 }, 982 }; 983 984 static const struct drm_display_mode innolux_at043tn24_mode = { 985 .clock = 9000, 986 .hdisplay = 480, 987 .hsync_start = 480 + 2, 988 .hsync_end = 480 + 2 + 41, 989 .htotal = 480 + 2 + 41 + 2, 990 .vdisplay = 272, 991 .vsync_start = 272 + 2, 992 .vsync_end = 272 + 2 + 11, 993 .vtotal = 272 + 2 + 11 + 2, 994 .vrefresh = 60, 995 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 996 }; 997 998 static const struct panel_desc innolux_at043tn24 = { 999 .modes = &innolux_at043tn24_mode, 1000 .num_modes = 1, 1001 .bpc = 8, 1002 .size = { 1003 .width = 95, 1004 .height = 54, 1005 }, 1006 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1007 }; 1008 1009 static const struct drm_display_mode innolux_at070tn92_mode = { 1010 .clock = 33333, 1011 .hdisplay = 800, 1012 .hsync_start = 800 + 210, 1013 .hsync_end = 800 + 210 + 20, 1014 .htotal = 800 + 210 + 20 + 46, 1015 .vdisplay = 480, 1016 .vsync_start = 480 + 22, 1017 .vsync_end = 480 + 22 + 10, 1018 .vtotal = 480 + 22 + 23 + 10, 1019 .vrefresh = 60, 1020 }; 1021 1022 static const struct panel_desc innolux_at070tn92 = { 1023 .modes = &innolux_at070tn92_mode, 1024 .num_modes = 1, 1025 .size = { 1026 .width = 154, 1027 .height = 86, 1028 }, 1029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1030 }; 1031 1032 static const struct display_timing innolux_g101ice_l01_timing = { 1033 .pixelclock = { 60400000, 71100000, 74700000 }, 1034 .hactive = { 1280, 1280, 1280 }, 1035 .hfront_porch = { 41, 80, 100 }, 1036 .hback_porch = { 40, 79, 99 }, 1037 .hsync_len = { 1, 1, 1 }, 1038 .vactive = { 800, 800, 800 }, 1039 .vfront_porch = { 5, 11, 14 }, 1040 .vback_porch = { 4, 11, 14 }, 1041 .vsync_len = { 1, 1, 1 }, 1042 .flags = DISPLAY_FLAGS_DE_HIGH, 1043 }; 1044 1045 static const struct panel_desc innolux_g101ice_l01 = { 1046 .timings = &innolux_g101ice_l01_timing, 1047 .num_timings = 1, 1048 .bpc = 8, 1049 .size = { 1050 .width = 217, 1051 .height = 135, 1052 }, 1053 .delay = { 1054 .enable = 200, 1055 .disable = 200, 1056 }, 1057 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1058 }; 1059 1060 static const struct display_timing innolux_g121i1_l01_timing = { 1061 .pixelclock = { 67450000, 71000000, 74550000 }, 1062 .hactive = { 1280, 1280, 1280 }, 1063 .hfront_porch = { 40, 80, 160 }, 1064 .hback_porch = { 39, 79, 159 }, 1065 .hsync_len = { 1, 1, 1 }, 1066 .vactive = { 800, 800, 800 }, 1067 .vfront_porch = { 5, 11, 100 }, 1068 .vback_porch = { 4, 11, 99 }, 1069 .vsync_len = { 1, 1, 1 }, 1070 }; 1071 1072 static const struct panel_desc innolux_g121i1_l01 = { 1073 .timings = &innolux_g121i1_l01_timing, 1074 .num_timings = 1, 1075 .bpc = 6, 1076 .size = { 1077 .width = 261, 1078 .height = 163, 1079 }, 1080 .delay = { 1081 .enable = 200, 1082 .disable = 20, 1083 }, 1084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1085 }; 1086 1087 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1088 .clock = 65000, 1089 .hdisplay = 1024, 1090 .hsync_start = 1024 + 0, 1091 .hsync_end = 1024 + 1, 1092 .htotal = 1024 + 0 + 1 + 320, 1093 .vdisplay = 768, 1094 .vsync_start = 768 + 38, 1095 .vsync_end = 768 + 38 + 1, 1096 .vtotal = 768 + 38 + 1 + 0, 1097 .vrefresh = 60, 1098 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1099 }; 1100 1101 static const struct panel_desc innolux_g121x1_l03 = { 1102 .modes = &innolux_g121x1_l03_mode, 1103 .num_modes = 1, 1104 .bpc = 6, 1105 .size = { 1106 .width = 246, 1107 .height = 185, 1108 }, 1109 .delay = { 1110 .enable = 200, 1111 .unprepare = 200, 1112 .disable = 400, 1113 }, 1114 }; 1115 1116 static const struct drm_display_mode innolux_n116bge_mode = { 1117 .clock = 76420, 1118 .hdisplay = 1366, 1119 .hsync_start = 1366 + 136, 1120 .hsync_end = 1366 + 136 + 30, 1121 .htotal = 1366 + 136 + 30 + 60, 1122 .vdisplay = 768, 1123 .vsync_start = 768 + 8, 1124 .vsync_end = 768 + 8 + 12, 1125 .vtotal = 768 + 8 + 12 + 12, 1126 .vrefresh = 60, 1127 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1128 }; 1129 1130 static const struct panel_desc innolux_n116bge = { 1131 .modes = &innolux_n116bge_mode, 1132 .num_modes = 1, 1133 .bpc = 6, 1134 .size = { 1135 .width = 256, 1136 .height = 144, 1137 }, 1138 }; 1139 1140 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1141 .clock = 69300, 1142 .hdisplay = 1366, 1143 .hsync_start = 1366 + 16, 1144 .hsync_end = 1366 + 16 + 34, 1145 .htotal = 1366 + 16 + 34 + 50, 1146 .vdisplay = 768, 1147 .vsync_start = 768 + 2, 1148 .vsync_end = 768 + 2 + 6, 1149 .vtotal = 768 + 2 + 6 + 12, 1150 .vrefresh = 60, 1151 }; 1152 1153 static const struct panel_desc innolux_n156bge_l21 = { 1154 .modes = &innolux_n156bge_l21_mode, 1155 .num_modes = 1, 1156 .bpc = 6, 1157 .size = { 1158 .width = 344, 1159 .height = 193, 1160 }, 1161 }; 1162 1163 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1164 .clock = 51501, 1165 .hdisplay = 1024, 1166 .hsync_start = 1024 + 128, 1167 .hsync_end = 1024 + 128 + 64, 1168 .htotal = 1024 + 128 + 64 + 128, 1169 .vdisplay = 600, 1170 .vsync_start = 600 + 16, 1171 .vsync_end = 600 + 16 + 4, 1172 .vtotal = 600 + 16 + 4 + 16, 1173 .vrefresh = 60, 1174 }; 1175 1176 static const struct panel_desc innolux_zj070na_01p = { 1177 .modes = &innolux_zj070na_01p_mode, 1178 .num_modes = 1, 1179 .bpc = 6, 1180 .size = { 1181 .width = 154, 1182 .height = 90, 1183 }, 1184 }; 1185 1186 static const struct display_timing kyo_tcg121xglp_timing = { 1187 .pixelclock = { 52000000, 65000000, 71000000 }, 1188 .hactive = { 1024, 1024, 1024 }, 1189 .hfront_porch = { 2, 2, 2 }, 1190 .hback_porch = { 2, 2, 2 }, 1191 .hsync_len = { 86, 124, 244 }, 1192 .vactive = { 768, 768, 768 }, 1193 .vfront_porch = { 2, 2, 2 }, 1194 .vback_porch = { 2, 2, 2 }, 1195 .vsync_len = { 6, 34, 73 }, 1196 .flags = DISPLAY_FLAGS_DE_HIGH, 1197 }; 1198 1199 static const struct panel_desc kyo_tcg121xglp = { 1200 .timings = &kyo_tcg121xglp_timing, 1201 .num_timings = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 246, 1205 .height = 184, 1206 }, 1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1208 }; 1209 1210 static const struct drm_display_mode lg_lb070wv8_mode = { 1211 .clock = 33246, 1212 .hdisplay = 800, 1213 .hsync_start = 800 + 88, 1214 .hsync_end = 800 + 88 + 80, 1215 .htotal = 800 + 88 + 80 + 88, 1216 .vdisplay = 480, 1217 .vsync_start = 480 + 10, 1218 .vsync_end = 480 + 10 + 25, 1219 .vtotal = 480 + 10 + 25 + 10, 1220 .vrefresh = 60, 1221 }; 1222 1223 static const struct panel_desc lg_lb070wv8 = { 1224 .modes = &lg_lb070wv8_mode, 1225 .num_modes = 1, 1226 .bpc = 16, 1227 .size = { 1228 .width = 151, 1229 .height = 91, 1230 }, 1231 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1232 }; 1233 1234 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1235 .clock = 200000, 1236 .hdisplay = 1536, 1237 .hsync_start = 1536 + 12, 1238 .hsync_end = 1536 + 12 + 16, 1239 .htotal = 1536 + 12 + 16 + 48, 1240 .vdisplay = 2048, 1241 .vsync_start = 2048 + 8, 1242 .vsync_end = 2048 + 8 + 4, 1243 .vtotal = 2048 + 8 + 4 + 8, 1244 .vrefresh = 60, 1245 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1246 }; 1247 1248 static const struct panel_desc lg_lp079qx1_sp0v = { 1249 .modes = &lg_lp079qx1_sp0v_mode, 1250 .num_modes = 1, 1251 .size = { 1252 .width = 129, 1253 .height = 171, 1254 }, 1255 }; 1256 1257 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1258 .clock = 205210, 1259 .hdisplay = 2048, 1260 .hsync_start = 2048 + 150, 1261 .hsync_end = 2048 + 150 + 5, 1262 .htotal = 2048 + 150 + 5 + 5, 1263 .vdisplay = 1536, 1264 .vsync_start = 1536 + 3, 1265 .vsync_end = 1536 + 3 + 1, 1266 .vtotal = 1536 + 3 + 1 + 9, 1267 .vrefresh = 60, 1268 }; 1269 1270 static const struct panel_desc lg_lp097qx1_spa1 = { 1271 .modes = &lg_lp097qx1_spa1_mode, 1272 .num_modes = 1, 1273 .size = { 1274 .width = 208, 1275 .height = 147, 1276 }, 1277 }; 1278 1279 static const struct drm_display_mode lg_lp120up1_mode = { 1280 .clock = 162300, 1281 .hdisplay = 1920, 1282 .hsync_start = 1920 + 40, 1283 .hsync_end = 1920 + 40 + 40, 1284 .htotal = 1920 + 40 + 40+ 80, 1285 .vdisplay = 1280, 1286 .vsync_start = 1280 + 4, 1287 .vsync_end = 1280 + 4 + 4, 1288 .vtotal = 1280 + 4 + 4 + 12, 1289 .vrefresh = 60, 1290 }; 1291 1292 static const struct panel_desc lg_lp120up1 = { 1293 .modes = &lg_lp120up1_mode, 1294 .num_modes = 1, 1295 .bpc = 8, 1296 .size = { 1297 .width = 267, 1298 .height = 183, 1299 }, 1300 }; 1301 1302 static const struct drm_display_mode lg_lp129qe_mode = { 1303 .clock = 285250, 1304 .hdisplay = 2560, 1305 .hsync_start = 2560 + 48, 1306 .hsync_end = 2560 + 48 + 32, 1307 .htotal = 2560 + 48 + 32 + 80, 1308 .vdisplay = 1700, 1309 .vsync_start = 1700 + 3, 1310 .vsync_end = 1700 + 3 + 10, 1311 .vtotal = 1700 + 3 + 10 + 36, 1312 .vrefresh = 60, 1313 }; 1314 1315 static const struct panel_desc lg_lp129qe = { 1316 .modes = &lg_lp129qe_mode, 1317 .num_modes = 1, 1318 .bpc = 8, 1319 .size = { 1320 .width = 272, 1321 .height = 181, 1322 }, 1323 }; 1324 1325 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1326 .clock = 10870, 1327 .hdisplay = 480, 1328 .hsync_start = 480 + 2, 1329 .hsync_end = 480 + 2 + 41, 1330 .htotal = 480 + 2 + 41 + 2, 1331 .vdisplay = 272, 1332 .vsync_start = 272 + 2, 1333 .vsync_end = 272 + 2 + 4, 1334 .vtotal = 272 + 2 + 4 + 2, 1335 .vrefresh = 74, 1336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1337 }; 1338 1339 static const struct panel_desc nec_nl4827hc19_05b = { 1340 .modes = &nec_nl4827hc19_05b_mode, 1341 .num_modes = 1, 1342 .bpc = 8, 1343 .size = { 1344 .width = 95, 1345 .height = 54, 1346 }, 1347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1348 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1349 }; 1350 1351 static const struct drm_display_mode netron_dy_e231732_mode = { 1352 .clock = 66000, 1353 .hdisplay = 1024, 1354 .hsync_start = 1024 + 160, 1355 .hsync_end = 1024 + 160 + 70, 1356 .htotal = 1024 + 160 + 70 + 90, 1357 .vdisplay = 600, 1358 .vsync_start = 600 + 127, 1359 .vsync_end = 600 + 127 + 20, 1360 .vtotal = 600 + 127 + 20 + 3, 1361 .vrefresh = 60, 1362 }; 1363 1364 static const struct panel_desc netron_dy_e231732 = { 1365 .modes = &netron_dy_e231732_mode, 1366 .num_modes = 1, 1367 .size = { 1368 .width = 154, 1369 .height = 87, 1370 }, 1371 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1372 }; 1373 1374 static const struct drm_display_mode nvd_9128_mode = { 1375 .clock = 29500, 1376 .hdisplay = 800, 1377 .hsync_start = 800 + 130, 1378 .hsync_end = 800 + 130 + 98, 1379 .htotal = 800 + 0 + 130 + 98, 1380 .vdisplay = 480, 1381 .vsync_start = 480 + 10, 1382 .vsync_end = 480 + 10 + 50, 1383 .vtotal = 480 + 0 + 10 + 50, 1384 }; 1385 1386 static const struct panel_desc nvd_9128 = { 1387 .modes = &nvd_9128_mode, 1388 .num_modes = 1, 1389 .bpc = 8, 1390 .size = { 1391 .width = 156, 1392 .height = 88, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1395 }; 1396 1397 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1398 .pixelclock = { 30000000, 30000000, 40000000 }, 1399 .hactive = { 800, 800, 800 }, 1400 .hfront_porch = { 40, 40, 40 }, 1401 .hback_porch = { 40, 40, 40 }, 1402 .hsync_len = { 1, 48, 48 }, 1403 .vactive = { 480, 480, 480 }, 1404 .vfront_porch = { 13, 13, 13 }, 1405 .vback_porch = { 29, 29, 29 }, 1406 .vsync_len = { 3, 3, 3 }, 1407 .flags = DISPLAY_FLAGS_DE_HIGH, 1408 }; 1409 1410 static const struct panel_desc okaya_rs800480t_7x0gp = { 1411 .timings = &okaya_rs800480t_7x0gp_timing, 1412 .num_timings = 1, 1413 .bpc = 6, 1414 .size = { 1415 .width = 154, 1416 .height = 87, 1417 }, 1418 .delay = { 1419 .prepare = 41, 1420 .enable = 50, 1421 .unprepare = 41, 1422 .disable = 50, 1423 }, 1424 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1425 }; 1426 1427 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1428 .clock = 9000, 1429 .hdisplay = 480, 1430 .hsync_start = 480 + 5, 1431 .hsync_end = 480 + 5 + 30, 1432 .htotal = 480 + 5 + 30 + 10, 1433 .vdisplay = 272, 1434 .vsync_start = 272 + 8, 1435 .vsync_end = 272 + 8 + 5, 1436 .vtotal = 272 + 8 + 5 + 3, 1437 .vrefresh = 60, 1438 }; 1439 1440 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1441 .modes = &olimex_lcd_olinuxino_43ts_mode, 1442 .num_modes = 1, 1443 .size = { 1444 .width = 105, 1445 .height = 67, 1446 }, 1447 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1448 }; 1449 1450 /* 1451 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1452 * pixel clocks, but this is the timing that was being used in the Adafruit 1453 * installation instructions. 1454 */ 1455 static const struct drm_display_mode ontat_yx700wv03_mode = { 1456 .clock = 29500, 1457 .hdisplay = 800, 1458 .hsync_start = 824, 1459 .hsync_end = 896, 1460 .htotal = 992, 1461 .vdisplay = 480, 1462 .vsync_start = 483, 1463 .vsync_end = 493, 1464 .vtotal = 500, 1465 .vrefresh = 60, 1466 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1467 }; 1468 1469 /* 1470 * Specification at: 1471 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1472 */ 1473 static const struct panel_desc ontat_yx700wv03 = { 1474 .modes = &ontat_yx700wv03_mode, 1475 .num_modes = 1, 1476 .bpc = 8, 1477 .size = { 1478 .width = 154, 1479 .height = 83, 1480 }, 1481 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1482 }; 1483 1484 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1485 .clock = 25000, 1486 .hdisplay = 480, 1487 .hsync_start = 480 + 10, 1488 .hsync_end = 480 + 10 + 10, 1489 .htotal = 480 + 10 + 10 + 15, 1490 .vdisplay = 800, 1491 .vsync_start = 800 + 3, 1492 .vsync_end = 800 + 3 + 3, 1493 .vtotal = 800 + 3 + 3 + 3, 1494 .vrefresh = 60, 1495 }; 1496 1497 static const struct panel_desc ortustech_com43h4m85ulc = { 1498 .modes = &ortustech_com43h4m85ulc_mode, 1499 .num_modes = 1, 1500 .bpc = 8, 1501 .size = { 1502 .width = 56, 1503 .height = 93, 1504 }, 1505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1506 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1507 }; 1508 1509 static const struct drm_display_mode qd43003c0_40_mode = { 1510 .clock = 9000, 1511 .hdisplay = 480, 1512 .hsync_start = 480 + 8, 1513 .hsync_end = 480 + 8 + 4, 1514 .htotal = 480 + 8 + 4 + 39, 1515 .vdisplay = 272, 1516 .vsync_start = 272 + 4, 1517 .vsync_end = 272 + 4 + 10, 1518 .vtotal = 272 + 4 + 10 + 2, 1519 .vrefresh = 60, 1520 }; 1521 1522 static const struct panel_desc qd43003c0_40 = { 1523 .modes = &qd43003c0_40_mode, 1524 .num_modes = 1, 1525 .bpc = 8, 1526 .size = { 1527 .width = 95, 1528 .height = 53, 1529 }, 1530 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1531 }; 1532 1533 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1534 .clock = 271560, 1535 .hdisplay = 2560, 1536 .hsync_start = 2560 + 48, 1537 .hsync_end = 2560 + 48 + 32, 1538 .htotal = 2560 + 48 + 32 + 80, 1539 .vdisplay = 1600, 1540 .vsync_start = 1600 + 2, 1541 .vsync_end = 1600 + 2 + 5, 1542 .vtotal = 1600 + 2 + 5 + 57, 1543 .vrefresh = 60, 1544 }; 1545 1546 static const struct panel_desc samsung_lsn122dl01_c01 = { 1547 .modes = &samsung_lsn122dl01_c01_mode, 1548 .num_modes = 1, 1549 .size = { 1550 .width = 263, 1551 .height = 164, 1552 }, 1553 }; 1554 1555 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1556 .clock = 54030, 1557 .hdisplay = 1024, 1558 .hsync_start = 1024 + 24, 1559 .hsync_end = 1024 + 24 + 136, 1560 .htotal = 1024 + 24 + 136 + 160, 1561 .vdisplay = 600, 1562 .vsync_start = 600 + 3, 1563 .vsync_end = 600 + 3 + 6, 1564 .vtotal = 600 + 3 + 6 + 61, 1565 .vrefresh = 60, 1566 }; 1567 1568 static const struct panel_desc samsung_ltn101nt05 = { 1569 .modes = &samsung_ltn101nt05_mode, 1570 .num_modes = 1, 1571 .bpc = 6, 1572 .size = { 1573 .width = 223, 1574 .height = 125, 1575 }, 1576 }; 1577 1578 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1579 .clock = 76300, 1580 .hdisplay = 1366, 1581 .hsync_start = 1366 + 64, 1582 .hsync_end = 1366 + 64 + 48, 1583 .htotal = 1366 + 64 + 48 + 128, 1584 .vdisplay = 768, 1585 .vsync_start = 768 + 2, 1586 .vsync_end = 768 + 2 + 5, 1587 .vtotal = 768 + 2 + 5 + 17, 1588 .vrefresh = 60, 1589 }; 1590 1591 static const struct panel_desc samsung_ltn140at29_301 = { 1592 .modes = &samsung_ltn140at29_301_mode, 1593 .num_modes = 1, 1594 .bpc = 6, 1595 .size = { 1596 .width = 320, 1597 .height = 187, 1598 }, 1599 }; 1600 1601 static const struct display_timing sharp_lq101k1ly04_timing = { 1602 .pixelclock = { 60000000, 65000000, 80000000 }, 1603 .hactive = { 1280, 1280, 1280 }, 1604 .hfront_porch = { 20, 20, 20 }, 1605 .hback_porch = { 20, 20, 20 }, 1606 .hsync_len = { 10, 10, 10 }, 1607 .vactive = { 800, 800, 800 }, 1608 .vfront_porch = { 4, 4, 4 }, 1609 .vback_porch = { 4, 4, 4 }, 1610 .vsync_len = { 4, 4, 4 }, 1611 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1612 }; 1613 1614 static const struct panel_desc sharp_lq101k1ly04 = { 1615 .timings = &sharp_lq101k1ly04_timing, 1616 .num_timings = 1, 1617 .bpc = 8, 1618 .size = { 1619 .width = 217, 1620 .height = 136, 1621 }, 1622 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1623 }; 1624 1625 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1626 .clock = 252750, 1627 .hdisplay = 2400, 1628 .hsync_start = 2400 + 48, 1629 .hsync_end = 2400 + 48 + 32, 1630 .htotal = 2400 + 48 + 32 + 80, 1631 .vdisplay = 1600, 1632 .vsync_start = 1600 + 3, 1633 .vsync_end = 1600 + 3 + 10, 1634 .vtotal = 1600 + 3 + 10 + 33, 1635 .vrefresh = 60, 1636 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1637 }; 1638 1639 static const struct panel_desc sharp_lq123p1jx31 = { 1640 .modes = &sharp_lq123p1jx31_mode, 1641 .num_modes = 1, 1642 .bpc = 8, 1643 .size = { 1644 .width = 259, 1645 .height = 173, 1646 }, 1647 .delay = { 1648 .prepare = 110, 1649 .enable = 50, 1650 .unprepare = 550, 1651 }, 1652 }; 1653 1654 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 1655 .clock = 71100, 1656 .hdisplay = 1024, 1657 .hsync_start = 1024 + 168, 1658 .hsync_end = 1024 + 168 + 64, 1659 .htotal = 1024 + 168 + 64 + 88, 1660 .vdisplay = 768, 1661 .vsync_start = 768 + 37, 1662 .vsync_end = 768 + 37 + 2, 1663 .vtotal = 768 + 37 + 2 + 8, 1664 .vrefresh = 60, 1665 }; 1666 1667 static const struct panel_desc sharp_lq150x1lg11 = { 1668 .modes = &sharp_lq150x1lg11_mode, 1669 .num_modes = 1, 1670 .bpc = 6, 1671 .size = { 1672 .width = 304, 1673 .height = 228, 1674 }, 1675 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 1676 }; 1677 1678 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1679 .clock = 33300, 1680 .hdisplay = 800, 1681 .hsync_start = 800 + 1, 1682 .hsync_end = 800 + 1 + 64, 1683 .htotal = 800 + 1 + 64 + 64, 1684 .vdisplay = 480, 1685 .vsync_start = 480 + 1, 1686 .vsync_end = 480 + 1 + 23, 1687 .vtotal = 480 + 1 + 23 + 22, 1688 .vrefresh = 60, 1689 }; 1690 1691 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1692 .modes = &shelly_sca07010_bfn_lnn_mode, 1693 .num_modes = 1, 1694 .size = { 1695 .width = 152, 1696 .height = 91, 1697 }, 1698 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1699 }; 1700 1701 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1702 .clock = 147000, 1703 .hdisplay = 1920, 1704 .hsync_start = 1920 + 16, 1705 .hsync_end = 1920 + 16 + 16, 1706 .htotal = 1920 + 16 + 16 + 32, 1707 .vdisplay = 1200, 1708 .vsync_start = 1200 + 15, 1709 .vsync_end = 1200 + 15 + 2, 1710 .vtotal = 1200 + 15 + 2 + 18, 1711 .vrefresh = 60, 1712 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1713 }; 1714 1715 static const struct panel_desc starry_kr122ea0sra = { 1716 .modes = &starry_kr122ea0sra_mode, 1717 .num_modes = 1, 1718 .size = { 1719 .width = 263, 1720 .height = 164, 1721 }, 1722 .delay = { 1723 .prepare = 10 + 200, 1724 .enable = 50, 1725 .unprepare = 10 + 500, 1726 }, 1727 }; 1728 1729 static const struct display_timing tianma_tm070jdhg30_timing = { 1730 .pixelclock = { 62600000, 68200000, 78100000 }, 1731 .hactive = { 1280, 1280, 1280 }, 1732 .hfront_porch = { 15, 64, 159 }, 1733 .hback_porch = { 5, 5, 5 }, 1734 .hsync_len = { 1, 1, 256 }, 1735 .vactive = { 800, 800, 800 }, 1736 .vfront_porch = { 3, 40, 99 }, 1737 .vback_porch = { 2, 2, 2 }, 1738 .vsync_len = { 1, 1, 128 }, 1739 .flags = DISPLAY_FLAGS_DE_HIGH, 1740 }; 1741 1742 static const struct panel_desc tianma_tm070jdhg30 = { 1743 .timings = &tianma_tm070jdhg30_timing, 1744 .num_timings = 1, 1745 .bpc = 8, 1746 .size = { 1747 .width = 151, 1748 .height = 95, 1749 }, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 }; 1752 1753 static const struct drm_display_mode tpk_f07a_0102_mode = { 1754 .clock = 33260, 1755 .hdisplay = 800, 1756 .hsync_start = 800 + 40, 1757 .hsync_end = 800 + 40 + 128, 1758 .htotal = 800 + 40 + 128 + 88, 1759 .vdisplay = 480, 1760 .vsync_start = 480 + 10, 1761 .vsync_end = 480 + 10 + 2, 1762 .vtotal = 480 + 10 + 2 + 33, 1763 .vrefresh = 60, 1764 }; 1765 1766 static const struct panel_desc tpk_f07a_0102 = { 1767 .modes = &tpk_f07a_0102_mode, 1768 .num_modes = 1, 1769 .size = { 1770 .width = 152, 1771 .height = 91, 1772 }, 1773 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1774 }; 1775 1776 static const struct drm_display_mode tpk_f10a_0102_mode = { 1777 .clock = 45000, 1778 .hdisplay = 1024, 1779 .hsync_start = 1024 + 176, 1780 .hsync_end = 1024 + 176 + 5, 1781 .htotal = 1024 + 176 + 5 + 88, 1782 .vdisplay = 600, 1783 .vsync_start = 600 + 20, 1784 .vsync_end = 600 + 20 + 5, 1785 .vtotal = 600 + 20 + 5 + 25, 1786 .vrefresh = 60, 1787 }; 1788 1789 static const struct panel_desc tpk_f10a_0102 = { 1790 .modes = &tpk_f10a_0102_mode, 1791 .num_modes = 1, 1792 .size = { 1793 .width = 223, 1794 .height = 125, 1795 }, 1796 }; 1797 1798 static const struct display_timing urt_umsh_8596md_timing = { 1799 .pixelclock = { 33260000, 33260000, 33260000 }, 1800 .hactive = { 800, 800, 800 }, 1801 .hfront_porch = { 41, 41, 41 }, 1802 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1803 .hsync_len = { 71, 128, 128 }, 1804 .vactive = { 480, 480, 480 }, 1805 .vfront_porch = { 10, 10, 10 }, 1806 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1807 .vsync_len = { 2, 2, 2 }, 1808 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1809 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1810 }; 1811 1812 static const struct panel_desc urt_umsh_8596md_lvds = { 1813 .timings = &urt_umsh_8596md_timing, 1814 .num_timings = 1, 1815 .bpc = 6, 1816 .size = { 1817 .width = 152, 1818 .height = 91, 1819 }, 1820 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1821 }; 1822 1823 static const struct panel_desc urt_umsh_8596md_parallel = { 1824 .timings = &urt_umsh_8596md_timing, 1825 .num_timings = 1, 1826 .bpc = 6, 1827 .size = { 1828 .width = 152, 1829 .height = 91, 1830 }, 1831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1832 }; 1833 1834 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 1835 .clock = 6410, 1836 .hdisplay = 320, 1837 .hsync_start = 320 + 20, 1838 .hsync_end = 320 + 20 + 30, 1839 .htotal = 320 + 20 + 30 + 38, 1840 .vdisplay = 240, 1841 .vsync_start = 240 + 4, 1842 .vsync_end = 240 + 4 + 3, 1843 .vtotal = 240 + 4 + 3 + 15, 1844 .vrefresh = 60, 1845 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1846 }; 1847 1848 static const struct panel_desc winstar_wf35ltiacd = { 1849 .modes = &winstar_wf35ltiacd_mode, 1850 .num_modes = 1, 1851 .bpc = 8, 1852 .size = { 1853 .width = 70, 1854 .height = 53, 1855 }, 1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1857 }; 1858 1859 static const struct of_device_id platform_of_match[] = { 1860 { 1861 .compatible = "ampire,am-480272h3tmqw-t01h", 1862 .data = &ire_am_480272h3tmqw_t01h, 1863 }, { 1864 .compatible = "ampire,am800480r3tmqwa1h", 1865 .data = &ire_am800480r3tmqwa1h, 1866 }, { 1867 .compatible = "auo,b101aw03", 1868 .data = &auo_b101aw03, 1869 }, { 1870 .compatible = "auo,b101ean01", 1871 .data = &auo_b101ean01, 1872 }, { 1873 .compatible = "auo,b101xtn01", 1874 .data = &auo_b101xtn01, 1875 }, { 1876 .compatible = "auo,b116xw03", 1877 .data = &auo_b116xw03, 1878 }, { 1879 .compatible = "auo,b133htn01", 1880 .data = &auo_b133htn01, 1881 }, { 1882 .compatible = "auo,b133xtn01", 1883 .data = &auo_b133xtn01, 1884 }, { 1885 .compatible = "auo,g133han01", 1886 .data = &auo_g133han01, 1887 }, { 1888 .compatible = "auo,g185han01", 1889 .data = &auo_g185han01, 1890 }, { 1891 .compatible = "auo,t215hvn01", 1892 .data = &auo_t215hvn01, 1893 }, { 1894 .compatible = "avic,tm070ddh03", 1895 .data = &avic_tm070ddh03, 1896 }, { 1897 .compatible = "boe,nv101wxmn51", 1898 .data = &boe_nv101wxmn51, 1899 }, { 1900 .compatible = "chunghwa,claa070wp03xg", 1901 .data = &chunghwa_claa070wp03xg, 1902 }, { 1903 .compatible = "chunghwa,claa101wa01a", 1904 .data = &chunghwa_claa101wa01a 1905 }, { 1906 .compatible = "chunghwa,claa101wb01", 1907 .data = &chunghwa_claa101wb01 1908 }, { 1909 .compatible = "edt,et057090dhu", 1910 .data = &edt_et057090dhu, 1911 }, { 1912 .compatible = "edt,et070080dh6", 1913 .data = &edt_etm0700g0dh6, 1914 }, { 1915 .compatible = "edt,etm0700g0dh6", 1916 .data = &edt_etm0700g0dh6, 1917 }, { 1918 .compatible = "foxlink,fl500wvr00-a0t", 1919 .data = &foxlink_fl500wvr00_a0t, 1920 }, { 1921 .compatible = "giantplus,gpg482739qs5", 1922 .data = &giantplus_gpg482739qs5 1923 }, { 1924 .compatible = "hannstar,hsd070pww1", 1925 .data = &hannstar_hsd070pww1, 1926 }, { 1927 .compatible = "hannstar,hsd100pxn1", 1928 .data = &hannstar_hsd100pxn1, 1929 }, { 1930 .compatible = "hit,tx23d38vm0caa", 1931 .data = &hitachi_tx23d38vm0caa 1932 }, { 1933 .compatible = "innolux,at043tn24", 1934 .data = &innolux_at043tn24, 1935 }, { 1936 .compatible = "innolux,at070tn92", 1937 .data = &innolux_at070tn92, 1938 }, { 1939 .compatible ="innolux,g101ice-l01", 1940 .data = &innolux_g101ice_l01 1941 }, { 1942 .compatible ="innolux,g121i1-l01", 1943 .data = &innolux_g121i1_l01 1944 }, { 1945 .compatible = "innolux,g121x1-l03", 1946 .data = &innolux_g121x1_l03, 1947 }, { 1948 .compatible = "innolux,n116bge", 1949 .data = &innolux_n116bge, 1950 }, { 1951 .compatible = "innolux,n156bge-l21", 1952 .data = &innolux_n156bge_l21, 1953 }, { 1954 .compatible = "innolux,zj070na-01p", 1955 .data = &innolux_zj070na_01p, 1956 }, { 1957 .compatible = "kyo,tcg121xglp", 1958 .data = &kyo_tcg121xglp, 1959 }, { 1960 .compatible = "lg,lb070wv8", 1961 .data = &lg_lb070wv8, 1962 }, { 1963 .compatible = "lg,lp079qx1-sp0v", 1964 .data = &lg_lp079qx1_sp0v, 1965 }, { 1966 .compatible = "lg,lp097qx1-spa1", 1967 .data = &lg_lp097qx1_spa1, 1968 }, { 1969 .compatible = "lg,lp120up1", 1970 .data = &lg_lp120up1, 1971 }, { 1972 .compatible = "lg,lp129qe", 1973 .data = &lg_lp129qe, 1974 }, { 1975 .compatible = "nec,nl4827hc19-05b", 1976 .data = &nec_nl4827hc19_05b, 1977 }, { 1978 .compatible = "netron-dy,e231732", 1979 .data = &netron_dy_e231732, 1980 }, { 1981 .compatible = "nvd,9128", 1982 .data = &nvd_9128, 1983 }, { 1984 .compatible = "okaya,rs800480t-7x0gp", 1985 .data = &okaya_rs800480t_7x0gp, 1986 }, { 1987 .compatible = "olimex,lcd-olinuxino-43-ts", 1988 .data = &olimex_lcd_olinuxino_43ts, 1989 }, { 1990 .compatible = "ontat,yx700wv03", 1991 .data = &ontat_yx700wv03, 1992 }, { 1993 .compatible = "ortustech,com43h4m85ulc", 1994 .data = &ortustech_com43h4m85ulc, 1995 }, { 1996 .compatible = "qiaodian,qd43003c0-40", 1997 .data = &qd43003c0_40, 1998 }, { 1999 .compatible = "samsung,lsn122dl01-c01", 2000 .data = &samsung_lsn122dl01_c01, 2001 }, { 2002 .compatible = "samsung,ltn101nt05", 2003 .data = &samsung_ltn101nt05, 2004 }, { 2005 .compatible = "samsung,ltn140at29-301", 2006 .data = &samsung_ltn140at29_301, 2007 }, { 2008 .compatible = "sharp,lq101k1ly04", 2009 .data = &sharp_lq101k1ly04, 2010 }, { 2011 .compatible = "sharp,lq123p1jx31", 2012 .data = &sharp_lq123p1jx31, 2013 }, { 2014 .compatible = "sharp,lq150x1lg11", 2015 .data = &sharp_lq150x1lg11, 2016 }, { 2017 .compatible = "shelly,sca07010-bfn-lnn", 2018 .data = &shelly_sca07010_bfn_lnn, 2019 }, { 2020 .compatible = "starry,kr122ea0sra", 2021 .data = &starry_kr122ea0sra, 2022 }, { 2023 .compatible = "tianma,tm070jdhg30", 2024 .data = &tianma_tm070jdhg30, 2025 }, { 2026 .compatible = "tpk,f07a-0102", 2027 .data = &tpk_f07a_0102, 2028 }, { 2029 .compatible = "tpk,f10a-0102", 2030 .data = &tpk_f10a_0102, 2031 }, { 2032 .compatible = "urt,umsh-8596md-t", 2033 .data = &urt_umsh_8596md_parallel, 2034 }, { 2035 .compatible = "urt,umsh-8596md-1t", 2036 .data = &urt_umsh_8596md_parallel, 2037 }, { 2038 .compatible = "urt,umsh-8596md-7t", 2039 .data = &urt_umsh_8596md_parallel, 2040 }, { 2041 .compatible = "urt,umsh-8596md-11t", 2042 .data = &urt_umsh_8596md_lvds, 2043 }, { 2044 .compatible = "urt,umsh-8596md-19t", 2045 .data = &urt_umsh_8596md_lvds, 2046 }, { 2047 .compatible = "urt,umsh-8596md-20t", 2048 .data = &urt_umsh_8596md_parallel, 2049 }, { 2050 .compatible = "winstar,wf35ltiacd", 2051 .data = &winstar_wf35ltiacd, 2052 }, { 2053 /* sentinel */ 2054 } 2055 }; 2056 MODULE_DEVICE_TABLE(of, platform_of_match); 2057 2058 static int panel_simple_platform_probe(struct platform_device *pdev) 2059 { 2060 const struct of_device_id *id; 2061 2062 id = of_match_node(platform_of_match, pdev->dev.of_node); 2063 if (!id) 2064 return -ENODEV; 2065 2066 return panel_simple_probe(&pdev->dev, id->data); 2067 } 2068 2069 static int panel_simple_platform_remove(struct platform_device *pdev) 2070 { 2071 return panel_simple_remove(&pdev->dev); 2072 } 2073 2074 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2075 { 2076 panel_simple_shutdown(&pdev->dev); 2077 } 2078 2079 static struct platform_driver panel_simple_platform_driver = { 2080 .driver = { 2081 .name = "panel-simple", 2082 .of_match_table = platform_of_match, 2083 }, 2084 .probe = panel_simple_platform_probe, 2085 .remove = panel_simple_platform_remove, 2086 .shutdown = panel_simple_platform_shutdown, 2087 }; 2088 2089 struct panel_desc_dsi { 2090 struct panel_desc desc; 2091 2092 unsigned long flags; 2093 enum mipi_dsi_pixel_format format; 2094 unsigned int lanes; 2095 }; 2096 2097 static const struct drm_display_mode auo_b080uan01_mode = { 2098 .clock = 154500, 2099 .hdisplay = 1200, 2100 .hsync_start = 1200 + 62, 2101 .hsync_end = 1200 + 62 + 4, 2102 .htotal = 1200 + 62 + 4 + 62, 2103 .vdisplay = 1920, 2104 .vsync_start = 1920 + 9, 2105 .vsync_end = 1920 + 9 + 2, 2106 .vtotal = 1920 + 9 + 2 + 8, 2107 .vrefresh = 60, 2108 }; 2109 2110 static const struct panel_desc_dsi auo_b080uan01 = { 2111 .desc = { 2112 .modes = &auo_b080uan01_mode, 2113 .num_modes = 1, 2114 .bpc = 8, 2115 .size = { 2116 .width = 108, 2117 .height = 272, 2118 }, 2119 }, 2120 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2121 .format = MIPI_DSI_FMT_RGB888, 2122 .lanes = 4, 2123 }; 2124 2125 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2126 .clock = 160000, 2127 .hdisplay = 1200, 2128 .hsync_start = 1200 + 120, 2129 .hsync_end = 1200 + 120 + 20, 2130 .htotal = 1200 + 120 + 20 + 21, 2131 .vdisplay = 1920, 2132 .vsync_start = 1920 + 21, 2133 .vsync_end = 1920 + 21 + 3, 2134 .vtotal = 1920 + 21 + 3 + 18, 2135 .vrefresh = 60, 2136 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2137 }; 2138 2139 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2140 .desc = { 2141 .modes = &boe_tv080wum_nl0_mode, 2142 .num_modes = 1, 2143 .size = { 2144 .width = 107, 2145 .height = 172, 2146 }, 2147 }, 2148 .flags = MIPI_DSI_MODE_VIDEO | 2149 MIPI_DSI_MODE_VIDEO_BURST | 2150 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2151 .format = MIPI_DSI_FMT_RGB888, 2152 .lanes = 4, 2153 }; 2154 2155 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2156 .clock = 71000, 2157 .hdisplay = 800, 2158 .hsync_start = 800 + 32, 2159 .hsync_end = 800 + 32 + 1, 2160 .htotal = 800 + 32 + 1 + 57, 2161 .vdisplay = 1280, 2162 .vsync_start = 1280 + 28, 2163 .vsync_end = 1280 + 28 + 1, 2164 .vtotal = 1280 + 28 + 1 + 14, 2165 .vrefresh = 60, 2166 }; 2167 2168 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2169 .desc = { 2170 .modes = &lg_ld070wx3_sl01_mode, 2171 .num_modes = 1, 2172 .bpc = 8, 2173 .size = { 2174 .width = 94, 2175 .height = 151, 2176 }, 2177 }, 2178 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2179 .format = MIPI_DSI_FMT_RGB888, 2180 .lanes = 4, 2181 }; 2182 2183 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2184 .clock = 67000, 2185 .hdisplay = 720, 2186 .hsync_start = 720 + 12, 2187 .hsync_end = 720 + 12 + 4, 2188 .htotal = 720 + 12 + 4 + 112, 2189 .vdisplay = 1280, 2190 .vsync_start = 1280 + 8, 2191 .vsync_end = 1280 + 8 + 4, 2192 .vtotal = 1280 + 8 + 4 + 12, 2193 .vrefresh = 60, 2194 }; 2195 2196 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2197 .desc = { 2198 .modes = &lg_lh500wx1_sd03_mode, 2199 .num_modes = 1, 2200 .bpc = 8, 2201 .size = { 2202 .width = 62, 2203 .height = 110, 2204 }, 2205 }, 2206 .flags = MIPI_DSI_MODE_VIDEO, 2207 .format = MIPI_DSI_FMT_RGB888, 2208 .lanes = 4, 2209 }; 2210 2211 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2212 .clock = 157200, 2213 .hdisplay = 1920, 2214 .hsync_start = 1920 + 154, 2215 .hsync_end = 1920 + 154 + 16, 2216 .htotal = 1920 + 154 + 16 + 32, 2217 .vdisplay = 1200, 2218 .vsync_start = 1200 + 17, 2219 .vsync_end = 1200 + 17 + 2, 2220 .vtotal = 1200 + 17 + 2 + 16, 2221 .vrefresh = 60, 2222 }; 2223 2224 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2225 .desc = { 2226 .modes = &panasonic_vvx10f004b00_mode, 2227 .num_modes = 1, 2228 .bpc = 8, 2229 .size = { 2230 .width = 217, 2231 .height = 136, 2232 }, 2233 }, 2234 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2235 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2236 .format = MIPI_DSI_FMT_RGB888, 2237 .lanes = 4, 2238 }; 2239 2240 static const struct of_device_id dsi_of_match[] = { 2241 { 2242 .compatible = "auo,b080uan01", 2243 .data = &auo_b080uan01 2244 }, { 2245 .compatible = "boe,tv080wum-nl0", 2246 .data = &boe_tv080wum_nl0 2247 }, { 2248 .compatible = "lg,ld070wx3-sl01", 2249 .data = &lg_ld070wx3_sl01 2250 }, { 2251 .compatible = "lg,lh500wx1-sd03", 2252 .data = &lg_lh500wx1_sd03 2253 }, { 2254 .compatible = "panasonic,vvx10f004b00", 2255 .data = &panasonic_vvx10f004b00 2256 }, { 2257 /* sentinel */ 2258 } 2259 }; 2260 MODULE_DEVICE_TABLE(of, dsi_of_match); 2261 2262 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2263 { 2264 const struct panel_desc_dsi *desc; 2265 const struct of_device_id *id; 2266 int err; 2267 2268 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2269 if (!id) 2270 return -ENODEV; 2271 2272 desc = id->data; 2273 2274 err = panel_simple_probe(&dsi->dev, &desc->desc); 2275 if (err < 0) 2276 return err; 2277 2278 dsi->mode_flags = desc->flags; 2279 dsi->format = desc->format; 2280 dsi->lanes = desc->lanes; 2281 2282 return mipi_dsi_attach(dsi); 2283 } 2284 2285 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2286 { 2287 int err; 2288 2289 err = mipi_dsi_detach(dsi); 2290 if (err < 0) 2291 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2292 2293 return panel_simple_remove(&dsi->dev); 2294 } 2295 2296 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2297 { 2298 panel_simple_shutdown(&dsi->dev); 2299 } 2300 2301 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2302 .driver = { 2303 .name = "panel-simple-dsi", 2304 .of_match_table = dsi_of_match, 2305 }, 2306 .probe = panel_simple_dsi_probe, 2307 .remove = panel_simple_dsi_remove, 2308 .shutdown = panel_simple_dsi_shutdown, 2309 }; 2310 2311 static int __init panel_simple_init(void) 2312 { 2313 int err; 2314 2315 err = platform_driver_register(&panel_simple_platform_driver); 2316 if (err < 0) 2317 return err; 2318 2319 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2320 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2321 if (err < 0) 2322 return err; 2323 } 2324 2325 return 0; 2326 } 2327 module_init(panel_simple_init); 2328 2329 static void __exit panel_simple_exit(void) 2330 { 2331 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2332 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2333 2334 platform_driver_unregister(&panel_simple_platform_driver); 2335 } 2336 module_exit(panel_simple_exit); 2337 2338 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2339 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2340 MODULE_LICENSE("GPL and additional rights"); 2341