1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/regulator/consumer.h> 32 33 #include <video/display_timing.h> 34 #include <video/of_display_timing.h> 35 #include <video/videomode.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_device.h> 39 #include <drm/drm_dp_aux_bus.h> 40 #include <drm/drm_dp_helper.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up. 99 * 100 * Add this to the prepare delay if we know Hot Plug Detect 101 * isn't used. 102 */ 103 unsigned int hpd_absent_delay; 104 105 /** 106 * @delay.prepare_to_enable: Time between prepare and enable. 107 * 108 * The minimum time, in milliseconds, that needs to have passed 109 * between when prepare finished and enable may begin. If at 110 * enable time less time has passed since prepare finished, 111 * the driver waits for the remaining time. 112 * 113 * If a fixed enable delay is also specified, we'll start 114 * counting before delaying for the fixed delay. 115 * 116 * If a fixed prepare delay is also specified, we won't start 117 * counting until after the fixed delay. We can't overlap this 118 * fixed delay with the min time because the fixed delay 119 * doesn't happen at the end of the function if a HPD GPIO was 120 * specified. 121 * 122 * In other words: 123 * prepare() 124 * ... 125 * // do fixed prepare delay 126 * // wait for HPD GPIO if applicable 127 * // start counting for prepare_to_enable 128 * 129 * enable() 130 * // do fixed enable delay 131 * // enforce prepare_to_enable min time 132 */ 133 unsigned int prepare_to_enable; 134 135 /** 136 * @delay.enable: Time for the panel to display a valid frame. 137 * 138 * The time (in milliseconds) that it takes for the panel to 139 * display the first valid frame after starting to receive 140 * video data. 141 */ 142 unsigned int enable; 143 144 /** 145 * @delay.disable: Time for the panel to turn the display off. 146 * 147 * The time (in milliseconds) that it takes for the panel to 148 * turn the display off (no content is visible). 149 */ 150 unsigned int disable; 151 152 /** 153 * @delay.unprepare: Time to power down completely. 154 * 155 * The time (in milliseconds) that it takes for the panel 156 * to power itself down completely. 157 * 158 * This time is used to prevent a future "prepare" from 159 * starting until at least this many milliseconds has passed. 160 * If at prepare time less time has passed since unprepare 161 * finished, the driver waits for the remaining time. 162 */ 163 unsigned int unprepare; 164 } delay; 165 166 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 167 u32 bus_format; 168 169 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 170 u32 bus_flags; 171 172 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 173 int connector_type; 174 }; 175 176 struct panel_simple { 177 struct drm_panel base; 178 bool enabled; 179 bool no_hpd; 180 181 bool prepared; 182 183 ktime_t prepared_time; 184 ktime_t unprepared_time; 185 186 const struct panel_desc *desc; 187 188 struct regulator *supply; 189 struct i2c_adapter *ddc; 190 struct drm_dp_aux *aux; 191 192 struct gpio_desc *enable_gpio; 193 struct gpio_desc *hpd_gpio; 194 195 struct edid *edid; 196 197 struct drm_display_mode override_mode; 198 199 enum drm_panel_orientation orientation; 200 }; 201 202 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 203 { 204 return container_of(panel, struct panel_simple, base); 205 } 206 207 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 208 struct drm_connector *connector) 209 { 210 struct drm_display_mode *mode; 211 unsigned int i, num = 0; 212 213 for (i = 0; i < panel->desc->num_timings; i++) { 214 const struct display_timing *dt = &panel->desc->timings[i]; 215 struct videomode vm; 216 217 videomode_from_timing(dt, &vm); 218 mode = drm_mode_create(connector->dev); 219 if (!mode) { 220 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 221 dt->hactive.typ, dt->vactive.typ); 222 continue; 223 } 224 225 drm_display_mode_from_videomode(&vm, mode); 226 227 mode->type |= DRM_MODE_TYPE_DRIVER; 228 229 if (panel->desc->num_timings == 1) 230 mode->type |= DRM_MODE_TYPE_PREFERRED; 231 232 drm_mode_probed_add(connector, mode); 233 num++; 234 } 235 236 return num; 237 } 238 239 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 240 struct drm_connector *connector) 241 { 242 struct drm_display_mode *mode; 243 unsigned int i, num = 0; 244 245 for (i = 0; i < panel->desc->num_modes; i++) { 246 const struct drm_display_mode *m = &panel->desc->modes[i]; 247 248 mode = drm_mode_duplicate(connector->dev, m); 249 if (!mode) { 250 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 251 m->hdisplay, m->vdisplay, 252 drm_mode_vrefresh(m)); 253 continue; 254 } 255 256 mode->type |= DRM_MODE_TYPE_DRIVER; 257 258 if (panel->desc->num_modes == 1) 259 mode->type |= DRM_MODE_TYPE_PREFERRED; 260 261 drm_mode_set_name(mode); 262 263 drm_mode_probed_add(connector, mode); 264 num++; 265 } 266 267 return num; 268 } 269 270 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 271 struct drm_connector *connector) 272 { 273 struct drm_display_mode *mode; 274 bool has_override = panel->override_mode.type; 275 unsigned int num = 0; 276 277 if (!panel->desc) 278 return 0; 279 280 if (has_override) { 281 mode = drm_mode_duplicate(connector->dev, 282 &panel->override_mode); 283 if (mode) { 284 drm_mode_probed_add(connector, mode); 285 num = 1; 286 } else { 287 dev_err(panel->base.dev, "failed to add override mode\n"); 288 } 289 } 290 291 /* Only add timings if override was not there or failed to validate */ 292 if (num == 0 && panel->desc->num_timings) 293 num = panel_simple_get_timings_modes(panel, connector); 294 295 /* 296 * Only add fixed modes if timings/override added no mode. 297 * 298 * We should only ever have either the display timings specified 299 * or a fixed mode. Anything else is rather bogus. 300 */ 301 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 302 if (num == 0) 303 num = panel_simple_get_display_modes(panel, connector); 304 305 connector->display_info.bpc = panel->desc->bpc; 306 connector->display_info.width_mm = panel->desc->size.width; 307 connector->display_info.height_mm = panel->desc->size.height; 308 if (panel->desc->bus_format) 309 drm_display_info_set_bus_formats(&connector->display_info, 310 &panel->desc->bus_format, 1); 311 connector->display_info.bus_flags = panel->desc->bus_flags; 312 313 return num; 314 } 315 316 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 317 { 318 ktime_t now_ktime, min_ktime; 319 320 if (!min_ms) 321 return; 322 323 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 324 now_ktime = ktime_get(); 325 326 if (ktime_before(now_ktime, min_ktime)) 327 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 328 } 329 330 static int panel_simple_disable(struct drm_panel *panel) 331 { 332 struct panel_simple *p = to_panel_simple(panel); 333 334 if (!p->enabled) 335 return 0; 336 337 if (p->desc->delay.disable) 338 msleep(p->desc->delay.disable); 339 340 p->enabled = false; 341 342 return 0; 343 } 344 345 static int panel_simple_suspend(struct device *dev) 346 { 347 struct panel_simple *p = dev_get_drvdata(dev); 348 349 gpiod_set_value_cansleep(p->enable_gpio, 0); 350 regulator_disable(p->supply); 351 p->unprepared_time = ktime_get(); 352 353 kfree(p->edid); 354 p->edid = NULL; 355 356 return 0; 357 } 358 359 static int panel_simple_unprepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Unpreparing when already unprepared is a no-op */ 365 if (!p->prepared) 366 return 0; 367 368 pm_runtime_mark_last_busy(panel->dev); 369 ret = pm_runtime_put_autosuspend(panel->dev); 370 if (ret < 0) 371 return ret; 372 p->prepared = false; 373 374 return 0; 375 } 376 377 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p) 378 { 379 int err; 380 381 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 382 if (IS_ERR(p->hpd_gpio)) { 383 err = PTR_ERR(p->hpd_gpio); 384 385 if (err != -EPROBE_DEFER) 386 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 387 388 return err; 389 } 390 391 return 0; 392 } 393 394 static int panel_simple_prepare_once(struct panel_simple *p) 395 { 396 struct device *dev = p->base.dev; 397 unsigned int delay; 398 int err; 399 int hpd_asserted; 400 unsigned long hpd_wait_us; 401 402 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 403 404 err = regulator_enable(p->supply); 405 if (err < 0) { 406 dev_err(dev, "failed to enable supply: %d\n", err); 407 return err; 408 } 409 410 gpiod_set_value_cansleep(p->enable_gpio, 1); 411 412 delay = p->desc->delay.prepare; 413 if (p->no_hpd) 414 delay += p->desc->delay.hpd_absent_delay; 415 if (delay) 416 msleep(delay); 417 418 if (p->hpd_gpio) { 419 if (p->desc->delay.hpd_absent_delay) 420 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL; 421 else 422 hpd_wait_us = 2000000; 423 424 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 425 hpd_asserted, hpd_asserted, 426 1000, hpd_wait_us); 427 if (hpd_asserted < 0) 428 err = hpd_asserted; 429 430 if (err) { 431 if (err != -ETIMEDOUT) 432 dev_err(dev, 433 "error waiting for hpd GPIO: %d\n", err); 434 goto error; 435 } 436 } 437 438 p->prepared_time = ktime_get(); 439 440 return 0; 441 442 error: 443 gpiod_set_value_cansleep(p->enable_gpio, 0); 444 regulator_disable(p->supply); 445 p->unprepared_time = ktime_get(); 446 447 return err; 448 } 449 450 /* 451 * Some panels simply don't always come up and need to be power cycled to 452 * work properly. We'll allow for a handful of retries. 453 */ 454 #define MAX_PANEL_PREPARE_TRIES 5 455 456 static int panel_simple_resume(struct device *dev) 457 { 458 struct panel_simple *p = dev_get_drvdata(dev); 459 int ret; 460 int try; 461 462 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) { 463 ret = panel_simple_prepare_once(p); 464 if (ret != -ETIMEDOUT) 465 break; 466 } 467 468 if (ret == -ETIMEDOUT) 469 dev_err(dev, "Prepare timeout after %d tries\n", try); 470 else if (try) 471 dev_warn(dev, "Prepare needed %d retries\n", try); 472 473 return ret; 474 } 475 476 static int panel_simple_prepare(struct drm_panel *panel) 477 { 478 struct panel_simple *p = to_panel_simple(panel); 479 int ret; 480 481 /* Preparing when already prepared is a no-op */ 482 if (p->prepared) 483 return 0; 484 485 ret = pm_runtime_get_sync(panel->dev); 486 if (ret < 0) { 487 pm_runtime_put_autosuspend(panel->dev); 488 return ret; 489 } 490 491 p->prepared = true; 492 493 return 0; 494 } 495 496 static int panel_simple_enable(struct drm_panel *panel) 497 { 498 struct panel_simple *p = to_panel_simple(panel); 499 500 if (p->enabled) 501 return 0; 502 503 if (p->desc->delay.enable) 504 msleep(p->desc->delay.enable); 505 506 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable); 507 508 p->enabled = true; 509 510 return 0; 511 } 512 513 static int panel_simple_get_modes(struct drm_panel *panel, 514 struct drm_connector *connector) 515 { 516 struct panel_simple *p = to_panel_simple(panel); 517 int num = 0; 518 519 /* probe EDID if a DDC bus is available */ 520 if (p->ddc) { 521 pm_runtime_get_sync(panel->dev); 522 523 if (!p->edid) 524 p->edid = drm_get_edid(connector, p->ddc); 525 526 if (p->edid) 527 num += drm_add_edid_modes(connector, p->edid); 528 529 pm_runtime_mark_last_busy(panel->dev); 530 pm_runtime_put_autosuspend(panel->dev); 531 } 532 533 /* add hard-coded panel modes */ 534 num += panel_simple_get_non_edid_modes(p, connector); 535 536 /* set up connector's "panel orientation" property */ 537 drm_connector_set_panel_orientation(connector, p->orientation); 538 539 return num; 540 } 541 542 static int panel_simple_get_timings(struct drm_panel *panel, 543 unsigned int num_timings, 544 struct display_timing *timings) 545 { 546 struct panel_simple *p = to_panel_simple(panel); 547 unsigned int i; 548 549 if (p->desc->num_timings < num_timings) 550 num_timings = p->desc->num_timings; 551 552 if (timings) 553 for (i = 0; i < num_timings; i++) 554 timings[i] = p->desc->timings[i]; 555 556 return p->desc->num_timings; 557 } 558 559 static const struct drm_panel_funcs panel_simple_funcs = { 560 .disable = panel_simple_disable, 561 .unprepare = panel_simple_unprepare, 562 .prepare = panel_simple_prepare, 563 .enable = panel_simple_enable, 564 .get_modes = panel_simple_get_modes, 565 .get_timings = panel_simple_get_timings, 566 }; 567 568 static struct panel_desc panel_dpi; 569 570 static int panel_dpi_probe(struct device *dev, 571 struct panel_simple *panel) 572 { 573 struct display_timing *timing; 574 const struct device_node *np; 575 struct panel_desc *desc; 576 unsigned int bus_flags; 577 struct videomode vm; 578 int ret; 579 580 np = dev->of_node; 581 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 582 if (!desc) 583 return -ENOMEM; 584 585 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 586 if (!timing) 587 return -ENOMEM; 588 589 ret = of_get_display_timing(np, "panel-timing", timing); 590 if (ret < 0) { 591 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 592 np); 593 return ret; 594 } 595 596 desc->timings = timing; 597 desc->num_timings = 1; 598 599 of_property_read_u32(np, "width-mm", &desc->size.width); 600 of_property_read_u32(np, "height-mm", &desc->size.height); 601 602 /* Extract bus_flags from display_timing */ 603 bus_flags = 0; 604 vm.flags = timing->flags; 605 drm_bus_flags_from_videomode(&vm, &bus_flags); 606 desc->bus_flags = bus_flags; 607 608 /* We do not know the connector for the DT node, so guess it */ 609 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 610 611 panel->desc = desc; 612 613 return 0; 614 } 615 616 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 617 (to_check->field.typ >= bounds->field.min && \ 618 to_check->field.typ <= bounds->field.max) 619 static void panel_simple_parse_panel_timing_node(struct device *dev, 620 struct panel_simple *panel, 621 const struct display_timing *ot) 622 { 623 const struct panel_desc *desc = panel->desc; 624 struct videomode vm; 625 unsigned int i; 626 627 if (WARN_ON(desc->num_modes)) { 628 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 629 return; 630 } 631 if (WARN_ON(!desc->num_timings)) { 632 dev_err(dev, "Reject override mode: no timings specified\n"); 633 return; 634 } 635 636 for (i = 0; i < panel->desc->num_timings; i++) { 637 const struct display_timing *dt = &panel->desc->timings[i]; 638 639 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 640 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 641 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 642 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 643 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 644 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 645 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 646 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 647 continue; 648 649 if (ot->flags != dt->flags) 650 continue; 651 652 videomode_from_timing(ot, &vm); 653 drm_display_mode_from_videomode(&vm, &panel->override_mode); 654 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 655 DRM_MODE_TYPE_PREFERRED; 656 break; 657 } 658 659 if (WARN_ON(!panel->override_mode.type)) 660 dev_err(dev, "Reject override mode: No display_timing found\n"); 661 } 662 663 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc, 664 struct drm_dp_aux *aux) 665 { 666 struct panel_simple *panel; 667 struct display_timing dt; 668 struct device_node *ddc; 669 int connector_type; 670 u32 bus_flags; 671 int err; 672 673 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 674 if (!panel) 675 return -ENOMEM; 676 677 panel->enabled = false; 678 panel->prepared_time = 0; 679 panel->desc = desc; 680 panel->aux = aux; 681 682 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 683 if (!panel->no_hpd) { 684 err = panel_simple_get_hpd_gpio(dev, panel); 685 if (err) 686 return err; 687 } 688 689 panel->supply = devm_regulator_get(dev, "power"); 690 if (IS_ERR(panel->supply)) 691 return PTR_ERR(panel->supply); 692 693 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 694 GPIOD_OUT_LOW); 695 if (IS_ERR(panel->enable_gpio)) { 696 err = PTR_ERR(panel->enable_gpio); 697 if (err != -EPROBE_DEFER) 698 dev_err(dev, "failed to request GPIO: %d\n", err); 699 return err; 700 } 701 702 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 703 if (err) { 704 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 705 return err; 706 } 707 708 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 709 if (ddc) { 710 panel->ddc = of_find_i2c_adapter_by_node(ddc); 711 of_node_put(ddc); 712 713 if (!panel->ddc) 714 return -EPROBE_DEFER; 715 } else if (aux) { 716 panel->ddc = &aux->ddc; 717 } 718 719 if (desc == &panel_dpi) { 720 /* Handle the generic panel-dpi binding */ 721 err = panel_dpi_probe(dev, panel); 722 if (err) 723 goto free_ddc; 724 } else { 725 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 726 panel_simple_parse_panel_timing_node(dev, panel, &dt); 727 } 728 729 connector_type = desc->connector_type; 730 /* Catch common mistakes for panels. */ 731 switch (connector_type) { 732 case 0: 733 dev_warn(dev, "Specify missing connector_type\n"); 734 connector_type = DRM_MODE_CONNECTOR_DPI; 735 break; 736 case DRM_MODE_CONNECTOR_LVDS: 737 WARN_ON(desc->bus_flags & 738 ~(DRM_BUS_FLAG_DE_LOW | 739 DRM_BUS_FLAG_DE_HIGH | 740 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 741 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 742 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 743 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 744 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 745 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 746 desc->bpc != 6); 747 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 748 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 749 desc->bpc != 8); 750 break; 751 case DRM_MODE_CONNECTOR_eDP: 752 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10) 753 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc); 754 break; 755 case DRM_MODE_CONNECTOR_DSI: 756 if (desc->bpc != 6 && desc->bpc != 8) 757 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 758 break; 759 case DRM_MODE_CONNECTOR_DPI: 760 bus_flags = DRM_BUS_FLAG_DE_LOW | 761 DRM_BUS_FLAG_DE_HIGH | 762 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 763 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 764 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 765 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 766 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 767 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 768 if (desc->bus_flags & ~bus_flags) 769 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 770 if (!(desc->bus_flags & bus_flags)) 771 dev_warn(dev, "Specify missing bus_flags\n"); 772 if (desc->bus_format == 0) 773 dev_warn(dev, "Specify missing bus_format\n"); 774 if (desc->bpc != 6 && desc->bpc != 8) 775 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 776 break; 777 default: 778 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 779 connector_type = DRM_MODE_CONNECTOR_DPI; 780 break; 781 } 782 783 dev_set_drvdata(dev, panel); 784 785 /* 786 * We use runtime PM for prepare / unprepare since those power the panel 787 * on and off and those can be very slow operations. This is important 788 * to optimize powering the panel on briefly to read the EDID before 789 * fully enabling the panel. 790 */ 791 pm_runtime_enable(dev); 792 pm_runtime_set_autosuspend_delay(dev, 1000); 793 pm_runtime_use_autosuspend(dev); 794 795 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 796 797 err = drm_panel_of_backlight(&panel->base); 798 if (err) 799 goto disable_pm_runtime; 800 801 if (!panel->base.backlight && panel->aux) { 802 pm_runtime_get_sync(dev); 803 err = drm_panel_dp_aux_backlight(&panel->base, panel->aux); 804 pm_runtime_mark_last_busy(dev); 805 pm_runtime_put_autosuspend(dev); 806 if (err) 807 goto disable_pm_runtime; 808 } 809 810 drm_panel_add(&panel->base); 811 812 return 0; 813 814 disable_pm_runtime: 815 pm_runtime_dont_use_autosuspend(dev); 816 pm_runtime_disable(dev); 817 free_ddc: 818 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc)) 819 put_device(&panel->ddc->dev); 820 821 return err; 822 } 823 824 static int panel_simple_remove(struct device *dev) 825 { 826 struct panel_simple *panel = dev_get_drvdata(dev); 827 828 drm_panel_remove(&panel->base); 829 drm_panel_disable(&panel->base); 830 drm_panel_unprepare(&panel->base); 831 832 pm_runtime_dont_use_autosuspend(dev); 833 pm_runtime_disable(dev); 834 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc)) 835 put_device(&panel->ddc->dev); 836 837 return 0; 838 } 839 840 static void panel_simple_shutdown(struct device *dev) 841 { 842 struct panel_simple *panel = dev_get_drvdata(dev); 843 844 drm_panel_disable(&panel->base); 845 drm_panel_unprepare(&panel->base); 846 } 847 848 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 849 .clock = 71100, 850 .hdisplay = 1280, 851 .hsync_start = 1280 + 40, 852 .hsync_end = 1280 + 40 + 80, 853 .htotal = 1280 + 40 + 80 + 40, 854 .vdisplay = 800, 855 .vsync_start = 800 + 3, 856 .vsync_end = 800 + 3 + 10, 857 .vtotal = 800 + 3 + 10 + 10, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 862 .modes = &ire_am_1280800n3tzqw_t00h_mode, 863 .num_modes = 1, 864 .bpc = 6, 865 .size = { 866 .width = 217, 867 .height = 136, 868 }, 869 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 872 }; 873 874 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 875 .clock = 9000, 876 .hdisplay = 480, 877 .hsync_start = 480 + 2, 878 .hsync_end = 480 + 2 + 41, 879 .htotal = 480 + 2 + 41 + 2, 880 .vdisplay = 272, 881 .vsync_start = 272 + 2, 882 .vsync_end = 272 + 2 + 10, 883 .vtotal = 272 + 2 + 10 + 2, 884 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 885 }; 886 887 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 888 .modes = &ire_am_480272h3tmqw_t01h_mode, 889 .num_modes = 1, 890 .bpc = 8, 891 .size = { 892 .width = 105, 893 .height = 67, 894 }, 895 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 896 }; 897 898 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 899 .clock = 33333, 900 .hdisplay = 800, 901 .hsync_start = 800 + 0, 902 .hsync_end = 800 + 0 + 255, 903 .htotal = 800 + 0 + 255 + 0, 904 .vdisplay = 480, 905 .vsync_start = 480 + 2, 906 .vsync_end = 480 + 2 + 45, 907 .vtotal = 480 + 2 + 45 + 0, 908 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 909 }; 910 911 static const struct panel_desc ampire_am800480r3tmqwa1h = { 912 .modes = &ire_am800480r3tmqwa1h_mode, 913 .num_modes = 1, 914 .bpc = 6, 915 .size = { 916 .width = 152, 917 .height = 91, 918 }, 919 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 920 }; 921 922 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 923 .pixelclock = { 26400000, 33300000, 46800000 }, 924 .hactive = { 800, 800, 800 }, 925 .hfront_porch = { 16, 210, 354 }, 926 .hback_porch = { 45, 36, 6 }, 927 .hsync_len = { 1, 10, 40 }, 928 .vactive = { 480, 480, 480 }, 929 .vfront_porch = { 7, 22, 147 }, 930 .vback_porch = { 22, 13, 3 }, 931 .vsync_len = { 1, 10, 20 }, 932 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 933 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 934 }; 935 936 static const struct panel_desc armadeus_st0700_adapt = { 937 .timings = &santek_st0700i5y_rbslw_f_timing, 938 .num_timings = 1, 939 .bpc = 6, 940 .size = { 941 .width = 154, 942 .height = 86, 943 }, 944 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 946 }; 947 948 static const struct drm_display_mode auo_b101aw03_mode = { 949 .clock = 51450, 950 .hdisplay = 1024, 951 .hsync_start = 1024 + 156, 952 .hsync_end = 1024 + 156 + 8, 953 .htotal = 1024 + 156 + 8 + 156, 954 .vdisplay = 600, 955 .vsync_start = 600 + 16, 956 .vsync_end = 600 + 16 + 6, 957 .vtotal = 600 + 16 + 6 + 16, 958 }; 959 960 static const struct panel_desc auo_b101aw03 = { 961 .modes = &auo_b101aw03_mode, 962 .num_modes = 1, 963 .bpc = 6, 964 .size = { 965 .width = 223, 966 .height = 125, 967 }, 968 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 969 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 970 .connector_type = DRM_MODE_CONNECTOR_LVDS, 971 }; 972 973 static const struct display_timing auo_b101ean01_timing = { 974 .pixelclock = { 65300000, 72500000, 75000000 }, 975 .hactive = { 1280, 1280, 1280 }, 976 .hfront_porch = { 18, 119, 119 }, 977 .hback_porch = { 21, 21, 21 }, 978 .hsync_len = { 32, 32, 32 }, 979 .vactive = { 800, 800, 800 }, 980 .vfront_porch = { 4, 4, 4 }, 981 .vback_porch = { 8, 8, 8 }, 982 .vsync_len = { 18, 20, 20 }, 983 }; 984 985 static const struct panel_desc auo_b101ean01 = { 986 .timings = &auo_b101ean01_timing, 987 .num_timings = 1, 988 .bpc = 6, 989 .size = { 990 .width = 217, 991 .height = 136, 992 }, 993 }; 994 995 static const struct drm_display_mode auo_b101xtn01_mode = { 996 .clock = 72000, 997 .hdisplay = 1366, 998 .hsync_start = 1366 + 20, 999 .hsync_end = 1366 + 20 + 70, 1000 .htotal = 1366 + 20 + 70, 1001 .vdisplay = 768, 1002 .vsync_start = 768 + 14, 1003 .vsync_end = 768 + 14 + 42, 1004 .vtotal = 768 + 14 + 42, 1005 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1006 }; 1007 1008 static const struct panel_desc auo_b101xtn01 = { 1009 .modes = &auo_b101xtn01_mode, 1010 .num_modes = 1, 1011 .bpc = 6, 1012 .size = { 1013 .width = 223, 1014 .height = 125, 1015 }, 1016 }; 1017 1018 static const struct drm_display_mode auo_b116xak01_mode = { 1019 .clock = 69300, 1020 .hdisplay = 1366, 1021 .hsync_start = 1366 + 48, 1022 .hsync_end = 1366 + 48 + 32, 1023 .htotal = 1366 + 48 + 32 + 10, 1024 .vdisplay = 768, 1025 .vsync_start = 768 + 4, 1026 .vsync_end = 768 + 4 + 6, 1027 .vtotal = 768 + 4 + 6 + 15, 1028 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1029 }; 1030 1031 static const struct panel_desc auo_b116xak01 = { 1032 .modes = &auo_b116xak01_mode, 1033 .num_modes = 1, 1034 .bpc = 6, 1035 .size = { 1036 .width = 256, 1037 .height = 144, 1038 }, 1039 .delay = { 1040 .hpd_absent_delay = 200, 1041 }, 1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1043 .connector_type = DRM_MODE_CONNECTOR_eDP, 1044 }; 1045 1046 static const struct drm_display_mode auo_b116xw03_mode = { 1047 .clock = 70589, 1048 .hdisplay = 1366, 1049 .hsync_start = 1366 + 40, 1050 .hsync_end = 1366 + 40 + 40, 1051 .htotal = 1366 + 40 + 40 + 32, 1052 .vdisplay = 768, 1053 .vsync_start = 768 + 10, 1054 .vsync_end = 768 + 10 + 12, 1055 .vtotal = 768 + 10 + 12 + 6, 1056 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1057 }; 1058 1059 static const struct panel_desc auo_b116xw03 = { 1060 .modes = &auo_b116xw03_mode, 1061 .num_modes = 1, 1062 .bpc = 6, 1063 .size = { 1064 .width = 256, 1065 .height = 144, 1066 }, 1067 .delay = { 1068 .enable = 400, 1069 }, 1070 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 1071 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1072 .connector_type = DRM_MODE_CONNECTOR_eDP, 1073 }; 1074 1075 static const struct drm_display_mode auo_b133xtn01_mode = { 1076 .clock = 69500, 1077 .hdisplay = 1366, 1078 .hsync_start = 1366 + 48, 1079 .hsync_end = 1366 + 48 + 32, 1080 .htotal = 1366 + 48 + 32 + 20, 1081 .vdisplay = 768, 1082 .vsync_start = 768 + 3, 1083 .vsync_end = 768 + 3 + 6, 1084 .vtotal = 768 + 3 + 6 + 13, 1085 }; 1086 1087 static const struct panel_desc auo_b133xtn01 = { 1088 .modes = &auo_b133xtn01_mode, 1089 .num_modes = 1, 1090 .bpc = 6, 1091 .size = { 1092 .width = 293, 1093 .height = 165, 1094 }, 1095 }; 1096 1097 static const struct drm_display_mode auo_b133han05_mode = { 1098 .clock = 142600, 1099 .hdisplay = 1920, 1100 .hsync_start = 1920 + 58, 1101 .hsync_end = 1920 + 58 + 42, 1102 .htotal = 1920 + 58 + 42 + 60, 1103 .vdisplay = 1080, 1104 .vsync_start = 1080 + 3, 1105 .vsync_end = 1080 + 3 + 5, 1106 .vtotal = 1080 + 3 + 5 + 54, 1107 }; 1108 1109 static const struct panel_desc auo_b133han05 = { 1110 .modes = &auo_b133han05_mode, 1111 .num_modes = 1, 1112 .bpc = 8, 1113 .size = { 1114 .width = 293, 1115 .height = 165, 1116 }, 1117 .delay = { 1118 .prepare = 100, 1119 .enable = 20, 1120 .unprepare = 50, 1121 }, 1122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1123 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1124 .connector_type = DRM_MODE_CONNECTOR_eDP, 1125 }; 1126 1127 static const struct drm_display_mode auo_b133htn01_mode = { 1128 .clock = 150660, 1129 .hdisplay = 1920, 1130 .hsync_start = 1920 + 172, 1131 .hsync_end = 1920 + 172 + 80, 1132 .htotal = 1920 + 172 + 80 + 60, 1133 .vdisplay = 1080, 1134 .vsync_start = 1080 + 25, 1135 .vsync_end = 1080 + 25 + 10, 1136 .vtotal = 1080 + 25 + 10 + 10, 1137 }; 1138 1139 static const struct panel_desc auo_b133htn01 = { 1140 .modes = &auo_b133htn01_mode, 1141 .num_modes = 1, 1142 .bpc = 6, 1143 .size = { 1144 .width = 293, 1145 .height = 165, 1146 }, 1147 .delay = { 1148 .prepare = 105, 1149 .enable = 20, 1150 .unprepare = 50, 1151 }, 1152 }; 1153 1154 static const struct drm_display_mode auo_b140han06_mode = { 1155 .clock = 141000, 1156 .hdisplay = 1920, 1157 .hsync_start = 1920 + 16, 1158 .hsync_end = 1920 + 16 + 16, 1159 .htotal = 1920 + 16 + 16 + 152, 1160 .vdisplay = 1080, 1161 .vsync_start = 1080 + 3, 1162 .vsync_end = 1080 + 3 + 14, 1163 .vtotal = 1080 + 3 + 14 + 19, 1164 }; 1165 1166 static const struct panel_desc auo_b140han06 = { 1167 .modes = &auo_b140han06_mode, 1168 .num_modes = 1, 1169 .bpc = 8, 1170 .size = { 1171 .width = 309, 1172 .height = 174, 1173 }, 1174 .delay = { 1175 .prepare = 100, 1176 .enable = 20, 1177 .unprepare = 50, 1178 }, 1179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1180 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1181 .connector_type = DRM_MODE_CONNECTOR_eDP, 1182 }; 1183 1184 static const struct display_timing auo_g070vvn01_timings = { 1185 .pixelclock = { 33300000, 34209000, 45000000 }, 1186 .hactive = { 800, 800, 800 }, 1187 .hfront_porch = { 20, 40, 200 }, 1188 .hback_porch = { 87, 40, 1 }, 1189 .hsync_len = { 1, 48, 87 }, 1190 .vactive = { 480, 480, 480 }, 1191 .vfront_porch = { 5, 13, 200 }, 1192 .vback_porch = { 31, 31, 29 }, 1193 .vsync_len = { 1, 1, 3 }, 1194 }; 1195 1196 static const struct panel_desc auo_g070vvn01 = { 1197 .timings = &auo_g070vvn01_timings, 1198 .num_timings = 1, 1199 .bpc = 8, 1200 .size = { 1201 .width = 152, 1202 .height = 91, 1203 }, 1204 .delay = { 1205 .prepare = 200, 1206 .enable = 50, 1207 .disable = 50, 1208 .unprepare = 1000, 1209 }, 1210 }; 1211 1212 static const struct drm_display_mode auo_g101evn010_mode = { 1213 .clock = 68930, 1214 .hdisplay = 1280, 1215 .hsync_start = 1280 + 82, 1216 .hsync_end = 1280 + 82 + 2, 1217 .htotal = 1280 + 82 + 2 + 84, 1218 .vdisplay = 800, 1219 .vsync_start = 800 + 8, 1220 .vsync_end = 800 + 8 + 2, 1221 .vtotal = 800 + 8 + 2 + 6, 1222 }; 1223 1224 static const struct panel_desc auo_g101evn010 = { 1225 .modes = &auo_g101evn010_mode, 1226 .num_modes = 1, 1227 .bpc = 6, 1228 .size = { 1229 .width = 216, 1230 .height = 135, 1231 }, 1232 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1233 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1234 }; 1235 1236 static const struct drm_display_mode auo_g104sn02_mode = { 1237 .clock = 40000, 1238 .hdisplay = 800, 1239 .hsync_start = 800 + 40, 1240 .hsync_end = 800 + 40 + 216, 1241 .htotal = 800 + 40 + 216 + 128, 1242 .vdisplay = 600, 1243 .vsync_start = 600 + 10, 1244 .vsync_end = 600 + 10 + 35, 1245 .vtotal = 600 + 10 + 35 + 2, 1246 }; 1247 1248 static const struct panel_desc auo_g104sn02 = { 1249 .modes = &auo_g104sn02_mode, 1250 .num_modes = 1, 1251 .bpc = 8, 1252 .size = { 1253 .width = 211, 1254 .height = 158, 1255 }, 1256 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1257 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1258 }; 1259 1260 static const struct drm_display_mode auo_g121ean01_mode = { 1261 .clock = 66700, 1262 .hdisplay = 1280, 1263 .hsync_start = 1280 + 58, 1264 .hsync_end = 1280 + 58 + 8, 1265 .htotal = 1280 + 58 + 8 + 70, 1266 .vdisplay = 800, 1267 .vsync_start = 800 + 6, 1268 .vsync_end = 800 + 6 + 4, 1269 .vtotal = 800 + 6 + 4 + 10, 1270 }; 1271 1272 static const struct panel_desc auo_g121ean01 = { 1273 .modes = &auo_g121ean01_mode, 1274 .num_modes = 1, 1275 .bpc = 8, 1276 .size = { 1277 .width = 261, 1278 .height = 163, 1279 }, 1280 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1281 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1282 }; 1283 1284 static const struct display_timing auo_g133han01_timings = { 1285 .pixelclock = { 134000000, 141200000, 149000000 }, 1286 .hactive = { 1920, 1920, 1920 }, 1287 .hfront_porch = { 39, 58, 77 }, 1288 .hback_porch = { 59, 88, 117 }, 1289 .hsync_len = { 28, 42, 56 }, 1290 .vactive = { 1080, 1080, 1080 }, 1291 .vfront_porch = { 3, 8, 11 }, 1292 .vback_porch = { 5, 14, 19 }, 1293 .vsync_len = { 4, 14, 19 }, 1294 }; 1295 1296 static const struct panel_desc auo_g133han01 = { 1297 .timings = &auo_g133han01_timings, 1298 .num_timings = 1, 1299 .bpc = 8, 1300 .size = { 1301 .width = 293, 1302 .height = 165, 1303 }, 1304 .delay = { 1305 .prepare = 200, 1306 .enable = 50, 1307 .disable = 50, 1308 .unprepare = 1000, 1309 }, 1310 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1311 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1312 }; 1313 1314 static const struct drm_display_mode auo_g156xtn01_mode = { 1315 .clock = 76000, 1316 .hdisplay = 1366, 1317 .hsync_start = 1366 + 33, 1318 .hsync_end = 1366 + 33 + 67, 1319 .htotal = 1560, 1320 .vdisplay = 768, 1321 .vsync_start = 768 + 4, 1322 .vsync_end = 768 + 4 + 4, 1323 .vtotal = 806, 1324 }; 1325 1326 static const struct panel_desc auo_g156xtn01 = { 1327 .modes = &auo_g156xtn01_mode, 1328 .num_modes = 1, 1329 .bpc = 8, 1330 .size = { 1331 .width = 344, 1332 .height = 194, 1333 }, 1334 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1335 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1336 }; 1337 1338 static const struct display_timing auo_g185han01_timings = { 1339 .pixelclock = { 120000000, 144000000, 175000000 }, 1340 .hactive = { 1920, 1920, 1920 }, 1341 .hfront_porch = { 36, 120, 148 }, 1342 .hback_porch = { 24, 88, 108 }, 1343 .hsync_len = { 20, 48, 64 }, 1344 .vactive = { 1080, 1080, 1080 }, 1345 .vfront_porch = { 6, 10, 40 }, 1346 .vback_porch = { 2, 5, 20 }, 1347 .vsync_len = { 2, 5, 20 }, 1348 }; 1349 1350 static const struct panel_desc auo_g185han01 = { 1351 .timings = &auo_g185han01_timings, 1352 .num_timings = 1, 1353 .bpc = 8, 1354 .size = { 1355 .width = 409, 1356 .height = 230, 1357 }, 1358 .delay = { 1359 .prepare = 50, 1360 .enable = 200, 1361 .disable = 110, 1362 .unprepare = 1000, 1363 }, 1364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1365 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1366 }; 1367 1368 static const struct display_timing auo_g190ean01_timings = { 1369 .pixelclock = { 90000000, 108000000, 135000000 }, 1370 .hactive = { 1280, 1280, 1280 }, 1371 .hfront_porch = { 126, 184, 1266 }, 1372 .hback_porch = { 84, 122, 844 }, 1373 .hsync_len = { 70, 102, 704 }, 1374 .vactive = { 1024, 1024, 1024 }, 1375 .vfront_porch = { 4, 26, 76 }, 1376 .vback_porch = { 2, 8, 25 }, 1377 .vsync_len = { 2, 8, 25 }, 1378 }; 1379 1380 static const struct panel_desc auo_g190ean01 = { 1381 .timings = &auo_g190ean01_timings, 1382 .num_timings = 1, 1383 .bpc = 8, 1384 .size = { 1385 .width = 376, 1386 .height = 301, 1387 }, 1388 .delay = { 1389 .prepare = 50, 1390 .enable = 200, 1391 .disable = 110, 1392 .unprepare = 1000, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1396 }; 1397 1398 static const struct display_timing auo_p320hvn03_timings = { 1399 .pixelclock = { 106000000, 148500000, 164000000 }, 1400 .hactive = { 1920, 1920, 1920 }, 1401 .hfront_porch = { 25, 50, 130 }, 1402 .hback_porch = { 25, 50, 130 }, 1403 .hsync_len = { 20, 40, 105 }, 1404 .vactive = { 1080, 1080, 1080 }, 1405 .vfront_porch = { 8, 17, 150 }, 1406 .vback_porch = { 8, 17, 150 }, 1407 .vsync_len = { 4, 11, 100 }, 1408 }; 1409 1410 static const struct panel_desc auo_p320hvn03 = { 1411 .timings = &auo_p320hvn03_timings, 1412 .num_timings = 1, 1413 .bpc = 8, 1414 .size = { 1415 .width = 698, 1416 .height = 393, 1417 }, 1418 .delay = { 1419 .prepare = 1, 1420 .enable = 450, 1421 .unprepare = 500, 1422 }, 1423 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1425 }; 1426 1427 static const struct drm_display_mode auo_t215hvn01_mode = { 1428 .clock = 148800, 1429 .hdisplay = 1920, 1430 .hsync_start = 1920 + 88, 1431 .hsync_end = 1920 + 88 + 44, 1432 .htotal = 1920 + 88 + 44 + 148, 1433 .vdisplay = 1080, 1434 .vsync_start = 1080 + 4, 1435 .vsync_end = 1080 + 4 + 5, 1436 .vtotal = 1080 + 4 + 5 + 36, 1437 }; 1438 1439 static const struct panel_desc auo_t215hvn01 = { 1440 .modes = &auo_t215hvn01_mode, 1441 .num_modes = 1, 1442 .bpc = 8, 1443 .size = { 1444 .width = 430, 1445 .height = 270, 1446 }, 1447 .delay = { 1448 .disable = 5, 1449 .unprepare = 1000, 1450 } 1451 }; 1452 1453 static const struct drm_display_mode avic_tm070ddh03_mode = { 1454 .clock = 51200, 1455 .hdisplay = 1024, 1456 .hsync_start = 1024 + 160, 1457 .hsync_end = 1024 + 160 + 4, 1458 .htotal = 1024 + 160 + 4 + 156, 1459 .vdisplay = 600, 1460 .vsync_start = 600 + 17, 1461 .vsync_end = 600 + 17 + 1, 1462 .vtotal = 600 + 17 + 1 + 17, 1463 }; 1464 1465 static const struct panel_desc avic_tm070ddh03 = { 1466 .modes = &avic_tm070ddh03_mode, 1467 .num_modes = 1, 1468 .bpc = 8, 1469 .size = { 1470 .width = 154, 1471 .height = 90, 1472 }, 1473 .delay = { 1474 .prepare = 20, 1475 .enable = 200, 1476 .disable = 200, 1477 }, 1478 }; 1479 1480 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1481 .clock = 30000, 1482 .hdisplay = 800, 1483 .hsync_start = 800 + 40, 1484 .hsync_end = 800 + 40 + 48, 1485 .htotal = 800 + 40 + 48 + 40, 1486 .vdisplay = 480, 1487 .vsync_start = 480 + 13, 1488 .vsync_end = 480 + 13 + 3, 1489 .vtotal = 480 + 13 + 3 + 29, 1490 }; 1491 1492 static const struct panel_desc bananapi_s070wv20_ct16 = { 1493 .modes = &bananapi_s070wv20_ct16_mode, 1494 .num_modes = 1, 1495 .bpc = 6, 1496 .size = { 1497 .width = 154, 1498 .height = 86, 1499 }, 1500 }; 1501 1502 static const struct drm_display_mode boe_hv070wsa_mode = { 1503 .clock = 42105, 1504 .hdisplay = 1024, 1505 .hsync_start = 1024 + 30, 1506 .hsync_end = 1024 + 30 + 30, 1507 .htotal = 1024 + 30 + 30 + 30, 1508 .vdisplay = 600, 1509 .vsync_start = 600 + 10, 1510 .vsync_end = 600 + 10 + 10, 1511 .vtotal = 600 + 10 + 10 + 10, 1512 }; 1513 1514 static const struct panel_desc boe_hv070wsa = { 1515 .modes = &boe_hv070wsa_mode, 1516 .num_modes = 1, 1517 .bpc = 8, 1518 .size = { 1519 .width = 154, 1520 .height = 90, 1521 }, 1522 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1523 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1524 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1525 }; 1526 1527 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1528 { 1529 .clock = 71900, 1530 .hdisplay = 1280, 1531 .hsync_start = 1280 + 48, 1532 .hsync_end = 1280 + 48 + 32, 1533 .htotal = 1280 + 48 + 32 + 80, 1534 .vdisplay = 800, 1535 .vsync_start = 800 + 3, 1536 .vsync_end = 800 + 3 + 5, 1537 .vtotal = 800 + 3 + 5 + 24, 1538 }, 1539 { 1540 .clock = 57500, 1541 .hdisplay = 1280, 1542 .hsync_start = 1280 + 48, 1543 .hsync_end = 1280 + 48 + 32, 1544 .htotal = 1280 + 48 + 32 + 80, 1545 .vdisplay = 800, 1546 .vsync_start = 800 + 3, 1547 .vsync_end = 800 + 3 + 5, 1548 .vtotal = 800 + 3 + 5 + 24, 1549 }, 1550 }; 1551 1552 static const struct panel_desc boe_nv101wxmn51 = { 1553 .modes = boe_nv101wxmn51_modes, 1554 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1555 .bpc = 8, 1556 .size = { 1557 .width = 217, 1558 .height = 136, 1559 }, 1560 .delay = { 1561 .prepare = 210, 1562 .enable = 50, 1563 .unprepare = 160, 1564 }, 1565 }; 1566 1567 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = { 1568 { 1569 .clock = 207800, 1570 .hdisplay = 2160, 1571 .hsync_start = 2160 + 48, 1572 .hsync_end = 2160 + 48 + 32, 1573 .htotal = 2160 + 48 + 32 + 100, 1574 .vdisplay = 1440, 1575 .vsync_start = 1440 + 3, 1576 .vsync_end = 1440 + 3 + 6, 1577 .vtotal = 1440 + 3 + 6 + 31, 1578 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1579 }, 1580 { 1581 .clock = 138500, 1582 .hdisplay = 2160, 1583 .hsync_start = 2160 + 48, 1584 .hsync_end = 2160 + 48 + 32, 1585 .htotal = 2160 + 48 + 32 + 100, 1586 .vdisplay = 1440, 1587 .vsync_start = 1440 + 3, 1588 .vsync_end = 1440 + 3 + 6, 1589 .vtotal = 1440 + 3 + 6 + 31, 1590 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1591 }, 1592 }; 1593 1594 static const struct panel_desc boe_nv110wtm_n61 = { 1595 .modes = boe_nv110wtm_n61_modes, 1596 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes), 1597 .bpc = 8, 1598 .size = { 1599 .width = 233, 1600 .height = 155, 1601 }, 1602 .delay = { 1603 .hpd_absent_delay = 200, 1604 .prepare_to_enable = 80, 1605 .enable = 50, 1606 .unprepare = 500, 1607 }, 1608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1609 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1610 .connector_type = DRM_MODE_CONNECTOR_eDP, 1611 }; 1612 1613 /* Also used for boe_nv133fhm_n62 */ 1614 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1615 .clock = 147840, 1616 .hdisplay = 1920, 1617 .hsync_start = 1920 + 48, 1618 .hsync_end = 1920 + 48 + 32, 1619 .htotal = 1920 + 48 + 32 + 200, 1620 .vdisplay = 1080, 1621 .vsync_start = 1080 + 3, 1622 .vsync_end = 1080 + 3 + 6, 1623 .vtotal = 1080 + 3 + 6 + 31, 1624 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1625 }; 1626 1627 /* Also used for boe_nv133fhm_n62 */ 1628 static const struct panel_desc boe_nv133fhm_n61 = { 1629 .modes = &boe_nv133fhm_n61_modes, 1630 .num_modes = 1, 1631 .bpc = 6, 1632 .size = { 1633 .width = 294, 1634 .height = 165, 1635 }, 1636 .delay = { 1637 /* 1638 * When power is first given to the panel there's a short 1639 * spike on the HPD line. It was explained that this spike 1640 * was until the TCON data download was complete. On 1641 * one system this was measured at 8 ms. We'll put 15 ms 1642 * in the prepare delay just to be safe and take it away 1643 * from the hpd_absent_delay (which would otherwise be 200 ms) 1644 * to handle this. That means: 1645 * - If HPD isn't hooked up you still have 200 ms delay. 1646 * - If HPD is hooked up we won't try to look at it for the 1647 * first 15 ms. 1648 */ 1649 .prepare = 15, 1650 .hpd_absent_delay = 185, 1651 1652 .unprepare = 500, 1653 }, 1654 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1655 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1656 .connector_type = DRM_MODE_CONNECTOR_eDP, 1657 }; 1658 1659 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1660 { 1661 .clock = 148500, 1662 .hdisplay = 1920, 1663 .hsync_start = 1920 + 48, 1664 .hsync_end = 1920 + 48 + 32, 1665 .htotal = 2200, 1666 .vdisplay = 1080, 1667 .vsync_start = 1080 + 3, 1668 .vsync_end = 1080 + 3 + 5, 1669 .vtotal = 1125, 1670 }, 1671 }; 1672 1673 static const struct panel_desc boe_nv140fhmn49 = { 1674 .modes = boe_nv140fhmn49_modes, 1675 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1676 .bpc = 6, 1677 .size = { 1678 .width = 309, 1679 .height = 174, 1680 }, 1681 .delay = { 1682 .prepare = 210, 1683 .enable = 50, 1684 .unprepare = 160, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1687 .connector_type = DRM_MODE_CONNECTOR_eDP, 1688 }; 1689 1690 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1691 .clock = 9000, 1692 .hdisplay = 480, 1693 .hsync_start = 480 + 5, 1694 .hsync_end = 480 + 5 + 5, 1695 .htotal = 480 + 5 + 5 + 40, 1696 .vdisplay = 272, 1697 .vsync_start = 272 + 8, 1698 .vsync_end = 272 + 8 + 8, 1699 .vtotal = 272 + 8 + 8 + 8, 1700 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1701 }; 1702 1703 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1704 .modes = &cdtech_s043wq26h_ct7_mode, 1705 .num_modes = 1, 1706 .bpc = 8, 1707 .size = { 1708 .width = 95, 1709 .height = 54, 1710 }, 1711 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1712 }; 1713 1714 /* S070PWS19HP-FC21 2017/04/22 */ 1715 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1716 .clock = 51200, 1717 .hdisplay = 1024, 1718 .hsync_start = 1024 + 160, 1719 .hsync_end = 1024 + 160 + 20, 1720 .htotal = 1024 + 160 + 20 + 140, 1721 .vdisplay = 600, 1722 .vsync_start = 600 + 12, 1723 .vsync_end = 600 + 12 + 3, 1724 .vtotal = 600 + 12 + 3 + 20, 1725 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1726 }; 1727 1728 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1729 .modes = &cdtech_s070pws19hp_fc21_mode, 1730 .num_modes = 1, 1731 .bpc = 6, 1732 .size = { 1733 .width = 154, 1734 .height = 86, 1735 }, 1736 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1737 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1738 .connector_type = DRM_MODE_CONNECTOR_DPI, 1739 }; 1740 1741 /* S070SWV29HG-DC44 2017/09/21 */ 1742 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1743 .clock = 33300, 1744 .hdisplay = 800, 1745 .hsync_start = 800 + 210, 1746 .hsync_end = 800 + 210 + 2, 1747 .htotal = 800 + 210 + 2 + 44, 1748 .vdisplay = 480, 1749 .vsync_start = 480 + 22, 1750 .vsync_end = 480 + 22 + 2, 1751 .vtotal = 480 + 22 + 2 + 21, 1752 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1753 }; 1754 1755 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1756 .modes = &cdtech_s070swv29hg_dc44_mode, 1757 .num_modes = 1, 1758 .bpc = 6, 1759 .size = { 1760 .width = 154, 1761 .height = 86, 1762 }, 1763 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1765 .connector_type = DRM_MODE_CONNECTOR_DPI, 1766 }; 1767 1768 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1769 .clock = 35000, 1770 .hdisplay = 800, 1771 .hsync_start = 800 + 40, 1772 .hsync_end = 800 + 40 + 40, 1773 .htotal = 800 + 40 + 40 + 48, 1774 .vdisplay = 480, 1775 .vsync_start = 480 + 29, 1776 .vsync_end = 480 + 29 + 13, 1777 .vtotal = 480 + 29 + 13 + 3, 1778 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1779 }; 1780 1781 static const struct panel_desc cdtech_s070wv95_ct16 = { 1782 .modes = &cdtech_s070wv95_ct16_mode, 1783 .num_modes = 1, 1784 .bpc = 8, 1785 .size = { 1786 .width = 154, 1787 .height = 85, 1788 }, 1789 }; 1790 1791 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1792 .pixelclock = { 68900000, 71100000, 73400000 }, 1793 .hactive = { 1280, 1280, 1280 }, 1794 .hfront_porch = { 65, 80, 95 }, 1795 .hback_porch = { 64, 79, 94 }, 1796 .hsync_len = { 1, 1, 1 }, 1797 .vactive = { 800, 800, 800 }, 1798 .vfront_porch = { 7, 11, 14 }, 1799 .vback_porch = { 7, 11, 14 }, 1800 .vsync_len = { 1, 1, 1 }, 1801 .flags = DISPLAY_FLAGS_DE_HIGH, 1802 }; 1803 1804 static const struct panel_desc chefree_ch101olhlwh_002 = { 1805 .timings = &chefree_ch101olhlwh_002_timing, 1806 .num_timings = 1, 1807 .bpc = 8, 1808 .size = { 1809 .width = 217, 1810 .height = 135, 1811 }, 1812 .delay = { 1813 .enable = 200, 1814 .disable = 200, 1815 }, 1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1817 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1818 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1819 }; 1820 1821 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1822 .clock = 66770, 1823 .hdisplay = 800, 1824 .hsync_start = 800 + 49, 1825 .hsync_end = 800 + 49 + 33, 1826 .htotal = 800 + 49 + 33 + 17, 1827 .vdisplay = 1280, 1828 .vsync_start = 1280 + 1, 1829 .vsync_end = 1280 + 1 + 7, 1830 .vtotal = 1280 + 1 + 7 + 15, 1831 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1832 }; 1833 1834 static const struct panel_desc chunghwa_claa070wp03xg = { 1835 .modes = &chunghwa_claa070wp03xg_mode, 1836 .num_modes = 1, 1837 .bpc = 6, 1838 .size = { 1839 .width = 94, 1840 .height = 150, 1841 }, 1842 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1843 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1844 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1845 }; 1846 1847 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1848 .clock = 72070, 1849 .hdisplay = 1366, 1850 .hsync_start = 1366 + 58, 1851 .hsync_end = 1366 + 58 + 58, 1852 .htotal = 1366 + 58 + 58 + 58, 1853 .vdisplay = 768, 1854 .vsync_start = 768 + 4, 1855 .vsync_end = 768 + 4 + 4, 1856 .vtotal = 768 + 4 + 4 + 4, 1857 }; 1858 1859 static const struct panel_desc chunghwa_claa101wa01a = { 1860 .modes = &chunghwa_claa101wa01a_mode, 1861 .num_modes = 1, 1862 .bpc = 6, 1863 .size = { 1864 .width = 220, 1865 .height = 120, 1866 }, 1867 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1868 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1869 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1870 }; 1871 1872 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1873 .clock = 69300, 1874 .hdisplay = 1366, 1875 .hsync_start = 1366 + 48, 1876 .hsync_end = 1366 + 48 + 32, 1877 .htotal = 1366 + 48 + 32 + 20, 1878 .vdisplay = 768, 1879 .vsync_start = 768 + 16, 1880 .vsync_end = 768 + 16 + 8, 1881 .vtotal = 768 + 16 + 8 + 16, 1882 }; 1883 1884 static const struct panel_desc chunghwa_claa101wb01 = { 1885 .modes = &chunghwa_claa101wb01_mode, 1886 .num_modes = 1, 1887 .bpc = 6, 1888 .size = { 1889 .width = 223, 1890 .height = 125, 1891 }, 1892 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1893 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1894 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1895 }; 1896 1897 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1898 .clock = 33260, 1899 .hdisplay = 800, 1900 .hsync_start = 800 + 40, 1901 .hsync_end = 800 + 40 + 128, 1902 .htotal = 800 + 40 + 128 + 88, 1903 .vdisplay = 480, 1904 .vsync_start = 480 + 10, 1905 .vsync_end = 480 + 10 + 2, 1906 .vtotal = 480 + 10 + 2 + 33, 1907 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1908 }; 1909 1910 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1911 .modes = &dataimage_scf0700c48ggu18_mode, 1912 .num_modes = 1, 1913 .bpc = 8, 1914 .size = { 1915 .width = 152, 1916 .height = 91, 1917 }, 1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1920 }; 1921 1922 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1923 .pixelclock = { 45000000, 51200000, 57000000 }, 1924 .hactive = { 1024, 1024, 1024 }, 1925 .hfront_porch = { 100, 106, 113 }, 1926 .hback_porch = { 100, 106, 113 }, 1927 .hsync_len = { 100, 108, 114 }, 1928 .vactive = { 600, 600, 600 }, 1929 .vfront_porch = { 8, 11, 15 }, 1930 .vback_porch = { 8, 11, 15 }, 1931 .vsync_len = { 9, 13, 15 }, 1932 .flags = DISPLAY_FLAGS_DE_HIGH, 1933 }; 1934 1935 static const struct panel_desc dlc_dlc0700yzg_1 = { 1936 .timings = &dlc_dlc0700yzg_1_timing, 1937 .num_timings = 1, 1938 .bpc = 6, 1939 .size = { 1940 .width = 154, 1941 .height = 86, 1942 }, 1943 .delay = { 1944 .prepare = 30, 1945 .enable = 200, 1946 .disable = 200, 1947 }, 1948 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1950 }; 1951 1952 static const struct display_timing dlc_dlc1010gig_timing = { 1953 .pixelclock = { 68900000, 71100000, 73400000 }, 1954 .hactive = { 1280, 1280, 1280 }, 1955 .hfront_porch = { 43, 53, 63 }, 1956 .hback_porch = { 43, 53, 63 }, 1957 .hsync_len = { 44, 54, 64 }, 1958 .vactive = { 800, 800, 800 }, 1959 .vfront_porch = { 5, 8, 11 }, 1960 .vback_porch = { 5, 8, 11 }, 1961 .vsync_len = { 5, 7, 11 }, 1962 .flags = DISPLAY_FLAGS_DE_HIGH, 1963 }; 1964 1965 static const struct panel_desc dlc_dlc1010gig = { 1966 .timings = &dlc_dlc1010gig_timing, 1967 .num_timings = 1, 1968 .bpc = 8, 1969 .size = { 1970 .width = 216, 1971 .height = 135, 1972 }, 1973 .delay = { 1974 .prepare = 60, 1975 .enable = 150, 1976 .disable = 100, 1977 .unprepare = 60, 1978 }, 1979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1981 }; 1982 1983 static const struct drm_display_mode edt_et035012dm6_mode = { 1984 .clock = 6500, 1985 .hdisplay = 320, 1986 .hsync_start = 320 + 20, 1987 .hsync_end = 320 + 20 + 30, 1988 .htotal = 320 + 20 + 68, 1989 .vdisplay = 240, 1990 .vsync_start = 240 + 4, 1991 .vsync_end = 240 + 4 + 4, 1992 .vtotal = 240 + 4 + 4 + 14, 1993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1994 }; 1995 1996 static const struct panel_desc edt_et035012dm6 = { 1997 .modes = &edt_et035012dm6_mode, 1998 .num_modes = 1, 1999 .bpc = 8, 2000 .size = { 2001 .width = 70, 2002 .height = 52, 2003 }, 2004 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2005 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2006 }; 2007 2008 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 2009 .clock = 6520, 2010 .hdisplay = 320, 2011 .hsync_start = 320 + 20, 2012 .hsync_end = 320 + 20 + 68, 2013 .htotal = 320 + 20 + 68, 2014 .vdisplay = 240, 2015 .vsync_start = 240 + 4, 2016 .vsync_end = 240 + 4 + 18, 2017 .vtotal = 240 + 4 + 18, 2018 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2019 }; 2020 2021 static const struct panel_desc edt_etm0350g0dh6 = { 2022 .modes = &edt_etm0350g0dh6_mode, 2023 .num_modes = 1, 2024 .bpc = 6, 2025 .size = { 2026 .width = 70, 2027 .height = 53, 2028 }, 2029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2030 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2031 .connector_type = DRM_MODE_CONNECTOR_DPI, 2032 }; 2033 2034 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2035 .clock = 10870, 2036 .hdisplay = 480, 2037 .hsync_start = 480 + 8, 2038 .hsync_end = 480 + 8 + 4, 2039 .htotal = 480 + 8 + 4 + 41, 2040 2041 /* 2042 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2043 * fb_align 2044 */ 2045 2046 .vdisplay = 288, 2047 .vsync_start = 288 + 2, 2048 .vsync_end = 288 + 2 + 4, 2049 .vtotal = 288 + 2 + 4 + 10, 2050 }; 2051 2052 static const struct panel_desc edt_etm043080dh6gp = { 2053 .modes = &edt_etm043080dh6gp_mode, 2054 .num_modes = 1, 2055 .bpc = 8, 2056 .size = { 2057 .width = 100, 2058 .height = 65, 2059 }, 2060 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2061 .connector_type = DRM_MODE_CONNECTOR_DPI, 2062 }; 2063 2064 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2065 .clock = 9000, 2066 .hdisplay = 480, 2067 .hsync_start = 480 + 2, 2068 .hsync_end = 480 + 2 + 41, 2069 .htotal = 480 + 2 + 41 + 2, 2070 .vdisplay = 272, 2071 .vsync_start = 272 + 2, 2072 .vsync_end = 272 + 2 + 10, 2073 .vtotal = 272 + 2 + 10 + 2, 2074 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2075 }; 2076 2077 static const struct panel_desc edt_etm0430g0dh6 = { 2078 .modes = &edt_etm0430g0dh6_mode, 2079 .num_modes = 1, 2080 .bpc = 6, 2081 .size = { 2082 .width = 95, 2083 .height = 54, 2084 }, 2085 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2086 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2087 .connector_type = DRM_MODE_CONNECTOR_DPI, 2088 }; 2089 2090 static const struct drm_display_mode edt_et057090dhu_mode = { 2091 .clock = 25175, 2092 .hdisplay = 640, 2093 .hsync_start = 640 + 16, 2094 .hsync_end = 640 + 16 + 30, 2095 .htotal = 640 + 16 + 30 + 114, 2096 .vdisplay = 480, 2097 .vsync_start = 480 + 10, 2098 .vsync_end = 480 + 10 + 3, 2099 .vtotal = 480 + 10 + 3 + 32, 2100 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2101 }; 2102 2103 static const struct panel_desc edt_et057090dhu = { 2104 .modes = &edt_et057090dhu_mode, 2105 .num_modes = 1, 2106 .bpc = 6, 2107 .size = { 2108 .width = 115, 2109 .height = 86, 2110 }, 2111 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2112 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2113 .connector_type = DRM_MODE_CONNECTOR_DPI, 2114 }; 2115 2116 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2117 .clock = 33260, 2118 .hdisplay = 800, 2119 .hsync_start = 800 + 40, 2120 .hsync_end = 800 + 40 + 128, 2121 .htotal = 800 + 40 + 128 + 88, 2122 .vdisplay = 480, 2123 .vsync_start = 480 + 10, 2124 .vsync_end = 480 + 10 + 2, 2125 .vtotal = 480 + 10 + 2 + 33, 2126 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2127 }; 2128 2129 static const struct panel_desc edt_etm0700g0dh6 = { 2130 .modes = &edt_etm0700g0dh6_mode, 2131 .num_modes = 1, 2132 .bpc = 6, 2133 .size = { 2134 .width = 152, 2135 .height = 91, 2136 }, 2137 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2138 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2139 .connector_type = DRM_MODE_CONNECTOR_DPI, 2140 }; 2141 2142 static const struct panel_desc edt_etm0700g0bdh6 = { 2143 .modes = &edt_etm0700g0dh6_mode, 2144 .num_modes = 1, 2145 .bpc = 6, 2146 .size = { 2147 .width = 152, 2148 .height = 91, 2149 }, 2150 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2151 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2152 .connector_type = DRM_MODE_CONNECTOR_DPI, 2153 }; 2154 2155 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2156 .clock = 25175, 2157 .hdisplay = 640, 2158 .hsync_start = 640, 2159 .hsync_end = 640 + 16, 2160 .htotal = 640 + 16 + 30 + 114, 2161 .vdisplay = 480, 2162 .vsync_start = 480 + 10, 2163 .vsync_end = 480 + 10 + 3, 2164 .vtotal = 480 + 10 + 3 + 35, 2165 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2166 }; 2167 2168 static const struct panel_desc edt_etmv570g2dhu = { 2169 .modes = &edt_etmv570g2dhu_mode, 2170 .num_modes = 1, 2171 .bpc = 6, 2172 .size = { 2173 .width = 115, 2174 .height = 86, 2175 }, 2176 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2177 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2178 .connector_type = DRM_MODE_CONNECTOR_DPI, 2179 }; 2180 2181 static const struct display_timing eink_vb3300_kca_timing = { 2182 .pixelclock = { 40000000, 40000000, 40000000 }, 2183 .hactive = { 334, 334, 334 }, 2184 .hfront_porch = { 1, 1, 1 }, 2185 .hback_porch = { 1, 1, 1 }, 2186 .hsync_len = { 1, 1, 1 }, 2187 .vactive = { 1405, 1405, 1405 }, 2188 .vfront_porch = { 1, 1, 1 }, 2189 .vback_porch = { 1, 1, 1 }, 2190 .vsync_len = { 1, 1, 1 }, 2191 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2192 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2193 }; 2194 2195 static const struct panel_desc eink_vb3300_kca = { 2196 .timings = &eink_vb3300_kca_timing, 2197 .num_timings = 1, 2198 .bpc = 6, 2199 .size = { 2200 .width = 157, 2201 .height = 209, 2202 }, 2203 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2204 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2205 .connector_type = DRM_MODE_CONNECTOR_DPI, 2206 }; 2207 2208 static const struct display_timing evervision_vgg804821_timing = { 2209 .pixelclock = { 27600000, 33300000, 50000000 }, 2210 .hactive = { 800, 800, 800 }, 2211 .hfront_porch = { 40, 66, 70 }, 2212 .hback_porch = { 40, 67, 70 }, 2213 .hsync_len = { 40, 67, 70 }, 2214 .vactive = { 480, 480, 480 }, 2215 .vfront_porch = { 6, 10, 10 }, 2216 .vback_porch = { 7, 11, 11 }, 2217 .vsync_len = { 7, 11, 11 }, 2218 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2219 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2220 DISPLAY_FLAGS_SYNC_NEGEDGE, 2221 }; 2222 2223 static const struct panel_desc evervision_vgg804821 = { 2224 .timings = &evervision_vgg804821_timing, 2225 .num_timings = 1, 2226 .bpc = 8, 2227 .size = { 2228 .width = 108, 2229 .height = 64, 2230 }, 2231 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2232 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2233 }; 2234 2235 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2236 .clock = 32260, 2237 .hdisplay = 800, 2238 .hsync_start = 800 + 168, 2239 .hsync_end = 800 + 168 + 64, 2240 .htotal = 800 + 168 + 64 + 88, 2241 .vdisplay = 480, 2242 .vsync_start = 480 + 37, 2243 .vsync_end = 480 + 37 + 2, 2244 .vtotal = 480 + 37 + 2 + 8, 2245 }; 2246 2247 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2248 .modes = &foxlink_fl500wvr00_a0t_mode, 2249 .num_modes = 1, 2250 .bpc = 8, 2251 .size = { 2252 .width = 108, 2253 .height = 65, 2254 }, 2255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2256 }; 2257 2258 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2259 { /* 60 Hz */ 2260 .clock = 6000, 2261 .hdisplay = 320, 2262 .hsync_start = 320 + 44, 2263 .hsync_end = 320 + 44 + 16, 2264 .htotal = 320 + 44 + 16 + 20, 2265 .vdisplay = 240, 2266 .vsync_start = 240 + 2, 2267 .vsync_end = 240 + 2 + 6, 2268 .vtotal = 240 + 2 + 6 + 2, 2269 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2270 }, 2271 { /* 50 Hz */ 2272 .clock = 5400, 2273 .hdisplay = 320, 2274 .hsync_start = 320 + 56, 2275 .hsync_end = 320 + 56 + 16, 2276 .htotal = 320 + 56 + 16 + 40, 2277 .vdisplay = 240, 2278 .vsync_start = 240 + 2, 2279 .vsync_end = 240 + 2 + 6, 2280 .vtotal = 240 + 2 + 6 + 2, 2281 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2282 }, 2283 }; 2284 2285 static const struct panel_desc frida_frd350h54004 = { 2286 .modes = frida_frd350h54004_modes, 2287 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2288 .bpc = 8, 2289 .size = { 2290 .width = 77, 2291 .height = 64, 2292 }, 2293 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2294 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2295 .connector_type = DRM_MODE_CONNECTOR_DPI, 2296 }; 2297 2298 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2299 .clock = 67185, 2300 .hdisplay = 800, 2301 .hsync_start = 800 + 20, 2302 .hsync_end = 800 + 20 + 24, 2303 .htotal = 800 + 20 + 24 + 20, 2304 .vdisplay = 1280, 2305 .vsync_start = 1280 + 4, 2306 .vsync_end = 1280 + 4 + 8, 2307 .vtotal = 1280 + 4 + 8 + 4, 2308 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2309 }; 2310 2311 static const struct panel_desc friendlyarm_hd702e = { 2312 .modes = &friendlyarm_hd702e_mode, 2313 .num_modes = 1, 2314 .size = { 2315 .width = 94, 2316 .height = 151, 2317 }, 2318 }; 2319 2320 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2321 .clock = 9000, 2322 .hdisplay = 480, 2323 .hsync_start = 480 + 5, 2324 .hsync_end = 480 + 5 + 1, 2325 .htotal = 480 + 5 + 1 + 40, 2326 .vdisplay = 272, 2327 .vsync_start = 272 + 8, 2328 .vsync_end = 272 + 8 + 1, 2329 .vtotal = 272 + 8 + 1 + 8, 2330 }; 2331 2332 static const struct panel_desc giantplus_gpg482739qs5 = { 2333 .modes = &giantplus_gpg482739qs5_mode, 2334 .num_modes = 1, 2335 .bpc = 8, 2336 .size = { 2337 .width = 95, 2338 .height = 54, 2339 }, 2340 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2341 }; 2342 2343 static const struct display_timing giantplus_gpm940b0_timing = { 2344 .pixelclock = { 13500000, 27000000, 27500000 }, 2345 .hactive = { 320, 320, 320 }, 2346 .hfront_porch = { 14, 686, 718 }, 2347 .hback_porch = { 50, 70, 255 }, 2348 .hsync_len = { 1, 1, 1 }, 2349 .vactive = { 240, 240, 240 }, 2350 .vfront_porch = { 1, 1, 179 }, 2351 .vback_porch = { 1, 21, 31 }, 2352 .vsync_len = { 1, 1, 6 }, 2353 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2354 }; 2355 2356 static const struct panel_desc giantplus_gpm940b0 = { 2357 .timings = &giantplus_gpm940b0_timing, 2358 .num_timings = 1, 2359 .bpc = 8, 2360 .size = { 2361 .width = 60, 2362 .height = 45, 2363 }, 2364 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2365 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2366 }; 2367 2368 static const struct display_timing hannstar_hsd070pww1_timing = { 2369 .pixelclock = { 64300000, 71100000, 82000000 }, 2370 .hactive = { 1280, 1280, 1280 }, 2371 .hfront_porch = { 1, 1, 10 }, 2372 .hback_porch = { 1, 1, 10 }, 2373 /* 2374 * According to the data sheet, the minimum horizontal blanking interval 2375 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2376 * minimum working horizontal blanking interval to be 60 clocks. 2377 */ 2378 .hsync_len = { 58, 158, 661 }, 2379 .vactive = { 800, 800, 800 }, 2380 .vfront_porch = { 1, 1, 10 }, 2381 .vback_porch = { 1, 1, 10 }, 2382 .vsync_len = { 1, 21, 203 }, 2383 .flags = DISPLAY_FLAGS_DE_HIGH, 2384 }; 2385 2386 static const struct panel_desc hannstar_hsd070pww1 = { 2387 .timings = &hannstar_hsd070pww1_timing, 2388 .num_timings = 1, 2389 .bpc = 6, 2390 .size = { 2391 .width = 151, 2392 .height = 94, 2393 }, 2394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2396 }; 2397 2398 static const struct display_timing hannstar_hsd100pxn1_timing = { 2399 .pixelclock = { 55000000, 65000000, 75000000 }, 2400 .hactive = { 1024, 1024, 1024 }, 2401 .hfront_porch = { 40, 40, 40 }, 2402 .hback_porch = { 220, 220, 220 }, 2403 .hsync_len = { 20, 60, 100 }, 2404 .vactive = { 768, 768, 768 }, 2405 .vfront_porch = { 7, 7, 7 }, 2406 .vback_porch = { 21, 21, 21 }, 2407 .vsync_len = { 10, 10, 10 }, 2408 .flags = DISPLAY_FLAGS_DE_HIGH, 2409 }; 2410 2411 static const struct panel_desc hannstar_hsd100pxn1 = { 2412 .timings = &hannstar_hsd100pxn1_timing, 2413 .num_timings = 1, 2414 .bpc = 6, 2415 .size = { 2416 .width = 203, 2417 .height = 152, 2418 }, 2419 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2420 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2421 }; 2422 2423 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2424 .clock = 33333, 2425 .hdisplay = 800, 2426 .hsync_start = 800 + 85, 2427 .hsync_end = 800 + 85 + 86, 2428 .htotal = 800 + 85 + 86 + 85, 2429 .vdisplay = 480, 2430 .vsync_start = 480 + 16, 2431 .vsync_end = 480 + 16 + 13, 2432 .vtotal = 480 + 16 + 13 + 16, 2433 }; 2434 2435 static const struct panel_desc hitachi_tx23d38vm0caa = { 2436 .modes = &hitachi_tx23d38vm0caa_mode, 2437 .num_modes = 1, 2438 .bpc = 6, 2439 .size = { 2440 .width = 195, 2441 .height = 117, 2442 }, 2443 .delay = { 2444 .enable = 160, 2445 .disable = 160, 2446 }, 2447 }; 2448 2449 static const struct drm_display_mode innolux_at043tn24_mode = { 2450 .clock = 9000, 2451 .hdisplay = 480, 2452 .hsync_start = 480 + 2, 2453 .hsync_end = 480 + 2 + 41, 2454 .htotal = 480 + 2 + 41 + 2, 2455 .vdisplay = 272, 2456 .vsync_start = 272 + 2, 2457 .vsync_end = 272 + 2 + 10, 2458 .vtotal = 272 + 2 + 10 + 2, 2459 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2460 }; 2461 2462 static const struct panel_desc innolux_at043tn24 = { 2463 .modes = &innolux_at043tn24_mode, 2464 .num_modes = 1, 2465 .bpc = 8, 2466 .size = { 2467 .width = 95, 2468 .height = 54, 2469 }, 2470 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2472 }; 2473 2474 static const struct drm_display_mode innolux_at070tn92_mode = { 2475 .clock = 33333, 2476 .hdisplay = 800, 2477 .hsync_start = 800 + 210, 2478 .hsync_end = 800 + 210 + 20, 2479 .htotal = 800 + 210 + 20 + 46, 2480 .vdisplay = 480, 2481 .vsync_start = 480 + 22, 2482 .vsync_end = 480 + 22 + 10, 2483 .vtotal = 480 + 22 + 23 + 10, 2484 }; 2485 2486 static const struct panel_desc innolux_at070tn92 = { 2487 .modes = &innolux_at070tn92_mode, 2488 .num_modes = 1, 2489 .size = { 2490 .width = 154, 2491 .height = 86, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2494 }; 2495 2496 static const struct display_timing innolux_g070y2_l01_timing = { 2497 .pixelclock = { 28000000, 29500000, 32000000 }, 2498 .hactive = { 800, 800, 800 }, 2499 .hfront_porch = { 61, 91, 141 }, 2500 .hback_porch = { 60, 90, 140 }, 2501 .hsync_len = { 12, 12, 12 }, 2502 .vactive = { 480, 480, 480 }, 2503 .vfront_porch = { 4, 9, 30 }, 2504 .vback_porch = { 4, 8, 28 }, 2505 .vsync_len = { 2, 2, 2 }, 2506 .flags = DISPLAY_FLAGS_DE_HIGH, 2507 }; 2508 2509 static const struct panel_desc innolux_g070y2_l01 = { 2510 .timings = &innolux_g070y2_l01_timing, 2511 .num_timings = 1, 2512 .bpc = 6, 2513 .size = { 2514 .width = 152, 2515 .height = 91, 2516 }, 2517 .delay = { 2518 .prepare = 10, 2519 .enable = 100, 2520 .disable = 100, 2521 .unprepare = 800, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2524 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2525 }; 2526 2527 static const struct display_timing innolux_g101ice_l01_timing = { 2528 .pixelclock = { 60400000, 71100000, 74700000 }, 2529 .hactive = { 1280, 1280, 1280 }, 2530 .hfront_porch = { 41, 80, 100 }, 2531 .hback_porch = { 40, 79, 99 }, 2532 .hsync_len = { 1, 1, 1 }, 2533 .vactive = { 800, 800, 800 }, 2534 .vfront_porch = { 5, 11, 14 }, 2535 .vback_porch = { 4, 11, 14 }, 2536 .vsync_len = { 1, 1, 1 }, 2537 .flags = DISPLAY_FLAGS_DE_HIGH, 2538 }; 2539 2540 static const struct panel_desc innolux_g101ice_l01 = { 2541 .timings = &innolux_g101ice_l01_timing, 2542 .num_timings = 1, 2543 .bpc = 8, 2544 .size = { 2545 .width = 217, 2546 .height = 135, 2547 }, 2548 .delay = { 2549 .enable = 200, 2550 .disable = 200, 2551 }, 2552 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2553 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2554 }; 2555 2556 static const struct display_timing innolux_g121i1_l01_timing = { 2557 .pixelclock = { 67450000, 71000000, 74550000 }, 2558 .hactive = { 1280, 1280, 1280 }, 2559 .hfront_porch = { 40, 80, 160 }, 2560 .hback_porch = { 39, 79, 159 }, 2561 .hsync_len = { 1, 1, 1 }, 2562 .vactive = { 800, 800, 800 }, 2563 .vfront_porch = { 5, 11, 100 }, 2564 .vback_porch = { 4, 11, 99 }, 2565 .vsync_len = { 1, 1, 1 }, 2566 }; 2567 2568 static const struct panel_desc innolux_g121i1_l01 = { 2569 .timings = &innolux_g121i1_l01_timing, 2570 .num_timings = 1, 2571 .bpc = 6, 2572 .size = { 2573 .width = 261, 2574 .height = 163, 2575 }, 2576 .delay = { 2577 .enable = 200, 2578 .disable = 20, 2579 }, 2580 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2581 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2582 }; 2583 2584 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2585 .clock = 65000, 2586 .hdisplay = 1024, 2587 .hsync_start = 1024 + 0, 2588 .hsync_end = 1024 + 1, 2589 .htotal = 1024 + 0 + 1 + 320, 2590 .vdisplay = 768, 2591 .vsync_start = 768 + 38, 2592 .vsync_end = 768 + 38 + 1, 2593 .vtotal = 768 + 38 + 1 + 0, 2594 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2595 }; 2596 2597 static const struct panel_desc innolux_g121x1_l03 = { 2598 .modes = &innolux_g121x1_l03_mode, 2599 .num_modes = 1, 2600 .bpc = 6, 2601 .size = { 2602 .width = 246, 2603 .height = 185, 2604 }, 2605 .delay = { 2606 .enable = 200, 2607 .unprepare = 200, 2608 .disable = 400, 2609 }, 2610 }; 2611 2612 static const struct drm_display_mode innolux_n116bca_ea1_mode = { 2613 .clock = 76420, 2614 .hdisplay = 1366, 2615 .hsync_start = 1366 + 136, 2616 .hsync_end = 1366 + 136 + 30, 2617 .htotal = 1366 + 136 + 30 + 60, 2618 .vdisplay = 768, 2619 .vsync_start = 768 + 8, 2620 .vsync_end = 768 + 8 + 12, 2621 .vtotal = 768 + 8 + 12 + 12, 2622 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2623 }; 2624 2625 static const struct panel_desc innolux_n116bca_ea1 = { 2626 .modes = &innolux_n116bca_ea1_mode, 2627 .num_modes = 1, 2628 .bpc = 6, 2629 .size = { 2630 .width = 256, 2631 .height = 144, 2632 }, 2633 .delay = { 2634 .hpd_absent_delay = 200, 2635 .prepare_to_enable = 80, 2636 .unprepare = 500, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2639 .connector_type = DRM_MODE_CONNECTOR_eDP, 2640 }; 2641 2642 /* 2643 * Datasheet specifies that at 60 Hz refresh rate: 2644 * - total horizontal time: { 1506, 1592, 1716 } 2645 * - total vertical time: { 788, 800, 868 } 2646 * 2647 * ...but doesn't go into exactly how that should be split into a front 2648 * porch, back porch, or sync length. For now we'll leave a single setting 2649 * here which allows a bit of tweaking of the pixel clock at the expense of 2650 * refresh rate. 2651 */ 2652 static const struct display_timing innolux_n116bge_timing = { 2653 .pixelclock = { 72600000, 76420000, 80240000 }, 2654 .hactive = { 1366, 1366, 1366 }, 2655 .hfront_porch = { 136, 136, 136 }, 2656 .hback_porch = { 60, 60, 60 }, 2657 .hsync_len = { 30, 30, 30 }, 2658 .vactive = { 768, 768, 768 }, 2659 .vfront_porch = { 8, 8, 8 }, 2660 .vback_porch = { 12, 12, 12 }, 2661 .vsync_len = { 12, 12, 12 }, 2662 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2663 }; 2664 2665 static const struct panel_desc innolux_n116bge = { 2666 .timings = &innolux_n116bge_timing, 2667 .num_timings = 1, 2668 .bpc = 6, 2669 .size = { 2670 .width = 256, 2671 .height = 144, 2672 }, 2673 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2674 .connector_type = DRM_MODE_CONNECTOR_eDP, 2675 }; 2676 2677 static const struct drm_display_mode innolux_n125hce_gn1_mode = { 2678 .clock = 162000, 2679 .hdisplay = 1920, 2680 .hsync_start = 1920 + 40, 2681 .hsync_end = 1920 + 40 + 40, 2682 .htotal = 1920 + 40 + 40 + 80, 2683 .vdisplay = 1080, 2684 .vsync_start = 1080 + 4, 2685 .vsync_end = 1080 + 4 + 4, 2686 .vtotal = 1080 + 4 + 4 + 24, 2687 }; 2688 2689 static const struct panel_desc innolux_n125hce_gn1 = { 2690 .modes = &innolux_n125hce_gn1_mode, 2691 .num_modes = 1, 2692 .bpc = 8, 2693 .size = { 2694 .width = 276, 2695 .height = 155, 2696 }, 2697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2698 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2699 .connector_type = DRM_MODE_CONNECTOR_eDP, 2700 }; 2701 2702 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2703 .clock = 69300, 2704 .hdisplay = 1366, 2705 .hsync_start = 1366 + 16, 2706 .hsync_end = 1366 + 16 + 34, 2707 .htotal = 1366 + 16 + 34 + 50, 2708 .vdisplay = 768, 2709 .vsync_start = 768 + 2, 2710 .vsync_end = 768 + 2 + 6, 2711 .vtotal = 768 + 2 + 6 + 12, 2712 }; 2713 2714 static const struct panel_desc innolux_n156bge_l21 = { 2715 .modes = &innolux_n156bge_l21_mode, 2716 .num_modes = 1, 2717 .bpc = 6, 2718 .size = { 2719 .width = 344, 2720 .height = 193, 2721 }, 2722 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2723 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2724 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2725 }; 2726 2727 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2728 .clock = 206016, 2729 .hdisplay = 2160, 2730 .hsync_start = 2160 + 48, 2731 .hsync_end = 2160 + 48 + 32, 2732 .htotal = 2160 + 48 + 32 + 80, 2733 .vdisplay = 1440, 2734 .vsync_start = 1440 + 3, 2735 .vsync_end = 1440 + 3 + 10, 2736 .vtotal = 1440 + 3 + 10 + 27, 2737 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2738 }; 2739 2740 static const struct panel_desc innolux_p120zdg_bf1 = { 2741 .modes = &innolux_p120zdg_bf1_mode, 2742 .num_modes = 1, 2743 .bpc = 8, 2744 .size = { 2745 .width = 254, 2746 .height = 169, 2747 }, 2748 .delay = { 2749 .hpd_absent_delay = 200, 2750 .unprepare = 500, 2751 }, 2752 }; 2753 2754 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2755 .clock = 51501, 2756 .hdisplay = 1024, 2757 .hsync_start = 1024 + 128, 2758 .hsync_end = 1024 + 128 + 64, 2759 .htotal = 1024 + 128 + 64 + 128, 2760 .vdisplay = 600, 2761 .vsync_start = 600 + 16, 2762 .vsync_end = 600 + 16 + 4, 2763 .vtotal = 600 + 16 + 4 + 16, 2764 }; 2765 2766 static const struct panel_desc innolux_zj070na_01p = { 2767 .modes = &innolux_zj070na_01p_mode, 2768 .num_modes = 1, 2769 .bpc = 6, 2770 .size = { 2771 .width = 154, 2772 .height = 90, 2773 }, 2774 }; 2775 2776 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2777 .clock = 138778, 2778 .hdisplay = 1920, 2779 .hsync_start = 1920 + 24, 2780 .hsync_end = 1920 + 24 + 48, 2781 .htotal = 1920 + 24 + 48 + 88, 2782 .vdisplay = 1080, 2783 .vsync_start = 1080 + 3, 2784 .vsync_end = 1080 + 3 + 12, 2785 .vtotal = 1080 + 3 + 12 + 17, 2786 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2787 }; 2788 2789 static const struct panel_desc ivo_m133nwf4_r0 = { 2790 .modes = &ivo_m133nwf4_r0_mode, 2791 .num_modes = 1, 2792 .bpc = 8, 2793 .size = { 2794 .width = 294, 2795 .height = 165, 2796 }, 2797 .delay = { 2798 .hpd_absent_delay = 200, 2799 .unprepare = 500, 2800 }, 2801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2802 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2803 .connector_type = DRM_MODE_CONNECTOR_eDP, 2804 }; 2805 2806 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2807 .clock = 81000, 2808 .hdisplay = 1366, 2809 .hsync_start = 1366 + 40, 2810 .hsync_end = 1366 + 40 + 32, 2811 .htotal = 1366 + 40 + 32 + 62, 2812 .vdisplay = 768, 2813 .vsync_start = 768 + 5, 2814 .vsync_end = 768 + 5 + 5, 2815 .vtotal = 768 + 5 + 5 + 122, 2816 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2817 }; 2818 2819 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2820 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2821 .num_modes = 1, 2822 .bpc = 6, 2823 .size = { 2824 .width = 256, 2825 .height = 144, 2826 }, 2827 .delay = { 2828 .hpd_absent_delay = 200, 2829 }, 2830 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2831 .connector_type = DRM_MODE_CONNECTOR_eDP, 2832 }; 2833 2834 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2835 .pixelclock = { 5580000, 5850000, 6200000 }, 2836 .hactive = { 320, 320, 320 }, 2837 .hfront_porch = { 30, 30, 30 }, 2838 .hback_porch = { 30, 30, 30 }, 2839 .hsync_len = { 1, 5, 17 }, 2840 .vactive = { 240, 240, 240 }, 2841 .vfront_porch = { 6, 6, 6 }, 2842 .vback_porch = { 5, 5, 5 }, 2843 .vsync_len = { 1, 2, 11 }, 2844 .flags = DISPLAY_FLAGS_DE_HIGH, 2845 }; 2846 2847 static const struct panel_desc koe_tx14d24vm1bpa = { 2848 .timings = &koe_tx14d24vm1bpa_timing, 2849 .num_timings = 1, 2850 .bpc = 6, 2851 .size = { 2852 .width = 115, 2853 .height = 86, 2854 }, 2855 }; 2856 2857 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2858 .pixelclock = { 151820000, 156720000, 159780000 }, 2859 .hactive = { 1920, 1920, 1920 }, 2860 .hfront_porch = { 105, 130, 142 }, 2861 .hback_porch = { 45, 70, 82 }, 2862 .hsync_len = { 30, 30, 30 }, 2863 .vactive = { 1200, 1200, 1200}, 2864 .vfront_porch = { 3, 5, 10 }, 2865 .vback_porch = { 2, 5, 10 }, 2866 .vsync_len = { 5, 5, 5 }, 2867 }; 2868 2869 static const struct panel_desc koe_tx26d202vm0bwa = { 2870 .timings = &koe_tx26d202vm0bwa_timing, 2871 .num_timings = 1, 2872 .bpc = 8, 2873 .size = { 2874 .width = 217, 2875 .height = 136, 2876 }, 2877 .delay = { 2878 .prepare = 1000, 2879 .enable = 1000, 2880 .unprepare = 1000, 2881 .disable = 1000, 2882 }, 2883 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2884 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2886 }; 2887 2888 static const struct display_timing koe_tx31d200vm0baa_timing = { 2889 .pixelclock = { 39600000, 43200000, 48000000 }, 2890 .hactive = { 1280, 1280, 1280 }, 2891 .hfront_porch = { 16, 36, 56 }, 2892 .hback_porch = { 16, 36, 56 }, 2893 .hsync_len = { 8, 8, 8 }, 2894 .vactive = { 480, 480, 480 }, 2895 .vfront_porch = { 6, 21, 33 }, 2896 .vback_porch = { 6, 21, 33 }, 2897 .vsync_len = { 8, 8, 8 }, 2898 .flags = DISPLAY_FLAGS_DE_HIGH, 2899 }; 2900 2901 static const struct panel_desc koe_tx31d200vm0baa = { 2902 .timings = &koe_tx31d200vm0baa_timing, 2903 .num_timings = 1, 2904 .bpc = 6, 2905 .size = { 2906 .width = 292, 2907 .height = 109, 2908 }, 2909 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2910 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2911 }; 2912 2913 static const struct display_timing kyo_tcg121xglp_timing = { 2914 .pixelclock = { 52000000, 65000000, 71000000 }, 2915 .hactive = { 1024, 1024, 1024 }, 2916 .hfront_porch = { 2, 2, 2 }, 2917 .hback_porch = { 2, 2, 2 }, 2918 .hsync_len = { 86, 124, 244 }, 2919 .vactive = { 768, 768, 768 }, 2920 .vfront_porch = { 2, 2, 2 }, 2921 .vback_porch = { 2, 2, 2 }, 2922 .vsync_len = { 6, 34, 73 }, 2923 .flags = DISPLAY_FLAGS_DE_HIGH, 2924 }; 2925 2926 static const struct panel_desc kyo_tcg121xglp = { 2927 .timings = &kyo_tcg121xglp_timing, 2928 .num_timings = 1, 2929 .bpc = 8, 2930 .size = { 2931 .width = 246, 2932 .height = 184, 2933 }, 2934 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2935 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2936 }; 2937 2938 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2939 .clock = 7000, 2940 .hdisplay = 320, 2941 .hsync_start = 320 + 20, 2942 .hsync_end = 320 + 20 + 30, 2943 .htotal = 320 + 20 + 30 + 38, 2944 .vdisplay = 240, 2945 .vsync_start = 240 + 4, 2946 .vsync_end = 240 + 4 + 3, 2947 .vtotal = 240 + 4 + 3 + 15, 2948 }; 2949 2950 static const struct panel_desc lemaker_bl035_rgb_002 = { 2951 .modes = &lemaker_bl035_rgb_002_mode, 2952 .num_modes = 1, 2953 .size = { 2954 .width = 70, 2955 .height = 52, 2956 }, 2957 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2958 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2959 }; 2960 2961 static const struct drm_display_mode lg_lb070wv8_mode = { 2962 .clock = 33246, 2963 .hdisplay = 800, 2964 .hsync_start = 800 + 88, 2965 .hsync_end = 800 + 88 + 80, 2966 .htotal = 800 + 88 + 80 + 88, 2967 .vdisplay = 480, 2968 .vsync_start = 480 + 10, 2969 .vsync_end = 480 + 10 + 25, 2970 .vtotal = 480 + 10 + 25 + 10, 2971 }; 2972 2973 static const struct panel_desc lg_lb070wv8 = { 2974 .modes = &lg_lb070wv8_mode, 2975 .num_modes = 1, 2976 .bpc = 8, 2977 .size = { 2978 .width = 151, 2979 .height = 91, 2980 }, 2981 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2982 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2983 }; 2984 2985 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2986 .clock = 200000, 2987 .hdisplay = 1536, 2988 .hsync_start = 1536 + 12, 2989 .hsync_end = 1536 + 12 + 16, 2990 .htotal = 1536 + 12 + 16 + 48, 2991 .vdisplay = 2048, 2992 .vsync_start = 2048 + 8, 2993 .vsync_end = 2048 + 8 + 4, 2994 .vtotal = 2048 + 8 + 4 + 8, 2995 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2996 }; 2997 2998 static const struct panel_desc lg_lp079qx1_sp0v = { 2999 .modes = &lg_lp079qx1_sp0v_mode, 3000 .num_modes = 1, 3001 .size = { 3002 .width = 129, 3003 .height = 171, 3004 }, 3005 }; 3006 3007 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 3008 .clock = 205210, 3009 .hdisplay = 2048, 3010 .hsync_start = 2048 + 150, 3011 .hsync_end = 2048 + 150 + 5, 3012 .htotal = 2048 + 150 + 5 + 5, 3013 .vdisplay = 1536, 3014 .vsync_start = 1536 + 3, 3015 .vsync_end = 1536 + 3 + 1, 3016 .vtotal = 1536 + 3 + 1 + 9, 3017 }; 3018 3019 static const struct panel_desc lg_lp097qx1_spa1 = { 3020 .modes = &lg_lp097qx1_spa1_mode, 3021 .num_modes = 1, 3022 .size = { 3023 .width = 208, 3024 .height = 147, 3025 }, 3026 }; 3027 3028 static const struct drm_display_mode lg_lp120up1_mode = { 3029 .clock = 162300, 3030 .hdisplay = 1920, 3031 .hsync_start = 1920 + 40, 3032 .hsync_end = 1920 + 40 + 40, 3033 .htotal = 1920 + 40 + 40+ 80, 3034 .vdisplay = 1280, 3035 .vsync_start = 1280 + 4, 3036 .vsync_end = 1280 + 4 + 4, 3037 .vtotal = 1280 + 4 + 4 + 12, 3038 }; 3039 3040 static const struct panel_desc lg_lp120up1 = { 3041 .modes = &lg_lp120up1_mode, 3042 .num_modes = 1, 3043 .bpc = 8, 3044 .size = { 3045 .width = 267, 3046 .height = 183, 3047 }, 3048 .connector_type = DRM_MODE_CONNECTOR_eDP, 3049 }; 3050 3051 static const struct drm_display_mode lg_lp129qe_mode = { 3052 .clock = 285250, 3053 .hdisplay = 2560, 3054 .hsync_start = 2560 + 48, 3055 .hsync_end = 2560 + 48 + 32, 3056 .htotal = 2560 + 48 + 32 + 80, 3057 .vdisplay = 1700, 3058 .vsync_start = 1700 + 3, 3059 .vsync_end = 1700 + 3 + 10, 3060 .vtotal = 1700 + 3 + 10 + 36, 3061 }; 3062 3063 static const struct panel_desc lg_lp129qe = { 3064 .modes = &lg_lp129qe_mode, 3065 .num_modes = 1, 3066 .bpc = 8, 3067 .size = { 3068 .width = 272, 3069 .height = 181, 3070 }, 3071 }; 3072 3073 static const struct display_timing logictechno_lt161010_2nh_timing = { 3074 .pixelclock = { 26400000, 33300000, 46800000 }, 3075 .hactive = { 800, 800, 800 }, 3076 .hfront_porch = { 16, 210, 354 }, 3077 .hback_porch = { 46, 46, 46 }, 3078 .hsync_len = { 1, 20, 40 }, 3079 .vactive = { 480, 480, 480 }, 3080 .vfront_porch = { 7, 22, 147 }, 3081 .vback_porch = { 23, 23, 23 }, 3082 .vsync_len = { 1, 10, 20 }, 3083 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3084 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3085 DISPLAY_FLAGS_SYNC_POSEDGE, 3086 }; 3087 3088 static const struct panel_desc logictechno_lt161010_2nh = { 3089 .timings = &logictechno_lt161010_2nh_timing, 3090 .num_timings = 1, 3091 .size = { 3092 .width = 154, 3093 .height = 86, 3094 }, 3095 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3096 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3097 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3098 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3099 .connector_type = DRM_MODE_CONNECTOR_DPI, 3100 }; 3101 3102 static const struct display_timing logictechno_lt170410_2whc_timing = { 3103 .pixelclock = { 68900000, 71100000, 73400000 }, 3104 .hactive = { 1280, 1280, 1280 }, 3105 .hfront_porch = { 23, 60, 71 }, 3106 .hback_porch = { 23, 60, 71 }, 3107 .hsync_len = { 15, 40, 47 }, 3108 .vactive = { 800, 800, 800 }, 3109 .vfront_porch = { 5, 7, 10 }, 3110 .vback_porch = { 5, 7, 10 }, 3111 .vsync_len = { 6, 9, 12 }, 3112 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3113 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3114 DISPLAY_FLAGS_SYNC_POSEDGE, 3115 }; 3116 3117 static const struct panel_desc logictechno_lt170410_2whc = { 3118 .timings = &logictechno_lt170410_2whc_timing, 3119 .num_timings = 1, 3120 .size = { 3121 .width = 217, 3122 .height = 136, 3123 }, 3124 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3125 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3126 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3127 }; 3128 3129 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3130 .clock = 33000, 3131 .hdisplay = 800, 3132 .hsync_start = 800 + 154, 3133 .hsync_end = 800 + 154 + 3, 3134 .htotal = 800 + 154 + 3 + 43, 3135 .vdisplay = 480, 3136 .vsync_start = 480 + 47, 3137 .vsync_end = 480 + 47 + 3, 3138 .vtotal = 480 + 47 + 3 + 20, 3139 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3140 }; 3141 3142 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3143 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3144 .num_modes = 1, 3145 .bpc = 8, 3146 .size = { 3147 .width = 154, 3148 .height = 86, 3149 }, 3150 .delay = { 3151 .prepare = 45, 3152 .enable = 100, 3153 .disable = 100, 3154 .unprepare = 45 3155 }, 3156 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3157 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3158 .connector_type = DRM_MODE_CONNECTOR_DPI, 3159 }; 3160 3161 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3162 .clock = 30400, 3163 .hdisplay = 800, 3164 .hsync_start = 800 + 0, 3165 .hsync_end = 800 + 1, 3166 .htotal = 800 + 0 + 1 + 160, 3167 .vdisplay = 480, 3168 .vsync_start = 480 + 0, 3169 .vsync_end = 480 + 48 + 1, 3170 .vtotal = 480 + 48 + 1 + 0, 3171 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3172 }; 3173 3174 static const struct drm_display_mode logicpd_type_28_mode = { 3175 .clock = 9107, 3176 .hdisplay = 480, 3177 .hsync_start = 480 + 3, 3178 .hsync_end = 480 + 3 + 42, 3179 .htotal = 480 + 3 + 42 + 2, 3180 3181 .vdisplay = 272, 3182 .vsync_start = 272 + 2, 3183 .vsync_end = 272 + 2 + 11, 3184 .vtotal = 272 + 2 + 11 + 3, 3185 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3186 }; 3187 3188 static const struct panel_desc logicpd_type_28 = { 3189 .modes = &logicpd_type_28_mode, 3190 .num_modes = 1, 3191 .bpc = 8, 3192 .size = { 3193 .width = 105, 3194 .height = 67, 3195 }, 3196 .delay = { 3197 .prepare = 200, 3198 .enable = 200, 3199 .unprepare = 200, 3200 .disable = 200, 3201 }, 3202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3203 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3204 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3205 .connector_type = DRM_MODE_CONNECTOR_DPI, 3206 }; 3207 3208 static const struct panel_desc mitsubishi_aa070mc01 = { 3209 .modes = &mitsubishi_aa070mc01_mode, 3210 .num_modes = 1, 3211 .bpc = 8, 3212 .size = { 3213 .width = 152, 3214 .height = 91, 3215 }, 3216 3217 .delay = { 3218 .enable = 200, 3219 .unprepare = 200, 3220 .disable = 400, 3221 }, 3222 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3223 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3225 }; 3226 3227 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3228 .pixelclock = { 68900000, 70000000, 73400000 }, 3229 .hactive = { 1280, 1280, 1280 }, 3230 .hfront_porch = { 30, 60, 71 }, 3231 .hback_porch = { 30, 60, 71 }, 3232 .hsync_len = { 10, 10, 48 }, 3233 .vactive = { 800, 800, 800 }, 3234 .vfront_porch = { 5, 10, 10 }, 3235 .vback_porch = { 5, 10, 10 }, 3236 .vsync_len = { 5, 6, 13 }, 3237 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3238 DISPLAY_FLAGS_DE_HIGH, 3239 }; 3240 3241 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3242 .timings = &multi_inno_mi1010ait_1cp_timing, 3243 .num_timings = 1, 3244 .bpc = 8, 3245 .size = { 3246 .width = 217, 3247 .height = 136, 3248 }, 3249 .delay = { 3250 .enable = 50, 3251 .disable = 50, 3252 }, 3253 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3254 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3255 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3256 }; 3257 3258 static const struct display_timing nec_nl12880bc20_05_timing = { 3259 .pixelclock = { 67000000, 71000000, 75000000 }, 3260 .hactive = { 1280, 1280, 1280 }, 3261 .hfront_porch = { 2, 30, 30 }, 3262 .hback_porch = { 6, 100, 100 }, 3263 .hsync_len = { 2, 30, 30 }, 3264 .vactive = { 800, 800, 800 }, 3265 .vfront_porch = { 5, 5, 5 }, 3266 .vback_porch = { 11, 11, 11 }, 3267 .vsync_len = { 7, 7, 7 }, 3268 }; 3269 3270 static const struct panel_desc nec_nl12880bc20_05 = { 3271 .timings = &nec_nl12880bc20_05_timing, 3272 .num_timings = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 261, 3276 .height = 163, 3277 }, 3278 .delay = { 3279 .enable = 50, 3280 .disable = 50, 3281 }, 3282 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3283 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3284 }; 3285 3286 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3287 .clock = 10870, 3288 .hdisplay = 480, 3289 .hsync_start = 480 + 2, 3290 .hsync_end = 480 + 2 + 41, 3291 .htotal = 480 + 2 + 41 + 2, 3292 .vdisplay = 272, 3293 .vsync_start = 272 + 2, 3294 .vsync_end = 272 + 2 + 4, 3295 .vtotal = 272 + 2 + 4 + 2, 3296 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3297 }; 3298 3299 static const struct panel_desc nec_nl4827hc19_05b = { 3300 .modes = &nec_nl4827hc19_05b_mode, 3301 .num_modes = 1, 3302 .bpc = 8, 3303 .size = { 3304 .width = 95, 3305 .height = 54, 3306 }, 3307 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3308 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3309 }; 3310 3311 static const struct drm_display_mode netron_dy_e231732_mode = { 3312 .clock = 66000, 3313 .hdisplay = 1024, 3314 .hsync_start = 1024 + 160, 3315 .hsync_end = 1024 + 160 + 70, 3316 .htotal = 1024 + 160 + 70 + 90, 3317 .vdisplay = 600, 3318 .vsync_start = 600 + 127, 3319 .vsync_end = 600 + 127 + 20, 3320 .vtotal = 600 + 127 + 20 + 3, 3321 }; 3322 3323 static const struct panel_desc netron_dy_e231732 = { 3324 .modes = &netron_dy_e231732_mode, 3325 .num_modes = 1, 3326 .size = { 3327 .width = 154, 3328 .height = 87, 3329 }, 3330 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3331 }; 3332 3333 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 3334 { 3335 .clock = 138500, 3336 .hdisplay = 1920, 3337 .hsync_start = 1920 + 48, 3338 .hsync_end = 1920 + 48 + 32, 3339 .htotal = 1920 + 48 + 32 + 80, 3340 .vdisplay = 1080, 3341 .vsync_start = 1080 + 3, 3342 .vsync_end = 1080 + 3 + 5, 3343 .vtotal = 1080 + 3 + 5 + 23, 3344 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3345 }, { 3346 .clock = 110920, 3347 .hdisplay = 1920, 3348 .hsync_start = 1920 + 48, 3349 .hsync_end = 1920 + 48 + 32, 3350 .htotal = 1920 + 48 + 32 + 80, 3351 .vdisplay = 1080, 3352 .vsync_start = 1080 + 3, 3353 .vsync_end = 1080 + 3 + 5, 3354 .vtotal = 1080 + 3 + 5 + 23, 3355 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3356 } 3357 }; 3358 3359 static const struct panel_desc neweast_wjfh116008a = { 3360 .modes = neweast_wjfh116008a_modes, 3361 .num_modes = 2, 3362 .bpc = 6, 3363 .size = { 3364 .width = 260, 3365 .height = 150, 3366 }, 3367 .delay = { 3368 .prepare = 110, 3369 .enable = 20, 3370 .unprepare = 500, 3371 }, 3372 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3373 .connector_type = DRM_MODE_CONNECTOR_eDP, 3374 }; 3375 3376 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3377 .clock = 9000, 3378 .hdisplay = 480, 3379 .hsync_start = 480 + 2, 3380 .hsync_end = 480 + 2 + 41, 3381 .htotal = 480 + 2 + 41 + 2, 3382 .vdisplay = 272, 3383 .vsync_start = 272 + 2, 3384 .vsync_end = 272 + 2 + 10, 3385 .vtotal = 272 + 2 + 10 + 2, 3386 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3387 }; 3388 3389 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3390 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3391 .num_modes = 1, 3392 .bpc = 8, 3393 .size = { 3394 .width = 95, 3395 .height = 54, 3396 }, 3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3398 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3399 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3400 .connector_type = DRM_MODE_CONNECTOR_DPI, 3401 }; 3402 3403 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3404 .pixelclock = { 130000000, 148350000, 163000000 }, 3405 .hactive = { 1920, 1920, 1920 }, 3406 .hfront_porch = { 80, 100, 100 }, 3407 .hback_porch = { 100, 120, 120 }, 3408 .hsync_len = { 50, 60, 60 }, 3409 .vactive = { 1080, 1080, 1080 }, 3410 .vfront_porch = { 12, 30, 30 }, 3411 .vback_porch = { 4, 10, 10 }, 3412 .vsync_len = { 4, 5, 5 }, 3413 }; 3414 3415 static const struct panel_desc nlt_nl192108ac18_02d = { 3416 .timings = &nlt_nl192108ac18_02d_timing, 3417 .num_timings = 1, 3418 .bpc = 8, 3419 .size = { 3420 .width = 344, 3421 .height = 194, 3422 }, 3423 .delay = { 3424 .unprepare = 500, 3425 }, 3426 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3427 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3428 }; 3429 3430 static const struct drm_display_mode nvd_9128_mode = { 3431 .clock = 29500, 3432 .hdisplay = 800, 3433 .hsync_start = 800 + 130, 3434 .hsync_end = 800 + 130 + 98, 3435 .htotal = 800 + 0 + 130 + 98, 3436 .vdisplay = 480, 3437 .vsync_start = 480 + 10, 3438 .vsync_end = 480 + 10 + 50, 3439 .vtotal = 480 + 0 + 10 + 50, 3440 }; 3441 3442 static const struct panel_desc nvd_9128 = { 3443 .modes = &nvd_9128_mode, 3444 .num_modes = 1, 3445 .bpc = 8, 3446 .size = { 3447 .width = 156, 3448 .height = 88, 3449 }, 3450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3451 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3452 }; 3453 3454 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3455 .pixelclock = { 30000000, 30000000, 40000000 }, 3456 .hactive = { 800, 800, 800 }, 3457 .hfront_porch = { 40, 40, 40 }, 3458 .hback_porch = { 40, 40, 40 }, 3459 .hsync_len = { 1, 48, 48 }, 3460 .vactive = { 480, 480, 480 }, 3461 .vfront_porch = { 13, 13, 13 }, 3462 .vback_porch = { 29, 29, 29 }, 3463 .vsync_len = { 3, 3, 3 }, 3464 .flags = DISPLAY_FLAGS_DE_HIGH, 3465 }; 3466 3467 static const struct panel_desc okaya_rs800480t_7x0gp = { 3468 .timings = &okaya_rs800480t_7x0gp_timing, 3469 .num_timings = 1, 3470 .bpc = 6, 3471 .size = { 3472 .width = 154, 3473 .height = 87, 3474 }, 3475 .delay = { 3476 .prepare = 41, 3477 .enable = 50, 3478 .unprepare = 41, 3479 .disable = 50, 3480 }, 3481 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3482 }; 3483 3484 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3485 .clock = 9000, 3486 .hdisplay = 480, 3487 .hsync_start = 480 + 5, 3488 .hsync_end = 480 + 5 + 30, 3489 .htotal = 480 + 5 + 30 + 10, 3490 .vdisplay = 272, 3491 .vsync_start = 272 + 8, 3492 .vsync_end = 272 + 8 + 5, 3493 .vtotal = 272 + 8 + 5 + 3, 3494 }; 3495 3496 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3497 .modes = &olimex_lcd_olinuxino_43ts_mode, 3498 .num_modes = 1, 3499 .size = { 3500 .width = 95, 3501 .height = 54, 3502 }, 3503 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3504 }; 3505 3506 /* 3507 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3508 * pixel clocks, but this is the timing that was being used in the Adafruit 3509 * installation instructions. 3510 */ 3511 static const struct drm_display_mode ontat_yx700wv03_mode = { 3512 .clock = 29500, 3513 .hdisplay = 800, 3514 .hsync_start = 824, 3515 .hsync_end = 896, 3516 .htotal = 992, 3517 .vdisplay = 480, 3518 .vsync_start = 483, 3519 .vsync_end = 493, 3520 .vtotal = 500, 3521 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3522 }; 3523 3524 /* 3525 * Specification at: 3526 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3527 */ 3528 static const struct panel_desc ontat_yx700wv03 = { 3529 .modes = &ontat_yx700wv03_mode, 3530 .num_modes = 1, 3531 .bpc = 8, 3532 .size = { 3533 .width = 154, 3534 .height = 83, 3535 }, 3536 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3537 }; 3538 3539 static const struct drm_display_mode ortustech_com37h3m_mode = { 3540 .clock = 22230, 3541 .hdisplay = 480, 3542 .hsync_start = 480 + 40, 3543 .hsync_end = 480 + 40 + 10, 3544 .htotal = 480 + 40 + 10 + 40, 3545 .vdisplay = 640, 3546 .vsync_start = 640 + 4, 3547 .vsync_end = 640 + 4 + 2, 3548 .vtotal = 640 + 4 + 2 + 4, 3549 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3550 }; 3551 3552 static const struct panel_desc ortustech_com37h3m = { 3553 .modes = &ortustech_com37h3m_mode, 3554 .num_modes = 1, 3555 .bpc = 8, 3556 .size = { 3557 .width = 56, /* 56.16mm */ 3558 .height = 75, /* 74.88mm */ 3559 }, 3560 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3562 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3563 }; 3564 3565 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3566 .clock = 25000, 3567 .hdisplay = 480, 3568 .hsync_start = 480 + 10, 3569 .hsync_end = 480 + 10 + 10, 3570 .htotal = 480 + 10 + 10 + 15, 3571 .vdisplay = 800, 3572 .vsync_start = 800 + 3, 3573 .vsync_end = 800 + 3 + 3, 3574 .vtotal = 800 + 3 + 3 + 3, 3575 }; 3576 3577 static const struct panel_desc ortustech_com43h4m85ulc = { 3578 .modes = &ortustech_com43h4m85ulc_mode, 3579 .num_modes = 1, 3580 .bpc = 6, 3581 .size = { 3582 .width = 56, 3583 .height = 93, 3584 }, 3585 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3586 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3587 .connector_type = DRM_MODE_CONNECTOR_DPI, 3588 }; 3589 3590 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3591 .clock = 33000, 3592 .hdisplay = 800, 3593 .hsync_start = 800 + 210, 3594 .hsync_end = 800 + 210 + 30, 3595 .htotal = 800 + 210 + 30 + 16, 3596 .vdisplay = 480, 3597 .vsync_start = 480 + 22, 3598 .vsync_end = 480 + 22 + 13, 3599 .vtotal = 480 + 22 + 13 + 10, 3600 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3601 }; 3602 3603 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3604 .modes = &osddisplays_osd070t1718_19ts_mode, 3605 .num_modes = 1, 3606 .bpc = 8, 3607 .size = { 3608 .width = 152, 3609 .height = 91, 3610 }, 3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3612 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3613 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3614 .connector_type = DRM_MODE_CONNECTOR_DPI, 3615 }; 3616 3617 static const struct drm_display_mode pda_91_00156_a0_mode = { 3618 .clock = 33300, 3619 .hdisplay = 800, 3620 .hsync_start = 800 + 1, 3621 .hsync_end = 800 + 1 + 64, 3622 .htotal = 800 + 1 + 64 + 64, 3623 .vdisplay = 480, 3624 .vsync_start = 480 + 1, 3625 .vsync_end = 480 + 1 + 23, 3626 .vtotal = 480 + 1 + 23 + 22, 3627 }; 3628 3629 static const struct panel_desc pda_91_00156_a0 = { 3630 .modes = &pda_91_00156_a0_mode, 3631 .num_modes = 1, 3632 .size = { 3633 .width = 152, 3634 .height = 91, 3635 }, 3636 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3637 }; 3638 3639 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3640 .clock = 24750, 3641 .hdisplay = 800, 3642 .hsync_start = 800 + 54, 3643 .hsync_end = 800 + 54 + 2, 3644 .htotal = 800 + 54 + 2 + 44, 3645 .vdisplay = 480, 3646 .vsync_start = 480 + 49, 3647 .vsync_end = 480 + 49 + 2, 3648 .vtotal = 480 + 49 + 2 + 22, 3649 }; 3650 3651 static const struct panel_desc powertip_ph800480t013_idf02 = { 3652 .modes = &powertip_ph800480t013_idf02_mode, 3653 .num_modes = 1, 3654 .size = { 3655 .width = 152, 3656 .height = 91, 3657 }, 3658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3660 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3661 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3662 .connector_type = DRM_MODE_CONNECTOR_DPI, 3663 }; 3664 3665 static const struct drm_display_mode qd43003c0_40_mode = { 3666 .clock = 9000, 3667 .hdisplay = 480, 3668 .hsync_start = 480 + 8, 3669 .hsync_end = 480 + 8 + 4, 3670 .htotal = 480 + 8 + 4 + 39, 3671 .vdisplay = 272, 3672 .vsync_start = 272 + 4, 3673 .vsync_end = 272 + 4 + 10, 3674 .vtotal = 272 + 4 + 10 + 2, 3675 }; 3676 3677 static const struct panel_desc qd43003c0_40 = { 3678 .modes = &qd43003c0_40_mode, 3679 .num_modes = 1, 3680 .bpc = 8, 3681 .size = { 3682 .width = 95, 3683 .height = 53, 3684 }, 3685 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3686 }; 3687 3688 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3689 { /* 60 Hz */ 3690 .clock = 10800, 3691 .hdisplay = 480, 3692 .hsync_start = 480 + 77, 3693 .hsync_end = 480 + 77 + 41, 3694 .htotal = 480 + 77 + 41 + 2, 3695 .vdisplay = 272, 3696 .vsync_start = 272 + 16, 3697 .vsync_end = 272 + 16 + 10, 3698 .vtotal = 272 + 16 + 10 + 2, 3699 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3700 }, 3701 { /* 50 Hz */ 3702 .clock = 10800, 3703 .hdisplay = 480, 3704 .hsync_start = 480 + 17, 3705 .hsync_end = 480 + 17 + 41, 3706 .htotal = 480 + 17 + 41 + 2, 3707 .vdisplay = 272, 3708 .vsync_start = 272 + 116, 3709 .vsync_end = 272 + 116 + 10, 3710 .vtotal = 272 + 116 + 10 + 2, 3711 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3712 }, 3713 }; 3714 3715 static const struct panel_desc qishenglong_gopher2b_lcd = { 3716 .modes = qishenglong_gopher2b_lcd_modes, 3717 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3718 .bpc = 8, 3719 .size = { 3720 .width = 95, 3721 .height = 54, 3722 }, 3723 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3724 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3725 .connector_type = DRM_MODE_CONNECTOR_DPI, 3726 }; 3727 3728 static const struct display_timing rocktech_rk070er9427_timing = { 3729 .pixelclock = { 26400000, 33300000, 46800000 }, 3730 .hactive = { 800, 800, 800 }, 3731 .hfront_porch = { 16, 210, 354 }, 3732 .hback_porch = { 46, 46, 46 }, 3733 .hsync_len = { 1, 1, 1 }, 3734 .vactive = { 480, 480, 480 }, 3735 .vfront_porch = { 7, 22, 147 }, 3736 .vback_porch = { 23, 23, 23 }, 3737 .vsync_len = { 1, 1, 1 }, 3738 .flags = DISPLAY_FLAGS_DE_HIGH, 3739 }; 3740 3741 static const struct panel_desc rocktech_rk070er9427 = { 3742 .timings = &rocktech_rk070er9427_timing, 3743 .num_timings = 1, 3744 .bpc = 6, 3745 .size = { 3746 .width = 154, 3747 .height = 86, 3748 }, 3749 .delay = { 3750 .prepare = 41, 3751 .enable = 50, 3752 .unprepare = 41, 3753 .disable = 50, 3754 }, 3755 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3756 }; 3757 3758 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3759 .clock = 71100, 3760 .hdisplay = 1280, 3761 .hsync_start = 1280 + 48, 3762 .hsync_end = 1280 + 48 + 32, 3763 .htotal = 1280 + 48 + 32 + 80, 3764 .vdisplay = 800, 3765 .vsync_start = 800 + 2, 3766 .vsync_end = 800 + 2 + 5, 3767 .vtotal = 800 + 2 + 5 + 16, 3768 }; 3769 3770 static const struct panel_desc rocktech_rk101ii01d_ct = { 3771 .modes = &rocktech_rk101ii01d_ct_mode, 3772 .num_modes = 1, 3773 .size = { 3774 .width = 217, 3775 .height = 136, 3776 }, 3777 .delay = { 3778 .prepare = 50, 3779 .disable = 50, 3780 }, 3781 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3783 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3784 }; 3785 3786 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3787 .clock = 271560, 3788 .hdisplay = 2560, 3789 .hsync_start = 2560 + 48, 3790 .hsync_end = 2560 + 48 + 32, 3791 .htotal = 2560 + 48 + 32 + 80, 3792 .vdisplay = 1600, 3793 .vsync_start = 1600 + 2, 3794 .vsync_end = 1600 + 2 + 5, 3795 .vtotal = 1600 + 2 + 5 + 57, 3796 }; 3797 3798 static const struct panel_desc samsung_lsn122dl01_c01 = { 3799 .modes = &samsung_lsn122dl01_c01_mode, 3800 .num_modes = 1, 3801 .size = { 3802 .width = 263, 3803 .height = 164, 3804 }, 3805 }; 3806 3807 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3808 .clock = 54030, 3809 .hdisplay = 1024, 3810 .hsync_start = 1024 + 24, 3811 .hsync_end = 1024 + 24 + 136, 3812 .htotal = 1024 + 24 + 136 + 160, 3813 .vdisplay = 600, 3814 .vsync_start = 600 + 3, 3815 .vsync_end = 600 + 3 + 6, 3816 .vtotal = 600 + 3 + 6 + 61, 3817 }; 3818 3819 static const struct panel_desc samsung_ltn101nt05 = { 3820 .modes = &samsung_ltn101nt05_mode, 3821 .num_modes = 1, 3822 .bpc = 6, 3823 .size = { 3824 .width = 223, 3825 .height = 125, 3826 }, 3827 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3828 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3829 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3830 }; 3831 3832 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3833 .clock = 76300, 3834 .hdisplay = 1366, 3835 .hsync_start = 1366 + 64, 3836 .hsync_end = 1366 + 64 + 48, 3837 .htotal = 1366 + 64 + 48 + 128, 3838 .vdisplay = 768, 3839 .vsync_start = 768 + 2, 3840 .vsync_end = 768 + 2 + 5, 3841 .vtotal = 768 + 2 + 5 + 17, 3842 }; 3843 3844 static const struct panel_desc samsung_ltn140at29_301 = { 3845 .modes = &samsung_ltn140at29_301_mode, 3846 .num_modes = 1, 3847 .bpc = 6, 3848 .size = { 3849 .width = 320, 3850 .height = 187, 3851 }, 3852 }; 3853 3854 static const struct display_timing satoz_sat050at40h12r2_timing = { 3855 .pixelclock = {33300000, 33300000, 50000000}, 3856 .hactive = {800, 800, 800}, 3857 .hfront_porch = {16, 210, 354}, 3858 .hback_porch = {46, 46, 46}, 3859 .hsync_len = {1, 1, 40}, 3860 .vactive = {480, 480, 480}, 3861 .vfront_porch = {7, 22, 147}, 3862 .vback_porch = {23, 23, 23}, 3863 .vsync_len = {1, 1, 20}, 3864 }; 3865 3866 static const struct panel_desc satoz_sat050at40h12r2 = { 3867 .timings = &satoz_sat050at40h12r2_timing, 3868 .num_timings = 1, 3869 .bpc = 8, 3870 .size = { 3871 .width = 108, 3872 .height = 65, 3873 }, 3874 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3875 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3876 }; 3877 3878 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3879 .clock = 168480, 3880 .hdisplay = 1920, 3881 .hsync_start = 1920 + 48, 3882 .hsync_end = 1920 + 48 + 32, 3883 .htotal = 1920 + 48 + 32 + 80, 3884 .vdisplay = 1280, 3885 .vsync_start = 1280 + 3, 3886 .vsync_end = 1280 + 3 + 10, 3887 .vtotal = 1280 + 3 + 10 + 57, 3888 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3889 }; 3890 3891 static const struct panel_desc sharp_ld_d5116z01b = { 3892 .modes = &sharp_ld_d5116z01b_mode, 3893 .num_modes = 1, 3894 .bpc = 8, 3895 .size = { 3896 .width = 260, 3897 .height = 120, 3898 }, 3899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3900 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3901 }; 3902 3903 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3904 .clock = 33260, 3905 .hdisplay = 800, 3906 .hsync_start = 800 + 64, 3907 .hsync_end = 800 + 64 + 128, 3908 .htotal = 800 + 64 + 128 + 64, 3909 .vdisplay = 480, 3910 .vsync_start = 480 + 8, 3911 .vsync_end = 480 + 8 + 2, 3912 .vtotal = 480 + 8 + 2 + 35, 3913 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3914 }; 3915 3916 static const struct panel_desc sharp_lq070y3dg3b = { 3917 .modes = &sharp_lq070y3dg3b_mode, 3918 .num_modes = 1, 3919 .bpc = 8, 3920 .size = { 3921 .width = 152, /* 152.4mm */ 3922 .height = 91, /* 91.4mm */ 3923 }, 3924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3926 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3927 }; 3928 3929 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3930 .clock = 5500, 3931 .hdisplay = 240, 3932 .hsync_start = 240 + 16, 3933 .hsync_end = 240 + 16 + 7, 3934 .htotal = 240 + 16 + 7 + 5, 3935 .vdisplay = 320, 3936 .vsync_start = 320 + 9, 3937 .vsync_end = 320 + 9 + 1, 3938 .vtotal = 320 + 9 + 1 + 7, 3939 }; 3940 3941 static const struct panel_desc sharp_lq035q7db03 = { 3942 .modes = &sharp_lq035q7db03_mode, 3943 .num_modes = 1, 3944 .bpc = 6, 3945 .size = { 3946 .width = 54, 3947 .height = 72, 3948 }, 3949 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3950 }; 3951 3952 static const struct display_timing sharp_lq101k1ly04_timing = { 3953 .pixelclock = { 60000000, 65000000, 80000000 }, 3954 .hactive = { 1280, 1280, 1280 }, 3955 .hfront_porch = { 20, 20, 20 }, 3956 .hback_porch = { 20, 20, 20 }, 3957 .hsync_len = { 10, 10, 10 }, 3958 .vactive = { 800, 800, 800 }, 3959 .vfront_porch = { 4, 4, 4 }, 3960 .vback_porch = { 4, 4, 4 }, 3961 .vsync_len = { 4, 4, 4 }, 3962 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3963 }; 3964 3965 static const struct panel_desc sharp_lq101k1ly04 = { 3966 .timings = &sharp_lq101k1ly04_timing, 3967 .num_timings = 1, 3968 .bpc = 8, 3969 .size = { 3970 .width = 217, 3971 .height = 136, 3972 }, 3973 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3974 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3975 }; 3976 3977 static const struct display_timing sharp_lq123p1jx31_timing = { 3978 .pixelclock = { 252750000, 252750000, 266604720 }, 3979 .hactive = { 2400, 2400, 2400 }, 3980 .hfront_porch = { 48, 48, 48 }, 3981 .hback_porch = { 80, 80, 84 }, 3982 .hsync_len = { 32, 32, 32 }, 3983 .vactive = { 1600, 1600, 1600 }, 3984 .vfront_porch = { 3, 3, 3 }, 3985 .vback_porch = { 33, 33, 120 }, 3986 .vsync_len = { 10, 10, 10 }, 3987 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3988 }; 3989 3990 static const struct panel_desc sharp_lq123p1jx31 = { 3991 .timings = &sharp_lq123p1jx31_timing, 3992 .num_timings = 1, 3993 .bpc = 8, 3994 .size = { 3995 .width = 259, 3996 .height = 173, 3997 }, 3998 .delay = { 3999 .prepare = 110, 4000 .enable = 50, 4001 .unprepare = 550, 4002 }, 4003 }; 4004 4005 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4006 { /* 50 Hz */ 4007 .clock = 3000, 4008 .hdisplay = 240, 4009 .hsync_start = 240 + 58, 4010 .hsync_end = 240 + 58 + 1, 4011 .htotal = 240 + 58 + 1 + 1, 4012 .vdisplay = 160, 4013 .vsync_start = 160 + 24, 4014 .vsync_end = 160 + 24 + 10, 4015 .vtotal = 160 + 24 + 10 + 6, 4016 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4017 }, 4018 { /* 60 Hz */ 4019 .clock = 3000, 4020 .hdisplay = 240, 4021 .hsync_start = 240 + 8, 4022 .hsync_end = 240 + 8 + 1, 4023 .htotal = 240 + 8 + 1 + 1, 4024 .vdisplay = 160, 4025 .vsync_start = 160 + 24, 4026 .vsync_end = 160 + 24 + 10, 4027 .vtotal = 160 + 24 + 10 + 6, 4028 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4029 }, 4030 }; 4031 4032 static const struct panel_desc sharp_ls020b1dd01d = { 4033 .modes = sharp_ls020b1dd01d_modes, 4034 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4035 .bpc = 6, 4036 .size = { 4037 .width = 42, 4038 .height = 28, 4039 }, 4040 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4041 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4042 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4043 | DRM_BUS_FLAG_SHARP_SIGNALS, 4044 }; 4045 4046 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4047 .clock = 33300, 4048 .hdisplay = 800, 4049 .hsync_start = 800 + 1, 4050 .hsync_end = 800 + 1 + 64, 4051 .htotal = 800 + 1 + 64 + 64, 4052 .vdisplay = 480, 4053 .vsync_start = 480 + 1, 4054 .vsync_end = 480 + 1 + 23, 4055 .vtotal = 480 + 1 + 23 + 22, 4056 }; 4057 4058 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4059 .modes = &shelly_sca07010_bfn_lnn_mode, 4060 .num_modes = 1, 4061 .size = { 4062 .width = 152, 4063 .height = 91, 4064 }, 4065 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4066 }; 4067 4068 static const struct drm_display_mode starry_kr070pe2t_mode = { 4069 .clock = 33000, 4070 .hdisplay = 800, 4071 .hsync_start = 800 + 209, 4072 .hsync_end = 800 + 209 + 1, 4073 .htotal = 800 + 209 + 1 + 45, 4074 .vdisplay = 480, 4075 .vsync_start = 480 + 22, 4076 .vsync_end = 480 + 22 + 1, 4077 .vtotal = 480 + 22 + 1 + 22, 4078 }; 4079 4080 static const struct panel_desc starry_kr070pe2t = { 4081 .modes = &starry_kr070pe2t_mode, 4082 .num_modes = 1, 4083 .bpc = 8, 4084 .size = { 4085 .width = 152, 4086 .height = 86, 4087 }, 4088 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4089 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4090 .connector_type = DRM_MODE_CONNECTOR_DPI, 4091 }; 4092 4093 static const struct drm_display_mode starry_kr122ea0sra_mode = { 4094 .clock = 147000, 4095 .hdisplay = 1920, 4096 .hsync_start = 1920 + 16, 4097 .hsync_end = 1920 + 16 + 16, 4098 .htotal = 1920 + 16 + 16 + 32, 4099 .vdisplay = 1200, 4100 .vsync_start = 1200 + 15, 4101 .vsync_end = 1200 + 15 + 2, 4102 .vtotal = 1200 + 15 + 2 + 18, 4103 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4104 }; 4105 4106 static const struct panel_desc starry_kr122ea0sra = { 4107 .modes = &starry_kr122ea0sra_mode, 4108 .num_modes = 1, 4109 .size = { 4110 .width = 263, 4111 .height = 164, 4112 }, 4113 .delay = { 4114 .prepare = 10 + 200, 4115 .enable = 50, 4116 .unprepare = 10 + 500, 4117 }, 4118 }; 4119 4120 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4121 .clock = 30000, 4122 .hdisplay = 800, 4123 .hsync_start = 800 + 39, 4124 .hsync_end = 800 + 39 + 47, 4125 .htotal = 800 + 39 + 47 + 39, 4126 .vdisplay = 480, 4127 .vsync_start = 480 + 13, 4128 .vsync_end = 480 + 13 + 2, 4129 .vtotal = 480 + 13 + 2 + 29, 4130 }; 4131 4132 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4133 .modes = &tfc_s9700rtwv43tr_01b_mode, 4134 .num_modes = 1, 4135 .bpc = 8, 4136 .size = { 4137 .width = 155, 4138 .height = 90, 4139 }, 4140 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4141 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4142 }; 4143 4144 static const struct display_timing tianma_tm070jdhg30_timing = { 4145 .pixelclock = { 62600000, 68200000, 78100000 }, 4146 .hactive = { 1280, 1280, 1280 }, 4147 .hfront_porch = { 15, 64, 159 }, 4148 .hback_porch = { 5, 5, 5 }, 4149 .hsync_len = { 1, 1, 256 }, 4150 .vactive = { 800, 800, 800 }, 4151 .vfront_porch = { 3, 40, 99 }, 4152 .vback_porch = { 2, 2, 2 }, 4153 .vsync_len = { 1, 1, 128 }, 4154 .flags = DISPLAY_FLAGS_DE_HIGH, 4155 }; 4156 4157 static const struct panel_desc tianma_tm070jdhg30 = { 4158 .timings = &tianma_tm070jdhg30_timing, 4159 .num_timings = 1, 4160 .bpc = 8, 4161 .size = { 4162 .width = 151, 4163 .height = 95, 4164 }, 4165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4167 }; 4168 4169 static const struct panel_desc tianma_tm070jvhg33 = { 4170 .timings = &tianma_tm070jdhg30_timing, 4171 .num_timings = 1, 4172 .bpc = 8, 4173 .size = { 4174 .width = 150, 4175 .height = 94, 4176 }, 4177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4178 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4179 }; 4180 4181 static const struct display_timing tianma_tm070rvhg71_timing = { 4182 .pixelclock = { 27700000, 29200000, 39600000 }, 4183 .hactive = { 800, 800, 800 }, 4184 .hfront_porch = { 12, 40, 212 }, 4185 .hback_porch = { 88, 88, 88 }, 4186 .hsync_len = { 1, 1, 40 }, 4187 .vactive = { 480, 480, 480 }, 4188 .vfront_porch = { 1, 13, 88 }, 4189 .vback_porch = { 32, 32, 32 }, 4190 .vsync_len = { 1, 1, 3 }, 4191 .flags = DISPLAY_FLAGS_DE_HIGH, 4192 }; 4193 4194 static const struct panel_desc tianma_tm070rvhg71 = { 4195 .timings = &tianma_tm070rvhg71_timing, 4196 .num_timings = 1, 4197 .bpc = 8, 4198 .size = { 4199 .width = 154, 4200 .height = 86, 4201 }, 4202 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4203 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4204 }; 4205 4206 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4207 { 4208 .clock = 10000, 4209 .hdisplay = 320, 4210 .hsync_start = 320 + 50, 4211 .hsync_end = 320 + 50 + 6, 4212 .htotal = 320 + 50 + 6 + 38, 4213 .vdisplay = 240, 4214 .vsync_start = 240 + 3, 4215 .vsync_end = 240 + 3 + 1, 4216 .vtotal = 240 + 3 + 1 + 17, 4217 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4218 }, 4219 }; 4220 4221 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4222 .modes = ti_nspire_cx_lcd_mode, 4223 .num_modes = 1, 4224 .bpc = 8, 4225 .size = { 4226 .width = 65, 4227 .height = 49, 4228 }, 4229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4230 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4231 }; 4232 4233 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4234 { 4235 .clock = 10000, 4236 .hdisplay = 320, 4237 .hsync_start = 320 + 6, 4238 .hsync_end = 320 + 6 + 6, 4239 .htotal = 320 + 6 + 6 + 6, 4240 .vdisplay = 240, 4241 .vsync_start = 240 + 0, 4242 .vsync_end = 240 + 0 + 1, 4243 .vtotal = 240 + 0 + 1 + 0, 4244 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4245 }, 4246 }; 4247 4248 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4249 .modes = ti_nspire_classic_lcd_mode, 4250 .num_modes = 1, 4251 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4252 .bpc = 8, 4253 .size = { 4254 .width = 71, 4255 .height = 53, 4256 }, 4257 /* This is the grayscale bus format */ 4258 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4259 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4260 }; 4261 4262 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4263 .clock = 79500, 4264 .hdisplay = 1280, 4265 .hsync_start = 1280 + 192, 4266 .hsync_end = 1280 + 192 + 128, 4267 .htotal = 1280 + 192 + 128 + 64, 4268 .vdisplay = 768, 4269 .vsync_start = 768 + 20, 4270 .vsync_end = 768 + 20 + 7, 4271 .vtotal = 768 + 20 + 7 + 3, 4272 }; 4273 4274 static const struct panel_desc toshiba_lt089ac29000 = { 4275 .modes = &toshiba_lt089ac29000_mode, 4276 .num_modes = 1, 4277 .size = { 4278 .width = 194, 4279 .height = 116, 4280 }, 4281 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4282 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4283 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4284 }; 4285 4286 static const struct drm_display_mode tpk_f07a_0102_mode = { 4287 .clock = 33260, 4288 .hdisplay = 800, 4289 .hsync_start = 800 + 40, 4290 .hsync_end = 800 + 40 + 128, 4291 .htotal = 800 + 40 + 128 + 88, 4292 .vdisplay = 480, 4293 .vsync_start = 480 + 10, 4294 .vsync_end = 480 + 10 + 2, 4295 .vtotal = 480 + 10 + 2 + 33, 4296 }; 4297 4298 static const struct panel_desc tpk_f07a_0102 = { 4299 .modes = &tpk_f07a_0102_mode, 4300 .num_modes = 1, 4301 .size = { 4302 .width = 152, 4303 .height = 91, 4304 }, 4305 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4306 }; 4307 4308 static const struct drm_display_mode tpk_f10a_0102_mode = { 4309 .clock = 45000, 4310 .hdisplay = 1024, 4311 .hsync_start = 1024 + 176, 4312 .hsync_end = 1024 + 176 + 5, 4313 .htotal = 1024 + 176 + 5 + 88, 4314 .vdisplay = 600, 4315 .vsync_start = 600 + 20, 4316 .vsync_end = 600 + 20 + 5, 4317 .vtotal = 600 + 20 + 5 + 25, 4318 }; 4319 4320 static const struct panel_desc tpk_f10a_0102 = { 4321 .modes = &tpk_f10a_0102_mode, 4322 .num_modes = 1, 4323 .size = { 4324 .width = 223, 4325 .height = 125, 4326 }, 4327 }; 4328 4329 static const struct display_timing urt_umsh_8596md_timing = { 4330 .pixelclock = { 33260000, 33260000, 33260000 }, 4331 .hactive = { 800, 800, 800 }, 4332 .hfront_porch = { 41, 41, 41 }, 4333 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4334 .hsync_len = { 71, 128, 128 }, 4335 .vactive = { 480, 480, 480 }, 4336 .vfront_porch = { 10, 10, 10 }, 4337 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4338 .vsync_len = { 2, 2, 2 }, 4339 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4340 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4341 }; 4342 4343 static const struct panel_desc urt_umsh_8596md_lvds = { 4344 .timings = &urt_umsh_8596md_timing, 4345 .num_timings = 1, 4346 .bpc = 6, 4347 .size = { 4348 .width = 152, 4349 .height = 91, 4350 }, 4351 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4352 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4353 }; 4354 4355 static const struct panel_desc urt_umsh_8596md_parallel = { 4356 .timings = &urt_umsh_8596md_timing, 4357 .num_timings = 1, 4358 .bpc = 6, 4359 .size = { 4360 .width = 152, 4361 .height = 91, 4362 }, 4363 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4364 }; 4365 4366 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4367 .clock = 33333, 4368 .hdisplay = 800, 4369 .hsync_start = 800 + 210, 4370 .hsync_end = 800 + 210 + 20, 4371 .htotal = 800 + 210 + 20 + 46, 4372 .vdisplay = 480, 4373 .vsync_start = 480 + 22, 4374 .vsync_end = 480 + 22 + 10, 4375 .vtotal = 480 + 22 + 10 + 23, 4376 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4377 }; 4378 4379 static const struct panel_desc vl050_8048nt_c01 = { 4380 .modes = &vl050_8048nt_c01_mode, 4381 .num_modes = 1, 4382 .bpc = 8, 4383 .size = { 4384 .width = 120, 4385 .height = 76, 4386 }, 4387 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4388 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4389 }; 4390 4391 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4392 .clock = 6410, 4393 .hdisplay = 320, 4394 .hsync_start = 320 + 20, 4395 .hsync_end = 320 + 20 + 30, 4396 .htotal = 320 + 20 + 30 + 38, 4397 .vdisplay = 240, 4398 .vsync_start = 240 + 4, 4399 .vsync_end = 240 + 4 + 3, 4400 .vtotal = 240 + 4 + 3 + 15, 4401 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4402 }; 4403 4404 static const struct panel_desc winstar_wf35ltiacd = { 4405 .modes = &winstar_wf35ltiacd_mode, 4406 .num_modes = 1, 4407 .bpc = 8, 4408 .size = { 4409 .width = 70, 4410 .height = 53, 4411 }, 4412 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4413 }; 4414 4415 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4416 .clock = 51200, 4417 .hdisplay = 1024, 4418 .hsync_start = 1024 + 100, 4419 .hsync_end = 1024 + 100 + 100, 4420 .htotal = 1024 + 100 + 100 + 120, 4421 .vdisplay = 600, 4422 .vsync_start = 600 + 10, 4423 .vsync_end = 600 + 10 + 10, 4424 .vtotal = 600 + 10 + 10 + 15, 4425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4426 }; 4427 4428 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4429 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4430 .num_modes = 1, 4431 .bpc = 8, 4432 .size = { 4433 .width = 154, 4434 .height = 90, 4435 }, 4436 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4437 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4438 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4439 }; 4440 4441 static const struct drm_display_mode arm_rtsm_mode[] = { 4442 { 4443 .clock = 65000, 4444 .hdisplay = 1024, 4445 .hsync_start = 1024 + 24, 4446 .hsync_end = 1024 + 24 + 136, 4447 .htotal = 1024 + 24 + 136 + 160, 4448 .vdisplay = 768, 4449 .vsync_start = 768 + 3, 4450 .vsync_end = 768 + 3 + 6, 4451 .vtotal = 768 + 3 + 6 + 29, 4452 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4453 }, 4454 }; 4455 4456 static const struct panel_desc arm_rtsm = { 4457 .modes = arm_rtsm_mode, 4458 .num_modes = 1, 4459 .bpc = 8, 4460 .size = { 4461 .width = 400, 4462 .height = 300, 4463 }, 4464 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4465 }; 4466 4467 static const struct of_device_id platform_of_match[] = { 4468 { 4469 .compatible = "ampire,am-1280800n3tzqw-t00h", 4470 .data = &ire_am_1280800n3tzqw_t00h, 4471 }, { 4472 .compatible = "ampire,am-480272h3tmqw-t01h", 4473 .data = &ire_am_480272h3tmqw_t01h, 4474 }, { 4475 .compatible = "ampire,am800480r3tmqwa1h", 4476 .data = &ire_am800480r3tmqwa1h, 4477 }, { 4478 .compatible = "arm,rtsm-display", 4479 .data = &arm_rtsm, 4480 }, { 4481 .compatible = "armadeus,st0700-adapt", 4482 .data = &armadeus_st0700_adapt, 4483 }, { 4484 .compatible = "auo,b101aw03", 4485 .data = &auo_b101aw03, 4486 }, { 4487 .compatible = "auo,b101ean01", 4488 .data = &auo_b101ean01, 4489 }, { 4490 .compatible = "auo,b101xtn01", 4491 .data = &auo_b101xtn01, 4492 }, { 4493 .compatible = "auo,b116xa01", 4494 .data = &auo_b116xak01, 4495 }, { 4496 .compatible = "auo,b116xw03", 4497 .data = &auo_b116xw03, 4498 }, { 4499 .compatible = "auo,b133han05", 4500 .data = &auo_b133han05, 4501 }, { 4502 .compatible = "auo,b133htn01", 4503 .data = &auo_b133htn01, 4504 }, { 4505 .compatible = "auo,b140han06", 4506 .data = &auo_b140han06, 4507 }, { 4508 .compatible = "auo,b133xtn01", 4509 .data = &auo_b133xtn01, 4510 }, { 4511 .compatible = "auo,g070vvn01", 4512 .data = &auo_g070vvn01, 4513 }, { 4514 .compatible = "auo,g101evn010", 4515 .data = &auo_g101evn010, 4516 }, { 4517 .compatible = "auo,g104sn02", 4518 .data = &auo_g104sn02, 4519 }, { 4520 .compatible = "auo,g121ean01", 4521 .data = &auo_g121ean01, 4522 }, { 4523 .compatible = "auo,g133han01", 4524 .data = &auo_g133han01, 4525 }, { 4526 .compatible = "auo,g156xtn01", 4527 .data = &auo_g156xtn01, 4528 }, { 4529 .compatible = "auo,g185han01", 4530 .data = &auo_g185han01, 4531 }, { 4532 .compatible = "auo,g190ean01", 4533 .data = &auo_g190ean01, 4534 }, { 4535 .compatible = "auo,p320hvn03", 4536 .data = &auo_p320hvn03, 4537 }, { 4538 .compatible = "auo,t215hvn01", 4539 .data = &auo_t215hvn01, 4540 }, { 4541 .compatible = "avic,tm070ddh03", 4542 .data = &avic_tm070ddh03, 4543 }, { 4544 .compatible = "bananapi,s070wv20-ct16", 4545 .data = &bananapi_s070wv20_ct16, 4546 }, { 4547 .compatible = "boe,hv070wsa-100", 4548 .data = &boe_hv070wsa 4549 }, { 4550 .compatible = "boe,nv101wxmn51", 4551 .data = &boe_nv101wxmn51, 4552 }, { 4553 .compatible = "boe,nv110wtm-n61", 4554 .data = &boe_nv110wtm_n61, 4555 }, { 4556 .compatible = "boe,nv133fhm-n61", 4557 .data = &boe_nv133fhm_n61, 4558 }, { 4559 .compatible = "boe,nv133fhm-n62", 4560 .data = &boe_nv133fhm_n61, 4561 }, { 4562 .compatible = "boe,nv140fhmn49", 4563 .data = &boe_nv140fhmn49, 4564 }, { 4565 .compatible = "cdtech,s043wq26h-ct7", 4566 .data = &cdtech_s043wq26h_ct7, 4567 }, { 4568 .compatible = "cdtech,s070pws19hp-fc21", 4569 .data = &cdtech_s070pws19hp_fc21, 4570 }, { 4571 .compatible = "cdtech,s070swv29hg-dc44", 4572 .data = &cdtech_s070swv29hg_dc44, 4573 }, { 4574 .compatible = "cdtech,s070wv95-ct16", 4575 .data = &cdtech_s070wv95_ct16, 4576 }, { 4577 .compatible = "chefree,ch101olhlwh-002", 4578 .data = &chefree_ch101olhlwh_002, 4579 }, { 4580 .compatible = "chunghwa,claa070wp03xg", 4581 .data = &chunghwa_claa070wp03xg, 4582 }, { 4583 .compatible = "chunghwa,claa101wa01a", 4584 .data = &chunghwa_claa101wa01a 4585 }, { 4586 .compatible = "chunghwa,claa101wb01", 4587 .data = &chunghwa_claa101wb01 4588 }, { 4589 .compatible = "dataimage,scf0700c48ggu18", 4590 .data = &dataimage_scf0700c48ggu18, 4591 }, { 4592 .compatible = "dlc,dlc0700yzg-1", 4593 .data = &dlc_dlc0700yzg_1, 4594 }, { 4595 .compatible = "dlc,dlc1010gig", 4596 .data = &dlc_dlc1010gig, 4597 }, { 4598 .compatible = "edt,et035012dm6", 4599 .data = &edt_et035012dm6, 4600 }, { 4601 .compatible = "edt,etm0350g0dh6", 4602 .data = &edt_etm0350g0dh6, 4603 }, { 4604 .compatible = "edt,etm043080dh6gp", 4605 .data = &edt_etm043080dh6gp, 4606 }, { 4607 .compatible = "edt,etm0430g0dh6", 4608 .data = &edt_etm0430g0dh6, 4609 }, { 4610 .compatible = "edt,et057090dhu", 4611 .data = &edt_et057090dhu, 4612 }, { 4613 .compatible = "edt,et070080dh6", 4614 .data = &edt_etm0700g0dh6, 4615 }, { 4616 .compatible = "edt,etm0700g0dh6", 4617 .data = &edt_etm0700g0dh6, 4618 }, { 4619 .compatible = "edt,etm0700g0bdh6", 4620 .data = &edt_etm0700g0bdh6, 4621 }, { 4622 .compatible = "edt,etm0700g0edh6", 4623 .data = &edt_etm0700g0bdh6, 4624 }, { 4625 .compatible = "edt,etmv570g2dhu", 4626 .data = &edt_etmv570g2dhu, 4627 }, { 4628 .compatible = "eink,vb3300-kca", 4629 .data = &eink_vb3300_kca, 4630 }, { 4631 .compatible = "evervision,vgg804821", 4632 .data = &evervision_vgg804821, 4633 }, { 4634 .compatible = "foxlink,fl500wvr00-a0t", 4635 .data = &foxlink_fl500wvr00_a0t, 4636 }, { 4637 .compatible = "frida,frd350h54004", 4638 .data = &frida_frd350h54004, 4639 }, { 4640 .compatible = "friendlyarm,hd702e", 4641 .data = &friendlyarm_hd702e, 4642 }, { 4643 .compatible = "giantplus,gpg482739qs5", 4644 .data = &giantplus_gpg482739qs5 4645 }, { 4646 .compatible = "giantplus,gpm940b0", 4647 .data = &giantplus_gpm940b0, 4648 }, { 4649 .compatible = "hannstar,hsd070pww1", 4650 .data = &hannstar_hsd070pww1, 4651 }, { 4652 .compatible = "hannstar,hsd100pxn1", 4653 .data = &hannstar_hsd100pxn1, 4654 }, { 4655 .compatible = "hit,tx23d38vm0caa", 4656 .data = &hitachi_tx23d38vm0caa 4657 }, { 4658 .compatible = "innolux,at043tn24", 4659 .data = &innolux_at043tn24, 4660 }, { 4661 .compatible = "innolux,at070tn92", 4662 .data = &innolux_at070tn92, 4663 }, { 4664 .compatible = "innolux,g070y2-l01", 4665 .data = &innolux_g070y2_l01, 4666 }, { 4667 .compatible = "innolux,g101ice-l01", 4668 .data = &innolux_g101ice_l01 4669 }, { 4670 .compatible = "innolux,g121i1-l01", 4671 .data = &innolux_g121i1_l01 4672 }, { 4673 .compatible = "innolux,g121x1-l03", 4674 .data = &innolux_g121x1_l03, 4675 }, { 4676 .compatible = "innolux,n116bca-ea1", 4677 .data = &innolux_n116bca_ea1, 4678 }, { 4679 .compatible = "innolux,n116bge", 4680 .data = &innolux_n116bge, 4681 }, { 4682 .compatible = "innolux,n125hce-gn1", 4683 .data = &innolux_n125hce_gn1, 4684 }, { 4685 .compatible = "innolux,n156bge-l21", 4686 .data = &innolux_n156bge_l21, 4687 }, { 4688 .compatible = "innolux,p120zdg-bf1", 4689 .data = &innolux_p120zdg_bf1, 4690 }, { 4691 .compatible = "innolux,zj070na-01p", 4692 .data = &innolux_zj070na_01p, 4693 }, { 4694 .compatible = "ivo,m133nwf4-r0", 4695 .data = &ivo_m133nwf4_r0, 4696 }, { 4697 .compatible = "kingdisplay,kd116n21-30nv-a010", 4698 .data = &kingdisplay_kd116n21_30nv_a010, 4699 }, { 4700 .compatible = "koe,tx14d24vm1bpa", 4701 .data = &koe_tx14d24vm1bpa, 4702 }, { 4703 .compatible = "koe,tx26d202vm0bwa", 4704 .data = &koe_tx26d202vm0bwa, 4705 }, { 4706 .compatible = "koe,tx31d200vm0baa", 4707 .data = &koe_tx31d200vm0baa, 4708 }, { 4709 .compatible = "kyo,tcg121xglp", 4710 .data = &kyo_tcg121xglp, 4711 }, { 4712 .compatible = "lemaker,bl035-rgb-002", 4713 .data = &lemaker_bl035_rgb_002, 4714 }, { 4715 .compatible = "lg,lb070wv8", 4716 .data = &lg_lb070wv8, 4717 }, { 4718 .compatible = "lg,lp079qx1-sp0v", 4719 .data = &lg_lp079qx1_sp0v, 4720 }, { 4721 .compatible = "lg,lp097qx1-spa1", 4722 .data = &lg_lp097qx1_spa1, 4723 }, { 4724 .compatible = "lg,lp120up1", 4725 .data = &lg_lp120up1, 4726 }, { 4727 .compatible = "lg,lp129qe", 4728 .data = &lg_lp129qe, 4729 }, { 4730 .compatible = "logicpd,type28", 4731 .data = &logicpd_type_28, 4732 }, { 4733 .compatible = "logictechno,lt161010-2nhc", 4734 .data = &logictechno_lt161010_2nh, 4735 }, { 4736 .compatible = "logictechno,lt161010-2nhr", 4737 .data = &logictechno_lt161010_2nh, 4738 }, { 4739 .compatible = "logictechno,lt170410-2whc", 4740 .data = &logictechno_lt170410_2whc, 4741 }, { 4742 .compatible = "logictechno,lttd800480070-l6wh-rt", 4743 .data = &logictechno_lttd800480070_l6wh_rt, 4744 }, { 4745 .compatible = "mitsubishi,aa070mc01-ca1", 4746 .data = &mitsubishi_aa070mc01, 4747 }, { 4748 .compatible = "multi-inno,mi1010ait-1cp", 4749 .data = &multi_inno_mi1010ait_1cp, 4750 }, { 4751 .compatible = "nec,nl12880bc20-05", 4752 .data = &nec_nl12880bc20_05, 4753 }, { 4754 .compatible = "nec,nl4827hc19-05b", 4755 .data = &nec_nl4827hc19_05b, 4756 }, { 4757 .compatible = "netron-dy,e231732", 4758 .data = &netron_dy_e231732, 4759 }, { 4760 .compatible = "neweast,wjfh116008a", 4761 .data = &neweast_wjfh116008a, 4762 }, { 4763 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4764 .data = &newhaven_nhd_43_480272ef_atxl, 4765 }, { 4766 .compatible = "nlt,nl192108ac18-02d", 4767 .data = &nlt_nl192108ac18_02d, 4768 }, { 4769 .compatible = "nvd,9128", 4770 .data = &nvd_9128, 4771 }, { 4772 .compatible = "okaya,rs800480t-7x0gp", 4773 .data = &okaya_rs800480t_7x0gp, 4774 }, { 4775 .compatible = "olimex,lcd-olinuxino-43-ts", 4776 .data = &olimex_lcd_olinuxino_43ts, 4777 }, { 4778 .compatible = "ontat,yx700wv03", 4779 .data = &ontat_yx700wv03, 4780 }, { 4781 .compatible = "ortustech,com37h3m05dtc", 4782 .data = &ortustech_com37h3m, 4783 }, { 4784 .compatible = "ortustech,com37h3m99dtc", 4785 .data = &ortustech_com37h3m, 4786 }, { 4787 .compatible = "ortustech,com43h4m85ulc", 4788 .data = &ortustech_com43h4m85ulc, 4789 }, { 4790 .compatible = "osddisplays,osd070t1718-19ts", 4791 .data = &osddisplays_osd070t1718_19ts, 4792 }, { 4793 .compatible = "pda,91-00156-a0", 4794 .data = &pda_91_00156_a0, 4795 }, { 4796 .compatible = "powertip,ph800480t013-idf02", 4797 .data = &powertip_ph800480t013_idf02, 4798 }, { 4799 .compatible = "qiaodian,qd43003c0-40", 4800 .data = &qd43003c0_40, 4801 }, { 4802 .compatible = "qishenglong,gopher2b-lcd", 4803 .data = &qishenglong_gopher2b_lcd, 4804 }, { 4805 .compatible = "rocktech,rk070er9427", 4806 .data = &rocktech_rk070er9427, 4807 }, { 4808 .compatible = "rocktech,rk101ii01d-ct", 4809 .data = &rocktech_rk101ii01d_ct, 4810 }, { 4811 .compatible = "samsung,lsn122dl01-c01", 4812 .data = &samsung_lsn122dl01_c01, 4813 }, { 4814 .compatible = "samsung,ltn101nt05", 4815 .data = &samsung_ltn101nt05, 4816 }, { 4817 .compatible = "samsung,ltn140at29-301", 4818 .data = &samsung_ltn140at29_301, 4819 }, { 4820 .compatible = "satoz,sat050at40h12r2", 4821 .data = &satoz_sat050at40h12r2, 4822 }, { 4823 .compatible = "sharp,ld-d5116z01b", 4824 .data = &sharp_ld_d5116z01b, 4825 }, { 4826 .compatible = "sharp,lq035q7db03", 4827 .data = &sharp_lq035q7db03, 4828 }, { 4829 .compatible = "sharp,lq070y3dg3b", 4830 .data = &sharp_lq070y3dg3b, 4831 }, { 4832 .compatible = "sharp,lq101k1ly04", 4833 .data = &sharp_lq101k1ly04, 4834 }, { 4835 .compatible = "sharp,lq123p1jx31", 4836 .data = &sharp_lq123p1jx31, 4837 }, { 4838 .compatible = "sharp,ls020b1dd01d", 4839 .data = &sharp_ls020b1dd01d, 4840 }, { 4841 .compatible = "shelly,sca07010-bfn-lnn", 4842 .data = &shelly_sca07010_bfn_lnn, 4843 }, { 4844 .compatible = "starry,kr070pe2t", 4845 .data = &starry_kr070pe2t, 4846 }, { 4847 .compatible = "starry,kr122ea0sra", 4848 .data = &starry_kr122ea0sra, 4849 }, { 4850 .compatible = "tfc,s9700rtwv43tr-01b", 4851 .data = &tfc_s9700rtwv43tr_01b, 4852 }, { 4853 .compatible = "tianma,tm070jdhg30", 4854 .data = &tianma_tm070jdhg30, 4855 }, { 4856 .compatible = "tianma,tm070jvhg33", 4857 .data = &tianma_tm070jvhg33, 4858 }, { 4859 .compatible = "tianma,tm070rvhg71", 4860 .data = &tianma_tm070rvhg71, 4861 }, { 4862 .compatible = "ti,nspire-cx-lcd-panel", 4863 .data = &ti_nspire_cx_lcd_panel, 4864 }, { 4865 .compatible = "ti,nspire-classic-lcd-panel", 4866 .data = &ti_nspire_classic_lcd_panel, 4867 }, { 4868 .compatible = "toshiba,lt089ac29000", 4869 .data = &toshiba_lt089ac29000, 4870 }, { 4871 .compatible = "tpk,f07a-0102", 4872 .data = &tpk_f07a_0102, 4873 }, { 4874 .compatible = "tpk,f10a-0102", 4875 .data = &tpk_f10a_0102, 4876 }, { 4877 .compatible = "urt,umsh-8596md-t", 4878 .data = &urt_umsh_8596md_parallel, 4879 }, { 4880 .compatible = "urt,umsh-8596md-1t", 4881 .data = &urt_umsh_8596md_parallel, 4882 }, { 4883 .compatible = "urt,umsh-8596md-7t", 4884 .data = &urt_umsh_8596md_parallel, 4885 }, { 4886 .compatible = "urt,umsh-8596md-11t", 4887 .data = &urt_umsh_8596md_lvds, 4888 }, { 4889 .compatible = "urt,umsh-8596md-19t", 4890 .data = &urt_umsh_8596md_lvds, 4891 }, { 4892 .compatible = "urt,umsh-8596md-20t", 4893 .data = &urt_umsh_8596md_parallel, 4894 }, { 4895 .compatible = "vxt,vl050-8048nt-c01", 4896 .data = &vl050_8048nt_c01, 4897 }, { 4898 .compatible = "winstar,wf35ltiacd", 4899 .data = &winstar_wf35ltiacd, 4900 }, { 4901 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4902 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4903 }, { 4904 /* Must be the last entry */ 4905 .compatible = "panel-dpi", 4906 .data = &panel_dpi, 4907 }, { 4908 /* sentinel */ 4909 } 4910 }; 4911 MODULE_DEVICE_TABLE(of, platform_of_match); 4912 4913 static int panel_simple_platform_probe(struct platform_device *pdev) 4914 { 4915 const struct of_device_id *id; 4916 4917 id = of_match_node(platform_of_match, pdev->dev.of_node); 4918 if (!id) 4919 return -ENODEV; 4920 4921 return panel_simple_probe(&pdev->dev, id->data, NULL); 4922 } 4923 4924 static int panel_simple_platform_remove(struct platform_device *pdev) 4925 { 4926 return panel_simple_remove(&pdev->dev); 4927 } 4928 4929 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4930 { 4931 panel_simple_shutdown(&pdev->dev); 4932 } 4933 4934 static const struct dev_pm_ops panel_simple_pm_ops = { 4935 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4936 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4937 pm_runtime_force_resume) 4938 }; 4939 4940 static struct platform_driver panel_simple_platform_driver = { 4941 .driver = { 4942 .name = "panel-simple", 4943 .of_match_table = platform_of_match, 4944 .pm = &panel_simple_pm_ops, 4945 }, 4946 .probe = panel_simple_platform_probe, 4947 .remove = panel_simple_platform_remove, 4948 .shutdown = panel_simple_platform_shutdown, 4949 }; 4950 4951 struct panel_desc_dsi { 4952 struct panel_desc desc; 4953 4954 unsigned long flags; 4955 enum mipi_dsi_pixel_format format; 4956 unsigned int lanes; 4957 }; 4958 4959 static const struct drm_display_mode auo_b080uan01_mode = { 4960 .clock = 154500, 4961 .hdisplay = 1200, 4962 .hsync_start = 1200 + 62, 4963 .hsync_end = 1200 + 62 + 4, 4964 .htotal = 1200 + 62 + 4 + 62, 4965 .vdisplay = 1920, 4966 .vsync_start = 1920 + 9, 4967 .vsync_end = 1920 + 9 + 2, 4968 .vtotal = 1920 + 9 + 2 + 8, 4969 }; 4970 4971 static const struct panel_desc_dsi auo_b080uan01 = { 4972 .desc = { 4973 .modes = &auo_b080uan01_mode, 4974 .num_modes = 1, 4975 .bpc = 8, 4976 .size = { 4977 .width = 108, 4978 .height = 272, 4979 }, 4980 .connector_type = DRM_MODE_CONNECTOR_DSI, 4981 }, 4982 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4983 .format = MIPI_DSI_FMT_RGB888, 4984 .lanes = 4, 4985 }; 4986 4987 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4988 .clock = 160000, 4989 .hdisplay = 1200, 4990 .hsync_start = 1200 + 120, 4991 .hsync_end = 1200 + 120 + 20, 4992 .htotal = 1200 + 120 + 20 + 21, 4993 .vdisplay = 1920, 4994 .vsync_start = 1920 + 21, 4995 .vsync_end = 1920 + 21 + 3, 4996 .vtotal = 1920 + 21 + 3 + 18, 4997 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4998 }; 4999 5000 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5001 .desc = { 5002 .modes = &boe_tv080wum_nl0_mode, 5003 .num_modes = 1, 5004 .size = { 5005 .width = 107, 5006 .height = 172, 5007 }, 5008 .connector_type = DRM_MODE_CONNECTOR_DSI, 5009 }, 5010 .flags = MIPI_DSI_MODE_VIDEO | 5011 MIPI_DSI_MODE_VIDEO_BURST | 5012 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5013 .format = MIPI_DSI_FMT_RGB888, 5014 .lanes = 4, 5015 }; 5016 5017 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5018 .clock = 71000, 5019 .hdisplay = 800, 5020 .hsync_start = 800 + 32, 5021 .hsync_end = 800 + 32 + 1, 5022 .htotal = 800 + 32 + 1 + 57, 5023 .vdisplay = 1280, 5024 .vsync_start = 1280 + 28, 5025 .vsync_end = 1280 + 28 + 1, 5026 .vtotal = 1280 + 28 + 1 + 14, 5027 }; 5028 5029 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5030 .desc = { 5031 .modes = &lg_ld070wx3_sl01_mode, 5032 .num_modes = 1, 5033 .bpc = 8, 5034 .size = { 5035 .width = 94, 5036 .height = 151, 5037 }, 5038 .connector_type = DRM_MODE_CONNECTOR_DSI, 5039 }, 5040 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5041 .format = MIPI_DSI_FMT_RGB888, 5042 .lanes = 4, 5043 }; 5044 5045 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5046 .clock = 67000, 5047 .hdisplay = 720, 5048 .hsync_start = 720 + 12, 5049 .hsync_end = 720 + 12 + 4, 5050 .htotal = 720 + 12 + 4 + 112, 5051 .vdisplay = 1280, 5052 .vsync_start = 1280 + 8, 5053 .vsync_end = 1280 + 8 + 4, 5054 .vtotal = 1280 + 8 + 4 + 12, 5055 }; 5056 5057 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5058 .desc = { 5059 .modes = &lg_lh500wx1_sd03_mode, 5060 .num_modes = 1, 5061 .bpc = 8, 5062 .size = { 5063 .width = 62, 5064 .height = 110, 5065 }, 5066 .connector_type = DRM_MODE_CONNECTOR_DSI, 5067 }, 5068 .flags = MIPI_DSI_MODE_VIDEO, 5069 .format = MIPI_DSI_FMT_RGB888, 5070 .lanes = 4, 5071 }; 5072 5073 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5074 .clock = 157200, 5075 .hdisplay = 1920, 5076 .hsync_start = 1920 + 154, 5077 .hsync_end = 1920 + 154 + 16, 5078 .htotal = 1920 + 154 + 16 + 32, 5079 .vdisplay = 1200, 5080 .vsync_start = 1200 + 17, 5081 .vsync_end = 1200 + 17 + 2, 5082 .vtotal = 1200 + 17 + 2 + 16, 5083 }; 5084 5085 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5086 .desc = { 5087 .modes = &panasonic_vvx10f004b00_mode, 5088 .num_modes = 1, 5089 .bpc = 8, 5090 .size = { 5091 .width = 217, 5092 .height = 136, 5093 }, 5094 .connector_type = DRM_MODE_CONNECTOR_DSI, 5095 }, 5096 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5097 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5098 .format = MIPI_DSI_FMT_RGB888, 5099 .lanes = 4, 5100 }; 5101 5102 static const struct drm_display_mode lg_acx467akm_7_mode = { 5103 .clock = 150000, 5104 .hdisplay = 1080, 5105 .hsync_start = 1080 + 2, 5106 .hsync_end = 1080 + 2 + 2, 5107 .htotal = 1080 + 2 + 2 + 2, 5108 .vdisplay = 1920, 5109 .vsync_start = 1920 + 2, 5110 .vsync_end = 1920 + 2 + 2, 5111 .vtotal = 1920 + 2 + 2 + 2, 5112 }; 5113 5114 static const struct panel_desc_dsi lg_acx467akm_7 = { 5115 .desc = { 5116 .modes = &lg_acx467akm_7_mode, 5117 .num_modes = 1, 5118 .bpc = 8, 5119 .size = { 5120 .width = 62, 5121 .height = 110, 5122 }, 5123 .connector_type = DRM_MODE_CONNECTOR_DSI, 5124 }, 5125 .flags = 0, 5126 .format = MIPI_DSI_FMT_RGB888, 5127 .lanes = 4, 5128 }; 5129 5130 static const struct drm_display_mode osd101t2045_53ts_mode = { 5131 .clock = 154500, 5132 .hdisplay = 1920, 5133 .hsync_start = 1920 + 112, 5134 .hsync_end = 1920 + 112 + 16, 5135 .htotal = 1920 + 112 + 16 + 32, 5136 .vdisplay = 1200, 5137 .vsync_start = 1200 + 16, 5138 .vsync_end = 1200 + 16 + 2, 5139 .vtotal = 1200 + 16 + 2 + 16, 5140 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5141 }; 5142 5143 static const struct panel_desc_dsi osd101t2045_53ts = { 5144 .desc = { 5145 .modes = &osd101t2045_53ts_mode, 5146 .num_modes = 1, 5147 .bpc = 8, 5148 .size = { 5149 .width = 217, 5150 .height = 136, 5151 }, 5152 .connector_type = DRM_MODE_CONNECTOR_DSI, 5153 }, 5154 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5155 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5156 MIPI_DSI_MODE_NO_EOT_PACKET, 5157 .format = MIPI_DSI_FMT_RGB888, 5158 .lanes = 4, 5159 }; 5160 5161 static const struct of_device_id dsi_of_match[] = { 5162 { 5163 .compatible = "auo,b080uan01", 5164 .data = &auo_b080uan01 5165 }, { 5166 .compatible = "boe,tv080wum-nl0", 5167 .data = &boe_tv080wum_nl0 5168 }, { 5169 .compatible = "lg,ld070wx3-sl01", 5170 .data = &lg_ld070wx3_sl01 5171 }, { 5172 .compatible = "lg,lh500wx1-sd03", 5173 .data = &lg_lh500wx1_sd03 5174 }, { 5175 .compatible = "panasonic,vvx10f004b00", 5176 .data = &panasonic_vvx10f004b00 5177 }, { 5178 .compatible = "lg,acx467akm-7", 5179 .data = &lg_acx467akm_7 5180 }, { 5181 .compatible = "osddisplays,osd101t2045-53ts", 5182 .data = &osd101t2045_53ts 5183 }, { 5184 /* sentinel */ 5185 } 5186 }; 5187 MODULE_DEVICE_TABLE(of, dsi_of_match); 5188 5189 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5190 { 5191 const struct panel_desc_dsi *desc; 5192 const struct of_device_id *id; 5193 int err; 5194 5195 id = of_match_node(dsi_of_match, dsi->dev.of_node); 5196 if (!id) 5197 return -ENODEV; 5198 5199 desc = id->data; 5200 5201 err = panel_simple_probe(&dsi->dev, &desc->desc, NULL); 5202 if (err < 0) 5203 return err; 5204 5205 dsi->mode_flags = desc->flags; 5206 dsi->format = desc->format; 5207 dsi->lanes = desc->lanes; 5208 5209 err = mipi_dsi_attach(dsi); 5210 if (err) { 5211 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5212 5213 drm_panel_remove(&panel->base); 5214 } 5215 5216 return err; 5217 } 5218 5219 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5220 { 5221 int err; 5222 5223 err = mipi_dsi_detach(dsi); 5224 if (err < 0) 5225 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5226 5227 return panel_simple_remove(&dsi->dev); 5228 } 5229 5230 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5231 { 5232 panel_simple_shutdown(&dsi->dev); 5233 } 5234 5235 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5236 .driver = { 5237 .name = "panel-simple-dsi", 5238 .of_match_table = dsi_of_match, 5239 .pm = &panel_simple_pm_ops, 5240 }, 5241 .probe = panel_simple_dsi_probe, 5242 .remove = panel_simple_dsi_remove, 5243 .shutdown = panel_simple_dsi_shutdown, 5244 }; 5245 5246 static int panel_simple_dp_aux_ep_probe(struct dp_aux_ep_device *aux_ep) 5247 { 5248 const struct of_device_id *id; 5249 5250 id = of_match_node(platform_of_match, aux_ep->dev.of_node); 5251 if (!id) 5252 return -ENODEV; 5253 5254 return panel_simple_probe(&aux_ep->dev, id->data, aux_ep->aux); 5255 } 5256 5257 static void panel_simple_dp_aux_ep_remove(struct dp_aux_ep_device *aux_ep) 5258 { 5259 panel_simple_remove(&aux_ep->dev); 5260 } 5261 5262 static void panel_simple_dp_aux_ep_shutdown(struct dp_aux_ep_device *aux_ep) 5263 { 5264 panel_simple_shutdown(&aux_ep->dev); 5265 } 5266 5267 static struct dp_aux_ep_driver panel_simple_dp_aux_ep_driver = { 5268 .driver = { 5269 .name = "panel-simple-dp-aux", 5270 .of_match_table = platform_of_match, /* Same as platform one! */ 5271 .pm = &panel_simple_pm_ops, 5272 }, 5273 .probe = panel_simple_dp_aux_ep_probe, 5274 .remove = panel_simple_dp_aux_ep_remove, 5275 .shutdown = panel_simple_dp_aux_ep_shutdown, 5276 }; 5277 5278 static int __init panel_simple_init(void) 5279 { 5280 int err; 5281 5282 err = platform_driver_register(&panel_simple_platform_driver); 5283 if (err < 0) 5284 return err; 5285 5286 err = dp_aux_dp_driver_register(&panel_simple_dp_aux_ep_driver); 5287 if (err < 0) 5288 goto err_did_platform_register; 5289 5290 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5291 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5292 if (err < 0) 5293 goto err_did_aux_ep_register; 5294 } 5295 5296 return 0; 5297 5298 err_did_aux_ep_register: 5299 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver); 5300 5301 err_did_platform_register: 5302 platform_driver_unregister(&panel_simple_platform_driver); 5303 5304 return err; 5305 } 5306 module_init(panel_simple_init); 5307 5308 static void __exit panel_simple_exit(void) 5309 { 5310 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5311 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5312 5313 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver); 5314 platform_driver_unregister(&panel_simple_platform_driver); 5315 } 5316 module_exit(panel_simple_exit); 5317 5318 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5319 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5320 MODULE_LICENSE("GPL and additional rights"); 5321