1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_modes == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 if (p->enable_gpio) 191 gpiod_set_value_cansleep(p->enable_gpio, 0); 192 193 regulator_disable(p->supply); 194 195 if (p->desc->delay.unprepare) 196 msleep(p->desc->delay.unprepare); 197 198 p->prepared = false; 199 200 return 0; 201 } 202 203 static int panel_simple_prepare(struct drm_panel *panel) 204 { 205 struct panel_simple *p = to_panel_simple(panel); 206 int err; 207 208 if (p->prepared) 209 return 0; 210 211 err = regulator_enable(p->supply); 212 if (err < 0) { 213 dev_err(panel->dev, "failed to enable supply: %d\n", err); 214 return err; 215 } 216 217 if (p->enable_gpio) 218 gpiod_set_value_cansleep(p->enable_gpio, 1); 219 220 if (p->desc->delay.prepare) 221 msleep(p->desc->delay.prepare); 222 223 p->prepared = true; 224 225 return 0; 226 } 227 228 static int panel_simple_enable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (p->enabled) 233 return 0; 234 235 if (p->desc->delay.enable) 236 msleep(p->desc->delay.enable); 237 238 if (p->backlight) { 239 p->backlight->props.state &= ~BL_CORE_FBBLANK; 240 p->backlight->props.power = FB_BLANK_UNBLANK; 241 backlight_update_status(p->backlight); 242 } 243 244 p->enabled = true; 245 246 return 0; 247 } 248 249 static int panel_simple_get_modes(struct drm_panel *panel) 250 { 251 struct panel_simple *p = to_panel_simple(panel); 252 int num = 0; 253 254 /* probe EDID if a DDC bus is available */ 255 if (p->ddc) { 256 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 257 drm_mode_connector_update_edid_property(panel->connector, edid); 258 if (edid) { 259 num += drm_add_edid_modes(panel->connector, edid); 260 kfree(edid); 261 } 262 } 263 264 /* add hard-coded panel modes */ 265 num += panel_simple_get_fixed_modes(p); 266 267 return num; 268 } 269 270 static int panel_simple_get_timings(struct drm_panel *panel, 271 unsigned int num_timings, 272 struct display_timing *timings) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int i; 276 277 if (p->desc->num_timings < num_timings) 278 num_timings = p->desc->num_timings; 279 280 if (timings) 281 for (i = 0; i < num_timings; i++) 282 timings[i] = p->desc->timings[i]; 283 284 return p->desc->num_timings; 285 } 286 287 static const struct drm_panel_funcs panel_simple_funcs = { 288 .disable = panel_simple_disable, 289 .unprepare = panel_simple_unprepare, 290 .prepare = panel_simple_prepare, 291 .enable = panel_simple_enable, 292 .get_modes = panel_simple_get_modes, 293 .get_timings = panel_simple_get_timings, 294 }; 295 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 297 { 298 struct device_node *backlight, *ddc; 299 struct panel_simple *panel; 300 int err; 301 302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 303 if (!panel) 304 return -ENOMEM; 305 306 panel->enabled = false; 307 panel->prepared = false; 308 panel->desc = desc; 309 310 panel->supply = devm_regulator_get(dev, "power"); 311 if (IS_ERR(panel->supply)) 312 return PTR_ERR(panel->supply); 313 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 315 GPIOD_OUT_LOW); 316 if (IS_ERR(panel->enable_gpio)) { 317 err = PTR_ERR(panel->enable_gpio); 318 dev_err(dev, "failed to request GPIO: %d\n", err); 319 return err; 320 } 321 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 323 if (backlight) { 324 panel->backlight = of_find_backlight_by_node(backlight); 325 of_node_put(backlight); 326 327 if (!panel->backlight) 328 return -EPROBE_DEFER; 329 } 330 331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 332 if (ddc) { 333 panel->ddc = of_find_i2c_adapter_by_node(ddc); 334 of_node_put(ddc); 335 336 if (!panel->ddc) { 337 err = -EPROBE_DEFER; 338 goto free_backlight; 339 } 340 } 341 342 drm_panel_init(&panel->base); 343 panel->base.dev = dev; 344 panel->base.funcs = &panel_simple_funcs; 345 346 err = drm_panel_add(&panel->base); 347 if (err < 0) 348 goto free_ddc; 349 350 dev_set_drvdata(dev, panel); 351 352 return 0; 353 354 free_ddc: 355 if (panel->ddc) 356 put_device(&panel->ddc->dev); 357 free_backlight: 358 if (panel->backlight) 359 put_device(&panel->backlight->dev); 360 361 return err; 362 } 363 364 static int panel_simple_remove(struct device *dev) 365 { 366 struct panel_simple *panel = dev_get_drvdata(dev); 367 368 drm_panel_detach(&panel->base); 369 drm_panel_remove(&panel->base); 370 371 panel_simple_disable(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 390 .clock = 33333, 391 .hdisplay = 800, 392 .hsync_start = 800 + 0, 393 .hsync_end = 800 + 0 + 255, 394 .htotal = 800 + 0 + 255 + 0, 395 .vdisplay = 480, 396 .vsync_start = 480 + 2, 397 .vsync_end = 480 + 2 + 45, 398 .vtotal = 480 + 2 + 45 + 0, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am800480r3tmqwa1h = { 404 .modes = &ire_am800480r3tmqwa1h_mode, 405 .num_modes = 1, 406 .bpc = 6, 407 .size = { 408 .width = 152, 409 .height = 91, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 412 }; 413 414 static const struct drm_display_mode auo_b101aw03_mode = { 415 .clock = 51450, 416 .hdisplay = 1024, 417 .hsync_start = 1024 + 156, 418 .hsync_end = 1024 + 156 + 8, 419 .htotal = 1024 + 156 + 8 + 156, 420 .vdisplay = 600, 421 .vsync_start = 600 + 16, 422 .vsync_end = 600 + 16 + 6, 423 .vtotal = 600 + 16 + 6 + 16, 424 .vrefresh = 60, 425 }; 426 427 static const struct panel_desc auo_b101aw03 = { 428 .modes = &auo_b101aw03_mode, 429 .num_modes = 1, 430 .bpc = 6, 431 .size = { 432 .width = 223, 433 .height = 125, 434 }, 435 }; 436 437 static const struct drm_display_mode auo_b101ean01_mode = { 438 .clock = 72500, 439 .hdisplay = 1280, 440 .hsync_start = 1280 + 119, 441 .hsync_end = 1280 + 119 + 32, 442 .htotal = 1280 + 119 + 32 + 21, 443 .vdisplay = 800, 444 .vsync_start = 800 + 4, 445 .vsync_end = 800 + 4 + 20, 446 .vtotal = 800 + 4 + 20 + 8, 447 .vrefresh = 60, 448 }; 449 450 static const struct panel_desc auo_b101ean01 = { 451 .modes = &auo_b101ean01_mode, 452 .num_modes = 1, 453 .bpc = 6, 454 .size = { 455 .width = 217, 456 .height = 136, 457 }, 458 }; 459 460 static const struct drm_display_mode auo_b101xtn01_mode = { 461 .clock = 72000, 462 .hdisplay = 1366, 463 .hsync_start = 1366 + 20, 464 .hsync_end = 1366 + 20 + 70, 465 .htotal = 1366 + 20 + 70, 466 .vdisplay = 768, 467 .vsync_start = 768 + 14, 468 .vsync_end = 768 + 14 + 42, 469 .vtotal = 768 + 14 + 42, 470 .vrefresh = 60, 471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 472 }; 473 474 static const struct panel_desc auo_b101xtn01 = { 475 .modes = &auo_b101xtn01_mode, 476 .num_modes = 1, 477 .bpc = 6, 478 .size = { 479 .width = 223, 480 .height = 125, 481 }, 482 }; 483 484 static const struct drm_display_mode auo_b116xw03_mode = { 485 .clock = 70589, 486 .hdisplay = 1366, 487 .hsync_start = 1366 + 40, 488 .hsync_end = 1366 + 40 + 40, 489 .htotal = 1366 + 40 + 40 + 32, 490 .vdisplay = 768, 491 .vsync_start = 768 + 10, 492 .vsync_end = 768 + 10 + 12, 493 .vtotal = 768 + 10 + 12 + 6, 494 .vrefresh = 60, 495 }; 496 497 static const struct panel_desc auo_b116xw03 = { 498 .modes = &auo_b116xw03_mode, 499 .num_modes = 1, 500 .bpc = 6, 501 .size = { 502 .width = 256, 503 .height = 144, 504 }, 505 }; 506 507 static const struct drm_display_mode auo_b133xtn01_mode = { 508 .clock = 69500, 509 .hdisplay = 1366, 510 .hsync_start = 1366 + 48, 511 .hsync_end = 1366 + 48 + 32, 512 .htotal = 1366 + 48 + 32 + 20, 513 .vdisplay = 768, 514 .vsync_start = 768 + 3, 515 .vsync_end = 768 + 3 + 6, 516 .vtotal = 768 + 3 + 6 + 13, 517 .vrefresh = 60, 518 }; 519 520 static const struct panel_desc auo_b133xtn01 = { 521 .modes = &auo_b133xtn01_mode, 522 .num_modes = 1, 523 .bpc = 6, 524 .size = { 525 .width = 293, 526 .height = 165, 527 }, 528 }; 529 530 static const struct drm_display_mode auo_b133htn01_mode = { 531 .clock = 150660, 532 .hdisplay = 1920, 533 .hsync_start = 1920 + 172, 534 .hsync_end = 1920 + 172 + 80, 535 .htotal = 1920 + 172 + 80 + 60, 536 .vdisplay = 1080, 537 .vsync_start = 1080 + 25, 538 .vsync_end = 1080 + 25 + 10, 539 .vtotal = 1080 + 25 + 10 + 10, 540 .vrefresh = 60, 541 }; 542 543 static const struct panel_desc auo_b133htn01 = { 544 .modes = &auo_b133htn01_mode, 545 .num_modes = 1, 546 .bpc = 6, 547 .size = { 548 .width = 293, 549 .height = 165, 550 }, 551 .delay = { 552 .prepare = 105, 553 .enable = 20, 554 .unprepare = 50, 555 }, 556 }; 557 558 static const struct drm_display_mode avic_tm070ddh03_mode = { 559 .clock = 51200, 560 .hdisplay = 1024, 561 .hsync_start = 1024 + 160, 562 .hsync_end = 1024 + 160 + 4, 563 .htotal = 1024 + 160 + 4 + 156, 564 .vdisplay = 600, 565 .vsync_start = 600 + 17, 566 .vsync_end = 600 + 17 + 1, 567 .vtotal = 600 + 17 + 1 + 17, 568 .vrefresh = 60, 569 }; 570 571 static const struct panel_desc avic_tm070ddh03 = { 572 .modes = &avic_tm070ddh03_mode, 573 .num_modes = 1, 574 .bpc = 8, 575 .size = { 576 .width = 154, 577 .height = 90, 578 }, 579 .delay = { 580 .prepare = 20, 581 .enable = 200, 582 .disable = 200, 583 }, 584 }; 585 586 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 587 .clock = 72070, 588 .hdisplay = 1366, 589 .hsync_start = 1366 + 58, 590 .hsync_end = 1366 + 58 + 58, 591 .htotal = 1366 + 58 + 58 + 58, 592 .vdisplay = 768, 593 .vsync_start = 768 + 4, 594 .vsync_end = 768 + 4 + 4, 595 .vtotal = 768 + 4 + 4 + 4, 596 .vrefresh = 60, 597 }; 598 599 static const struct panel_desc chunghwa_claa101wa01a = { 600 .modes = &chunghwa_claa101wa01a_mode, 601 .num_modes = 1, 602 .bpc = 6, 603 .size = { 604 .width = 220, 605 .height = 120, 606 }, 607 }; 608 609 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 610 .clock = 69300, 611 .hdisplay = 1366, 612 .hsync_start = 1366 + 48, 613 .hsync_end = 1366 + 48 + 32, 614 .htotal = 1366 + 48 + 32 + 20, 615 .vdisplay = 768, 616 .vsync_start = 768 + 16, 617 .vsync_end = 768 + 16 + 8, 618 .vtotal = 768 + 16 + 8 + 16, 619 .vrefresh = 60, 620 }; 621 622 static const struct panel_desc chunghwa_claa101wb01 = { 623 .modes = &chunghwa_claa101wb01_mode, 624 .num_modes = 1, 625 .bpc = 6, 626 .size = { 627 .width = 223, 628 .height = 125, 629 }, 630 }; 631 632 static const struct drm_display_mode edt_et057090dhu_mode = { 633 .clock = 25175, 634 .hdisplay = 640, 635 .hsync_start = 640 + 16, 636 .hsync_end = 640 + 16 + 30, 637 .htotal = 640 + 16 + 30 + 114, 638 .vdisplay = 480, 639 .vsync_start = 480 + 10, 640 .vsync_end = 480 + 10 + 3, 641 .vtotal = 480 + 10 + 3 + 32, 642 .vrefresh = 60, 643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 644 }; 645 646 static const struct panel_desc edt_et057090dhu = { 647 .modes = &edt_et057090dhu_mode, 648 .num_modes = 1, 649 .bpc = 6, 650 .size = { 651 .width = 115, 652 .height = 86, 653 }, 654 }; 655 656 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 657 .clock = 33260, 658 .hdisplay = 800, 659 .hsync_start = 800 + 40, 660 .hsync_end = 800 + 40 + 128, 661 .htotal = 800 + 40 + 128 + 88, 662 .vdisplay = 480, 663 .vsync_start = 480 + 10, 664 .vsync_end = 480 + 10 + 2, 665 .vtotal = 480 + 10 + 2 + 33, 666 .vrefresh = 60, 667 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 668 }; 669 670 static const struct panel_desc edt_etm0700g0dh6 = { 671 .modes = &edt_etm0700g0dh6_mode, 672 .num_modes = 1, 673 .bpc = 6, 674 .size = { 675 .width = 152, 676 .height = 91, 677 }, 678 }; 679 680 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 681 .clock = 32260, 682 .hdisplay = 800, 683 .hsync_start = 800 + 168, 684 .hsync_end = 800 + 168 + 64, 685 .htotal = 800 + 168 + 64 + 88, 686 .vdisplay = 480, 687 .vsync_start = 480 + 37, 688 .vsync_end = 480 + 37 + 2, 689 .vtotal = 480 + 37 + 2 + 8, 690 .vrefresh = 60, 691 }; 692 693 static const struct panel_desc foxlink_fl500wvr00_a0t = { 694 .modes = &foxlink_fl500wvr00_a0t_mode, 695 .num_modes = 1, 696 .bpc = 8, 697 .size = { 698 .width = 108, 699 .height = 65, 700 }, 701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 702 }; 703 704 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 705 .clock = 9000, 706 .hdisplay = 480, 707 .hsync_start = 480 + 5, 708 .hsync_end = 480 + 5 + 1, 709 .htotal = 480 + 5 + 1 + 40, 710 .vdisplay = 272, 711 .vsync_start = 272 + 8, 712 .vsync_end = 272 + 8 + 1, 713 .vtotal = 272 + 8 + 1 + 8, 714 .vrefresh = 60, 715 }; 716 717 static const struct panel_desc giantplus_gpg482739qs5 = { 718 .modes = &giantplus_gpg482739qs5_mode, 719 .num_modes = 1, 720 .bpc = 8, 721 .size = { 722 .width = 95, 723 .height = 54, 724 }, 725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 726 }; 727 728 static const struct display_timing hannstar_hsd070pww1_timing = { 729 .pixelclock = { 64300000, 71100000, 82000000 }, 730 .hactive = { 1280, 1280, 1280 }, 731 .hfront_porch = { 1, 1, 10 }, 732 .hback_porch = { 1, 1, 10 }, 733 /* 734 * According to the data sheet, the minimum horizontal blanking interval 735 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 736 * minimum working horizontal blanking interval to be 60 clocks. 737 */ 738 .hsync_len = { 58, 158, 661 }, 739 .vactive = { 800, 800, 800 }, 740 .vfront_porch = { 1, 1, 10 }, 741 .vback_porch = { 1, 1, 10 }, 742 .vsync_len = { 1, 21, 203 }, 743 .flags = DISPLAY_FLAGS_DE_HIGH, 744 }; 745 746 static const struct panel_desc hannstar_hsd070pww1 = { 747 .timings = &hannstar_hsd070pww1_timing, 748 .num_timings = 1, 749 .bpc = 6, 750 .size = { 751 .width = 151, 752 .height = 94, 753 }, 754 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 755 }; 756 757 static const struct display_timing hannstar_hsd100pxn1_timing = { 758 .pixelclock = { 55000000, 65000000, 75000000 }, 759 .hactive = { 1024, 1024, 1024 }, 760 .hfront_porch = { 40, 40, 40 }, 761 .hback_porch = { 220, 220, 220 }, 762 .hsync_len = { 20, 60, 100 }, 763 .vactive = { 768, 768, 768 }, 764 .vfront_porch = { 7, 7, 7 }, 765 .vback_porch = { 21, 21, 21 }, 766 .vsync_len = { 10, 10, 10 }, 767 .flags = DISPLAY_FLAGS_DE_HIGH, 768 }; 769 770 static const struct panel_desc hannstar_hsd100pxn1 = { 771 .timings = &hannstar_hsd100pxn1_timing, 772 .num_timings = 1, 773 .bpc = 6, 774 .size = { 775 .width = 203, 776 .height = 152, 777 }, 778 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 779 }; 780 781 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 782 .clock = 33333, 783 .hdisplay = 800, 784 .hsync_start = 800 + 85, 785 .hsync_end = 800 + 85 + 86, 786 .htotal = 800 + 85 + 86 + 85, 787 .vdisplay = 480, 788 .vsync_start = 480 + 16, 789 .vsync_end = 480 + 16 + 13, 790 .vtotal = 480 + 16 + 13 + 16, 791 .vrefresh = 60, 792 }; 793 794 static const struct panel_desc hitachi_tx23d38vm0caa = { 795 .modes = &hitachi_tx23d38vm0caa_mode, 796 .num_modes = 1, 797 .bpc = 6, 798 .size = { 799 .width = 195, 800 .height = 117, 801 }, 802 }; 803 804 static const struct drm_display_mode innolux_at043tn24_mode = { 805 .clock = 9000, 806 .hdisplay = 480, 807 .hsync_start = 480 + 2, 808 .hsync_end = 480 + 2 + 41, 809 .htotal = 480 + 2 + 41 + 2, 810 .vdisplay = 272, 811 .vsync_start = 272 + 2, 812 .vsync_end = 272 + 2 + 11, 813 .vtotal = 272 + 2 + 11 + 2, 814 .vrefresh = 60, 815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 816 }; 817 818 static const struct panel_desc innolux_at043tn24 = { 819 .modes = &innolux_at043tn24_mode, 820 .num_modes = 1, 821 .bpc = 8, 822 .size = { 823 .width = 95, 824 .height = 54, 825 }, 826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 827 }; 828 829 static const struct drm_display_mode innolux_at070tn92_mode = { 830 .clock = 33333, 831 .hdisplay = 800, 832 .hsync_start = 800 + 210, 833 .hsync_end = 800 + 210 + 20, 834 .htotal = 800 + 210 + 20 + 46, 835 .vdisplay = 480, 836 .vsync_start = 480 + 22, 837 .vsync_end = 480 + 22 + 10, 838 .vtotal = 480 + 22 + 23 + 10, 839 .vrefresh = 60, 840 }; 841 842 static const struct panel_desc innolux_at070tn92 = { 843 .modes = &innolux_at070tn92_mode, 844 .num_modes = 1, 845 .size = { 846 .width = 154, 847 .height = 86, 848 }, 849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 850 }; 851 852 static const struct display_timing innolux_g101ice_l01_timing = { 853 .pixelclock = { 60400000, 71100000, 74700000 }, 854 .hactive = { 1280, 1280, 1280 }, 855 .hfront_porch = { 41, 80, 100 }, 856 .hback_porch = { 40, 79, 99 }, 857 .hsync_len = { 1, 1, 1 }, 858 .vactive = { 800, 800, 800 }, 859 .vfront_porch = { 5, 11, 14 }, 860 .vback_porch = { 4, 11, 14 }, 861 .vsync_len = { 1, 1, 1 }, 862 .flags = DISPLAY_FLAGS_DE_HIGH, 863 }; 864 865 static const struct panel_desc innolux_g101ice_l01 = { 866 .timings = &innolux_g101ice_l01_timing, 867 .num_timings = 1, 868 .bpc = 8, 869 .size = { 870 .width = 217, 871 .height = 135, 872 }, 873 .delay = { 874 .enable = 200, 875 .disable = 200, 876 }, 877 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 878 }; 879 880 static const struct drm_display_mode innolux_g121i1_l01_mode = { 881 .clock = 71000, 882 .hdisplay = 1280, 883 .hsync_start = 1280 + 64, 884 .hsync_end = 1280 + 64 + 32, 885 .htotal = 1280 + 64 + 32 + 64, 886 .vdisplay = 800, 887 .vsync_start = 800 + 9, 888 .vsync_end = 800 + 9 + 6, 889 .vtotal = 800 + 9 + 6 + 9, 890 .vrefresh = 60, 891 }; 892 893 static const struct panel_desc innolux_g121i1_l01 = { 894 .modes = &innolux_g121i1_l01_mode, 895 .num_modes = 1, 896 .bpc = 6, 897 .size = { 898 .width = 261, 899 .height = 163, 900 }, 901 }; 902 903 static const struct drm_display_mode innolux_g121x1_l03_mode = { 904 .clock = 65000, 905 .hdisplay = 1024, 906 .hsync_start = 1024 + 0, 907 .hsync_end = 1024 + 1, 908 .htotal = 1024 + 0 + 1 + 320, 909 .vdisplay = 768, 910 .vsync_start = 768 + 38, 911 .vsync_end = 768 + 38 + 1, 912 .vtotal = 768 + 38 + 1 + 0, 913 .vrefresh = 60, 914 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 915 }; 916 917 static const struct panel_desc innolux_g121x1_l03 = { 918 .modes = &innolux_g121x1_l03_mode, 919 .num_modes = 1, 920 .bpc = 6, 921 .size = { 922 .width = 246, 923 .height = 185, 924 }, 925 .delay = { 926 .enable = 200, 927 .unprepare = 200, 928 .disable = 400, 929 }, 930 }; 931 932 static const struct drm_display_mode innolux_n116bge_mode = { 933 .clock = 76420, 934 .hdisplay = 1366, 935 .hsync_start = 1366 + 136, 936 .hsync_end = 1366 + 136 + 30, 937 .htotal = 1366 + 136 + 30 + 60, 938 .vdisplay = 768, 939 .vsync_start = 768 + 8, 940 .vsync_end = 768 + 8 + 12, 941 .vtotal = 768 + 8 + 12 + 12, 942 .vrefresh = 60, 943 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 944 }; 945 946 static const struct panel_desc innolux_n116bge = { 947 .modes = &innolux_n116bge_mode, 948 .num_modes = 1, 949 .bpc = 6, 950 .size = { 951 .width = 256, 952 .height = 144, 953 }, 954 }; 955 956 static const struct drm_display_mode innolux_n156bge_l21_mode = { 957 .clock = 69300, 958 .hdisplay = 1366, 959 .hsync_start = 1366 + 16, 960 .hsync_end = 1366 + 16 + 34, 961 .htotal = 1366 + 16 + 34 + 50, 962 .vdisplay = 768, 963 .vsync_start = 768 + 2, 964 .vsync_end = 768 + 2 + 6, 965 .vtotal = 768 + 2 + 6 + 12, 966 .vrefresh = 60, 967 }; 968 969 static const struct panel_desc innolux_n156bge_l21 = { 970 .modes = &innolux_n156bge_l21_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 344, 975 .height = 193, 976 }, 977 }; 978 979 static const struct drm_display_mode innolux_zj070na_01p_mode = { 980 .clock = 51501, 981 .hdisplay = 1024, 982 .hsync_start = 1024 + 128, 983 .hsync_end = 1024 + 128 + 64, 984 .htotal = 1024 + 128 + 64 + 128, 985 .vdisplay = 600, 986 .vsync_start = 600 + 16, 987 .vsync_end = 600 + 16 + 4, 988 .vtotal = 600 + 16 + 4 + 16, 989 .vrefresh = 60, 990 }; 991 992 static const struct panel_desc innolux_zj070na_01p = { 993 .modes = &innolux_zj070na_01p_mode, 994 .num_modes = 1, 995 .bpc = 6, 996 .size = { 997 .width = 154, 998 .height = 90, 999 }, 1000 }; 1001 1002 static const struct display_timing kyo_tcg121xglp_timing = { 1003 .pixelclock = { 52000000, 65000000, 71000000 }, 1004 .hactive = { 1024, 1024, 1024 }, 1005 .hfront_porch = { 2, 2, 2 }, 1006 .hback_porch = { 2, 2, 2 }, 1007 .hsync_len = { 86, 124, 244 }, 1008 .vactive = { 768, 768, 768 }, 1009 .vfront_porch = { 2, 2, 2 }, 1010 .vback_porch = { 2, 2, 2 }, 1011 .vsync_len = { 6, 34, 73 }, 1012 .flags = DISPLAY_FLAGS_DE_HIGH, 1013 }; 1014 1015 static const struct panel_desc kyo_tcg121xglp = { 1016 .timings = &kyo_tcg121xglp_timing, 1017 .num_timings = 1, 1018 .bpc = 8, 1019 .size = { 1020 .width = 246, 1021 .height = 184, 1022 }, 1023 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1024 }; 1025 1026 static const struct drm_display_mode lg_lb070wv8_mode = { 1027 .clock = 33246, 1028 .hdisplay = 800, 1029 .hsync_start = 800 + 88, 1030 .hsync_end = 800 + 88 + 80, 1031 .htotal = 800 + 88 + 80 + 88, 1032 .vdisplay = 480, 1033 .vsync_start = 480 + 10, 1034 .vsync_end = 480 + 10 + 25, 1035 .vtotal = 480 + 10 + 25 + 10, 1036 .vrefresh = 60, 1037 }; 1038 1039 static const struct panel_desc lg_lb070wv8 = { 1040 .modes = &lg_lb070wv8_mode, 1041 .num_modes = 1, 1042 .bpc = 16, 1043 .size = { 1044 .width = 151, 1045 .height = 91, 1046 }, 1047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1048 }; 1049 1050 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1051 .clock = 200000, 1052 .hdisplay = 1536, 1053 .hsync_start = 1536 + 12, 1054 .hsync_end = 1536 + 12 + 16, 1055 .htotal = 1536 + 12 + 16 + 48, 1056 .vdisplay = 2048, 1057 .vsync_start = 2048 + 8, 1058 .vsync_end = 2048 + 8 + 4, 1059 .vtotal = 2048 + 8 + 4 + 8, 1060 .vrefresh = 60, 1061 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1062 }; 1063 1064 static const struct panel_desc lg_lp079qx1_sp0v = { 1065 .modes = &lg_lp079qx1_sp0v_mode, 1066 .num_modes = 1, 1067 .size = { 1068 .width = 129, 1069 .height = 171, 1070 }, 1071 }; 1072 1073 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1074 .clock = 205210, 1075 .hdisplay = 2048, 1076 .hsync_start = 2048 + 150, 1077 .hsync_end = 2048 + 150 + 5, 1078 .htotal = 2048 + 150 + 5 + 5, 1079 .vdisplay = 1536, 1080 .vsync_start = 1536 + 3, 1081 .vsync_end = 1536 + 3 + 1, 1082 .vtotal = 1536 + 3 + 1 + 9, 1083 .vrefresh = 60, 1084 }; 1085 1086 static const struct panel_desc lg_lp097qx1_spa1 = { 1087 .modes = &lg_lp097qx1_spa1_mode, 1088 .num_modes = 1, 1089 .size = { 1090 .width = 208, 1091 .height = 147, 1092 }, 1093 }; 1094 1095 static const struct drm_display_mode lg_lp120up1_mode = { 1096 .clock = 162300, 1097 .hdisplay = 1920, 1098 .hsync_start = 1920 + 40, 1099 .hsync_end = 1920 + 40 + 40, 1100 .htotal = 1920 + 40 + 40+ 80, 1101 .vdisplay = 1280, 1102 .vsync_start = 1280 + 4, 1103 .vsync_end = 1280 + 4 + 4, 1104 .vtotal = 1280 + 4 + 4 + 12, 1105 .vrefresh = 60, 1106 }; 1107 1108 static const struct panel_desc lg_lp120up1 = { 1109 .modes = &lg_lp120up1_mode, 1110 .num_modes = 1, 1111 .bpc = 8, 1112 .size = { 1113 .width = 267, 1114 .height = 183, 1115 }, 1116 }; 1117 1118 static const struct drm_display_mode lg_lp129qe_mode = { 1119 .clock = 285250, 1120 .hdisplay = 2560, 1121 .hsync_start = 2560 + 48, 1122 .hsync_end = 2560 + 48 + 32, 1123 .htotal = 2560 + 48 + 32 + 80, 1124 .vdisplay = 1700, 1125 .vsync_start = 1700 + 3, 1126 .vsync_end = 1700 + 3 + 10, 1127 .vtotal = 1700 + 3 + 10 + 36, 1128 .vrefresh = 60, 1129 }; 1130 1131 static const struct panel_desc lg_lp129qe = { 1132 .modes = &lg_lp129qe_mode, 1133 .num_modes = 1, 1134 .bpc = 8, 1135 .size = { 1136 .width = 272, 1137 .height = 181, 1138 }, 1139 }; 1140 1141 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1142 .clock = 10870, 1143 .hdisplay = 480, 1144 .hsync_start = 480 + 2, 1145 .hsync_end = 480 + 2 + 41, 1146 .htotal = 480 + 2 + 41 + 2, 1147 .vdisplay = 272, 1148 .vsync_start = 272 + 2, 1149 .vsync_end = 272 + 2 + 4, 1150 .vtotal = 272 + 2 + 4 + 2, 1151 .vrefresh = 74, 1152 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1153 }; 1154 1155 static const struct panel_desc nec_nl4827hc19_05b = { 1156 .modes = &nec_nl4827hc19_05b_mode, 1157 .num_modes = 1, 1158 .bpc = 8, 1159 .size = { 1160 .width = 95, 1161 .height = 54, 1162 }, 1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1164 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1165 }; 1166 1167 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1168 .pixelclock = { 30000000, 30000000, 40000000 }, 1169 .hactive = { 800, 800, 800 }, 1170 .hfront_porch = { 40, 40, 40 }, 1171 .hback_porch = { 40, 40, 40 }, 1172 .hsync_len = { 1, 48, 48 }, 1173 .vactive = { 480, 480, 480 }, 1174 .vfront_porch = { 13, 13, 13 }, 1175 .vback_porch = { 29, 29, 29 }, 1176 .vsync_len = { 3, 3, 3 }, 1177 .flags = DISPLAY_FLAGS_DE_HIGH, 1178 }; 1179 1180 static const struct panel_desc okaya_rs800480t_7x0gp = { 1181 .timings = &okaya_rs800480t_7x0gp_timing, 1182 .num_timings = 1, 1183 .bpc = 6, 1184 .size = { 1185 .width = 154, 1186 .height = 87, 1187 }, 1188 .delay = { 1189 .prepare = 41, 1190 .enable = 50, 1191 .unprepare = 41, 1192 .disable = 50, 1193 }, 1194 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1195 }; 1196 1197 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1198 .clock = 9000, 1199 .hdisplay = 480, 1200 .hsync_start = 480 + 5, 1201 .hsync_end = 480 + 5 + 30, 1202 .htotal = 480 + 5 + 30 + 10, 1203 .vdisplay = 272, 1204 .vsync_start = 272 + 8, 1205 .vsync_end = 272 + 8 + 5, 1206 .vtotal = 272 + 8 + 5 + 3, 1207 .vrefresh = 60, 1208 }; 1209 1210 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1211 .modes = &olimex_lcd_olinuxino_43ts_mode, 1212 .num_modes = 1, 1213 .size = { 1214 .width = 105, 1215 .height = 67, 1216 }, 1217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1218 }; 1219 1220 /* 1221 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1222 * pixel clocks, but this is the timing that was being used in the Adafruit 1223 * installation instructions. 1224 */ 1225 static const struct drm_display_mode ontat_yx700wv03_mode = { 1226 .clock = 29500, 1227 .hdisplay = 800, 1228 .hsync_start = 824, 1229 .hsync_end = 896, 1230 .htotal = 992, 1231 .vdisplay = 480, 1232 .vsync_start = 483, 1233 .vsync_end = 493, 1234 .vtotal = 500, 1235 .vrefresh = 60, 1236 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1237 }; 1238 1239 /* 1240 * Specification at: 1241 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1242 */ 1243 static const struct panel_desc ontat_yx700wv03 = { 1244 .modes = &ontat_yx700wv03_mode, 1245 .num_modes = 1, 1246 .bpc = 8, 1247 .size = { 1248 .width = 154, 1249 .height = 83, 1250 }, 1251 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1252 }; 1253 1254 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1255 .clock = 25000, 1256 .hdisplay = 480, 1257 .hsync_start = 480 + 10, 1258 .hsync_end = 480 + 10 + 10, 1259 .htotal = 480 + 10 + 10 + 15, 1260 .vdisplay = 800, 1261 .vsync_start = 800 + 3, 1262 .vsync_end = 800 + 3 + 3, 1263 .vtotal = 800 + 3 + 3 + 3, 1264 .vrefresh = 60, 1265 }; 1266 1267 static const struct panel_desc ortustech_com43h4m85ulc = { 1268 .modes = &ortustech_com43h4m85ulc_mode, 1269 .num_modes = 1, 1270 .bpc = 8, 1271 .size = { 1272 .width = 56, 1273 .height = 93, 1274 }, 1275 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1276 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1277 }; 1278 1279 static const struct drm_display_mode qd43003c0_40_mode = { 1280 .clock = 9000, 1281 .hdisplay = 480, 1282 .hsync_start = 480 + 8, 1283 .hsync_end = 480 + 8 + 4, 1284 .htotal = 480 + 8 + 4 + 39, 1285 .vdisplay = 272, 1286 .vsync_start = 272 + 4, 1287 .vsync_end = 272 + 4 + 10, 1288 .vtotal = 272 + 4 + 10 + 2, 1289 .vrefresh = 60, 1290 }; 1291 1292 static const struct panel_desc qd43003c0_40 = { 1293 .modes = &qd43003c0_40_mode, 1294 .num_modes = 1, 1295 .bpc = 8, 1296 .size = { 1297 .width = 95, 1298 .height = 53, 1299 }, 1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1301 }; 1302 1303 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1304 .clock = 271560, 1305 .hdisplay = 2560, 1306 .hsync_start = 2560 + 48, 1307 .hsync_end = 2560 + 48 + 32, 1308 .htotal = 2560 + 48 + 32 + 80, 1309 .vdisplay = 1600, 1310 .vsync_start = 1600 + 2, 1311 .vsync_end = 1600 + 2 + 5, 1312 .vtotal = 1600 + 2 + 5 + 57, 1313 .vrefresh = 60, 1314 }; 1315 1316 static const struct panel_desc samsung_lsn122dl01_c01 = { 1317 .modes = &samsung_lsn122dl01_c01_mode, 1318 .num_modes = 1, 1319 .size = { 1320 .width = 263, 1321 .height = 164, 1322 }, 1323 }; 1324 1325 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1326 .clock = 54030, 1327 .hdisplay = 1024, 1328 .hsync_start = 1024 + 24, 1329 .hsync_end = 1024 + 24 + 136, 1330 .htotal = 1024 + 24 + 136 + 160, 1331 .vdisplay = 600, 1332 .vsync_start = 600 + 3, 1333 .vsync_end = 600 + 3 + 6, 1334 .vtotal = 600 + 3 + 6 + 61, 1335 .vrefresh = 60, 1336 }; 1337 1338 static const struct panel_desc samsung_ltn101nt05 = { 1339 .modes = &samsung_ltn101nt05_mode, 1340 .num_modes = 1, 1341 .bpc = 6, 1342 .size = { 1343 .width = 223, 1344 .height = 125, 1345 }, 1346 }; 1347 1348 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1349 .clock = 76300, 1350 .hdisplay = 1366, 1351 .hsync_start = 1366 + 64, 1352 .hsync_end = 1366 + 64 + 48, 1353 .htotal = 1366 + 64 + 48 + 128, 1354 .vdisplay = 768, 1355 .vsync_start = 768 + 2, 1356 .vsync_end = 768 + 2 + 5, 1357 .vtotal = 768 + 2 + 5 + 17, 1358 .vrefresh = 60, 1359 }; 1360 1361 static const struct panel_desc samsung_ltn140at29_301 = { 1362 .modes = &samsung_ltn140at29_301_mode, 1363 .num_modes = 1, 1364 .bpc = 6, 1365 .size = { 1366 .width = 320, 1367 .height = 187, 1368 }, 1369 }; 1370 1371 static const struct display_timing sharp_lq101k1ly04_timing = { 1372 .pixelclock = { 60000000, 65000000, 80000000 }, 1373 .hactive = { 1280, 1280, 1280 }, 1374 .hfront_porch = { 20, 20, 20 }, 1375 .hback_porch = { 20, 20, 20 }, 1376 .hsync_len = { 10, 10, 10 }, 1377 .vactive = { 800, 800, 800 }, 1378 .vfront_porch = { 4, 4, 4 }, 1379 .vback_porch = { 4, 4, 4 }, 1380 .vsync_len = { 4, 4, 4 }, 1381 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1382 }; 1383 1384 static const struct panel_desc sharp_lq101k1ly04 = { 1385 .timings = &sharp_lq101k1ly04_timing, 1386 .num_timings = 1, 1387 .bpc = 8, 1388 .size = { 1389 .width = 217, 1390 .height = 136, 1391 }, 1392 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1393 }; 1394 1395 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1396 .clock = 252750, 1397 .hdisplay = 2400, 1398 .hsync_start = 2400 + 48, 1399 .hsync_end = 2400 + 48 + 32, 1400 .htotal = 2400 + 48 + 32 + 80, 1401 .vdisplay = 1600, 1402 .vsync_start = 1600 + 3, 1403 .vsync_end = 1600 + 3 + 10, 1404 .vtotal = 1600 + 3 + 10 + 33, 1405 .vrefresh = 60, 1406 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1407 }; 1408 1409 static const struct panel_desc sharp_lq123p1jx31 = { 1410 .modes = &sharp_lq123p1jx31_mode, 1411 .num_modes = 1, 1412 .size = { 1413 .width = 259, 1414 .height = 173, 1415 }, 1416 .delay = { 1417 .prepare = 110, 1418 .enable = 50, 1419 .unprepare = 550, 1420 }, 1421 }; 1422 1423 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1424 .clock = 33300, 1425 .hdisplay = 800, 1426 .hsync_start = 800 + 1, 1427 .hsync_end = 800 + 1 + 64, 1428 .htotal = 800 + 1 + 64 + 64, 1429 .vdisplay = 480, 1430 .vsync_start = 480 + 1, 1431 .vsync_end = 480 + 1 + 23, 1432 .vtotal = 480 + 1 + 23 + 22, 1433 .vrefresh = 60, 1434 }; 1435 1436 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1437 .modes = &shelly_sca07010_bfn_lnn_mode, 1438 .num_modes = 1, 1439 .size = { 1440 .width = 152, 1441 .height = 91, 1442 }, 1443 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1444 }; 1445 1446 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1447 .clock = 147000, 1448 .hdisplay = 1920, 1449 .hsync_start = 1920 + 16, 1450 .hsync_end = 1920 + 16 + 16, 1451 .htotal = 1920 + 16 + 16 + 32, 1452 .vdisplay = 1200, 1453 .vsync_start = 1200 + 15, 1454 .vsync_end = 1200 + 15 + 2, 1455 .vtotal = 1200 + 15 + 2 + 18, 1456 .vrefresh = 60, 1457 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1458 }; 1459 1460 static const struct panel_desc starry_kr122ea0sra = { 1461 .modes = &starry_kr122ea0sra_mode, 1462 .num_modes = 1, 1463 .size = { 1464 .width = 263, 1465 .height = 164, 1466 }, 1467 .delay = { 1468 .prepare = 10 + 200, 1469 .enable = 50, 1470 .unprepare = 10 + 500, 1471 }, 1472 }; 1473 1474 static const struct drm_display_mode tpk_f07a_0102_mode = { 1475 .clock = 33260, 1476 .hdisplay = 800, 1477 .hsync_start = 800 + 40, 1478 .hsync_end = 800 + 40 + 128, 1479 .htotal = 800 + 40 + 128 + 88, 1480 .vdisplay = 480, 1481 .vsync_start = 480 + 10, 1482 .vsync_end = 480 + 10 + 2, 1483 .vtotal = 480 + 10 + 2 + 33, 1484 .vrefresh = 60, 1485 }; 1486 1487 static const struct panel_desc tpk_f07a_0102 = { 1488 .modes = &tpk_f07a_0102_mode, 1489 .num_modes = 1, 1490 .size = { 1491 .width = 152, 1492 .height = 91, 1493 }, 1494 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1495 }; 1496 1497 static const struct drm_display_mode tpk_f10a_0102_mode = { 1498 .clock = 45000, 1499 .hdisplay = 1024, 1500 .hsync_start = 1024 + 176, 1501 .hsync_end = 1024 + 176 + 5, 1502 .htotal = 1024 + 176 + 5 + 88, 1503 .vdisplay = 600, 1504 .vsync_start = 600 + 20, 1505 .vsync_end = 600 + 20 + 5, 1506 .vtotal = 600 + 20 + 5 + 25, 1507 .vrefresh = 60, 1508 }; 1509 1510 static const struct panel_desc tpk_f10a_0102 = { 1511 .modes = &tpk_f10a_0102_mode, 1512 .num_modes = 1, 1513 .size = { 1514 .width = 223, 1515 .height = 125, 1516 }, 1517 }; 1518 1519 static const struct display_timing urt_umsh_8596md_timing = { 1520 .pixelclock = { 33260000, 33260000, 33260000 }, 1521 .hactive = { 800, 800, 800 }, 1522 .hfront_porch = { 41, 41, 41 }, 1523 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1524 .hsync_len = { 71, 128, 128 }, 1525 .vactive = { 480, 480, 480 }, 1526 .vfront_porch = { 10, 10, 10 }, 1527 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1528 .vsync_len = { 2, 2, 2 }, 1529 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1530 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1531 }; 1532 1533 static const struct panel_desc urt_umsh_8596md_lvds = { 1534 .timings = &urt_umsh_8596md_timing, 1535 .num_timings = 1, 1536 .bpc = 6, 1537 .size = { 1538 .width = 152, 1539 .height = 91, 1540 }, 1541 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1542 }; 1543 1544 static const struct panel_desc urt_umsh_8596md_parallel = { 1545 .timings = &urt_umsh_8596md_timing, 1546 .num_timings = 1, 1547 .bpc = 6, 1548 .size = { 1549 .width = 152, 1550 .height = 91, 1551 }, 1552 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1553 }; 1554 1555 static const struct of_device_id platform_of_match[] = { 1556 { 1557 .compatible = "ampire,am800480r3tmqwa1h", 1558 .data = &ire_am800480r3tmqwa1h, 1559 }, { 1560 .compatible = "auo,b101aw03", 1561 .data = &auo_b101aw03, 1562 }, { 1563 .compatible = "auo,b101ean01", 1564 .data = &auo_b101ean01, 1565 }, { 1566 .compatible = "auo,b101xtn01", 1567 .data = &auo_b101xtn01, 1568 }, { 1569 .compatible = "auo,b116xw03", 1570 .data = &auo_b116xw03, 1571 }, { 1572 .compatible = "auo,b133htn01", 1573 .data = &auo_b133htn01, 1574 }, { 1575 .compatible = "auo,b133xtn01", 1576 .data = &auo_b133xtn01, 1577 }, { 1578 .compatible = "avic,tm070ddh03", 1579 .data = &avic_tm070ddh03, 1580 }, { 1581 .compatible = "chunghwa,claa101wa01a", 1582 .data = &chunghwa_claa101wa01a 1583 }, { 1584 .compatible = "chunghwa,claa101wb01", 1585 .data = &chunghwa_claa101wb01 1586 }, { 1587 .compatible = "edt,et057090dhu", 1588 .data = &edt_et057090dhu, 1589 }, { 1590 .compatible = "edt,et070080dh6", 1591 .data = &edt_etm0700g0dh6, 1592 }, { 1593 .compatible = "edt,etm0700g0dh6", 1594 .data = &edt_etm0700g0dh6, 1595 }, { 1596 .compatible = "foxlink,fl500wvr00-a0t", 1597 .data = &foxlink_fl500wvr00_a0t, 1598 }, { 1599 .compatible = "giantplus,gpg482739qs5", 1600 .data = &giantplus_gpg482739qs5 1601 }, { 1602 .compatible = "hannstar,hsd070pww1", 1603 .data = &hannstar_hsd070pww1, 1604 }, { 1605 .compatible = "hannstar,hsd100pxn1", 1606 .data = &hannstar_hsd100pxn1, 1607 }, { 1608 .compatible = "hit,tx23d38vm0caa", 1609 .data = &hitachi_tx23d38vm0caa 1610 }, { 1611 .compatible = "innolux,at043tn24", 1612 .data = &innolux_at043tn24, 1613 }, { 1614 .compatible = "innolux,at070tn92", 1615 .data = &innolux_at070tn92, 1616 }, { 1617 .compatible ="innolux,g101ice-l01", 1618 .data = &innolux_g101ice_l01 1619 }, { 1620 .compatible ="innolux,g121i1-l01", 1621 .data = &innolux_g121i1_l01 1622 }, { 1623 .compatible = "innolux,g121x1-l03", 1624 .data = &innolux_g121x1_l03, 1625 }, { 1626 .compatible = "innolux,n116bge", 1627 .data = &innolux_n116bge, 1628 }, { 1629 .compatible = "innolux,n156bge-l21", 1630 .data = &innolux_n156bge_l21, 1631 }, { 1632 .compatible = "innolux,zj070na-01p", 1633 .data = &innolux_zj070na_01p, 1634 }, { 1635 .compatible = "kyo,tcg121xglp", 1636 .data = &kyo_tcg121xglp, 1637 }, { 1638 .compatible = "lg,lb070wv8", 1639 .data = &lg_lb070wv8, 1640 }, { 1641 .compatible = "lg,lp079qx1-sp0v", 1642 .data = &lg_lp079qx1_sp0v, 1643 }, { 1644 .compatible = "lg,lp097qx1-spa1", 1645 .data = &lg_lp097qx1_spa1, 1646 }, { 1647 .compatible = "lg,lp120up1", 1648 .data = &lg_lp120up1, 1649 }, { 1650 .compatible = "lg,lp129qe", 1651 .data = &lg_lp129qe, 1652 }, { 1653 .compatible = "nec,nl4827hc19-05b", 1654 .data = &nec_nl4827hc19_05b, 1655 }, { 1656 .compatible = "okaya,rs800480t-7x0gp", 1657 .data = &okaya_rs800480t_7x0gp, 1658 }, { 1659 .compatible = "olimex,lcd-olinuxino-43-ts", 1660 .data = &olimex_lcd_olinuxino_43ts, 1661 }, { 1662 .compatible = "ontat,yx700wv03", 1663 .data = &ontat_yx700wv03, 1664 }, { 1665 .compatible = "ortustech,com43h4m85ulc", 1666 .data = &ortustech_com43h4m85ulc, 1667 }, { 1668 .compatible = "qiaodian,qd43003c0-40", 1669 .data = &qd43003c0_40, 1670 }, { 1671 .compatible = "samsung,lsn122dl01-c01", 1672 .data = &samsung_lsn122dl01_c01, 1673 }, { 1674 .compatible = "samsung,ltn101nt05", 1675 .data = &samsung_ltn101nt05, 1676 }, { 1677 .compatible = "samsung,ltn140at29-301", 1678 .data = &samsung_ltn140at29_301, 1679 }, { 1680 .compatible = "sharp,lq101k1ly04", 1681 .data = &sharp_lq101k1ly04, 1682 }, { 1683 .compatible = "sharp,lq123p1jx31", 1684 .data = &sharp_lq123p1jx31, 1685 }, { 1686 .compatible = "shelly,sca07010-bfn-lnn", 1687 .data = &shelly_sca07010_bfn_lnn, 1688 }, { 1689 .compatible = "starry,kr122ea0sra", 1690 .data = &starry_kr122ea0sra, 1691 }, { 1692 .compatible = "tpk,f07a-0102", 1693 .data = &tpk_f07a_0102, 1694 }, { 1695 .compatible = "tpk,f10a-0102", 1696 .data = &tpk_f10a_0102, 1697 }, { 1698 .compatible = "urt,umsh-8596md-t", 1699 .data = &urt_umsh_8596md_parallel, 1700 }, { 1701 .compatible = "urt,umsh-8596md-1t", 1702 .data = &urt_umsh_8596md_parallel, 1703 }, { 1704 .compatible = "urt,umsh-8596md-7t", 1705 .data = &urt_umsh_8596md_parallel, 1706 }, { 1707 .compatible = "urt,umsh-8596md-11t", 1708 .data = &urt_umsh_8596md_lvds, 1709 }, { 1710 .compatible = "urt,umsh-8596md-19t", 1711 .data = &urt_umsh_8596md_lvds, 1712 }, { 1713 .compatible = "urt,umsh-8596md-20t", 1714 .data = &urt_umsh_8596md_parallel, 1715 }, { 1716 /* sentinel */ 1717 } 1718 }; 1719 MODULE_DEVICE_TABLE(of, platform_of_match); 1720 1721 static int panel_simple_platform_probe(struct platform_device *pdev) 1722 { 1723 const struct of_device_id *id; 1724 1725 id = of_match_node(platform_of_match, pdev->dev.of_node); 1726 if (!id) 1727 return -ENODEV; 1728 1729 return panel_simple_probe(&pdev->dev, id->data); 1730 } 1731 1732 static int panel_simple_platform_remove(struct platform_device *pdev) 1733 { 1734 return panel_simple_remove(&pdev->dev); 1735 } 1736 1737 static void panel_simple_platform_shutdown(struct platform_device *pdev) 1738 { 1739 panel_simple_shutdown(&pdev->dev); 1740 } 1741 1742 static struct platform_driver panel_simple_platform_driver = { 1743 .driver = { 1744 .name = "panel-simple", 1745 .of_match_table = platform_of_match, 1746 }, 1747 .probe = panel_simple_platform_probe, 1748 .remove = panel_simple_platform_remove, 1749 .shutdown = panel_simple_platform_shutdown, 1750 }; 1751 1752 struct panel_desc_dsi { 1753 struct panel_desc desc; 1754 1755 unsigned long flags; 1756 enum mipi_dsi_pixel_format format; 1757 unsigned int lanes; 1758 }; 1759 1760 static const struct drm_display_mode auo_b080uan01_mode = { 1761 .clock = 154500, 1762 .hdisplay = 1200, 1763 .hsync_start = 1200 + 62, 1764 .hsync_end = 1200 + 62 + 4, 1765 .htotal = 1200 + 62 + 4 + 62, 1766 .vdisplay = 1920, 1767 .vsync_start = 1920 + 9, 1768 .vsync_end = 1920 + 9 + 2, 1769 .vtotal = 1920 + 9 + 2 + 8, 1770 .vrefresh = 60, 1771 }; 1772 1773 static const struct panel_desc_dsi auo_b080uan01 = { 1774 .desc = { 1775 .modes = &auo_b080uan01_mode, 1776 .num_modes = 1, 1777 .bpc = 8, 1778 .size = { 1779 .width = 108, 1780 .height = 272, 1781 }, 1782 }, 1783 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 1784 .format = MIPI_DSI_FMT_RGB888, 1785 .lanes = 4, 1786 }; 1787 1788 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 1789 .clock = 160000, 1790 .hdisplay = 1200, 1791 .hsync_start = 1200 + 120, 1792 .hsync_end = 1200 + 120 + 20, 1793 .htotal = 1200 + 120 + 20 + 21, 1794 .vdisplay = 1920, 1795 .vsync_start = 1920 + 21, 1796 .vsync_end = 1920 + 21 + 3, 1797 .vtotal = 1920 + 21 + 3 + 18, 1798 .vrefresh = 60, 1799 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1800 }; 1801 1802 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 1803 .desc = { 1804 .modes = &boe_tv080wum_nl0_mode, 1805 .num_modes = 1, 1806 .size = { 1807 .width = 107, 1808 .height = 172, 1809 }, 1810 }, 1811 .flags = MIPI_DSI_MODE_VIDEO | 1812 MIPI_DSI_MODE_VIDEO_BURST | 1813 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 1814 .format = MIPI_DSI_FMT_RGB888, 1815 .lanes = 4, 1816 }; 1817 1818 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 1819 .clock = 71000, 1820 .hdisplay = 800, 1821 .hsync_start = 800 + 32, 1822 .hsync_end = 800 + 32 + 1, 1823 .htotal = 800 + 32 + 1 + 57, 1824 .vdisplay = 1280, 1825 .vsync_start = 1280 + 28, 1826 .vsync_end = 1280 + 28 + 1, 1827 .vtotal = 1280 + 28 + 1 + 14, 1828 .vrefresh = 60, 1829 }; 1830 1831 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 1832 .desc = { 1833 .modes = &lg_ld070wx3_sl01_mode, 1834 .num_modes = 1, 1835 .bpc = 8, 1836 .size = { 1837 .width = 94, 1838 .height = 151, 1839 }, 1840 }, 1841 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 1842 .format = MIPI_DSI_FMT_RGB888, 1843 .lanes = 4, 1844 }; 1845 1846 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 1847 .clock = 67000, 1848 .hdisplay = 720, 1849 .hsync_start = 720 + 12, 1850 .hsync_end = 720 + 12 + 4, 1851 .htotal = 720 + 12 + 4 + 112, 1852 .vdisplay = 1280, 1853 .vsync_start = 1280 + 8, 1854 .vsync_end = 1280 + 8 + 4, 1855 .vtotal = 1280 + 8 + 4 + 12, 1856 .vrefresh = 60, 1857 }; 1858 1859 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 1860 .desc = { 1861 .modes = &lg_lh500wx1_sd03_mode, 1862 .num_modes = 1, 1863 .bpc = 8, 1864 .size = { 1865 .width = 62, 1866 .height = 110, 1867 }, 1868 }, 1869 .flags = MIPI_DSI_MODE_VIDEO, 1870 .format = MIPI_DSI_FMT_RGB888, 1871 .lanes = 4, 1872 }; 1873 1874 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 1875 .clock = 157200, 1876 .hdisplay = 1920, 1877 .hsync_start = 1920 + 154, 1878 .hsync_end = 1920 + 154 + 16, 1879 .htotal = 1920 + 154 + 16 + 32, 1880 .vdisplay = 1200, 1881 .vsync_start = 1200 + 17, 1882 .vsync_end = 1200 + 17 + 2, 1883 .vtotal = 1200 + 17 + 2 + 16, 1884 .vrefresh = 60, 1885 }; 1886 1887 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 1888 .desc = { 1889 .modes = &panasonic_vvx10f004b00_mode, 1890 .num_modes = 1, 1891 .bpc = 8, 1892 .size = { 1893 .width = 217, 1894 .height = 136, 1895 }, 1896 }, 1897 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1898 MIPI_DSI_CLOCK_NON_CONTINUOUS, 1899 .format = MIPI_DSI_FMT_RGB888, 1900 .lanes = 4, 1901 }; 1902 1903 static const struct of_device_id dsi_of_match[] = { 1904 { 1905 .compatible = "auo,b080uan01", 1906 .data = &auo_b080uan01 1907 }, { 1908 .compatible = "boe,tv080wum-nl0", 1909 .data = &boe_tv080wum_nl0 1910 }, { 1911 .compatible = "lg,ld070wx3-sl01", 1912 .data = &lg_ld070wx3_sl01 1913 }, { 1914 .compatible = "lg,lh500wx1-sd03", 1915 .data = &lg_lh500wx1_sd03 1916 }, { 1917 .compatible = "panasonic,vvx10f004b00", 1918 .data = &panasonic_vvx10f004b00 1919 }, { 1920 /* sentinel */ 1921 } 1922 }; 1923 MODULE_DEVICE_TABLE(of, dsi_of_match); 1924 1925 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 1926 { 1927 const struct panel_desc_dsi *desc; 1928 const struct of_device_id *id; 1929 int err; 1930 1931 id = of_match_node(dsi_of_match, dsi->dev.of_node); 1932 if (!id) 1933 return -ENODEV; 1934 1935 desc = id->data; 1936 1937 err = panel_simple_probe(&dsi->dev, &desc->desc); 1938 if (err < 0) 1939 return err; 1940 1941 dsi->mode_flags = desc->flags; 1942 dsi->format = desc->format; 1943 dsi->lanes = desc->lanes; 1944 1945 return mipi_dsi_attach(dsi); 1946 } 1947 1948 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 1949 { 1950 int err; 1951 1952 err = mipi_dsi_detach(dsi); 1953 if (err < 0) 1954 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 1955 1956 return panel_simple_remove(&dsi->dev); 1957 } 1958 1959 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 1960 { 1961 panel_simple_shutdown(&dsi->dev); 1962 } 1963 1964 static struct mipi_dsi_driver panel_simple_dsi_driver = { 1965 .driver = { 1966 .name = "panel-simple-dsi", 1967 .of_match_table = dsi_of_match, 1968 }, 1969 .probe = panel_simple_dsi_probe, 1970 .remove = panel_simple_dsi_remove, 1971 .shutdown = panel_simple_dsi_shutdown, 1972 }; 1973 1974 static int __init panel_simple_init(void) 1975 { 1976 int err; 1977 1978 err = platform_driver_register(&panel_simple_platform_driver); 1979 if (err < 0) 1980 return err; 1981 1982 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 1983 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 1984 if (err < 0) 1985 return err; 1986 } 1987 1988 return 0; 1989 } 1990 module_init(panel_simple_init); 1991 1992 static void __exit panel_simple_exit(void) 1993 { 1994 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 1995 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 1996 1997 platform_driver_unregister(&panel_simple_platform_driver); 1998 } 1999 module_exit(panel_simple_exit); 2000 2001 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2002 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2003 MODULE_LICENSE("GPL and additional rights"); 2004