1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * struct panel_desc - Describes a simple panel. 43 */ 44 struct panel_desc { 45 /** 46 * @modes: Pointer to array of fixed modes appropriate for this panel. 47 * 48 * If only one mode then this can just be the address of the mode. 49 * NOTE: cannot be used with "timings" and also if this is specified 50 * then you cannot override the mode in the device tree. 51 */ 52 const struct drm_display_mode *modes; 53 54 /** @num_modes: Number of elements in modes array. */ 55 unsigned int num_modes; 56 57 /** 58 * @timings: Pointer to array of display timings 59 * 60 * NOTE: cannot be used with "modes" and also these will be used to 61 * validate a device tree override if one is present. 62 */ 63 const struct display_timing *timings; 64 65 /** @num_timings: Number of elements in timings array. */ 66 unsigned int num_timings; 67 68 /** @bpc: Bits per color. */ 69 unsigned int bpc; 70 71 /** @size: Structure containing the physical size of this panel. */ 72 struct { 73 /** 74 * @size.width: Width (in mm) of the active display area. 75 */ 76 unsigned int width; 77 78 /** 79 * @size.height: Height (in mm) of the active display area. 80 */ 81 unsigned int height; 82 } size; 83 84 /** @delay: Structure containing various delay values for this panel. */ 85 struct { 86 /** 87 * @delay.prepare: Time for the panel to become ready. 88 * 89 * The time (in milliseconds) that it takes for the panel to 90 * become ready and start receiving video data 91 */ 92 unsigned int prepare; 93 94 /** 95 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up. 96 * 97 * Add this to the prepare delay if we know Hot Plug Detect 98 * isn't used. 99 */ 100 unsigned int hpd_absent_delay; 101 102 /** 103 * @delay.prepare_to_enable: Time between prepare and enable. 104 * 105 * The minimum time, in milliseconds, that needs to have passed 106 * between when prepare finished and enable may begin. If at 107 * enable time less time has passed since prepare finished, 108 * the driver waits for the remaining time. 109 * 110 * If a fixed enable delay is also specified, we'll start 111 * counting before delaying for the fixed delay. 112 * 113 * If a fixed prepare delay is also specified, we won't start 114 * counting until after the fixed delay. We can't overlap this 115 * fixed delay with the min time because the fixed delay 116 * doesn't happen at the end of the function if a HPD GPIO was 117 * specified. 118 * 119 * In other words: 120 * prepare() 121 * ... 122 * // do fixed prepare delay 123 * // wait for HPD GPIO if applicable 124 * // start counting for prepare_to_enable 125 * 126 * enable() 127 * // do fixed enable delay 128 * // enforce prepare_to_enable min time 129 */ 130 unsigned int prepare_to_enable; 131 132 /** 133 * @delay.enable: Time for the panel to display a valid frame. 134 * 135 * The time (in milliseconds) that it takes for the panel to 136 * display the first valid frame after starting to receive 137 * video data. 138 */ 139 unsigned int enable; 140 141 /** 142 * @delay.disable: Time for the panel to turn the display off. 143 * 144 * The time (in milliseconds) that it takes for the panel to 145 * turn the display off (no content is visible). 146 */ 147 unsigned int disable; 148 149 /** 150 * @delay.unprepare: Time to power down completely. 151 * 152 * The time (in milliseconds) that it takes for the panel 153 * to power itself down completely. 154 * 155 * This time is used to prevent a future "prepare" from 156 * starting until at least this many milliseconds has passed. 157 * If at prepare time less time has passed since unprepare 158 * finished, the driver waits for the remaining time. 159 */ 160 unsigned int unprepare; 161 } delay; 162 163 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 164 u32 bus_format; 165 166 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 167 u32 bus_flags; 168 169 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 170 int connector_type; 171 }; 172 173 struct panel_simple { 174 struct drm_panel base; 175 bool enabled; 176 bool no_hpd; 177 178 ktime_t prepared_time; 179 ktime_t unprepared_time; 180 181 const struct panel_desc *desc; 182 183 struct regulator *supply; 184 struct i2c_adapter *ddc; 185 186 struct gpio_desc *enable_gpio; 187 struct gpio_desc *hpd_gpio; 188 189 struct drm_display_mode override_mode; 190 191 enum drm_panel_orientation orientation; 192 }; 193 194 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 195 { 196 return container_of(panel, struct panel_simple, base); 197 } 198 199 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 200 struct drm_connector *connector) 201 { 202 struct drm_display_mode *mode; 203 unsigned int i, num = 0; 204 205 for (i = 0; i < panel->desc->num_timings; i++) { 206 const struct display_timing *dt = &panel->desc->timings[i]; 207 struct videomode vm; 208 209 videomode_from_timing(dt, &vm); 210 mode = drm_mode_create(connector->dev); 211 if (!mode) { 212 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 213 dt->hactive.typ, dt->vactive.typ); 214 continue; 215 } 216 217 drm_display_mode_from_videomode(&vm, mode); 218 219 mode->type |= DRM_MODE_TYPE_DRIVER; 220 221 if (panel->desc->num_timings == 1) 222 mode->type |= DRM_MODE_TYPE_PREFERRED; 223 224 drm_mode_probed_add(connector, mode); 225 num++; 226 } 227 228 return num; 229 } 230 231 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 232 struct drm_connector *connector) 233 { 234 struct drm_display_mode *mode; 235 unsigned int i, num = 0; 236 237 for (i = 0; i < panel->desc->num_modes; i++) { 238 const struct drm_display_mode *m = &panel->desc->modes[i]; 239 240 mode = drm_mode_duplicate(connector->dev, m); 241 if (!mode) { 242 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 243 m->hdisplay, m->vdisplay, 244 drm_mode_vrefresh(m)); 245 continue; 246 } 247 248 mode->type |= DRM_MODE_TYPE_DRIVER; 249 250 if (panel->desc->num_modes == 1) 251 mode->type |= DRM_MODE_TYPE_PREFERRED; 252 253 drm_mode_set_name(mode); 254 255 drm_mode_probed_add(connector, mode); 256 num++; 257 } 258 259 return num; 260 } 261 262 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 263 struct drm_connector *connector) 264 { 265 struct drm_display_mode *mode; 266 bool has_override = panel->override_mode.type; 267 unsigned int num = 0; 268 269 if (!panel->desc) 270 return 0; 271 272 if (has_override) { 273 mode = drm_mode_duplicate(connector->dev, 274 &panel->override_mode); 275 if (mode) { 276 drm_mode_probed_add(connector, mode); 277 num = 1; 278 } else { 279 dev_err(panel->base.dev, "failed to add override mode\n"); 280 } 281 } 282 283 /* Only add timings if override was not there or failed to validate */ 284 if (num == 0 && panel->desc->num_timings) 285 num = panel_simple_get_timings_modes(panel, connector); 286 287 /* 288 * Only add fixed modes if timings/override added no mode. 289 * 290 * We should only ever have either the display timings specified 291 * or a fixed mode. Anything else is rather bogus. 292 */ 293 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 294 if (num == 0) 295 num = panel_simple_get_display_modes(panel, connector); 296 297 connector->display_info.bpc = panel->desc->bpc; 298 connector->display_info.width_mm = panel->desc->size.width; 299 connector->display_info.height_mm = panel->desc->size.height; 300 if (panel->desc->bus_format) 301 drm_display_info_set_bus_formats(&connector->display_info, 302 &panel->desc->bus_format, 1); 303 connector->display_info.bus_flags = panel->desc->bus_flags; 304 305 return num; 306 } 307 308 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 309 { 310 ktime_t now_ktime, min_ktime; 311 312 if (!min_ms) 313 return; 314 315 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 316 now_ktime = ktime_get(); 317 318 if (ktime_before(now_ktime, min_ktime)) 319 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 320 } 321 322 static int panel_simple_disable(struct drm_panel *panel) 323 { 324 struct panel_simple *p = to_panel_simple(panel); 325 326 if (!p->enabled) 327 return 0; 328 329 if (p->desc->delay.disable) 330 msleep(p->desc->delay.disable); 331 332 p->enabled = false; 333 334 return 0; 335 } 336 337 static int panel_simple_unprepare(struct drm_panel *panel) 338 { 339 struct panel_simple *p = to_panel_simple(panel); 340 341 if (p->prepared_time == 0) 342 return 0; 343 344 gpiod_set_value_cansleep(p->enable_gpio, 0); 345 346 regulator_disable(p->supply); 347 348 p->prepared_time = 0; 349 p->unprepared_time = ktime_get(); 350 351 return 0; 352 } 353 354 static int panel_simple_get_hpd_gpio(struct device *dev, 355 struct panel_simple *p, bool from_probe) 356 { 357 int err; 358 359 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 360 if (IS_ERR(p->hpd_gpio)) { 361 err = PTR_ERR(p->hpd_gpio); 362 363 /* 364 * If we're called from probe we won't consider '-EPROBE_DEFER' 365 * to be an error--we'll leave the error code in "hpd_gpio". 366 * When we try to use it we'll try again. This allows for 367 * circular dependencies where the component providing the 368 * hpd gpio needs the panel to init before probing. 369 */ 370 if (err != -EPROBE_DEFER || !from_probe) { 371 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 372 return err; 373 } 374 } 375 376 return 0; 377 } 378 379 static int panel_simple_prepare_once(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 unsigned int delay; 383 int err; 384 int hpd_asserted; 385 unsigned long hpd_wait_us; 386 387 if (p->prepared_time != 0) 388 return 0; 389 390 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 391 392 err = regulator_enable(p->supply); 393 if (err < 0) { 394 dev_err(panel->dev, "failed to enable supply: %d\n", err); 395 return err; 396 } 397 398 gpiod_set_value_cansleep(p->enable_gpio, 1); 399 400 delay = p->desc->delay.prepare; 401 if (p->no_hpd) 402 delay += p->desc->delay.hpd_absent_delay; 403 if (delay) 404 msleep(delay); 405 406 if (p->hpd_gpio) { 407 if (IS_ERR(p->hpd_gpio)) { 408 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 409 if (err) 410 goto error; 411 } 412 413 if (p->desc->delay.hpd_absent_delay) 414 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL; 415 else 416 hpd_wait_us = 2000000; 417 418 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 419 hpd_asserted, hpd_asserted, 420 1000, hpd_wait_us); 421 if (hpd_asserted < 0) 422 err = hpd_asserted; 423 424 if (err) { 425 if (err != -ETIMEDOUT) 426 dev_err(panel->dev, 427 "error waiting for hpd GPIO: %d\n", err); 428 goto error; 429 } 430 } 431 432 p->prepared_time = ktime_get(); 433 434 return 0; 435 436 error: 437 gpiod_set_value_cansleep(p->enable_gpio, 0); 438 regulator_disable(p->supply); 439 p->unprepared_time = ktime_get(); 440 441 return err; 442 } 443 444 /* 445 * Some panels simply don't always come up and need to be power cycled to 446 * work properly. We'll allow for a handful of retries. 447 */ 448 #define MAX_PANEL_PREPARE_TRIES 5 449 450 static int panel_simple_prepare(struct drm_panel *panel) 451 { 452 int ret; 453 int try; 454 455 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) { 456 ret = panel_simple_prepare_once(panel); 457 if (ret != -ETIMEDOUT) 458 break; 459 } 460 461 if (ret == -ETIMEDOUT) 462 dev_err(panel->dev, "Prepare timeout after %d tries\n", try); 463 else if (try) 464 dev_warn(panel->dev, "Prepare needed %d retries\n", try); 465 466 return ret; 467 } 468 469 static int panel_simple_enable(struct drm_panel *panel) 470 { 471 struct panel_simple *p = to_panel_simple(panel); 472 473 if (p->enabled) 474 return 0; 475 476 if (p->desc->delay.enable) 477 msleep(p->desc->delay.enable); 478 479 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable); 480 481 p->enabled = true; 482 483 return 0; 484 } 485 486 static int panel_simple_get_modes(struct drm_panel *panel, 487 struct drm_connector *connector) 488 { 489 struct panel_simple *p = to_panel_simple(panel); 490 int num = 0; 491 492 /* probe EDID if a DDC bus is available */ 493 if (p->ddc) { 494 struct edid *edid = drm_get_edid(connector, p->ddc); 495 496 drm_connector_update_edid_property(connector, edid); 497 if (edid) { 498 num += drm_add_edid_modes(connector, edid); 499 kfree(edid); 500 } 501 } 502 503 /* add hard-coded panel modes */ 504 num += panel_simple_get_non_edid_modes(p, connector); 505 506 /* set up connector's "panel orientation" property */ 507 drm_connector_set_panel_orientation(connector, p->orientation); 508 509 return num; 510 } 511 512 static int panel_simple_get_timings(struct drm_panel *panel, 513 unsigned int num_timings, 514 struct display_timing *timings) 515 { 516 struct panel_simple *p = to_panel_simple(panel); 517 unsigned int i; 518 519 if (p->desc->num_timings < num_timings) 520 num_timings = p->desc->num_timings; 521 522 if (timings) 523 for (i = 0; i < num_timings; i++) 524 timings[i] = p->desc->timings[i]; 525 526 return p->desc->num_timings; 527 } 528 529 static const struct drm_panel_funcs panel_simple_funcs = { 530 .disable = panel_simple_disable, 531 .unprepare = panel_simple_unprepare, 532 .prepare = panel_simple_prepare, 533 .enable = panel_simple_enable, 534 .get_modes = panel_simple_get_modes, 535 .get_timings = panel_simple_get_timings, 536 }; 537 538 static struct panel_desc panel_dpi; 539 540 static int panel_dpi_probe(struct device *dev, 541 struct panel_simple *panel) 542 { 543 struct display_timing *timing; 544 const struct device_node *np; 545 struct panel_desc *desc; 546 unsigned int bus_flags; 547 struct videomode vm; 548 int ret; 549 550 np = dev->of_node; 551 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 552 if (!desc) 553 return -ENOMEM; 554 555 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 556 if (!timing) 557 return -ENOMEM; 558 559 ret = of_get_display_timing(np, "panel-timing", timing); 560 if (ret < 0) { 561 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 562 np); 563 return ret; 564 } 565 566 desc->timings = timing; 567 desc->num_timings = 1; 568 569 of_property_read_u32(np, "width-mm", &desc->size.width); 570 of_property_read_u32(np, "height-mm", &desc->size.height); 571 572 /* Extract bus_flags from display_timing */ 573 bus_flags = 0; 574 vm.flags = timing->flags; 575 drm_bus_flags_from_videomode(&vm, &bus_flags); 576 desc->bus_flags = bus_flags; 577 578 /* We do not know the connector for the DT node, so guess it */ 579 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 580 581 panel->desc = desc; 582 583 return 0; 584 } 585 586 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 587 (to_check->field.typ >= bounds->field.min && \ 588 to_check->field.typ <= bounds->field.max) 589 static void panel_simple_parse_panel_timing_node(struct device *dev, 590 struct panel_simple *panel, 591 const struct display_timing *ot) 592 { 593 const struct panel_desc *desc = panel->desc; 594 struct videomode vm; 595 unsigned int i; 596 597 if (WARN_ON(desc->num_modes)) { 598 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 599 return; 600 } 601 if (WARN_ON(!desc->num_timings)) { 602 dev_err(dev, "Reject override mode: no timings specified\n"); 603 return; 604 } 605 606 for (i = 0; i < panel->desc->num_timings; i++) { 607 const struct display_timing *dt = &panel->desc->timings[i]; 608 609 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 610 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 611 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 612 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 613 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 614 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 615 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 616 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 617 continue; 618 619 if (ot->flags != dt->flags) 620 continue; 621 622 videomode_from_timing(ot, &vm); 623 drm_display_mode_from_videomode(&vm, &panel->override_mode); 624 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 625 DRM_MODE_TYPE_PREFERRED; 626 break; 627 } 628 629 if (WARN_ON(!panel->override_mode.type)) 630 dev_err(dev, "Reject override mode: No display_timing found\n"); 631 } 632 633 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 634 { 635 struct panel_simple *panel; 636 struct display_timing dt; 637 struct device_node *ddc; 638 int connector_type; 639 u32 bus_flags; 640 int err; 641 642 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 643 if (!panel) 644 return -ENOMEM; 645 646 panel->enabled = false; 647 panel->prepared_time = 0; 648 panel->desc = desc; 649 650 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 651 if (!panel->no_hpd) { 652 err = panel_simple_get_hpd_gpio(dev, panel, true); 653 if (err) 654 return err; 655 } 656 657 panel->supply = devm_regulator_get(dev, "power"); 658 if (IS_ERR(panel->supply)) 659 return PTR_ERR(panel->supply); 660 661 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 662 GPIOD_OUT_LOW); 663 if (IS_ERR(panel->enable_gpio)) { 664 err = PTR_ERR(panel->enable_gpio); 665 if (err != -EPROBE_DEFER) 666 dev_err(dev, "failed to request GPIO: %d\n", err); 667 return err; 668 } 669 670 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 671 if (err) { 672 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 673 return err; 674 } 675 676 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 677 if (ddc) { 678 panel->ddc = of_find_i2c_adapter_by_node(ddc); 679 of_node_put(ddc); 680 681 if (!panel->ddc) 682 return -EPROBE_DEFER; 683 } 684 685 if (desc == &panel_dpi) { 686 /* Handle the generic panel-dpi binding */ 687 err = panel_dpi_probe(dev, panel); 688 if (err) 689 goto free_ddc; 690 } else { 691 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 692 panel_simple_parse_panel_timing_node(dev, panel, &dt); 693 } 694 695 connector_type = desc->connector_type; 696 /* Catch common mistakes for panels. */ 697 switch (connector_type) { 698 case 0: 699 dev_warn(dev, "Specify missing connector_type\n"); 700 connector_type = DRM_MODE_CONNECTOR_DPI; 701 break; 702 case DRM_MODE_CONNECTOR_LVDS: 703 WARN_ON(desc->bus_flags & 704 ~(DRM_BUS_FLAG_DE_LOW | 705 DRM_BUS_FLAG_DE_HIGH | 706 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 707 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 708 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 709 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 710 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 711 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 712 desc->bpc != 6); 713 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 714 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 715 desc->bpc != 8); 716 break; 717 case DRM_MODE_CONNECTOR_eDP: 718 if (desc->bus_format == 0) 719 dev_warn(dev, "Specify missing bus_format\n"); 720 if (desc->bpc != 6 && desc->bpc != 8) 721 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 722 break; 723 case DRM_MODE_CONNECTOR_DSI: 724 if (desc->bpc != 6 && desc->bpc != 8) 725 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 726 break; 727 case DRM_MODE_CONNECTOR_DPI: 728 bus_flags = DRM_BUS_FLAG_DE_LOW | 729 DRM_BUS_FLAG_DE_HIGH | 730 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 731 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 732 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 733 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 734 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 735 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 736 if (desc->bus_flags & ~bus_flags) 737 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 738 if (!(desc->bus_flags & bus_flags)) 739 dev_warn(dev, "Specify missing bus_flags\n"); 740 if (desc->bus_format == 0) 741 dev_warn(dev, "Specify missing bus_format\n"); 742 if (desc->bpc != 6 && desc->bpc != 8) 743 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 744 break; 745 default: 746 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 747 connector_type = DRM_MODE_CONNECTOR_DPI; 748 break; 749 } 750 751 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 752 753 err = drm_panel_of_backlight(&panel->base); 754 if (err) 755 goto free_ddc; 756 757 drm_panel_add(&panel->base); 758 759 dev_set_drvdata(dev, panel); 760 761 return 0; 762 763 free_ddc: 764 if (panel->ddc) 765 put_device(&panel->ddc->dev); 766 767 return err; 768 } 769 770 static int panel_simple_remove(struct device *dev) 771 { 772 struct panel_simple *panel = dev_get_drvdata(dev); 773 774 drm_panel_remove(&panel->base); 775 drm_panel_disable(&panel->base); 776 drm_panel_unprepare(&panel->base); 777 778 if (panel->ddc) 779 put_device(&panel->ddc->dev); 780 781 return 0; 782 } 783 784 static void panel_simple_shutdown(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_disable(&panel->base); 789 drm_panel_unprepare(&panel->base); 790 } 791 792 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 793 .clock = 71100, 794 .hdisplay = 1280, 795 .hsync_start = 1280 + 40, 796 .hsync_end = 1280 + 40 + 80, 797 .htotal = 1280 + 40 + 80 + 40, 798 .vdisplay = 800, 799 .vsync_start = 800 + 3, 800 .vsync_end = 800 + 3 + 10, 801 .vtotal = 800 + 3 + 10 + 10, 802 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 803 }; 804 805 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 806 .modes = &ire_am_1280800n3tzqw_t00h_mode, 807 .num_modes = 1, 808 .bpc = 6, 809 .size = { 810 .width = 217, 811 .height = 136, 812 }, 813 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 815 .connector_type = DRM_MODE_CONNECTOR_LVDS, 816 }; 817 818 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 819 .clock = 9000, 820 .hdisplay = 480, 821 .hsync_start = 480 + 2, 822 .hsync_end = 480 + 2 + 41, 823 .htotal = 480 + 2 + 41 + 2, 824 .vdisplay = 272, 825 .vsync_start = 272 + 2, 826 .vsync_end = 272 + 2 + 10, 827 .vtotal = 272 + 2 + 10 + 2, 828 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 829 }; 830 831 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 832 .modes = &ire_am_480272h3tmqw_t01h_mode, 833 .num_modes = 1, 834 .bpc = 8, 835 .size = { 836 .width = 105, 837 .height = 67, 838 }, 839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 840 }; 841 842 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 843 .clock = 33333, 844 .hdisplay = 800, 845 .hsync_start = 800 + 0, 846 .hsync_end = 800 + 0 + 255, 847 .htotal = 800 + 0 + 255 + 0, 848 .vdisplay = 480, 849 .vsync_start = 480 + 2, 850 .vsync_end = 480 + 2 + 45, 851 .vtotal = 480 + 2 + 45 + 0, 852 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 853 }; 854 855 static const struct panel_desc ampire_am800480r3tmqwa1h = { 856 .modes = &ire_am800480r3tmqwa1h_mode, 857 .num_modes = 1, 858 .bpc = 6, 859 .size = { 860 .width = 152, 861 .height = 91, 862 }, 863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 864 }; 865 866 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 867 .pixelclock = { 26400000, 33300000, 46800000 }, 868 .hactive = { 800, 800, 800 }, 869 .hfront_porch = { 16, 210, 354 }, 870 .hback_porch = { 45, 36, 6 }, 871 .hsync_len = { 1, 10, 40 }, 872 .vactive = { 480, 480, 480 }, 873 .vfront_porch = { 7, 22, 147 }, 874 .vback_porch = { 22, 13, 3 }, 875 .vsync_len = { 1, 10, 20 }, 876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 878 }; 879 880 static const struct panel_desc armadeus_st0700_adapt = { 881 .timings = &santek_st0700i5y_rbslw_f_timing, 882 .num_timings = 1, 883 .bpc = 6, 884 .size = { 885 .width = 154, 886 .height = 86, 887 }, 888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 890 }; 891 892 static const struct drm_display_mode auo_b101aw03_mode = { 893 .clock = 51450, 894 .hdisplay = 1024, 895 .hsync_start = 1024 + 156, 896 .hsync_end = 1024 + 156 + 8, 897 .htotal = 1024 + 156 + 8 + 156, 898 .vdisplay = 600, 899 .vsync_start = 600 + 16, 900 .vsync_end = 600 + 16 + 6, 901 .vtotal = 600 + 16 + 6 + 16, 902 }; 903 904 static const struct panel_desc auo_b101aw03 = { 905 .modes = &auo_b101aw03_mode, 906 .num_modes = 1, 907 .bpc = 6, 908 .size = { 909 .width = 223, 910 .height = 125, 911 }, 912 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 913 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 914 .connector_type = DRM_MODE_CONNECTOR_LVDS, 915 }; 916 917 static const struct display_timing auo_b101ean01_timing = { 918 .pixelclock = { 65300000, 72500000, 75000000 }, 919 .hactive = { 1280, 1280, 1280 }, 920 .hfront_porch = { 18, 119, 119 }, 921 .hback_porch = { 21, 21, 21 }, 922 .hsync_len = { 32, 32, 32 }, 923 .vactive = { 800, 800, 800 }, 924 .vfront_porch = { 4, 4, 4 }, 925 .vback_porch = { 8, 8, 8 }, 926 .vsync_len = { 18, 20, 20 }, 927 }; 928 929 static const struct panel_desc auo_b101ean01 = { 930 .timings = &auo_b101ean01_timing, 931 .num_timings = 1, 932 .bpc = 6, 933 .size = { 934 .width = 217, 935 .height = 136, 936 }, 937 }; 938 939 static const struct drm_display_mode auo_b101xtn01_mode = { 940 .clock = 72000, 941 .hdisplay = 1366, 942 .hsync_start = 1366 + 20, 943 .hsync_end = 1366 + 20 + 70, 944 .htotal = 1366 + 20 + 70, 945 .vdisplay = 768, 946 .vsync_start = 768 + 14, 947 .vsync_end = 768 + 14 + 42, 948 .vtotal = 768 + 14 + 42, 949 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 950 }; 951 952 static const struct panel_desc auo_b101xtn01 = { 953 .modes = &auo_b101xtn01_mode, 954 .num_modes = 1, 955 .bpc = 6, 956 .size = { 957 .width = 223, 958 .height = 125, 959 }, 960 }; 961 962 static const struct drm_display_mode auo_b116xak01_mode = { 963 .clock = 69300, 964 .hdisplay = 1366, 965 .hsync_start = 1366 + 48, 966 .hsync_end = 1366 + 48 + 32, 967 .htotal = 1366 + 48 + 32 + 10, 968 .vdisplay = 768, 969 .vsync_start = 768 + 4, 970 .vsync_end = 768 + 4 + 6, 971 .vtotal = 768 + 4 + 6 + 15, 972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 973 }; 974 975 static const struct panel_desc auo_b116xak01 = { 976 .modes = &auo_b116xak01_mode, 977 .num_modes = 1, 978 .bpc = 6, 979 .size = { 980 .width = 256, 981 .height = 144, 982 }, 983 .delay = { 984 .hpd_absent_delay = 200, 985 }, 986 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 987 .connector_type = DRM_MODE_CONNECTOR_eDP, 988 }; 989 990 static const struct drm_display_mode auo_b116xw03_mode = { 991 .clock = 70589, 992 .hdisplay = 1366, 993 .hsync_start = 1366 + 40, 994 .hsync_end = 1366 + 40 + 40, 995 .htotal = 1366 + 40 + 40 + 32, 996 .vdisplay = 768, 997 .vsync_start = 768 + 10, 998 .vsync_end = 768 + 10 + 12, 999 .vtotal = 768 + 10 + 12 + 6, 1000 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1001 }; 1002 1003 static const struct panel_desc auo_b116xw03 = { 1004 .modes = &auo_b116xw03_mode, 1005 .num_modes = 1, 1006 .bpc = 6, 1007 .size = { 1008 .width = 256, 1009 .height = 144, 1010 }, 1011 .delay = { 1012 .enable = 400, 1013 }, 1014 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 1015 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1016 .connector_type = DRM_MODE_CONNECTOR_eDP, 1017 }; 1018 1019 static const struct drm_display_mode auo_b133xtn01_mode = { 1020 .clock = 69500, 1021 .hdisplay = 1366, 1022 .hsync_start = 1366 + 48, 1023 .hsync_end = 1366 + 48 + 32, 1024 .htotal = 1366 + 48 + 32 + 20, 1025 .vdisplay = 768, 1026 .vsync_start = 768 + 3, 1027 .vsync_end = 768 + 3 + 6, 1028 .vtotal = 768 + 3 + 6 + 13, 1029 }; 1030 1031 static const struct panel_desc auo_b133xtn01 = { 1032 .modes = &auo_b133xtn01_mode, 1033 .num_modes = 1, 1034 .bpc = 6, 1035 .size = { 1036 .width = 293, 1037 .height = 165, 1038 }, 1039 }; 1040 1041 static const struct drm_display_mode auo_b133htn01_mode = { 1042 .clock = 150660, 1043 .hdisplay = 1920, 1044 .hsync_start = 1920 + 172, 1045 .hsync_end = 1920 + 172 + 80, 1046 .htotal = 1920 + 172 + 80 + 60, 1047 .vdisplay = 1080, 1048 .vsync_start = 1080 + 25, 1049 .vsync_end = 1080 + 25 + 10, 1050 .vtotal = 1080 + 25 + 10 + 10, 1051 }; 1052 1053 static const struct panel_desc auo_b133htn01 = { 1054 .modes = &auo_b133htn01_mode, 1055 .num_modes = 1, 1056 .bpc = 6, 1057 .size = { 1058 .width = 293, 1059 .height = 165, 1060 }, 1061 .delay = { 1062 .prepare = 105, 1063 .enable = 20, 1064 .unprepare = 50, 1065 }, 1066 }; 1067 1068 static const struct display_timing auo_g070vvn01_timings = { 1069 .pixelclock = { 33300000, 34209000, 45000000 }, 1070 .hactive = { 800, 800, 800 }, 1071 .hfront_porch = { 20, 40, 200 }, 1072 .hback_porch = { 87, 40, 1 }, 1073 .hsync_len = { 1, 48, 87 }, 1074 .vactive = { 480, 480, 480 }, 1075 .vfront_porch = { 5, 13, 200 }, 1076 .vback_porch = { 31, 31, 29 }, 1077 .vsync_len = { 1, 1, 3 }, 1078 }; 1079 1080 static const struct panel_desc auo_g070vvn01 = { 1081 .timings = &auo_g070vvn01_timings, 1082 .num_timings = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 152, 1086 .height = 91, 1087 }, 1088 .delay = { 1089 .prepare = 200, 1090 .enable = 50, 1091 .disable = 50, 1092 .unprepare = 1000, 1093 }, 1094 }; 1095 1096 static const struct drm_display_mode auo_g101evn010_mode = { 1097 .clock = 68930, 1098 .hdisplay = 1280, 1099 .hsync_start = 1280 + 82, 1100 .hsync_end = 1280 + 82 + 2, 1101 .htotal = 1280 + 82 + 2 + 84, 1102 .vdisplay = 800, 1103 .vsync_start = 800 + 8, 1104 .vsync_end = 800 + 8 + 2, 1105 .vtotal = 800 + 8 + 2 + 6, 1106 }; 1107 1108 static const struct panel_desc auo_g101evn010 = { 1109 .modes = &auo_g101evn010_mode, 1110 .num_modes = 1, 1111 .bpc = 6, 1112 .size = { 1113 .width = 216, 1114 .height = 135, 1115 }, 1116 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1117 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1118 }; 1119 1120 static const struct drm_display_mode auo_g104sn02_mode = { 1121 .clock = 40000, 1122 .hdisplay = 800, 1123 .hsync_start = 800 + 40, 1124 .hsync_end = 800 + 40 + 216, 1125 .htotal = 800 + 40 + 216 + 128, 1126 .vdisplay = 600, 1127 .vsync_start = 600 + 10, 1128 .vsync_end = 600 + 10 + 35, 1129 .vtotal = 600 + 10 + 35 + 2, 1130 }; 1131 1132 static const struct panel_desc auo_g104sn02 = { 1133 .modes = &auo_g104sn02_mode, 1134 .num_modes = 1, 1135 .bpc = 8, 1136 .size = { 1137 .width = 211, 1138 .height = 158, 1139 }, 1140 }; 1141 1142 static const struct drm_display_mode auo_g121ean01_mode = { 1143 .clock = 66700, 1144 .hdisplay = 1280, 1145 .hsync_start = 1280 + 58, 1146 .hsync_end = 1280 + 58 + 8, 1147 .htotal = 1280 + 58 + 8 + 70, 1148 .vdisplay = 800, 1149 .vsync_start = 800 + 6, 1150 .vsync_end = 800 + 6 + 4, 1151 .vtotal = 800 + 6 + 4 + 10, 1152 }; 1153 1154 static const struct panel_desc auo_g121ean01 = { 1155 .modes = &auo_g121ean01_mode, 1156 .num_modes = 1, 1157 .bpc = 8, 1158 .size = { 1159 .width = 261, 1160 .height = 163, 1161 }, 1162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1164 }; 1165 1166 static const struct display_timing auo_g133han01_timings = { 1167 .pixelclock = { 134000000, 141200000, 149000000 }, 1168 .hactive = { 1920, 1920, 1920 }, 1169 .hfront_porch = { 39, 58, 77 }, 1170 .hback_porch = { 59, 88, 117 }, 1171 .hsync_len = { 28, 42, 56 }, 1172 .vactive = { 1080, 1080, 1080 }, 1173 .vfront_porch = { 3, 8, 11 }, 1174 .vback_porch = { 5, 14, 19 }, 1175 .vsync_len = { 4, 14, 19 }, 1176 }; 1177 1178 static const struct panel_desc auo_g133han01 = { 1179 .timings = &auo_g133han01_timings, 1180 .num_timings = 1, 1181 .bpc = 8, 1182 .size = { 1183 .width = 293, 1184 .height = 165, 1185 }, 1186 .delay = { 1187 .prepare = 200, 1188 .enable = 50, 1189 .disable = 50, 1190 .unprepare = 1000, 1191 }, 1192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1194 }; 1195 1196 static const struct drm_display_mode auo_g156xtn01_mode = { 1197 .clock = 76000, 1198 .hdisplay = 1366, 1199 .hsync_start = 1366 + 33, 1200 .hsync_end = 1366 + 33 + 67, 1201 .htotal = 1560, 1202 .vdisplay = 768, 1203 .vsync_start = 768 + 4, 1204 .vsync_end = 768 + 4 + 4, 1205 .vtotal = 806, 1206 }; 1207 1208 static const struct panel_desc auo_g156xtn01 = { 1209 .modes = &auo_g156xtn01_mode, 1210 .num_modes = 1, 1211 .bpc = 8, 1212 .size = { 1213 .width = 344, 1214 .height = 194, 1215 }, 1216 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1217 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1218 }; 1219 1220 static const struct display_timing auo_g185han01_timings = { 1221 .pixelclock = { 120000000, 144000000, 175000000 }, 1222 .hactive = { 1920, 1920, 1920 }, 1223 .hfront_porch = { 36, 120, 148 }, 1224 .hback_porch = { 24, 88, 108 }, 1225 .hsync_len = { 20, 48, 64 }, 1226 .vactive = { 1080, 1080, 1080 }, 1227 .vfront_porch = { 6, 10, 40 }, 1228 .vback_porch = { 2, 5, 20 }, 1229 .vsync_len = { 2, 5, 20 }, 1230 }; 1231 1232 static const struct panel_desc auo_g185han01 = { 1233 .timings = &auo_g185han01_timings, 1234 .num_timings = 1, 1235 .bpc = 8, 1236 .size = { 1237 .width = 409, 1238 .height = 230, 1239 }, 1240 .delay = { 1241 .prepare = 50, 1242 .enable = 200, 1243 .disable = 110, 1244 .unprepare = 1000, 1245 }, 1246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1248 }; 1249 1250 static const struct display_timing auo_g190ean01_timings = { 1251 .pixelclock = { 90000000, 108000000, 135000000 }, 1252 .hactive = { 1280, 1280, 1280 }, 1253 .hfront_porch = { 126, 184, 1266 }, 1254 .hback_porch = { 84, 122, 844 }, 1255 .hsync_len = { 70, 102, 704 }, 1256 .vactive = { 1024, 1024, 1024 }, 1257 .vfront_porch = { 4, 26, 76 }, 1258 .vback_porch = { 2, 8, 25 }, 1259 .vsync_len = { 2, 8, 25 }, 1260 }; 1261 1262 static const struct panel_desc auo_g190ean01 = { 1263 .timings = &auo_g190ean01_timings, 1264 .num_timings = 1, 1265 .bpc = 8, 1266 .size = { 1267 .width = 376, 1268 .height = 301, 1269 }, 1270 .delay = { 1271 .prepare = 50, 1272 .enable = 200, 1273 .disable = 110, 1274 .unprepare = 1000, 1275 }, 1276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1277 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1278 }; 1279 1280 static const struct display_timing auo_p320hvn03_timings = { 1281 .pixelclock = { 106000000, 148500000, 164000000 }, 1282 .hactive = { 1920, 1920, 1920 }, 1283 .hfront_porch = { 25, 50, 130 }, 1284 .hback_porch = { 25, 50, 130 }, 1285 .hsync_len = { 20, 40, 105 }, 1286 .vactive = { 1080, 1080, 1080 }, 1287 .vfront_porch = { 8, 17, 150 }, 1288 .vback_porch = { 8, 17, 150 }, 1289 .vsync_len = { 4, 11, 100 }, 1290 }; 1291 1292 static const struct panel_desc auo_p320hvn03 = { 1293 .timings = &auo_p320hvn03_timings, 1294 .num_timings = 1, 1295 .bpc = 8, 1296 .size = { 1297 .width = 698, 1298 .height = 393, 1299 }, 1300 .delay = { 1301 .prepare = 1, 1302 .enable = 450, 1303 .unprepare = 500, 1304 }, 1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1307 }; 1308 1309 static const struct drm_display_mode auo_t215hvn01_mode = { 1310 .clock = 148800, 1311 .hdisplay = 1920, 1312 .hsync_start = 1920 + 88, 1313 .hsync_end = 1920 + 88 + 44, 1314 .htotal = 1920 + 88 + 44 + 148, 1315 .vdisplay = 1080, 1316 .vsync_start = 1080 + 4, 1317 .vsync_end = 1080 + 4 + 5, 1318 .vtotal = 1080 + 4 + 5 + 36, 1319 }; 1320 1321 static const struct panel_desc auo_t215hvn01 = { 1322 .modes = &auo_t215hvn01_mode, 1323 .num_modes = 1, 1324 .bpc = 8, 1325 .size = { 1326 .width = 430, 1327 .height = 270, 1328 }, 1329 .delay = { 1330 .disable = 5, 1331 .unprepare = 1000, 1332 } 1333 }; 1334 1335 static const struct drm_display_mode avic_tm070ddh03_mode = { 1336 .clock = 51200, 1337 .hdisplay = 1024, 1338 .hsync_start = 1024 + 160, 1339 .hsync_end = 1024 + 160 + 4, 1340 .htotal = 1024 + 160 + 4 + 156, 1341 .vdisplay = 600, 1342 .vsync_start = 600 + 17, 1343 .vsync_end = 600 + 17 + 1, 1344 .vtotal = 600 + 17 + 1 + 17, 1345 }; 1346 1347 static const struct panel_desc avic_tm070ddh03 = { 1348 .modes = &avic_tm070ddh03_mode, 1349 .num_modes = 1, 1350 .bpc = 8, 1351 .size = { 1352 .width = 154, 1353 .height = 90, 1354 }, 1355 .delay = { 1356 .prepare = 20, 1357 .enable = 200, 1358 .disable = 200, 1359 }, 1360 }; 1361 1362 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1363 .clock = 30000, 1364 .hdisplay = 800, 1365 .hsync_start = 800 + 40, 1366 .hsync_end = 800 + 40 + 48, 1367 .htotal = 800 + 40 + 48 + 40, 1368 .vdisplay = 480, 1369 .vsync_start = 480 + 13, 1370 .vsync_end = 480 + 13 + 3, 1371 .vtotal = 480 + 13 + 3 + 29, 1372 }; 1373 1374 static const struct panel_desc bananapi_s070wv20_ct16 = { 1375 .modes = &bananapi_s070wv20_ct16_mode, 1376 .num_modes = 1, 1377 .bpc = 6, 1378 .size = { 1379 .width = 154, 1380 .height = 86, 1381 }, 1382 }; 1383 1384 static const struct drm_display_mode boe_hv070wsa_mode = { 1385 .clock = 42105, 1386 .hdisplay = 1024, 1387 .hsync_start = 1024 + 30, 1388 .hsync_end = 1024 + 30 + 30, 1389 .htotal = 1024 + 30 + 30 + 30, 1390 .vdisplay = 600, 1391 .vsync_start = 600 + 10, 1392 .vsync_end = 600 + 10 + 10, 1393 .vtotal = 600 + 10 + 10 + 10, 1394 }; 1395 1396 static const struct panel_desc boe_hv070wsa = { 1397 .modes = &boe_hv070wsa_mode, 1398 .num_modes = 1, 1399 .bpc = 8, 1400 .size = { 1401 .width = 154, 1402 .height = 90, 1403 }, 1404 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1405 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1406 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1407 }; 1408 1409 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1410 { 1411 .clock = 71900, 1412 .hdisplay = 1280, 1413 .hsync_start = 1280 + 48, 1414 .hsync_end = 1280 + 48 + 32, 1415 .htotal = 1280 + 48 + 32 + 80, 1416 .vdisplay = 800, 1417 .vsync_start = 800 + 3, 1418 .vsync_end = 800 + 3 + 5, 1419 .vtotal = 800 + 3 + 5 + 24, 1420 }, 1421 { 1422 .clock = 57500, 1423 .hdisplay = 1280, 1424 .hsync_start = 1280 + 48, 1425 .hsync_end = 1280 + 48 + 32, 1426 .htotal = 1280 + 48 + 32 + 80, 1427 .vdisplay = 800, 1428 .vsync_start = 800 + 3, 1429 .vsync_end = 800 + 3 + 5, 1430 .vtotal = 800 + 3 + 5 + 24, 1431 }, 1432 }; 1433 1434 static const struct panel_desc boe_nv101wxmn51 = { 1435 .modes = boe_nv101wxmn51_modes, 1436 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1437 .bpc = 8, 1438 .size = { 1439 .width = 217, 1440 .height = 136, 1441 }, 1442 .delay = { 1443 .prepare = 210, 1444 .enable = 50, 1445 .unprepare = 160, 1446 }, 1447 }; 1448 1449 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = { 1450 { 1451 .clock = 207800, 1452 .hdisplay = 2160, 1453 .hsync_start = 2160 + 48, 1454 .hsync_end = 2160 + 48 + 32, 1455 .htotal = 2160 + 48 + 32 + 100, 1456 .vdisplay = 1440, 1457 .vsync_start = 1440 + 3, 1458 .vsync_end = 1440 + 3 + 6, 1459 .vtotal = 1440 + 3 + 6 + 31, 1460 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1461 }, 1462 { 1463 .clock = 138500, 1464 .hdisplay = 2160, 1465 .hsync_start = 2160 + 48, 1466 .hsync_end = 2160 + 48 + 32, 1467 .htotal = 2160 + 48 + 32 + 100, 1468 .vdisplay = 1440, 1469 .vsync_start = 1440 + 3, 1470 .vsync_end = 1440 + 3 + 6, 1471 .vtotal = 1440 + 3 + 6 + 31, 1472 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1473 }, 1474 }; 1475 1476 static const struct panel_desc boe_nv110wtm_n61 = { 1477 .modes = boe_nv110wtm_n61_modes, 1478 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes), 1479 .bpc = 8, 1480 .size = { 1481 .width = 233, 1482 .height = 155, 1483 }, 1484 .delay = { 1485 .hpd_absent_delay = 200, 1486 .prepare_to_enable = 80, 1487 .enable = 50, 1488 .unprepare = 500, 1489 }, 1490 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1491 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1492 .connector_type = DRM_MODE_CONNECTOR_eDP, 1493 }; 1494 1495 /* Also used for boe_nv133fhm_n62 */ 1496 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1497 .clock = 147840, 1498 .hdisplay = 1920, 1499 .hsync_start = 1920 + 48, 1500 .hsync_end = 1920 + 48 + 32, 1501 .htotal = 1920 + 48 + 32 + 200, 1502 .vdisplay = 1080, 1503 .vsync_start = 1080 + 3, 1504 .vsync_end = 1080 + 3 + 6, 1505 .vtotal = 1080 + 3 + 6 + 31, 1506 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1507 }; 1508 1509 /* Also used for boe_nv133fhm_n62 */ 1510 static const struct panel_desc boe_nv133fhm_n61 = { 1511 .modes = &boe_nv133fhm_n61_modes, 1512 .num_modes = 1, 1513 .bpc = 6, 1514 .size = { 1515 .width = 294, 1516 .height = 165, 1517 }, 1518 .delay = { 1519 /* 1520 * When power is first given to the panel there's a short 1521 * spike on the HPD line. It was explained that this spike 1522 * was until the TCON data download was complete. On 1523 * one system this was measured at 8 ms. We'll put 15 ms 1524 * in the prepare delay just to be safe and take it away 1525 * from the hpd_absent_delay (which would otherwise be 200 ms) 1526 * to handle this. That means: 1527 * - If HPD isn't hooked up you still have 200 ms delay. 1528 * - If HPD is hooked up we won't try to look at it for the 1529 * first 15 ms. 1530 */ 1531 .prepare = 15, 1532 .hpd_absent_delay = 185, 1533 1534 .unprepare = 500, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1537 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1538 .connector_type = DRM_MODE_CONNECTOR_eDP, 1539 }; 1540 1541 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1542 { 1543 .clock = 148500, 1544 .hdisplay = 1920, 1545 .hsync_start = 1920 + 48, 1546 .hsync_end = 1920 + 48 + 32, 1547 .htotal = 2200, 1548 .vdisplay = 1080, 1549 .vsync_start = 1080 + 3, 1550 .vsync_end = 1080 + 3 + 5, 1551 .vtotal = 1125, 1552 }, 1553 }; 1554 1555 static const struct panel_desc boe_nv140fhmn49 = { 1556 .modes = boe_nv140fhmn49_modes, 1557 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1558 .bpc = 6, 1559 .size = { 1560 .width = 309, 1561 .height = 174, 1562 }, 1563 .delay = { 1564 .prepare = 210, 1565 .enable = 50, 1566 .unprepare = 160, 1567 }, 1568 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1569 .connector_type = DRM_MODE_CONNECTOR_eDP, 1570 }; 1571 1572 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1573 .clock = 9000, 1574 .hdisplay = 480, 1575 .hsync_start = 480 + 5, 1576 .hsync_end = 480 + 5 + 5, 1577 .htotal = 480 + 5 + 5 + 40, 1578 .vdisplay = 272, 1579 .vsync_start = 272 + 8, 1580 .vsync_end = 272 + 8 + 8, 1581 .vtotal = 272 + 8 + 8 + 8, 1582 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1583 }; 1584 1585 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1586 .modes = &cdtech_s043wq26h_ct7_mode, 1587 .num_modes = 1, 1588 .bpc = 8, 1589 .size = { 1590 .width = 95, 1591 .height = 54, 1592 }, 1593 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1594 }; 1595 1596 /* S070PWS19HP-FC21 2017/04/22 */ 1597 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1598 .clock = 51200, 1599 .hdisplay = 1024, 1600 .hsync_start = 1024 + 160, 1601 .hsync_end = 1024 + 160 + 20, 1602 .htotal = 1024 + 160 + 20 + 140, 1603 .vdisplay = 600, 1604 .vsync_start = 600 + 12, 1605 .vsync_end = 600 + 12 + 3, 1606 .vtotal = 600 + 12 + 3 + 20, 1607 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1608 }; 1609 1610 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1611 .modes = &cdtech_s070pws19hp_fc21_mode, 1612 .num_modes = 1, 1613 .bpc = 6, 1614 .size = { 1615 .width = 154, 1616 .height = 86, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 /* S070SWV29HG-DC44 2017/09/21 */ 1624 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1625 .clock = 33300, 1626 .hdisplay = 800, 1627 .hsync_start = 800 + 210, 1628 .hsync_end = 800 + 210 + 2, 1629 .htotal = 800 + 210 + 2 + 44, 1630 .vdisplay = 480, 1631 .vsync_start = 480 + 22, 1632 .vsync_end = 480 + 22 + 2, 1633 .vtotal = 480 + 22 + 2 + 21, 1634 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1635 }; 1636 1637 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1638 .modes = &cdtech_s070swv29hg_dc44_mode, 1639 .num_modes = 1, 1640 .bpc = 6, 1641 .size = { 1642 .width = 154, 1643 .height = 86, 1644 }, 1645 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1646 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1647 .connector_type = DRM_MODE_CONNECTOR_DPI, 1648 }; 1649 1650 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1651 .clock = 35000, 1652 .hdisplay = 800, 1653 .hsync_start = 800 + 40, 1654 .hsync_end = 800 + 40 + 40, 1655 .htotal = 800 + 40 + 40 + 48, 1656 .vdisplay = 480, 1657 .vsync_start = 480 + 29, 1658 .vsync_end = 480 + 29 + 13, 1659 .vtotal = 480 + 29 + 13 + 3, 1660 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1661 }; 1662 1663 static const struct panel_desc cdtech_s070wv95_ct16 = { 1664 .modes = &cdtech_s070wv95_ct16_mode, 1665 .num_modes = 1, 1666 .bpc = 8, 1667 .size = { 1668 .width = 154, 1669 .height = 85, 1670 }, 1671 }; 1672 1673 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1674 .pixelclock = { 68900000, 71100000, 73400000 }, 1675 .hactive = { 1280, 1280, 1280 }, 1676 .hfront_porch = { 65, 80, 95 }, 1677 .hback_porch = { 64, 79, 94 }, 1678 .hsync_len = { 1, 1, 1 }, 1679 .vactive = { 800, 800, 800 }, 1680 .vfront_porch = { 7, 11, 14 }, 1681 .vback_porch = { 7, 11, 14 }, 1682 .vsync_len = { 1, 1, 1 }, 1683 .flags = DISPLAY_FLAGS_DE_HIGH, 1684 }; 1685 1686 static const struct panel_desc chefree_ch101olhlwh_002 = { 1687 .timings = &chefree_ch101olhlwh_002_timing, 1688 .num_timings = 1, 1689 .bpc = 8, 1690 .size = { 1691 .width = 217, 1692 .height = 135, 1693 }, 1694 .delay = { 1695 .enable = 200, 1696 .disable = 200, 1697 }, 1698 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1700 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1701 }; 1702 1703 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1704 .clock = 66770, 1705 .hdisplay = 800, 1706 .hsync_start = 800 + 49, 1707 .hsync_end = 800 + 49 + 33, 1708 .htotal = 800 + 49 + 33 + 17, 1709 .vdisplay = 1280, 1710 .vsync_start = 1280 + 1, 1711 .vsync_end = 1280 + 1 + 7, 1712 .vtotal = 1280 + 1 + 7 + 15, 1713 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1714 }; 1715 1716 static const struct panel_desc chunghwa_claa070wp03xg = { 1717 .modes = &chunghwa_claa070wp03xg_mode, 1718 .num_modes = 1, 1719 .bpc = 6, 1720 .size = { 1721 .width = 94, 1722 .height = 150, 1723 }, 1724 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1725 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1726 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1727 }; 1728 1729 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1730 .clock = 72070, 1731 .hdisplay = 1366, 1732 .hsync_start = 1366 + 58, 1733 .hsync_end = 1366 + 58 + 58, 1734 .htotal = 1366 + 58 + 58 + 58, 1735 .vdisplay = 768, 1736 .vsync_start = 768 + 4, 1737 .vsync_end = 768 + 4 + 4, 1738 .vtotal = 768 + 4 + 4 + 4, 1739 }; 1740 1741 static const struct panel_desc chunghwa_claa101wa01a = { 1742 .modes = &chunghwa_claa101wa01a_mode, 1743 .num_modes = 1, 1744 .bpc = 6, 1745 .size = { 1746 .width = 220, 1747 .height = 120, 1748 }, 1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1750 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1755 .clock = 69300, 1756 .hdisplay = 1366, 1757 .hsync_start = 1366 + 48, 1758 .hsync_end = 1366 + 48 + 32, 1759 .htotal = 1366 + 48 + 32 + 20, 1760 .vdisplay = 768, 1761 .vsync_start = 768 + 16, 1762 .vsync_end = 768 + 16 + 8, 1763 .vtotal = 768 + 16 + 8 + 16, 1764 }; 1765 1766 static const struct panel_desc chunghwa_claa101wb01 = { 1767 .modes = &chunghwa_claa101wb01_mode, 1768 .num_modes = 1, 1769 .bpc = 6, 1770 .size = { 1771 .width = 223, 1772 .height = 125, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1776 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1777 }; 1778 1779 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1780 .clock = 33260, 1781 .hdisplay = 800, 1782 .hsync_start = 800 + 40, 1783 .hsync_end = 800 + 40 + 128, 1784 .htotal = 800 + 40 + 128 + 88, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 2, 1788 .vtotal = 480 + 10 + 2 + 33, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790 }; 1791 1792 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1793 .modes = &dataimage_scf0700c48ggu18_mode, 1794 .num_modes = 1, 1795 .bpc = 8, 1796 .size = { 1797 .width = 152, 1798 .height = 91, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1802 }; 1803 1804 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1805 .pixelclock = { 45000000, 51200000, 57000000 }, 1806 .hactive = { 1024, 1024, 1024 }, 1807 .hfront_porch = { 100, 106, 113 }, 1808 .hback_porch = { 100, 106, 113 }, 1809 .hsync_len = { 100, 108, 114 }, 1810 .vactive = { 600, 600, 600 }, 1811 .vfront_porch = { 8, 11, 15 }, 1812 .vback_porch = { 8, 11, 15 }, 1813 .vsync_len = { 9, 13, 15 }, 1814 .flags = DISPLAY_FLAGS_DE_HIGH, 1815 }; 1816 1817 static const struct panel_desc dlc_dlc0700yzg_1 = { 1818 .timings = &dlc_dlc0700yzg_1_timing, 1819 .num_timings = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 154, 1823 .height = 86, 1824 }, 1825 .delay = { 1826 .prepare = 30, 1827 .enable = 200, 1828 .disable = 200, 1829 }, 1830 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1831 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1832 }; 1833 1834 static const struct display_timing dlc_dlc1010gig_timing = { 1835 .pixelclock = { 68900000, 71100000, 73400000 }, 1836 .hactive = { 1280, 1280, 1280 }, 1837 .hfront_porch = { 43, 53, 63 }, 1838 .hback_porch = { 43, 53, 63 }, 1839 .hsync_len = { 44, 54, 64 }, 1840 .vactive = { 800, 800, 800 }, 1841 .vfront_porch = { 5, 8, 11 }, 1842 .vback_porch = { 5, 8, 11 }, 1843 .vsync_len = { 5, 7, 11 }, 1844 .flags = DISPLAY_FLAGS_DE_HIGH, 1845 }; 1846 1847 static const struct panel_desc dlc_dlc1010gig = { 1848 .timings = &dlc_dlc1010gig_timing, 1849 .num_timings = 1, 1850 .bpc = 8, 1851 .size = { 1852 .width = 216, 1853 .height = 135, 1854 }, 1855 .delay = { 1856 .prepare = 60, 1857 .enable = 150, 1858 .disable = 100, 1859 .unprepare = 60, 1860 }, 1861 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1862 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1863 }; 1864 1865 static const struct drm_display_mode edt_et035012dm6_mode = { 1866 .clock = 6500, 1867 .hdisplay = 320, 1868 .hsync_start = 320 + 20, 1869 .hsync_end = 320 + 20 + 30, 1870 .htotal = 320 + 20 + 68, 1871 .vdisplay = 240, 1872 .vsync_start = 240 + 4, 1873 .vsync_end = 240 + 4 + 4, 1874 .vtotal = 240 + 4 + 4 + 14, 1875 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1876 }; 1877 1878 static const struct panel_desc edt_et035012dm6 = { 1879 .modes = &edt_et035012dm6_mode, 1880 .num_modes = 1, 1881 .bpc = 8, 1882 .size = { 1883 .width = 70, 1884 .height = 52, 1885 }, 1886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1887 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1888 }; 1889 1890 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1891 .clock = 10870, 1892 .hdisplay = 480, 1893 .hsync_start = 480 + 8, 1894 .hsync_end = 480 + 8 + 4, 1895 .htotal = 480 + 8 + 4 + 41, 1896 1897 /* 1898 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1899 * fb_align 1900 */ 1901 1902 .vdisplay = 288, 1903 .vsync_start = 288 + 2, 1904 .vsync_end = 288 + 2 + 4, 1905 .vtotal = 288 + 2 + 4 + 10, 1906 }; 1907 1908 static const struct panel_desc edt_etm043080dh6gp = { 1909 .modes = &edt_etm043080dh6gp_mode, 1910 .num_modes = 1, 1911 .bpc = 8, 1912 .size = { 1913 .width = 100, 1914 .height = 65, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1917 .connector_type = DRM_MODE_CONNECTOR_DPI, 1918 }; 1919 1920 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1921 .clock = 9000, 1922 .hdisplay = 480, 1923 .hsync_start = 480 + 2, 1924 .hsync_end = 480 + 2 + 41, 1925 .htotal = 480 + 2 + 41 + 2, 1926 .vdisplay = 272, 1927 .vsync_start = 272 + 2, 1928 .vsync_end = 272 + 2 + 10, 1929 .vtotal = 272 + 2 + 10 + 2, 1930 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1931 }; 1932 1933 static const struct panel_desc edt_etm0430g0dh6 = { 1934 .modes = &edt_etm0430g0dh6_mode, 1935 .num_modes = 1, 1936 .bpc = 6, 1937 .size = { 1938 .width = 95, 1939 .height = 54, 1940 }, 1941 }; 1942 1943 static const struct drm_display_mode edt_et057090dhu_mode = { 1944 .clock = 25175, 1945 .hdisplay = 640, 1946 .hsync_start = 640 + 16, 1947 .hsync_end = 640 + 16 + 30, 1948 .htotal = 640 + 16 + 30 + 114, 1949 .vdisplay = 480, 1950 .vsync_start = 480 + 10, 1951 .vsync_end = 480 + 10 + 3, 1952 .vtotal = 480 + 10 + 3 + 32, 1953 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1954 }; 1955 1956 static const struct panel_desc edt_et057090dhu = { 1957 .modes = &edt_et057090dhu_mode, 1958 .num_modes = 1, 1959 .bpc = 6, 1960 .size = { 1961 .width = 115, 1962 .height = 86, 1963 }, 1964 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1965 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1966 .connector_type = DRM_MODE_CONNECTOR_DPI, 1967 }; 1968 1969 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1970 .clock = 33260, 1971 .hdisplay = 800, 1972 .hsync_start = 800 + 40, 1973 .hsync_end = 800 + 40 + 128, 1974 .htotal = 800 + 40 + 128 + 88, 1975 .vdisplay = 480, 1976 .vsync_start = 480 + 10, 1977 .vsync_end = 480 + 10 + 2, 1978 .vtotal = 480 + 10 + 2 + 33, 1979 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1980 }; 1981 1982 static const struct panel_desc edt_etm0700g0dh6 = { 1983 .modes = &edt_etm0700g0dh6_mode, 1984 .num_modes = 1, 1985 .bpc = 6, 1986 .size = { 1987 .width = 152, 1988 .height = 91, 1989 }, 1990 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1991 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1992 .connector_type = DRM_MODE_CONNECTOR_DPI, 1993 }; 1994 1995 static const struct panel_desc edt_etm0700g0bdh6 = { 1996 .modes = &edt_etm0700g0dh6_mode, 1997 .num_modes = 1, 1998 .bpc = 6, 1999 .size = { 2000 .width = 152, 2001 .height = 91, 2002 }, 2003 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2004 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2005 }; 2006 2007 static const struct display_timing evervision_vgg804821_timing = { 2008 .pixelclock = { 27600000, 33300000, 50000000 }, 2009 .hactive = { 800, 800, 800 }, 2010 .hfront_porch = { 40, 66, 70 }, 2011 .hback_porch = { 40, 67, 70 }, 2012 .hsync_len = { 40, 67, 70 }, 2013 .vactive = { 480, 480, 480 }, 2014 .vfront_porch = { 6, 10, 10 }, 2015 .vback_porch = { 7, 11, 11 }, 2016 .vsync_len = { 7, 11, 11 }, 2017 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2018 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2019 DISPLAY_FLAGS_SYNC_NEGEDGE, 2020 }; 2021 2022 static const struct panel_desc evervision_vgg804821 = { 2023 .timings = &evervision_vgg804821_timing, 2024 .num_timings = 1, 2025 .bpc = 8, 2026 .size = { 2027 .width = 108, 2028 .height = 64, 2029 }, 2030 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2031 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2032 }; 2033 2034 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2035 .clock = 32260, 2036 .hdisplay = 800, 2037 .hsync_start = 800 + 168, 2038 .hsync_end = 800 + 168 + 64, 2039 .htotal = 800 + 168 + 64 + 88, 2040 .vdisplay = 480, 2041 .vsync_start = 480 + 37, 2042 .vsync_end = 480 + 37 + 2, 2043 .vtotal = 480 + 37 + 2 + 8, 2044 }; 2045 2046 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2047 .modes = &foxlink_fl500wvr00_a0t_mode, 2048 .num_modes = 1, 2049 .bpc = 8, 2050 .size = { 2051 .width = 108, 2052 .height = 65, 2053 }, 2054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2055 }; 2056 2057 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2058 { /* 60 Hz */ 2059 .clock = 6000, 2060 .hdisplay = 320, 2061 .hsync_start = 320 + 44, 2062 .hsync_end = 320 + 44 + 16, 2063 .htotal = 320 + 44 + 16 + 20, 2064 .vdisplay = 240, 2065 .vsync_start = 240 + 2, 2066 .vsync_end = 240 + 2 + 6, 2067 .vtotal = 240 + 2 + 6 + 2, 2068 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2069 }, 2070 { /* 50 Hz */ 2071 .clock = 5400, 2072 .hdisplay = 320, 2073 .hsync_start = 320 + 56, 2074 .hsync_end = 320 + 56 + 16, 2075 .htotal = 320 + 56 + 16 + 40, 2076 .vdisplay = 240, 2077 .vsync_start = 240 + 2, 2078 .vsync_end = 240 + 2 + 6, 2079 .vtotal = 240 + 2 + 6 + 2, 2080 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2081 }, 2082 }; 2083 2084 static const struct panel_desc frida_frd350h54004 = { 2085 .modes = frida_frd350h54004_modes, 2086 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2087 .bpc = 8, 2088 .size = { 2089 .width = 77, 2090 .height = 64, 2091 }, 2092 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2093 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2094 .connector_type = DRM_MODE_CONNECTOR_DPI, 2095 }; 2096 2097 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2098 .clock = 67185, 2099 .hdisplay = 800, 2100 .hsync_start = 800 + 20, 2101 .hsync_end = 800 + 20 + 24, 2102 .htotal = 800 + 20 + 24 + 20, 2103 .vdisplay = 1280, 2104 .vsync_start = 1280 + 4, 2105 .vsync_end = 1280 + 4 + 8, 2106 .vtotal = 1280 + 4 + 8 + 4, 2107 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2108 }; 2109 2110 static const struct panel_desc friendlyarm_hd702e = { 2111 .modes = &friendlyarm_hd702e_mode, 2112 .num_modes = 1, 2113 .size = { 2114 .width = 94, 2115 .height = 151, 2116 }, 2117 }; 2118 2119 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2120 .clock = 9000, 2121 .hdisplay = 480, 2122 .hsync_start = 480 + 5, 2123 .hsync_end = 480 + 5 + 1, 2124 .htotal = 480 + 5 + 1 + 40, 2125 .vdisplay = 272, 2126 .vsync_start = 272 + 8, 2127 .vsync_end = 272 + 8 + 1, 2128 .vtotal = 272 + 8 + 1 + 8, 2129 }; 2130 2131 static const struct panel_desc giantplus_gpg482739qs5 = { 2132 .modes = &giantplus_gpg482739qs5_mode, 2133 .num_modes = 1, 2134 .bpc = 8, 2135 .size = { 2136 .width = 95, 2137 .height = 54, 2138 }, 2139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2140 }; 2141 2142 static const struct display_timing giantplus_gpm940b0_timing = { 2143 .pixelclock = { 13500000, 27000000, 27500000 }, 2144 .hactive = { 320, 320, 320 }, 2145 .hfront_porch = { 14, 686, 718 }, 2146 .hback_porch = { 50, 70, 255 }, 2147 .hsync_len = { 1, 1, 1 }, 2148 .vactive = { 240, 240, 240 }, 2149 .vfront_porch = { 1, 1, 179 }, 2150 .vback_porch = { 1, 21, 31 }, 2151 .vsync_len = { 1, 1, 6 }, 2152 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2153 }; 2154 2155 static const struct panel_desc giantplus_gpm940b0 = { 2156 .timings = &giantplus_gpm940b0_timing, 2157 .num_timings = 1, 2158 .bpc = 8, 2159 .size = { 2160 .width = 60, 2161 .height = 45, 2162 }, 2163 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2164 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2165 }; 2166 2167 static const struct display_timing hannstar_hsd070pww1_timing = { 2168 .pixelclock = { 64300000, 71100000, 82000000 }, 2169 .hactive = { 1280, 1280, 1280 }, 2170 .hfront_porch = { 1, 1, 10 }, 2171 .hback_porch = { 1, 1, 10 }, 2172 /* 2173 * According to the data sheet, the minimum horizontal blanking interval 2174 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2175 * minimum working horizontal blanking interval to be 60 clocks. 2176 */ 2177 .hsync_len = { 58, 158, 661 }, 2178 .vactive = { 800, 800, 800 }, 2179 .vfront_porch = { 1, 1, 10 }, 2180 .vback_porch = { 1, 1, 10 }, 2181 .vsync_len = { 1, 21, 203 }, 2182 .flags = DISPLAY_FLAGS_DE_HIGH, 2183 }; 2184 2185 static const struct panel_desc hannstar_hsd070pww1 = { 2186 .timings = &hannstar_hsd070pww1_timing, 2187 .num_timings = 1, 2188 .bpc = 6, 2189 .size = { 2190 .width = 151, 2191 .height = 94, 2192 }, 2193 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2195 }; 2196 2197 static const struct display_timing hannstar_hsd100pxn1_timing = { 2198 .pixelclock = { 55000000, 65000000, 75000000 }, 2199 .hactive = { 1024, 1024, 1024 }, 2200 .hfront_porch = { 40, 40, 40 }, 2201 .hback_porch = { 220, 220, 220 }, 2202 .hsync_len = { 20, 60, 100 }, 2203 .vactive = { 768, 768, 768 }, 2204 .vfront_porch = { 7, 7, 7 }, 2205 .vback_porch = { 21, 21, 21 }, 2206 .vsync_len = { 10, 10, 10 }, 2207 .flags = DISPLAY_FLAGS_DE_HIGH, 2208 }; 2209 2210 static const struct panel_desc hannstar_hsd100pxn1 = { 2211 .timings = &hannstar_hsd100pxn1_timing, 2212 .num_timings = 1, 2213 .bpc = 6, 2214 .size = { 2215 .width = 203, 2216 .height = 152, 2217 }, 2218 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2220 }; 2221 2222 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2223 .clock = 33333, 2224 .hdisplay = 800, 2225 .hsync_start = 800 + 85, 2226 .hsync_end = 800 + 85 + 86, 2227 .htotal = 800 + 85 + 86 + 85, 2228 .vdisplay = 480, 2229 .vsync_start = 480 + 16, 2230 .vsync_end = 480 + 16 + 13, 2231 .vtotal = 480 + 16 + 13 + 16, 2232 }; 2233 2234 static const struct panel_desc hitachi_tx23d38vm0caa = { 2235 .modes = &hitachi_tx23d38vm0caa_mode, 2236 .num_modes = 1, 2237 .bpc = 6, 2238 .size = { 2239 .width = 195, 2240 .height = 117, 2241 }, 2242 .delay = { 2243 .enable = 160, 2244 .disable = 160, 2245 }, 2246 }; 2247 2248 static const struct drm_display_mode innolux_at043tn24_mode = { 2249 .clock = 9000, 2250 .hdisplay = 480, 2251 .hsync_start = 480 + 2, 2252 .hsync_end = 480 + 2 + 41, 2253 .htotal = 480 + 2 + 41 + 2, 2254 .vdisplay = 272, 2255 .vsync_start = 272 + 2, 2256 .vsync_end = 272 + 2 + 10, 2257 .vtotal = 272 + 2 + 10 + 2, 2258 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2259 }; 2260 2261 static const struct panel_desc innolux_at043tn24 = { 2262 .modes = &innolux_at043tn24_mode, 2263 .num_modes = 1, 2264 .bpc = 8, 2265 .size = { 2266 .width = 95, 2267 .height = 54, 2268 }, 2269 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2270 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2271 }; 2272 2273 static const struct drm_display_mode innolux_at070tn92_mode = { 2274 .clock = 33333, 2275 .hdisplay = 800, 2276 .hsync_start = 800 + 210, 2277 .hsync_end = 800 + 210 + 20, 2278 .htotal = 800 + 210 + 20 + 46, 2279 .vdisplay = 480, 2280 .vsync_start = 480 + 22, 2281 .vsync_end = 480 + 22 + 10, 2282 .vtotal = 480 + 22 + 23 + 10, 2283 }; 2284 2285 static const struct panel_desc innolux_at070tn92 = { 2286 .modes = &innolux_at070tn92_mode, 2287 .num_modes = 1, 2288 .size = { 2289 .width = 154, 2290 .height = 86, 2291 }, 2292 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2293 }; 2294 2295 static const struct display_timing innolux_g070y2_l01_timing = { 2296 .pixelclock = { 28000000, 29500000, 32000000 }, 2297 .hactive = { 800, 800, 800 }, 2298 .hfront_porch = { 61, 91, 141 }, 2299 .hback_porch = { 60, 90, 140 }, 2300 .hsync_len = { 12, 12, 12 }, 2301 .vactive = { 480, 480, 480 }, 2302 .vfront_porch = { 4, 9, 30 }, 2303 .vback_porch = { 4, 8, 28 }, 2304 .vsync_len = { 2, 2, 2 }, 2305 .flags = DISPLAY_FLAGS_DE_HIGH, 2306 }; 2307 2308 static const struct panel_desc innolux_g070y2_l01 = { 2309 .timings = &innolux_g070y2_l01_timing, 2310 .num_timings = 1, 2311 .bpc = 6, 2312 .size = { 2313 .width = 152, 2314 .height = 91, 2315 }, 2316 .delay = { 2317 .prepare = 10, 2318 .enable = 100, 2319 .disable = 100, 2320 .unprepare = 800, 2321 }, 2322 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2323 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2324 }; 2325 2326 static const struct display_timing innolux_g101ice_l01_timing = { 2327 .pixelclock = { 60400000, 71100000, 74700000 }, 2328 .hactive = { 1280, 1280, 1280 }, 2329 .hfront_porch = { 41, 80, 100 }, 2330 .hback_porch = { 40, 79, 99 }, 2331 .hsync_len = { 1, 1, 1 }, 2332 .vactive = { 800, 800, 800 }, 2333 .vfront_porch = { 5, 11, 14 }, 2334 .vback_porch = { 4, 11, 14 }, 2335 .vsync_len = { 1, 1, 1 }, 2336 .flags = DISPLAY_FLAGS_DE_HIGH, 2337 }; 2338 2339 static const struct panel_desc innolux_g101ice_l01 = { 2340 .timings = &innolux_g101ice_l01_timing, 2341 .num_timings = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 217, 2345 .height = 135, 2346 }, 2347 .delay = { 2348 .enable = 200, 2349 .disable = 200, 2350 }, 2351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2352 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2353 }; 2354 2355 static const struct display_timing innolux_g121i1_l01_timing = { 2356 .pixelclock = { 67450000, 71000000, 74550000 }, 2357 .hactive = { 1280, 1280, 1280 }, 2358 .hfront_porch = { 40, 80, 160 }, 2359 .hback_porch = { 39, 79, 159 }, 2360 .hsync_len = { 1, 1, 1 }, 2361 .vactive = { 800, 800, 800 }, 2362 .vfront_porch = { 5, 11, 100 }, 2363 .vback_porch = { 4, 11, 99 }, 2364 .vsync_len = { 1, 1, 1 }, 2365 }; 2366 2367 static const struct panel_desc innolux_g121i1_l01 = { 2368 .timings = &innolux_g121i1_l01_timing, 2369 .num_timings = 1, 2370 .bpc = 6, 2371 .size = { 2372 .width = 261, 2373 .height = 163, 2374 }, 2375 .delay = { 2376 .enable = 200, 2377 .disable = 20, 2378 }, 2379 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2380 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2381 }; 2382 2383 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2384 .clock = 65000, 2385 .hdisplay = 1024, 2386 .hsync_start = 1024 + 0, 2387 .hsync_end = 1024 + 1, 2388 .htotal = 1024 + 0 + 1 + 320, 2389 .vdisplay = 768, 2390 .vsync_start = 768 + 38, 2391 .vsync_end = 768 + 38 + 1, 2392 .vtotal = 768 + 38 + 1 + 0, 2393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2394 }; 2395 2396 static const struct panel_desc innolux_g121x1_l03 = { 2397 .modes = &innolux_g121x1_l03_mode, 2398 .num_modes = 1, 2399 .bpc = 6, 2400 .size = { 2401 .width = 246, 2402 .height = 185, 2403 }, 2404 .delay = { 2405 .enable = 200, 2406 .unprepare = 200, 2407 .disable = 400, 2408 }, 2409 }; 2410 2411 static const struct drm_display_mode innolux_n116bca_ea1_mode = { 2412 .clock = 76420, 2413 .hdisplay = 1366, 2414 .hsync_start = 1366 + 136, 2415 .hsync_end = 1366 + 136 + 30, 2416 .htotal = 1366 + 136 + 30 + 60, 2417 .vdisplay = 768, 2418 .vsync_start = 768 + 8, 2419 .vsync_end = 768 + 8 + 12, 2420 .vtotal = 768 + 8 + 12 + 12, 2421 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2422 }; 2423 2424 static const struct panel_desc innolux_n116bca_ea1 = { 2425 .modes = &innolux_n116bca_ea1_mode, 2426 .num_modes = 1, 2427 .bpc = 6, 2428 .size = { 2429 .width = 256, 2430 .height = 144, 2431 }, 2432 .delay = { 2433 .hpd_absent_delay = 200, 2434 .prepare_to_enable = 80, 2435 .unprepare = 500, 2436 }, 2437 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2438 .connector_type = DRM_MODE_CONNECTOR_eDP, 2439 }; 2440 2441 /* 2442 * Datasheet specifies that at 60 Hz refresh rate: 2443 * - total horizontal time: { 1506, 1592, 1716 } 2444 * - total vertical time: { 788, 800, 868 } 2445 * 2446 * ...but doesn't go into exactly how that should be split into a front 2447 * porch, back porch, or sync length. For now we'll leave a single setting 2448 * here which allows a bit of tweaking of the pixel clock at the expense of 2449 * refresh rate. 2450 */ 2451 static const struct display_timing innolux_n116bge_timing = { 2452 .pixelclock = { 72600000, 76420000, 80240000 }, 2453 .hactive = { 1366, 1366, 1366 }, 2454 .hfront_porch = { 136, 136, 136 }, 2455 .hback_porch = { 60, 60, 60 }, 2456 .hsync_len = { 30, 30, 30 }, 2457 .vactive = { 768, 768, 768 }, 2458 .vfront_porch = { 8, 8, 8 }, 2459 .vback_porch = { 12, 12, 12 }, 2460 .vsync_len = { 12, 12, 12 }, 2461 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2462 }; 2463 2464 static const struct panel_desc innolux_n116bge = { 2465 .timings = &innolux_n116bge_timing, 2466 .num_timings = 1, 2467 .bpc = 6, 2468 .size = { 2469 .width = 256, 2470 .height = 144, 2471 }, 2472 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2473 .connector_type = DRM_MODE_CONNECTOR_eDP, 2474 }; 2475 2476 static const struct drm_display_mode innolux_n125hce_gn1_mode = { 2477 .clock = 162000, 2478 .hdisplay = 1920, 2479 .hsync_start = 1920 + 40, 2480 .hsync_end = 1920 + 40 + 40, 2481 .htotal = 1920 + 40 + 40 + 80, 2482 .vdisplay = 1080, 2483 .vsync_start = 1080 + 4, 2484 .vsync_end = 1080 + 4 + 4, 2485 .vtotal = 1080 + 4 + 4 + 24, 2486 }; 2487 2488 static const struct panel_desc innolux_n125hce_gn1 = { 2489 .modes = &innolux_n125hce_gn1_mode, 2490 .num_modes = 1, 2491 .bpc = 8, 2492 .size = { 2493 .width = 276, 2494 .height = 155, 2495 }, 2496 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2497 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2498 .connector_type = DRM_MODE_CONNECTOR_eDP, 2499 }; 2500 2501 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2502 .clock = 69300, 2503 .hdisplay = 1366, 2504 .hsync_start = 1366 + 16, 2505 .hsync_end = 1366 + 16 + 34, 2506 .htotal = 1366 + 16 + 34 + 50, 2507 .vdisplay = 768, 2508 .vsync_start = 768 + 2, 2509 .vsync_end = 768 + 2 + 6, 2510 .vtotal = 768 + 2 + 6 + 12, 2511 }; 2512 2513 static const struct panel_desc innolux_n156bge_l21 = { 2514 .modes = &innolux_n156bge_l21_mode, 2515 .num_modes = 1, 2516 .bpc = 6, 2517 .size = { 2518 .width = 344, 2519 .height = 193, 2520 }, 2521 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2522 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2523 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2524 }; 2525 2526 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2527 .clock = 206016, 2528 .hdisplay = 2160, 2529 .hsync_start = 2160 + 48, 2530 .hsync_end = 2160 + 48 + 32, 2531 .htotal = 2160 + 48 + 32 + 80, 2532 .vdisplay = 1440, 2533 .vsync_start = 1440 + 3, 2534 .vsync_end = 1440 + 3 + 10, 2535 .vtotal = 1440 + 3 + 10 + 27, 2536 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2537 }; 2538 2539 static const struct panel_desc innolux_p120zdg_bf1 = { 2540 .modes = &innolux_p120zdg_bf1_mode, 2541 .num_modes = 1, 2542 .bpc = 8, 2543 .size = { 2544 .width = 254, 2545 .height = 169, 2546 }, 2547 .delay = { 2548 .hpd_absent_delay = 200, 2549 .unprepare = 500, 2550 }, 2551 }; 2552 2553 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2554 .clock = 51501, 2555 .hdisplay = 1024, 2556 .hsync_start = 1024 + 128, 2557 .hsync_end = 1024 + 128 + 64, 2558 .htotal = 1024 + 128 + 64 + 128, 2559 .vdisplay = 600, 2560 .vsync_start = 600 + 16, 2561 .vsync_end = 600 + 16 + 4, 2562 .vtotal = 600 + 16 + 4 + 16, 2563 }; 2564 2565 static const struct panel_desc innolux_zj070na_01p = { 2566 .modes = &innolux_zj070na_01p_mode, 2567 .num_modes = 1, 2568 .bpc = 6, 2569 .size = { 2570 .width = 154, 2571 .height = 90, 2572 }, 2573 }; 2574 2575 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2576 .clock = 138778, 2577 .hdisplay = 1920, 2578 .hsync_start = 1920 + 24, 2579 .hsync_end = 1920 + 24 + 48, 2580 .htotal = 1920 + 24 + 48 + 88, 2581 .vdisplay = 1080, 2582 .vsync_start = 1080 + 3, 2583 .vsync_end = 1080 + 3 + 12, 2584 .vtotal = 1080 + 3 + 12 + 17, 2585 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2586 }; 2587 2588 static const struct panel_desc ivo_m133nwf4_r0 = { 2589 .modes = &ivo_m133nwf4_r0_mode, 2590 .num_modes = 1, 2591 .bpc = 8, 2592 .size = { 2593 .width = 294, 2594 .height = 165, 2595 }, 2596 .delay = { 2597 .hpd_absent_delay = 200, 2598 .unprepare = 500, 2599 }, 2600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2601 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2602 .connector_type = DRM_MODE_CONNECTOR_eDP, 2603 }; 2604 2605 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2606 .clock = 81000, 2607 .hdisplay = 1366, 2608 .hsync_start = 1366 + 40, 2609 .hsync_end = 1366 + 40 + 32, 2610 .htotal = 1366 + 40 + 32 + 62, 2611 .vdisplay = 768, 2612 .vsync_start = 768 + 5, 2613 .vsync_end = 768 + 5 + 5, 2614 .vtotal = 768 + 5 + 5 + 122, 2615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2616 }; 2617 2618 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2619 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2620 .num_modes = 1, 2621 .bpc = 6, 2622 .size = { 2623 .width = 256, 2624 .height = 144, 2625 }, 2626 .delay = { 2627 .hpd_absent_delay = 200, 2628 }, 2629 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2630 .connector_type = DRM_MODE_CONNECTOR_eDP, 2631 }; 2632 2633 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2634 .pixelclock = { 5580000, 5850000, 6200000 }, 2635 .hactive = { 320, 320, 320 }, 2636 .hfront_porch = { 30, 30, 30 }, 2637 .hback_porch = { 30, 30, 30 }, 2638 .hsync_len = { 1, 5, 17 }, 2639 .vactive = { 240, 240, 240 }, 2640 .vfront_porch = { 6, 6, 6 }, 2641 .vback_porch = { 5, 5, 5 }, 2642 .vsync_len = { 1, 2, 11 }, 2643 .flags = DISPLAY_FLAGS_DE_HIGH, 2644 }; 2645 2646 static const struct panel_desc koe_tx14d24vm1bpa = { 2647 .timings = &koe_tx14d24vm1bpa_timing, 2648 .num_timings = 1, 2649 .bpc = 6, 2650 .size = { 2651 .width = 115, 2652 .height = 86, 2653 }, 2654 }; 2655 2656 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2657 .pixelclock = { 151820000, 156720000, 159780000 }, 2658 .hactive = { 1920, 1920, 1920 }, 2659 .hfront_porch = { 105, 130, 142 }, 2660 .hback_porch = { 45, 70, 82 }, 2661 .hsync_len = { 30, 30, 30 }, 2662 .vactive = { 1200, 1200, 1200}, 2663 .vfront_porch = { 3, 5, 10 }, 2664 .vback_porch = { 2, 5, 10 }, 2665 .vsync_len = { 5, 5, 5 }, 2666 }; 2667 2668 static const struct panel_desc koe_tx26d202vm0bwa = { 2669 .timings = &koe_tx26d202vm0bwa_timing, 2670 .num_timings = 1, 2671 .bpc = 8, 2672 .size = { 2673 .width = 217, 2674 .height = 136, 2675 }, 2676 .delay = { 2677 .prepare = 1000, 2678 .enable = 1000, 2679 .unprepare = 1000, 2680 .disable = 1000, 2681 }, 2682 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2683 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2684 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2685 }; 2686 2687 static const struct display_timing koe_tx31d200vm0baa_timing = { 2688 .pixelclock = { 39600000, 43200000, 48000000 }, 2689 .hactive = { 1280, 1280, 1280 }, 2690 .hfront_porch = { 16, 36, 56 }, 2691 .hback_porch = { 16, 36, 56 }, 2692 .hsync_len = { 8, 8, 8 }, 2693 .vactive = { 480, 480, 480 }, 2694 .vfront_porch = { 6, 21, 33 }, 2695 .vback_porch = { 6, 21, 33 }, 2696 .vsync_len = { 8, 8, 8 }, 2697 .flags = DISPLAY_FLAGS_DE_HIGH, 2698 }; 2699 2700 static const struct panel_desc koe_tx31d200vm0baa = { 2701 .timings = &koe_tx31d200vm0baa_timing, 2702 .num_timings = 1, 2703 .bpc = 6, 2704 .size = { 2705 .width = 292, 2706 .height = 109, 2707 }, 2708 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2709 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2710 }; 2711 2712 static const struct display_timing kyo_tcg121xglp_timing = { 2713 .pixelclock = { 52000000, 65000000, 71000000 }, 2714 .hactive = { 1024, 1024, 1024 }, 2715 .hfront_porch = { 2, 2, 2 }, 2716 .hback_porch = { 2, 2, 2 }, 2717 .hsync_len = { 86, 124, 244 }, 2718 .vactive = { 768, 768, 768 }, 2719 .vfront_porch = { 2, 2, 2 }, 2720 .vback_porch = { 2, 2, 2 }, 2721 .vsync_len = { 6, 34, 73 }, 2722 .flags = DISPLAY_FLAGS_DE_HIGH, 2723 }; 2724 2725 static const struct panel_desc kyo_tcg121xglp = { 2726 .timings = &kyo_tcg121xglp_timing, 2727 .num_timings = 1, 2728 .bpc = 8, 2729 .size = { 2730 .width = 246, 2731 .height = 184, 2732 }, 2733 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2734 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2735 }; 2736 2737 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2738 .clock = 7000, 2739 .hdisplay = 320, 2740 .hsync_start = 320 + 20, 2741 .hsync_end = 320 + 20 + 30, 2742 .htotal = 320 + 20 + 30 + 38, 2743 .vdisplay = 240, 2744 .vsync_start = 240 + 4, 2745 .vsync_end = 240 + 4 + 3, 2746 .vtotal = 240 + 4 + 3 + 15, 2747 }; 2748 2749 static const struct panel_desc lemaker_bl035_rgb_002 = { 2750 .modes = &lemaker_bl035_rgb_002_mode, 2751 .num_modes = 1, 2752 .size = { 2753 .width = 70, 2754 .height = 52, 2755 }, 2756 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2757 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2758 }; 2759 2760 static const struct drm_display_mode lg_lb070wv8_mode = { 2761 .clock = 33246, 2762 .hdisplay = 800, 2763 .hsync_start = 800 + 88, 2764 .hsync_end = 800 + 88 + 80, 2765 .htotal = 800 + 88 + 80 + 88, 2766 .vdisplay = 480, 2767 .vsync_start = 480 + 10, 2768 .vsync_end = 480 + 10 + 25, 2769 .vtotal = 480 + 10 + 25 + 10, 2770 }; 2771 2772 static const struct panel_desc lg_lb070wv8 = { 2773 .modes = &lg_lb070wv8_mode, 2774 .num_modes = 1, 2775 .bpc = 8, 2776 .size = { 2777 .width = 151, 2778 .height = 91, 2779 }, 2780 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2781 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2782 }; 2783 2784 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2785 .clock = 200000, 2786 .hdisplay = 1536, 2787 .hsync_start = 1536 + 12, 2788 .hsync_end = 1536 + 12 + 16, 2789 .htotal = 1536 + 12 + 16 + 48, 2790 .vdisplay = 2048, 2791 .vsync_start = 2048 + 8, 2792 .vsync_end = 2048 + 8 + 4, 2793 .vtotal = 2048 + 8 + 4 + 8, 2794 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2795 }; 2796 2797 static const struct panel_desc lg_lp079qx1_sp0v = { 2798 .modes = &lg_lp079qx1_sp0v_mode, 2799 .num_modes = 1, 2800 .size = { 2801 .width = 129, 2802 .height = 171, 2803 }, 2804 }; 2805 2806 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2807 .clock = 205210, 2808 .hdisplay = 2048, 2809 .hsync_start = 2048 + 150, 2810 .hsync_end = 2048 + 150 + 5, 2811 .htotal = 2048 + 150 + 5 + 5, 2812 .vdisplay = 1536, 2813 .vsync_start = 1536 + 3, 2814 .vsync_end = 1536 + 3 + 1, 2815 .vtotal = 1536 + 3 + 1 + 9, 2816 }; 2817 2818 static const struct panel_desc lg_lp097qx1_spa1 = { 2819 .modes = &lg_lp097qx1_spa1_mode, 2820 .num_modes = 1, 2821 .size = { 2822 .width = 208, 2823 .height = 147, 2824 }, 2825 }; 2826 2827 static const struct drm_display_mode lg_lp120up1_mode = { 2828 .clock = 162300, 2829 .hdisplay = 1920, 2830 .hsync_start = 1920 + 40, 2831 .hsync_end = 1920 + 40 + 40, 2832 .htotal = 1920 + 40 + 40+ 80, 2833 .vdisplay = 1280, 2834 .vsync_start = 1280 + 4, 2835 .vsync_end = 1280 + 4 + 4, 2836 .vtotal = 1280 + 4 + 4 + 12, 2837 }; 2838 2839 static const struct panel_desc lg_lp120up1 = { 2840 .modes = &lg_lp120up1_mode, 2841 .num_modes = 1, 2842 .bpc = 8, 2843 .size = { 2844 .width = 267, 2845 .height = 183, 2846 }, 2847 .connector_type = DRM_MODE_CONNECTOR_eDP, 2848 }; 2849 2850 static const struct drm_display_mode lg_lp129qe_mode = { 2851 .clock = 285250, 2852 .hdisplay = 2560, 2853 .hsync_start = 2560 + 48, 2854 .hsync_end = 2560 + 48 + 32, 2855 .htotal = 2560 + 48 + 32 + 80, 2856 .vdisplay = 1700, 2857 .vsync_start = 1700 + 3, 2858 .vsync_end = 1700 + 3 + 10, 2859 .vtotal = 1700 + 3 + 10 + 36, 2860 }; 2861 2862 static const struct panel_desc lg_lp129qe = { 2863 .modes = &lg_lp129qe_mode, 2864 .num_modes = 1, 2865 .bpc = 8, 2866 .size = { 2867 .width = 272, 2868 .height = 181, 2869 }, 2870 }; 2871 2872 static const struct display_timing logictechno_lt161010_2nh_timing = { 2873 .pixelclock = { 26400000, 33300000, 46800000 }, 2874 .hactive = { 800, 800, 800 }, 2875 .hfront_porch = { 16, 210, 354 }, 2876 .hback_porch = { 46, 46, 46 }, 2877 .hsync_len = { 1, 20, 40 }, 2878 .vactive = { 480, 480, 480 }, 2879 .vfront_porch = { 7, 22, 147 }, 2880 .vback_porch = { 23, 23, 23 }, 2881 .vsync_len = { 1, 10, 20 }, 2882 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2883 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2884 DISPLAY_FLAGS_SYNC_POSEDGE, 2885 }; 2886 2887 static const struct panel_desc logictechno_lt161010_2nh = { 2888 .timings = &logictechno_lt161010_2nh_timing, 2889 .num_timings = 1, 2890 .size = { 2891 .width = 154, 2892 .height = 86, 2893 }, 2894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2898 .connector_type = DRM_MODE_CONNECTOR_DPI, 2899 }; 2900 2901 static const struct display_timing logictechno_lt170410_2whc_timing = { 2902 .pixelclock = { 68900000, 71100000, 73400000 }, 2903 .hactive = { 1280, 1280, 1280 }, 2904 .hfront_porch = { 23, 60, 71 }, 2905 .hback_porch = { 23, 60, 71 }, 2906 .hsync_len = { 15, 40, 47 }, 2907 .vactive = { 800, 800, 800 }, 2908 .vfront_porch = { 5, 7, 10 }, 2909 .vback_porch = { 5, 7, 10 }, 2910 .vsync_len = { 6, 9, 12 }, 2911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2913 DISPLAY_FLAGS_SYNC_POSEDGE, 2914 }; 2915 2916 static const struct panel_desc logictechno_lt170410_2whc = { 2917 .timings = &logictechno_lt170410_2whc_timing, 2918 .num_timings = 1, 2919 .size = { 2920 .width = 217, 2921 .height = 136, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2924 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2925 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2926 }; 2927 2928 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2929 .clock = 30400, 2930 .hdisplay = 800, 2931 .hsync_start = 800 + 0, 2932 .hsync_end = 800 + 1, 2933 .htotal = 800 + 0 + 1 + 160, 2934 .vdisplay = 480, 2935 .vsync_start = 480 + 0, 2936 .vsync_end = 480 + 48 + 1, 2937 .vtotal = 480 + 48 + 1 + 0, 2938 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2939 }; 2940 2941 static const struct drm_display_mode logicpd_type_28_mode = { 2942 .clock = 9107, 2943 .hdisplay = 480, 2944 .hsync_start = 480 + 3, 2945 .hsync_end = 480 + 3 + 42, 2946 .htotal = 480 + 3 + 42 + 2, 2947 2948 .vdisplay = 272, 2949 .vsync_start = 272 + 2, 2950 .vsync_end = 272 + 2 + 11, 2951 .vtotal = 272 + 2 + 11 + 3, 2952 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2953 }; 2954 2955 static const struct panel_desc logicpd_type_28 = { 2956 .modes = &logicpd_type_28_mode, 2957 .num_modes = 1, 2958 .bpc = 8, 2959 .size = { 2960 .width = 105, 2961 .height = 67, 2962 }, 2963 .delay = { 2964 .prepare = 200, 2965 .enable = 200, 2966 .unprepare = 200, 2967 .disable = 200, 2968 }, 2969 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2970 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2971 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2972 .connector_type = DRM_MODE_CONNECTOR_DPI, 2973 }; 2974 2975 static const struct panel_desc mitsubishi_aa070mc01 = { 2976 .modes = &mitsubishi_aa070mc01_mode, 2977 .num_modes = 1, 2978 .bpc = 8, 2979 .size = { 2980 .width = 152, 2981 .height = 91, 2982 }, 2983 2984 .delay = { 2985 .enable = 200, 2986 .unprepare = 200, 2987 .disable = 400, 2988 }, 2989 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2990 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2991 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2992 }; 2993 2994 static const struct display_timing nec_nl12880bc20_05_timing = { 2995 .pixelclock = { 67000000, 71000000, 75000000 }, 2996 .hactive = { 1280, 1280, 1280 }, 2997 .hfront_porch = { 2, 30, 30 }, 2998 .hback_porch = { 6, 100, 100 }, 2999 .hsync_len = { 2, 30, 30 }, 3000 .vactive = { 800, 800, 800 }, 3001 .vfront_porch = { 5, 5, 5 }, 3002 .vback_porch = { 11, 11, 11 }, 3003 .vsync_len = { 7, 7, 7 }, 3004 }; 3005 3006 static const struct panel_desc nec_nl12880bc20_05 = { 3007 .timings = &nec_nl12880bc20_05_timing, 3008 .num_timings = 1, 3009 .bpc = 8, 3010 .size = { 3011 .width = 261, 3012 .height = 163, 3013 }, 3014 .delay = { 3015 .enable = 50, 3016 .disable = 50, 3017 }, 3018 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3019 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3020 }; 3021 3022 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3023 .clock = 10870, 3024 .hdisplay = 480, 3025 .hsync_start = 480 + 2, 3026 .hsync_end = 480 + 2 + 41, 3027 .htotal = 480 + 2 + 41 + 2, 3028 .vdisplay = 272, 3029 .vsync_start = 272 + 2, 3030 .vsync_end = 272 + 2 + 4, 3031 .vtotal = 272 + 2 + 4 + 2, 3032 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3033 }; 3034 3035 static const struct panel_desc nec_nl4827hc19_05b = { 3036 .modes = &nec_nl4827hc19_05b_mode, 3037 .num_modes = 1, 3038 .bpc = 8, 3039 .size = { 3040 .width = 95, 3041 .height = 54, 3042 }, 3043 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3044 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3045 }; 3046 3047 static const struct drm_display_mode netron_dy_e231732_mode = { 3048 .clock = 66000, 3049 .hdisplay = 1024, 3050 .hsync_start = 1024 + 160, 3051 .hsync_end = 1024 + 160 + 70, 3052 .htotal = 1024 + 160 + 70 + 90, 3053 .vdisplay = 600, 3054 .vsync_start = 600 + 127, 3055 .vsync_end = 600 + 127 + 20, 3056 .vtotal = 600 + 127 + 20 + 3, 3057 }; 3058 3059 static const struct panel_desc netron_dy_e231732 = { 3060 .modes = &netron_dy_e231732_mode, 3061 .num_modes = 1, 3062 .size = { 3063 .width = 154, 3064 .height = 87, 3065 }, 3066 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3067 }; 3068 3069 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 3070 { 3071 .clock = 138500, 3072 .hdisplay = 1920, 3073 .hsync_start = 1920 + 48, 3074 .hsync_end = 1920 + 48 + 32, 3075 .htotal = 1920 + 48 + 32 + 80, 3076 .vdisplay = 1080, 3077 .vsync_start = 1080 + 3, 3078 .vsync_end = 1080 + 3 + 5, 3079 .vtotal = 1080 + 3 + 5 + 23, 3080 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3081 }, { 3082 .clock = 110920, 3083 .hdisplay = 1920, 3084 .hsync_start = 1920 + 48, 3085 .hsync_end = 1920 + 48 + 32, 3086 .htotal = 1920 + 48 + 32 + 80, 3087 .vdisplay = 1080, 3088 .vsync_start = 1080 + 3, 3089 .vsync_end = 1080 + 3 + 5, 3090 .vtotal = 1080 + 3 + 5 + 23, 3091 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3092 } 3093 }; 3094 3095 static const struct panel_desc neweast_wjfh116008a = { 3096 .modes = neweast_wjfh116008a_modes, 3097 .num_modes = 2, 3098 .bpc = 6, 3099 .size = { 3100 .width = 260, 3101 .height = 150, 3102 }, 3103 .delay = { 3104 .prepare = 110, 3105 .enable = 20, 3106 .unprepare = 500, 3107 }, 3108 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3109 .connector_type = DRM_MODE_CONNECTOR_eDP, 3110 }; 3111 3112 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3113 .clock = 9000, 3114 .hdisplay = 480, 3115 .hsync_start = 480 + 2, 3116 .hsync_end = 480 + 2 + 41, 3117 .htotal = 480 + 2 + 41 + 2, 3118 .vdisplay = 272, 3119 .vsync_start = 272 + 2, 3120 .vsync_end = 272 + 2 + 10, 3121 .vtotal = 272 + 2 + 10 + 2, 3122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3123 }; 3124 3125 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3126 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3127 .num_modes = 1, 3128 .bpc = 8, 3129 .size = { 3130 .width = 95, 3131 .height = 54, 3132 }, 3133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3135 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3136 .connector_type = DRM_MODE_CONNECTOR_DPI, 3137 }; 3138 3139 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3140 .pixelclock = { 130000000, 148350000, 163000000 }, 3141 .hactive = { 1920, 1920, 1920 }, 3142 .hfront_porch = { 80, 100, 100 }, 3143 .hback_porch = { 100, 120, 120 }, 3144 .hsync_len = { 50, 60, 60 }, 3145 .vactive = { 1080, 1080, 1080 }, 3146 .vfront_porch = { 12, 30, 30 }, 3147 .vback_porch = { 4, 10, 10 }, 3148 .vsync_len = { 4, 5, 5 }, 3149 }; 3150 3151 static const struct panel_desc nlt_nl192108ac18_02d = { 3152 .timings = &nlt_nl192108ac18_02d_timing, 3153 .num_timings = 1, 3154 .bpc = 8, 3155 .size = { 3156 .width = 344, 3157 .height = 194, 3158 }, 3159 .delay = { 3160 .unprepare = 500, 3161 }, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3164 }; 3165 3166 static const struct drm_display_mode nvd_9128_mode = { 3167 .clock = 29500, 3168 .hdisplay = 800, 3169 .hsync_start = 800 + 130, 3170 .hsync_end = 800 + 130 + 98, 3171 .htotal = 800 + 0 + 130 + 98, 3172 .vdisplay = 480, 3173 .vsync_start = 480 + 10, 3174 .vsync_end = 480 + 10 + 50, 3175 .vtotal = 480 + 0 + 10 + 50, 3176 }; 3177 3178 static const struct panel_desc nvd_9128 = { 3179 .modes = &nvd_9128_mode, 3180 .num_modes = 1, 3181 .bpc = 8, 3182 .size = { 3183 .width = 156, 3184 .height = 88, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3187 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3188 }; 3189 3190 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3191 .pixelclock = { 30000000, 30000000, 40000000 }, 3192 .hactive = { 800, 800, 800 }, 3193 .hfront_porch = { 40, 40, 40 }, 3194 .hback_porch = { 40, 40, 40 }, 3195 .hsync_len = { 1, 48, 48 }, 3196 .vactive = { 480, 480, 480 }, 3197 .vfront_porch = { 13, 13, 13 }, 3198 .vback_porch = { 29, 29, 29 }, 3199 .vsync_len = { 3, 3, 3 }, 3200 .flags = DISPLAY_FLAGS_DE_HIGH, 3201 }; 3202 3203 static const struct panel_desc okaya_rs800480t_7x0gp = { 3204 .timings = &okaya_rs800480t_7x0gp_timing, 3205 .num_timings = 1, 3206 .bpc = 6, 3207 .size = { 3208 .width = 154, 3209 .height = 87, 3210 }, 3211 .delay = { 3212 .prepare = 41, 3213 .enable = 50, 3214 .unprepare = 41, 3215 .disable = 50, 3216 }, 3217 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3218 }; 3219 3220 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3221 .clock = 9000, 3222 .hdisplay = 480, 3223 .hsync_start = 480 + 5, 3224 .hsync_end = 480 + 5 + 30, 3225 .htotal = 480 + 5 + 30 + 10, 3226 .vdisplay = 272, 3227 .vsync_start = 272 + 8, 3228 .vsync_end = 272 + 8 + 5, 3229 .vtotal = 272 + 8 + 5 + 3, 3230 }; 3231 3232 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3233 .modes = &olimex_lcd_olinuxino_43ts_mode, 3234 .num_modes = 1, 3235 .size = { 3236 .width = 95, 3237 .height = 54, 3238 }, 3239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3240 }; 3241 3242 /* 3243 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3244 * pixel clocks, but this is the timing that was being used in the Adafruit 3245 * installation instructions. 3246 */ 3247 static const struct drm_display_mode ontat_yx700wv03_mode = { 3248 .clock = 29500, 3249 .hdisplay = 800, 3250 .hsync_start = 824, 3251 .hsync_end = 896, 3252 .htotal = 992, 3253 .vdisplay = 480, 3254 .vsync_start = 483, 3255 .vsync_end = 493, 3256 .vtotal = 500, 3257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3258 }; 3259 3260 /* 3261 * Specification at: 3262 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3263 */ 3264 static const struct panel_desc ontat_yx700wv03 = { 3265 .modes = &ontat_yx700wv03_mode, 3266 .num_modes = 1, 3267 .bpc = 8, 3268 .size = { 3269 .width = 154, 3270 .height = 83, 3271 }, 3272 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3273 }; 3274 3275 static const struct drm_display_mode ortustech_com37h3m_mode = { 3276 .clock = 22230, 3277 .hdisplay = 480, 3278 .hsync_start = 480 + 40, 3279 .hsync_end = 480 + 40 + 10, 3280 .htotal = 480 + 40 + 10 + 40, 3281 .vdisplay = 640, 3282 .vsync_start = 640 + 4, 3283 .vsync_end = 640 + 4 + 2, 3284 .vtotal = 640 + 4 + 2 + 4, 3285 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3286 }; 3287 3288 static const struct panel_desc ortustech_com37h3m = { 3289 .modes = &ortustech_com37h3m_mode, 3290 .num_modes = 1, 3291 .bpc = 8, 3292 .size = { 3293 .width = 56, /* 56.16mm */ 3294 .height = 75, /* 74.88mm */ 3295 }, 3296 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3297 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3298 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3299 }; 3300 3301 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3302 .clock = 25000, 3303 .hdisplay = 480, 3304 .hsync_start = 480 + 10, 3305 .hsync_end = 480 + 10 + 10, 3306 .htotal = 480 + 10 + 10 + 15, 3307 .vdisplay = 800, 3308 .vsync_start = 800 + 3, 3309 .vsync_end = 800 + 3 + 3, 3310 .vtotal = 800 + 3 + 3 + 3, 3311 }; 3312 3313 static const struct panel_desc ortustech_com43h4m85ulc = { 3314 .modes = &ortustech_com43h4m85ulc_mode, 3315 .num_modes = 1, 3316 .bpc = 6, 3317 .size = { 3318 .width = 56, 3319 .height = 93, 3320 }, 3321 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3322 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3323 .connector_type = DRM_MODE_CONNECTOR_DPI, 3324 }; 3325 3326 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3327 .clock = 33000, 3328 .hdisplay = 800, 3329 .hsync_start = 800 + 210, 3330 .hsync_end = 800 + 210 + 30, 3331 .htotal = 800 + 210 + 30 + 16, 3332 .vdisplay = 480, 3333 .vsync_start = 480 + 22, 3334 .vsync_end = 480 + 22 + 13, 3335 .vtotal = 480 + 22 + 13 + 10, 3336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3337 }; 3338 3339 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3340 .modes = &osddisplays_osd070t1718_19ts_mode, 3341 .num_modes = 1, 3342 .bpc = 8, 3343 .size = { 3344 .width = 152, 3345 .height = 91, 3346 }, 3347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3348 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3349 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3350 .connector_type = DRM_MODE_CONNECTOR_DPI, 3351 }; 3352 3353 static const struct drm_display_mode pda_91_00156_a0_mode = { 3354 .clock = 33300, 3355 .hdisplay = 800, 3356 .hsync_start = 800 + 1, 3357 .hsync_end = 800 + 1 + 64, 3358 .htotal = 800 + 1 + 64 + 64, 3359 .vdisplay = 480, 3360 .vsync_start = 480 + 1, 3361 .vsync_end = 480 + 1 + 23, 3362 .vtotal = 480 + 1 + 23 + 22, 3363 }; 3364 3365 static const struct panel_desc pda_91_00156_a0 = { 3366 .modes = &pda_91_00156_a0_mode, 3367 .num_modes = 1, 3368 .size = { 3369 .width = 152, 3370 .height = 91, 3371 }, 3372 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3373 }; 3374 3375 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3376 .clock = 24750, 3377 .hdisplay = 800, 3378 .hsync_start = 800 + 54, 3379 .hsync_end = 800 + 54 + 2, 3380 .htotal = 800 + 54 + 2 + 44, 3381 .vdisplay = 480, 3382 .vsync_start = 480 + 49, 3383 .vsync_end = 480 + 49 + 2, 3384 .vtotal = 480 + 49 + 2 + 22, 3385 }; 3386 3387 static const struct panel_desc powertip_ph800480t013_idf02 = { 3388 .modes = &powertip_ph800480t013_idf02_mode, 3389 .num_modes = 1, 3390 .size = { 3391 .width = 152, 3392 .height = 91, 3393 }, 3394 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3395 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3396 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3398 .connector_type = DRM_MODE_CONNECTOR_DPI, 3399 }; 3400 3401 static const struct drm_display_mode qd43003c0_40_mode = { 3402 .clock = 9000, 3403 .hdisplay = 480, 3404 .hsync_start = 480 + 8, 3405 .hsync_end = 480 + 8 + 4, 3406 .htotal = 480 + 8 + 4 + 39, 3407 .vdisplay = 272, 3408 .vsync_start = 272 + 4, 3409 .vsync_end = 272 + 4 + 10, 3410 .vtotal = 272 + 4 + 10 + 2, 3411 }; 3412 3413 static const struct panel_desc qd43003c0_40 = { 3414 .modes = &qd43003c0_40_mode, 3415 .num_modes = 1, 3416 .bpc = 8, 3417 .size = { 3418 .width = 95, 3419 .height = 53, 3420 }, 3421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3422 }; 3423 3424 static const struct display_timing rocktech_rk070er9427_timing = { 3425 .pixelclock = { 26400000, 33300000, 46800000 }, 3426 .hactive = { 800, 800, 800 }, 3427 .hfront_porch = { 16, 210, 354 }, 3428 .hback_porch = { 46, 46, 46 }, 3429 .hsync_len = { 1, 1, 1 }, 3430 .vactive = { 480, 480, 480 }, 3431 .vfront_porch = { 7, 22, 147 }, 3432 .vback_porch = { 23, 23, 23 }, 3433 .vsync_len = { 1, 1, 1 }, 3434 .flags = DISPLAY_FLAGS_DE_HIGH, 3435 }; 3436 3437 static const struct panel_desc rocktech_rk070er9427 = { 3438 .timings = &rocktech_rk070er9427_timing, 3439 .num_timings = 1, 3440 .bpc = 6, 3441 .size = { 3442 .width = 154, 3443 .height = 86, 3444 }, 3445 .delay = { 3446 .prepare = 41, 3447 .enable = 50, 3448 .unprepare = 41, 3449 .disable = 50, 3450 }, 3451 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3452 }; 3453 3454 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3455 .clock = 71100, 3456 .hdisplay = 1280, 3457 .hsync_start = 1280 + 48, 3458 .hsync_end = 1280 + 48 + 32, 3459 .htotal = 1280 + 48 + 32 + 80, 3460 .vdisplay = 800, 3461 .vsync_start = 800 + 2, 3462 .vsync_end = 800 + 2 + 5, 3463 .vtotal = 800 + 2 + 5 + 16, 3464 }; 3465 3466 static const struct panel_desc rocktech_rk101ii01d_ct = { 3467 .modes = &rocktech_rk101ii01d_ct_mode, 3468 .num_modes = 1, 3469 .size = { 3470 .width = 217, 3471 .height = 136, 3472 }, 3473 .delay = { 3474 .prepare = 50, 3475 .disable = 50, 3476 }, 3477 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3478 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3480 }; 3481 3482 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3483 .clock = 271560, 3484 .hdisplay = 2560, 3485 .hsync_start = 2560 + 48, 3486 .hsync_end = 2560 + 48 + 32, 3487 .htotal = 2560 + 48 + 32 + 80, 3488 .vdisplay = 1600, 3489 .vsync_start = 1600 + 2, 3490 .vsync_end = 1600 + 2 + 5, 3491 .vtotal = 1600 + 2 + 5 + 57, 3492 }; 3493 3494 static const struct panel_desc samsung_lsn122dl01_c01 = { 3495 .modes = &samsung_lsn122dl01_c01_mode, 3496 .num_modes = 1, 3497 .size = { 3498 .width = 263, 3499 .height = 164, 3500 }, 3501 }; 3502 3503 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3504 .clock = 54030, 3505 .hdisplay = 1024, 3506 .hsync_start = 1024 + 24, 3507 .hsync_end = 1024 + 24 + 136, 3508 .htotal = 1024 + 24 + 136 + 160, 3509 .vdisplay = 600, 3510 .vsync_start = 600 + 3, 3511 .vsync_end = 600 + 3 + 6, 3512 .vtotal = 600 + 3 + 6 + 61, 3513 }; 3514 3515 static const struct panel_desc samsung_ltn101nt05 = { 3516 .modes = &samsung_ltn101nt05_mode, 3517 .num_modes = 1, 3518 .bpc = 6, 3519 .size = { 3520 .width = 223, 3521 .height = 125, 3522 }, 3523 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3524 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3525 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3526 }; 3527 3528 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3529 .clock = 76300, 3530 .hdisplay = 1366, 3531 .hsync_start = 1366 + 64, 3532 .hsync_end = 1366 + 64 + 48, 3533 .htotal = 1366 + 64 + 48 + 128, 3534 .vdisplay = 768, 3535 .vsync_start = 768 + 2, 3536 .vsync_end = 768 + 2 + 5, 3537 .vtotal = 768 + 2 + 5 + 17, 3538 }; 3539 3540 static const struct panel_desc samsung_ltn140at29_301 = { 3541 .modes = &samsung_ltn140at29_301_mode, 3542 .num_modes = 1, 3543 .bpc = 6, 3544 .size = { 3545 .width = 320, 3546 .height = 187, 3547 }, 3548 }; 3549 3550 static const struct display_timing satoz_sat050at40h12r2_timing = { 3551 .pixelclock = {33300000, 33300000, 50000000}, 3552 .hactive = {800, 800, 800}, 3553 .hfront_porch = {16, 210, 354}, 3554 .hback_porch = {46, 46, 46}, 3555 .hsync_len = {1, 1, 40}, 3556 .vactive = {480, 480, 480}, 3557 .vfront_porch = {7, 22, 147}, 3558 .vback_porch = {23, 23, 23}, 3559 .vsync_len = {1, 1, 20}, 3560 }; 3561 3562 static const struct panel_desc satoz_sat050at40h12r2 = { 3563 .timings = &satoz_sat050at40h12r2_timing, 3564 .num_timings = 1, 3565 .bpc = 8, 3566 .size = { 3567 .width = 108, 3568 .height = 65, 3569 }, 3570 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3571 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3572 }; 3573 3574 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3575 .clock = 168480, 3576 .hdisplay = 1920, 3577 .hsync_start = 1920 + 48, 3578 .hsync_end = 1920 + 48 + 32, 3579 .htotal = 1920 + 48 + 32 + 80, 3580 .vdisplay = 1280, 3581 .vsync_start = 1280 + 3, 3582 .vsync_end = 1280 + 3 + 10, 3583 .vtotal = 1280 + 3 + 10 + 57, 3584 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3585 }; 3586 3587 static const struct panel_desc sharp_ld_d5116z01b = { 3588 .modes = &sharp_ld_d5116z01b_mode, 3589 .num_modes = 1, 3590 .bpc = 8, 3591 .size = { 3592 .width = 260, 3593 .height = 120, 3594 }, 3595 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3596 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3597 }; 3598 3599 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3600 .clock = 33260, 3601 .hdisplay = 800, 3602 .hsync_start = 800 + 64, 3603 .hsync_end = 800 + 64 + 128, 3604 .htotal = 800 + 64 + 128 + 64, 3605 .vdisplay = 480, 3606 .vsync_start = 480 + 8, 3607 .vsync_end = 480 + 8 + 2, 3608 .vtotal = 480 + 8 + 2 + 35, 3609 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3610 }; 3611 3612 static const struct panel_desc sharp_lq070y3dg3b = { 3613 .modes = &sharp_lq070y3dg3b_mode, 3614 .num_modes = 1, 3615 .bpc = 8, 3616 .size = { 3617 .width = 152, /* 152.4mm */ 3618 .height = 91, /* 91.4mm */ 3619 }, 3620 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3621 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3622 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3623 }; 3624 3625 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3626 .clock = 5500, 3627 .hdisplay = 240, 3628 .hsync_start = 240 + 16, 3629 .hsync_end = 240 + 16 + 7, 3630 .htotal = 240 + 16 + 7 + 5, 3631 .vdisplay = 320, 3632 .vsync_start = 320 + 9, 3633 .vsync_end = 320 + 9 + 1, 3634 .vtotal = 320 + 9 + 1 + 7, 3635 }; 3636 3637 static const struct panel_desc sharp_lq035q7db03 = { 3638 .modes = &sharp_lq035q7db03_mode, 3639 .num_modes = 1, 3640 .bpc = 6, 3641 .size = { 3642 .width = 54, 3643 .height = 72, 3644 }, 3645 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3646 }; 3647 3648 static const struct display_timing sharp_lq101k1ly04_timing = { 3649 .pixelclock = { 60000000, 65000000, 80000000 }, 3650 .hactive = { 1280, 1280, 1280 }, 3651 .hfront_porch = { 20, 20, 20 }, 3652 .hback_porch = { 20, 20, 20 }, 3653 .hsync_len = { 10, 10, 10 }, 3654 .vactive = { 800, 800, 800 }, 3655 .vfront_porch = { 4, 4, 4 }, 3656 .vback_porch = { 4, 4, 4 }, 3657 .vsync_len = { 4, 4, 4 }, 3658 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3659 }; 3660 3661 static const struct panel_desc sharp_lq101k1ly04 = { 3662 .timings = &sharp_lq101k1ly04_timing, 3663 .num_timings = 1, 3664 .bpc = 8, 3665 .size = { 3666 .width = 217, 3667 .height = 136, 3668 }, 3669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3670 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3671 }; 3672 3673 static const struct display_timing sharp_lq123p1jx31_timing = { 3674 .pixelclock = { 252750000, 252750000, 266604720 }, 3675 .hactive = { 2400, 2400, 2400 }, 3676 .hfront_porch = { 48, 48, 48 }, 3677 .hback_porch = { 80, 80, 84 }, 3678 .hsync_len = { 32, 32, 32 }, 3679 .vactive = { 1600, 1600, 1600 }, 3680 .vfront_porch = { 3, 3, 3 }, 3681 .vback_porch = { 33, 33, 120 }, 3682 .vsync_len = { 10, 10, 10 }, 3683 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3684 }; 3685 3686 static const struct panel_desc sharp_lq123p1jx31 = { 3687 .timings = &sharp_lq123p1jx31_timing, 3688 .num_timings = 1, 3689 .bpc = 8, 3690 .size = { 3691 .width = 259, 3692 .height = 173, 3693 }, 3694 .delay = { 3695 .prepare = 110, 3696 .enable = 50, 3697 .unprepare = 550, 3698 }, 3699 }; 3700 3701 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3702 { /* 50 Hz */ 3703 .clock = 3000, 3704 .hdisplay = 240, 3705 .hsync_start = 240 + 58, 3706 .hsync_end = 240 + 58 + 1, 3707 .htotal = 240 + 58 + 1 + 1, 3708 .vdisplay = 160, 3709 .vsync_start = 160 + 24, 3710 .vsync_end = 160 + 24 + 10, 3711 .vtotal = 160 + 24 + 10 + 6, 3712 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3713 }, 3714 { /* 60 Hz */ 3715 .clock = 3000, 3716 .hdisplay = 240, 3717 .hsync_start = 240 + 8, 3718 .hsync_end = 240 + 8 + 1, 3719 .htotal = 240 + 8 + 1 + 1, 3720 .vdisplay = 160, 3721 .vsync_start = 160 + 24, 3722 .vsync_end = 160 + 24 + 10, 3723 .vtotal = 160 + 24 + 10 + 6, 3724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3725 }, 3726 }; 3727 3728 static const struct panel_desc sharp_ls020b1dd01d = { 3729 .modes = sharp_ls020b1dd01d_modes, 3730 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3731 .bpc = 6, 3732 .size = { 3733 .width = 42, 3734 .height = 28, 3735 }, 3736 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3737 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3738 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3739 | DRM_BUS_FLAG_SHARP_SIGNALS, 3740 }; 3741 3742 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3743 .clock = 33300, 3744 .hdisplay = 800, 3745 .hsync_start = 800 + 1, 3746 .hsync_end = 800 + 1 + 64, 3747 .htotal = 800 + 1 + 64 + 64, 3748 .vdisplay = 480, 3749 .vsync_start = 480 + 1, 3750 .vsync_end = 480 + 1 + 23, 3751 .vtotal = 480 + 1 + 23 + 22, 3752 }; 3753 3754 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3755 .modes = &shelly_sca07010_bfn_lnn_mode, 3756 .num_modes = 1, 3757 .size = { 3758 .width = 152, 3759 .height = 91, 3760 }, 3761 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3762 }; 3763 3764 static const struct drm_display_mode starry_kr070pe2t_mode = { 3765 .clock = 33000, 3766 .hdisplay = 800, 3767 .hsync_start = 800 + 209, 3768 .hsync_end = 800 + 209 + 1, 3769 .htotal = 800 + 209 + 1 + 45, 3770 .vdisplay = 480, 3771 .vsync_start = 480 + 22, 3772 .vsync_end = 480 + 22 + 1, 3773 .vtotal = 480 + 22 + 1 + 22, 3774 }; 3775 3776 static const struct panel_desc starry_kr070pe2t = { 3777 .modes = &starry_kr070pe2t_mode, 3778 .num_modes = 1, 3779 .bpc = 8, 3780 .size = { 3781 .width = 152, 3782 .height = 86, 3783 }, 3784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3785 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3786 .connector_type = DRM_MODE_CONNECTOR_DPI, 3787 }; 3788 3789 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3790 .clock = 147000, 3791 .hdisplay = 1920, 3792 .hsync_start = 1920 + 16, 3793 .hsync_end = 1920 + 16 + 16, 3794 .htotal = 1920 + 16 + 16 + 32, 3795 .vdisplay = 1200, 3796 .vsync_start = 1200 + 15, 3797 .vsync_end = 1200 + 15 + 2, 3798 .vtotal = 1200 + 15 + 2 + 18, 3799 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3800 }; 3801 3802 static const struct panel_desc starry_kr122ea0sra = { 3803 .modes = &starry_kr122ea0sra_mode, 3804 .num_modes = 1, 3805 .size = { 3806 .width = 263, 3807 .height = 164, 3808 }, 3809 .delay = { 3810 .prepare = 10 + 200, 3811 .enable = 50, 3812 .unprepare = 10 + 500, 3813 }, 3814 }; 3815 3816 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3817 .clock = 30000, 3818 .hdisplay = 800, 3819 .hsync_start = 800 + 39, 3820 .hsync_end = 800 + 39 + 47, 3821 .htotal = 800 + 39 + 47 + 39, 3822 .vdisplay = 480, 3823 .vsync_start = 480 + 13, 3824 .vsync_end = 480 + 13 + 2, 3825 .vtotal = 480 + 13 + 2 + 29, 3826 }; 3827 3828 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3829 .modes = &tfc_s9700rtwv43tr_01b_mode, 3830 .num_modes = 1, 3831 .bpc = 8, 3832 .size = { 3833 .width = 155, 3834 .height = 90, 3835 }, 3836 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3838 }; 3839 3840 static const struct display_timing tianma_tm070jdhg30_timing = { 3841 .pixelclock = { 62600000, 68200000, 78100000 }, 3842 .hactive = { 1280, 1280, 1280 }, 3843 .hfront_porch = { 15, 64, 159 }, 3844 .hback_porch = { 5, 5, 5 }, 3845 .hsync_len = { 1, 1, 256 }, 3846 .vactive = { 800, 800, 800 }, 3847 .vfront_porch = { 3, 40, 99 }, 3848 .vback_porch = { 2, 2, 2 }, 3849 .vsync_len = { 1, 1, 128 }, 3850 .flags = DISPLAY_FLAGS_DE_HIGH, 3851 }; 3852 3853 static const struct panel_desc tianma_tm070jdhg30 = { 3854 .timings = &tianma_tm070jdhg30_timing, 3855 .num_timings = 1, 3856 .bpc = 8, 3857 .size = { 3858 .width = 151, 3859 .height = 95, 3860 }, 3861 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3862 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3863 }; 3864 3865 static const struct panel_desc tianma_tm070jvhg33 = { 3866 .timings = &tianma_tm070jdhg30_timing, 3867 .num_timings = 1, 3868 .bpc = 8, 3869 .size = { 3870 .width = 150, 3871 .height = 94, 3872 }, 3873 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3874 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3875 }; 3876 3877 static const struct display_timing tianma_tm070rvhg71_timing = { 3878 .pixelclock = { 27700000, 29200000, 39600000 }, 3879 .hactive = { 800, 800, 800 }, 3880 .hfront_porch = { 12, 40, 212 }, 3881 .hback_porch = { 88, 88, 88 }, 3882 .hsync_len = { 1, 1, 40 }, 3883 .vactive = { 480, 480, 480 }, 3884 .vfront_porch = { 1, 13, 88 }, 3885 .vback_porch = { 32, 32, 32 }, 3886 .vsync_len = { 1, 1, 3 }, 3887 .flags = DISPLAY_FLAGS_DE_HIGH, 3888 }; 3889 3890 static const struct panel_desc tianma_tm070rvhg71 = { 3891 .timings = &tianma_tm070rvhg71_timing, 3892 .num_timings = 1, 3893 .bpc = 8, 3894 .size = { 3895 .width = 154, 3896 .height = 86, 3897 }, 3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3899 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3900 }; 3901 3902 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3903 { 3904 .clock = 10000, 3905 .hdisplay = 320, 3906 .hsync_start = 320 + 50, 3907 .hsync_end = 320 + 50 + 6, 3908 .htotal = 320 + 50 + 6 + 38, 3909 .vdisplay = 240, 3910 .vsync_start = 240 + 3, 3911 .vsync_end = 240 + 3 + 1, 3912 .vtotal = 240 + 3 + 1 + 17, 3913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3914 }, 3915 }; 3916 3917 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3918 .modes = ti_nspire_cx_lcd_mode, 3919 .num_modes = 1, 3920 .bpc = 8, 3921 .size = { 3922 .width = 65, 3923 .height = 49, 3924 }, 3925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3926 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3927 }; 3928 3929 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3930 { 3931 .clock = 10000, 3932 .hdisplay = 320, 3933 .hsync_start = 320 + 6, 3934 .hsync_end = 320 + 6 + 6, 3935 .htotal = 320 + 6 + 6 + 6, 3936 .vdisplay = 240, 3937 .vsync_start = 240 + 0, 3938 .vsync_end = 240 + 0 + 1, 3939 .vtotal = 240 + 0 + 1 + 0, 3940 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3941 }, 3942 }; 3943 3944 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3945 .modes = ti_nspire_classic_lcd_mode, 3946 .num_modes = 1, 3947 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3948 .bpc = 8, 3949 .size = { 3950 .width = 71, 3951 .height = 53, 3952 }, 3953 /* This is the grayscale bus format */ 3954 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3955 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3956 }; 3957 3958 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3959 .clock = 79500, 3960 .hdisplay = 1280, 3961 .hsync_start = 1280 + 192, 3962 .hsync_end = 1280 + 192 + 128, 3963 .htotal = 1280 + 192 + 128 + 64, 3964 .vdisplay = 768, 3965 .vsync_start = 768 + 20, 3966 .vsync_end = 768 + 20 + 7, 3967 .vtotal = 768 + 20 + 7 + 3, 3968 }; 3969 3970 static const struct panel_desc toshiba_lt089ac29000 = { 3971 .modes = &toshiba_lt089ac29000_mode, 3972 .num_modes = 1, 3973 .size = { 3974 .width = 194, 3975 .height = 116, 3976 }, 3977 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3980 }; 3981 3982 static const struct drm_display_mode tpk_f07a_0102_mode = { 3983 .clock = 33260, 3984 .hdisplay = 800, 3985 .hsync_start = 800 + 40, 3986 .hsync_end = 800 + 40 + 128, 3987 .htotal = 800 + 40 + 128 + 88, 3988 .vdisplay = 480, 3989 .vsync_start = 480 + 10, 3990 .vsync_end = 480 + 10 + 2, 3991 .vtotal = 480 + 10 + 2 + 33, 3992 }; 3993 3994 static const struct panel_desc tpk_f07a_0102 = { 3995 .modes = &tpk_f07a_0102_mode, 3996 .num_modes = 1, 3997 .size = { 3998 .width = 152, 3999 .height = 91, 4000 }, 4001 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4002 }; 4003 4004 static const struct drm_display_mode tpk_f10a_0102_mode = { 4005 .clock = 45000, 4006 .hdisplay = 1024, 4007 .hsync_start = 1024 + 176, 4008 .hsync_end = 1024 + 176 + 5, 4009 .htotal = 1024 + 176 + 5 + 88, 4010 .vdisplay = 600, 4011 .vsync_start = 600 + 20, 4012 .vsync_end = 600 + 20 + 5, 4013 .vtotal = 600 + 20 + 5 + 25, 4014 }; 4015 4016 static const struct panel_desc tpk_f10a_0102 = { 4017 .modes = &tpk_f10a_0102_mode, 4018 .num_modes = 1, 4019 .size = { 4020 .width = 223, 4021 .height = 125, 4022 }, 4023 }; 4024 4025 static const struct display_timing urt_umsh_8596md_timing = { 4026 .pixelclock = { 33260000, 33260000, 33260000 }, 4027 .hactive = { 800, 800, 800 }, 4028 .hfront_porch = { 41, 41, 41 }, 4029 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4030 .hsync_len = { 71, 128, 128 }, 4031 .vactive = { 480, 480, 480 }, 4032 .vfront_porch = { 10, 10, 10 }, 4033 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4034 .vsync_len = { 2, 2, 2 }, 4035 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4036 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4037 }; 4038 4039 static const struct panel_desc urt_umsh_8596md_lvds = { 4040 .timings = &urt_umsh_8596md_timing, 4041 .num_timings = 1, 4042 .bpc = 6, 4043 .size = { 4044 .width = 152, 4045 .height = 91, 4046 }, 4047 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4048 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4049 }; 4050 4051 static const struct panel_desc urt_umsh_8596md_parallel = { 4052 .timings = &urt_umsh_8596md_timing, 4053 .num_timings = 1, 4054 .bpc = 6, 4055 .size = { 4056 .width = 152, 4057 .height = 91, 4058 }, 4059 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4060 }; 4061 4062 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4063 .clock = 33333, 4064 .hdisplay = 800, 4065 .hsync_start = 800 + 210, 4066 .hsync_end = 800 + 210 + 20, 4067 .htotal = 800 + 210 + 20 + 46, 4068 .vdisplay = 480, 4069 .vsync_start = 480 + 22, 4070 .vsync_end = 480 + 22 + 10, 4071 .vtotal = 480 + 22 + 10 + 23, 4072 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4073 }; 4074 4075 static const struct panel_desc vl050_8048nt_c01 = { 4076 .modes = &vl050_8048nt_c01_mode, 4077 .num_modes = 1, 4078 .bpc = 8, 4079 .size = { 4080 .width = 120, 4081 .height = 76, 4082 }, 4083 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4084 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4085 }; 4086 4087 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4088 .clock = 6410, 4089 .hdisplay = 320, 4090 .hsync_start = 320 + 20, 4091 .hsync_end = 320 + 20 + 30, 4092 .htotal = 320 + 20 + 30 + 38, 4093 .vdisplay = 240, 4094 .vsync_start = 240 + 4, 4095 .vsync_end = 240 + 4 + 3, 4096 .vtotal = 240 + 4 + 3 + 15, 4097 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4098 }; 4099 4100 static const struct panel_desc winstar_wf35ltiacd = { 4101 .modes = &winstar_wf35ltiacd_mode, 4102 .num_modes = 1, 4103 .bpc = 8, 4104 .size = { 4105 .width = 70, 4106 .height = 53, 4107 }, 4108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4109 }; 4110 4111 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4112 .clock = 51200, 4113 .hdisplay = 1024, 4114 .hsync_start = 1024 + 100, 4115 .hsync_end = 1024 + 100 + 100, 4116 .htotal = 1024 + 100 + 100 + 120, 4117 .vdisplay = 600, 4118 .vsync_start = 600 + 10, 4119 .vsync_end = 600 + 10 + 10, 4120 .vtotal = 600 + 10 + 10 + 15, 4121 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4122 }; 4123 4124 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4125 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4126 .num_modes = 1, 4127 .bpc = 6, 4128 .size = { 4129 .width = 154, 4130 .height = 90, 4131 }, 4132 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4135 }; 4136 4137 static const struct drm_display_mode arm_rtsm_mode[] = { 4138 { 4139 .clock = 65000, 4140 .hdisplay = 1024, 4141 .hsync_start = 1024 + 24, 4142 .hsync_end = 1024 + 24 + 136, 4143 .htotal = 1024 + 24 + 136 + 160, 4144 .vdisplay = 768, 4145 .vsync_start = 768 + 3, 4146 .vsync_end = 768 + 3 + 6, 4147 .vtotal = 768 + 3 + 6 + 29, 4148 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4149 }, 4150 }; 4151 4152 static const struct panel_desc arm_rtsm = { 4153 .modes = arm_rtsm_mode, 4154 .num_modes = 1, 4155 .bpc = 8, 4156 .size = { 4157 .width = 400, 4158 .height = 300, 4159 }, 4160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4161 }; 4162 4163 static const struct of_device_id platform_of_match[] = { 4164 { 4165 .compatible = "ampire,am-1280800n3tzqw-t00h", 4166 .data = &ire_am_1280800n3tzqw_t00h, 4167 }, { 4168 .compatible = "ampire,am-480272h3tmqw-t01h", 4169 .data = &ire_am_480272h3tmqw_t01h, 4170 }, { 4171 .compatible = "ampire,am800480r3tmqwa1h", 4172 .data = &ire_am800480r3tmqwa1h, 4173 }, { 4174 .compatible = "arm,rtsm-display", 4175 .data = &arm_rtsm, 4176 }, { 4177 .compatible = "armadeus,st0700-adapt", 4178 .data = &armadeus_st0700_adapt, 4179 }, { 4180 .compatible = "auo,b101aw03", 4181 .data = &auo_b101aw03, 4182 }, { 4183 .compatible = "auo,b101ean01", 4184 .data = &auo_b101ean01, 4185 }, { 4186 .compatible = "auo,b101xtn01", 4187 .data = &auo_b101xtn01, 4188 }, { 4189 .compatible = "auo,b116xa01", 4190 .data = &auo_b116xak01, 4191 }, { 4192 .compatible = "auo,b116xw03", 4193 .data = &auo_b116xw03, 4194 }, { 4195 .compatible = "auo,b133htn01", 4196 .data = &auo_b133htn01, 4197 }, { 4198 .compatible = "auo,b133xtn01", 4199 .data = &auo_b133xtn01, 4200 }, { 4201 .compatible = "auo,g070vvn01", 4202 .data = &auo_g070vvn01, 4203 }, { 4204 .compatible = "auo,g101evn010", 4205 .data = &auo_g101evn010, 4206 }, { 4207 .compatible = "auo,g104sn02", 4208 .data = &auo_g104sn02, 4209 }, { 4210 .compatible = "auo,g121ean01", 4211 .data = &auo_g121ean01, 4212 }, { 4213 .compatible = "auo,g133han01", 4214 .data = &auo_g133han01, 4215 }, { 4216 .compatible = "auo,g156xtn01", 4217 .data = &auo_g156xtn01, 4218 }, { 4219 .compatible = "auo,g185han01", 4220 .data = &auo_g185han01, 4221 }, { 4222 .compatible = "auo,g190ean01", 4223 .data = &auo_g190ean01, 4224 }, { 4225 .compatible = "auo,p320hvn03", 4226 .data = &auo_p320hvn03, 4227 }, { 4228 .compatible = "auo,t215hvn01", 4229 .data = &auo_t215hvn01, 4230 }, { 4231 .compatible = "avic,tm070ddh03", 4232 .data = &avic_tm070ddh03, 4233 }, { 4234 .compatible = "bananapi,s070wv20-ct16", 4235 .data = &bananapi_s070wv20_ct16, 4236 }, { 4237 .compatible = "boe,hv070wsa-100", 4238 .data = &boe_hv070wsa 4239 }, { 4240 .compatible = "boe,nv101wxmn51", 4241 .data = &boe_nv101wxmn51, 4242 }, { 4243 .compatible = "boe,nv110wtm-n61", 4244 .data = &boe_nv110wtm_n61, 4245 }, { 4246 .compatible = "boe,nv133fhm-n61", 4247 .data = &boe_nv133fhm_n61, 4248 }, { 4249 .compatible = "boe,nv133fhm-n62", 4250 .data = &boe_nv133fhm_n61, 4251 }, { 4252 .compatible = "boe,nv140fhmn49", 4253 .data = &boe_nv140fhmn49, 4254 }, { 4255 .compatible = "cdtech,s043wq26h-ct7", 4256 .data = &cdtech_s043wq26h_ct7, 4257 }, { 4258 .compatible = "cdtech,s070pws19hp-fc21", 4259 .data = &cdtech_s070pws19hp_fc21, 4260 }, { 4261 .compatible = "cdtech,s070swv29hg-dc44", 4262 .data = &cdtech_s070swv29hg_dc44, 4263 }, { 4264 .compatible = "cdtech,s070wv95-ct16", 4265 .data = &cdtech_s070wv95_ct16, 4266 }, { 4267 .compatible = "chefree,ch101olhlwh-002", 4268 .data = &chefree_ch101olhlwh_002, 4269 }, { 4270 .compatible = "chunghwa,claa070wp03xg", 4271 .data = &chunghwa_claa070wp03xg, 4272 }, { 4273 .compatible = "chunghwa,claa101wa01a", 4274 .data = &chunghwa_claa101wa01a 4275 }, { 4276 .compatible = "chunghwa,claa101wb01", 4277 .data = &chunghwa_claa101wb01 4278 }, { 4279 .compatible = "dataimage,scf0700c48ggu18", 4280 .data = &dataimage_scf0700c48ggu18, 4281 }, { 4282 .compatible = "dlc,dlc0700yzg-1", 4283 .data = &dlc_dlc0700yzg_1, 4284 }, { 4285 .compatible = "dlc,dlc1010gig", 4286 .data = &dlc_dlc1010gig, 4287 }, { 4288 .compatible = "edt,et035012dm6", 4289 .data = &edt_et035012dm6, 4290 }, { 4291 .compatible = "edt,etm043080dh6gp", 4292 .data = &edt_etm043080dh6gp, 4293 }, { 4294 .compatible = "edt,etm0430g0dh6", 4295 .data = &edt_etm0430g0dh6, 4296 }, { 4297 .compatible = "edt,et057090dhu", 4298 .data = &edt_et057090dhu, 4299 }, { 4300 .compatible = "edt,et070080dh6", 4301 .data = &edt_etm0700g0dh6, 4302 }, { 4303 .compatible = "edt,etm0700g0dh6", 4304 .data = &edt_etm0700g0dh6, 4305 }, { 4306 .compatible = "edt,etm0700g0bdh6", 4307 .data = &edt_etm0700g0bdh6, 4308 }, { 4309 .compatible = "edt,etm0700g0edh6", 4310 .data = &edt_etm0700g0bdh6, 4311 }, { 4312 .compatible = "evervision,vgg804821", 4313 .data = &evervision_vgg804821, 4314 }, { 4315 .compatible = "foxlink,fl500wvr00-a0t", 4316 .data = &foxlink_fl500wvr00_a0t, 4317 }, { 4318 .compatible = "frida,frd350h54004", 4319 .data = &frida_frd350h54004, 4320 }, { 4321 .compatible = "friendlyarm,hd702e", 4322 .data = &friendlyarm_hd702e, 4323 }, { 4324 .compatible = "giantplus,gpg482739qs5", 4325 .data = &giantplus_gpg482739qs5 4326 }, { 4327 .compatible = "giantplus,gpm940b0", 4328 .data = &giantplus_gpm940b0, 4329 }, { 4330 .compatible = "hannstar,hsd070pww1", 4331 .data = &hannstar_hsd070pww1, 4332 }, { 4333 .compatible = "hannstar,hsd100pxn1", 4334 .data = &hannstar_hsd100pxn1, 4335 }, { 4336 .compatible = "hit,tx23d38vm0caa", 4337 .data = &hitachi_tx23d38vm0caa 4338 }, { 4339 .compatible = "innolux,at043tn24", 4340 .data = &innolux_at043tn24, 4341 }, { 4342 .compatible = "innolux,at070tn92", 4343 .data = &innolux_at070tn92, 4344 }, { 4345 .compatible = "innolux,g070y2-l01", 4346 .data = &innolux_g070y2_l01, 4347 }, { 4348 .compatible = "innolux,g101ice-l01", 4349 .data = &innolux_g101ice_l01 4350 }, { 4351 .compatible = "innolux,g121i1-l01", 4352 .data = &innolux_g121i1_l01 4353 }, { 4354 .compatible = "innolux,g121x1-l03", 4355 .data = &innolux_g121x1_l03, 4356 }, { 4357 .compatible = "innolux,n116bca-ea1", 4358 .data = &innolux_n116bca_ea1, 4359 }, { 4360 .compatible = "innolux,n116bge", 4361 .data = &innolux_n116bge, 4362 }, { 4363 .compatible = "innolux,n125hce-gn1", 4364 .data = &innolux_n125hce_gn1, 4365 }, { 4366 .compatible = "innolux,n156bge-l21", 4367 .data = &innolux_n156bge_l21, 4368 }, { 4369 .compatible = "innolux,p120zdg-bf1", 4370 .data = &innolux_p120zdg_bf1, 4371 }, { 4372 .compatible = "innolux,zj070na-01p", 4373 .data = &innolux_zj070na_01p, 4374 }, { 4375 .compatible = "ivo,m133nwf4-r0", 4376 .data = &ivo_m133nwf4_r0, 4377 }, { 4378 .compatible = "kingdisplay,kd116n21-30nv-a010", 4379 .data = &kingdisplay_kd116n21_30nv_a010, 4380 }, { 4381 .compatible = "koe,tx14d24vm1bpa", 4382 .data = &koe_tx14d24vm1bpa, 4383 }, { 4384 .compatible = "koe,tx26d202vm0bwa", 4385 .data = &koe_tx26d202vm0bwa, 4386 }, { 4387 .compatible = "koe,tx31d200vm0baa", 4388 .data = &koe_tx31d200vm0baa, 4389 }, { 4390 .compatible = "kyo,tcg121xglp", 4391 .data = &kyo_tcg121xglp, 4392 }, { 4393 .compatible = "lemaker,bl035-rgb-002", 4394 .data = &lemaker_bl035_rgb_002, 4395 }, { 4396 .compatible = "lg,lb070wv8", 4397 .data = &lg_lb070wv8, 4398 }, { 4399 .compatible = "lg,lp079qx1-sp0v", 4400 .data = &lg_lp079qx1_sp0v, 4401 }, { 4402 .compatible = "lg,lp097qx1-spa1", 4403 .data = &lg_lp097qx1_spa1, 4404 }, { 4405 .compatible = "lg,lp120up1", 4406 .data = &lg_lp120up1, 4407 }, { 4408 .compatible = "lg,lp129qe", 4409 .data = &lg_lp129qe, 4410 }, { 4411 .compatible = "logicpd,type28", 4412 .data = &logicpd_type_28, 4413 }, { 4414 .compatible = "logictechno,lt161010-2nhc", 4415 .data = &logictechno_lt161010_2nh, 4416 }, { 4417 .compatible = "logictechno,lt161010-2nhr", 4418 .data = &logictechno_lt161010_2nh, 4419 }, { 4420 .compatible = "logictechno,lt170410-2whc", 4421 .data = &logictechno_lt170410_2whc, 4422 }, { 4423 .compatible = "mitsubishi,aa070mc01-ca1", 4424 .data = &mitsubishi_aa070mc01, 4425 }, { 4426 .compatible = "nec,nl12880bc20-05", 4427 .data = &nec_nl12880bc20_05, 4428 }, { 4429 .compatible = "nec,nl4827hc19-05b", 4430 .data = &nec_nl4827hc19_05b, 4431 }, { 4432 .compatible = "netron-dy,e231732", 4433 .data = &netron_dy_e231732, 4434 }, { 4435 .compatible = "neweast,wjfh116008a", 4436 .data = &neweast_wjfh116008a, 4437 }, { 4438 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4439 .data = &newhaven_nhd_43_480272ef_atxl, 4440 }, { 4441 .compatible = "nlt,nl192108ac18-02d", 4442 .data = &nlt_nl192108ac18_02d, 4443 }, { 4444 .compatible = "nvd,9128", 4445 .data = &nvd_9128, 4446 }, { 4447 .compatible = "okaya,rs800480t-7x0gp", 4448 .data = &okaya_rs800480t_7x0gp, 4449 }, { 4450 .compatible = "olimex,lcd-olinuxino-43-ts", 4451 .data = &olimex_lcd_olinuxino_43ts, 4452 }, { 4453 .compatible = "ontat,yx700wv03", 4454 .data = &ontat_yx700wv03, 4455 }, { 4456 .compatible = "ortustech,com37h3m05dtc", 4457 .data = &ortustech_com37h3m, 4458 }, { 4459 .compatible = "ortustech,com37h3m99dtc", 4460 .data = &ortustech_com37h3m, 4461 }, { 4462 .compatible = "ortustech,com43h4m85ulc", 4463 .data = &ortustech_com43h4m85ulc, 4464 }, { 4465 .compatible = "osddisplays,osd070t1718-19ts", 4466 .data = &osddisplays_osd070t1718_19ts, 4467 }, { 4468 .compatible = "pda,91-00156-a0", 4469 .data = &pda_91_00156_a0, 4470 }, { 4471 .compatible = "powertip,ph800480t013-idf02", 4472 .data = &powertip_ph800480t013_idf02, 4473 }, { 4474 .compatible = "qiaodian,qd43003c0-40", 4475 .data = &qd43003c0_40, 4476 }, { 4477 .compatible = "rocktech,rk070er9427", 4478 .data = &rocktech_rk070er9427, 4479 }, { 4480 .compatible = "rocktech,rk101ii01d-ct", 4481 .data = &rocktech_rk101ii01d_ct, 4482 }, { 4483 .compatible = "samsung,lsn122dl01-c01", 4484 .data = &samsung_lsn122dl01_c01, 4485 }, { 4486 .compatible = "samsung,ltn101nt05", 4487 .data = &samsung_ltn101nt05, 4488 }, { 4489 .compatible = "samsung,ltn140at29-301", 4490 .data = &samsung_ltn140at29_301, 4491 }, { 4492 .compatible = "satoz,sat050at40h12r2", 4493 .data = &satoz_sat050at40h12r2, 4494 }, { 4495 .compatible = "sharp,ld-d5116z01b", 4496 .data = &sharp_ld_d5116z01b, 4497 }, { 4498 .compatible = "sharp,lq035q7db03", 4499 .data = &sharp_lq035q7db03, 4500 }, { 4501 .compatible = "sharp,lq070y3dg3b", 4502 .data = &sharp_lq070y3dg3b, 4503 }, { 4504 .compatible = "sharp,lq101k1ly04", 4505 .data = &sharp_lq101k1ly04, 4506 }, { 4507 .compatible = "sharp,lq123p1jx31", 4508 .data = &sharp_lq123p1jx31, 4509 }, { 4510 .compatible = "sharp,ls020b1dd01d", 4511 .data = &sharp_ls020b1dd01d, 4512 }, { 4513 .compatible = "shelly,sca07010-bfn-lnn", 4514 .data = &shelly_sca07010_bfn_lnn, 4515 }, { 4516 .compatible = "starry,kr070pe2t", 4517 .data = &starry_kr070pe2t, 4518 }, { 4519 .compatible = "starry,kr122ea0sra", 4520 .data = &starry_kr122ea0sra, 4521 }, { 4522 .compatible = "tfc,s9700rtwv43tr-01b", 4523 .data = &tfc_s9700rtwv43tr_01b, 4524 }, { 4525 .compatible = "tianma,tm070jdhg30", 4526 .data = &tianma_tm070jdhg30, 4527 }, { 4528 .compatible = "tianma,tm070jvhg33", 4529 .data = &tianma_tm070jvhg33, 4530 }, { 4531 .compatible = "tianma,tm070rvhg71", 4532 .data = &tianma_tm070rvhg71, 4533 }, { 4534 .compatible = "ti,nspire-cx-lcd-panel", 4535 .data = &ti_nspire_cx_lcd_panel, 4536 }, { 4537 .compatible = "ti,nspire-classic-lcd-panel", 4538 .data = &ti_nspire_classic_lcd_panel, 4539 }, { 4540 .compatible = "toshiba,lt089ac29000", 4541 .data = &toshiba_lt089ac29000, 4542 }, { 4543 .compatible = "tpk,f07a-0102", 4544 .data = &tpk_f07a_0102, 4545 }, { 4546 .compatible = "tpk,f10a-0102", 4547 .data = &tpk_f10a_0102, 4548 }, { 4549 .compatible = "urt,umsh-8596md-t", 4550 .data = &urt_umsh_8596md_parallel, 4551 }, { 4552 .compatible = "urt,umsh-8596md-1t", 4553 .data = &urt_umsh_8596md_parallel, 4554 }, { 4555 .compatible = "urt,umsh-8596md-7t", 4556 .data = &urt_umsh_8596md_parallel, 4557 }, { 4558 .compatible = "urt,umsh-8596md-11t", 4559 .data = &urt_umsh_8596md_lvds, 4560 }, { 4561 .compatible = "urt,umsh-8596md-19t", 4562 .data = &urt_umsh_8596md_lvds, 4563 }, { 4564 .compatible = "urt,umsh-8596md-20t", 4565 .data = &urt_umsh_8596md_parallel, 4566 }, { 4567 .compatible = "vxt,vl050-8048nt-c01", 4568 .data = &vl050_8048nt_c01, 4569 }, { 4570 .compatible = "winstar,wf35ltiacd", 4571 .data = &winstar_wf35ltiacd, 4572 }, { 4573 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4574 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4575 }, { 4576 /* Must be the last entry */ 4577 .compatible = "panel-dpi", 4578 .data = &panel_dpi, 4579 }, { 4580 /* sentinel */ 4581 } 4582 }; 4583 MODULE_DEVICE_TABLE(of, platform_of_match); 4584 4585 static int panel_simple_platform_probe(struct platform_device *pdev) 4586 { 4587 const struct of_device_id *id; 4588 4589 id = of_match_node(platform_of_match, pdev->dev.of_node); 4590 if (!id) 4591 return -ENODEV; 4592 4593 return panel_simple_probe(&pdev->dev, id->data); 4594 } 4595 4596 static int panel_simple_platform_remove(struct platform_device *pdev) 4597 { 4598 return panel_simple_remove(&pdev->dev); 4599 } 4600 4601 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4602 { 4603 panel_simple_shutdown(&pdev->dev); 4604 } 4605 4606 static struct platform_driver panel_simple_platform_driver = { 4607 .driver = { 4608 .name = "panel-simple", 4609 .of_match_table = platform_of_match, 4610 }, 4611 .probe = panel_simple_platform_probe, 4612 .remove = panel_simple_platform_remove, 4613 .shutdown = panel_simple_platform_shutdown, 4614 }; 4615 4616 struct panel_desc_dsi { 4617 struct panel_desc desc; 4618 4619 unsigned long flags; 4620 enum mipi_dsi_pixel_format format; 4621 unsigned int lanes; 4622 }; 4623 4624 static const struct drm_display_mode auo_b080uan01_mode = { 4625 .clock = 154500, 4626 .hdisplay = 1200, 4627 .hsync_start = 1200 + 62, 4628 .hsync_end = 1200 + 62 + 4, 4629 .htotal = 1200 + 62 + 4 + 62, 4630 .vdisplay = 1920, 4631 .vsync_start = 1920 + 9, 4632 .vsync_end = 1920 + 9 + 2, 4633 .vtotal = 1920 + 9 + 2 + 8, 4634 }; 4635 4636 static const struct panel_desc_dsi auo_b080uan01 = { 4637 .desc = { 4638 .modes = &auo_b080uan01_mode, 4639 .num_modes = 1, 4640 .bpc = 8, 4641 .size = { 4642 .width = 108, 4643 .height = 272, 4644 }, 4645 .connector_type = DRM_MODE_CONNECTOR_DSI, 4646 }, 4647 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4648 .format = MIPI_DSI_FMT_RGB888, 4649 .lanes = 4, 4650 }; 4651 4652 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4653 .clock = 160000, 4654 .hdisplay = 1200, 4655 .hsync_start = 1200 + 120, 4656 .hsync_end = 1200 + 120 + 20, 4657 .htotal = 1200 + 120 + 20 + 21, 4658 .vdisplay = 1920, 4659 .vsync_start = 1920 + 21, 4660 .vsync_end = 1920 + 21 + 3, 4661 .vtotal = 1920 + 21 + 3 + 18, 4662 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4663 }; 4664 4665 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4666 .desc = { 4667 .modes = &boe_tv080wum_nl0_mode, 4668 .num_modes = 1, 4669 .size = { 4670 .width = 107, 4671 .height = 172, 4672 }, 4673 .connector_type = DRM_MODE_CONNECTOR_DSI, 4674 }, 4675 .flags = MIPI_DSI_MODE_VIDEO | 4676 MIPI_DSI_MODE_VIDEO_BURST | 4677 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4678 .format = MIPI_DSI_FMT_RGB888, 4679 .lanes = 4, 4680 }; 4681 4682 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4683 .clock = 71000, 4684 .hdisplay = 800, 4685 .hsync_start = 800 + 32, 4686 .hsync_end = 800 + 32 + 1, 4687 .htotal = 800 + 32 + 1 + 57, 4688 .vdisplay = 1280, 4689 .vsync_start = 1280 + 28, 4690 .vsync_end = 1280 + 28 + 1, 4691 .vtotal = 1280 + 28 + 1 + 14, 4692 }; 4693 4694 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4695 .desc = { 4696 .modes = &lg_ld070wx3_sl01_mode, 4697 .num_modes = 1, 4698 .bpc = 8, 4699 .size = { 4700 .width = 94, 4701 .height = 151, 4702 }, 4703 .connector_type = DRM_MODE_CONNECTOR_DSI, 4704 }, 4705 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4706 .format = MIPI_DSI_FMT_RGB888, 4707 .lanes = 4, 4708 }; 4709 4710 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4711 .clock = 67000, 4712 .hdisplay = 720, 4713 .hsync_start = 720 + 12, 4714 .hsync_end = 720 + 12 + 4, 4715 .htotal = 720 + 12 + 4 + 112, 4716 .vdisplay = 1280, 4717 .vsync_start = 1280 + 8, 4718 .vsync_end = 1280 + 8 + 4, 4719 .vtotal = 1280 + 8 + 4 + 12, 4720 }; 4721 4722 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4723 .desc = { 4724 .modes = &lg_lh500wx1_sd03_mode, 4725 .num_modes = 1, 4726 .bpc = 8, 4727 .size = { 4728 .width = 62, 4729 .height = 110, 4730 }, 4731 .connector_type = DRM_MODE_CONNECTOR_DSI, 4732 }, 4733 .flags = MIPI_DSI_MODE_VIDEO, 4734 .format = MIPI_DSI_FMT_RGB888, 4735 .lanes = 4, 4736 }; 4737 4738 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4739 .clock = 157200, 4740 .hdisplay = 1920, 4741 .hsync_start = 1920 + 154, 4742 .hsync_end = 1920 + 154 + 16, 4743 .htotal = 1920 + 154 + 16 + 32, 4744 .vdisplay = 1200, 4745 .vsync_start = 1200 + 17, 4746 .vsync_end = 1200 + 17 + 2, 4747 .vtotal = 1200 + 17 + 2 + 16, 4748 }; 4749 4750 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4751 .desc = { 4752 .modes = &panasonic_vvx10f004b00_mode, 4753 .num_modes = 1, 4754 .bpc = 8, 4755 .size = { 4756 .width = 217, 4757 .height = 136, 4758 }, 4759 .connector_type = DRM_MODE_CONNECTOR_DSI, 4760 }, 4761 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4762 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4763 .format = MIPI_DSI_FMT_RGB888, 4764 .lanes = 4, 4765 }; 4766 4767 static const struct drm_display_mode lg_acx467akm_7_mode = { 4768 .clock = 150000, 4769 .hdisplay = 1080, 4770 .hsync_start = 1080 + 2, 4771 .hsync_end = 1080 + 2 + 2, 4772 .htotal = 1080 + 2 + 2 + 2, 4773 .vdisplay = 1920, 4774 .vsync_start = 1920 + 2, 4775 .vsync_end = 1920 + 2 + 2, 4776 .vtotal = 1920 + 2 + 2 + 2, 4777 }; 4778 4779 static const struct panel_desc_dsi lg_acx467akm_7 = { 4780 .desc = { 4781 .modes = &lg_acx467akm_7_mode, 4782 .num_modes = 1, 4783 .bpc = 8, 4784 .size = { 4785 .width = 62, 4786 .height = 110, 4787 }, 4788 .connector_type = DRM_MODE_CONNECTOR_DSI, 4789 }, 4790 .flags = 0, 4791 .format = MIPI_DSI_FMT_RGB888, 4792 .lanes = 4, 4793 }; 4794 4795 static const struct drm_display_mode osd101t2045_53ts_mode = { 4796 .clock = 154500, 4797 .hdisplay = 1920, 4798 .hsync_start = 1920 + 112, 4799 .hsync_end = 1920 + 112 + 16, 4800 .htotal = 1920 + 112 + 16 + 32, 4801 .vdisplay = 1200, 4802 .vsync_start = 1200 + 16, 4803 .vsync_end = 1200 + 16 + 2, 4804 .vtotal = 1200 + 16 + 2 + 16, 4805 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4806 }; 4807 4808 static const struct panel_desc_dsi osd101t2045_53ts = { 4809 .desc = { 4810 .modes = &osd101t2045_53ts_mode, 4811 .num_modes = 1, 4812 .bpc = 8, 4813 .size = { 4814 .width = 217, 4815 .height = 136, 4816 }, 4817 .connector_type = DRM_MODE_CONNECTOR_DSI, 4818 }, 4819 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4820 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4821 MIPI_DSI_MODE_EOT_PACKET, 4822 .format = MIPI_DSI_FMT_RGB888, 4823 .lanes = 4, 4824 }; 4825 4826 static const struct of_device_id dsi_of_match[] = { 4827 { 4828 .compatible = "auo,b080uan01", 4829 .data = &auo_b080uan01 4830 }, { 4831 .compatible = "boe,tv080wum-nl0", 4832 .data = &boe_tv080wum_nl0 4833 }, { 4834 .compatible = "lg,ld070wx3-sl01", 4835 .data = &lg_ld070wx3_sl01 4836 }, { 4837 .compatible = "lg,lh500wx1-sd03", 4838 .data = &lg_lh500wx1_sd03 4839 }, { 4840 .compatible = "panasonic,vvx10f004b00", 4841 .data = &panasonic_vvx10f004b00 4842 }, { 4843 .compatible = "lg,acx467akm-7", 4844 .data = &lg_acx467akm_7 4845 }, { 4846 .compatible = "osddisplays,osd101t2045-53ts", 4847 .data = &osd101t2045_53ts 4848 }, { 4849 /* sentinel */ 4850 } 4851 }; 4852 MODULE_DEVICE_TABLE(of, dsi_of_match); 4853 4854 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4855 { 4856 const struct panel_desc_dsi *desc; 4857 const struct of_device_id *id; 4858 int err; 4859 4860 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4861 if (!id) 4862 return -ENODEV; 4863 4864 desc = id->data; 4865 4866 err = panel_simple_probe(&dsi->dev, &desc->desc); 4867 if (err < 0) 4868 return err; 4869 4870 dsi->mode_flags = desc->flags; 4871 dsi->format = desc->format; 4872 dsi->lanes = desc->lanes; 4873 4874 err = mipi_dsi_attach(dsi); 4875 if (err) { 4876 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4877 4878 drm_panel_remove(&panel->base); 4879 } 4880 4881 return err; 4882 } 4883 4884 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4885 { 4886 int err; 4887 4888 err = mipi_dsi_detach(dsi); 4889 if (err < 0) 4890 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4891 4892 return panel_simple_remove(&dsi->dev); 4893 } 4894 4895 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4896 { 4897 panel_simple_shutdown(&dsi->dev); 4898 } 4899 4900 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4901 .driver = { 4902 .name = "panel-simple-dsi", 4903 .of_match_table = dsi_of_match, 4904 }, 4905 .probe = panel_simple_dsi_probe, 4906 .remove = panel_simple_dsi_remove, 4907 .shutdown = panel_simple_dsi_shutdown, 4908 }; 4909 4910 static int __init panel_simple_init(void) 4911 { 4912 int err; 4913 4914 err = platform_driver_register(&panel_simple_platform_driver); 4915 if (err < 0) 4916 return err; 4917 4918 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4919 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4920 if (err < 0) { 4921 platform_driver_unregister(&panel_simple_platform_driver); 4922 return err; 4923 } 4924 } 4925 4926 return 0; 4927 } 4928 module_init(panel_simple_init); 4929 4930 static void __exit panel_simple_exit(void) 4931 { 4932 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4933 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4934 4935 platform_driver_unregister(&panel_simple_platform_driver); 4936 } 4937 module_exit(panel_simple_exit); 4938 4939 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4940 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4941 MODULE_LICENSE("GPL and additional rights"); 4942