1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_modes == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 if (p->enable_gpio) 191 gpiod_set_value_cansleep(p->enable_gpio, 0); 192 193 regulator_disable(p->supply); 194 195 if (p->desc->delay.unprepare) 196 msleep(p->desc->delay.unprepare); 197 198 p->prepared = false; 199 200 return 0; 201 } 202 203 static int panel_simple_prepare(struct drm_panel *panel) 204 { 205 struct panel_simple *p = to_panel_simple(panel); 206 int err; 207 208 if (p->prepared) 209 return 0; 210 211 err = regulator_enable(p->supply); 212 if (err < 0) { 213 dev_err(panel->dev, "failed to enable supply: %d\n", err); 214 return err; 215 } 216 217 if (p->enable_gpio) 218 gpiod_set_value_cansleep(p->enable_gpio, 1); 219 220 if (p->desc->delay.prepare) 221 msleep(p->desc->delay.prepare); 222 223 p->prepared = true; 224 225 return 0; 226 } 227 228 static int panel_simple_enable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (p->enabled) 233 return 0; 234 235 if (p->desc->delay.enable) 236 msleep(p->desc->delay.enable); 237 238 if (p->backlight) { 239 p->backlight->props.state &= ~BL_CORE_FBBLANK; 240 p->backlight->props.power = FB_BLANK_UNBLANK; 241 backlight_update_status(p->backlight); 242 } 243 244 p->enabled = true; 245 246 return 0; 247 } 248 249 static int panel_simple_get_modes(struct drm_panel *panel) 250 { 251 struct panel_simple *p = to_panel_simple(panel); 252 int num = 0; 253 254 /* probe EDID if a DDC bus is available */ 255 if (p->ddc) { 256 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 257 drm_mode_connector_update_edid_property(panel->connector, edid); 258 if (edid) { 259 num += drm_add_edid_modes(panel->connector, edid); 260 kfree(edid); 261 } 262 } 263 264 /* add hard-coded panel modes */ 265 num += panel_simple_get_fixed_modes(p); 266 267 return num; 268 } 269 270 static int panel_simple_get_timings(struct drm_panel *panel, 271 unsigned int num_timings, 272 struct display_timing *timings) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int i; 276 277 if (p->desc->num_timings < num_timings) 278 num_timings = p->desc->num_timings; 279 280 if (timings) 281 for (i = 0; i < num_timings; i++) 282 timings[i] = p->desc->timings[i]; 283 284 return p->desc->num_timings; 285 } 286 287 static const struct drm_panel_funcs panel_simple_funcs = { 288 .disable = panel_simple_disable, 289 .unprepare = panel_simple_unprepare, 290 .prepare = panel_simple_prepare, 291 .enable = panel_simple_enable, 292 .get_modes = panel_simple_get_modes, 293 .get_timings = panel_simple_get_timings, 294 }; 295 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 297 { 298 struct device_node *backlight, *ddc; 299 struct panel_simple *panel; 300 int err; 301 302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 303 if (!panel) 304 return -ENOMEM; 305 306 panel->enabled = false; 307 panel->prepared = false; 308 panel->desc = desc; 309 310 panel->supply = devm_regulator_get(dev, "power"); 311 if (IS_ERR(panel->supply)) 312 return PTR_ERR(panel->supply); 313 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 315 GPIOD_OUT_LOW); 316 if (IS_ERR(panel->enable_gpio)) { 317 err = PTR_ERR(panel->enable_gpio); 318 dev_err(dev, "failed to request GPIO: %d\n", err); 319 return err; 320 } 321 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 323 if (backlight) { 324 panel->backlight = of_find_backlight_by_node(backlight); 325 of_node_put(backlight); 326 327 if (!panel->backlight) 328 return -EPROBE_DEFER; 329 } 330 331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 332 if (ddc) { 333 panel->ddc = of_find_i2c_adapter_by_node(ddc); 334 of_node_put(ddc); 335 336 if (!panel->ddc) { 337 err = -EPROBE_DEFER; 338 goto free_backlight; 339 } 340 } 341 342 drm_panel_init(&panel->base); 343 panel->base.dev = dev; 344 panel->base.funcs = &panel_simple_funcs; 345 346 err = drm_panel_add(&panel->base); 347 if (err < 0) 348 goto free_ddc; 349 350 dev_set_drvdata(dev, panel); 351 352 return 0; 353 354 free_ddc: 355 if (panel->ddc) 356 put_device(&panel->ddc->dev); 357 free_backlight: 358 if (panel->backlight) 359 put_device(&panel->backlight->dev); 360 361 return err; 362 } 363 364 static int panel_simple_remove(struct device *dev) 365 { 366 struct panel_simple *panel = dev_get_drvdata(dev); 367 368 drm_panel_detach(&panel->base); 369 drm_panel_remove(&panel->base); 370 371 panel_simple_disable(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 390 .clock = 33333, 391 .hdisplay = 800, 392 .hsync_start = 800 + 0, 393 .hsync_end = 800 + 0 + 255, 394 .htotal = 800 + 0 + 255 + 0, 395 .vdisplay = 480, 396 .vsync_start = 480 + 2, 397 .vsync_end = 480 + 2 + 45, 398 .vtotal = 480 + 2 + 45 + 0, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am800480r3tmqwa1h = { 404 .modes = &ire_am800480r3tmqwa1h_mode, 405 .num_modes = 1, 406 .bpc = 6, 407 .size = { 408 .width = 152, 409 .height = 91, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 412 }; 413 414 static const struct drm_display_mode auo_b101aw03_mode = { 415 .clock = 51450, 416 .hdisplay = 1024, 417 .hsync_start = 1024 + 156, 418 .hsync_end = 1024 + 156 + 8, 419 .htotal = 1024 + 156 + 8 + 156, 420 .vdisplay = 600, 421 .vsync_start = 600 + 16, 422 .vsync_end = 600 + 16 + 6, 423 .vtotal = 600 + 16 + 6 + 16, 424 .vrefresh = 60, 425 }; 426 427 static const struct panel_desc auo_b101aw03 = { 428 .modes = &auo_b101aw03_mode, 429 .num_modes = 1, 430 .bpc = 6, 431 .size = { 432 .width = 223, 433 .height = 125, 434 }, 435 }; 436 437 static const struct drm_display_mode auo_b101ean01_mode = { 438 .clock = 72500, 439 .hdisplay = 1280, 440 .hsync_start = 1280 + 119, 441 .hsync_end = 1280 + 119 + 32, 442 .htotal = 1280 + 119 + 32 + 21, 443 .vdisplay = 800, 444 .vsync_start = 800 + 4, 445 .vsync_end = 800 + 4 + 20, 446 .vtotal = 800 + 4 + 20 + 8, 447 .vrefresh = 60, 448 }; 449 450 static const struct panel_desc auo_b101ean01 = { 451 .modes = &auo_b101ean01_mode, 452 .num_modes = 1, 453 .bpc = 6, 454 .size = { 455 .width = 217, 456 .height = 136, 457 }, 458 }; 459 460 static const struct drm_display_mode auo_b101xtn01_mode = { 461 .clock = 72000, 462 .hdisplay = 1366, 463 .hsync_start = 1366 + 20, 464 .hsync_end = 1366 + 20 + 70, 465 .htotal = 1366 + 20 + 70, 466 .vdisplay = 768, 467 .vsync_start = 768 + 14, 468 .vsync_end = 768 + 14 + 42, 469 .vtotal = 768 + 14 + 42, 470 .vrefresh = 60, 471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 472 }; 473 474 static const struct panel_desc auo_b101xtn01 = { 475 .modes = &auo_b101xtn01_mode, 476 .num_modes = 1, 477 .bpc = 6, 478 .size = { 479 .width = 223, 480 .height = 125, 481 }, 482 }; 483 484 static const struct drm_display_mode auo_b116xw03_mode = { 485 .clock = 70589, 486 .hdisplay = 1366, 487 .hsync_start = 1366 + 40, 488 .hsync_end = 1366 + 40 + 40, 489 .htotal = 1366 + 40 + 40 + 32, 490 .vdisplay = 768, 491 .vsync_start = 768 + 10, 492 .vsync_end = 768 + 10 + 12, 493 .vtotal = 768 + 10 + 12 + 6, 494 .vrefresh = 60, 495 }; 496 497 static const struct panel_desc auo_b116xw03 = { 498 .modes = &auo_b116xw03_mode, 499 .num_modes = 1, 500 .bpc = 6, 501 .size = { 502 .width = 256, 503 .height = 144, 504 }, 505 }; 506 507 static const struct drm_display_mode auo_b133xtn01_mode = { 508 .clock = 69500, 509 .hdisplay = 1366, 510 .hsync_start = 1366 + 48, 511 .hsync_end = 1366 + 48 + 32, 512 .htotal = 1366 + 48 + 32 + 20, 513 .vdisplay = 768, 514 .vsync_start = 768 + 3, 515 .vsync_end = 768 + 3 + 6, 516 .vtotal = 768 + 3 + 6 + 13, 517 .vrefresh = 60, 518 }; 519 520 static const struct panel_desc auo_b133xtn01 = { 521 .modes = &auo_b133xtn01_mode, 522 .num_modes = 1, 523 .bpc = 6, 524 .size = { 525 .width = 293, 526 .height = 165, 527 }, 528 }; 529 530 static const struct drm_display_mode auo_b133htn01_mode = { 531 .clock = 150660, 532 .hdisplay = 1920, 533 .hsync_start = 1920 + 172, 534 .hsync_end = 1920 + 172 + 80, 535 .htotal = 1920 + 172 + 80 + 60, 536 .vdisplay = 1080, 537 .vsync_start = 1080 + 25, 538 .vsync_end = 1080 + 25 + 10, 539 .vtotal = 1080 + 25 + 10 + 10, 540 .vrefresh = 60, 541 }; 542 543 static const struct panel_desc auo_b133htn01 = { 544 .modes = &auo_b133htn01_mode, 545 .num_modes = 1, 546 .bpc = 6, 547 .size = { 548 .width = 293, 549 .height = 165, 550 }, 551 .delay = { 552 .prepare = 105, 553 .enable = 20, 554 .unprepare = 50, 555 }, 556 }; 557 558 static const struct drm_display_mode avic_tm070ddh03_mode = { 559 .clock = 51200, 560 .hdisplay = 1024, 561 .hsync_start = 1024 + 160, 562 .hsync_end = 1024 + 160 + 4, 563 .htotal = 1024 + 160 + 4 + 156, 564 .vdisplay = 600, 565 .vsync_start = 600 + 17, 566 .vsync_end = 600 + 17 + 1, 567 .vtotal = 600 + 17 + 1 + 17, 568 .vrefresh = 60, 569 }; 570 571 static const struct panel_desc avic_tm070ddh03 = { 572 .modes = &avic_tm070ddh03_mode, 573 .num_modes = 1, 574 .bpc = 8, 575 .size = { 576 .width = 154, 577 .height = 90, 578 }, 579 .delay = { 580 .prepare = 20, 581 .enable = 200, 582 .disable = 200, 583 }, 584 }; 585 586 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 587 .clock = 72070, 588 .hdisplay = 1366, 589 .hsync_start = 1366 + 58, 590 .hsync_end = 1366 + 58 + 58, 591 .htotal = 1366 + 58 + 58 + 58, 592 .vdisplay = 768, 593 .vsync_start = 768 + 4, 594 .vsync_end = 768 + 4 + 4, 595 .vtotal = 768 + 4 + 4 + 4, 596 .vrefresh = 60, 597 }; 598 599 static const struct panel_desc chunghwa_claa101wa01a = { 600 .modes = &chunghwa_claa101wa01a_mode, 601 .num_modes = 1, 602 .bpc = 6, 603 .size = { 604 .width = 220, 605 .height = 120, 606 }, 607 }; 608 609 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 610 .clock = 69300, 611 .hdisplay = 1366, 612 .hsync_start = 1366 + 48, 613 .hsync_end = 1366 + 48 + 32, 614 .htotal = 1366 + 48 + 32 + 20, 615 .vdisplay = 768, 616 .vsync_start = 768 + 16, 617 .vsync_end = 768 + 16 + 8, 618 .vtotal = 768 + 16 + 8 + 16, 619 .vrefresh = 60, 620 }; 621 622 static const struct panel_desc chunghwa_claa101wb01 = { 623 .modes = &chunghwa_claa101wb01_mode, 624 .num_modes = 1, 625 .bpc = 6, 626 .size = { 627 .width = 223, 628 .height = 125, 629 }, 630 }; 631 632 static const struct drm_display_mode edt_et057090dhu_mode = { 633 .clock = 25175, 634 .hdisplay = 640, 635 .hsync_start = 640 + 16, 636 .hsync_end = 640 + 16 + 30, 637 .htotal = 640 + 16 + 30 + 114, 638 .vdisplay = 480, 639 .vsync_start = 480 + 10, 640 .vsync_end = 480 + 10 + 3, 641 .vtotal = 480 + 10 + 3 + 32, 642 .vrefresh = 60, 643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 644 }; 645 646 static const struct panel_desc edt_et057090dhu = { 647 .modes = &edt_et057090dhu_mode, 648 .num_modes = 1, 649 .bpc = 6, 650 .size = { 651 .width = 115, 652 .height = 86, 653 }, 654 }; 655 656 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 657 .clock = 33260, 658 .hdisplay = 800, 659 .hsync_start = 800 + 40, 660 .hsync_end = 800 + 40 + 128, 661 .htotal = 800 + 40 + 128 + 88, 662 .vdisplay = 480, 663 .vsync_start = 480 + 10, 664 .vsync_end = 480 + 10 + 2, 665 .vtotal = 480 + 10 + 2 + 33, 666 .vrefresh = 60, 667 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 668 }; 669 670 static const struct panel_desc edt_etm0700g0dh6 = { 671 .modes = &edt_etm0700g0dh6_mode, 672 .num_modes = 1, 673 .bpc = 6, 674 .size = { 675 .width = 152, 676 .height = 91, 677 }, 678 }; 679 680 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 681 .clock = 32260, 682 .hdisplay = 800, 683 .hsync_start = 800 + 168, 684 .hsync_end = 800 + 168 + 64, 685 .htotal = 800 + 168 + 64 + 88, 686 .vdisplay = 480, 687 .vsync_start = 480 + 37, 688 .vsync_end = 480 + 37 + 2, 689 .vtotal = 480 + 37 + 2 + 8, 690 .vrefresh = 60, 691 }; 692 693 static const struct panel_desc foxlink_fl500wvr00_a0t = { 694 .modes = &foxlink_fl500wvr00_a0t_mode, 695 .num_modes = 1, 696 .bpc = 8, 697 .size = { 698 .width = 108, 699 .height = 65, 700 }, 701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 702 }; 703 704 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 705 .clock = 9000, 706 .hdisplay = 480, 707 .hsync_start = 480 + 5, 708 .hsync_end = 480 + 5 + 1, 709 .htotal = 480 + 5 + 1 + 40, 710 .vdisplay = 272, 711 .vsync_start = 272 + 8, 712 .vsync_end = 272 + 8 + 1, 713 .vtotal = 272 + 8 + 1 + 8, 714 .vrefresh = 60, 715 }; 716 717 static const struct panel_desc giantplus_gpg482739qs5 = { 718 .modes = &giantplus_gpg482739qs5_mode, 719 .num_modes = 1, 720 .bpc = 8, 721 .size = { 722 .width = 95, 723 .height = 54, 724 }, 725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 726 }; 727 728 static const struct display_timing hannstar_hsd070pww1_timing = { 729 .pixelclock = { 64300000, 71100000, 82000000 }, 730 .hactive = { 1280, 1280, 1280 }, 731 .hfront_porch = { 1, 1, 10 }, 732 .hback_porch = { 1, 1, 10 }, 733 /* 734 * According to the data sheet, the minimum horizontal blanking interval 735 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 736 * minimum working horizontal blanking interval to be 60 clocks. 737 */ 738 .hsync_len = { 58, 158, 661 }, 739 .vactive = { 800, 800, 800 }, 740 .vfront_porch = { 1, 1, 10 }, 741 .vback_porch = { 1, 1, 10 }, 742 .vsync_len = { 1, 21, 203 }, 743 .flags = DISPLAY_FLAGS_DE_HIGH, 744 }; 745 746 static const struct panel_desc hannstar_hsd070pww1 = { 747 .timings = &hannstar_hsd070pww1_timing, 748 .num_timings = 1, 749 .bpc = 6, 750 .size = { 751 .width = 151, 752 .height = 94, 753 }, 754 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 755 }; 756 757 static const struct display_timing hannstar_hsd100pxn1_timing = { 758 .pixelclock = { 55000000, 65000000, 75000000 }, 759 .hactive = { 1024, 1024, 1024 }, 760 .hfront_porch = { 40, 40, 40 }, 761 .hback_porch = { 220, 220, 220 }, 762 .hsync_len = { 20, 60, 100 }, 763 .vactive = { 768, 768, 768 }, 764 .vfront_porch = { 7, 7, 7 }, 765 .vback_porch = { 21, 21, 21 }, 766 .vsync_len = { 10, 10, 10 }, 767 .flags = DISPLAY_FLAGS_DE_HIGH, 768 }; 769 770 static const struct panel_desc hannstar_hsd100pxn1 = { 771 .timings = &hannstar_hsd100pxn1_timing, 772 .num_timings = 1, 773 .bpc = 6, 774 .size = { 775 .width = 203, 776 .height = 152, 777 }, 778 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 779 }; 780 781 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 782 .clock = 33333, 783 .hdisplay = 800, 784 .hsync_start = 800 + 85, 785 .hsync_end = 800 + 85 + 86, 786 .htotal = 800 + 85 + 86 + 85, 787 .vdisplay = 480, 788 .vsync_start = 480 + 16, 789 .vsync_end = 480 + 16 + 13, 790 .vtotal = 480 + 16 + 13 + 16, 791 .vrefresh = 60, 792 }; 793 794 static const struct panel_desc hitachi_tx23d38vm0caa = { 795 .modes = &hitachi_tx23d38vm0caa_mode, 796 .num_modes = 1, 797 .bpc = 6, 798 .size = { 799 .width = 195, 800 .height = 117, 801 }, 802 }; 803 804 static const struct drm_display_mode innolux_at043tn24_mode = { 805 .clock = 9000, 806 .hdisplay = 480, 807 .hsync_start = 480 + 2, 808 .hsync_end = 480 + 2 + 41, 809 .htotal = 480 + 2 + 41 + 2, 810 .vdisplay = 272, 811 .vsync_start = 272 + 2, 812 .vsync_end = 272 + 2 + 11, 813 .vtotal = 272 + 2 + 11 + 2, 814 .vrefresh = 60, 815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 816 }; 817 818 static const struct panel_desc innolux_at043tn24 = { 819 .modes = &innolux_at043tn24_mode, 820 .num_modes = 1, 821 .bpc = 8, 822 .size = { 823 .width = 95, 824 .height = 54, 825 }, 826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 827 }; 828 829 static const struct drm_display_mode innolux_at070tn92_mode = { 830 .clock = 33333, 831 .hdisplay = 800, 832 .hsync_start = 800 + 210, 833 .hsync_end = 800 + 210 + 20, 834 .htotal = 800 + 210 + 20 + 46, 835 .vdisplay = 480, 836 .vsync_start = 480 + 22, 837 .vsync_end = 480 + 22 + 10, 838 .vtotal = 480 + 22 + 23 + 10, 839 .vrefresh = 60, 840 }; 841 842 static const struct panel_desc innolux_at070tn92 = { 843 .modes = &innolux_at070tn92_mode, 844 .num_modes = 1, 845 .size = { 846 .width = 154, 847 .height = 86, 848 }, 849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 850 }; 851 852 static const struct drm_display_mode innolux_g121i1_l01_mode = { 853 .clock = 71000, 854 .hdisplay = 1280, 855 .hsync_start = 1280 + 64, 856 .hsync_end = 1280 + 64 + 32, 857 .htotal = 1280 + 64 + 32 + 64, 858 .vdisplay = 800, 859 .vsync_start = 800 + 9, 860 .vsync_end = 800 + 9 + 6, 861 .vtotal = 800 + 9 + 6 + 9, 862 .vrefresh = 60, 863 }; 864 865 static const struct panel_desc innolux_g121i1_l01 = { 866 .modes = &innolux_g121i1_l01_mode, 867 .num_modes = 1, 868 .bpc = 6, 869 .size = { 870 .width = 261, 871 .height = 163, 872 }, 873 }; 874 875 static const struct drm_display_mode innolux_g121x1_l03_mode = { 876 .clock = 65000, 877 .hdisplay = 1024, 878 .hsync_start = 1024 + 0, 879 .hsync_end = 1024 + 1, 880 .htotal = 1024 + 0 + 1 + 320, 881 .vdisplay = 768, 882 .vsync_start = 768 + 38, 883 .vsync_end = 768 + 38 + 1, 884 .vtotal = 768 + 38 + 1 + 0, 885 .vrefresh = 60, 886 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 887 }; 888 889 static const struct panel_desc innolux_g121x1_l03 = { 890 .modes = &innolux_g121x1_l03_mode, 891 .num_modes = 1, 892 .bpc = 6, 893 .size = { 894 .width = 246, 895 .height = 185, 896 }, 897 .delay = { 898 .enable = 200, 899 .unprepare = 200, 900 .disable = 400, 901 }, 902 }; 903 904 static const struct drm_display_mode innolux_n116bge_mode = { 905 .clock = 76420, 906 .hdisplay = 1366, 907 .hsync_start = 1366 + 136, 908 .hsync_end = 1366 + 136 + 30, 909 .htotal = 1366 + 136 + 30 + 60, 910 .vdisplay = 768, 911 .vsync_start = 768 + 8, 912 .vsync_end = 768 + 8 + 12, 913 .vtotal = 768 + 8 + 12 + 12, 914 .vrefresh = 60, 915 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 916 }; 917 918 static const struct panel_desc innolux_n116bge = { 919 .modes = &innolux_n116bge_mode, 920 .num_modes = 1, 921 .bpc = 6, 922 .size = { 923 .width = 256, 924 .height = 144, 925 }, 926 }; 927 928 static const struct drm_display_mode innolux_n156bge_l21_mode = { 929 .clock = 69300, 930 .hdisplay = 1366, 931 .hsync_start = 1366 + 16, 932 .hsync_end = 1366 + 16 + 34, 933 .htotal = 1366 + 16 + 34 + 50, 934 .vdisplay = 768, 935 .vsync_start = 768 + 2, 936 .vsync_end = 768 + 2 + 6, 937 .vtotal = 768 + 2 + 6 + 12, 938 .vrefresh = 60, 939 }; 940 941 static const struct panel_desc innolux_n156bge_l21 = { 942 .modes = &innolux_n156bge_l21_mode, 943 .num_modes = 1, 944 .bpc = 6, 945 .size = { 946 .width = 344, 947 .height = 193, 948 }, 949 }; 950 951 static const struct drm_display_mode innolux_zj070na_01p_mode = { 952 .clock = 51501, 953 .hdisplay = 1024, 954 .hsync_start = 1024 + 128, 955 .hsync_end = 1024 + 128 + 64, 956 .htotal = 1024 + 128 + 64 + 128, 957 .vdisplay = 600, 958 .vsync_start = 600 + 16, 959 .vsync_end = 600 + 16 + 4, 960 .vtotal = 600 + 16 + 4 + 16, 961 .vrefresh = 60, 962 }; 963 964 static const struct panel_desc innolux_zj070na_01p = { 965 .modes = &innolux_zj070na_01p_mode, 966 .num_modes = 1, 967 .bpc = 6, 968 .size = { 969 .width = 154, 970 .height = 90, 971 }, 972 }; 973 974 static const struct display_timing kyo_tcg121xglp_timing = { 975 .pixelclock = { 52000000, 65000000, 71000000 }, 976 .hactive = { 1024, 1024, 1024 }, 977 .hfront_porch = { 2, 2, 2 }, 978 .hback_porch = { 2, 2, 2 }, 979 .hsync_len = { 86, 124, 244 }, 980 .vactive = { 768, 768, 768 }, 981 .vfront_porch = { 2, 2, 2 }, 982 .vback_porch = { 2, 2, 2 }, 983 .vsync_len = { 6, 34, 73 }, 984 .flags = DISPLAY_FLAGS_DE_HIGH, 985 }; 986 987 static const struct panel_desc kyo_tcg121xglp = { 988 .timings = &kyo_tcg121xglp_timing, 989 .num_timings = 1, 990 .bpc = 8, 991 .size = { 992 .width = 246, 993 .height = 184, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 }; 997 998 static const struct drm_display_mode lg_lb070wv8_mode = { 999 .clock = 33246, 1000 .hdisplay = 800, 1001 .hsync_start = 800 + 88, 1002 .hsync_end = 800 + 88 + 80, 1003 .htotal = 800 + 88 + 80 + 88, 1004 .vdisplay = 480, 1005 .vsync_start = 480 + 10, 1006 .vsync_end = 480 + 10 + 25, 1007 .vtotal = 480 + 10 + 25 + 10, 1008 .vrefresh = 60, 1009 }; 1010 1011 static const struct panel_desc lg_lb070wv8 = { 1012 .modes = &lg_lb070wv8_mode, 1013 .num_modes = 1, 1014 .bpc = 16, 1015 .size = { 1016 .width = 151, 1017 .height = 91, 1018 }, 1019 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1020 }; 1021 1022 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1023 .clock = 200000, 1024 .hdisplay = 1536, 1025 .hsync_start = 1536 + 12, 1026 .hsync_end = 1536 + 12 + 16, 1027 .htotal = 1536 + 12 + 16 + 48, 1028 .vdisplay = 2048, 1029 .vsync_start = 2048 + 8, 1030 .vsync_end = 2048 + 8 + 4, 1031 .vtotal = 2048 + 8 + 4 + 8, 1032 .vrefresh = 60, 1033 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1034 }; 1035 1036 static const struct panel_desc lg_lp079qx1_sp0v = { 1037 .modes = &lg_lp079qx1_sp0v_mode, 1038 .num_modes = 1, 1039 .size = { 1040 .width = 129, 1041 .height = 171, 1042 }, 1043 }; 1044 1045 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1046 .clock = 205210, 1047 .hdisplay = 2048, 1048 .hsync_start = 2048 + 150, 1049 .hsync_end = 2048 + 150 + 5, 1050 .htotal = 2048 + 150 + 5 + 5, 1051 .vdisplay = 1536, 1052 .vsync_start = 1536 + 3, 1053 .vsync_end = 1536 + 3 + 1, 1054 .vtotal = 1536 + 3 + 1 + 9, 1055 .vrefresh = 60, 1056 }; 1057 1058 static const struct panel_desc lg_lp097qx1_spa1 = { 1059 .modes = &lg_lp097qx1_spa1_mode, 1060 .num_modes = 1, 1061 .size = { 1062 .width = 208, 1063 .height = 147, 1064 }, 1065 }; 1066 1067 static const struct drm_display_mode lg_lp120up1_mode = { 1068 .clock = 162300, 1069 .hdisplay = 1920, 1070 .hsync_start = 1920 + 40, 1071 .hsync_end = 1920 + 40 + 40, 1072 .htotal = 1920 + 40 + 40+ 80, 1073 .vdisplay = 1280, 1074 .vsync_start = 1280 + 4, 1075 .vsync_end = 1280 + 4 + 4, 1076 .vtotal = 1280 + 4 + 4 + 12, 1077 .vrefresh = 60, 1078 }; 1079 1080 static const struct panel_desc lg_lp120up1 = { 1081 .modes = &lg_lp120up1_mode, 1082 .num_modes = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 267, 1086 .height = 183, 1087 }, 1088 }; 1089 1090 static const struct drm_display_mode lg_lp129qe_mode = { 1091 .clock = 285250, 1092 .hdisplay = 2560, 1093 .hsync_start = 2560 + 48, 1094 .hsync_end = 2560 + 48 + 32, 1095 .htotal = 2560 + 48 + 32 + 80, 1096 .vdisplay = 1700, 1097 .vsync_start = 1700 + 3, 1098 .vsync_end = 1700 + 3 + 10, 1099 .vtotal = 1700 + 3 + 10 + 36, 1100 .vrefresh = 60, 1101 }; 1102 1103 static const struct panel_desc lg_lp129qe = { 1104 .modes = &lg_lp129qe_mode, 1105 .num_modes = 1, 1106 .bpc = 8, 1107 .size = { 1108 .width = 272, 1109 .height = 181, 1110 }, 1111 }; 1112 1113 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1114 .clock = 10870, 1115 .hdisplay = 480, 1116 .hsync_start = 480 + 2, 1117 .hsync_end = 480 + 2 + 41, 1118 .htotal = 480 + 2 + 41 + 2, 1119 .vdisplay = 272, 1120 .vsync_start = 272 + 2, 1121 .vsync_end = 272 + 2 + 4, 1122 .vtotal = 272 + 2 + 4 + 2, 1123 .vrefresh = 74, 1124 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1125 }; 1126 1127 static const struct panel_desc nec_nl4827hc19_05b = { 1128 .modes = &nec_nl4827hc19_05b_mode, 1129 .num_modes = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 95, 1133 .height = 54, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1136 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1137 }; 1138 1139 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1140 .pixelclock = { 30000000, 30000000, 40000000 }, 1141 .hactive = { 800, 800, 800 }, 1142 .hfront_porch = { 40, 40, 40 }, 1143 .hback_porch = { 40, 40, 40 }, 1144 .hsync_len = { 1, 48, 48 }, 1145 .vactive = { 480, 480, 480 }, 1146 .vfront_porch = { 13, 13, 13 }, 1147 .vback_porch = { 29, 29, 29 }, 1148 .vsync_len = { 3, 3, 3 }, 1149 .flags = DISPLAY_FLAGS_DE_HIGH, 1150 }; 1151 1152 static const struct panel_desc okaya_rs800480t_7x0gp = { 1153 .timings = &okaya_rs800480t_7x0gp_timing, 1154 .num_timings = 1, 1155 .bpc = 6, 1156 .size = { 1157 .width = 154, 1158 .height = 87, 1159 }, 1160 .delay = { 1161 .prepare = 41, 1162 .enable = 50, 1163 .unprepare = 41, 1164 .disable = 50, 1165 }, 1166 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1167 }; 1168 1169 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1170 .clock = 9000, 1171 .hdisplay = 480, 1172 .hsync_start = 480 + 5, 1173 .hsync_end = 480 + 5 + 30, 1174 .htotal = 480 + 5 + 30 + 10, 1175 .vdisplay = 272, 1176 .vsync_start = 272 + 8, 1177 .vsync_end = 272 + 8 + 5, 1178 .vtotal = 272 + 8 + 5 + 3, 1179 .vrefresh = 60, 1180 }; 1181 1182 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1183 .modes = &olimex_lcd_olinuxino_43ts_mode, 1184 .num_modes = 1, 1185 .size = { 1186 .width = 105, 1187 .height = 67, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1190 }; 1191 1192 /* 1193 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1194 * pixel clocks, but this is the timing that was being used in the Adafruit 1195 * installation instructions. 1196 */ 1197 static const struct drm_display_mode ontat_yx700wv03_mode = { 1198 .clock = 29500, 1199 .hdisplay = 800, 1200 .hsync_start = 824, 1201 .hsync_end = 896, 1202 .htotal = 992, 1203 .vdisplay = 480, 1204 .vsync_start = 483, 1205 .vsync_end = 493, 1206 .vtotal = 500, 1207 .vrefresh = 60, 1208 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1209 }; 1210 1211 /* 1212 * Specification at: 1213 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1214 */ 1215 static const struct panel_desc ontat_yx700wv03 = { 1216 .modes = &ontat_yx700wv03_mode, 1217 .num_modes = 1, 1218 .bpc = 8, 1219 .size = { 1220 .width = 154, 1221 .height = 83, 1222 }, 1223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1224 }; 1225 1226 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1227 .clock = 25000, 1228 .hdisplay = 480, 1229 .hsync_start = 480 + 10, 1230 .hsync_end = 480 + 10 + 10, 1231 .htotal = 480 + 10 + 10 + 15, 1232 .vdisplay = 800, 1233 .vsync_start = 800 + 3, 1234 .vsync_end = 800 + 3 + 3, 1235 .vtotal = 800 + 3 + 3 + 3, 1236 .vrefresh = 60, 1237 }; 1238 1239 static const struct panel_desc ortustech_com43h4m85ulc = { 1240 .modes = &ortustech_com43h4m85ulc_mode, 1241 .num_modes = 1, 1242 .bpc = 8, 1243 .size = { 1244 .width = 56, 1245 .height = 93, 1246 }, 1247 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1248 }; 1249 1250 static const struct drm_display_mode qd43003c0_40_mode = { 1251 .clock = 9000, 1252 .hdisplay = 480, 1253 .hsync_start = 480 + 8, 1254 .hsync_end = 480 + 8 + 4, 1255 .htotal = 480 + 8 + 4 + 39, 1256 .vdisplay = 272, 1257 .vsync_start = 272 + 4, 1258 .vsync_end = 272 + 4 + 10, 1259 .vtotal = 272 + 4 + 10 + 2, 1260 .vrefresh = 60, 1261 }; 1262 1263 static const struct panel_desc qd43003c0_40 = { 1264 .modes = &qd43003c0_40_mode, 1265 .num_modes = 1, 1266 .bpc = 8, 1267 .size = { 1268 .width = 95, 1269 .height = 53, 1270 }, 1271 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1272 }; 1273 1274 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1275 .clock = 271560, 1276 .hdisplay = 2560, 1277 .hsync_start = 2560 + 48, 1278 .hsync_end = 2560 + 48 + 32, 1279 .htotal = 2560 + 48 + 32 + 80, 1280 .vdisplay = 1600, 1281 .vsync_start = 1600 + 2, 1282 .vsync_end = 1600 + 2 + 5, 1283 .vtotal = 1600 + 2 + 5 + 57, 1284 .vrefresh = 60, 1285 }; 1286 1287 static const struct panel_desc samsung_lsn122dl01_c01 = { 1288 .modes = &samsung_lsn122dl01_c01_mode, 1289 .num_modes = 1, 1290 .size = { 1291 .width = 263, 1292 .height = 164, 1293 }, 1294 }; 1295 1296 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1297 .clock = 54030, 1298 .hdisplay = 1024, 1299 .hsync_start = 1024 + 24, 1300 .hsync_end = 1024 + 24 + 136, 1301 .htotal = 1024 + 24 + 136 + 160, 1302 .vdisplay = 600, 1303 .vsync_start = 600 + 3, 1304 .vsync_end = 600 + 3 + 6, 1305 .vtotal = 600 + 3 + 6 + 61, 1306 .vrefresh = 60, 1307 }; 1308 1309 static const struct panel_desc samsung_ltn101nt05 = { 1310 .modes = &samsung_ltn101nt05_mode, 1311 .num_modes = 1, 1312 .bpc = 6, 1313 .size = { 1314 .width = 223, 1315 .height = 125, 1316 }, 1317 }; 1318 1319 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1320 .clock = 76300, 1321 .hdisplay = 1366, 1322 .hsync_start = 1366 + 64, 1323 .hsync_end = 1366 + 64 + 48, 1324 .htotal = 1366 + 64 + 48 + 128, 1325 .vdisplay = 768, 1326 .vsync_start = 768 + 2, 1327 .vsync_end = 768 + 2 + 5, 1328 .vtotal = 768 + 2 + 5 + 17, 1329 .vrefresh = 60, 1330 }; 1331 1332 static const struct panel_desc samsung_ltn140at29_301 = { 1333 .modes = &samsung_ltn140at29_301_mode, 1334 .num_modes = 1, 1335 .bpc = 6, 1336 .size = { 1337 .width = 320, 1338 .height = 187, 1339 }, 1340 }; 1341 1342 static const struct display_timing sharp_lq101k1ly04_timing = { 1343 .pixelclock = { 60000000, 65000000, 80000000 }, 1344 .hactive = { 1280, 1280, 1280 }, 1345 .hfront_porch = { 20, 20, 20 }, 1346 .hback_porch = { 20, 20, 20 }, 1347 .hsync_len = { 10, 10, 10 }, 1348 .vactive = { 800, 800, 800 }, 1349 .vfront_porch = { 4, 4, 4 }, 1350 .vback_porch = { 4, 4, 4 }, 1351 .vsync_len = { 4, 4, 4 }, 1352 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1353 }; 1354 1355 static const struct panel_desc sharp_lq101k1ly04 = { 1356 .timings = &sharp_lq101k1ly04_timing, 1357 .num_timings = 1, 1358 .bpc = 8, 1359 .size = { 1360 .width = 217, 1361 .height = 136, 1362 }, 1363 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1364 }; 1365 1366 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1367 .clock = 252750, 1368 .hdisplay = 2400, 1369 .hsync_start = 2400 + 48, 1370 .hsync_end = 2400 + 48 + 32, 1371 .htotal = 2400 + 48 + 32 + 80, 1372 .vdisplay = 1600, 1373 .vsync_start = 1600 + 3, 1374 .vsync_end = 1600 + 3 + 10, 1375 .vtotal = 1600 + 3 + 10 + 33, 1376 .vrefresh = 60, 1377 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1378 }; 1379 1380 static const struct panel_desc sharp_lq123p1jx31 = { 1381 .modes = &sharp_lq123p1jx31_mode, 1382 .num_modes = 1, 1383 .size = { 1384 .width = 259, 1385 .height = 173, 1386 }, 1387 }; 1388 1389 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1390 .clock = 33300, 1391 .hdisplay = 800, 1392 .hsync_start = 800 + 1, 1393 .hsync_end = 800 + 1 + 64, 1394 .htotal = 800 + 1 + 64 + 64, 1395 .vdisplay = 480, 1396 .vsync_start = 480 + 1, 1397 .vsync_end = 480 + 1 + 23, 1398 .vtotal = 480 + 1 + 23 + 22, 1399 .vrefresh = 60, 1400 }; 1401 1402 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1403 .modes = &shelly_sca07010_bfn_lnn_mode, 1404 .num_modes = 1, 1405 .size = { 1406 .width = 152, 1407 .height = 91, 1408 }, 1409 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1410 }; 1411 1412 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1413 .clock = 147000, 1414 .hdisplay = 1920, 1415 .hsync_start = 1920 + 16, 1416 .hsync_end = 1920 + 16 + 16, 1417 .htotal = 1920 + 16 + 16 + 32, 1418 .vdisplay = 1200, 1419 .vsync_start = 1200 + 15, 1420 .vsync_end = 1200 + 15 + 2, 1421 .vtotal = 1200 + 15 + 2 + 18, 1422 .vrefresh = 60, 1423 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1424 }; 1425 1426 static const struct panel_desc starry_kr122ea0sra = { 1427 .modes = &starry_kr122ea0sra_mode, 1428 .num_modes = 1, 1429 .size = { 1430 .width = 263, 1431 .height = 164, 1432 }, 1433 }; 1434 1435 static const struct drm_display_mode tpk_f07a_0102_mode = { 1436 .clock = 33260, 1437 .hdisplay = 800, 1438 .hsync_start = 800 + 40, 1439 .hsync_end = 800 + 40 + 128, 1440 .htotal = 800 + 40 + 128 + 88, 1441 .vdisplay = 480, 1442 .vsync_start = 480 + 10, 1443 .vsync_end = 480 + 10 + 2, 1444 .vtotal = 480 + 10 + 2 + 33, 1445 .vrefresh = 60, 1446 }; 1447 1448 static const struct panel_desc tpk_f07a_0102 = { 1449 .modes = &tpk_f07a_0102_mode, 1450 .num_modes = 1, 1451 .size = { 1452 .width = 152, 1453 .height = 91, 1454 }, 1455 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1456 }; 1457 1458 static const struct drm_display_mode tpk_f10a_0102_mode = { 1459 .clock = 45000, 1460 .hdisplay = 1024, 1461 .hsync_start = 1024 + 176, 1462 .hsync_end = 1024 + 176 + 5, 1463 .htotal = 1024 + 176 + 5 + 88, 1464 .vdisplay = 600, 1465 .vsync_start = 600 + 20, 1466 .vsync_end = 600 + 20 + 5, 1467 .vtotal = 600 + 20 + 5 + 25, 1468 .vrefresh = 60, 1469 }; 1470 1471 static const struct panel_desc tpk_f10a_0102 = { 1472 .modes = &tpk_f10a_0102_mode, 1473 .num_modes = 1, 1474 .size = { 1475 .width = 223, 1476 .height = 125, 1477 }, 1478 }; 1479 1480 static const struct display_timing urt_umsh_8596md_timing = { 1481 .pixelclock = { 33260000, 33260000, 33260000 }, 1482 .hactive = { 800, 800, 800 }, 1483 .hfront_porch = { 41, 41, 41 }, 1484 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1485 .hsync_len = { 71, 128, 128 }, 1486 .vactive = { 480, 480, 480 }, 1487 .vfront_porch = { 10, 10, 10 }, 1488 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1489 .vsync_len = { 2, 2, 2 }, 1490 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1491 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1492 }; 1493 1494 static const struct panel_desc urt_umsh_8596md_lvds = { 1495 .timings = &urt_umsh_8596md_timing, 1496 .num_timings = 1, 1497 .bpc = 6, 1498 .size = { 1499 .width = 152, 1500 .height = 91, 1501 }, 1502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1503 }; 1504 1505 static const struct panel_desc urt_umsh_8596md_parallel = { 1506 .timings = &urt_umsh_8596md_timing, 1507 .num_timings = 1, 1508 .bpc = 6, 1509 .size = { 1510 .width = 152, 1511 .height = 91, 1512 }, 1513 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1514 }; 1515 1516 static const struct of_device_id platform_of_match[] = { 1517 { 1518 .compatible = "ampire,am800480r3tmqwa1h", 1519 .data = &ire_am800480r3tmqwa1h, 1520 }, { 1521 .compatible = "auo,b101aw03", 1522 .data = &auo_b101aw03, 1523 }, { 1524 .compatible = "auo,b101ean01", 1525 .data = &auo_b101ean01, 1526 }, { 1527 .compatible = "auo,b101xtn01", 1528 .data = &auo_b101xtn01, 1529 }, { 1530 .compatible = "auo,b116xw03", 1531 .data = &auo_b116xw03, 1532 }, { 1533 .compatible = "auo,b133htn01", 1534 .data = &auo_b133htn01, 1535 }, { 1536 .compatible = "auo,b133xtn01", 1537 .data = &auo_b133xtn01, 1538 }, { 1539 .compatible = "avic,tm070ddh03", 1540 .data = &avic_tm070ddh03, 1541 }, { 1542 .compatible = "chunghwa,claa101wa01a", 1543 .data = &chunghwa_claa101wa01a 1544 }, { 1545 .compatible = "chunghwa,claa101wb01", 1546 .data = &chunghwa_claa101wb01 1547 }, { 1548 .compatible = "edt,et057090dhu", 1549 .data = &edt_et057090dhu, 1550 }, { 1551 .compatible = "edt,et070080dh6", 1552 .data = &edt_etm0700g0dh6, 1553 }, { 1554 .compatible = "edt,etm0700g0dh6", 1555 .data = &edt_etm0700g0dh6, 1556 }, { 1557 .compatible = "foxlink,fl500wvr00-a0t", 1558 .data = &foxlink_fl500wvr00_a0t, 1559 }, { 1560 .compatible = "giantplus,gpg482739qs5", 1561 .data = &giantplus_gpg482739qs5 1562 }, { 1563 .compatible = "hannstar,hsd070pww1", 1564 .data = &hannstar_hsd070pww1, 1565 }, { 1566 .compatible = "hannstar,hsd100pxn1", 1567 .data = &hannstar_hsd100pxn1, 1568 }, { 1569 .compatible = "hit,tx23d38vm0caa", 1570 .data = &hitachi_tx23d38vm0caa 1571 }, { 1572 .compatible = "innolux,at043tn24", 1573 .data = &innolux_at043tn24, 1574 }, { 1575 .compatible = "innolux,at070tn92", 1576 .data = &innolux_at070tn92, 1577 }, { 1578 .compatible ="innolux,g121i1-l01", 1579 .data = &innolux_g121i1_l01 1580 }, { 1581 .compatible = "innolux,g121x1-l03", 1582 .data = &innolux_g121x1_l03, 1583 }, { 1584 .compatible = "innolux,n116bge", 1585 .data = &innolux_n116bge, 1586 }, { 1587 .compatible = "innolux,n156bge-l21", 1588 .data = &innolux_n156bge_l21, 1589 }, { 1590 .compatible = "innolux,zj070na-01p", 1591 .data = &innolux_zj070na_01p, 1592 }, { 1593 .compatible = "kyo,tcg121xglp", 1594 .data = &kyo_tcg121xglp, 1595 }, { 1596 .compatible = "lg,lb070wv8", 1597 .data = &lg_lb070wv8, 1598 }, { 1599 .compatible = "lg,lp079qx1-sp0v", 1600 .data = &lg_lp079qx1_sp0v, 1601 }, { 1602 .compatible = "lg,lp097qx1-spa1", 1603 .data = &lg_lp097qx1_spa1, 1604 }, { 1605 .compatible = "lg,lp120up1", 1606 .data = &lg_lp120up1, 1607 }, { 1608 .compatible = "lg,lp129qe", 1609 .data = &lg_lp129qe, 1610 }, { 1611 .compatible = "nec,nl4827hc19-05b", 1612 .data = &nec_nl4827hc19_05b, 1613 }, { 1614 .compatible = "okaya,rs800480t-7x0gp", 1615 .data = &okaya_rs800480t_7x0gp, 1616 }, { 1617 .compatible = "olimex,lcd-olinuxino-43-ts", 1618 .data = &olimex_lcd_olinuxino_43ts, 1619 }, { 1620 .compatible = "ontat,yx700wv03", 1621 .data = &ontat_yx700wv03, 1622 }, { 1623 .compatible = "ortustech,com43h4m85ulc", 1624 .data = &ortustech_com43h4m85ulc, 1625 }, { 1626 .compatible = "qiaodian,qd43003c0-40", 1627 .data = &qd43003c0_40, 1628 }, { 1629 .compatible = "samsung,lsn122dl01-c01", 1630 .data = &samsung_lsn122dl01_c01, 1631 }, { 1632 .compatible = "samsung,ltn101nt05", 1633 .data = &samsung_ltn101nt05, 1634 }, { 1635 .compatible = "samsung,ltn140at29-301", 1636 .data = &samsung_ltn140at29_301, 1637 }, { 1638 .compatible = "sharp,lq101k1ly04", 1639 .data = &sharp_lq101k1ly04, 1640 }, { 1641 .compatible = "sharp,lq123p1jx31", 1642 .data = &sharp_lq123p1jx31, 1643 }, { 1644 .compatible = "shelly,sca07010-bfn-lnn", 1645 .data = &shelly_sca07010_bfn_lnn, 1646 }, { 1647 .compatible = "starry,kr122ea0sra", 1648 .data = &starry_kr122ea0sra, 1649 }, { 1650 .compatible = "tpk,f07a-0102", 1651 .data = &tpk_f07a_0102, 1652 }, { 1653 .compatible = "tpk,f10a-0102", 1654 .data = &tpk_f10a_0102, 1655 }, { 1656 .compatible = "urt,umsh-8596md-t", 1657 .data = &urt_umsh_8596md_parallel, 1658 }, { 1659 .compatible = "urt,umsh-8596md-1t", 1660 .data = &urt_umsh_8596md_parallel, 1661 }, { 1662 .compatible = "urt,umsh-8596md-7t", 1663 .data = &urt_umsh_8596md_parallel, 1664 }, { 1665 .compatible = "urt,umsh-8596md-11t", 1666 .data = &urt_umsh_8596md_lvds, 1667 }, { 1668 .compatible = "urt,umsh-8596md-19t", 1669 .data = &urt_umsh_8596md_lvds, 1670 }, { 1671 .compatible = "urt,umsh-8596md-20t", 1672 .data = &urt_umsh_8596md_parallel, 1673 }, { 1674 /* sentinel */ 1675 } 1676 }; 1677 MODULE_DEVICE_TABLE(of, platform_of_match); 1678 1679 static int panel_simple_platform_probe(struct platform_device *pdev) 1680 { 1681 const struct of_device_id *id; 1682 1683 id = of_match_node(platform_of_match, pdev->dev.of_node); 1684 if (!id) 1685 return -ENODEV; 1686 1687 return panel_simple_probe(&pdev->dev, id->data); 1688 } 1689 1690 static int panel_simple_platform_remove(struct platform_device *pdev) 1691 { 1692 return panel_simple_remove(&pdev->dev); 1693 } 1694 1695 static void panel_simple_platform_shutdown(struct platform_device *pdev) 1696 { 1697 panel_simple_shutdown(&pdev->dev); 1698 } 1699 1700 static struct platform_driver panel_simple_platform_driver = { 1701 .driver = { 1702 .name = "panel-simple", 1703 .of_match_table = platform_of_match, 1704 }, 1705 .probe = panel_simple_platform_probe, 1706 .remove = panel_simple_platform_remove, 1707 .shutdown = panel_simple_platform_shutdown, 1708 }; 1709 1710 struct panel_desc_dsi { 1711 struct panel_desc desc; 1712 1713 unsigned long flags; 1714 enum mipi_dsi_pixel_format format; 1715 unsigned int lanes; 1716 }; 1717 1718 static const struct drm_display_mode auo_b080uan01_mode = { 1719 .clock = 154500, 1720 .hdisplay = 1200, 1721 .hsync_start = 1200 + 62, 1722 .hsync_end = 1200 + 62 + 4, 1723 .htotal = 1200 + 62 + 4 + 62, 1724 .vdisplay = 1920, 1725 .vsync_start = 1920 + 9, 1726 .vsync_end = 1920 + 9 + 2, 1727 .vtotal = 1920 + 9 + 2 + 8, 1728 .vrefresh = 60, 1729 }; 1730 1731 static const struct panel_desc_dsi auo_b080uan01 = { 1732 .desc = { 1733 .modes = &auo_b080uan01_mode, 1734 .num_modes = 1, 1735 .bpc = 8, 1736 .size = { 1737 .width = 108, 1738 .height = 272, 1739 }, 1740 }, 1741 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 1742 .format = MIPI_DSI_FMT_RGB888, 1743 .lanes = 4, 1744 }; 1745 1746 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 1747 .clock = 160000, 1748 .hdisplay = 1200, 1749 .hsync_start = 1200 + 120, 1750 .hsync_end = 1200 + 120 + 20, 1751 .htotal = 1200 + 120 + 20 + 21, 1752 .vdisplay = 1920, 1753 .vsync_start = 1920 + 21, 1754 .vsync_end = 1920 + 21 + 3, 1755 .vtotal = 1920 + 21 + 3 + 18, 1756 .vrefresh = 60, 1757 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1758 }; 1759 1760 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 1761 .desc = { 1762 .modes = &boe_tv080wum_nl0_mode, 1763 .num_modes = 1, 1764 .size = { 1765 .width = 107, 1766 .height = 172, 1767 }, 1768 }, 1769 .flags = MIPI_DSI_MODE_VIDEO | 1770 MIPI_DSI_MODE_VIDEO_BURST | 1771 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 1772 .format = MIPI_DSI_FMT_RGB888, 1773 .lanes = 4, 1774 }; 1775 1776 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 1777 .clock = 71000, 1778 .hdisplay = 800, 1779 .hsync_start = 800 + 32, 1780 .hsync_end = 800 + 32 + 1, 1781 .htotal = 800 + 32 + 1 + 57, 1782 .vdisplay = 1280, 1783 .vsync_start = 1280 + 28, 1784 .vsync_end = 1280 + 28 + 1, 1785 .vtotal = 1280 + 28 + 1 + 14, 1786 .vrefresh = 60, 1787 }; 1788 1789 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 1790 .desc = { 1791 .modes = &lg_ld070wx3_sl01_mode, 1792 .num_modes = 1, 1793 .bpc = 8, 1794 .size = { 1795 .width = 94, 1796 .height = 151, 1797 }, 1798 }, 1799 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 1800 .format = MIPI_DSI_FMT_RGB888, 1801 .lanes = 4, 1802 }; 1803 1804 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 1805 .clock = 67000, 1806 .hdisplay = 720, 1807 .hsync_start = 720 + 12, 1808 .hsync_end = 720 + 12 + 4, 1809 .htotal = 720 + 12 + 4 + 112, 1810 .vdisplay = 1280, 1811 .vsync_start = 1280 + 8, 1812 .vsync_end = 1280 + 8 + 4, 1813 .vtotal = 1280 + 8 + 4 + 12, 1814 .vrefresh = 60, 1815 }; 1816 1817 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 1818 .desc = { 1819 .modes = &lg_lh500wx1_sd03_mode, 1820 .num_modes = 1, 1821 .bpc = 8, 1822 .size = { 1823 .width = 62, 1824 .height = 110, 1825 }, 1826 }, 1827 .flags = MIPI_DSI_MODE_VIDEO, 1828 .format = MIPI_DSI_FMT_RGB888, 1829 .lanes = 4, 1830 }; 1831 1832 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 1833 .clock = 157200, 1834 .hdisplay = 1920, 1835 .hsync_start = 1920 + 154, 1836 .hsync_end = 1920 + 154 + 16, 1837 .htotal = 1920 + 154 + 16 + 32, 1838 .vdisplay = 1200, 1839 .vsync_start = 1200 + 17, 1840 .vsync_end = 1200 + 17 + 2, 1841 .vtotal = 1200 + 17 + 2 + 16, 1842 .vrefresh = 60, 1843 }; 1844 1845 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 1846 .desc = { 1847 .modes = &panasonic_vvx10f004b00_mode, 1848 .num_modes = 1, 1849 .bpc = 8, 1850 .size = { 1851 .width = 217, 1852 .height = 136, 1853 }, 1854 }, 1855 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1856 MIPI_DSI_CLOCK_NON_CONTINUOUS, 1857 .format = MIPI_DSI_FMT_RGB888, 1858 .lanes = 4, 1859 }; 1860 1861 static const struct of_device_id dsi_of_match[] = { 1862 { 1863 .compatible = "auo,b080uan01", 1864 .data = &auo_b080uan01 1865 }, { 1866 .compatible = "boe,tv080wum-nl0", 1867 .data = &boe_tv080wum_nl0 1868 }, { 1869 .compatible = "lg,ld070wx3-sl01", 1870 .data = &lg_ld070wx3_sl01 1871 }, { 1872 .compatible = "lg,lh500wx1-sd03", 1873 .data = &lg_lh500wx1_sd03 1874 }, { 1875 .compatible = "panasonic,vvx10f004b00", 1876 .data = &panasonic_vvx10f004b00 1877 }, { 1878 /* sentinel */ 1879 } 1880 }; 1881 MODULE_DEVICE_TABLE(of, dsi_of_match); 1882 1883 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 1884 { 1885 const struct panel_desc_dsi *desc; 1886 const struct of_device_id *id; 1887 int err; 1888 1889 id = of_match_node(dsi_of_match, dsi->dev.of_node); 1890 if (!id) 1891 return -ENODEV; 1892 1893 desc = id->data; 1894 1895 err = panel_simple_probe(&dsi->dev, &desc->desc); 1896 if (err < 0) 1897 return err; 1898 1899 dsi->mode_flags = desc->flags; 1900 dsi->format = desc->format; 1901 dsi->lanes = desc->lanes; 1902 1903 return mipi_dsi_attach(dsi); 1904 } 1905 1906 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 1907 { 1908 int err; 1909 1910 err = mipi_dsi_detach(dsi); 1911 if (err < 0) 1912 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 1913 1914 return panel_simple_remove(&dsi->dev); 1915 } 1916 1917 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 1918 { 1919 panel_simple_shutdown(&dsi->dev); 1920 } 1921 1922 static struct mipi_dsi_driver panel_simple_dsi_driver = { 1923 .driver = { 1924 .name = "panel-simple-dsi", 1925 .of_match_table = dsi_of_match, 1926 }, 1927 .probe = panel_simple_dsi_probe, 1928 .remove = panel_simple_dsi_remove, 1929 .shutdown = panel_simple_dsi_shutdown, 1930 }; 1931 1932 static int __init panel_simple_init(void) 1933 { 1934 int err; 1935 1936 err = platform_driver_register(&panel_simple_platform_driver); 1937 if (err < 0) 1938 return err; 1939 1940 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 1941 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 1942 if (err < 0) 1943 return err; 1944 } 1945 1946 return 0; 1947 } 1948 module_init(panel_simple_init); 1949 1950 static void __exit panel_simple_exit(void) 1951 { 1952 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 1953 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 1954 1955 platform_driver_unregister(&panel_simple_platform_driver); 1956 } 1957 module_exit(panel_simple_exit); 1958 1959 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1960 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 1961 MODULE_LICENSE("GPL and additional rights"); 1962