1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get_boottime(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) 579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 580 "failed to request GPIO\n"); 581 582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 583 if (err) { 584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 585 return err; 586 } 587 588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 589 if (ddc) { 590 panel->ddc = of_find_i2c_adapter_by_node(ddc); 591 of_node_put(ddc); 592 593 if (!panel->ddc) 594 return -EPROBE_DEFER; 595 } 596 597 if (desc == &panel_dpi) { 598 /* Handle the generic panel-dpi binding */ 599 err = panel_dpi_probe(dev, panel); 600 if (err) 601 goto free_ddc; 602 desc = panel->desc; 603 } else { 604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 605 panel_simple_parse_panel_timing_node(dev, panel, &dt); 606 } 607 608 connector_type = desc->connector_type; 609 /* Catch common mistakes for panels. */ 610 switch (connector_type) { 611 case 0: 612 dev_warn(dev, "Specify missing connector_type\n"); 613 connector_type = DRM_MODE_CONNECTOR_DPI; 614 break; 615 case DRM_MODE_CONNECTOR_LVDS: 616 WARN_ON(desc->bus_flags & 617 ~(DRM_BUS_FLAG_DE_LOW | 618 DRM_BUS_FLAG_DE_HIGH | 619 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 620 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bpc != 6); 626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 628 desc->bpc != 8); 629 break; 630 case DRM_MODE_CONNECTOR_eDP: 631 dev_warn(dev, "eDP panels moved to panel-edp\n"); 632 err = -EINVAL; 633 goto free_ddc; 634 case DRM_MODE_CONNECTOR_DSI: 635 if (desc->bpc != 6 && desc->bpc != 8) 636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 637 break; 638 case DRM_MODE_CONNECTOR_DPI: 639 bus_flags = DRM_BUS_FLAG_DE_LOW | 640 DRM_BUS_FLAG_DE_HIGH | 641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 647 if (desc->bus_flags & ~bus_flags) 648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 649 if (!(desc->bus_flags & bus_flags)) 650 dev_warn(dev, "Specify missing bus_flags\n"); 651 if (desc->bus_format == 0) 652 dev_warn(dev, "Specify missing bus_format\n"); 653 if (desc->bpc != 6 && desc->bpc != 8) 654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 655 break; 656 default: 657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 658 connector_type = DRM_MODE_CONNECTOR_DPI; 659 break; 660 } 661 662 dev_set_drvdata(dev, panel); 663 664 /* 665 * We use runtime PM for prepare / unprepare since those power the panel 666 * on and off and those can be very slow operations. This is important 667 * to optimize powering the panel on briefly to read the EDID before 668 * fully enabling the panel. 669 */ 670 pm_runtime_enable(dev); 671 pm_runtime_set_autosuspend_delay(dev, 1000); 672 pm_runtime_use_autosuspend(dev); 673 674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 675 676 err = drm_panel_of_backlight(&panel->base); 677 if (err) { 678 dev_err_probe(dev, err, "Could not find backlight\n"); 679 goto disable_pm_runtime; 680 } 681 682 drm_panel_add(&panel->base); 683 684 return 0; 685 686 disable_pm_runtime: 687 pm_runtime_dont_use_autosuspend(dev); 688 pm_runtime_disable(dev); 689 free_ddc: 690 if (panel->ddc) 691 put_device(&panel->ddc->dev); 692 693 return err; 694 } 695 696 static void panel_simple_remove(struct device *dev) 697 { 698 struct panel_simple *panel = dev_get_drvdata(dev); 699 700 drm_panel_remove(&panel->base); 701 drm_panel_disable(&panel->base); 702 drm_panel_unprepare(&panel->base); 703 704 pm_runtime_dont_use_autosuspend(dev); 705 pm_runtime_disable(dev); 706 if (panel->ddc) 707 put_device(&panel->ddc->dev); 708 } 709 710 static void panel_simple_shutdown(struct device *dev) 711 { 712 struct panel_simple *panel = dev_get_drvdata(dev); 713 714 drm_panel_disable(&panel->base); 715 drm_panel_unprepare(&panel->base); 716 } 717 718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 719 .clock = 71100, 720 .hdisplay = 1280, 721 .hsync_start = 1280 + 40, 722 .hsync_end = 1280 + 40 + 80, 723 .htotal = 1280 + 40 + 80 + 40, 724 .vdisplay = 800, 725 .vsync_start = 800 + 3, 726 .vsync_end = 800 + 3 + 10, 727 .vtotal = 800 + 3 + 10 + 10, 728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 729 }; 730 731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 732 .modes = &ire_am_1280800n3tzqw_t00h_mode, 733 .num_modes = 1, 734 .bpc = 8, 735 .size = { 736 .width = 217, 737 .height = 136, 738 }, 739 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 742 }; 743 744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 745 .clock = 9000, 746 .hdisplay = 480, 747 .hsync_start = 480 + 2, 748 .hsync_end = 480 + 2 + 41, 749 .htotal = 480 + 2 + 41 + 2, 750 .vdisplay = 272, 751 .vsync_start = 272 + 2, 752 .vsync_end = 272 + 2 + 10, 753 .vtotal = 272 + 2 + 10 + 2, 754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 755 }; 756 757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 758 .modes = &ire_am_480272h3tmqw_t01h_mode, 759 .num_modes = 1, 760 .bpc = 8, 761 .size = { 762 .width = 105, 763 .height = 67, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 766 }; 767 768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 769 .clock = 33333, 770 .hdisplay = 800, 771 .hsync_start = 800 + 0, 772 .hsync_end = 800 + 0 + 255, 773 .htotal = 800 + 0 + 255 + 0, 774 .vdisplay = 480, 775 .vsync_start = 480 + 2, 776 .vsync_end = 480 + 2 + 45, 777 .vtotal = 480 + 2 + 45 + 0, 778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 779 }; 780 781 static const struct panel_desc ampire_am800480r3tmqwa1h = { 782 .modes = &ire_am800480r3tmqwa1h_mode, 783 .num_modes = 1, 784 .bpc = 6, 785 .size = { 786 .width = 152, 787 .height = 91, 788 }, 789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 790 }; 791 792 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 793 .pixelclock = { 34500000, 39600000, 50400000 }, 794 .hactive = { 800, 800, 800 }, 795 .hfront_porch = { 12, 112, 312 }, 796 .hback_porch = { 87, 87, 48 }, 797 .hsync_len = { 1, 1, 40 }, 798 .vactive = { 600, 600, 600 }, 799 .vfront_porch = { 1, 21, 61 }, 800 .vback_porch = { 38, 38, 19 }, 801 .vsync_len = { 1, 1, 20 }, 802 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 803 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 804 DISPLAY_FLAGS_SYNC_POSEDGE, 805 }; 806 807 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 808 .timings = &ire_am800600p5tmqw_tb8h_timing, 809 .num_timings = 1, 810 .bpc = 6, 811 .size = { 812 .width = 162, 813 .height = 122, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 817 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 818 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 819 .connector_type = DRM_MODE_CONNECTOR_DPI, 820 }; 821 822 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 823 .pixelclock = { 26400000, 33300000, 46800000 }, 824 .hactive = { 800, 800, 800 }, 825 .hfront_porch = { 16, 210, 354 }, 826 .hback_porch = { 45, 36, 6 }, 827 .hsync_len = { 1, 10, 40 }, 828 .vactive = { 480, 480, 480 }, 829 .vfront_porch = { 7, 22, 147 }, 830 .vback_porch = { 22, 13, 3 }, 831 .vsync_len = { 1, 10, 20 }, 832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 834 }; 835 836 static const struct panel_desc armadeus_st0700_adapt = { 837 .timings = &santek_st0700i5y_rbslw_f_timing, 838 .num_timings = 1, 839 .bpc = 6, 840 .size = { 841 .width = 154, 842 .height = 86, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 846 }; 847 848 static const struct drm_display_mode auo_b101aw03_mode = { 849 .clock = 51450, 850 .hdisplay = 1024, 851 .hsync_start = 1024 + 156, 852 .hsync_end = 1024 + 156 + 8, 853 .htotal = 1024 + 156 + 8 + 156, 854 .vdisplay = 600, 855 .vsync_start = 600 + 16, 856 .vsync_end = 600 + 16 + 6, 857 .vtotal = 600 + 16 + 6 + 16, 858 }; 859 860 static const struct panel_desc auo_b101aw03 = { 861 .modes = &auo_b101aw03_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 223, 866 .height = 125, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 869 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 871 }; 872 873 static const struct drm_display_mode auo_b101xtn01_mode = { 874 .clock = 72000, 875 .hdisplay = 1366, 876 .hsync_start = 1366 + 20, 877 .hsync_end = 1366 + 20 + 70, 878 .htotal = 1366 + 20 + 70, 879 .vdisplay = 768, 880 .vsync_start = 768 + 14, 881 .vsync_end = 768 + 14 + 42, 882 .vtotal = 768 + 14 + 42, 883 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 884 }; 885 886 static const struct panel_desc auo_b101xtn01 = { 887 .modes = &auo_b101xtn01_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 }; 895 896 static const struct display_timing auo_g070vvn01_timings = { 897 .pixelclock = { 33300000, 34209000, 45000000 }, 898 .hactive = { 800, 800, 800 }, 899 .hfront_porch = { 20, 40, 200 }, 900 .hback_porch = { 87, 40, 1 }, 901 .hsync_len = { 1, 48, 87 }, 902 .vactive = { 480, 480, 480 }, 903 .vfront_porch = { 5, 13, 200 }, 904 .vback_porch = { 31, 31, 29 }, 905 .vsync_len = { 1, 1, 3 }, 906 }; 907 908 static const struct panel_desc auo_g070vvn01 = { 909 .timings = &auo_g070vvn01_timings, 910 .num_timings = 1, 911 .bpc = 8, 912 .size = { 913 .width = 152, 914 .height = 91, 915 }, 916 .delay = { 917 .prepare = 200, 918 .enable = 50, 919 .disable = 50, 920 .unprepare = 1000, 921 }, 922 }; 923 924 static const struct drm_display_mode auo_g101evn010_mode = { 925 .clock = 68930, 926 .hdisplay = 1280, 927 .hsync_start = 1280 + 82, 928 .hsync_end = 1280 + 82 + 2, 929 .htotal = 1280 + 82 + 2 + 84, 930 .vdisplay = 800, 931 .vsync_start = 800 + 8, 932 .vsync_end = 800 + 8 + 2, 933 .vtotal = 800 + 8 + 2 + 6, 934 }; 935 936 static const struct panel_desc auo_g101evn010 = { 937 .modes = &auo_g101evn010_mode, 938 .num_modes = 1, 939 .bpc = 6, 940 .size = { 941 .width = 216, 942 .height = 135, 943 }, 944 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 946 }; 947 948 static const struct drm_display_mode auo_g104sn02_mode = { 949 .clock = 40000, 950 .hdisplay = 800, 951 .hsync_start = 800 + 40, 952 .hsync_end = 800 + 40 + 216, 953 .htotal = 800 + 40 + 216 + 128, 954 .vdisplay = 600, 955 .vsync_start = 600 + 10, 956 .vsync_end = 600 + 10 + 35, 957 .vtotal = 600 + 10 + 35 + 2, 958 }; 959 960 static const struct panel_desc auo_g104sn02 = { 961 .modes = &auo_g104sn02_mode, 962 .num_modes = 1, 963 .bpc = 8, 964 .size = { 965 .width = 211, 966 .height = 158, 967 }, 968 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 970 }; 971 972 static const struct drm_display_mode auo_g121ean01_mode = { 973 .clock = 66700, 974 .hdisplay = 1280, 975 .hsync_start = 1280 + 58, 976 .hsync_end = 1280 + 58 + 8, 977 .htotal = 1280 + 58 + 8 + 70, 978 .vdisplay = 800, 979 .vsync_start = 800 + 6, 980 .vsync_end = 800 + 6 + 4, 981 .vtotal = 800 + 6 + 4 + 10, 982 }; 983 984 static const struct panel_desc auo_g121ean01 = { 985 .modes = &auo_g121ean01_mode, 986 .num_modes = 1, 987 .bpc = 8, 988 .size = { 989 .width = 261, 990 .height = 163, 991 }, 992 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 993 .connector_type = DRM_MODE_CONNECTOR_LVDS, 994 }; 995 996 static const struct display_timing auo_g133han01_timings = { 997 .pixelclock = { 134000000, 141200000, 149000000 }, 998 .hactive = { 1920, 1920, 1920 }, 999 .hfront_porch = { 39, 58, 77 }, 1000 .hback_porch = { 59, 88, 117 }, 1001 .hsync_len = { 28, 42, 56 }, 1002 .vactive = { 1080, 1080, 1080 }, 1003 .vfront_porch = { 3, 8, 11 }, 1004 .vback_porch = { 5, 14, 19 }, 1005 .vsync_len = { 4, 14, 19 }, 1006 }; 1007 1008 static const struct panel_desc auo_g133han01 = { 1009 .timings = &auo_g133han01_timings, 1010 .num_timings = 1, 1011 .bpc = 8, 1012 .size = { 1013 .width = 293, 1014 .height = 165, 1015 }, 1016 .delay = { 1017 .prepare = 200, 1018 .enable = 50, 1019 .disable = 50, 1020 .unprepare = 1000, 1021 }, 1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1024 }; 1025 1026 static const struct drm_display_mode auo_g156xtn01_mode = { 1027 .clock = 76000, 1028 .hdisplay = 1366, 1029 .hsync_start = 1366 + 33, 1030 .hsync_end = 1366 + 33 + 67, 1031 .htotal = 1560, 1032 .vdisplay = 768, 1033 .vsync_start = 768 + 4, 1034 .vsync_end = 768 + 4 + 4, 1035 .vtotal = 806, 1036 }; 1037 1038 static const struct panel_desc auo_g156xtn01 = { 1039 .modes = &auo_g156xtn01_mode, 1040 .num_modes = 1, 1041 .bpc = 8, 1042 .size = { 1043 .width = 344, 1044 .height = 194, 1045 }, 1046 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1048 }; 1049 1050 static const struct display_timing auo_g185han01_timings = { 1051 .pixelclock = { 120000000, 144000000, 175000000 }, 1052 .hactive = { 1920, 1920, 1920 }, 1053 .hfront_porch = { 36, 120, 148 }, 1054 .hback_porch = { 24, 88, 108 }, 1055 .hsync_len = { 20, 48, 64 }, 1056 .vactive = { 1080, 1080, 1080 }, 1057 .vfront_porch = { 6, 10, 40 }, 1058 .vback_porch = { 2, 5, 20 }, 1059 .vsync_len = { 2, 5, 20 }, 1060 }; 1061 1062 static const struct panel_desc auo_g185han01 = { 1063 .timings = &auo_g185han01_timings, 1064 .num_timings = 1, 1065 .bpc = 8, 1066 .size = { 1067 .width = 409, 1068 .height = 230, 1069 }, 1070 .delay = { 1071 .prepare = 50, 1072 .enable = 200, 1073 .disable = 110, 1074 .unprepare = 1000, 1075 }, 1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1077 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1078 }; 1079 1080 static const struct display_timing auo_g190ean01_timings = { 1081 .pixelclock = { 90000000, 108000000, 135000000 }, 1082 .hactive = { 1280, 1280, 1280 }, 1083 .hfront_porch = { 126, 184, 1266 }, 1084 .hback_porch = { 84, 122, 844 }, 1085 .hsync_len = { 70, 102, 704 }, 1086 .vactive = { 1024, 1024, 1024 }, 1087 .vfront_porch = { 4, 26, 76 }, 1088 .vback_porch = { 2, 8, 25 }, 1089 .vsync_len = { 2, 8, 25 }, 1090 }; 1091 1092 static const struct panel_desc auo_g190ean01 = { 1093 .timings = &auo_g190ean01_timings, 1094 .num_timings = 1, 1095 .bpc = 8, 1096 .size = { 1097 .width = 376, 1098 .height = 301, 1099 }, 1100 .delay = { 1101 .prepare = 50, 1102 .enable = 200, 1103 .disable = 110, 1104 .unprepare = 1000, 1105 }, 1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1108 }; 1109 1110 static const struct display_timing auo_p320hvn03_timings = { 1111 .pixelclock = { 106000000, 148500000, 164000000 }, 1112 .hactive = { 1920, 1920, 1920 }, 1113 .hfront_porch = { 25, 50, 130 }, 1114 .hback_porch = { 25, 50, 130 }, 1115 .hsync_len = { 20, 40, 105 }, 1116 .vactive = { 1080, 1080, 1080 }, 1117 .vfront_porch = { 8, 17, 150 }, 1118 .vback_porch = { 8, 17, 150 }, 1119 .vsync_len = { 4, 11, 100 }, 1120 }; 1121 1122 static const struct panel_desc auo_p320hvn03 = { 1123 .timings = &auo_p320hvn03_timings, 1124 .num_timings = 1, 1125 .bpc = 8, 1126 .size = { 1127 .width = 698, 1128 .height = 393, 1129 }, 1130 .delay = { 1131 .prepare = 1, 1132 .enable = 450, 1133 .unprepare = 500, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct drm_display_mode auo_t215hvn01_mode = { 1140 .clock = 148800, 1141 .hdisplay = 1920, 1142 .hsync_start = 1920 + 88, 1143 .hsync_end = 1920 + 88 + 44, 1144 .htotal = 1920 + 88 + 44 + 148, 1145 .vdisplay = 1080, 1146 .vsync_start = 1080 + 4, 1147 .vsync_end = 1080 + 4 + 5, 1148 .vtotal = 1080 + 4 + 5 + 36, 1149 }; 1150 1151 static const struct panel_desc auo_t215hvn01 = { 1152 .modes = &auo_t215hvn01_mode, 1153 .num_modes = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 430, 1157 .height = 270, 1158 }, 1159 .delay = { 1160 .disable = 5, 1161 .unprepare = 1000, 1162 } 1163 }; 1164 1165 static const struct drm_display_mode avic_tm070ddh03_mode = { 1166 .clock = 51200, 1167 .hdisplay = 1024, 1168 .hsync_start = 1024 + 160, 1169 .hsync_end = 1024 + 160 + 4, 1170 .htotal = 1024 + 160 + 4 + 156, 1171 .vdisplay = 600, 1172 .vsync_start = 600 + 17, 1173 .vsync_end = 600 + 17 + 1, 1174 .vtotal = 600 + 17 + 1 + 17, 1175 }; 1176 1177 static const struct panel_desc avic_tm070ddh03 = { 1178 .modes = &avic_tm070ddh03_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 154, 1183 .height = 90, 1184 }, 1185 .delay = { 1186 .prepare = 20, 1187 .enable = 200, 1188 .disable = 200, 1189 }, 1190 }; 1191 1192 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1193 .clock = 30000, 1194 .hdisplay = 800, 1195 .hsync_start = 800 + 40, 1196 .hsync_end = 800 + 40 + 48, 1197 .htotal = 800 + 40 + 48 + 40, 1198 .vdisplay = 480, 1199 .vsync_start = 480 + 13, 1200 .vsync_end = 480 + 13 + 3, 1201 .vtotal = 480 + 13 + 3 + 29, 1202 }; 1203 1204 static const struct panel_desc bananapi_s070wv20_ct16 = { 1205 .modes = &bananapi_s070wv20_ct16_mode, 1206 .num_modes = 1, 1207 .bpc = 6, 1208 .size = { 1209 .width = 154, 1210 .height = 86, 1211 }, 1212 }; 1213 1214 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1215 .pixelclock = { 69922000, 71000000, 72293000 }, 1216 .hactive = { 1280, 1280, 1280 }, 1217 .hfront_porch = { 48, 48, 48 }, 1218 .hback_porch = { 80, 80, 80 }, 1219 .hsync_len = { 32, 32, 32 }, 1220 .vactive = { 800, 800, 800 }, 1221 .vfront_porch = { 3, 3, 3 }, 1222 .vback_porch = { 14, 14, 14 }, 1223 .vsync_len = { 6, 6, 6 }, 1224 }; 1225 1226 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1227 .timings = &boe_ev121wxm_n10_1850_timing, 1228 .num_timings = 1, 1229 .bpc = 8, 1230 .size = { 1231 .width = 261, 1232 .height = 163, 1233 }, 1234 .delay = { 1235 .prepare = 9, 1236 .enable = 300, 1237 .unprepare = 300, 1238 .disable = 560, 1239 }, 1240 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1241 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1242 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1243 }; 1244 1245 static const struct drm_display_mode boe_hv070wsa_mode = { 1246 .clock = 42105, 1247 .hdisplay = 1024, 1248 .hsync_start = 1024 + 30, 1249 .hsync_end = 1024 + 30 + 30, 1250 .htotal = 1024 + 30 + 30 + 30, 1251 .vdisplay = 600, 1252 .vsync_start = 600 + 10, 1253 .vsync_end = 600 + 10 + 10, 1254 .vtotal = 600 + 10 + 10 + 10, 1255 }; 1256 1257 static const struct panel_desc boe_hv070wsa = { 1258 .modes = &boe_hv070wsa_mode, 1259 .num_modes = 1, 1260 .bpc = 8, 1261 .size = { 1262 .width = 154, 1263 .height = 90, 1264 }, 1265 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1266 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1268 }; 1269 1270 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1271 .clock = 9000, 1272 .hdisplay = 480, 1273 .hsync_start = 480 + 5, 1274 .hsync_end = 480 + 5 + 5, 1275 .htotal = 480 + 5 + 5 + 40, 1276 .vdisplay = 272, 1277 .vsync_start = 272 + 8, 1278 .vsync_end = 272 + 8 + 8, 1279 .vtotal = 272 + 8 + 8 + 8, 1280 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1281 }; 1282 1283 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1284 .modes = &cdtech_s043wq26h_ct7_mode, 1285 .num_modes = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 95, 1289 .height = 54, 1290 }, 1291 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1292 }; 1293 1294 /* S070PWS19HP-FC21 2017/04/22 */ 1295 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1296 .clock = 51200, 1297 .hdisplay = 1024, 1298 .hsync_start = 1024 + 160, 1299 .hsync_end = 1024 + 160 + 20, 1300 .htotal = 1024 + 160 + 20 + 140, 1301 .vdisplay = 600, 1302 .vsync_start = 600 + 12, 1303 .vsync_end = 600 + 12 + 3, 1304 .vtotal = 600 + 12 + 3 + 20, 1305 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1306 }; 1307 1308 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1309 .modes = &cdtech_s070pws19hp_fc21_mode, 1310 .num_modes = 1, 1311 .bpc = 6, 1312 .size = { 1313 .width = 154, 1314 .height = 86, 1315 }, 1316 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1317 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1318 .connector_type = DRM_MODE_CONNECTOR_DPI, 1319 }; 1320 1321 /* S070SWV29HG-DC44 2017/09/21 */ 1322 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1323 .clock = 33300, 1324 .hdisplay = 800, 1325 .hsync_start = 800 + 210, 1326 .hsync_end = 800 + 210 + 2, 1327 .htotal = 800 + 210 + 2 + 44, 1328 .vdisplay = 480, 1329 .vsync_start = 480 + 22, 1330 .vsync_end = 480 + 22 + 2, 1331 .vtotal = 480 + 22 + 2 + 21, 1332 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1333 }; 1334 1335 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1336 .modes = &cdtech_s070swv29hg_dc44_mode, 1337 .num_modes = 1, 1338 .bpc = 6, 1339 .size = { 1340 .width = 154, 1341 .height = 86, 1342 }, 1343 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1344 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1345 .connector_type = DRM_MODE_CONNECTOR_DPI, 1346 }; 1347 1348 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1349 .clock = 35000, 1350 .hdisplay = 800, 1351 .hsync_start = 800 + 40, 1352 .hsync_end = 800 + 40 + 40, 1353 .htotal = 800 + 40 + 40 + 48, 1354 .vdisplay = 480, 1355 .vsync_start = 480 + 29, 1356 .vsync_end = 480 + 29 + 13, 1357 .vtotal = 480 + 29 + 13 + 3, 1358 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1359 }; 1360 1361 static const struct panel_desc cdtech_s070wv95_ct16 = { 1362 .modes = &cdtech_s070wv95_ct16_mode, 1363 .num_modes = 1, 1364 .bpc = 8, 1365 .size = { 1366 .width = 154, 1367 .height = 85, 1368 }, 1369 }; 1370 1371 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1372 .pixelclock = { 68900000, 71100000, 73400000 }, 1373 .hactive = { 1280, 1280, 1280 }, 1374 .hfront_porch = { 65, 80, 95 }, 1375 .hback_porch = { 64, 79, 94 }, 1376 .hsync_len = { 1, 1, 1 }, 1377 .vactive = { 800, 800, 800 }, 1378 .vfront_porch = { 7, 11, 14 }, 1379 .vback_porch = { 7, 11, 14 }, 1380 .vsync_len = { 1, 1, 1 }, 1381 .flags = DISPLAY_FLAGS_DE_HIGH, 1382 }; 1383 1384 static const struct panel_desc chefree_ch101olhlwh_002 = { 1385 .timings = &chefree_ch101olhlwh_002_timing, 1386 .num_timings = 1, 1387 .bpc = 8, 1388 .size = { 1389 .width = 217, 1390 .height = 135, 1391 }, 1392 .delay = { 1393 .enable = 200, 1394 .disable = 200, 1395 }, 1396 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1397 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1399 }; 1400 1401 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1402 .clock = 66770, 1403 .hdisplay = 800, 1404 .hsync_start = 800 + 49, 1405 .hsync_end = 800 + 49 + 33, 1406 .htotal = 800 + 49 + 33 + 17, 1407 .vdisplay = 1280, 1408 .vsync_start = 1280 + 1, 1409 .vsync_end = 1280 + 1 + 7, 1410 .vtotal = 1280 + 1 + 7 + 15, 1411 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1412 }; 1413 1414 static const struct panel_desc chunghwa_claa070wp03xg = { 1415 .modes = &chunghwa_claa070wp03xg_mode, 1416 .num_modes = 1, 1417 .bpc = 6, 1418 .size = { 1419 .width = 94, 1420 .height = 150, 1421 }, 1422 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1423 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1425 }; 1426 1427 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1428 .clock = 72070, 1429 .hdisplay = 1366, 1430 .hsync_start = 1366 + 58, 1431 .hsync_end = 1366 + 58 + 58, 1432 .htotal = 1366 + 58 + 58 + 58, 1433 .vdisplay = 768, 1434 .vsync_start = 768 + 4, 1435 .vsync_end = 768 + 4 + 4, 1436 .vtotal = 768 + 4 + 4 + 4, 1437 }; 1438 1439 static const struct panel_desc chunghwa_claa101wa01a = { 1440 .modes = &chunghwa_claa101wa01a_mode, 1441 .num_modes = 1, 1442 .bpc = 6, 1443 .size = { 1444 .width = 220, 1445 .height = 120, 1446 }, 1447 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1448 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1449 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1450 }; 1451 1452 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1453 .clock = 69300, 1454 .hdisplay = 1366, 1455 .hsync_start = 1366 + 48, 1456 .hsync_end = 1366 + 48 + 32, 1457 .htotal = 1366 + 48 + 32 + 20, 1458 .vdisplay = 768, 1459 .vsync_start = 768 + 16, 1460 .vsync_end = 768 + 16 + 8, 1461 .vtotal = 768 + 16 + 8 + 16, 1462 }; 1463 1464 static const struct panel_desc chunghwa_claa101wb01 = { 1465 .modes = &chunghwa_claa101wb01_mode, 1466 .num_modes = 1, 1467 .bpc = 6, 1468 .size = { 1469 .width = 223, 1470 .height = 125, 1471 }, 1472 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1473 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1474 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1475 }; 1476 1477 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1478 .pixelclock = { 5000000, 9000000, 12000000 }, 1479 .hactive = { 480, 480, 480 }, 1480 .hfront_porch = { 12, 12, 12 }, 1481 .hback_porch = { 12, 12, 12 }, 1482 .hsync_len = { 21, 21, 21 }, 1483 .vactive = { 272, 272, 272 }, 1484 .vfront_porch = { 4, 4, 4 }, 1485 .vback_porch = { 4, 4, 4 }, 1486 .vsync_len = { 8, 8, 8 }, 1487 }; 1488 1489 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1490 .timings = &dataimage_fg040346dsswbg04_timing, 1491 .num_timings = 1, 1492 .bpc = 8, 1493 .size = { 1494 .width = 95, 1495 .height = 54, 1496 }, 1497 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1498 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1499 .connector_type = DRM_MODE_CONNECTOR_DPI, 1500 }; 1501 1502 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1503 .pixelclock = { 68900000, 71110000, 73400000 }, 1504 .hactive = { 1280, 1280, 1280 }, 1505 .vactive = { 800, 800, 800 }, 1506 .hback_porch = { 100, 100, 100 }, 1507 .hfront_porch = { 100, 100, 100 }, 1508 .vback_porch = { 5, 5, 5 }, 1509 .vfront_porch = { 5, 5, 5 }, 1510 .hsync_len = { 24, 24, 24 }, 1511 .vsync_len = { 3, 3, 3 }, 1512 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1513 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1514 }; 1515 1516 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1517 .timings = &dataimage_fg1001l0dsswmg01_timing, 1518 .num_timings = 1, 1519 .bpc = 8, 1520 .size = { 1521 .width = 217, 1522 .height = 136, 1523 }, 1524 }; 1525 1526 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1527 .clock = 33260, 1528 .hdisplay = 800, 1529 .hsync_start = 800 + 40, 1530 .hsync_end = 800 + 40 + 128, 1531 .htotal = 800 + 40 + 128 + 88, 1532 .vdisplay = 480, 1533 .vsync_start = 480 + 10, 1534 .vsync_end = 480 + 10 + 2, 1535 .vtotal = 480 + 10 + 2 + 33, 1536 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1537 }; 1538 1539 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1540 .modes = &dataimage_scf0700c48ggu18_mode, 1541 .num_modes = 1, 1542 .bpc = 8, 1543 .size = { 1544 .width = 152, 1545 .height = 91, 1546 }, 1547 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1548 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1549 }; 1550 1551 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1552 .pixelclock = { 45000000, 51200000, 57000000 }, 1553 .hactive = { 1024, 1024, 1024 }, 1554 .hfront_porch = { 100, 106, 113 }, 1555 .hback_porch = { 100, 106, 113 }, 1556 .hsync_len = { 100, 108, 114 }, 1557 .vactive = { 600, 600, 600 }, 1558 .vfront_porch = { 8, 11, 15 }, 1559 .vback_porch = { 8, 11, 15 }, 1560 .vsync_len = { 9, 13, 15 }, 1561 .flags = DISPLAY_FLAGS_DE_HIGH, 1562 }; 1563 1564 static const struct panel_desc dlc_dlc0700yzg_1 = { 1565 .timings = &dlc_dlc0700yzg_1_timing, 1566 .num_timings = 1, 1567 .bpc = 6, 1568 .size = { 1569 .width = 154, 1570 .height = 86, 1571 }, 1572 .delay = { 1573 .prepare = 30, 1574 .enable = 200, 1575 .disable = 200, 1576 }, 1577 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1579 }; 1580 1581 static const struct display_timing dlc_dlc1010gig_timing = { 1582 .pixelclock = { 68900000, 71100000, 73400000 }, 1583 .hactive = { 1280, 1280, 1280 }, 1584 .hfront_porch = { 43, 53, 63 }, 1585 .hback_porch = { 43, 53, 63 }, 1586 .hsync_len = { 44, 54, 64 }, 1587 .vactive = { 800, 800, 800 }, 1588 .vfront_porch = { 5, 8, 11 }, 1589 .vback_porch = { 5, 8, 11 }, 1590 .vsync_len = { 5, 7, 11 }, 1591 .flags = DISPLAY_FLAGS_DE_HIGH, 1592 }; 1593 1594 static const struct panel_desc dlc_dlc1010gig = { 1595 .timings = &dlc_dlc1010gig_timing, 1596 .num_timings = 1, 1597 .bpc = 8, 1598 .size = { 1599 .width = 216, 1600 .height = 135, 1601 }, 1602 .delay = { 1603 .prepare = 60, 1604 .enable = 150, 1605 .disable = 100, 1606 .unprepare = 60, 1607 }, 1608 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1609 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1610 }; 1611 1612 static const struct drm_display_mode edt_et035012dm6_mode = { 1613 .clock = 6500, 1614 .hdisplay = 320, 1615 .hsync_start = 320 + 20, 1616 .hsync_end = 320 + 20 + 30, 1617 .htotal = 320 + 20 + 68, 1618 .vdisplay = 240, 1619 .vsync_start = 240 + 4, 1620 .vsync_end = 240 + 4 + 4, 1621 .vtotal = 240 + 4 + 4 + 14, 1622 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1623 }; 1624 1625 static const struct panel_desc edt_et035012dm6 = { 1626 .modes = &edt_et035012dm6_mode, 1627 .num_modes = 1, 1628 .bpc = 8, 1629 .size = { 1630 .width = 70, 1631 .height = 52, 1632 }, 1633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1634 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1635 }; 1636 1637 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1638 .clock = 6520, 1639 .hdisplay = 320, 1640 .hsync_start = 320 + 20, 1641 .hsync_end = 320 + 20 + 68, 1642 .htotal = 320 + 20 + 68, 1643 .vdisplay = 240, 1644 .vsync_start = 240 + 4, 1645 .vsync_end = 240 + 4 + 18, 1646 .vtotal = 240 + 4 + 18, 1647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1648 }; 1649 1650 static const struct panel_desc edt_etm0350g0dh6 = { 1651 .modes = &edt_etm0350g0dh6_mode, 1652 .num_modes = 1, 1653 .bpc = 6, 1654 .size = { 1655 .width = 70, 1656 .height = 53, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1659 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1660 .connector_type = DRM_MODE_CONNECTOR_DPI, 1661 }; 1662 1663 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1664 .clock = 10870, 1665 .hdisplay = 480, 1666 .hsync_start = 480 + 8, 1667 .hsync_end = 480 + 8 + 4, 1668 .htotal = 480 + 8 + 4 + 41, 1669 1670 /* 1671 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1672 * fb_align 1673 */ 1674 1675 .vdisplay = 288, 1676 .vsync_start = 288 + 2, 1677 .vsync_end = 288 + 2 + 4, 1678 .vtotal = 288 + 2 + 4 + 10, 1679 }; 1680 1681 static const struct panel_desc edt_etm043080dh6gp = { 1682 .modes = &edt_etm043080dh6gp_mode, 1683 .num_modes = 1, 1684 .bpc = 8, 1685 .size = { 1686 .width = 100, 1687 .height = 65, 1688 }, 1689 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1690 .connector_type = DRM_MODE_CONNECTOR_DPI, 1691 }; 1692 1693 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1694 .clock = 9000, 1695 .hdisplay = 480, 1696 .hsync_start = 480 + 2, 1697 .hsync_end = 480 + 2 + 41, 1698 .htotal = 480 + 2 + 41 + 2, 1699 .vdisplay = 272, 1700 .vsync_start = 272 + 2, 1701 .vsync_end = 272 + 2 + 10, 1702 .vtotal = 272 + 2 + 10 + 2, 1703 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1704 }; 1705 1706 static const struct panel_desc edt_etm0430g0dh6 = { 1707 .modes = &edt_etm0430g0dh6_mode, 1708 .num_modes = 1, 1709 .bpc = 6, 1710 .size = { 1711 .width = 95, 1712 .height = 54, 1713 }, 1714 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1715 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1716 .connector_type = DRM_MODE_CONNECTOR_DPI, 1717 }; 1718 1719 static const struct drm_display_mode edt_et057090dhu_mode = { 1720 .clock = 25175, 1721 .hdisplay = 640, 1722 .hsync_start = 640 + 16, 1723 .hsync_end = 640 + 16 + 30, 1724 .htotal = 640 + 16 + 30 + 114, 1725 .vdisplay = 480, 1726 .vsync_start = 480 + 10, 1727 .vsync_end = 480 + 10 + 3, 1728 .vtotal = 480 + 10 + 3 + 32, 1729 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1730 }; 1731 1732 static const struct panel_desc edt_et057090dhu = { 1733 .modes = &edt_et057090dhu_mode, 1734 .num_modes = 1, 1735 .bpc = 6, 1736 .size = { 1737 .width = 115, 1738 .height = 86, 1739 }, 1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1742 .connector_type = DRM_MODE_CONNECTOR_DPI, 1743 }; 1744 1745 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1746 .clock = 33260, 1747 .hdisplay = 800, 1748 .hsync_start = 800 + 40, 1749 .hsync_end = 800 + 40 + 128, 1750 .htotal = 800 + 40 + 128 + 88, 1751 .vdisplay = 480, 1752 .vsync_start = 480 + 10, 1753 .vsync_end = 480 + 10 + 2, 1754 .vtotal = 480 + 10 + 2 + 33, 1755 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1756 }; 1757 1758 static const struct panel_desc edt_etm0700g0dh6 = { 1759 .modes = &edt_etm0700g0dh6_mode, 1760 .num_modes = 1, 1761 .bpc = 6, 1762 .size = { 1763 .width = 152, 1764 .height = 91, 1765 }, 1766 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1767 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1768 .connector_type = DRM_MODE_CONNECTOR_DPI, 1769 }; 1770 1771 static const struct panel_desc edt_etm0700g0bdh6 = { 1772 .modes = &edt_etm0700g0dh6_mode, 1773 .num_modes = 1, 1774 .bpc = 6, 1775 .size = { 1776 .width = 152, 1777 .height = 91, 1778 }, 1779 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1780 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1781 .connector_type = DRM_MODE_CONNECTOR_DPI, 1782 }; 1783 1784 static const struct display_timing edt_etml0700y5dha_timing = { 1785 .pixelclock = { 40800000, 51200000, 67200000 }, 1786 .hactive = { 1024, 1024, 1024 }, 1787 .hfront_porch = { 30, 106, 125 }, 1788 .hback_porch = { 30, 106, 125 }, 1789 .hsync_len = { 30, 108, 126 }, 1790 .vactive = { 600, 600, 600 }, 1791 .vfront_porch = { 3, 12, 67}, 1792 .vback_porch = { 3, 12, 67 }, 1793 .vsync_len = { 4, 11, 66 }, 1794 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1795 DISPLAY_FLAGS_DE_HIGH, 1796 }; 1797 1798 static const struct panel_desc edt_etml0700y5dha = { 1799 .timings = &edt_etml0700y5dha_timing, 1800 .num_timings = 1, 1801 .bpc = 8, 1802 .size = { 1803 .width = 155, 1804 .height = 86, 1805 }, 1806 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1807 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1808 }; 1809 1810 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1811 .clock = 25175, 1812 .hdisplay = 640, 1813 .hsync_start = 640, 1814 .hsync_end = 640 + 16, 1815 .htotal = 640 + 16 + 30 + 114, 1816 .vdisplay = 480, 1817 .vsync_start = 480 + 10, 1818 .vsync_end = 480 + 10 + 3, 1819 .vtotal = 480 + 10 + 3 + 35, 1820 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1821 }; 1822 1823 static const struct panel_desc edt_etmv570g2dhu = { 1824 .modes = &edt_etmv570g2dhu_mode, 1825 .num_modes = 1, 1826 .bpc = 6, 1827 .size = { 1828 .width = 115, 1829 .height = 86, 1830 }, 1831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1833 .connector_type = DRM_MODE_CONNECTOR_DPI, 1834 }; 1835 1836 static const struct display_timing eink_vb3300_kca_timing = { 1837 .pixelclock = { 40000000, 40000000, 40000000 }, 1838 .hactive = { 334, 334, 334 }, 1839 .hfront_porch = { 1, 1, 1 }, 1840 .hback_porch = { 1, 1, 1 }, 1841 .hsync_len = { 1, 1, 1 }, 1842 .vactive = { 1405, 1405, 1405 }, 1843 .vfront_porch = { 1, 1, 1 }, 1844 .vback_porch = { 1, 1, 1 }, 1845 .vsync_len = { 1, 1, 1 }, 1846 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1847 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1848 }; 1849 1850 static const struct panel_desc eink_vb3300_kca = { 1851 .timings = &eink_vb3300_kca_timing, 1852 .num_timings = 1, 1853 .bpc = 6, 1854 .size = { 1855 .width = 157, 1856 .height = 209, 1857 }, 1858 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1860 .connector_type = DRM_MODE_CONNECTOR_DPI, 1861 }; 1862 1863 static const struct display_timing evervision_vgg804821_timing = { 1864 .pixelclock = { 27600000, 33300000, 50000000 }, 1865 .hactive = { 800, 800, 800 }, 1866 .hfront_porch = { 40, 66, 70 }, 1867 .hback_porch = { 40, 67, 70 }, 1868 .hsync_len = { 40, 67, 70 }, 1869 .vactive = { 480, 480, 480 }, 1870 .vfront_porch = { 6, 10, 10 }, 1871 .vback_porch = { 7, 11, 11 }, 1872 .vsync_len = { 7, 11, 11 }, 1873 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1874 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1875 DISPLAY_FLAGS_SYNC_NEGEDGE, 1876 }; 1877 1878 static const struct panel_desc evervision_vgg804821 = { 1879 .timings = &evervision_vgg804821_timing, 1880 .num_timings = 1, 1881 .bpc = 8, 1882 .size = { 1883 .width = 108, 1884 .height = 64, 1885 }, 1886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1887 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1888 }; 1889 1890 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1891 .clock = 32260, 1892 .hdisplay = 800, 1893 .hsync_start = 800 + 168, 1894 .hsync_end = 800 + 168 + 64, 1895 .htotal = 800 + 168 + 64 + 88, 1896 .vdisplay = 480, 1897 .vsync_start = 480 + 37, 1898 .vsync_end = 480 + 37 + 2, 1899 .vtotal = 480 + 37 + 2 + 8, 1900 }; 1901 1902 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1903 .modes = &foxlink_fl500wvr00_a0t_mode, 1904 .num_modes = 1, 1905 .bpc = 8, 1906 .size = { 1907 .width = 108, 1908 .height = 65, 1909 }, 1910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1911 }; 1912 1913 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1914 { /* 60 Hz */ 1915 .clock = 6000, 1916 .hdisplay = 320, 1917 .hsync_start = 320 + 44, 1918 .hsync_end = 320 + 44 + 16, 1919 .htotal = 320 + 44 + 16 + 20, 1920 .vdisplay = 240, 1921 .vsync_start = 240 + 2, 1922 .vsync_end = 240 + 2 + 6, 1923 .vtotal = 240 + 2 + 6 + 2, 1924 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1925 }, 1926 { /* 50 Hz */ 1927 .clock = 5400, 1928 .hdisplay = 320, 1929 .hsync_start = 320 + 56, 1930 .hsync_end = 320 + 56 + 16, 1931 .htotal = 320 + 56 + 16 + 40, 1932 .vdisplay = 240, 1933 .vsync_start = 240 + 2, 1934 .vsync_end = 240 + 2 + 6, 1935 .vtotal = 240 + 2 + 6 + 2, 1936 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1937 }, 1938 }; 1939 1940 static const struct panel_desc frida_frd350h54004 = { 1941 .modes = frida_frd350h54004_modes, 1942 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1943 .bpc = 8, 1944 .size = { 1945 .width = 77, 1946 .height = 64, 1947 }, 1948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1950 .connector_type = DRM_MODE_CONNECTOR_DPI, 1951 }; 1952 1953 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1954 .clock = 67185, 1955 .hdisplay = 800, 1956 .hsync_start = 800 + 20, 1957 .hsync_end = 800 + 20 + 24, 1958 .htotal = 800 + 20 + 24 + 20, 1959 .vdisplay = 1280, 1960 .vsync_start = 1280 + 4, 1961 .vsync_end = 1280 + 4 + 8, 1962 .vtotal = 1280 + 4 + 8 + 4, 1963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1964 }; 1965 1966 static const struct panel_desc friendlyarm_hd702e = { 1967 .modes = &friendlyarm_hd702e_mode, 1968 .num_modes = 1, 1969 .size = { 1970 .width = 94, 1971 .height = 151, 1972 }, 1973 }; 1974 1975 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1976 .clock = 9000, 1977 .hdisplay = 480, 1978 .hsync_start = 480 + 5, 1979 .hsync_end = 480 + 5 + 1, 1980 .htotal = 480 + 5 + 1 + 40, 1981 .vdisplay = 272, 1982 .vsync_start = 272 + 8, 1983 .vsync_end = 272 + 8 + 1, 1984 .vtotal = 272 + 8 + 1 + 8, 1985 }; 1986 1987 static const struct panel_desc giantplus_gpg482739qs5 = { 1988 .modes = &giantplus_gpg482739qs5_mode, 1989 .num_modes = 1, 1990 .bpc = 8, 1991 .size = { 1992 .width = 95, 1993 .height = 54, 1994 }, 1995 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1996 }; 1997 1998 static const struct display_timing giantplus_gpm940b0_timing = { 1999 .pixelclock = { 13500000, 27000000, 27500000 }, 2000 .hactive = { 320, 320, 320 }, 2001 .hfront_porch = { 14, 686, 718 }, 2002 .hback_porch = { 50, 70, 255 }, 2003 .hsync_len = { 1, 1, 1 }, 2004 .vactive = { 240, 240, 240 }, 2005 .vfront_porch = { 1, 1, 179 }, 2006 .vback_porch = { 1, 21, 31 }, 2007 .vsync_len = { 1, 1, 6 }, 2008 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2009 }; 2010 2011 static const struct panel_desc giantplus_gpm940b0 = { 2012 .timings = &giantplus_gpm940b0_timing, 2013 .num_timings = 1, 2014 .bpc = 8, 2015 .size = { 2016 .width = 60, 2017 .height = 45, 2018 }, 2019 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2021 }; 2022 2023 static const struct display_timing hannstar_hsd070pww1_timing = { 2024 .pixelclock = { 64300000, 71100000, 82000000 }, 2025 .hactive = { 1280, 1280, 1280 }, 2026 .hfront_porch = { 1, 1, 10 }, 2027 .hback_porch = { 1, 1, 10 }, 2028 /* 2029 * According to the data sheet, the minimum horizontal blanking interval 2030 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2031 * minimum working horizontal blanking interval to be 60 clocks. 2032 */ 2033 .hsync_len = { 58, 158, 661 }, 2034 .vactive = { 800, 800, 800 }, 2035 .vfront_porch = { 1, 1, 10 }, 2036 .vback_porch = { 1, 1, 10 }, 2037 .vsync_len = { 1, 21, 203 }, 2038 .flags = DISPLAY_FLAGS_DE_HIGH, 2039 }; 2040 2041 static const struct panel_desc hannstar_hsd070pww1 = { 2042 .timings = &hannstar_hsd070pww1_timing, 2043 .num_timings = 1, 2044 .bpc = 6, 2045 .size = { 2046 .width = 151, 2047 .height = 94, 2048 }, 2049 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2051 }; 2052 2053 static const struct display_timing hannstar_hsd100pxn1_timing = { 2054 .pixelclock = { 55000000, 65000000, 75000000 }, 2055 .hactive = { 1024, 1024, 1024 }, 2056 .hfront_porch = { 40, 40, 40 }, 2057 .hback_porch = { 220, 220, 220 }, 2058 .hsync_len = { 20, 60, 100 }, 2059 .vactive = { 768, 768, 768 }, 2060 .vfront_porch = { 7, 7, 7 }, 2061 .vback_porch = { 21, 21, 21 }, 2062 .vsync_len = { 10, 10, 10 }, 2063 .flags = DISPLAY_FLAGS_DE_HIGH, 2064 }; 2065 2066 static const struct panel_desc hannstar_hsd100pxn1 = { 2067 .timings = &hannstar_hsd100pxn1_timing, 2068 .num_timings = 1, 2069 .bpc = 6, 2070 .size = { 2071 .width = 203, 2072 .height = 152, 2073 }, 2074 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2076 }; 2077 2078 static const struct display_timing hannstar_hsd101pww2_timing = { 2079 .pixelclock = { 64300000, 71100000, 82000000 }, 2080 .hactive = { 1280, 1280, 1280 }, 2081 .hfront_porch = { 1, 1, 10 }, 2082 .hback_porch = { 1, 1, 10 }, 2083 .hsync_len = { 58, 158, 661 }, 2084 .vactive = { 800, 800, 800 }, 2085 .vfront_porch = { 1, 1, 10 }, 2086 .vback_porch = { 1, 1, 10 }, 2087 .vsync_len = { 1, 21, 203 }, 2088 .flags = DISPLAY_FLAGS_DE_HIGH, 2089 }; 2090 2091 static const struct panel_desc hannstar_hsd101pww2 = { 2092 .timings = &hannstar_hsd101pww2_timing, 2093 .num_timings = 1, 2094 .bpc = 8, 2095 .size = { 2096 .width = 217, 2097 .height = 136, 2098 }, 2099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2100 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2101 }; 2102 2103 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2104 .clock = 33333, 2105 .hdisplay = 800, 2106 .hsync_start = 800 + 85, 2107 .hsync_end = 800 + 85 + 86, 2108 .htotal = 800 + 85 + 86 + 85, 2109 .vdisplay = 480, 2110 .vsync_start = 480 + 16, 2111 .vsync_end = 480 + 16 + 13, 2112 .vtotal = 480 + 16 + 13 + 16, 2113 }; 2114 2115 static const struct panel_desc hitachi_tx23d38vm0caa = { 2116 .modes = &hitachi_tx23d38vm0caa_mode, 2117 .num_modes = 1, 2118 .bpc = 6, 2119 .size = { 2120 .width = 195, 2121 .height = 117, 2122 }, 2123 .delay = { 2124 .enable = 160, 2125 .disable = 160, 2126 }, 2127 }; 2128 2129 static const struct drm_display_mode innolux_at043tn24_mode = { 2130 .clock = 9000, 2131 .hdisplay = 480, 2132 .hsync_start = 480 + 2, 2133 .hsync_end = 480 + 2 + 41, 2134 .htotal = 480 + 2 + 41 + 2, 2135 .vdisplay = 272, 2136 .vsync_start = 272 + 2, 2137 .vsync_end = 272 + 2 + 10, 2138 .vtotal = 272 + 2 + 10 + 2, 2139 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2140 }; 2141 2142 static const struct panel_desc innolux_at043tn24 = { 2143 .modes = &innolux_at043tn24_mode, 2144 .num_modes = 1, 2145 .bpc = 8, 2146 .size = { 2147 .width = 95, 2148 .height = 54, 2149 }, 2150 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2151 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2152 }; 2153 2154 static const struct drm_display_mode innolux_at070tn92_mode = { 2155 .clock = 33333, 2156 .hdisplay = 800, 2157 .hsync_start = 800 + 210, 2158 .hsync_end = 800 + 210 + 20, 2159 .htotal = 800 + 210 + 20 + 46, 2160 .vdisplay = 480, 2161 .vsync_start = 480 + 22, 2162 .vsync_end = 480 + 22 + 10, 2163 .vtotal = 480 + 22 + 23 + 10, 2164 }; 2165 2166 static const struct panel_desc innolux_at070tn92 = { 2167 .modes = &innolux_at070tn92_mode, 2168 .num_modes = 1, 2169 .size = { 2170 .width = 154, 2171 .height = 86, 2172 }, 2173 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2174 }; 2175 2176 static const struct display_timing innolux_g070ace_l01_timing = { 2177 .pixelclock = { 25200000, 35000000, 35700000 }, 2178 .hactive = { 800, 800, 800 }, 2179 .hfront_porch = { 30, 32, 87 }, 2180 .hback_porch = { 30, 32, 87 }, 2181 .hsync_len = { 1, 1, 1 }, 2182 .vactive = { 480, 480, 480 }, 2183 .vfront_porch = { 3, 3, 3 }, 2184 .vback_porch = { 13, 13, 13 }, 2185 .vsync_len = { 1, 1, 4 }, 2186 .flags = DISPLAY_FLAGS_DE_HIGH, 2187 }; 2188 2189 static const struct panel_desc innolux_g070ace_l01 = { 2190 .timings = &innolux_g070ace_l01_timing, 2191 .num_timings = 1, 2192 .bpc = 8, 2193 .size = { 2194 .width = 152, 2195 .height = 91, 2196 }, 2197 .delay = { 2198 .prepare = 10, 2199 .enable = 50, 2200 .disable = 50, 2201 .unprepare = 500, 2202 }, 2203 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2204 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2205 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2206 }; 2207 2208 static const struct display_timing innolux_g070y2_l01_timing = { 2209 .pixelclock = { 28000000, 29500000, 32000000 }, 2210 .hactive = { 800, 800, 800 }, 2211 .hfront_porch = { 61, 91, 141 }, 2212 .hback_porch = { 60, 90, 140 }, 2213 .hsync_len = { 12, 12, 12 }, 2214 .vactive = { 480, 480, 480 }, 2215 .vfront_porch = { 4, 9, 30 }, 2216 .vback_porch = { 4, 8, 28 }, 2217 .vsync_len = { 2, 2, 2 }, 2218 .flags = DISPLAY_FLAGS_DE_HIGH, 2219 }; 2220 2221 static const struct panel_desc innolux_g070y2_l01 = { 2222 .timings = &innolux_g070y2_l01_timing, 2223 .num_timings = 1, 2224 .bpc = 8, 2225 .size = { 2226 .width = 152, 2227 .height = 91, 2228 }, 2229 .delay = { 2230 .prepare = 10, 2231 .enable = 100, 2232 .disable = 100, 2233 .unprepare = 800, 2234 }, 2235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2236 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2237 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2238 }; 2239 2240 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2241 .clock = 33333, 2242 .hdisplay = 800, 2243 .hsync_start = 800 + 210, 2244 .hsync_end = 800 + 210 + 20, 2245 .htotal = 800 + 210 + 20 + 46, 2246 .vdisplay = 480, 2247 .vsync_start = 480 + 22, 2248 .vsync_end = 480 + 22 + 10, 2249 .vtotal = 480 + 22 + 23 + 10, 2250 }; 2251 2252 static const struct panel_desc innolux_g070y2_t02 = { 2253 .modes = &innolux_g070y2_t02_mode, 2254 .num_modes = 1, 2255 .bpc = 8, 2256 .size = { 2257 .width = 152, 2258 .height = 92, 2259 }, 2260 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2261 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2262 .connector_type = DRM_MODE_CONNECTOR_DPI, 2263 }; 2264 2265 static const struct display_timing innolux_g101ice_l01_timing = { 2266 .pixelclock = { 60400000, 71100000, 74700000 }, 2267 .hactive = { 1280, 1280, 1280 }, 2268 .hfront_porch = { 41, 80, 100 }, 2269 .hback_porch = { 40, 79, 99 }, 2270 .hsync_len = { 1, 1, 1 }, 2271 .vactive = { 800, 800, 800 }, 2272 .vfront_porch = { 5, 11, 14 }, 2273 .vback_porch = { 4, 11, 14 }, 2274 .vsync_len = { 1, 1, 1 }, 2275 .flags = DISPLAY_FLAGS_DE_HIGH, 2276 }; 2277 2278 static const struct panel_desc innolux_g101ice_l01 = { 2279 .timings = &innolux_g101ice_l01_timing, 2280 .num_timings = 1, 2281 .bpc = 8, 2282 .size = { 2283 .width = 217, 2284 .height = 135, 2285 }, 2286 .delay = { 2287 .enable = 200, 2288 .disable = 200, 2289 }, 2290 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2291 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2292 }; 2293 2294 static const struct display_timing innolux_g121i1_l01_timing = { 2295 .pixelclock = { 67450000, 71000000, 74550000 }, 2296 .hactive = { 1280, 1280, 1280 }, 2297 .hfront_porch = { 40, 80, 160 }, 2298 .hback_porch = { 39, 79, 159 }, 2299 .hsync_len = { 1, 1, 1 }, 2300 .vactive = { 800, 800, 800 }, 2301 .vfront_porch = { 5, 11, 100 }, 2302 .vback_porch = { 4, 11, 99 }, 2303 .vsync_len = { 1, 1, 1 }, 2304 }; 2305 2306 static const struct panel_desc innolux_g121i1_l01 = { 2307 .timings = &innolux_g121i1_l01_timing, 2308 .num_timings = 1, 2309 .bpc = 6, 2310 .size = { 2311 .width = 261, 2312 .height = 163, 2313 }, 2314 .delay = { 2315 .enable = 200, 2316 .disable = 20, 2317 }, 2318 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2319 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2320 }; 2321 2322 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2323 .clock = 65000, 2324 .hdisplay = 1024, 2325 .hsync_start = 1024 + 0, 2326 .hsync_end = 1024 + 1, 2327 .htotal = 1024 + 0 + 1 + 320, 2328 .vdisplay = 768, 2329 .vsync_start = 768 + 38, 2330 .vsync_end = 768 + 38 + 1, 2331 .vtotal = 768 + 38 + 1 + 0, 2332 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2333 }; 2334 2335 static const struct panel_desc innolux_g121x1_l03 = { 2336 .modes = &innolux_g121x1_l03_mode, 2337 .num_modes = 1, 2338 .bpc = 6, 2339 .size = { 2340 .width = 246, 2341 .height = 185, 2342 }, 2343 .delay = { 2344 .enable = 200, 2345 .unprepare = 200, 2346 .disable = 400, 2347 }, 2348 }; 2349 2350 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2351 .clock = 69300, 2352 .hdisplay = 1366, 2353 .hsync_start = 1366 + 16, 2354 .hsync_end = 1366 + 16 + 34, 2355 .htotal = 1366 + 16 + 34 + 50, 2356 .vdisplay = 768, 2357 .vsync_start = 768 + 2, 2358 .vsync_end = 768 + 2 + 6, 2359 .vtotal = 768 + 2 + 6 + 12, 2360 }; 2361 2362 static const struct panel_desc innolux_n156bge_l21 = { 2363 .modes = &innolux_n156bge_l21_mode, 2364 .num_modes = 1, 2365 .bpc = 6, 2366 .size = { 2367 .width = 344, 2368 .height = 193, 2369 }, 2370 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2371 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2372 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2373 }; 2374 2375 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2376 .clock = 51501, 2377 .hdisplay = 1024, 2378 .hsync_start = 1024 + 128, 2379 .hsync_end = 1024 + 128 + 64, 2380 .htotal = 1024 + 128 + 64 + 128, 2381 .vdisplay = 600, 2382 .vsync_start = 600 + 16, 2383 .vsync_end = 600 + 16 + 4, 2384 .vtotal = 600 + 16 + 4 + 16, 2385 }; 2386 2387 static const struct panel_desc innolux_zj070na_01p = { 2388 .modes = &innolux_zj070na_01p_mode, 2389 .num_modes = 1, 2390 .bpc = 6, 2391 .size = { 2392 .width = 154, 2393 .height = 90, 2394 }, 2395 }; 2396 2397 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2398 .pixelclock = { 5580000, 5850000, 6200000 }, 2399 .hactive = { 320, 320, 320 }, 2400 .hfront_porch = { 30, 30, 30 }, 2401 .hback_porch = { 30, 30, 30 }, 2402 .hsync_len = { 1, 5, 17 }, 2403 .vactive = { 240, 240, 240 }, 2404 .vfront_porch = { 6, 6, 6 }, 2405 .vback_porch = { 5, 5, 5 }, 2406 .vsync_len = { 1, 2, 11 }, 2407 .flags = DISPLAY_FLAGS_DE_HIGH, 2408 }; 2409 2410 static const struct panel_desc koe_tx14d24vm1bpa = { 2411 .timings = &koe_tx14d24vm1bpa_timing, 2412 .num_timings = 1, 2413 .bpc = 6, 2414 .size = { 2415 .width = 115, 2416 .height = 86, 2417 }, 2418 }; 2419 2420 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2421 .pixelclock = { 151820000, 156720000, 159780000 }, 2422 .hactive = { 1920, 1920, 1920 }, 2423 .hfront_porch = { 105, 130, 142 }, 2424 .hback_porch = { 45, 70, 82 }, 2425 .hsync_len = { 30, 30, 30 }, 2426 .vactive = { 1200, 1200, 1200}, 2427 .vfront_porch = { 3, 5, 10 }, 2428 .vback_porch = { 2, 5, 10 }, 2429 .vsync_len = { 5, 5, 5 }, 2430 }; 2431 2432 static const struct panel_desc koe_tx26d202vm0bwa = { 2433 .timings = &koe_tx26d202vm0bwa_timing, 2434 .num_timings = 1, 2435 .bpc = 8, 2436 .size = { 2437 .width = 217, 2438 .height = 136, 2439 }, 2440 .delay = { 2441 .prepare = 1000, 2442 .enable = 1000, 2443 .unprepare = 1000, 2444 .disable = 1000, 2445 }, 2446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2447 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2448 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2449 }; 2450 2451 static const struct display_timing koe_tx31d200vm0baa_timing = { 2452 .pixelclock = { 39600000, 43200000, 48000000 }, 2453 .hactive = { 1280, 1280, 1280 }, 2454 .hfront_porch = { 16, 36, 56 }, 2455 .hback_porch = { 16, 36, 56 }, 2456 .hsync_len = { 8, 8, 8 }, 2457 .vactive = { 480, 480, 480 }, 2458 .vfront_porch = { 6, 21, 33 }, 2459 .vback_porch = { 6, 21, 33 }, 2460 .vsync_len = { 8, 8, 8 }, 2461 .flags = DISPLAY_FLAGS_DE_HIGH, 2462 }; 2463 2464 static const struct panel_desc koe_tx31d200vm0baa = { 2465 .timings = &koe_tx31d200vm0baa_timing, 2466 .num_timings = 1, 2467 .bpc = 6, 2468 .size = { 2469 .width = 292, 2470 .height = 109, 2471 }, 2472 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2473 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2474 }; 2475 2476 static const struct display_timing kyo_tcg121xglp_timing = { 2477 .pixelclock = { 52000000, 65000000, 71000000 }, 2478 .hactive = { 1024, 1024, 1024 }, 2479 .hfront_porch = { 2, 2, 2 }, 2480 .hback_porch = { 2, 2, 2 }, 2481 .hsync_len = { 86, 124, 244 }, 2482 .vactive = { 768, 768, 768 }, 2483 .vfront_porch = { 2, 2, 2 }, 2484 .vback_porch = { 2, 2, 2 }, 2485 .vsync_len = { 6, 34, 73 }, 2486 .flags = DISPLAY_FLAGS_DE_HIGH, 2487 }; 2488 2489 static const struct panel_desc kyo_tcg121xglp = { 2490 .timings = &kyo_tcg121xglp_timing, 2491 .num_timings = 1, 2492 .bpc = 8, 2493 .size = { 2494 .width = 246, 2495 .height = 184, 2496 }, 2497 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2498 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2499 }; 2500 2501 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2502 .clock = 7000, 2503 .hdisplay = 320, 2504 .hsync_start = 320 + 20, 2505 .hsync_end = 320 + 20 + 30, 2506 .htotal = 320 + 20 + 30 + 38, 2507 .vdisplay = 240, 2508 .vsync_start = 240 + 4, 2509 .vsync_end = 240 + 4 + 3, 2510 .vtotal = 240 + 4 + 3 + 15, 2511 }; 2512 2513 static const struct panel_desc lemaker_bl035_rgb_002 = { 2514 .modes = &lemaker_bl035_rgb_002_mode, 2515 .num_modes = 1, 2516 .size = { 2517 .width = 70, 2518 .height = 52, 2519 }, 2520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2521 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2522 }; 2523 2524 static const struct drm_display_mode lg_lb070wv8_mode = { 2525 .clock = 33246, 2526 .hdisplay = 800, 2527 .hsync_start = 800 + 88, 2528 .hsync_end = 800 + 88 + 80, 2529 .htotal = 800 + 88 + 80 + 88, 2530 .vdisplay = 480, 2531 .vsync_start = 480 + 10, 2532 .vsync_end = 480 + 10 + 25, 2533 .vtotal = 480 + 10 + 25 + 10, 2534 }; 2535 2536 static const struct panel_desc lg_lb070wv8 = { 2537 .modes = &lg_lb070wv8_mode, 2538 .num_modes = 1, 2539 .bpc = 8, 2540 .size = { 2541 .width = 151, 2542 .height = 91, 2543 }, 2544 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2545 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2546 }; 2547 2548 static const struct display_timing logictechno_lt161010_2nh_timing = { 2549 .pixelclock = { 26400000, 33300000, 46800000 }, 2550 .hactive = { 800, 800, 800 }, 2551 .hfront_porch = { 16, 210, 354 }, 2552 .hback_porch = { 46, 46, 46 }, 2553 .hsync_len = { 1, 20, 40 }, 2554 .vactive = { 480, 480, 480 }, 2555 .vfront_porch = { 7, 22, 147 }, 2556 .vback_porch = { 23, 23, 23 }, 2557 .vsync_len = { 1, 10, 20 }, 2558 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2559 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2560 DISPLAY_FLAGS_SYNC_POSEDGE, 2561 }; 2562 2563 static const struct panel_desc logictechno_lt161010_2nh = { 2564 .timings = &logictechno_lt161010_2nh_timing, 2565 .num_timings = 1, 2566 .bpc = 6, 2567 .size = { 2568 .width = 154, 2569 .height = 86, 2570 }, 2571 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2572 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2573 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2574 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2575 .connector_type = DRM_MODE_CONNECTOR_DPI, 2576 }; 2577 2578 static const struct display_timing logictechno_lt170410_2whc_timing = { 2579 .pixelclock = { 68900000, 71100000, 73400000 }, 2580 .hactive = { 1280, 1280, 1280 }, 2581 .hfront_porch = { 23, 60, 71 }, 2582 .hback_porch = { 23, 60, 71 }, 2583 .hsync_len = { 15, 40, 47 }, 2584 .vactive = { 800, 800, 800 }, 2585 .vfront_porch = { 5, 7, 10 }, 2586 .vback_porch = { 5, 7, 10 }, 2587 .vsync_len = { 6, 9, 12 }, 2588 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2589 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2590 DISPLAY_FLAGS_SYNC_POSEDGE, 2591 }; 2592 2593 static const struct panel_desc logictechno_lt170410_2whc = { 2594 .timings = &logictechno_lt170410_2whc_timing, 2595 .num_timings = 1, 2596 .bpc = 8, 2597 .size = { 2598 .width = 217, 2599 .height = 136, 2600 }, 2601 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2602 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2603 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2604 }; 2605 2606 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2607 .clock = 33000, 2608 .hdisplay = 800, 2609 .hsync_start = 800 + 112, 2610 .hsync_end = 800 + 112 + 3, 2611 .htotal = 800 + 112 + 3 + 85, 2612 .vdisplay = 480, 2613 .vsync_start = 480 + 38, 2614 .vsync_end = 480 + 38 + 3, 2615 .vtotal = 480 + 38 + 3 + 29, 2616 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2617 }; 2618 2619 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2620 .modes = &logictechno_lttd800480070_l2rt_mode, 2621 .num_modes = 1, 2622 .bpc = 8, 2623 .size = { 2624 .width = 154, 2625 .height = 86, 2626 }, 2627 .delay = { 2628 .prepare = 45, 2629 .enable = 100, 2630 .disable = 100, 2631 .unprepare = 45 2632 }, 2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2634 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2635 .connector_type = DRM_MODE_CONNECTOR_DPI, 2636 }; 2637 2638 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2639 .clock = 33000, 2640 .hdisplay = 800, 2641 .hsync_start = 800 + 154, 2642 .hsync_end = 800 + 154 + 3, 2643 .htotal = 800 + 154 + 3 + 43, 2644 .vdisplay = 480, 2645 .vsync_start = 480 + 47, 2646 .vsync_end = 480 + 47 + 3, 2647 .vtotal = 480 + 47 + 3 + 20, 2648 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2649 }; 2650 2651 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2652 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2653 .num_modes = 1, 2654 .bpc = 8, 2655 .size = { 2656 .width = 154, 2657 .height = 86, 2658 }, 2659 .delay = { 2660 .prepare = 45, 2661 .enable = 100, 2662 .disable = 100, 2663 .unprepare = 45 2664 }, 2665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2666 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2667 .connector_type = DRM_MODE_CONNECTOR_DPI, 2668 }; 2669 2670 static const struct drm_display_mode logicpd_type_28_mode = { 2671 .clock = 9107, 2672 .hdisplay = 480, 2673 .hsync_start = 480 + 3, 2674 .hsync_end = 480 + 3 + 42, 2675 .htotal = 480 + 3 + 42 + 2, 2676 2677 .vdisplay = 272, 2678 .vsync_start = 272 + 2, 2679 .vsync_end = 272 + 2 + 11, 2680 .vtotal = 272 + 2 + 11 + 3, 2681 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2682 }; 2683 2684 static const struct panel_desc logicpd_type_28 = { 2685 .modes = &logicpd_type_28_mode, 2686 .num_modes = 1, 2687 .bpc = 8, 2688 .size = { 2689 .width = 105, 2690 .height = 67, 2691 }, 2692 .delay = { 2693 .prepare = 200, 2694 .enable = 200, 2695 .unprepare = 200, 2696 .disable = 200, 2697 }, 2698 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2699 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2700 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2701 .connector_type = DRM_MODE_CONNECTOR_DPI, 2702 }; 2703 2704 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2705 .clock = 30400, 2706 .hdisplay = 800, 2707 .hsync_start = 800 + 0, 2708 .hsync_end = 800 + 1, 2709 .htotal = 800 + 0 + 1 + 160, 2710 .vdisplay = 480, 2711 .vsync_start = 480 + 0, 2712 .vsync_end = 480 + 48 + 1, 2713 .vtotal = 480 + 48 + 1 + 0, 2714 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2715 }; 2716 2717 static const struct panel_desc mitsubishi_aa070mc01 = { 2718 .modes = &mitsubishi_aa070mc01_mode, 2719 .num_modes = 1, 2720 .bpc = 8, 2721 .size = { 2722 .width = 152, 2723 .height = 91, 2724 }, 2725 2726 .delay = { 2727 .enable = 200, 2728 .unprepare = 200, 2729 .disable = 400, 2730 }, 2731 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2733 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2734 }; 2735 2736 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2737 .pixelclock = { 29000000, 33000000, 38000000 }, 2738 .hactive = { 800, 800, 800 }, 2739 .hfront_porch = { 180, 210, 240 }, 2740 .hback_porch = { 16, 16, 16 }, 2741 .hsync_len = { 30, 30, 30 }, 2742 .vactive = { 480, 480, 480 }, 2743 .vfront_porch = { 12, 22, 32 }, 2744 .vback_porch = { 10, 10, 10 }, 2745 .vsync_len = { 13, 13, 13 }, 2746 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2747 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2748 DISPLAY_FLAGS_SYNC_POSEDGE, 2749 }; 2750 2751 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2752 .timings = &multi_inno_mi0700s4t_6_timing, 2753 .num_timings = 1, 2754 .bpc = 8, 2755 .size = { 2756 .width = 154, 2757 .height = 86, 2758 }, 2759 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2760 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2761 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2762 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2763 .connector_type = DRM_MODE_CONNECTOR_DPI, 2764 }; 2765 2766 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2767 .pixelclock = { 32000000, 40000000, 50000000 }, 2768 .hactive = { 800, 800, 800 }, 2769 .hfront_porch = { 16, 210, 354 }, 2770 .hback_porch = { 6, 26, 45 }, 2771 .hsync_len = { 1, 20, 40 }, 2772 .vactive = { 600, 600, 600 }, 2773 .vfront_porch = { 1, 12, 77 }, 2774 .vback_porch = { 3, 13, 22 }, 2775 .vsync_len = { 1, 10, 20 }, 2776 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2777 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2778 DISPLAY_FLAGS_SYNC_POSEDGE, 2779 }; 2780 2781 static const struct panel_desc multi_inno_mi0800ft_9 = { 2782 .timings = &multi_inno_mi0800ft_9_timing, 2783 .num_timings = 1, 2784 .bpc = 8, 2785 .size = { 2786 .width = 162, 2787 .height = 122, 2788 }, 2789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2791 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2792 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2793 .connector_type = DRM_MODE_CONNECTOR_DPI, 2794 }; 2795 2796 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2797 .pixelclock = { 68900000, 70000000, 73400000 }, 2798 .hactive = { 1280, 1280, 1280 }, 2799 .hfront_porch = { 30, 60, 71 }, 2800 .hback_porch = { 30, 60, 71 }, 2801 .hsync_len = { 10, 10, 48 }, 2802 .vactive = { 800, 800, 800 }, 2803 .vfront_porch = { 5, 10, 10 }, 2804 .vback_porch = { 5, 10, 10 }, 2805 .vsync_len = { 5, 6, 13 }, 2806 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2807 DISPLAY_FLAGS_DE_HIGH, 2808 }; 2809 2810 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2811 .timings = &multi_inno_mi1010ait_1cp_timing, 2812 .num_timings = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 217, 2816 .height = 136, 2817 }, 2818 .delay = { 2819 .enable = 50, 2820 .disable = 50, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2823 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2824 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2825 }; 2826 2827 static const struct display_timing nec_nl12880bc20_05_timing = { 2828 .pixelclock = { 67000000, 71000000, 75000000 }, 2829 .hactive = { 1280, 1280, 1280 }, 2830 .hfront_porch = { 2, 30, 30 }, 2831 .hback_porch = { 6, 100, 100 }, 2832 .hsync_len = { 2, 30, 30 }, 2833 .vactive = { 800, 800, 800 }, 2834 .vfront_porch = { 5, 5, 5 }, 2835 .vback_porch = { 11, 11, 11 }, 2836 .vsync_len = { 7, 7, 7 }, 2837 }; 2838 2839 static const struct panel_desc nec_nl12880bc20_05 = { 2840 .timings = &nec_nl12880bc20_05_timing, 2841 .num_timings = 1, 2842 .bpc = 8, 2843 .size = { 2844 .width = 261, 2845 .height = 163, 2846 }, 2847 .delay = { 2848 .enable = 50, 2849 .disable = 50, 2850 }, 2851 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2852 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2853 }; 2854 2855 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2856 .clock = 10870, 2857 .hdisplay = 480, 2858 .hsync_start = 480 + 2, 2859 .hsync_end = 480 + 2 + 41, 2860 .htotal = 480 + 2 + 41 + 2, 2861 .vdisplay = 272, 2862 .vsync_start = 272 + 2, 2863 .vsync_end = 272 + 2 + 4, 2864 .vtotal = 272 + 2 + 4 + 2, 2865 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2866 }; 2867 2868 static const struct panel_desc nec_nl4827hc19_05b = { 2869 .modes = &nec_nl4827hc19_05b_mode, 2870 .num_modes = 1, 2871 .bpc = 8, 2872 .size = { 2873 .width = 95, 2874 .height = 54, 2875 }, 2876 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2877 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2878 }; 2879 2880 static const struct drm_display_mode netron_dy_e231732_mode = { 2881 .clock = 66000, 2882 .hdisplay = 1024, 2883 .hsync_start = 1024 + 160, 2884 .hsync_end = 1024 + 160 + 70, 2885 .htotal = 1024 + 160 + 70 + 90, 2886 .vdisplay = 600, 2887 .vsync_start = 600 + 127, 2888 .vsync_end = 600 + 127 + 20, 2889 .vtotal = 600 + 127 + 20 + 3, 2890 }; 2891 2892 static const struct panel_desc netron_dy_e231732 = { 2893 .modes = &netron_dy_e231732_mode, 2894 .num_modes = 1, 2895 .size = { 2896 .width = 154, 2897 .height = 87, 2898 }, 2899 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2900 }; 2901 2902 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2903 .clock = 9000, 2904 .hdisplay = 480, 2905 .hsync_start = 480 + 2, 2906 .hsync_end = 480 + 2 + 41, 2907 .htotal = 480 + 2 + 41 + 2, 2908 .vdisplay = 272, 2909 .vsync_start = 272 + 2, 2910 .vsync_end = 272 + 2 + 10, 2911 .vtotal = 272 + 2 + 10 + 2, 2912 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2913 }; 2914 2915 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2916 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2917 .num_modes = 1, 2918 .bpc = 8, 2919 .size = { 2920 .width = 95, 2921 .height = 54, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2925 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2926 .connector_type = DRM_MODE_CONNECTOR_DPI, 2927 }; 2928 2929 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2930 .pixelclock = { 130000000, 148350000, 163000000 }, 2931 .hactive = { 1920, 1920, 1920 }, 2932 .hfront_porch = { 80, 100, 100 }, 2933 .hback_porch = { 100, 120, 120 }, 2934 .hsync_len = { 50, 60, 60 }, 2935 .vactive = { 1080, 1080, 1080 }, 2936 .vfront_porch = { 12, 30, 30 }, 2937 .vback_porch = { 4, 10, 10 }, 2938 .vsync_len = { 4, 5, 5 }, 2939 }; 2940 2941 static const struct panel_desc nlt_nl192108ac18_02d = { 2942 .timings = &nlt_nl192108ac18_02d_timing, 2943 .num_timings = 1, 2944 .bpc = 8, 2945 .size = { 2946 .width = 344, 2947 .height = 194, 2948 }, 2949 .delay = { 2950 .unprepare = 500, 2951 }, 2952 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2953 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2954 }; 2955 2956 static const struct drm_display_mode nvd_9128_mode = { 2957 .clock = 29500, 2958 .hdisplay = 800, 2959 .hsync_start = 800 + 130, 2960 .hsync_end = 800 + 130 + 98, 2961 .htotal = 800 + 0 + 130 + 98, 2962 .vdisplay = 480, 2963 .vsync_start = 480 + 10, 2964 .vsync_end = 480 + 10 + 50, 2965 .vtotal = 480 + 0 + 10 + 50, 2966 }; 2967 2968 static const struct panel_desc nvd_9128 = { 2969 .modes = &nvd_9128_mode, 2970 .num_modes = 1, 2971 .bpc = 8, 2972 .size = { 2973 .width = 156, 2974 .height = 88, 2975 }, 2976 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2977 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2978 }; 2979 2980 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2981 .pixelclock = { 30000000, 30000000, 40000000 }, 2982 .hactive = { 800, 800, 800 }, 2983 .hfront_porch = { 40, 40, 40 }, 2984 .hback_porch = { 40, 40, 40 }, 2985 .hsync_len = { 1, 48, 48 }, 2986 .vactive = { 480, 480, 480 }, 2987 .vfront_porch = { 13, 13, 13 }, 2988 .vback_porch = { 29, 29, 29 }, 2989 .vsync_len = { 3, 3, 3 }, 2990 .flags = DISPLAY_FLAGS_DE_HIGH, 2991 }; 2992 2993 static const struct panel_desc okaya_rs800480t_7x0gp = { 2994 .timings = &okaya_rs800480t_7x0gp_timing, 2995 .num_timings = 1, 2996 .bpc = 6, 2997 .size = { 2998 .width = 154, 2999 .height = 87, 3000 }, 3001 .delay = { 3002 .prepare = 41, 3003 .enable = 50, 3004 .unprepare = 41, 3005 .disable = 50, 3006 }, 3007 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3008 }; 3009 3010 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3011 .clock = 9000, 3012 .hdisplay = 480, 3013 .hsync_start = 480 + 5, 3014 .hsync_end = 480 + 5 + 30, 3015 .htotal = 480 + 5 + 30 + 10, 3016 .vdisplay = 272, 3017 .vsync_start = 272 + 8, 3018 .vsync_end = 272 + 8 + 5, 3019 .vtotal = 272 + 8 + 5 + 3, 3020 }; 3021 3022 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3023 .modes = &olimex_lcd_olinuxino_43ts_mode, 3024 .num_modes = 1, 3025 .size = { 3026 .width = 95, 3027 .height = 54, 3028 }, 3029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3030 }; 3031 3032 /* 3033 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3034 * pixel clocks, but this is the timing that was being used in the Adafruit 3035 * installation instructions. 3036 */ 3037 static const struct drm_display_mode ontat_yx700wv03_mode = { 3038 .clock = 29500, 3039 .hdisplay = 800, 3040 .hsync_start = 824, 3041 .hsync_end = 896, 3042 .htotal = 992, 3043 .vdisplay = 480, 3044 .vsync_start = 483, 3045 .vsync_end = 493, 3046 .vtotal = 500, 3047 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3048 }; 3049 3050 /* 3051 * Specification at: 3052 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3053 */ 3054 static const struct panel_desc ontat_yx700wv03 = { 3055 .modes = &ontat_yx700wv03_mode, 3056 .num_modes = 1, 3057 .bpc = 8, 3058 .size = { 3059 .width = 154, 3060 .height = 83, 3061 }, 3062 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3063 }; 3064 3065 static const struct drm_display_mode ortustech_com37h3m_mode = { 3066 .clock = 22230, 3067 .hdisplay = 480, 3068 .hsync_start = 480 + 40, 3069 .hsync_end = 480 + 40 + 10, 3070 .htotal = 480 + 40 + 10 + 40, 3071 .vdisplay = 640, 3072 .vsync_start = 640 + 4, 3073 .vsync_end = 640 + 4 + 2, 3074 .vtotal = 640 + 4 + 2 + 4, 3075 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3076 }; 3077 3078 static const struct panel_desc ortustech_com37h3m = { 3079 .modes = &ortustech_com37h3m_mode, 3080 .num_modes = 1, 3081 .bpc = 8, 3082 .size = { 3083 .width = 56, /* 56.16mm */ 3084 .height = 75, /* 74.88mm */ 3085 }, 3086 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3088 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3089 }; 3090 3091 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3092 .clock = 25000, 3093 .hdisplay = 480, 3094 .hsync_start = 480 + 10, 3095 .hsync_end = 480 + 10 + 10, 3096 .htotal = 480 + 10 + 10 + 15, 3097 .vdisplay = 800, 3098 .vsync_start = 800 + 3, 3099 .vsync_end = 800 + 3 + 3, 3100 .vtotal = 800 + 3 + 3 + 3, 3101 }; 3102 3103 static const struct panel_desc ortustech_com43h4m85ulc = { 3104 .modes = &ortustech_com43h4m85ulc_mode, 3105 .num_modes = 1, 3106 .bpc = 6, 3107 .size = { 3108 .width = 56, 3109 .height = 93, 3110 }, 3111 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3112 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3113 .connector_type = DRM_MODE_CONNECTOR_DPI, 3114 }; 3115 3116 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3117 .clock = 33000, 3118 .hdisplay = 800, 3119 .hsync_start = 800 + 210, 3120 .hsync_end = 800 + 210 + 30, 3121 .htotal = 800 + 210 + 30 + 16, 3122 .vdisplay = 480, 3123 .vsync_start = 480 + 22, 3124 .vsync_end = 480 + 22 + 13, 3125 .vtotal = 480 + 22 + 13 + 10, 3126 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3127 }; 3128 3129 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3130 .modes = &osddisplays_osd070t1718_19ts_mode, 3131 .num_modes = 1, 3132 .bpc = 8, 3133 .size = { 3134 .width = 152, 3135 .height = 91, 3136 }, 3137 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3138 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3139 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3140 .connector_type = DRM_MODE_CONNECTOR_DPI, 3141 }; 3142 3143 static const struct drm_display_mode pda_91_00156_a0_mode = { 3144 .clock = 33300, 3145 .hdisplay = 800, 3146 .hsync_start = 800 + 1, 3147 .hsync_end = 800 + 1 + 64, 3148 .htotal = 800 + 1 + 64 + 64, 3149 .vdisplay = 480, 3150 .vsync_start = 480 + 1, 3151 .vsync_end = 480 + 1 + 23, 3152 .vtotal = 480 + 1 + 23 + 22, 3153 }; 3154 3155 static const struct panel_desc pda_91_00156_a0 = { 3156 .modes = &pda_91_00156_a0_mode, 3157 .num_modes = 1, 3158 .size = { 3159 .width = 152, 3160 .height = 91, 3161 }, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3163 }; 3164 3165 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3166 .clock = 24750, 3167 .hdisplay = 800, 3168 .hsync_start = 800 + 54, 3169 .hsync_end = 800 + 54 + 2, 3170 .htotal = 800 + 54 + 2 + 44, 3171 .vdisplay = 480, 3172 .vsync_start = 480 + 49, 3173 .vsync_end = 480 + 49 + 2, 3174 .vtotal = 480 + 49 + 2 + 22, 3175 }; 3176 3177 static const struct panel_desc powertip_ph800480t013_idf02 = { 3178 .modes = &powertip_ph800480t013_idf02_mode, 3179 .num_modes = 1, 3180 .size = { 3181 .width = 152, 3182 .height = 91, 3183 }, 3184 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3185 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3186 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3187 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3188 .connector_type = DRM_MODE_CONNECTOR_DPI, 3189 }; 3190 3191 static const struct drm_display_mode qd43003c0_40_mode = { 3192 .clock = 9000, 3193 .hdisplay = 480, 3194 .hsync_start = 480 + 8, 3195 .hsync_end = 480 + 8 + 4, 3196 .htotal = 480 + 8 + 4 + 39, 3197 .vdisplay = 272, 3198 .vsync_start = 272 + 4, 3199 .vsync_end = 272 + 4 + 10, 3200 .vtotal = 272 + 4 + 10 + 2, 3201 }; 3202 3203 static const struct panel_desc qd43003c0_40 = { 3204 .modes = &qd43003c0_40_mode, 3205 .num_modes = 1, 3206 .bpc = 8, 3207 .size = { 3208 .width = 95, 3209 .height = 53, 3210 }, 3211 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3212 }; 3213 3214 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3215 { /* 60 Hz */ 3216 .clock = 10800, 3217 .hdisplay = 480, 3218 .hsync_start = 480 + 77, 3219 .hsync_end = 480 + 77 + 41, 3220 .htotal = 480 + 77 + 41 + 2, 3221 .vdisplay = 272, 3222 .vsync_start = 272 + 16, 3223 .vsync_end = 272 + 16 + 10, 3224 .vtotal = 272 + 16 + 10 + 2, 3225 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3226 }, 3227 { /* 50 Hz */ 3228 .clock = 10800, 3229 .hdisplay = 480, 3230 .hsync_start = 480 + 17, 3231 .hsync_end = 480 + 17 + 41, 3232 .htotal = 480 + 17 + 41 + 2, 3233 .vdisplay = 272, 3234 .vsync_start = 272 + 116, 3235 .vsync_end = 272 + 116 + 10, 3236 .vtotal = 272 + 116 + 10 + 2, 3237 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3238 }, 3239 }; 3240 3241 static const struct panel_desc qishenglong_gopher2b_lcd = { 3242 .modes = qishenglong_gopher2b_lcd_modes, 3243 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3244 .bpc = 8, 3245 .size = { 3246 .width = 95, 3247 .height = 54, 3248 }, 3249 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3250 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3251 .connector_type = DRM_MODE_CONNECTOR_DPI, 3252 }; 3253 3254 static const struct display_timing rocktech_rk070er9427_timing = { 3255 .pixelclock = { 26400000, 33300000, 46800000 }, 3256 .hactive = { 800, 800, 800 }, 3257 .hfront_porch = { 16, 210, 354 }, 3258 .hback_porch = { 46, 46, 46 }, 3259 .hsync_len = { 1, 1, 1 }, 3260 .vactive = { 480, 480, 480 }, 3261 .vfront_porch = { 7, 22, 147 }, 3262 .vback_porch = { 23, 23, 23 }, 3263 .vsync_len = { 1, 1, 1 }, 3264 .flags = DISPLAY_FLAGS_DE_HIGH, 3265 }; 3266 3267 static const struct panel_desc rocktech_rk070er9427 = { 3268 .timings = &rocktech_rk070er9427_timing, 3269 .num_timings = 1, 3270 .bpc = 6, 3271 .size = { 3272 .width = 154, 3273 .height = 86, 3274 }, 3275 .delay = { 3276 .prepare = 41, 3277 .enable = 50, 3278 .unprepare = 41, 3279 .disable = 50, 3280 }, 3281 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3282 }; 3283 3284 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3285 .clock = 71100, 3286 .hdisplay = 1280, 3287 .hsync_start = 1280 + 48, 3288 .hsync_end = 1280 + 48 + 32, 3289 .htotal = 1280 + 48 + 32 + 80, 3290 .vdisplay = 800, 3291 .vsync_start = 800 + 2, 3292 .vsync_end = 800 + 2 + 5, 3293 .vtotal = 800 + 2 + 5 + 16, 3294 }; 3295 3296 static const struct panel_desc rocktech_rk101ii01d_ct = { 3297 .modes = &rocktech_rk101ii01d_ct_mode, 3298 .bpc = 8, 3299 .num_modes = 1, 3300 .size = { 3301 .width = 217, 3302 .height = 136, 3303 }, 3304 .delay = { 3305 .prepare = 50, 3306 .disable = 50, 3307 }, 3308 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3309 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3310 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3311 }; 3312 3313 static const struct display_timing samsung_ltl101al01_timing = { 3314 .pixelclock = { 66663000, 66663000, 66663000 }, 3315 .hactive = { 1280, 1280, 1280 }, 3316 .hfront_porch = { 18, 18, 18 }, 3317 .hback_porch = { 36, 36, 36 }, 3318 .hsync_len = { 16, 16, 16 }, 3319 .vactive = { 800, 800, 800 }, 3320 .vfront_porch = { 4, 4, 4 }, 3321 .vback_porch = { 16, 16, 16 }, 3322 .vsync_len = { 3, 3, 3 }, 3323 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3324 }; 3325 3326 static const struct panel_desc samsung_ltl101al01 = { 3327 .timings = &samsung_ltl101al01_timing, 3328 .num_timings = 1, 3329 .bpc = 8, 3330 .size = { 3331 .width = 217, 3332 .height = 135, 3333 }, 3334 .delay = { 3335 .prepare = 40, 3336 .enable = 300, 3337 .disable = 200, 3338 .unprepare = 600, 3339 }, 3340 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3341 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3342 }; 3343 3344 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3345 .clock = 54030, 3346 .hdisplay = 1024, 3347 .hsync_start = 1024 + 24, 3348 .hsync_end = 1024 + 24 + 136, 3349 .htotal = 1024 + 24 + 136 + 160, 3350 .vdisplay = 600, 3351 .vsync_start = 600 + 3, 3352 .vsync_end = 600 + 3 + 6, 3353 .vtotal = 600 + 3 + 6 + 61, 3354 }; 3355 3356 static const struct panel_desc samsung_ltn101nt05 = { 3357 .modes = &samsung_ltn101nt05_mode, 3358 .num_modes = 1, 3359 .bpc = 6, 3360 .size = { 3361 .width = 223, 3362 .height = 125, 3363 }, 3364 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3365 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3366 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3367 }; 3368 3369 static const struct display_timing satoz_sat050at40h12r2_timing = { 3370 .pixelclock = {33300000, 33300000, 50000000}, 3371 .hactive = {800, 800, 800}, 3372 .hfront_porch = {16, 210, 354}, 3373 .hback_porch = {46, 46, 46}, 3374 .hsync_len = {1, 1, 40}, 3375 .vactive = {480, 480, 480}, 3376 .vfront_porch = {7, 22, 147}, 3377 .vback_porch = {23, 23, 23}, 3378 .vsync_len = {1, 1, 20}, 3379 }; 3380 3381 static const struct panel_desc satoz_sat050at40h12r2 = { 3382 .timings = &satoz_sat050at40h12r2_timing, 3383 .num_timings = 1, 3384 .bpc = 8, 3385 .size = { 3386 .width = 108, 3387 .height = 65, 3388 }, 3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3390 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3391 }; 3392 3393 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3394 .clock = 33260, 3395 .hdisplay = 800, 3396 .hsync_start = 800 + 64, 3397 .hsync_end = 800 + 64 + 128, 3398 .htotal = 800 + 64 + 128 + 64, 3399 .vdisplay = 480, 3400 .vsync_start = 480 + 8, 3401 .vsync_end = 480 + 8 + 2, 3402 .vtotal = 480 + 8 + 2 + 35, 3403 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3404 }; 3405 3406 static const struct panel_desc sharp_lq070y3dg3b = { 3407 .modes = &sharp_lq070y3dg3b_mode, 3408 .num_modes = 1, 3409 .bpc = 8, 3410 .size = { 3411 .width = 152, /* 152.4mm */ 3412 .height = 91, /* 91.4mm */ 3413 }, 3414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3416 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3417 }; 3418 3419 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3420 .clock = 5500, 3421 .hdisplay = 240, 3422 .hsync_start = 240 + 16, 3423 .hsync_end = 240 + 16 + 7, 3424 .htotal = 240 + 16 + 7 + 5, 3425 .vdisplay = 320, 3426 .vsync_start = 320 + 9, 3427 .vsync_end = 320 + 9 + 1, 3428 .vtotal = 320 + 9 + 1 + 7, 3429 }; 3430 3431 static const struct panel_desc sharp_lq035q7db03 = { 3432 .modes = &sharp_lq035q7db03_mode, 3433 .num_modes = 1, 3434 .bpc = 6, 3435 .size = { 3436 .width = 54, 3437 .height = 72, 3438 }, 3439 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3440 }; 3441 3442 static const struct display_timing sharp_lq101k1ly04_timing = { 3443 .pixelclock = { 60000000, 65000000, 80000000 }, 3444 .hactive = { 1280, 1280, 1280 }, 3445 .hfront_porch = { 20, 20, 20 }, 3446 .hback_porch = { 20, 20, 20 }, 3447 .hsync_len = { 10, 10, 10 }, 3448 .vactive = { 800, 800, 800 }, 3449 .vfront_porch = { 4, 4, 4 }, 3450 .vback_porch = { 4, 4, 4 }, 3451 .vsync_len = { 4, 4, 4 }, 3452 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3453 }; 3454 3455 static const struct panel_desc sharp_lq101k1ly04 = { 3456 .timings = &sharp_lq101k1ly04_timing, 3457 .num_timings = 1, 3458 .bpc = 8, 3459 .size = { 3460 .width = 217, 3461 .height = 136, 3462 }, 3463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3464 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3465 }; 3466 3467 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3468 { /* 50 Hz */ 3469 .clock = 3000, 3470 .hdisplay = 240, 3471 .hsync_start = 240 + 58, 3472 .hsync_end = 240 + 58 + 1, 3473 .htotal = 240 + 58 + 1 + 1, 3474 .vdisplay = 160, 3475 .vsync_start = 160 + 24, 3476 .vsync_end = 160 + 24 + 10, 3477 .vtotal = 160 + 24 + 10 + 6, 3478 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3479 }, 3480 { /* 60 Hz */ 3481 .clock = 3000, 3482 .hdisplay = 240, 3483 .hsync_start = 240 + 8, 3484 .hsync_end = 240 + 8 + 1, 3485 .htotal = 240 + 8 + 1 + 1, 3486 .vdisplay = 160, 3487 .vsync_start = 160 + 24, 3488 .vsync_end = 160 + 24 + 10, 3489 .vtotal = 160 + 24 + 10 + 6, 3490 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3491 }, 3492 }; 3493 3494 static const struct panel_desc sharp_ls020b1dd01d = { 3495 .modes = sharp_ls020b1dd01d_modes, 3496 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3497 .bpc = 6, 3498 .size = { 3499 .width = 42, 3500 .height = 28, 3501 }, 3502 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3503 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3504 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3505 | DRM_BUS_FLAG_SHARP_SIGNALS, 3506 }; 3507 3508 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3509 .clock = 33300, 3510 .hdisplay = 800, 3511 .hsync_start = 800 + 1, 3512 .hsync_end = 800 + 1 + 64, 3513 .htotal = 800 + 1 + 64 + 64, 3514 .vdisplay = 480, 3515 .vsync_start = 480 + 1, 3516 .vsync_end = 480 + 1 + 23, 3517 .vtotal = 480 + 1 + 23 + 22, 3518 }; 3519 3520 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3521 .modes = &shelly_sca07010_bfn_lnn_mode, 3522 .num_modes = 1, 3523 .size = { 3524 .width = 152, 3525 .height = 91, 3526 }, 3527 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3528 }; 3529 3530 static const struct drm_display_mode starry_kr070pe2t_mode = { 3531 .clock = 33000, 3532 .hdisplay = 800, 3533 .hsync_start = 800 + 209, 3534 .hsync_end = 800 + 209 + 1, 3535 .htotal = 800 + 209 + 1 + 45, 3536 .vdisplay = 480, 3537 .vsync_start = 480 + 22, 3538 .vsync_end = 480 + 22 + 1, 3539 .vtotal = 480 + 22 + 1 + 22, 3540 }; 3541 3542 static const struct panel_desc starry_kr070pe2t = { 3543 .modes = &starry_kr070pe2t_mode, 3544 .num_modes = 1, 3545 .bpc = 8, 3546 .size = { 3547 .width = 152, 3548 .height = 86, 3549 }, 3550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3552 .connector_type = DRM_MODE_CONNECTOR_DPI, 3553 }; 3554 3555 static const struct display_timing startek_kd070wvfpa_mode = { 3556 .pixelclock = { 25200000, 27200000, 30500000 }, 3557 .hactive = { 800, 800, 800 }, 3558 .hfront_porch = { 19, 44, 115 }, 3559 .hback_porch = { 5, 16, 101 }, 3560 .hsync_len = { 1, 2, 100 }, 3561 .vactive = { 480, 480, 480 }, 3562 .vfront_porch = { 5, 43, 67 }, 3563 .vback_porch = { 5, 5, 67 }, 3564 .vsync_len = { 1, 2, 66 }, 3565 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3566 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3567 DISPLAY_FLAGS_SYNC_POSEDGE, 3568 }; 3569 3570 static const struct panel_desc startek_kd070wvfpa = { 3571 .timings = &startek_kd070wvfpa_mode, 3572 .num_timings = 1, 3573 .bpc = 8, 3574 .size = { 3575 .width = 152, 3576 .height = 91, 3577 }, 3578 .delay = { 3579 .prepare = 20, 3580 .enable = 200, 3581 .disable = 200, 3582 }, 3583 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3584 .connector_type = DRM_MODE_CONNECTOR_DPI, 3585 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3586 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3587 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3588 }; 3589 3590 static const struct display_timing tsd_tst043015cmhx_timing = { 3591 .pixelclock = { 5000000, 9000000, 12000000 }, 3592 .hactive = { 480, 480, 480 }, 3593 .hfront_porch = { 4, 5, 65 }, 3594 .hback_porch = { 36, 40, 255 }, 3595 .hsync_len = { 1, 1, 1 }, 3596 .vactive = { 272, 272, 272 }, 3597 .vfront_porch = { 2, 8, 97 }, 3598 .vback_porch = { 3, 8, 31 }, 3599 .vsync_len = { 1, 1, 1 }, 3600 3601 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3602 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3603 }; 3604 3605 static const struct panel_desc tsd_tst043015cmhx = { 3606 .timings = &tsd_tst043015cmhx_timing, 3607 .num_timings = 1, 3608 .bpc = 8, 3609 .size = { 3610 .width = 105, 3611 .height = 67, 3612 }, 3613 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3614 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3615 }; 3616 3617 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3618 .clock = 30000, 3619 .hdisplay = 800, 3620 .hsync_start = 800 + 39, 3621 .hsync_end = 800 + 39 + 47, 3622 .htotal = 800 + 39 + 47 + 39, 3623 .vdisplay = 480, 3624 .vsync_start = 480 + 13, 3625 .vsync_end = 480 + 13 + 2, 3626 .vtotal = 480 + 13 + 2 + 29, 3627 }; 3628 3629 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3630 .modes = &tfc_s9700rtwv43tr_01b_mode, 3631 .num_modes = 1, 3632 .bpc = 8, 3633 .size = { 3634 .width = 155, 3635 .height = 90, 3636 }, 3637 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3638 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3639 }; 3640 3641 static const struct display_timing tianma_tm070jdhg30_timing = { 3642 .pixelclock = { 62600000, 68200000, 78100000 }, 3643 .hactive = { 1280, 1280, 1280 }, 3644 .hfront_porch = { 15, 64, 159 }, 3645 .hback_porch = { 5, 5, 5 }, 3646 .hsync_len = { 1, 1, 256 }, 3647 .vactive = { 800, 800, 800 }, 3648 .vfront_porch = { 3, 40, 99 }, 3649 .vback_porch = { 2, 2, 2 }, 3650 .vsync_len = { 1, 1, 128 }, 3651 .flags = DISPLAY_FLAGS_DE_HIGH, 3652 }; 3653 3654 static const struct panel_desc tianma_tm070jdhg30 = { 3655 .timings = &tianma_tm070jdhg30_timing, 3656 .num_timings = 1, 3657 .bpc = 8, 3658 .size = { 3659 .width = 151, 3660 .height = 95, 3661 }, 3662 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3663 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3664 }; 3665 3666 static const struct panel_desc tianma_tm070jvhg33 = { 3667 .timings = &tianma_tm070jdhg30_timing, 3668 .num_timings = 1, 3669 .bpc = 8, 3670 .size = { 3671 .width = 150, 3672 .height = 94, 3673 }, 3674 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3675 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3676 }; 3677 3678 static const struct display_timing tianma_tm070rvhg71_timing = { 3679 .pixelclock = { 27700000, 29200000, 39600000 }, 3680 .hactive = { 800, 800, 800 }, 3681 .hfront_porch = { 12, 40, 212 }, 3682 .hback_porch = { 88, 88, 88 }, 3683 .hsync_len = { 1, 1, 40 }, 3684 .vactive = { 480, 480, 480 }, 3685 .vfront_porch = { 1, 13, 88 }, 3686 .vback_porch = { 32, 32, 32 }, 3687 .vsync_len = { 1, 1, 3 }, 3688 .flags = DISPLAY_FLAGS_DE_HIGH, 3689 }; 3690 3691 static const struct panel_desc tianma_tm070rvhg71 = { 3692 .timings = &tianma_tm070rvhg71_timing, 3693 .num_timings = 1, 3694 .bpc = 8, 3695 .size = { 3696 .width = 154, 3697 .height = 86, 3698 }, 3699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3700 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3701 }; 3702 3703 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3704 { 3705 .clock = 10000, 3706 .hdisplay = 320, 3707 .hsync_start = 320 + 50, 3708 .hsync_end = 320 + 50 + 6, 3709 .htotal = 320 + 50 + 6 + 38, 3710 .vdisplay = 240, 3711 .vsync_start = 240 + 3, 3712 .vsync_end = 240 + 3 + 1, 3713 .vtotal = 240 + 3 + 1 + 17, 3714 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3715 }, 3716 }; 3717 3718 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3719 .modes = ti_nspire_cx_lcd_mode, 3720 .num_modes = 1, 3721 .bpc = 8, 3722 .size = { 3723 .width = 65, 3724 .height = 49, 3725 }, 3726 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3727 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3728 }; 3729 3730 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3731 { 3732 .clock = 10000, 3733 .hdisplay = 320, 3734 .hsync_start = 320 + 6, 3735 .hsync_end = 320 + 6 + 6, 3736 .htotal = 320 + 6 + 6 + 6, 3737 .vdisplay = 240, 3738 .vsync_start = 240 + 0, 3739 .vsync_end = 240 + 0 + 1, 3740 .vtotal = 240 + 0 + 1 + 0, 3741 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3742 }, 3743 }; 3744 3745 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3746 .modes = ti_nspire_classic_lcd_mode, 3747 .num_modes = 1, 3748 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3749 .bpc = 8, 3750 .size = { 3751 .width = 71, 3752 .height = 53, 3753 }, 3754 /* This is the grayscale bus format */ 3755 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3756 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3757 }; 3758 3759 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3760 .clock = 79500, 3761 .hdisplay = 1280, 3762 .hsync_start = 1280 + 192, 3763 .hsync_end = 1280 + 192 + 128, 3764 .htotal = 1280 + 192 + 128 + 64, 3765 .vdisplay = 768, 3766 .vsync_start = 768 + 20, 3767 .vsync_end = 768 + 20 + 7, 3768 .vtotal = 768 + 20 + 7 + 3, 3769 }; 3770 3771 static const struct panel_desc toshiba_lt089ac29000 = { 3772 .modes = &toshiba_lt089ac29000_mode, 3773 .num_modes = 1, 3774 .size = { 3775 .width = 194, 3776 .height = 116, 3777 }, 3778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3779 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3780 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3781 }; 3782 3783 static const struct drm_display_mode tpk_f07a_0102_mode = { 3784 .clock = 33260, 3785 .hdisplay = 800, 3786 .hsync_start = 800 + 40, 3787 .hsync_end = 800 + 40 + 128, 3788 .htotal = 800 + 40 + 128 + 88, 3789 .vdisplay = 480, 3790 .vsync_start = 480 + 10, 3791 .vsync_end = 480 + 10 + 2, 3792 .vtotal = 480 + 10 + 2 + 33, 3793 }; 3794 3795 static const struct panel_desc tpk_f07a_0102 = { 3796 .modes = &tpk_f07a_0102_mode, 3797 .num_modes = 1, 3798 .size = { 3799 .width = 152, 3800 .height = 91, 3801 }, 3802 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3803 }; 3804 3805 static const struct drm_display_mode tpk_f10a_0102_mode = { 3806 .clock = 45000, 3807 .hdisplay = 1024, 3808 .hsync_start = 1024 + 176, 3809 .hsync_end = 1024 + 176 + 5, 3810 .htotal = 1024 + 176 + 5 + 88, 3811 .vdisplay = 600, 3812 .vsync_start = 600 + 20, 3813 .vsync_end = 600 + 20 + 5, 3814 .vtotal = 600 + 20 + 5 + 25, 3815 }; 3816 3817 static const struct panel_desc tpk_f10a_0102 = { 3818 .modes = &tpk_f10a_0102_mode, 3819 .num_modes = 1, 3820 .size = { 3821 .width = 223, 3822 .height = 125, 3823 }, 3824 }; 3825 3826 static const struct display_timing urt_umsh_8596md_timing = { 3827 .pixelclock = { 33260000, 33260000, 33260000 }, 3828 .hactive = { 800, 800, 800 }, 3829 .hfront_porch = { 41, 41, 41 }, 3830 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3831 .hsync_len = { 71, 128, 128 }, 3832 .vactive = { 480, 480, 480 }, 3833 .vfront_porch = { 10, 10, 10 }, 3834 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3835 .vsync_len = { 2, 2, 2 }, 3836 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3837 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3838 }; 3839 3840 static const struct panel_desc urt_umsh_8596md_lvds = { 3841 .timings = &urt_umsh_8596md_timing, 3842 .num_timings = 1, 3843 .bpc = 6, 3844 .size = { 3845 .width = 152, 3846 .height = 91, 3847 }, 3848 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3849 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3850 }; 3851 3852 static const struct panel_desc urt_umsh_8596md_parallel = { 3853 .timings = &urt_umsh_8596md_timing, 3854 .num_timings = 1, 3855 .bpc = 6, 3856 .size = { 3857 .width = 152, 3858 .height = 91, 3859 }, 3860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3861 }; 3862 3863 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3864 .clock = 60000, 3865 .hdisplay = 1024, 3866 .hsync_start = 1024 + 160, 3867 .hsync_end = 1024 + 160 + 100, 3868 .htotal = 1024 + 160 + 100 + 60, 3869 .vdisplay = 600, 3870 .vsync_start = 600 + 12, 3871 .vsync_end = 600 + 12 + 10, 3872 .vtotal = 600 + 12 + 10 + 13, 3873 }; 3874 3875 static const struct panel_desc vivax_tpc9150_panel = { 3876 .modes = &vivax_tpc9150_panel_mode, 3877 .num_modes = 1, 3878 .bpc = 6, 3879 .size = { 3880 .width = 200, 3881 .height = 115, 3882 }, 3883 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3884 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3886 }; 3887 3888 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3889 .clock = 33333, 3890 .hdisplay = 800, 3891 .hsync_start = 800 + 210, 3892 .hsync_end = 800 + 210 + 20, 3893 .htotal = 800 + 210 + 20 + 46, 3894 .vdisplay = 480, 3895 .vsync_start = 480 + 22, 3896 .vsync_end = 480 + 22 + 10, 3897 .vtotal = 480 + 22 + 10 + 23, 3898 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3899 }; 3900 3901 static const struct panel_desc vl050_8048nt_c01 = { 3902 .modes = &vl050_8048nt_c01_mode, 3903 .num_modes = 1, 3904 .bpc = 8, 3905 .size = { 3906 .width = 120, 3907 .height = 76, 3908 }, 3909 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3910 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3911 }; 3912 3913 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3914 .clock = 6410, 3915 .hdisplay = 320, 3916 .hsync_start = 320 + 20, 3917 .hsync_end = 320 + 20 + 30, 3918 .htotal = 320 + 20 + 30 + 38, 3919 .vdisplay = 240, 3920 .vsync_start = 240 + 4, 3921 .vsync_end = 240 + 4 + 3, 3922 .vtotal = 240 + 4 + 3 + 15, 3923 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3924 }; 3925 3926 static const struct panel_desc winstar_wf35ltiacd = { 3927 .modes = &winstar_wf35ltiacd_mode, 3928 .num_modes = 1, 3929 .bpc = 8, 3930 .size = { 3931 .width = 70, 3932 .height = 53, 3933 }, 3934 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3935 }; 3936 3937 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3938 .clock = 51200, 3939 .hdisplay = 1024, 3940 .hsync_start = 1024 + 100, 3941 .hsync_end = 1024 + 100 + 100, 3942 .htotal = 1024 + 100 + 100 + 120, 3943 .vdisplay = 600, 3944 .vsync_start = 600 + 10, 3945 .vsync_end = 600 + 10 + 10, 3946 .vtotal = 600 + 10 + 10 + 15, 3947 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3948 }; 3949 3950 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3951 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3952 .num_modes = 1, 3953 .bpc = 8, 3954 .size = { 3955 .width = 154, 3956 .height = 90, 3957 }, 3958 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3959 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3960 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3961 }; 3962 3963 static const struct drm_display_mode arm_rtsm_mode[] = { 3964 { 3965 .clock = 65000, 3966 .hdisplay = 1024, 3967 .hsync_start = 1024 + 24, 3968 .hsync_end = 1024 + 24 + 136, 3969 .htotal = 1024 + 24 + 136 + 160, 3970 .vdisplay = 768, 3971 .vsync_start = 768 + 3, 3972 .vsync_end = 768 + 3 + 6, 3973 .vtotal = 768 + 3 + 6 + 29, 3974 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3975 }, 3976 }; 3977 3978 static const struct panel_desc arm_rtsm = { 3979 .modes = arm_rtsm_mode, 3980 .num_modes = 1, 3981 .bpc = 8, 3982 .size = { 3983 .width = 400, 3984 .height = 300, 3985 }, 3986 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3987 }; 3988 3989 static const struct of_device_id platform_of_match[] = { 3990 { 3991 .compatible = "ampire,am-1280800n3tzqw-t00h", 3992 .data = &ire_am_1280800n3tzqw_t00h, 3993 }, { 3994 .compatible = "ampire,am-480272h3tmqw-t01h", 3995 .data = &ire_am_480272h3tmqw_t01h, 3996 }, { 3997 .compatible = "ampire,am800480r3tmqwa1h", 3998 .data = &ire_am800480r3tmqwa1h, 3999 }, { 4000 .compatible = "ampire,am800600p5tmqw-tb8h", 4001 .data = &ire_am800600p5tmqwtb8h, 4002 }, { 4003 .compatible = "arm,rtsm-display", 4004 .data = &arm_rtsm, 4005 }, { 4006 .compatible = "armadeus,st0700-adapt", 4007 .data = &armadeus_st0700_adapt, 4008 }, { 4009 .compatible = "auo,b101aw03", 4010 .data = &auo_b101aw03, 4011 }, { 4012 .compatible = "auo,b101xtn01", 4013 .data = &auo_b101xtn01, 4014 }, { 4015 .compatible = "auo,g070vvn01", 4016 .data = &auo_g070vvn01, 4017 }, { 4018 .compatible = "auo,g101evn010", 4019 .data = &auo_g101evn010, 4020 }, { 4021 .compatible = "auo,g104sn02", 4022 .data = &auo_g104sn02, 4023 }, { 4024 .compatible = "auo,g121ean01", 4025 .data = &auo_g121ean01, 4026 }, { 4027 .compatible = "auo,g133han01", 4028 .data = &auo_g133han01, 4029 }, { 4030 .compatible = "auo,g156xtn01", 4031 .data = &auo_g156xtn01, 4032 }, { 4033 .compatible = "auo,g185han01", 4034 .data = &auo_g185han01, 4035 }, { 4036 .compatible = "auo,g190ean01", 4037 .data = &auo_g190ean01, 4038 }, { 4039 .compatible = "auo,p320hvn03", 4040 .data = &auo_p320hvn03, 4041 }, { 4042 .compatible = "auo,t215hvn01", 4043 .data = &auo_t215hvn01, 4044 }, { 4045 .compatible = "avic,tm070ddh03", 4046 .data = &avic_tm070ddh03, 4047 }, { 4048 .compatible = "bananapi,s070wv20-ct16", 4049 .data = &bananapi_s070wv20_ct16, 4050 }, { 4051 .compatible = "boe,ev121wxm-n10-1850", 4052 .data = &boe_ev121wxm_n10_1850, 4053 }, { 4054 .compatible = "boe,hv070wsa-100", 4055 .data = &boe_hv070wsa 4056 }, { 4057 .compatible = "cdtech,s043wq26h-ct7", 4058 .data = &cdtech_s043wq26h_ct7, 4059 }, { 4060 .compatible = "cdtech,s070pws19hp-fc21", 4061 .data = &cdtech_s070pws19hp_fc21, 4062 }, { 4063 .compatible = "cdtech,s070swv29hg-dc44", 4064 .data = &cdtech_s070swv29hg_dc44, 4065 }, { 4066 .compatible = "cdtech,s070wv95-ct16", 4067 .data = &cdtech_s070wv95_ct16, 4068 }, { 4069 .compatible = "chefree,ch101olhlwh-002", 4070 .data = &chefree_ch101olhlwh_002, 4071 }, { 4072 .compatible = "chunghwa,claa070wp03xg", 4073 .data = &chunghwa_claa070wp03xg, 4074 }, { 4075 .compatible = "chunghwa,claa101wa01a", 4076 .data = &chunghwa_claa101wa01a 4077 }, { 4078 .compatible = "chunghwa,claa101wb01", 4079 .data = &chunghwa_claa101wb01 4080 }, { 4081 .compatible = "dataimage,fg040346dsswbg04", 4082 .data = &dataimage_fg040346dsswbg04, 4083 }, { 4084 .compatible = "dataimage,fg1001l0dsswmg01", 4085 .data = &dataimage_fg1001l0dsswmg01, 4086 }, { 4087 .compatible = "dataimage,scf0700c48ggu18", 4088 .data = &dataimage_scf0700c48ggu18, 4089 }, { 4090 .compatible = "dlc,dlc0700yzg-1", 4091 .data = &dlc_dlc0700yzg_1, 4092 }, { 4093 .compatible = "dlc,dlc1010gig", 4094 .data = &dlc_dlc1010gig, 4095 }, { 4096 .compatible = "edt,et035012dm6", 4097 .data = &edt_et035012dm6, 4098 }, { 4099 .compatible = "edt,etm0350g0dh6", 4100 .data = &edt_etm0350g0dh6, 4101 }, { 4102 .compatible = "edt,etm043080dh6gp", 4103 .data = &edt_etm043080dh6gp, 4104 }, { 4105 .compatible = "edt,etm0430g0dh6", 4106 .data = &edt_etm0430g0dh6, 4107 }, { 4108 .compatible = "edt,et057090dhu", 4109 .data = &edt_et057090dhu, 4110 }, { 4111 .compatible = "edt,et070080dh6", 4112 .data = &edt_etm0700g0dh6, 4113 }, { 4114 .compatible = "edt,etm0700g0dh6", 4115 .data = &edt_etm0700g0dh6, 4116 }, { 4117 .compatible = "edt,etm0700g0bdh6", 4118 .data = &edt_etm0700g0bdh6, 4119 }, { 4120 .compatible = "edt,etm0700g0edh6", 4121 .data = &edt_etm0700g0bdh6, 4122 }, { 4123 .compatible = "edt,etml0700y5dha", 4124 .data = &edt_etml0700y5dha, 4125 }, { 4126 .compatible = "edt,etmv570g2dhu", 4127 .data = &edt_etmv570g2dhu, 4128 }, { 4129 .compatible = "eink,vb3300-kca", 4130 .data = &eink_vb3300_kca, 4131 }, { 4132 .compatible = "evervision,vgg804821", 4133 .data = &evervision_vgg804821, 4134 }, { 4135 .compatible = "foxlink,fl500wvr00-a0t", 4136 .data = &foxlink_fl500wvr00_a0t, 4137 }, { 4138 .compatible = "frida,frd350h54004", 4139 .data = &frida_frd350h54004, 4140 }, { 4141 .compatible = "friendlyarm,hd702e", 4142 .data = &friendlyarm_hd702e, 4143 }, { 4144 .compatible = "giantplus,gpg482739qs5", 4145 .data = &giantplus_gpg482739qs5 4146 }, { 4147 .compatible = "giantplus,gpm940b0", 4148 .data = &giantplus_gpm940b0, 4149 }, { 4150 .compatible = "hannstar,hsd070pww1", 4151 .data = &hannstar_hsd070pww1, 4152 }, { 4153 .compatible = "hannstar,hsd100pxn1", 4154 .data = &hannstar_hsd100pxn1, 4155 }, { 4156 .compatible = "hannstar,hsd101pww2", 4157 .data = &hannstar_hsd101pww2, 4158 }, { 4159 .compatible = "hit,tx23d38vm0caa", 4160 .data = &hitachi_tx23d38vm0caa 4161 }, { 4162 .compatible = "innolux,at043tn24", 4163 .data = &innolux_at043tn24, 4164 }, { 4165 .compatible = "innolux,at070tn92", 4166 .data = &innolux_at070tn92, 4167 }, { 4168 .compatible = "innolux,g070ace-l01", 4169 .data = &innolux_g070ace_l01, 4170 }, { 4171 .compatible = "innolux,g070y2-l01", 4172 .data = &innolux_g070y2_l01, 4173 }, { 4174 .compatible = "innolux,g070y2-t02", 4175 .data = &innolux_g070y2_t02, 4176 }, { 4177 .compatible = "innolux,g101ice-l01", 4178 .data = &innolux_g101ice_l01 4179 }, { 4180 .compatible = "innolux,g121i1-l01", 4181 .data = &innolux_g121i1_l01 4182 }, { 4183 .compatible = "innolux,g121x1-l03", 4184 .data = &innolux_g121x1_l03, 4185 }, { 4186 .compatible = "innolux,n156bge-l21", 4187 .data = &innolux_n156bge_l21, 4188 }, { 4189 .compatible = "innolux,zj070na-01p", 4190 .data = &innolux_zj070na_01p, 4191 }, { 4192 .compatible = "koe,tx14d24vm1bpa", 4193 .data = &koe_tx14d24vm1bpa, 4194 }, { 4195 .compatible = "koe,tx26d202vm0bwa", 4196 .data = &koe_tx26d202vm0bwa, 4197 }, { 4198 .compatible = "koe,tx31d200vm0baa", 4199 .data = &koe_tx31d200vm0baa, 4200 }, { 4201 .compatible = "kyo,tcg121xglp", 4202 .data = &kyo_tcg121xglp, 4203 }, { 4204 .compatible = "lemaker,bl035-rgb-002", 4205 .data = &lemaker_bl035_rgb_002, 4206 }, { 4207 .compatible = "lg,lb070wv8", 4208 .data = &lg_lb070wv8, 4209 }, { 4210 .compatible = "logicpd,type28", 4211 .data = &logicpd_type_28, 4212 }, { 4213 .compatible = "logictechno,lt161010-2nhc", 4214 .data = &logictechno_lt161010_2nh, 4215 }, { 4216 .compatible = "logictechno,lt161010-2nhr", 4217 .data = &logictechno_lt161010_2nh, 4218 }, { 4219 .compatible = "logictechno,lt170410-2whc", 4220 .data = &logictechno_lt170410_2whc, 4221 }, { 4222 .compatible = "logictechno,lttd800480070-l2rt", 4223 .data = &logictechno_lttd800480070_l2rt, 4224 }, { 4225 .compatible = "logictechno,lttd800480070-l6wh-rt", 4226 .data = &logictechno_lttd800480070_l6wh_rt, 4227 }, { 4228 .compatible = "mitsubishi,aa070mc01-ca1", 4229 .data = &mitsubishi_aa070mc01, 4230 }, { 4231 .compatible = "multi-inno,mi0700s4t-6", 4232 .data = &multi_inno_mi0700s4t_6, 4233 }, { 4234 .compatible = "multi-inno,mi0800ft-9", 4235 .data = &multi_inno_mi0800ft_9, 4236 }, { 4237 .compatible = "multi-inno,mi1010ait-1cp", 4238 .data = &multi_inno_mi1010ait_1cp, 4239 }, { 4240 .compatible = "nec,nl12880bc20-05", 4241 .data = &nec_nl12880bc20_05, 4242 }, { 4243 .compatible = "nec,nl4827hc19-05b", 4244 .data = &nec_nl4827hc19_05b, 4245 }, { 4246 .compatible = "netron-dy,e231732", 4247 .data = &netron_dy_e231732, 4248 }, { 4249 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4250 .data = &newhaven_nhd_43_480272ef_atxl, 4251 }, { 4252 .compatible = "nlt,nl192108ac18-02d", 4253 .data = &nlt_nl192108ac18_02d, 4254 }, { 4255 .compatible = "nvd,9128", 4256 .data = &nvd_9128, 4257 }, { 4258 .compatible = "okaya,rs800480t-7x0gp", 4259 .data = &okaya_rs800480t_7x0gp, 4260 }, { 4261 .compatible = "olimex,lcd-olinuxino-43-ts", 4262 .data = &olimex_lcd_olinuxino_43ts, 4263 }, { 4264 .compatible = "ontat,yx700wv03", 4265 .data = &ontat_yx700wv03, 4266 }, { 4267 .compatible = "ortustech,com37h3m05dtc", 4268 .data = &ortustech_com37h3m, 4269 }, { 4270 .compatible = "ortustech,com37h3m99dtc", 4271 .data = &ortustech_com37h3m, 4272 }, { 4273 .compatible = "ortustech,com43h4m85ulc", 4274 .data = &ortustech_com43h4m85ulc, 4275 }, { 4276 .compatible = "osddisplays,osd070t1718-19ts", 4277 .data = &osddisplays_osd070t1718_19ts, 4278 }, { 4279 .compatible = "pda,91-00156-a0", 4280 .data = &pda_91_00156_a0, 4281 }, { 4282 .compatible = "powertip,ph800480t013-idf02", 4283 .data = &powertip_ph800480t013_idf02, 4284 }, { 4285 .compatible = "qiaodian,qd43003c0-40", 4286 .data = &qd43003c0_40, 4287 }, { 4288 .compatible = "qishenglong,gopher2b-lcd", 4289 .data = &qishenglong_gopher2b_lcd, 4290 }, { 4291 .compatible = "rocktech,rk070er9427", 4292 .data = &rocktech_rk070er9427, 4293 }, { 4294 .compatible = "rocktech,rk101ii01d-ct", 4295 .data = &rocktech_rk101ii01d_ct, 4296 }, { 4297 .compatible = "samsung,ltl101al01", 4298 .data = &samsung_ltl101al01, 4299 }, { 4300 .compatible = "samsung,ltn101nt05", 4301 .data = &samsung_ltn101nt05, 4302 }, { 4303 .compatible = "satoz,sat050at40h12r2", 4304 .data = &satoz_sat050at40h12r2, 4305 }, { 4306 .compatible = "sharp,lq035q7db03", 4307 .data = &sharp_lq035q7db03, 4308 }, { 4309 .compatible = "sharp,lq070y3dg3b", 4310 .data = &sharp_lq070y3dg3b, 4311 }, { 4312 .compatible = "sharp,lq101k1ly04", 4313 .data = &sharp_lq101k1ly04, 4314 }, { 4315 .compatible = "sharp,ls020b1dd01d", 4316 .data = &sharp_ls020b1dd01d, 4317 }, { 4318 .compatible = "shelly,sca07010-bfn-lnn", 4319 .data = &shelly_sca07010_bfn_lnn, 4320 }, { 4321 .compatible = "starry,kr070pe2t", 4322 .data = &starry_kr070pe2t, 4323 }, { 4324 .compatible = "startek,kd070wvfpa", 4325 .data = &startek_kd070wvfpa, 4326 }, { 4327 .compatible = "team-source-display,tst043015cmhx", 4328 .data = &tsd_tst043015cmhx, 4329 }, { 4330 .compatible = "tfc,s9700rtwv43tr-01b", 4331 .data = &tfc_s9700rtwv43tr_01b, 4332 }, { 4333 .compatible = "tianma,tm070jdhg30", 4334 .data = &tianma_tm070jdhg30, 4335 }, { 4336 .compatible = "tianma,tm070jvhg33", 4337 .data = &tianma_tm070jvhg33, 4338 }, { 4339 .compatible = "tianma,tm070rvhg71", 4340 .data = &tianma_tm070rvhg71, 4341 }, { 4342 .compatible = "ti,nspire-cx-lcd-panel", 4343 .data = &ti_nspire_cx_lcd_panel, 4344 }, { 4345 .compatible = "ti,nspire-classic-lcd-panel", 4346 .data = &ti_nspire_classic_lcd_panel, 4347 }, { 4348 .compatible = "toshiba,lt089ac29000", 4349 .data = &toshiba_lt089ac29000, 4350 }, { 4351 .compatible = "tpk,f07a-0102", 4352 .data = &tpk_f07a_0102, 4353 }, { 4354 .compatible = "tpk,f10a-0102", 4355 .data = &tpk_f10a_0102, 4356 }, { 4357 .compatible = "urt,umsh-8596md-t", 4358 .data = &urt_umsh_8596md_parallel, 4359 }, { 4360 .compatible = "urt,umsh-8596md-1t", 4361 .data = &urt_umsh_8596md_parallel, 4362 }, { 4363 .compatible = "urt,umsh-8596md-7t", 4364 .data = &urt_umsh_8596md_parallel, 4365 }, { 4366 .compatible = "urt,umsh-8596md-11t", 4367 .data = &urt_umsh_8596md_lvds, 4368 }, { 4369 .compatible = "urt,umsh-8596md-19t", 4370 .data = &urt_umsh_8596md_lvds, 4371 }, { 4372 .compatible = "urt,umsh-8596md-20t", 4373 .data = &urt_umsh_8596md_parallel, 4374 }, { 4375 .compatible = "vivax,tpc9150-panel", 4376 .data = &vivax_tpc9150_panel, 4377 }, { 4378 .compatible = "vxt,vl050-8048nt-c01", 4379 .data = &vl050_8048nt_c01, 4380 }, { 4381 .compatible = "winstar,wf35ltiacd", 4382 .data = &winstar_wf35ltiacd, 4383 }, { 4384 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4385 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4386 }, { 4387 /* Must be the last entry */ 4388 .compatible = "panel-dpi", 4389 .data = &panel_dpi, 4390 }, { 4391 /* sentinel */ 4392 } 4393 }; 4394 MODULE_DEVICE_TABLE(of, platform_of_match); 4395 4396 static int panel_simple_platform_probe(struct platform_device *pdev) 4397 { 4398 const struct of_device_id *id; 4399 4400 id = of_match_node(platform_of_match, pdev->dev.of_node); 4401 if (!id) 4402 return -ENODEV; 4403 4404 return panel_simple_probe(&pdev->dev, id->data); 4405 } 4406 4407 static int panel_simple_platform_remove(struct platform_device *pdev) 4408 { 4409 panel_simple_remove(&pdev->dev); 4410 4411 return 0; 4412 } 4413 4414 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4415 { 4416 panel_simple_shutdown(&pdev->dev); 4417 } 4418 4419 static const struct dev_pm_ops panel_simple_pm_ops = { 4420 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4421 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4422 pm_runtime_force_resume) 4423 }; 4424 4425 static struct platform_driver panel_simple_platform_driver = { 4426 .driver = { 4427 .name = "panel-simple", 4428 .of_match_table = platform_of_match, 4429 .pm = &panel_simple_pm_ops, 4430 }, 4431 .probe = panel_simple_platform_probe, 4432 .remove = panel_simple_platform_remove, 4433 .shutdown = panel_simple_platform_shutdown, 4434 }; 4435 4436 struct panel_desc_dsi { 4437 struct panel_desc desc; 4438 4439 unsigned long flags; 4440 enum mipi_dsi_pixel_format format; 4441 unsigned int lanes; 4442 }; 4443 4444 static const struct drm_display_mode auo_b080uan01_mode = { 4445 .clock = 154500, 4446 .hdisplay = 1200, 4447 .hsync_start = 1200 + 62, 4448 .hsync_end = 1200 + 62 + 4, 4449 .htotal = 1200 + 62 + 4 + 62, 4450 .vdisplay = 1920, 4451 .vsync_start = 1920 + 9, 4452 .vsync_end = 1920 + 9 + 2, 4453 .vtotal = 1920 + 9 + 2 + 8, 4454 }; 4455 4456 static const struct panel_desc_dsi auo_b080uan01 = { 4457 .desc = { 4458 .modes = &auo_b080uan01_mode, 4459 .num_modes = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 108, 4463 .height = 272, 4464 }, 4465 .connector_type = DRM_MODE_CONNECTOR_DSI, 4466 }, 4467 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4468 .format = MIPI_DSI_FMT_RGB888, 4469 .lanes = 4, 4470 }; 4471 4472 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4473 .clock = 160000, 4474 .hdisplay = 1200, 4475 .hsync_start = 1200 + 120, 4476 .hsync_end = 1200 + 120 + 20, 4477 .htotal = 1200 + 120 + 20 + 21, 4478 .vdisplay = 1920, 4479 .vsync_start = 1920 + 21, 4480 .vsync_end = 1920 + 21 + 3, 4481 .vtotal = 1920 + 21 + 3 + 18, 4482 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4483 }; 4484 4485 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4486 .desc = { 4487 .modes = &boe_tv080wum_nl0_mode, 4488 .num_modes = 1, 4489 .size = { 4490 .width = 107, 4491 .height = 172, 4492 }, 4493 .connector_type = DRM_MODE_CONNECTOR_DSI, 4494 }, 4495 .flags = MIPI_DSI_MODE_VIDEO | 4496 MIPI_DSI_MODE_VIDEO_BURST | 4497 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4498 .format = MIPI_DSI_FMT_RGB888, 4499 .lanes = 4, 4500 }; 4501 4502 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4503 .clock = 71000, 4504 .hdisplay = 800, 4505 .hsync_start = 800 + 32, 4506 .hsync_end = 800 + 32 + 1, 4507 .htotal = 800 + 32 + 1 + 57, 4508 .vdisplay = 1280, 4509 .vsync_start = 1280 + 28, 4510 .vsync_end = 1280 + 28 + 1, 4511 .vtotal = 1280 + 28 + 1 + 14, 4512 }; 4513 4514 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4515 .desc = { 4516 .modes = &lg_ld070wx3_sl01_mode, 4517 .num_modes = 1, 4518 .bpc = 8, 4519 .size = { 4520 .width = 94, 4521 .height = 151, 4522 }, 4523 .connector_type = DRM_MODE_CONNECTOR_DSI, 4524 }, 4525 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4526 .format = MIPI_DSI_FMT_RGB888, 4527 .lanes = 4, 4528 }; 4529 4530 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4531 .clock = 67000, 4532 .hdisplay = 720, 4533 .hsync_start = 720 + 12, 4534 .hsync_end = 720 + 12 + 4, 4535 .htotal = 720 + 12 + 4 + 112, 4536 .vdisplay = 1280, 4537 .vsync_start = 1280 + 8, 4538 .vsync_end = 1280 + 8 + 4, 4539 .vtotal = 1280 + 8 + 4 + 12, 4540 }; 4541 4542 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4543 .desc = { 4544 .modes = &lg_lh500wx1_sd03_mode, 4545 .num_modes = 1, 4546 .bpc = 8, 4547 .size = { 4548 .width = 62, 4549 .height = 110, 4550 }, 4551 .connector_type = DRM_MODE_CONNECTOR_DSI, 4552 }, 4553 .flags = MIPI_DSI_MODE_VIDEO, 4554 .format = MIPI_DSI_FMT_RGB888, 4555 .lanes = 4, 4556 }; 4557 4558 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4559 .clock = 157200, 4560 .hdisplay = 1920, 4561 .hsync_start = 1920 + 154, 4562 .hsync_end = 1920 + 154 + 16, 4563 .htotal = 1920 + 154 + 16 + 32, 4564 .vdisplay = 1200, 4565 .vsync_start = 1200 + 17, 4566 .vsync_end = 1200 + 17 + 2, 4567 .vtotal = 1200 + 17 + 2 + 16, 4568 }; 4569 4570 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4571 .desc = { 4572 .modes = &panasonic_vvx10f004b00_mode, 4573 .num_modes = 1, 4574 .bpc = 8, 4575 .size = { 4576 .width = 217, 4577 .height = 136, 4578 }, 4579 .connector_type = DRM_MODE_CONNECTOR_DSI, 4580 }, 4581 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4582 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4583 .format = MIPI_DSI_FMT_RGB888, 4584 .lanes = 4, 4585 }; 4586 4587 static const struct drm_display_mode lg_acx467akm_7_mode = { 4588 .clock = 150000, 4589 .hdisplay = 1080, 4590 .hsync_start = 1080 + 2, 4591 .hsync_end = 1080 + 2 + 2, 4592 .htotal = 1080 + 2 + 2 + 2, 4593 .vdisplay = 1920, 4594 .vsync_start = 1920 + 2, 4595 .vsync_end = 1920 + 2 + 2, 4596 .vtotal = 1920 + 2 + 2 + 2, 4597 }; 4598 4599 static const struct panel_desc_dsi lg_acx467akm_7 = { 4600 .desc = { 4601 .modes = &lg_acx467akm_7_mode, 4602 .num_modes = 1, 4603 .bpc = 8, 4604 .size = { 4605 .width = 62, 4606 .height = 110, 4607 }, 4608 .connector_type = DRM_MODE_CONNECTOR_DSI, 4609 }, 4610 .flags = 0, 4611 .format = MIPI_DSI_FMT_RGB888, 4612 .lanes = 4, 4613 }; 4614 4615 static const struct drm_display_mode osd101t2045_53ts_mode = { 4616 .clock = 154500, 4617 .hdisplay = 1920, 4618 .hsync_start = 1920 + 112, 4619 .hsync_end = 1920 + 112 + 16, 4620 .htotal = 1920 + 112 + 16 + 32, 4621 .vdisplay = 1200, 4622 .vsync_start = 1200 + 16, 4623 .vsync_end = 1200 + 16 + 2, 4624 .vtotal = 1200 + 16 + 2 + 16, 4625 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4626 }; 4627 4628 static const struct panel_desc_dsi osd101t2045_53ts = { 4629 .desc = { 4630 .modes = &osd101t2045_53ts_mode, 4631 .num_modes = 1, 4632 .bpc = 8, 4633 .size = { 4634 .width = 217, 4635 .height = 136, 4636 }, 4637 .connector_type = DRM_MODE_CONNECTOR_DSI, 4638 }, 4639 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4640 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4641 MIPI_DSI_MODE_NO_EOT_PACKET, 4642 .format = MIPI_DSI_FMT_RGB888, 4643 .lanes = 4, 4644 }; 4645 4646 static const struct of_device_id dsi_of_match[] = { 4647 { 4648 .compatible = "auo,b080uan01", 4649 .data = &auo_b080uan01 4650 }, { 4651 .compatible = "boe,tv080wum-nl0", 4652 .data = &boe_tv080wum_nl0 4653 }, { 4654 .compatible = "lg,ld070wx3-sl01", 4655 .data = &lg_ld070wx3_sl01 4656 }, { 4657 .compatible = "lg,lh500wx1-sd03", 4658 .data = &lg_lh500wx1_sd03 4659 }, { 4660 .compatible = "panasonic,vvx10f004b00", 4661 .data = &panasonic_vvx10f004b00 4662 }, { 4663 .compatible = "lg,acx467akm-7", 4664 .data = &lg_acx467akm_7 4665 }, { 4666 .compatible = "osddisplays,osd101t2045-53ts", 4667 .data = &osd101t2045_53ts 4668 }, { 4669 /* sentinel */ 4670 } 4671 }; 4672 MODULE_DEVICE_TABLE(of, dsi_of_match); 4673 4674 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4675 { 4676 const struct panel_desc_dsi *desc; 4677 const struct of_device_id *id; 4678 int err; 4679 4680 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4681 if (!id) 4682 return -ENODEV; 4683 4684 desc = id->data; 4685 4686 err = panel_simple_probe(&dsi->dev, &desc->desc); 4687 if (err < 0) 4688 return err; 4689 4690 dsi->mode_flags = desc->flags; 4691 dsi->format = desc->format; 4692 dsi->lanes = desc->lanes; 4693 4694 err = mipi_dsi_attach(dsi); 4695 if (err) { 4696 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4697 4698 drm_panel_remove(&panel->base); 4699 } 4700 4701 return err; 4702 } 4703 4704 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4705 { 4706 int err; 4707 4708 err = mipi_dsi_detach(dsi); 4709 if (err < 0) 4710 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4711 4712 panel_simple_remove(&dsi->dev); 4713 } 4714 4715 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4716 { 4717 panel_simple_shutdown(&dsi->dev); 4718 } 4719 4720 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4721 .driver = { 4722 .name = "panel-simple-dsi", 4723 .of_match_table = dsi_of_match, 4724 .pm = &panel_simple_pm_ops, 4725 }, 4726 .probe = panel_simple_dsi_probe, 4727 .remove = panel_simple_dsi_remove, 4728 .shutdown = panel_simple_dsi_shutdown, 4729 }; 4730 4731 static int __init panel_simple_init(void) 4732 { 4733 int err; 4734 4735 err = platform_driver_register(&panel_simple_platform_driver); 4736 if (err < 0) 4737 return err; 4738 4739 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4740 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4741 if (err < 0) 4742 goto err_did_platform_register; 4743 } 4744 4745 return 0; 4746 4747 err_did_platform_register: 4748 platform_driver_unregister(&panel_simple_platform_driver); 4749 4750 return err; 4751 } 4752 module_init(panel_simple_init); 4753 4754 static void __exit panel_simple_exit(void) 4755 { 4756 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4757 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4758 4759 platform_driver_unregister(&panel_simple_platform_driver); 4760 } 4761 module_exit(panel_simple_exit); 4762 4763 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4764 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4765 MODULE_LICENSE("GPL and additional rights"); 4766