1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * struct panel_desc 43 * @modes: Pointer to array of fixed modes appropriate for this panel. If 44 * only one mode then this can just be the address of this the mode. 45 * NOTE: cannot be used with "timings" and also if this is specified 46 * then you cannot override the mode in the device tree. 47 * @num_modes: Number of elements in modes array. 48 * @timings: Pointer to array of display timings. NOTE: cannot be used with 49 * "modes" and also these will be used to validate a device tree 50 * override if one is present. 51 * @num_timings: Number of elements in timings array. 52 * @bpc: Bits per color. 53 * @size: Structure containing the physical size of this panel. 54 * @delay: Structure containing various delay values for this panel. 55 * @bus_format: See MEDIA_BUS_FMT_... defines. 56 * @bus_flags: See DRM_BUS_FLAG_... defines. 57 * @connector_type: LVDS, eDP, DSI, DPI, etc. 58 */ 59 struct panel_desc { 60 const struct drm_display_mode *modes; 61 unsigned int num_modes; 62 const struct display_timing *timings; 63 unsigned int num_timings; 64 65 unsigned int bpc; 66 67 /** 68 * @width: width (in millimeters) of the panel's active display area 69 * @height: height (in millimeters) of the panel's active display area 70 */ 71 struct { 72 unsigned int width; 73 unsigned int height; 74 } size; 75 76 /** 77 * @prepare: the time (in milliseconds) that it takes for the panel to 78 * become ready and start receiving video data 79 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 80 * Plug Detect isn't used. 81 * @enable: the time (in milliseconds) that it takes for the panel to 82 * display the first valid frame after starting to receive 83 * video data 84 * @disable: the time (in milliseconds) that it takes for the panel to 85 * turn the display off (no content is visible) 86 * @unprepare: the time (in milliseconds) that it takes for the panel 87 * to power itself down completely 88 */ 89 struct { 90 unsigned int prepare; 91 unsigned int hpd_absent_delay; 92 unsigned int enable; 93 unsigned int disable; 94 unsigned int unprepare; 95 } delay; 96 97 u32 bus_format; 98 u32 bus_flags; 99 int connector_type; 100 }; 101 102 struct panel_simple { 103 struct drm_panel base; 104 bool prepared; 105 bool enabled; 106 bool no_hpd; 107 108 const struct panel_desc *desc; 109 110 struct regulator *supply; 111 struct i2c_adapter *ddc; 112 113 struct gpio_desc *enable_gpio; 114 struct gpio_desc *hpd_gpio; 115 116 struct drm_display_mode override_mode; 117 118 enum drm_panel_orientation orientation; 119 }; 120 121 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 122 { 123 return container_of(panel, struct panel_simple, base); 124 } 125 126 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 127 struct drm_connector *connector) 128 { 129 struct drm_display_mode *mode; 130 unsigned int i, num = 0; 131 132 for (i = 0; i < panel->desc->num_timings; i++) { 133 const struct display_timing *dt = &panel->desc->timings[i]; 134 struct videomode vm; 135 136 videomode_from_timing(dt, &vm); 137 mode = drm_mode_create(connector->dev); 138 if (!mode) { 139 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 140 dt->hactive.typ, dt->vactive.typ); 141 continue; 142 } 143 144 drm_display_mode_from_videomode(&vm, mode); 145 146 mode->type |= DRM_MODE_TYPE_DRIVER; 147 148 if (panel->desc->num_timings == 1) 149 mode->type |= DRM_MODE_TYPE_PREFERRED; 150 151 drm_mode_probed_add(connector, mode); 152 num++; 153 } 154 155 return num; 156 } 157 158 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 159 struct drm_connector *connector) 160 { 161 struct drm_display_mode *mode; 162 unsigned int i, num = 0; 163 164 for (i = 0; i < panel->desc->num_modes; i++) { 165 const struct drm_display_mode *m = &panel->desc->modes[i]; 166 167 mode = drm_mode_duplicate(connector->dev, m); 168 if (!mode) { 169 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 170 m->hdisplay, m->vdisplay, 171 drm_mode_vrefresh(m)); 172 continue; 173 } 174 175 mode->type |= DRM_MODE_TYPE_DRIVER; 176 177 if (panel->desc->num_modes == 1) 178 mode->type |= DRM_MODE_TYPE_PREFERRED; 179 180 drm_mode_set_name(mode); 181 182 drm_mode_probed_add(connector, mode); 183 num++; 184 } 185 186 return num; 187 } 188 189 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 190 struct drm_connector *connector) 191 { 192 struct drm_display_mode *mode; 193 bool has_override = panel->override_mode.type; 194 unsigned int num = 0; 195 196 if (!panel->desc) 197 return 0; 198 199 if (has_override) { 200 mode = drm_mode_duplicate(connector->dev, 201 &panel->override_mode); 202 if (mode) { 203 drm_mode_probed_add(connector, mode); 204 num = 1; 205 } else { 206 dev_err(panel->base.dev, "failed to add override mode\n"); 207 } 208 } 209 210 /* Only add timings if override was not there or failed to validate */ 211 if (num == 0 && panel->desc->num_timings) 212 num = panel_simple_get_timings_modes(panel, connector); 213 214 /* 215 * Only add fixed modes if timings/override added no mode. 216 * 217 * We should only ever have either the display timings specified 218 * or a fixed mode. Anything else is rather bogus. 219 */ 220 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 221 if (num == 0) 222 num = panel_simple_get_display_modes(panel, connector); 223 224 connector->display_info.bpc = panel->desc->bpc; 225 connector->display_info.width_mm = panel->desc->size.width; 226 connector->display_info.height_mm = panel->desc->size.height; 227 if (panel->desc->bus_format) 228 drm_display_info_set_bus_formats(&connector->display_info, 229 &panel->desc->bus_format, 1); 230 connector->display_info.bus_flags = panel->desc->bus_flags; 231 232 return num; 233 } 234 235 static int panel_simple_disable(struct drm_panel *panel) 236 { 237 struct panel_simple *p = to_panel_simple(panel); 238 239 if (!p->enabled) 240 return 0; 241 242 if (p->desc->delay.disable) 243 msleep(p->desc->delay.disable); 244 245 p->enabled = false; 246 247 return 0; 248 } 249 250 static int panel_simple_unprepare(struct drm_panel *panel) 251 { 252 struct panel_simple *p = to_panel_simple(panel); 253 254 if (!p->prepared) 255 return 0; 256 257 gpiod_set_value_cansleep(p->enable_gpio, 0); 258 259 regulator_disable(p->supply); 260 261 if (p->desc->delay.unprepare) 262 msleep(p->desc->delay.unprepare); 263 264 p->prepared = false; 265 266 return 0; 267 } 268 269 static int panel_simple_get_hpd_gpio(struct device *dev, 270 struct panel_simple *p, bool from_probe) 271 { 272 int err; 273 274 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 275 if (IS_ERR(p->hpd_gpio)) { 276 err = PTR_ERR(p->hpd_gpio); 277 278 /* 279 * If we're called from probe we won't consider '-EPROBE_DEFER' 280 * to be an error--we'll leave the error code in "hpd_gpio". 281 * When we try to use it we'll try again. This allows for 282 * circular dependencies where the component providing the 283 * hpd gpio needs the panel to init before probing. 284 */ 285 if (err != -EPROBE_DEFER || !from_probe) { 286 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 287 return err; 288 } 289 } 290 291 return 0; 292 } 293 294 static int panel_simple_prepare(struct drm_panel *panel) 295 { 296 struct panel_simple *p = to_panel_simple(panel); 297 unsigned int delay; 298 int err; 299 int hpd_asserted; 300 301 if (p->prepared) 302 return 0; 303 304 err = regulator_enable(p->supply); 305 if (err < 0) { 306 dev_err(panel->dev, "failed to enable supply: %d\n", err); 307 return err; 308 } 309 310 gpiod_set_value_cansleep(p->enable_gpio, 1); 311 312 delay = p->desc->delay.prepare; 313 if (p->no_hpd) 314 delay += p->desc->delay.hpd_absent_delay; 315 if (delay) 316 msleep(delay); 317 318 if (p->hpd_gpio) { 319 if (IS_ERR(p->hpd_gpio)) { 320 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 321 if (err) 322 return err; 323 } 324 325 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 326 hpd_asserted, hpd_asserted, 327 1000, 2000000); 328 if (hpd_asserted < 0) 329 err = hpd_asserted; 330 331 if (err) { 332 dev_err(panel->dev, 333 "error waiting for hpd GPIO: %d\n", err); 334 return err; 335 } 336 } 337 338 p->prepared = true; 339 340 return 0; 341 } 342 343 static int panel_simple_enable(struct drm_panel *panel) 344 { 345 struct panel_simple *p = to_panel_simple(panel); 346 347 if (p->enabled) 348 return 0; 349 350 if (p->desc->delay.enable) 351 msleep(p->desc->delay.enable); 352 353 p->enabled = true; 354 355 return 0; 356 } 357 358 static int panel_simple_get_modes(struct drm_panel *panel, 359 struct drm_connector *connector) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int num = 0; 363 364 /* probe EDID if a DDC bus is available */ 365 if (p->ddc) { 366 struct edid *edid = drm_get_edid(connector, p->ddc); 367 368 drm_connector_update_edid_property(connector, edid); 369 if (edid) { 370 num += drm_add_edid_modes(connector, edid); 371 kfree(edid); 372 } 373 } 374 375 /* add hard-coded panel modes */ 376 num += panel_simple_get_non_edid_modes(p, connector); 377 378 /* set up connector's "panel orientation" property */ 379 drm_connector_set_panel_orientation(connector, p->orientation); 380 381 return num; 382 } 383 384 static int panel_simple_get_timings(struct drm_panel *panel, 385 unsigned int num_timings, 386 struct display_timing *timings) 387 { 388 struct panel_simple *p = to_panel_simple(panel); 389 unsigned int i; 390 391 if (p->desc->num_timings < num_timings) 392 num_timings = p->desc->num_timings; 393 394 if (timings) 395 for (i = 0; i < num_timings; i++) 396 timings[i] = p->desc->timings[i]; 397 398 return p->desc->num_timings; 399 } 400 401 static const struct drm_panel_funcs panel_simple_funcs = { 402 .disable = panel_simple_disable, 403 .unprepare = panel_simple_unprepare, 404 .prepare = panel_simple_prepare, 405 .enable = panel_simple_enable, 406 .get_modes = panel_simple_get_modes, 407 .get_timings = panel_simple_get_timings, 408 }; 409 410 static struct panel_desc panel_dpi; 411 412 static int panel_dpi_probe(struct device *dev, 413 struct panel_simple *panel) 414 { 415 struct display_timing *timing; 416 const struct device_node *np; 417 struct panel_desc *desc; 418 unsigned int bus_flags; 419 struct videomode vm; 420 int ret; 421 422 np = dev->of_node; 423 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 424 if (!desc) 425 return -ENOMEM; 426 427 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 428 if (!timing) 429 return -ENOMEM; 430 431 ret = of_get_display_timing(np, "panel-timing", timing); 432 if (ret < 0) { 433 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 434 np); 435 return ret; 436 } 437 438 desc->timings = timing; 439 desc->num_timings = 1; 440 441 of_property_read_u32(np, "width-mm", &desc->size.width); 442 of_property_read_u32(np, "height-mm", &desc->size.height); 443 444 /* Extract bus_flags from display_timing */ 445 bus_flags = 0; 446 vm.flags = timing->flags; 447 drm_bus_flags_from_videomode(&vm, &bus_flags); 448 desc->bus_flags = bus_flags; 449 450 /* We do not know the connector for the DT node, so guess it */ 451 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 452 453 panel->desc = desc; 454 455 return 0; 456 } 457 458 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 459 (to_check->field.typ >= bounds->field.min && \ 460 to_check->field.typ <= bounds->field.max) 461 static void panel_simple_parse_panel_timing_node(struct device *dev, 462 struct panel_simple *panel, 463 const struct display_timing *ot) 464 { 465 const struct panel_desc *desc = panel->desc; 466 struct videomode vm; 467 unsigned int i; 468 469 if (WARN_ON(desc->num_modes)) { 470 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 471 return; 472 } 473 if (WARN_ON(!desc->num_timings)) { 474 dev_err(dev, "Reject override mode: no timings specified\n"); 475 return; 476 } 477 478 for (i = 0; i < panel->desc->num_timings; i++) { 479 const struct display_timing *dt = &panel->desc->timings[i]; 480 481 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 487 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 488 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 489 continue; 490 491 if (ot->flags != dt->flags) 492 continue; 493 494 videomode_from_timing(ot, &vm); 495 drm_display_mode_from_videomode(&vm, &panel->override_mode); 496 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 497 DRM_MODE_TYPE_PREFERRED; 498 break; 499 } 500 501 if (WARN_ON(!panel->override_mode.type)) 502 dev_err(dev, "Reject override mode: No display_timing found\n"); 503 } 504 505 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 506 { 507 struct panel_simple *panel; 508 struct display_timing dt; 509 struct device_node *ddc; 510 int connector_type; 511 u32 bus_flags; 512 int err; 513 514 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 515 if (!panel) 516 return -ENOMEM; 517 518 panel->enabled = false; 519 panel->prepared = false; 520 panel->desc = desc; 521 522 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 523 if (!panel->no_hpd) { 524 err = panel_simple_get_hpd_gpio(dev, panel, true); 525 if (err) 526 return err; 527 } 528 529 panel->supply = devm_regulator_get(dev, "power"); 530 if (IS_ERR(panel->supply)) 531 return PTR_ERR(panel->supply); 532 533 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 534 GPIOD_OUT_LOW); 535 if (IS_ERR(panel->enable_gpio)) { 536 err = PTR_ERR(panel->enable_gpio); 537 if (err != -EPROBE_DEFER) 538 dev_err(dev, "failed to request GPIO: %d\n", err); 539 return err; 540 } 541 542 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 543 if (err) { 544 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 545 return err; 546 } 547 548 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 549 if (ddc) { 550 panel->ddc = of_find_i2c_adapter_by_node(ddc); 551 of_node_put(ddc); 552 553 if (!panel->ddc) 554 return -EPROBE_DEFER; 555 } 556 557 if (desc == &panel_dpi) { 558 /* Handle the generic panel-dpi binding */ 559 err = panel_dpi_probe(dev, panel); 560 if (err) 561 goto free_ddc; 562 } else { 563 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 564 panel_simple_parse_panel_timing_node(dev, panel, &dt); 565 } 566 567 connector_type = desc->connector_type; 568 /* Catch common mistakes for panels. */ 569 switch (connector_type) { 570 case 0: 571 dev_warn(dev, "Specify missing connector_type\n"); 572 connector_type = DRM_MODE_CONNECTOR_DPI; 573 break; 574 case DRM_MODE_CONNECTOR_LVDS: 575 WARN_ON(desc->bus_flags & 576 ~(DRM_BUS_FLAG_DE_LOW | 577 DRM_BUS_FLAG_DE_HIGH | 578 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 579 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 580 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 582 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 583 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 584 desc->bpc != 6); 585 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 586 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 587 desc->bpc != 8); 588 break; 589 case DRM_MODE_CONNECTOR_eDP: 590 if (desc->bus_format == 0) 591 dev_warn(dev, "Specify missing bus_format\n"); 592 if (desc->bpc != 6 && desc->bpc != 8) 593 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 594 break; 595 case DRM_MODE_CONNECTOR_DSI: 596 if (desc->bpc != 6 && desc->bpc != 8) 597 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 598 break; 599 case DRM_MODE_CONNECTOR_DPI: 600 bus_flags = DRM_BUS_FLAG_DE_LOW | 601 DRM_BUS_FLAG_DE_HIGH | 602 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 603 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 604 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 605 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 606 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 607 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 608 if (desc->bus_flags & ~bus_flags) 609 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 610 if (!(desc->bus_flags & bus_flags)) 611 dev_warn(dev, "Specify missing bus_flags\n"); 612 if (desc->bus_format == 0) 613 dev_warn(dev, "Specify missing bus_format\n"); 614 if (desc->bpc != 6 && desc->bpc != 8) 615 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 616 break; 617 default: 618 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 619 connector_type = DRM_MODE_CONNECTOR_DPI; 620 break; 621 } 622 623 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 624 625 err = drm_panel_of_backlight(&panel->base); 626 if (err) 627 goto free_ddc; 628 629 drm_panel_add(&panel->base); 630 631 dev_set_drvdata(dev, panel); 632 633 return 0; 634 635 free_ddc: 636 if (panel->ddc) 637 put_device(&panel->ddc->dev); 638 639 return err; 640 } 641 642 static int panel_simple_remove(struct device *dev) 643 { 644 struct panel_simple *panel = dev_get_drvdata(dev); 645 646 drm_panel_remove(&panel->base); 647 drm_panel_disable(&panel->base); 648 drm_panel_unprepare(&panel->base); 649 650 if (panel->ddc) 651 put_device(&panel->ddc->dev); 652 653 return 0; 654 } 655 656 static void panel_simple_shutdown(struct device *dev) 657 { 658 struct panel_simple *panel = dev_get_drvdata(dev); 659 660 drm_panel_disable(&panel->base); 661 drm_panel_unprepare(&panel->base); 662 } 663 664 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 665 .clock = 71100, 666 .hdisplay = 1280, 667 .hsync_start = 1280 + 40, 668 .hsync_end = 1280 + 40 + 80, 669 .htotal = 1280 + 40 + 80 + 40, 670 .vdisplay = 800, 671 .vsync_start = 800 + 3, 672 .vsync_end = 800 + 3 + 10, 673 .vtotal = 800 + 3 + 10 + 10, 674 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 675 }; 676 677 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 678 .modes = &ire_am_1280800n3tzqw_t00h_mode, 679 .num_modes = 1, 680 .bpc = 6, 681 .size = { 682 .width = 217, 683 .height = 136, 684 }, 685 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 687 .connector_type = DRM_MODE_CONNECTOR_LVDS, 688 }; 689 690 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 691 .clock = 9000, 692 .hdisplay = 480, 693 .hsync_start = 480 + 2, 694 .hsync_end = 480 + 2 + 41, 695 .htotal = 480 + 2 + 41 + 2, 696 .vdisplay = 272, 697 .vsync_start = 272 + 2, 698 .vsync_end = 272 + 2 + 10, 699 .vtotal = 272 + 2 + 10 + 2, 700 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 701 }; 702 703 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 704 .modes = &ire_am_480272h3tmqw_t01h_mode, 705 .num_modes = 1, 706 .bpc = 8, 707 .size = { 708 .width = 105, 709 .height = 67, 710 }, 711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 712 }; 713 714 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 715 .clock = 33333, 716 .hdisplay = 800, 717 .hsync_start = 800 + 0, 718 .hsync_end = 800 + 0 + 255, 719 .htotal = 800 + 0 + 255 + 0, 720 .vdisplay = 480, 721 .vsync_start = 480 + 2, 722 .vsync_end = 480 + 2 + 45, 723 .vtotal = 480 + 2 + 45 + 0, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am800480r3tmqwa1h = { 728 .modes = &ire_am800480r3tmqwa1h_mode, 729 .num_modes = 1, 730 .bpc = 6, 731 .size = { 732 .width = 152, 733 .height = 91, 734 }, 735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 736 }; 737 738 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 739 .pixelclock = { 26400000, 33300000, 46800000 }, 740 .hactive = { 800, 800, 800 }, 741 .hfront_porch = { 16, 210, 354 }, 742 .hback_porch = { 45, 36, 6 }, 743 .hsync_len = { 1, 10, 40 }, 744 .vactive = { 480, 480, 480 }, 745 .vfront_porch = { 7, 22, 147 }, 746 .vback_porch = { 22, 13, 3 }, 747 .vsync_len = { 1, 10, 20 }, 748 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 749 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 750 }; 751 752 static const struct panel_desc armadeus_st0700_adapt = { 753 .timings = &santek_st0700i5y_rbslw_f_timing, 754 .num_timings = 1, 755 .bpc = 6, 756 .size = { 757 .width = 154, 758 .height = 86, 759 }, 760 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 761 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 762 }; 763 764 static const struct drm_display_mode auo_b101aw03_mode = { 765 .clock = 51450, 766 .hdisplay = 1024, 767 .hsync_start = 1024 + 156, 768 .hsync_end = 1024 + 156 + 8, 769 .htotal = 1024 + 156 + 8 + 156, 770 .vdisplay = 600, 771 .vsync_start = 600 + 16, 772 .vsync_end = 600 + 16 + 6, 773 .vtotal = 600 + 16 + 6 + 16, 774 }; 775 776 static const struct panel_desc auo_b101aw03 = { 777 .modes = &auo_b101aw03_mode, 778 .num_modes = 1, 779 .bpc = 6, 780 .size = { 781 .width = 223, 782 .height = 125, 783 }, 784 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 785 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 787 }; 788 789 static const struct display_timing auo_b101ean01_timing = { 790 .pixelclock = { 65300000, 72500000, 75000000 }, 791 .hactive = { 1280, 1280, 1280 }, 792 .hfront_porch = { 18, 119, 119 }, 793 .hback_porch = { 21, 21, 21 }, 794 .hsync_len = { 32, 32, 32 }, 795 .vactive = { 800, 800, 800 }, 796 .vfront_porch = { 4, 4, 4 }, 797 .vback_porch = { 8, 8, 8 }, 798 .vsync_len = { 18, 20, 20 }, 799 }; 800 801 static const struct panel_desc auo_b101ean01 = { 802 .timings = &auo_b101ean01_timing, 803 .num_timings = 1, 804 .bpc = 6, 805 .size = { 806 .width = 217, 807 .height = 136, 808 }, 809 }; 810 811 static const struct drm_display_mode auo_b101xtn01_mode = { 812 .clock = 72000, 813 .hdisplay = 1366, 814 .hsync_start = 1366 + 20, 815 .hsync_end = 1366 + 20 + 70, 816 .htotal = 1366 + 20 + 70, 817 .vdisplay = 768, 818 .vsync_start = 768 + 14, 819 .vsync_end = 768 + 14 + 42, 820 .vtotal = 768 + 14 + 42, 821 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 822 }; 823 824 static const struct panel_desc auo_b101xtn01 = { 825 .modes = &auo_b101xtn01_mode, 826 .num_modes = 1, 827 .bpc = 6, 828 .size = { 829 .width = 223, 830 .height = 125, 831 }, 832 }; 833 834 static const struct drm_display_mode auo_b116xak01_mode = { 835 .clock = 69300, 836 .hdisplay = 1366, 837 .hsync_start = 1366 + 48, 838 .hsync_end = 1366 + 48 + 32, 839 .htotal = 1366 + 48 + 32 + 10, 840 .vdisplay = 768, 841 .vsync_start = 768 + 4, 842 .vsync_end = 768 + 4 + 6, 843 .vtotal = 768 + 4 + 6 + 15, 844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 845 }; 846 847 static const struct panel_desc auo_b116xak01 = { 848 .modes = &auo_b116xak01_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 256, 853 .height = 144, 854 }, 855 .delay = { 856 .hpd_absent_delay = 200, 857 }, 858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 859 .connector_type = DRM_MODE_CONNECTOR_eDP, 860 }; 861 862 static const struct drm_display_mode auo_b116xw03_mode = { 863 .clock = 70589, 864 .hdisplay = 1366, 865 .hsync_start = 1366 + 40, 866 .hsync_end = 1366 + 40 + 40, 867 .htotal = 1366 + 40 + 40 + 32, 868 .vdisplay = 768, 869 .vsync_start = 768 + 10, 870 .vsync_end = 768 + 10 + 12, 871 .vtotal = 768 + 10 + 12 + 6, 872 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 873 }; 874 875 static const struct panel_desc auo_b116xw03 = { 876 .modes = &auo_b116xw03_mode, 877 .num_modes = 1, 878 .bpc = 6, 879 .size = { 880 .width = 256, 881 .height = 144, 882 }, 883 .delay = { 884 .enable = 400, 885 }, 886 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 888 .connector_type = DRM_MODE_CONNECTOR_eDP, 889 }; 890 891 static const struct drm_display_mode auo_b133xtn01_mode = { 892 .clock = 69500, 893 .hdisplay = 1366, 894 .hsync_start = 1366 + 48, 895 .hsync_end = 1366 + 48 + 32, 896 .htotal = 1366 + 48 + 32 + 20, 897 .vdisplay = 768, 898 .vsync_start = 768 + 3, 899 .vsync_end = 768 + 3 + 6, 900 .vtotal = 768 + 3 + 6 + 13, 901 }; 902 903 static const struct panel_desc auo_b133xtn01 = { 904 .modes = &auo_b133xtn01_mode, 905 .num_modes = 1, 906 .bpc = 6, 907 .size = { 908 .width = 293, 909 .height = 165, 910 }, 911 }; 912 913 static const struct drm_display_mode auo_b133htn01_mode = { 914 .clock = 150660, 915 .hdisplay = 1920, 916 .hsync_start = 1920 + 172, 917 .hsync_end = 1920 + 172 + 80, 918 .htotal = 1920 + 172 + 80 + 60, 919 .vdisplay = 1080, 920 .vsync_start = 1080 + 25, 921 .vsync_end = 1080 + 25 + 10, 922 .vtotal = 1080 + 25 + 10 + 10, 923 }; 924 925 static const struct panel_desc auo_b133htn01 = { 926 .modes = &auo_b133htn01_mode, 927 .num_modes = 1, 928 .bpc = 6, 929 .size = { 930 .width = 293, 931 .height = 165, 932 }, 933 .delay = { 934 .prepare = 105, 935 .enable = 20, 936 .unprepare = 50, 937 }, 938 }; 939 940 static const struct display_timing auo_g070vvn01_timings = { 941 .pixelclock = { 33300000, 34209000, 45000000 }, 942 .hactive = { 800, 800, 800 }, 943 .hfront_porch = { 20, 40, 200 }, 944 .hback_porch = { 87, 40, 1 }, 945 .hsync_len = { 1, 48, 87 }, 946 .vactive = { 480, 480, 480 }, 947 .vfront_porch = { 5, 13, 200 }, 948 .vback_porch = { 31, 31, 29 }, 949 .vsync_len = { 1, 1, 3 }, 950 }; 951 952 static const struct panel_desc auo_g070vvn01 = { 953 .timings = &auo_g070vvn01_timings, 954 .num_timings = 1, 955 .bpc = 8, 956 .size = { 957 .width = 152, 958 .height = 91, 959 }, 960 .delay = { 961 .prepare = 200, 962 .enable = 50, 963 .disable = 50, 964 .unprepare = 1000, 965 }, 966 }; 967 968 static const struct drm_display_mode auo_g101evn010_mode = { 969 .clock = 68930, 970 .hdisplay = 1280, 971 .hsync_start = 1280 + 82, 972 .hsync_end = 1280 + 82 + 2, 973 .htotal = 1280 + 82 + 2 + 84, 974 .vdisplay = 800, 975 .vsync_start = 800 + 8, 976 .vsync_end = 800 + 8 + 2, 977 .vtotal = 800 + 8 + 2 + 6, 978 }; 979 980 static const struct panel_desc auo_g101evn010 = { 981 .modes = &auo_g101evn010_mode, 982 .num_modes = 1, 983 .bpc = 6, 984 .size = { 985 .width = 216, 986 .height = 135, 987 }, 988 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 989 .connector_type = DRM_MODE_CONNECTOR_LVDS, 990 }; 991 992 static const struct drm_display_mode auo_g104sn02_mode = { 993 .clock = 40000, 994 .hdisplay = 800, 995 .hsync_start = 800 + 40, 996 .hsync_end = 800 + 40 + 216, 997 .htotal = 800 + 40 + 216 + 128, 998 .vdisplay = 600, 999 .vsync_start = 600 + 10, 1000 .vsync_end = 600 + 10 + 35, 1001 .vtotal = 600 + 10 + 35 + 2, 1002 }; 1003 1004 static const struct panel_desc auo_g104sn02 = { 1005 .modes = &auo_g104sn02_mode, 1006 .num_modes = 1, 1007 .bpc = 8, 1008 .size = { 1009 .width = 211, 1010 .height = 158, 1011 }, 1012 }; 1013 1014 static const struct drm_display_mode auo_g121ean01_mode = { 1015 .clock = 66700, 1016 .hdisplay = 1280, 1017 .hsync_start = 1280 + 58, 1018 .hsync_end = 1280 + 58 + 8, 1019 .htotal = 1280 + 58 + 8 + 70, 1020 .vdisplay = 800, 1021 .vsync_start = 800 + 6, 1022 .vsync_end = 800 + 6 + 4, 1023 .vtotal = 800 + 6 + 4 + 10, 1024 }; 1025 1026 static const struct panel_desc auo_g121ean01 = { 1027 .modes = &auo_g121ean01_mode, 1028 .num_modes = 1, 1029 .bpc = 8, 1030 .size = { 1031 .width = 261, 1032 .height = 163, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g133han01_timings = { 1039 .pixelclock = { 134000000, 141200000, 149000000 }, 1040 .hactive = { 1920, 1920, 1920 }, 1041 .hfront_porch = { 39, 58, 77 }, 1042 .hback_porch = { 59, 88, 117 }, 1043 .hsync_len = { 28, 42, 56 }, 1044 .vactive = { 1080, 1080, 1080 }, 1045 .vfront_porch = { 3, 8, 11 }, 1046 .vback_porch = { 5, 14, 19 }, 1047 .vsync_len = { 4, 14, 19 }, 1048 }; 1049 1050 static const struct panel_desc auo_g133han01 = { 1051 .timings = &auo_g133han01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 293, 1056 .height = 165, 1057 }, 1058 .delay = { 1059 .prepare = 200, 1060 .enable = 50, 1061 .disable = 50, 1062 .unprepare = 1000, 1063 }, 1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1066 }; 1067 1068 static const struct drm_display_mode auo_g156xtn01_mode = { 1069 .clock = 76000, 1070 .hdisplay = 1366, 1071 .hsync_start = 1366 + 33, 1072 .hsync_end = 1366 + 33 + 67, 1073 .htotal = 1560, 1074 .vdisplay = 768, 1075 .vsync_start = 768 + 4, 1076 .vsync_end = 768 + 4 + 4, 1077 .vtotal = 806, 1078 }; 1079 1080 static const struct panel_desc auo_g156xtn01 = { 1081 .modes = &auo_g156xtn01_mode, 1082 .num_modes = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 344, 1086 .height = 194, 1087 }, 1088 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1089 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1090 }; 1091 1092 static const struct display_timing auo_g185han01_timings = { 1093 .pixelclock = { 120000000, 144000000, 175000000 }, 1094 .hactive = { 1920, 1920, 1920 }, 1095 .hfront_porch = { 36, 120, 148 }, 1096 .hback_porch = { 24, 88, 108 }, 1097 .hsync_len = { 20, 48, 64 }, 1098 .vactive = { 1080, 1080, 1080 }, 1099 .vfront_porch = { 6, 10, 40 }, 1100 .vback_porch = { 2, 5, 20 }, 1101 .vsync_len = { 2, 5, 20 }, 1102 }; 1103 1104 static const struct panel_desc auo_g185han01 = { 1105 .timings = &auo_g185han01_timings, 1106 .num_timings = 1, 1107 .bpc = 8, 1108 .size = { 1109 .width = 409, 1110 .height = 230, 1111 }, 1112 .delay = { 1113 .prepare = 50, 1114 .enable = 200, 1115 .disable = 110, 1116 .unprepare = 1000, 1117 }, 1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1119 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1120 }; 1121 1122 static const struct display_timing auo_g190ean01_timings = { 1123 .pixelclock = { 90000000, 108000000, 135000000 }, 1124 .hactive = { 1280, 1280, 1280 }, 1125 .hfront_porch = { 126, 184, 1266 }, 1126 .hback_porch = { 84, 122, 844 }, 1127 .hsync_len = { 70, 102, 704 }, 1128 .vactive = { 1024, 1024, 1024 }, 1129 .vfront_porch = { 4, 26, 76 }, 1130 .vback_porch = { 2, 8, 25 }, 1131 .vsync_len = { 2, 8, 25 }, 1132 }; 1133 1134 static const struct panel_desc auo_g190ean01 = { 1135 .timings = &auo_g190ean01_timings, 1136 .num_timings = 1, 1137 .bpc = 8, 1138 .size = { 1139 .width = 376, 1140 .height = 301, 1141 }, 1142 .delay = { 1143 .prepare = 50, 1144 .enable = 200, 1145 .disable = 110, 1146 .unprepare = 1000, 1147 }, 1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1149 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1150 }; 1151 1152 static const struct display_timing auo_p320hvn03_timings = { 1153 .pixelclock = { 106000000, 148500000, 164000000 }, 1154 .hactive = { 1920, 1920, 1920 }, 1155 .hfront_porch = { 25, 50, 130 }, 1156 .hback_porch = { 25, 50, 130 }, 1157 .hsync_len = { 20, 40, 105 }, 1158 .vactive = { 1080, 1080, 1080 }, 1159 .vfront_porch = { 8, 17, 150 }, 1160 .vback_porch = { 8, 17, 150 }, 1161 .vsync_len = { 4, 11, 100 }, 1162 }; 1163 1164 static const struct panel_desc auo_p320hvn03 = { 1165 .timings = &auo_p320hvn03_timings, 1166 .num_timings = 1, 1167 .bpc = 8, 1168 .size = { 1169 .width = 698, 1170 .height = 393, 1171 }, 1172 .delay = { 1173 .prepare = 1, 1174 .enable = 450, 1175 .unprepare = 500, 1176 }, 1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1178 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1179 }; 1180 1181 static const struct drm_display_mode auo_t215hvn01_mode = { 1182 .clock = 148800, 1183 .hdisplay = 1920, 1184 .hsync_start = 1920 + 88, 1185 .hsync_end = 1920 + 88 + 44, 1186 .htotal = 1920 + 88 + 44 + 148, 1187 .vdisplay = 1080, 1188 .vsync_start = 1080 + 4, 1189 .vsync_end = 1080 + 4 + 5, 1190 .vtotal = 1080 + 4 + 5 + 36, 1191 }; 1192 1193 static const struct panel_desc auo_t215hvn01 = { 1194 .modes = &auo_t215hvn01_mode, 1195 .num_modes = 1, 1196 .bpc = 8, 1197 .size = { 1198 .width = 430, 1199 .height = 270, 1200 }, 1201 .delay = { 1202 .disable = 5, 1203 .unprepare = 1000, 1204 } 1205 }; 1206 1207 static const struct drm_display_mode avic_tm070ddh03_mode = { 1208 .clock = 51200, 1209 .hdisplay = 1024, 1210 .hsync_start = 1024 + 160, 1211 .hsync_end = 1024 + 160 + 4, 1212 .htotal = 1024 + 160 + 4 + 156, 1213 .vdisplay = 600, 1214 .vsync_start = 600 + 17, 1215 .vsync_end = 600 + 17 + 1, 1216 .vtotal = 600 + 17 + 1 + 17, 1217 }; 1218 1219 static const struct panel_desc avic_tm070ddh03 = { 1220 .modes = &avic_tm070ddh03_mode, 1221 .num_modes = 1, 1222 .bpc = 8, 1223 .size = { 1224 .width = 154, 1225 .height = 90, 1226 }, 1227 .delay = { 1228 .prepare = 20, 1229 .enable = 200, 1230 .disable = 200, 1231 }, 1232 }; 1233 1234 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1235 .clock = 30000, 1236 .hdisplay = 800, 1237 .hsync_start = 800 + 40, 1238 .hsync_end = 800 + 40 + 48, 1239 .htotal = 800 + 40 + 48 + 40, 1240 .vdisplay = 480, 1241 .vsync_start = 480 + 13, 1242 .vsync_end = 480 + 13 + 3, 1243 .vtotal = 480 + 13 + 3 + 29, 1244 }; 1245 1246 static const struct panel_desc bananapi_s070wv20_ct16 = { 1247 .modes = &bananapi_s070wv20_ct16_mode, 1248 .num_modes = 1, 1249 .bpc = 6, 1250 .size = { 1251 .width = 154, 1252 .height = 86, 1253 }, 1254 }; 1255 1256 static const struct drm_display_mode boe_hv070wsa_mode = { 1257 .clock = 42105, 1258 .hdisplay = 1024, 1259 .hsync_start = 1024 + 30, 1260 .hsync_end = 1024 + 30 + 30, 1261 .htotal = 1024 + 30 + 30 + 30, 1262 .vdisplay = 600, 1263 .vsync_start = 600 + 10, 1264 .vsync_end = 600 + 10 + 10, 1265 .vtotal = 600 + 10 + 10 + 10, 1266 }; 1267 1268 static const struct panel_desc boe_hv070wsa = { 1269 .modes = &boe_hv070wsa_mode, 1270 .num_modes = 1, 1271 .bpc = 8, 1272 .size = { 1273 .width = 154, 1274 .height = 90, 1275 }, 1276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1277 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1279 }; 1280 1281 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1282 { 1283 .clock = 71900, 1284 .hdisplay = 1280, 1285 .hsync_start = 1280 + 48, 1286 .hsync_end = 1280 + 48 + 32, 1287 .htotal = 1280 + 48 + 32 + 80, 1288 .vdisplay = 800, 1289 .vsync_start = 800 + 3, 1290 .vsync_end = 800 + 3 + 5, 1291 .vtotal = 800 + 3 + 5 + 24, 1292 }, 1293 { 1294 .clock = 57500, 1295 .hdisplay = 1280, 1296 .hsync_start = 1280 + 48, 1297 .hsync_end = 1280 + 48 + 32, 1298 .htotal = 1280 + 48 + 32 + 80, 1299 .vdisplay = 800, 1300 .vsync_start = 800 + 3, 1301 .vsync_end = 800 + 3 + 5, 1302 .vtotal = 800 + 3 + 5 + 24, 1303 }, 1304 }; 1305 1306 static const struct panel_desc boe_nv101wxmn51 = { 1307 .modes = boe_nv101wxmn51_modes, 1308 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1309 .bpc = 8, 1310 .size = { 1311 .width = 217, 1312 .height = 136, 1313 }, 1314 .delay = { 1315 .prepare = 210, 1316 .enable = 50, 1317 .unprepare = 160, 1318 }, 1319 }; 1320 1321 /* Also used for boe_nv133fhm_n62 */ 1322 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1323 .clock = 147840, 1324 .hdisplay = 1920, 1325 .hsync_start = 1920 + 48, 1326 .hsync_end = 1920 + 48 + 32, 1327 .htotal = 1920 + 48 + 32 + 200, 1328 .vdisplay = 1080, 1329 .vsync_start = 1080 + 3, 1330 .vsync_end = 1080 + 3 + 6, 1331 .vtotal = 1080 + 3 + 6 + 31, 1332 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1333 }; 1334 1335 /* Also used for boe_nv133fhm_n62 */ 1336 static const struct panel_desc boe_nv133fhm_n61 = { 1337 .modes = &boe_nv133fhm_n61_modes, 1338 .num_modes = 1, 1339 .bpc = 6, 1340 .size = { 1341 .width = 294, 1342 .height = 165, 1343 }, 1344 .delay = { 1345 /* 1346 * When power is first given to the panel there's a short 1347 * spike on the HPD line. It was explained that this spike 1348 * was until the TCON data download was complete. On 1349 * one system this was measured at 8 ms. We'll put 15 ms 1350 * in the prepare delay just to be safe and take it away 1351 * from the hpd_absent_delay (which would otherwise be 200 ms) 1352 * to handle this. That means: 1353 * - If HPD isn't hooked up you still have 200 ms delay. 1354 * - If HPD is hooked up we won't try to look at it for the 1355 * first 15 ms. 1356 */ 1357 .prepare = 15, 1358 .hpd_absent_delay = 185, 1359 1360 .unprepare = 500, 1361 }, 1362 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1363 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1364 .connector_type = DRM_MODE_CONNECTOR_eDP, 1365 }; 1366 1367 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1368 { 1369 .clock = 148500, 1370 .hdisplay = 1920, 1371 .hsync_start = 1920 + 48, 1372 .hsync_end = 1920 + 48 + 32, 1373 .htotal = 2200, 1374 .vdisplay = 1080, 1375 .vsync_start = 1080 + 3, 1376 .vsync_end = 1080 + 3 + 5, 1377 .vtotal = 1125, 1378 }, 1379 }; 1380 1381 static const struct panel_desc boe_nv140fhmn49 = { 1382 .modes = boe_nv140fhmn49_modes, 1383 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1384 .bpc = 6, 1385 .size = { 1386 .width = 309, 1387 .height = 174, 1388 }, 1389 .delay = { 1390 .prepare = 210, 1391 .enable = 50, 1392 .unprepare = 160, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1395 .connector_type = DRM_MODE_CONNECTOR_eDP, 1396 }; 1397 1398 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1399 .clock = 9000, 1400 .hdisplay = 480, 1401 .hsync_start = 480 + 5, 1402 .hsync_end = 480 + 5 + 5, 1403 .htotal = 480 + 5 + 5 + 40, 1404 .vdisplay = 272, 1405 .vsync_start = 272 + 8, 1406 .vsync_end = 272 + 8 + 8, 1407 .vtotal = 272 + 8 + 8 + 8, 1408 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1409 }; 1410 1411 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1412 .modes = &cdtech_s043wq26h_ct7_mode, 1413 .num_modes = 1, 1414 .bpc = 8, 1415 .size = { 1416 .width = 95, 1417 .height = 54, 1418 }, 1419 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1420 }; 1421 1422 /* S070PWS19HP-FC21 2017/04/22 */ 1423 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1424 .clock = 51200, 1425 .hdisplay = 1024, 1426 .hsync_start = 1024 + 160, 1427 .hsync_end = 1024 + 160 + 20, 1428 .htotal = 1024 + 160 + 20 + 140, 1429 .vdisplay = 600, 1430 .vsync_start = 600 + 12, 1431 .vsync_end = 600 + 12 + 3, 1432 .vtotal = 600 + 12 + 3 + 20, 1433 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1434 }; 1435 1436 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1437 .modes = &cdtech_s070pws19hp_fc21_mode, 1438 .num_modes = 1, 1439 .bpc = 6, 1440 .size = { 1441 .width = 154, 1442 .height = 86, 1443 }, 1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1446 .connector_type = DRM_MODE_CONNECTOR_DPI, 1447 }; 1448 1449 /* S070SWV29HG-DC44 2017/09/21 */ 1450 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1451 .clock = 33300, 1452 .hdisplay = 800, 1453 .hsync_start = 800 + 210, 1454 .hsync_end = 800 + 210 + 2, 1455 .htotal = 800 + 210 + 2 + 44, 1456 .vdisplay = 480, 1457 .vsync_start = 480 + 22, 1458 .vsync_end = 480 + 22 + 2, 1459 .vtotal = 480 + 22 + 2 + 21, 1460 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1461 }; 1462 1463 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1464 .modes = &cdtech_s070swv29hg_dc44_mode, 1465 .num_modes = 1, 1466 .bpc = 6, 1467 .size = { 1468 .width = 154, 1469 .height = 86, 1470 }, 1471 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1473 .connector_type = DRM_MODE_CONNECTOR_DPI, 1474 }; 1475 1476 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1477 .clock = 35000, 1478 .hdisplay = 800, 1479 .hsync_start = 800 + 40, 1480 .hsync_end = 800 + 40 + 40, 1481 .htotal = 800 + 40 + 40 + 48, 1482 .vdisplay = 480, 1483 .vsync_start = 480 + 29, 1484 .vsync_end = 480 + 29 + 13, 1485 .vtotal = 480 + 29 + 13 + 3, 1486 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1487 }; 1488 1489 static const struct panel_desc cdtech_s070wv95_ct16 = { 1490 .modes = &cdtech_s070wv95_ct16_mode, 1491 .num_modes = 1, 1492 .bpc = 8, 1493 .size = { 1494 .width = 154, 1495 .height = 85, 1496 }, 1497 }; 1498 1499 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1500 .pixelclock = { 68900000, 71100000, 73400000 }, 1501 .hactive = { 1280, 1280, 1280 }, 1502 .hfront_porch = { 65, 80, 95 }, 1503 .hback_porch = { 64, 79, 94 }, 1504 .hsync_len = { 1, 1, 1 }, 1505 .vactive = { 800, 800, 800 }, 1506 .vfront_porch = { 7, 11, 14 }, 1507 .vback_porch = { 7, 11, 14 }, 1508 .vsync_len = { 1, 1, 1 }, 1509 .flags = DISPLAY_FLAGS_DE_HIGH, 1510 }; 1511 1512 static const struct panel_desc chefree_ch101olhlwh_002 = { 1513 .timings = &chefree_ch101olhlwh_002_timing, 1514 .num_timings = 1, 1515 .bpc = 8, 1516 .size = { 1517 .width = 217, 1518 .height = 135, 1519 }, 1520 .delay = { 1521 .enable = 200, 1522 .disable = 200, 1523 }, 1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1526 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1527 }; 1528 1529 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1530 .clock = 66770, 1531 .hdisplay = 800, 1532 .hsync_start = 800 + 49, 1533 .hsync_end = 800 + 49 + 33, 1534 .htotal = 800 + 49 + 33 + 17, 1535 .vdisplay = 1280, 1536 .vsync_start = 1280 + 1, 1537 .vsync_end = 1280 + 1 + 7, 1538 .vtotal = 1280 + 1 + 7 + 15, 1539 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1540 }; 1541 1542 static const struct panel_desc chunghwa_claa070wp03xg = { 1543 .modes = &chunghwa_claa070wp03xg_mode, 1544 .num_modes = 1, 1545 .bpc = 6, 1546 .size = { 1547 .width = 94, 1548 .height = 150, 1549 }, 1550 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1551 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1552 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1553 }; 1554 1555 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1556 .clock = 72070, 1557 .hdisplay = 1366, 1558 .hsync_start = 1366 + 58, 1559 .hsync_end = 1366 + 58 + 58, 1560 .htotal = 1366 + 58 + 58 + 58, 1561 .vdisplay = 768, 1562 .vsync_start = 768 + 4, 1563 .vsync_end = 768 + 4 + 4, 1564 .vtotal = 768 + 4 + 4 + 4, 1565 }; 1566 1567 static const struct panel_desc chunghwa_claa101wa01a = { 1568 .modes = &chunghwa_claa101wa01a_mode, 1569 .num_modes = 1, 1570 .bpc = 6, 1571 .size = { 1572 .width = 220, 1573 .height = 120, 1574 }, 1575 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1576 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1577 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1578 }; 1579 1580 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1581 .clock = 69300, 1582 .hdisplay = 1366, 1583 .hsync_start = 1366 + 48, 1584 .hsync_end = 1366 + 48 + 32, 1585 .htotal = 1366 + 48 + 32 + 20, 1586 .vdisplay = 768, 1587 .vsync_start = 768 + 16, 1588 .vsync_end = 768 + 16 + 8, 1589 .vtotal = 768 + 16 + 8 + 16, 1590 }; 1591 1592 static const struct panel_desc chunghwa_claa101wb01 = { 1593 .modes = &chunghwa_claa101wb01_mode, 1594 .num_modes = 1, 1595 .bpc = 6, 1596 .size = { 1597 .width = 223, 1598 .height = 125, 1599 }, 1600 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1601 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1602 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1603 }; 1604 1605 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1606 .clock = 33260, 1607 .hdisplay = 800, 1608 .hsync_start = 800 + 40, 1609 .hsync_end = 800 + 40 + 128, 1610 .htotal = 800 + 40 + 128 + 88, 1611 .vdisplay = 480, 1612 .vsync_start = 480 + 10, 1613 .vsync_end = 480 + 10 + 2, 1614 .vtotal = 480 + 10 + 2 + 33, 1615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1616 }; 1617 1618 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1619 .modes = &dataimage_scf0700c48ggu18_mode, 1620 .num_modes = 1, 1621 .bpc = 8, 1622 .size = { 1623 .width = 152, 1624 .height = 91, 1625 }, 1626 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1627 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1628 }; 1629 1630 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1631 .pixelclock = { 45000000, 51200000, 57000000 }, 1632 .hactive = { 1024, 1024, 1024 }, 1633 .hfront_porch = { 100, 106, 113 }, 1634 .hback_porch = { 100, 106, 113 }, 1635 .hsync_len = { 100, 108, 114 }, 1636 .vactive = { 600, 600, 600 }, 1637 .vfront_porch = { 8, 11, 15 }, 1638 .vback_porch = { 8, 11, 15 }, 1639 .vsync_len = { 9, 13, 15 }, 1640 .flags = DISPLAY_FLAGS_DE_HIGH, 1641 }; 1642 1643 static const struct panel_desc dlc_dlc0700yzg_1 = { 1644 .timings = &dlc_dlc0700yzg_1_timing, 1645 .num_timings = 1, 1646 .bpc = 6, 1647 .size = { 1648 .width = 154, 1649 .height = 86, 1650 }, 1651 .delay = { 1652 .prepare = 30, 1653 .enable = 200, 1654 .disable = 200, 1655 }, 1656 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1657 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1658 }; 1659 1660 static const struct display_timing dlc_dlc1010gig_timing = { 1661 .pixelclock = { 68900000, 71100000, 73400000 }, 1662 .hactive = { 1280, 1280, 1280 }, 1663 .hfront_porch = { 43, 53, 63 }, 1664 .hback_porch = { 43, 53, 63 }, 1665 .hsync_len = { 44, 54, 64 }, 1666 .vactive = { 800, 800, 800 }, 1667 .vfront_porch = { 5, 8, 11 }, 1668 .vback_porch = { 5, 8, 11 }, 1669 .vsync_len = { 5, 7, 11 }, 1670 .flags = DISPLAY_FLAGS_DE_HIGH, 1671 }; 1672 1673 static const struct panel_desc dlc_dlc1010gig = { 1674 .timings = &dlc_dlc1010gig_timing, 1675 .num_timings = 1, 1676 .bpc = 8, 1677 .size = { 1678 .width = 216, 1679 .height = 135, 1680 }, 1681 .delay = { 1682 .prepare = 60, 1683 .enable = 150, 1684 .disable = 100, 1685 .unprepare = 60, 1686 }, 1687 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1688 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1689 }; 1690 1691 static const struct drm_display_mode edt_et035012dm6_mode = { 1692 .clock = 6500, 1693 .hdisplay = 320, 1694 .hsync_start = 320 + 20, 1695 .hsync_end = 320 + 20 + 30, 1696 .htotal = 320 + 20 + 68, 1697 .vdisplay = 240, 1698 .vsync_start = 240 + 4, 1699 .vsync_end = 240 + 4 + 4, 1700 .vtotal = 240 + 4 + 4 + 14, 1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1702 }; 1703 1704 static const struct panel_desc edt_et035012dm6 = { 1705 .modes = &edt_et035012dm6_mode, 1706 .num_modes = 1, 1707 .bpc = 8, 1708 .size = { 1709 .width = 70, 1710 .height = 52, 1711 }, 1712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1713 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1714 }; 1715 1716 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1717 .clock = 10870, 1718 .hdisplay = 480, 1719 .hsync_start = 480 + 8, 1720 .hsync_end = 480 + 8 + 4, 1721 .htotal = 480 + 8 + 4 + 41, 1722 1723 /* 1724 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1725 * fb_align 1726 */ 1727 1728 .vdisplay = 288, 1729 .vsync_start = 288 + 2, 1730 .vsync_end = 288 + 2 + 4, 1731 .vtotal = 288 + 2 + 4 + 10, 1732 }; 1733 1734 static const struct panel_desc edt_etm043080dh6gp = { 1735 .modes = &edt_etm043080dh6gp_mode, 1736 .num_modes = 1, 1737 .bpc = 8, 1738 .size = { 1739 .width = 100, 1740 .height = 65, 1741 }, 1742 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1743 .connector_type = DRM_MODE_CONNECTOR_DPI, 1744 }; 1745 1746 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1747 .clock = 9000, 1748 .hdisplay = 480, 1749 .hsync_start = 480 + 2, 1750 .hsync_end = 480 + 2 + 41, 1751 .htotal = 480 + 2 + 41 + 2, 1752 .vdisplay = 272, 1753 .vsync_start = 272 + 2, 1754 .vsync_end = 272 + 2 + 10, 1755 .vtotal = 272 + 2 + 10 + 2, 1756 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1757 }; 1758 1759 static const struct panel_desc edt_etm0430g0dh6 = { 1760 .modes = &edt_etm0430g0dh6_mode, 1761 .num_modes = 1, 1762 .bpc = 6, 1763 .size = { 1764 .width = 95, 1765 .height = 54, 1766 }, 1767 }; 1768 1769 static const struct drm_display_mode edt_et057090dhu_mode = { 1770 .clock = 25175, 1771 .hdisplay = 640, 1772 .hsync_start = 640 + 16, 1773 .hsync_end = 640 + 16 + 30, 1774 .htotal = 640 + 16 + 30 + 114, 1775 .vdisplay = 480, 1776 .vsync_start = 480 + 10, 1777 .vsync_end = 480 + 10 + 3, 1778 .vtotal = 480 + 10 + 3 + 32, 1779 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1780 }; 1781 1782 static const struct panel_desc edt_et057090dhu = { 1783 .modes = &edt_et057090dhu_mode, 1784 .num_modes = 1, 1785 .bpc = 6, 1786 .size = { 1787 .width = 115, 1788 .height = 86, 1789 }, 1790 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1792 .connector_type = DRM_MODE_CONNECTOR_DPI, 1793 }; 1794 1795 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1796 .clock = 33260, 1797 .hdisplay = 800, 1798 .hsync_start = 800 + 40, 1799 .hsync_end = 800 + 40 + 128, 1800 .htotal = 800 + 40 + 128 + 88, 1801 .vdisplay = 480, 1802 .vsync_start = 480 + 10, 1803 .vsync_end = 480 + 10 + 2, 1804 .vtotal = 480 + 10 + 2 + 33, 1805 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1806 }; 1807 1808 static const struct panel_desc edt_etm0700g0dh6 = { 1809 .modes = &edt_etm0700g0dh6_mode, 1810 .num_modes = 1, 1811 .bpc = 6, 1812 .size = { 1813 .width = 152, 1814 .height = 91, 1815 }, 1816 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1818 .connector_type = DRM_MODE_CONNECTOR_DPI, 1819 }; 1820 1821 static const struct panel_desc edt_etm0700g0bdh6 = { 1822 .modes = &edt_etm0700g0dh6_mode, 1823 .num_modes = 1, 1824 .bpc = 6, 1825 .size = { 1826 .width = 152, 1827 .height = 91, 1828 }, 1829 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1830 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1831 }; 1832 1833 static const struct display_timing evervision_vgg804821_timing = { 1834 .pixelclock = { 27600000, 33300000, 50000000 }, 1835 .hactive = { 800, 800, 800 }, 1836 .hfront_porch = { 40, 66, 70 }, 1837 .hback_porch = { 40, 67, 70 }, 1838 .hsync_len = { 40, 67, 70 }, 1839 .vactive = { 480, 480, 480 }, 1840 .vfront_porch = { 6, 10, 10 }, 1841 .vback_porch = { 7, 11, 11 }, 1842 .vsync_len = { 7, 11, 11 }, 1843 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1844 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1845 DISPLAY_FLAGS_SYNC_NEGEDGE, 1846 }; 1847 1848 static const struct panel_desc evervision_vgg804821 = { 1849 .timings = &evervision_vgg804821_timing, 1850 .num_timings = 1, 1851 .bpc = 8, 1852 .size = { 1853 .width = 108, 1854 .height = 64, 1855 }, 1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1858 }; 1859 1860 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1861 .clock = 32260, 1862 .hdisplay = 800, 1863 .hsync_start = 800 + 168, 1864 .hsync_end = 800 + 168 + 64, 1865 .htotal = 800 + 168 + 64 + 88, 1866 .vdisplay = 480, 1867 .vsync_start = 480 + 37, 1868 .vsync_end = 480 + 37 + 2, 1869 .vtotal = 480 + 37 + 2 + 8, 1870 }; 1871 1872 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1873 .modes = &foxlink_fl500wvr00_a0t_mode, 1874 .num_modes = 1, 1875 .bpc = 8, 1876 .size = { 1877 .width = 108, 1878 .height = 65, 1879 }, 1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1881 }; 1882 1883 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1884 { /* 60 Hz */ 1885 .clock = 6000, 1886 .hdisplay = 320, 1887 .hsync_start = 320 + 44, 1888 .hsync_end = 320 + 44 + 16, 1889 .htotal = 320 + 44 + 16 + 20, 1890 .vdisplay = 240, 1891 .vsync_start = 240 + 2, 1892 .vsync_end = 240 + 2 + 6, 1893 .vtotal = 240 + 2 + 6 + 2, 1894 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1895 }, 1896 { /* 50 Hz */ 1897 .clock = 5400, 1898 .hdisplay = 320, 1899 .hsync_start = 320 + 56, 1900 .hsync_end = 320 + 56 + 16, 1901 .htotal = 320 + 56 + 16 + 40, 1902 .vdisplay = 240, 1903 .vsync_start = 240 + 2, 1904 .vsync_end = 240 + 2 + 6, 1905 .vtotal = 240 + 2 + 6 + 2, 1906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1907 }, 1908 }; 1909 1910 static const struct panel_desc frida_frd350h54004 = { 1911 .modes = frida_frd350h54004_modes, 1912 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1913 .bpc = 8, 1914 .size = { 1915 .width = 77, 1916 .height = 64, 1917 }, 1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1920 .connector_type = DRM_MODE_CONNECTOR_DPI, 1921 }; 1922 1923 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1924 .clock = 67185, 1925 .hdisplay = 800, 1926 .hsync_start = 800 + 20, 1927 .hsync_end = 800 + 20 + 24, 1928 .htotal = 800 + 20 + 24 + 20, 1929 .vdisplay = 1280, 1930 .vsync_start = 1280 + 4, 1931 .vsync_end = 1280 + 4 + 8, 1932 .vtotal = 1280 + 4 + 8 + 4, 1933 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1934 }; 1935 1936 static const struct panel_desc friendlyarm_hd702e = { 1937 .modes = &friendlyarm_hd702e_mode, 1938 .num_modes = 1, 1939 .size = { 1940 .width = 94, 1941 .height = 151, 1942 }, 1943 }; 1944 1945 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1946 .clock = 9000, 1947 .hdisplay = 480, 1948 .hsync_start = 480 + 5, 1949 .hsync_end = 480 + 5 + 1, 1950 .htotal = 480 + 5 + 1 + 40, 1951 .vdisplay = 272, 1952 .vsync_start = 272 + 8, 1953 .vsync_end = 272 + 8 + 1, 1954 .vtotal = 272 + 8 + 1 + 8, 1955 }; 1956 1957 static const struct panel_desc giantplus_gpg482739qs5 = { 1958 .modes = &giantplus_gpg482739qs5_mode, 1959 .num_modes = 1, 1960 .bpc = 8, 1961 .size = { 1962 .width = 95, 1963 .height = 54, 1964 }, 1965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1966 }; 1967 1968 static const struct display_timing giantplus_gpm940b0_timing = { 1969 .pixelclock = { 13500000, 27000000, 27500000 }, 1970 .hactive = { 320, 320, 320 }, 1971 .hfront_porch = { 14, 686, 718 }, 1972 .hback_porch = { 50, 70, 255 }, 1973 .hsync_len = { 1, 1, 1 }, 1974 .vactive = { 240, 240, 240 }, 1975 .vfront_porch = { 1, 1, 179 }, 1976 .vback_porch = { 1, 21, 31 }, 1977 .vsync_len = { 1, 1, 6 }, 1978 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1979 }; 1980 1981 static const struct panel_desc giantplus_gpm940b0 = { 1982 .timings = &giantplus_gpm940b0_timing, 1983 .num_timings = 1, 1984 .bpc = 8, 1985 .size = { 1986 .width = 60, 1987 .height = 45, 1988 }, 1989 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1990 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1991 }; 1992 1993 static const struct display_timing hannstar_hsd070pww1_timing = { 1994 .pixelclock = { 64300000, 71100000, 82000000 }, 1995 .hactive = { 1280, 1280, 1280 }, 1996 .hfront_porch = { 1, 1, 10 }, 1997 .hback_porch = { 1, 1, 10 }, 1998 /* 1999 * According to the data sheet, the minimum horizontal blanking interval 2000 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2001 * minimum working horizontal blanking interval to be 60 clocks. 2002 */ 2003 .hsync_len = { 58, 158, 661 }, 2004 .vactive = { 800, 800, 800 }, 2005 .vfront_porch = { 1, 1, 10 }, 2006 .vback_porch = { 1, 1, 10 }, 2007 .vsync_len = { 1, 21, 203 }, 2008 .flags = DISPLAY_FLAGS_DE_HIGH, 2009 }; 2010 2011 static const struct panel_desc hannstar_hsd070pww1 = { 2012 .timings = &hannstar_hsd070pww1_timing, 2013 .num_timings = 1, 2014 .bpc = 6, 2015 .size = { 2016 .width = 151, 2017 .height = 94, 2018 }, 2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2020 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2021 }; 2022 2023 static const struct display_timing hannstar_hsd100pxn1_timing = { 2024 .pixelclock = { 55000000, 65000000, 75000000 }, 2025 .hactive = { 1024, 1024, 1024 }, 2026 .hfront_porch = { 40, 40, 40 }, 2027 .hback_porch = { 220, 220, 220 }, 2028 .hsync_len = { 20, 60, 100 }, 2029 .vactive = { 768, 768, 768 }, 2030 .vfront_porch = { 7, 7, 7 }, 2031 .vback_porch = { 21, 21, 21 }, 2032 .vsync_len = { 10, 10, 10 }, 2033 .flags = DISPLAY_FLAGS_DE_HIGH, 2034 }; 2035 2036 static const struct panel_desc hannstar_hsd100pxn1 = { 2037 .timings = &hannstar_hsd100pxn1_timing, 2038 .num_timings = 1, 2039 .bpc = 6, 2040 .size = { 2041 .width = 203, 2042 .height = 152, 2043 }, 2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2045 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2046 }; 2047 2048 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2049 .clock = 33333, 2050 .hdisplay = 800, 2051 .hsync_start = 800 + 85, 2052 .hsync_end = 800 + 85 + 86, 2053 .htotal = 800 + 85 + 86 + 85, 2054 .vdisplay = 480, 2055 .vsync_start = 480 + 16, 2056 .vsync_end = 480 + 16 + 13, 2057 .vtotal = 480 + 16 + 13 + 16, 2058 }; 2059 2060 static const struct panel_desc hitachi_tx23d38vm0caa = { 2061 .modes = &hitachi_tx23d38vm0caa_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 195, 2066 .height = 117, 2067 }, 2068 .delay = { 2069 .enable = 160, 2070 .disable = 160, 2071 }, 2072 }; 2073 2074 static const struct drm_display_mode innolux_at043tn24_mode = { 2075 .clock = 9000, 2076 .hdisplay = 480, 2077 .hsync_start = 480 + 2, 2078 .hsync_end = 480 + 2 + 41, 2079 .htotal = 480 + 2 + 41 + 2, 2080 .vdisplay = 272, 2081 .vsync_start = 272 + 2, 2082 .vsync_end = 272 + 2 + 10, 2083 .vtotal = 272 + 2 + 10 + 2, 2084 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2085 }; 2086 2087 static const struct panel_desc innolux_at043tn24 = { 2088 .modes = &innolux_at043tn24_mode, 2089 .num_modes = 1, 2090 .bpc = 8, 2091 .size = { 2092 .width = 95, 2093 .height = 54, 2094 }, 2095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2096 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2097 }; 2098 2099 static const struct drm_display_mode innolux_at070tn92_mode = { 2100 .clock = 33333, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 210, 2103 .hsync_end = 800 + 210 + 20, 2104 .htotal = 800 + 210 + 20 + 46, 2105 .vdisplay = 480, 2106 .vsync_start = 480 + 22, 2107 .vsync_end = 480 + 22 + 10, 2108 .vtotal = 480 + 22 + 23 + 10, 2109 }; 2110 2111 static const struct panel_desc innolux_at070tn92 = { 2112 .modes = &innolux_at070tn92_mode, 2113 .num_modes = 1, 2114 .size = { 2115 .width = 154, 2116 .height = 86, 2117 }, 2118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2119 }; 2120 2121 static const struct display_timing innolux_g070y2_l01_timing = { 2122 .pixelclock = { 28000000, 29500000, 32000000 }, 2123 .hactive = { 800, 800, 800 }, 2124 .hfront_porch = { 61, 91, 141 }, 2125 .hback_porch = { 60, 90, 140 }, 2126 .hsync_len = { 12, 12, 12 }, 2127 .vactive = { 480, 480, 480 }, 2128 .vfront_porch = { 4, 9, 30 }, 2129 .vback_porch = { 4, 8, 28 }, 2130 .vsync_len = { 2, 2, 2 }, 2131 .flags = DISPLAY_FLAGS_DE_HIGH, 2132 }; 2133 2134 static const struct panel_desc innolux_g070y2_l01 = { 2135 .timings = &innolux_g070y2_l01_timing, 2136 .num_timings = 1, 2137 .bpc = 6, 2138 .size = { 2139 .width = 152, 2140 .height = 91, 2141 }, 2142 .delay = { 2143 .prepare = 10, 2144 .enable = 100, 2145 .disable = 100, 2146 .unprepare = 800, 2147 }, 2148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2149 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2150 }; 2151 2152 static const struct display_timing innolux_g101ice_l01_timing = { 2153 .pixelclock = { 60400000, 71100000, 74700000 }, 2154 .hactive = { 1280, 1280, 1280 }, 2155 .hfront_porch = { 41, 80, 100 }, 2156 .hback_porch = { 40, 79, 99 }, 2157 .hsync_len = { 1, 1, 1 }, 2158 .vactive = { 800, 800, 800 }, 2159 .vfront_porch = { 5, 11, 14 }, 2160 .vback_porch = { 4, 11, 14 }, 2161 .vsync_len = { 1, 1, 1 }, 2162 .flags = DISPLAY_FLAGS_DE_HIGH, 2163 }; 2164 2165 static const struct panel_desc innolux_g101ice_l01 = { 2166 .timings = &innolux_g101ice_l01_timing, 2167 .num_timings = 1, 2168 .bpc = 8, 2169 .size = { 2170 .width = 217, 2171 .height = 135, 2172 }, 2173 .delay = { 2174 .enable = 200, 2175 .disable = 200, 2176 }, 2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2178 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2179 }; 2180 2181 static const struct display_timing innolux_g121i1_l01_timing = { 2182 .pixelclock = { 67450000, 71000000, 74550000 }, 2183 .hactive = { 1280, 1280, 1280 }, 2184 .hfront_porch = { 40, 80, 160 }, 2185 .hback_porch = { 39, 79, 159 }, 2186 .hsync_len = { 1, 1, 1 }, 2187 .vactive = { 800, 800, 800 }, 2188 .vfront_porch = { 5, 11, 100 }, 2189 .vback_porch = { 4, 11, 99 }, 2190 .vsync_len = { 1, 1, 1 }, 2191 }; 2192 2193 static const struct panel_desc innolux_g121i1_l01 = { 2194 .timings = &innolux_g121i1_l01_timing, 2195 .num_timings = 1, 2196 .bpc = 6, 2197 .size = { 2198 .width = 261, 2199 .height = 163, 2200 }, 2201 .delay = { 2202 .enable = 200, 2203 .disable = 20, 2204 }, 2205 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2206 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2207 }; 2208 2209 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2210 .clock = 65000, 2211 .hdisplay = 1024, 2212 .hsync_start = 1024 + 0, 2213 .hsync_end = 1024 + 1, 2214 .htotal = 1024 + 0 + 1 + 320, 2215 .vdisplay = 768, 2216 .vsync_start = 768 + 38, 2217 .vsync_end = 768 + 38 + 1, 2218 .vtotal = 768 + 38 + 1 + 0, 2219 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2220 }; 2221 2222 static const struct panel_desc innolux_g121x1_l03 = { 2223 .modes = &innolux_g121x1_l03_mode, 2224 .num_modes = 1, 2225 .bpc = 6, 2226 .size = { 2227 .width = 246, 2228 .height = 185, 2229 }, 2230 .delay = { 2231 .enable = 200, 2232 .unprepare = 200, 2233 .disable = 400, 2234 }, 2235 }; 2236 2237 /* 2238 * Datasheet specifies that at 60 Hz refresh rate: 2239 * - total horizontal time: { 1506, 1592, 1716 } 2240 * - total vertical time: { 788, 800, 868 } 2241 * 2242 * ...but doesn't go into exactly how that should be split into a front 2243 * porch, back porch, or sync length. For now we'll leave a single setting 2244 * here which allows a bit of tweaking of the pixel clock at the expense of 2245 * refresh rate. 2246 */ 2247 static const struct display_timing innolux_n116bge_timing = { 2248 .pixelclock = { 72600000, 76420000, 80240000 }, 2249 .hactive = { 1366, 1366, 1366 }, 2250 .hfront_porch = { 136, 136, 136 }, 2251 .hback_porch = { 60, 60, 60 }, 2252 .hsync_len = { 30, 30, 30 }, 2253 .vactive = { 768, 768, 768 }, 2254 .vfront_porch = { 8, 8, 8 }, 2255 .vback_porch = { 12, 12, 12 }, 2256 .vsync_len = { 12, 12, 12 }, 2257 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2258 }; 2259 2260 static const struct panel_desc innolux_n116bge = { 2261 .timings = &innolux_n116bge_timing, 2262 .num_timings = 1, 2263 .bpc = 6, 2264 .size = { 2265 .width = 256, 2266 .height = 144, 2267 }, 2268 }; 2269 2270 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2271 .clock = 69300, 2272 .hdisplay = 1366, 2273 .hsync_start = 1366 + 16, 2274 .hsync_end = 1366 + 16 + 34, 2275 .htotal = 1366 + 16 + 34 + 50, 2276 .vdisplay = 768, 2277 .vsync_start = 768 + 2, 2278 .vsync_end = 768 + 2 + 6, 2279 .vtotal = 768 + 2 + 6 + 12, 2280 }; 2281 2282 static const struct panel_desc innolux_n156bge_l21 = { 2283 .modes = &innolux_n156bge_l21_mode, 2284 .num_modes = 1, 2285 .bpc = 6, 2286 .size = { 2287 .width = 344, 2288 .height = 193, 2289 }, 2290 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2291 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2292 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2293 }; 2294 2295 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2296 .clock = 206016, 2297 .hdisplay = 2160, 2298 .hsync_start = 2160 + 48, 2299 .hsync_end = 2160 + 48 + 32, 2300 .htotal = 2160 + 48 + 32 + 80, 2301 .vdisplay = 1440, 2302 .vsync_start = 1440 + 3, 2303 .vsync_end = 1440 + 3 + 10, 2304 .vtotal = 1440 + 3 + 10 + 27, 2305 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2306 }; 2307 2308 static const struct panel_desc innolux_p120zdg_bf1 = { 2309 .modes = &innolux_p120zdg_bf1_mode, 2310 .num_modes = 1, 2311 .bpc = 8, 2312 .size = { 2313 .width = 254, 2314 .height = 169, 2315 }, 2316 .delay = { 2317 .hpd_absent_delay = 200, 2318 .unprepare = 500, 2319 }, 2320 }; 2321 2322 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2323 .clock = 51501, 2324 .hdisplay = 1024, 2325 .hsync_start = 1024 + 128, 2326 .hsync_end = 1024 + 128 + 64, 2327 .htotal = 1024 + 128 + 64 + 128, 2328 .vdisplay = 600, 2329 .vsync_start = 600 + 16, 2330 .vsync_end = 600 + 16 + 4, 2331 .vtotal = 600 + 16 + 4 + 16, 2332 }; 2333 2334 static const struct panel_desc innolux_zj070na_01p = { 2335 .modes = &innolux_zj070na_01p_mode, 2336 .num_modes = 1, 2337 .bpc = 6, 2338 .size = { 2339 .width = 154, 2340 .height = 90, 2341 }, 2342 }; 2343 2344 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2345 .clock = 138778, 2346 .hdisplay = 1920, 2347 .hsync_start = 1920 + 24, 2348 .hsync_end = 1920 + 24 + 48, 2349 .htotal = 1920 + 24 + 48 + 88, 2350 .vdisplay = 1080, 2351 .vsync_start = 1080 + 3, 2352 .vsync_end = 1080 + 3 + 12, 2353 .vtotal = 1080 + 3 + 12 + 17, 2354 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2355 }; 2356 2357 static const struct panel_desc ivo_m133nwf4_r0 = { 2358 .modes = &ivo_m133nwf4_r0_mode, 2359 .num_modes = 1, 2360 .bpc = 8, 2361 .size = { 2362 .width = 294, 2363 .height = 165, 2364 }, 2365 .delay = { 2366 .hpd_absent_delay = 200, 2367 .unprepare = 500, 2368 }, 2369 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2370 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2371 .connector_type = DRM_MODE_CONNECTOR_eDP, 2372 }; 2373 2374 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2375 .clock = 81000, 2376 .hdisplay = 1366, 2377 .hsync_start = 1366 + 40, 2378 .hsync_end = 1366 + 40 + 32, 2379 .htotal = 1366 + 40 + 32 + 62, 2380 .vdisplay = 768, 2381 .vsync_start = 768 + 5, 2382 .vsync_end = 768 + 5 + 5, 2383 .vtotal = 768 + 5 + 5 + 122, 2384 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2385 }; 2386 2387 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2388 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2389 .num_modes = 1, 2390 .bpc = 6, 2391 .size = { 2392 .width = 256, 2393 .height = 144, 2394 }, 2395 .delay = { 2396 .hpd_absent_delay = 200, 2397 }, 2398 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2399 .connector_type = DRM_MODE_CONNECTOR_eDP, 2400 }; 2401 2402 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2403 .pixelclock = { 5580000, 5850000, 6200000 }, 2404 .hactive = { 320, 320, 320 }, 2405 .hfront_porch = { 30, 30, 30 }, 2406 .hback_porch = { 30, 30, 30 }, 2407 .hsync_len = { 1, 5, 17 }, 2408 .vactive = { 240, 240, 240 }, 2409 .vfront_porch = { 6, 6, 6 }, 2410 .vback_porch = { 5, 5, 5 }, 2411 .vsync_len = { 1, 2, 11 }, 2412 .flags = DISPLAY_FLAGS_DE_HIGH, 2413 }; 2414 2415 static const struct panel_desc koe_tx14d24vm1bpa = { 2416 .timings = &koe_tx14d24vm1bpa_timing, 2417 .num_timings = 1, 2418 .bpc = 6, 2419 .size = { 2420 .width = 115, 2421 .height = 86, 2422 }, 2423 }; 2424 2425 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2426 .pixelclock = { 151820000, 156720000, 159780000 }, 2427 .hactive = { 1920, 1920, 1920 }, 2428 .hfront_porch = { 105, 130, 142 }, 2429 .hback_porch = { 45, 70, 82 }, 2430 .hsync_len = { 30, 30, 30 }, 2431 .vactive = { 1200, 1200, 1200}, 2432 .vfront_porch = { 3, 5, 10 }, 2433 .vback_porch = { 2, 5, 10 }, 2434 .vsync_len = { 5, 5, 5 }, 2435 }; 2436 2437 static const struct panel_desc koe_tx26d202vm0bwa = { 2438 .timings = &koe_tx26d202vm0bwa_timing, 2439 .num_timings = 1, 2440 .bpc = 8, 2441 .size = { 2442 .width = 217, 2443 .height = 136, 2444 }, 2445 .delay = { 2446 .prepare = 1000, 2447 .enable = 1000, 2448 .unprepare = 1000, 2449 .disable = 1000, 2450 }, 2451 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2452 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2453 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2454 }; 2455 2456 static const struct display_timing koe_tx31d200vm0baa_timing = { 2457 .pixelclock = { 39600000, 43200000, 48000000 }, 2458 .hactive = { 1280, 1280, 1280 }, 2459 .hfront_porch = { 16, 36, 56 }, 2460 .hback_porch = { 16, 36, 56 }, 2461 .hsync_len = { 8, 8, 8 }, 2462 .vactive = { 480, 480, 480 }, 2463 .vfront_porch = { 6, 21, 33 }, 2464 .vback_porch = { 6, 21, 33 }, 2465 .vsync_len = { 8, 8, 8 }, 2466 .flags = DISPLAY_FLAGS_DE_HIGH, 2467 }; 2468 2469 static const struct panel_desc koe_tx31d200vm0baa = { 2470 .timings = &koe_tx31d200vm0baa_timing, 2471 .num_timings = 1, 2472 .bpc = 6, 2473 .size = { 2474 .width = 292, 2475 .height = 109, 2476 }, 2477 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2478 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2479 }; 2480 2481 static const struct display_timing kyo_tcg121xglp_timing = { 2482 .pixelclock = { 52000000, 65000000, 71000000 }, 2483 .hactive = { 1024, 1024, 1024 }, 2484 .hfront_porch = { 2, 2, 2 }, 2485 .hback_porch = { 2, 2, 2 }, 2486 .hsync_len = { 86, 124, 244 }, 2487 .vactive = { 768, 768, 768 }, 2488 .vfront_porch = { 2, 2, 2 }, 2489 .vback_porch = { 2, 2, 2 }, 2490 .vsync_len = { 6, 34, 73 }, 2491 .flags = DISPLAY_FLAGS_DE_HIGH, 2492 }; 2493 2494 static const struct panel_desc kyo_tcg121xglp = { 2495 .timings = &kyo_tcg121xglp_timing, 2496 .num_timings = 1, 2497 .bpc = 8, 2498 .size = { 2499 .width = 246, 2500 .height = 184, 2501 }, 2502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2503 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2504 }; 2505 2506 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2507 .clock = 7000, 2508 .hdisplay = 320, 2509 .hsync_start = 320 + 20, 2510 .hsync_end = 320 + 20 + 30, 2511 .htotal = 320 + 20 + 30 + 38, 2512 .vdisplay = 240, 2513 .vsync_start = 240 + 4, 2514 .vsync_end = 240 + 4 + 3, 2515 .vtotal = 240 + 4 + 3 + 15, 2516 }; 2517 2518 static const struct panel_desc lemaker_bl035_rgb_002 = { 2519 .modes = &lemaker_bl035_rgb_002_mode, 2520 .num_modes = 1, 2521 .size = { 2522 .width = 70, 2523 .height = 52, 2524 }, 2525 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2526 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2527 }; 2528 2529 static const struct drm_display_mode lg_lb070wv8_mode = { 2530 .clock = 33246, 2531 .hdisplay = 800, 2532 .hsync_start = 800 + 88, 2533 .hsync_end = 800 + 88 + 80, 2534 .htotal = 800 + 88 + 80 + 88, 2535 .vdisplay = 480, 2536 .vsync_start = 480 + 10, 2537 .vsync_end = 480 + 10 + 25, 2538 .vtotal = 480 + 10 + 25 + 10, 2539 }; 2540 2541 static const struct panel_desc lg_lb070wv8 = { 2542 .modes = &lg_lb070wv8_mode, 2543 .num_modes = 1, 2544 .bpc = 8, 2545 .size = { 2546 .width = 151, 2547 .height = 91, 2548 }, 2549 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2551 }; 2552 2553 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2554 .clock = 200000, 2555 .hdisplay = 1536, 2556 .hsync_start = 1536 + 12, 2557 .hsync_end = 1536 + 12 + 16, 2558 .htotal = 1536 + 12 + 16 + 48, 2559 .vdisplay = 2048, 2560 .vsync_start = 2048 + 8, 2561 .vsync_end = 2048 + 8 + 4, 2562 .vtotal = 2048 + 8 + 4 + 8, 2563 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2564 }; 2565 2566 static const struct panel_desc lg_lp079qx1_sp0v = { 2567 .modes = &lg_lp079qx1_sp0v_mode, 2568 .num_modes = 1, 2569 .size = { 2570 .width = 129, 2571 .height = 171, 2572 }, 2573 }; 2574 2575 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2576 .clock = 205210, 2577 .hdisplay = 2048, 2578 .hsync_start = 2048 + 150, 2579 .hsync_end = 2048 + 150 + 5, 2580 .htotal = 2048 + 150 + 5 + 5, 2581 .vdisplay = 1536, 2582 .vsync_start = 1536 + 3, 2583 .vsync_end = 1536 + 3 + 1, 2584 .vtotal = 1536 + 3 + 1 + 9, 2585 }; 2586 2587 static const struct panel_desc lg_lp097qx1_spa1 = { 2588 .modes = &lg_lp097qx1_spa1_mode, 2589 .num_modes = 1, 2590 .size = { 2591 .width = 208, 2592 .height = 147, 2593 }, 2594 }; 2595 2596 static const struct drm_display_mode lg_lp120up1_mode = { 2597 .clock = 162300, 2598 .hdisplay = 1920, 2599 .hsync_start = 1920 + 40, 2600 .hsync_end = 1920 + 40 + 40, 2601 .htotal = 1920 + 40 + 40+ 80, 2602 .vdisplay = 1280, 2603 .vsync_start = 1280 + 4, 2604 .vsync_end = 1280 + 4 + 4, 2605 .vtotal = 1280 + 4 + 4 + 12, 2606 }; 2607 2608 static const struct panel_desc lg_lp120up1 = { 2609 .modes = &lg_lp120up1_mode, 2610 .num_modes = 1, 2611 .bpc = 8, 2612 .size = { 2613 .width = 267, 2614 .height = 183, 2615 }, 2616 .connector_type = DRM_MODE_CONNECTOR_eDP, 2617 }; 2618 2619 static const struct drm_display_mode lg_lp129qe_mode = { 2620 .clock = 285250, 2621 .hdisplay = 2560, 2622 .hsync_start = 2560 + 48, 2623 .hsync_end = 2560 + 48 + 32, 2624 .htotal = 2560 + 48 + 32 + 80, 2625 .vdisplay = 1700, 2626 .vsync_start = 1700 + 3, 2627 .vsync_end = 1700 + 3 + 10, 2628 .vtotal = 1700 + 3 + 10 + 36, 2629 }; 2630 2631 static const struct panel_desc lg_lp129qe = { 2632 .modes = &lg_lp129qe_mode, 2633 .num_modes = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 272, 2637 .height = 181, 2638 }, 2639 }; 2640 2641 static const struct display_timing logictechno_lt161010_2nh_timing = { 2642 .pixelclock = { 26400000, 33300000, 46800000 }, 2643 .hactive = { 800, 800, 800 }, 2644 .hfront_porch = { 16, 210, 354 }, 2645 .hback_porch = { 46, 46, 46 }, 2646 .hsync_len = { 1, 20, 40 }, 2647 .vactive = { 480, 480, 480 }, 2648 .vfront_porch = { 7, 22, 147 }, 2649 .vback_porch = { 23, 23, 23 }, 2650 .vsync_len = { 1, 10, 20 }, 2651 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2652 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2653 DISPLAY_FLAGS_SYNC_POSEDGE, 2654 }; 2655 2656 static const struct panel_desc logictechno_lt161010_2nh = { 2657 .timings = &logictechno_lt161010_2nh_timing, 2658 .num_timings = 1, 2659 .size = { 2660 .width = 154, 2661 .height = 86, 2662 }, 2663 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2664 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2666 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2667 .connector_type = DRM_MODE_CONNECTOR_DPI, 2668 }; 2669 2670 static const struct display_timing logictechno_lt170410_2whc_timing = { 2671 .pixelclock = { 68900000, 71100000, 73400000 }, 2672 .hactive = { 1280, 1280, 1280 }, 2673 .hfront_porch = { 23, 60, 71 }, 2674 .hback_porch = { 23, 60, 71 }, 2675 .hsync_len = { 15, 40, 47 }, 2676 .vactive = { 800, 800, 800 }, 2677 .vfront_porch = { 5, 7, 10 }, 2678 .vback_porch = { 5, 7, 10 }, 2679 .vsync_len = { 6, 9, 12 }, 2680 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2681 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2682 DISPLAY_FLAGS_SYNC_POSEDGE, 2683 }; 2684 2685 static const struct panel_desc logictechno_lt170410_2whc = { 2686 .timings = &logictechno_lt170410_2whc_timing, 2687 .num_timings = 1, 2688 .size = { 2689 .width = 217, 2690 .height = 136, 2691 }, 2692 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2693 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2694 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2695 }; 2696 2697 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2698 .clock = 30400, 2699 .hdisplay = 800, 2700 .hsync_start = 800 + 0, 2701 .hsync_end = 800 + 1, 2702 .htotal = 800 + 0 + 1 + 160, 2703 .vdisplay = 480, 2704 .vsync_start = 480 + 0, 2705 .vsync_end = 480 + 48 + 1, 2706 .vtotal = 480 + 48 + 1 + 0, 2707 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2708 }; 2709 2710 static const struct drm_display_mode logicpd_type_28_mode = { 2711 .clock = 9107, 2712 .hdisplay = 480, 2713 .hsync_start = 480 + 3, 2714 .hsync_end = 480 + 3 + 42, 2715 .htotal = 480 + 3 + 42 + 2, 2716 2717 .vdisplay = 272, 2718 .vsync_start = 272 + 2, 2719 .vsync_end = 272 + 2 + 11, 2720 .vtotal = 272 + 2 + 11 + 3, 2721 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2722 }; 2723 2724 static const struct panel_desc logicpd_type_28 = { 2725 .modes = &logicpd_type_28_mode, 2726 .num_modes = 1, 2727 .bpc = 8, 2728 .size = { 2729 .width = 105, 2730 .height = 67, 2731 }, 2732 .delay = { 2733 .prepare = 200, 2734 .enable = 200, 2735 .unprepare = 200, 2736 .disable = 200, 2737 }, 2738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2740 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2741 .connector_type = DRM_MODE_CONNECTOR_DPI, 2742 }; 2743 2744 static const struct panel_desc mitsubishi_aa070mc01 = { 2745 .modes = &mitsubishi_aa070mc01_mode, 2746 .num_modes = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 152, 2750 .height = 91, 2751 }, 2752 2753 .delay = { 2754 .enable = 200, 2755 .unprepare = 200, 2756 .disable = 400, 2757 }, 2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2760 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2761 }; 2762 2763 static const struct display_timing nec_nl12880bc20_05_timing = { 2764 .pixelclock = { 67000000, 71000000, 75000000 }, 2765 .hactive = { 1280, 1280, 1280 }, 2766 .hfront_porch = { 2, 30, 30 }, 2767 .hback_porch = { 6, 100, 100 }, 2768 .hsync_len = { 2, 30, 30 }, 2769 .vactive = { 800, 800, 800 }, 2770 .vfront_porch = { 5, 5, 5 }, 2771 .vback_porch = { 11, 11, 11 }, 2772 .vsync_len = { 7, 7, 7 }, 2773 }; 2774 2775 static const struct panel_desc nec_nl12880bc20_05 = { 2776 .timings = &nec_nl12880bc20_05_timing, 2777 .num_timings = 1, 2778 .bpc = 8, 2779 .size = { 2780 .width = 261, 2781 .height = 163, 2782 }, 2783 .delay = { 2784 .enable = 50, 2785 .disable = 50, 2786 }, 2787 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2788 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2789 }; 2790 2791 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2792 .clock = 10870, 2793 .hdisplay = 480, 2794 .hsync_start = 480 + 2, 2795 .hsync_end = 480 + 2 + 41, 2796 .htotal = 480 + 2 + 41 + 2, 2797 .vdisplay = 272, 2798 .vsync_start = 272 + 2, 2799 .vsync_end = 272 + 2 + 4, 2800 .vtotal = 272 + 2 + 4 + 2, 2801 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2802 }; 2803 2804 static const struct panel_desc nec_nl4827hc19_05b = { 2805 .modes = &nec_nl4827hc19_05b_mode, 2806 .num_modes = 1, 2807 .bpc = 8, 2808 .size = { 2809 .width = 95, 2810 .height = 54, 2811 }, 2812 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2813 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2814 }; 2815 2816 static const struct drm_display_mode netron_dy_e231732_mode = { 2817 .clock = 66000, 2818 .hdisplay = 1024, 2819 .hsync_start = 1024 + 160, 2820 .hsync_end = 1024 + 160 + 70, 2821 .htotal = 1024 + 160 + 70 + 90, 2822 .vdisplay = 600, 2823 .vsync_start = 600 + 127, 2824 .vsync_end = 600 + 127 + 20, 2825 .vtotal = 600 + 127 + 20 + 3, 2826 }; 2827 2828 static const struct panel_desc netron_dy_e231732 = { 2829 .modes = &netron_dy_e231732_mode, 2830 .num_modes = 1, 2831 .size = { 2832 .width = 154, 2833 .height = 87, 2834 }, 2835 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2836 }; 2837 2838 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2839 { 2840 .clock = 138500, 2841 .hdisplay = 1920, 2842 .hsync_start = 1920 + 48, 2843 .hsync_end = 1920 + 48 + 32, 2844 .htotal = 1920 + 48 + 32 + 80, 2845 .vdisplay = 1080, 2846 .vsync_start = 1080 + 3, 2847 .vsync_end = 1080 + 3 + 5, 2848 .vtotal = 1080 + 3 + 5 + 23, 2849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2850 }, { 2851 .clock = 110920, 2852 .hdisplay = 1920, 2853 .hsync_start = 1920 + 48, 2854 .hsync_end = 1920 + 48 + 32, 2855 .htotal = 1920 + 48 + 32 + 80, 2856 .vdisplay = 1080, 2857 .vsync_start = 1080 + 3, 2858 .vsync_end = 1080 + 3 + 5, 2859 .vtotal = 1080 + 3 + 5 + 23, 2860 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2861 } 2862 }; 2863 2864 static const struct panel_desc neweast_wjfh116008a = { 2865 .modes = neweast_wjfh116008a_modes, 2866 .num_modes = 2, 2867 .bpc = 6, 2868 .size = { 2869 .width = 260, 2870 .height = 150, 2871 }, 2872 .delay = { 2873 .prepare = 110, 2874 .enable = 20, 2875 .unprepare = 500, 2876 }, 2877 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2878 .connector_type = DRM_MODE_CONNECTOR_eDP, 2879 }; 2880 2881 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2882 .clock = 9000, 2883 .hdisplay = 480, 2884 .hsync_start = 480 + 2, 2885 .hsync_end = 480 + 2 + 41, 2886 .htotal = 480 + 2 + 41 + 2, 2887 .vdisplay = 272, 2888 .vsync_start = 272 + 2, 2889 .vsync_end = 272 + 2 + 10, 2890 .vtotal = 272 + 2 + 10 + 2, 2891 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2892 }; 2893 2894 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2895 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2896 .num_modes = 1, 2897 .bpc = 8, 2898 .size = { 2899 .width = 95, 2900 .height = 54, 2901 }, 2902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2903 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2904 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2905 .connector_type = DRM_MODE_CONNECTOR_DPI, 2906 }; 2907 2908 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2909 .pixelclock = { 130000000, 148350000, 163000000 }, 2910 .hactive = { 1920, 1920, 1920 }, 2911 .hfront_porch = { 80, 100, 100 }, 2912 .hback_porch = { 100, 120, 120 }, 2913 .hsync_len = { 50, 60, 60 }, 2914 .vactive = { 1080, 1080, 1080 }, 2915 .vfront_porch = { 12, 30, 30 }, 2916 .vback_porch = { 4, 10, 10 }, 2917 .vsync_len = { 4, 5, 5 }, 2918 }; 2919 2920 static const struct panel_desc nlt_nl192108ac18_02d = { 2921 .timings = &nlt_nl192108ac18_02d_timing, 2922 .num_timings = 1, 2923 .bpc = 8, 2924 .size = { 2925 .width = 344, 2926 .height = 194, 2927 }, 2928 .delay = { 2929 .unprepare = 500, 2930 }, 2931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2933 }; 2934 2935 static const struct drm_display_mode nvd_9128_mode = { 2936 .clock = 29500, 2937 .hdisplay = 800, 2938 .hsync_start = 800 + 130, 2939 .hsync_end = 800 + 130 + 98, 2940 .htotal = 800 + 0 + 130 + 98, 2941 .vdisplay = 480, 2942 .vsync_start = 480 + 10, 2943 .vsync_end = 480 + 10 + 50, 2944 .vtotal = 480 + 0 + 10 + 50, 2945 }; 2946 2947 static const struct panel_desc nvd_9128 = { 2948 .modes = &nvd_9128_mode, 2949 .num_modes = 1, 2950 .bpc = 8, 2951 .size = { 2952 .width = 156, 2953 .height = 88, 2954 }, 2955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2956 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2957 }; 2958 2959 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2960 .pixelclock = { 30000000, 30000000, 40000000 }, 2961 .hactive = { 800, 800, 800 }, 2962 .hfront_porch = { 40, 40, 40 }, 2963 .hback_porch = { 40, 40, 40 }, 2964 .hsync_len = { 1, 48, 48 }, 2965 .vactive = { 480, 480, 480 }, 2966 .vfront_porch = { 13, 13, 13 }, 2967 .vback_porch = { 29, 29, 29 }, 2968 .vsync_len = { 3, 3, 3 }, 2969 .flags = DISPLAY_FLAGS_DE_HIGH, 2970 }; 2971 2972 static const struct panel_desc okaya_rs800480t_7x0gp = { 2973 .timings = &okaya_rs800480t_7x0gp_timing, 2974 .num_timings = 1, 2975 .bpc = 6, 2976 .size = { 2977 .width = 154, 2978 .height = 87, 2979 }, 2980 .delay = { 2981 .prepare = 41, 2982 .enable = 50, 2983 .unprepare = 41, 2984 .disable = 50, 2985 }, 2986 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2987 }; 2988 2989 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2990 .clock = 9000, 2991 .hdisplay = 480, 2992 .hsync_start = 480 + 5, 2993 .hsync_end = 480 + 5 + 30, 2994 .htotal = 480 + 5 + 30 + 10, 2995 .vdisplay = 272, 2996 .vsync_start = 272 + 8, 2997 .vsync_end = 272 + 8 + 5, 2998 .vtotal = 272 + 8 + 5 + 3, 2999 }; 3000 3001 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3002 .modes = &olimex_lcd_olinuxino_43ts_mode, 3003 .num_modes = 1, 3004 .size = { 3005 .width = 95, 3006 .height = 54, 3007 }, 3008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3009 }; 3010 3011 /* 3012 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3013 * pixel clocks, but this is the timing that was being used in the Adafruit 3014 * installation instructions. 3015 */ 3016 static const struct drm_display_mode ontat_yx700wv03_mode = { 3017 .clock = 29500, 3018 .hdisplay = 800, 3019 .hsync_start = 824, 3020 .hsync_end = 896, 3021 .htotal = 992, 3022 .vdisplay = 480, 3023 .vsync_start = 483, 3024 .vsync_end = 493, 3025 .vtotal = 500, 3026 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3027 }; 3028 3029 /* 3030 * Specification at: 3031 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3032 */ 3033 static const struct panel_desc ontat_yx700wv03 = { 3034 .modes = &ontat_yx700wv03_mode, 3035 .num_modes = 1, 3036 .bpc = 8, 3037 .size = { 3038 .width = 154, 3039 .height = 83, 3040 }, 3041 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3042 }; 3043 3044 static const struct drm_display_mode ortustech_com37h3m_mode = { 3045 .clock = 22230, 3046 .hdisplay = 480, 3047 .hsync_start = 480 + 40, 3048 .hsync_end = 480 + 40 + 10, 3049 .htotal = 480 + 40 + 10 + 40, 3050 .vdisplay = 640, 3051 .vsync_start = 640 + 4, 3052 .vsync_end = 640 + 4 + 2, 3053 .vtotal = 640 + 4 + 2 + 4, 3054 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3055 }; 3056 3057 static const struct panel_desc ortustech_com37h3m = { 3058 .modes = &ortustech_com37h3m_mode, 3059 .num_modes = 1, 3060 .bpc = 8, 3061 .size = { 3062 .width = 56, /* 56.16mm */ 3063 .height = 75, /* 74.88mm */ 3064 }, 3065 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3067 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3068 }; 3069 3070 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3071 .clock = 25000, 3072 .hdisplay = 480, 3073 .hsync_start = 480 + 10, 3074 .hsync_end = 480 + 10 + 10, 3075 .htotal = 480 + 10 + 10 + 15, 3076 .vdisplay = 800, 3077 .vsync_start = 800 + 3, 3078 .vsync_end = 800 + 3 + 3, 3079 .vtotal = 800 + 3 + 3 + 3, 3080 }; 3081 3082 static const struct panel_desc ortustech_com43h4m85ulc = { 3083 .modes = &ortustech_com43h4m85ulc_mode, 3084 .num_modes = 1, 3085 .bpc = 6, 3086 .size = { 3087 .width = 56, 3088 .height = 93, 3089 }, 3090 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3091 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3092 .connector_type = DRM_MODE_CONNECTOR_DPI, 3093 }; 3094 3095 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3096 .clock = 33000, 3097 .hdisplay = 800, 3098 .hsync_start = 800 + 210, 3099 .hsync_end = 800 + 210 + 30, 3100 .htotal = 800 + 210 + 30 + 16, 3101 .vdisplay = 480, 3102 .vsync_start = 480 + 22, 3103 .vsync_end = 480 + 22 + 13, 3104 .vtotal = 480 + 22 + 13 + 10, 3105 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3106 }; 3107 3108 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3109 .modes = &osddisplays_osd070t1718_19ts_mode, 3110 .num_modes = 1, 3111 .bpc = 8, 3112 .size = { 3113 .width = 152, 3114 .height = 91, 3115 }, 3116 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3117 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3118 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3119 .connector_type = DRM_MODE_CONNECTOR_DPI, 3120 }; 3121 3122 static const struct drm_display_mode pda_91_00156_a0_mode = { 3123 .clock = 33300, 3124 .hdisplay = 800, 3125 .hsync_start = 800 + 1, 3126 .hsync_end = 800 + 1 + 64, 3127 .htotal = 800 + 1 + 64 + 64, 3128 .vdisplay = 480, 3129 .vsync_start = 480 + 1, 3130 .vsync_end = 480 + 1 + 23, 3131 .vtotal = 480 + 1 + 23 + 22, 3132 }; 3133 3134 static const struct panel_desc pda_91_00156_a0 = { 3135 .modes = &pda_91_00156_a0_mode, 3136 .num_modes = 1, 3137 .size = { 3138 .width = 152, 3139 .height = 91, 3140 }, 3141 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3142 }; 3143 3144 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3145 .clock = 24750, 3146 .hdisplay = 800, 3147 .hsync_start = 800 + 54, 3148 .hsync_end = 800 + 54 + 2, 3149 .htotal = 800 + 54 + 2 + 44, 3150 .vdisplay = 480, 3151 .vsync_start = 480 + 49, 3152 .vsync_end = 480 + 49 + 2, 3153 .vtotal = 480 + 49 + 2 + 22, 3154 }; 3155 3156 static const struct panel_desc powertip_ph800480t013_idf02 = { 3157 .modes = &powertip_ph800480t013_idf02_mode, 3158 .num_modes = 1, 3159 .size = { 3160 .width = 152, 3161 .height = 91, 3162 }, 3163 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3164 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3165 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3167 .connector_type = DRM_MODE_CONNECTOR_DPI, 3168 }; 3169 3170 static const struct drm_display_mode qd43003c0_40_mode = { 3171 .clock = 9000, 3172 .hdisplay = 480, 3173 .hsync_start = 480 + 8, 3174 .hsync_end = 480 + 8 + 4, 3175 .htotal = 480 + 8 + 4 + 39, 3176 .vdisplay = 272, 3177 .vsync_start = 272 + 4, 3178 .vsync_end = 272 + 4 + 10, 3179 .vtotal = 272 + 4 + 10 + 2, 3180 }; 3181 3182 static const struct panel_desc qd43003c0_40 = { 3183 .modes = &qd43003c0_40_mode, 3184 .num_modes = 1, 3185 .bpc = 8, 3186 .size = { 3187 .width = 95, 3188 .height = 53, 3189 }, 3190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3191 }; 3192 3193 static const struct display_timing rocktech_rk070er9427_timing = { 3194 .pixelclock = { 26400000, 33300000, 46800000 }, 3195 .hactive = { 800, 800, 800 }, 3196 .hfront_porch = { 16, 210, 354 }, 3197 .hback_porch = { 46, 46, 46 }, 3198 .hsync_len = { 1, 1, 1 }, 3199 .vactive = { 480, 480, 480 }, 3200 .vfront_porch = { 7, 22, 147 }, 3201 .vback_porch = { 23, 23, 23 }, 3202 .vsync_len = { 1, 1, 1 }, 3203 .flags = DISPLAY_FLAGS_DE_HIGH, 3204 }; 3205 3206 static const struct panel_desc rocktech_rk070er9427 = { 3207 .timings = &rocktech_rk070er9427_timing, 3208 .num_timings = 1, 3209 .bpc = 6, 3210 .size = { 3211 .width = 154, 3212 .height = 86, 3213 }, 3214 .delay = { 3215 .prepare = 41, 3216 .enable = 50, 3217 .unprepare = 41, 3218 .disable = 50, 3219 }, 3220 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3221 }; 3222 3223 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3224 .clock = 71100, 3225 .hdisplay = 1280, 3226 .hsync_start = 1280 + 48, 3227 .hsync_end = 1280 + 48 + 32, 3228 .htotal = 1280 + 48 + 32 + 80, 3229 .vdisplay = 800, 3230 .vsync_start = 800 + 2, 3231 .vsync_end = 800 + 2 + 5, 3232 .vtotal = 800 + 2 + 5 + 16, 3233 }; 3234 3235 static const struct panel_desc rocktech_rk101ii01d_ct = { 3236 .modes = &rocktech_rk101ii01d_ct_mode, 3237 .num_modes = 1, 3238 .size = { 3239 .width = 217, 3240 .height = 136, 3241 }, 3242 .delay = { 3243 .prepare = 50, 3244 .disable = 50, 3245 }, 3246 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3247 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3248 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3249 }; 3250 3251 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3252 .clock = 271560, 3253 .hdisplay = 2560, 3254 .hsync_start = 2560 + 48, 3255 .hsync_end = 2560 + 48 + 32, 3256 .htotal = 2560 + 48 + 32 + 80, 3257 .vdisplay = 1600, 3258 .vsync_start = 1600 + 2, 3259 .vsync_end = 1600 + 2 + 5, 3260 .vtotal = 1600 + 2 + 5 + 57, 3261 }; 3262 3263 static const struct panel_desc samsung_lsn122dl01_c01 = { 3264 .modes = &samsung_lsn122dl01_c01_mode, 3265 .num_modes = 1, 3266 .size = { 3267 .width = 263, 3268 .height = 164, 3269 }, 3270 }; 3271 3272 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3273 .clock = 54030, 3274 .hdisplay = 1024, 3275 .hsync_start = 1024 + 24, 3276 .hsync_end = 1024 + 24 + 136, 3277 .htotal = 1024 + 24 + 136 + 160, 3278 .vdisplay = 600, 3279 .vsync_start = 600 + 3, 3280 .vsync_end = 600 + 3 + 6, 3281 .vtotal = 600 + 3 + 6 + 61, 3282 }; 3283 3284 static const struct panel_desc samsung_ltn101nt05 = { 3285 .modes = &samsung_ltn101nt05_mode, 3286 .num_modes = 1, 3287 .bpc = 6, 3288 .size = { 3289 .width = 223, 3290 .height = 125, 3291 }, 3292 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3293 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3294 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3295 }; 3296 3297 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3298 .clock = 76300, 3299 .hdisplay = 1366, 3300 .hsync_start = 1366 + 64, 3301 .hsync_end = 1366 + 64 + 48, 3302 .htotal = 1366 + 64 + 48 + 128, 3303 .vdisplay = 768, 3304 .vsync_start = 768 + 2, 3305 .vsync_end = 768 + 2 + 5, 3306 .vtotal = 768 + 2 + 5 + 17, 3307 }; 3308 3309 static const struct panel_desc samsung_ltn140at29_301 = { 3310 .modes = &samsung_ltn140at29_301_mode, 3311 .num_modes = 1, 3312 .bpc = 6, 3313 .size = { 3314 .width = 320, 3315 .height = 187, 3316 }, 3317 }; 3318 3319 static const struct display_timing satoz_sat050at40h12r2_timing = { 3320 .pixelclock = {33300000, 33300000, 50000000}, 3321 .hactive = {800, 800, 800}, 3322 .hfront_porch = {16, 210, 354}, 3323 .hback_porch = {46, 46, 46}, 3324 .hsync_len = {1, 1, 40}, 3325 .vactive = {480, 480, 480}, 3326 .vfront_porch = {7, 22, 147}, 3327 .vback_porch = {23, 23, 23}, 3328 .vsync_len = {1, 1, 20}, 3329 }; 3330 3331 static const struct panel_desc satoz_sat050at40h12r2 = { 3332 .timings = &satoz_sat050at40h12r2_timing, 3333 .num_timings = 1, 3334 .bpc = 8, 3335 .size = { 3336 .width = 108, 3337 .height = 65, 3338 }, 3339 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3340 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3341 }; 3342 3343 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3344 .clock = 168480, 3345 .hdisplay = 1920, 3346 .hsync_start = 1920 + 48, 3347 .hsync_end = 1920 + 48 + 32, 3348 .htotal = 1920 + 48 + 32 + 80, 3349 .vdisplay = 1280, 3350 .vsync_start = 1280 + 3, 3351 .vsync_end = 1280 + 3 + 10, 3352 .vtotal = 1280 + 3 + 10 + 57, 3353 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3354 }; 3355 3356 static const struct panel_desc sharp_ld_d5116z01b = { 3357 .modes = &sharp_ld_d5116z01b_mode, 3358 .num_modes = 1, 3359 .bpc = 8, 3360 .size = { 3361 .width = 260, 3362 .height = 120, 3363 }, 3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3365 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3366 }; 3367 3368 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3369 .clock = 33260, 3370 .hdisplay = 800, 3371 .hsync_start = 800 + 64, 3372 .hsync_end = 800 + 64 + 128, 3373 .htotal = 800 + 64 + 128 + 64, 3374 .vdisplay = 480, 3375 .vsync_start = 480 + 8, 3376 .vsync_end = 480 + 8 + 2, 3377 .vtotal = 480 + 8 + 2 + 35, 3378 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3379 }; 3380 3381 static const struct panel_desc sharp_lq070y3dg3b = { 3382 .modes = &sharp_lq070y3dg3b_mode, 3383 .num_modes = 1, 3384 .bpc = 8, 3385 .size = { 3386 .width = 152, /* 152.4mm */ 3387 .height = 91, /* 91.4mm */ 3388 }, 3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3390 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3391 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3392 }; 3393 3394 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3395 .clock = 5500, 3396 .hdisplay = 240, 3397 .hsync_start = 240 + 16, 3398 .hsync_end = 240 + 16 + 7, 3399 .htotal = 240 + 16 + 7 + 5, 3400 .vdisplay = 320, 3401 .vsync_start = 320 + 9, 3402 .vsync_end = 320 + 9 + 1, 3403 .vtotal = 320 + 9 + 1 + 7, 3404 }; 3405 3406 static const struct panel_desc sharp_lq035q7db03 = { 3407 .modes = &sharp_lq035q7db03_mode, 3408 .num_modes = 1, 3409 .bpc = 6, 3410 .size = { 3411 .width = 54, 3412 .height = 72, 3413 }, 3414 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3415 }; 3416 3417 static const struct display_timing sharp_lq101k1ly04_timing = { 3418 .pixelclock = { 60000000, 65000000, 80000000 }, 3419 .hactive = { 1280, 1280, 1280 }, 3420 .hfront_porch = { 20, 20, 20 }, 3421 .hback_porch = { 20, 20, 20 }, 3422 .hsync_len = { 10, 10, 10 }, 3423 .vactive = { 800, 800, 800 }, 3424 .vfront_porch = { 4, 4, 4 }, 3425 .vback_porch = { 4, 4, 4 }, 3426 .vsync_len = { 4, 4, 4 }, 3427 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3428 }; 3429 3430 static const struct panel_desc sharp_lq101k1ly04 = { 3431 .timings = &sharp_lq101k1ly04_timing, 3432 .num_timings = 1, 3433 .bpc = 8, 3434 .size = { 3435 .width = 217, 3436 .height = 136, 3437 }, 3438 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3439 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3440 }; 3441 3442 static const struct display_timing sharp_lq123p1jx31_timing = { 3443 .pixelclock = { 252750000, 252750000, 266604720 }, 3444 .hactive = { 2400, 2400, 2400 }, 3445 .hfront_porch = { 48, 48, 48 }, 3446 .hback_porch = { 80, 80, 84 }, 3447 .hsync_len = { 32, 32, 32 }, 3448 .vactive = { 1600, 1600, 1600 }, 3449 .vfront_porch = { 3, 3, 3 }, 3450 .vback_porch = { 33, 33, 120 }, 3451 .vsync_len = { 10, 10, 10 }, 3452 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3453 }; 3454 3455 static const struct panel_desc sharp_lq123p1jx31 = { 3456 .timings = &sharp_lq123p1jx31_timing, 3457 .num_timings = 1, 3458 .bpc = 8, 3459 .size = { 3460 .width = 259, 3461 .height = 173, 3462 }, 3463 .delay = { 3464 .prepare = 110, 3465 .enable = 50, 3466 .unprepare = 550, 3467 }, 3468 }; 3469 3470 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3471 { /* 50 Hz */ 3472 .clock = 3000, 3473 .hdisplay = 240, 3474 .hsync_start = 240 + 58, 3475 .hsync_end = 240 + 58 + 1, 3476 .htotal = 240 + 58 + 1 + 1, 3477 .vdisplay = 160, 3478 .vsync_start = 160 + 24, 3479 .vsync_end = 160 + 24 + 10, 3480 .vtotal = 160 + 24 + 10 + 6, 3481 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3482 }, 3483 { /* 60 Hz */ 3484 .clock = 3000, 3485 .hdisplay = 240, 3486 .hsync_start = 240 + 8, 3487 .hsync_end = 240 + 8 + 1, 3488 .htotal = 240 + 8 + 1 + 1, 3489 .vdisplay = 160, 3490 .vsync_start = 160 + 24, 3491 .vsync_end = 160 + 24 + 10, 3492 .vtotal = 160 + 24 + 10 + 6, 3493 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3494 }, 3495 }; 3496 3497 static const struct panel_desc sharp_ls020b1dd01d = { 3498 .modes = sharp_ls020b1dd01d_modes, 3499 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3500 .bpc = 6, 3501 .size = { 3502 .width = 42, 3503 .height = 28, 3504 }, 3505 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3506 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3507 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3508 | DRM_BUS_FLAG_SHARP_SIGNALS, 3509 }; 3510 3511 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3512 .clock = 33300, 3513 .hdisplay = 800, 3514 .hsync_start = 800 + 1, 3515 .hsync_end = 800 + 1 + 64, 3516 .htotal = 800 + 1 + 64 + 64, 3517 .vdisplay = 480, 3518 .vsync_start = 480 + 1, 3519 .vsync_end = 480 + 1 + 23, 3520 .vtotal = 480 + 1 + 23 + 22, 3521 }; 3522 3523 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3524 .modes = &shelly_sca07010_bfn_lnn_mode, 3525 .num_modes = 1, 3526 .size = { 3527 .width = 152, 3528 .height = 91, 3529 }, 3530 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3531 }; 3532 3533 static const struct drm_display_mode starry_kr070pe2t_mode = { 3534 .clock = 33000, 3535 .hdisplay = 800, 3536 .hsync_start = 800 + 209, 3537 .hsync_end = 800 + 209 + 1, 3538 .htotal = 800 + 209 + 1 + 45, 3539 .vdisplay = 480, 3540 .vsync_start = 480 + 22, 3541 .vsync_end = 480 + 22 + 1, 3542 .vtotal = 480 + 22 + 1 + 22, 3543 }; 3544 3545 static const struct panel_desc starry_kr070pe2t = { 3546 .modes = &starry_kr070pe2t_mode, 3547 .num_modes = 1, 3548 .bpc = 8, 3549 .size = { 3550 .width = 152, 3551 .height = 86, 3552 }, 3553 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3554 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3555 .connector_type = DRM_MODE_CONNECTOR_DPI, 3556 }; 3557 3558 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3559 .clock = 147000, 3560 .hdisplay = 1920, 3561 .hsync_start = 1920 + 16, 3562 .hsync_end = 1920 + 16 + 16, 3563 .htotal = 1920 + 16 + 16 + 32, 3564 .vdisplay = 1200, 3565 .vsync_start = 1200 + 15, 3566 .vsync_end = 1200 + 15 + 2, 3567 .vtotal = 1200 + 15 + 2 + 18, 3568 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3569 }; 3570 3571 static const struct panel_desc starry_kr122ea0sra = { 3572 .modes = &starry_kr122ea0sra_mode, 3573 .num_modes = 1, 3574 .size = { 3575 .width = 263, 3576 .height = 164, 3577 }, 3578 .delay = { 3579 .prepare = 10 + 200, 3580 .enable = 50, 3581 .unprepare = 10 + 500, 3582 }, 3583 }; 3584 3585 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3586 .clock = 30000, 3587 .hdisplay = 800, 3588 .hsync_start = 800 + 39, 3589 .hsync_end = 800 + 39 + 47, 3590 .htotal = 800 + 39 + 47 + 39, 3591 .vdisplay = 480, 3592 .vsync_start = 480 + 13, 3593 .vsync_end = 480 + 13 + 2, 3594 .vtotal = 480 + 13 + 2 + 29, 3595 }; 3596 3597 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3598 .modes = &tfc_s9700rtwv43tr_01b_mode, 3599 .num_modes = 1, 3600 .bpc = 8, 3601 .size = { 3602 .width = 155, 3603 .height = 90, 3604 }, 3605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3606 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3607 }; 3608 3609 static const struct display_timing tianma_tm070jdhg30_timing = { 3610 .pixelclock = { 62600000, 68200000, 78100000 }, 3611 .hactive = { 1280, 1280, 1280 }, 3612 .hfront_porch = { 15, 64, 159 }, 3613 .hback_porch = { 5, 5, 5 }, 3614 .hsync_len = { 1, 1, 256 }, 3615 .vactive = { 800, 800, 800 }, 3616 .vfront_porch = { 3, 40, 99 }, 3617 .vback_porch = { 2, 2, 2 }, 3618 .vsync_len = { 1, 1, 128 }, 3619 .flags = DISPLAY_FLAGS_DE_HIGH, 3620 }; 3621 3622 static const struct panel_desc tianma_tm070jdhg30 = { 3623 .timings = &tianma_tm070jdhg30_timing, 3624 .num_timings = 1, 3625 .bpc = 8, 3626 .size = { 3627 .width = 151, 3628 .height = 95, 3629 }, 3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3631 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3632 }; 3633 3634 static const struct panel_desc tianma_tm070jvhg33 = { 3635 .timings = &tianma_tm070jdhg30_timing, 3636 .num_timings = 1, 3637 .bpc = 8, 3638 .size = { 3639 .width = 150, 3640 .height = 94, 3641 }, 3642 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3643 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3644 }; 3645 3646 static const struct display_timing tianma_tm070rvhg71_timing = { 3647 .pixelclock = { 27700000, 29200000, 39600000 }, 3648 .hactive = { 800, 800, 800 }, 3649 .hfront_porch = { 12, 40, 212 }, 3650 .hback_porch = { 88, 88, 88 }, 3651 .hsync_len = { 1, 1, 40 }, 3652 .vactive = { 480, 480, 480 }, 3653 .vfront_porch = { 1, 13, 88 }, 3654 .vback_porch = { 32, 32, 32 }, 3655 .vsync_len = { 1, 1, 3 }, 3656 .flags = DISPLAY_FLAGS_DE_HIGH, 3657 }; 3658 3659 static const struct panel_desc tianma_tm070rvhg71 = { 3660 .timings = &tianma_tm070rvhg71_timing, 3661 .num_timings = 1, 3662 .bpc = 8, 3663 .size = { 3664 .width = 154, 3665 .height = 86, 3666 }, 3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3668 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3669 }; 3670 3671 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3672 { 3673 .clock = 10000, 3674 .hdisplay = 320, 3675 .hsync_start = 320 + 50, 3676 .hsync_end = 320 + 50 + 6, 3677 .htotal = 320 + 50 + 6 + 38, 3678 .vdisplay = 240, 3679 .vsync_start = 240 + 3, 3680 .vsync_end = 240 + 3 + 1, 3681 .vtotal = 240 + 3 + 1 + 17, 3682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3683 }, 3684 }; 3685 3686 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3687 .modes = ti_nspire_cx_lcd_mode, 3688 .num_modes = 1, 3689 .bpc = 8, 3690 .size = { 3691 .width = 65, 3692 .height = 49, 3693 }, 3694 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3695 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3696 }; 3697 3698 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3699 { 3700 .clock = 10000, 3701 .hdisplay = 320, 3702 .hsync_start = 320 + 6, 3703 .hsync_end = 320 + 6 + 6, 3704 .htotal = 320 + 6 + 6 + 6, 3705 .vdisplay = 240, 3706 .vsync_start = 240 + 0, 3707 .vsync_end = 240 + 0 + 1, 3708 .vtotal = 240 + 0 + 1 + 0, 3709 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3710 }, 3711 }; 3712 3713 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3714 .modes = ti_nspire_classic_lcd_mode, 3715 .num_modes = 1, 3716 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3717 .bpc = 8, 3718 .size = { 3719 .width = 71, 3720 .height = 53, 3721 }, 3722 /* This is the grayscale bus format */ 3723 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3724 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3725 }; 3726 3727 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3728 .clock = 79500, 3729 .hdisplay = 1280, 3730 .hsync_start = 1280 + 192, 3731 .hsync_end = 1280 + 192 + 128, 3732 .htotal = 1280 + 192 + 128 + 64, 3733 .vdisplay = 768, 3734 .vsync_start = 768 + 20, 3735 .vsync_end = 768 + 20 + 7, 3736 .vtotal = 768 + 20 + 7 + 3, 3737 }; 3738 3739 static const struct panel_desc toshiba_lt089ac29000 = { 3740 .modes = &toshiba_lt089ac29000_mode, 3741 .num_modes = 1, 3742 .size = { 3743 .width = 194, 3744 .height = 116, 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3747 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3748 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3749 }; 3750 3751 static const struct drm_display_mode tpk_f07a_0102_mode = { 3752 .clock = 33260, 3753 .hdisplay = 800, 3754 .hsync_start = 800 + 40, 3755 .hsync_end = 800 + 40 + 128, 3756 .htotal = 800 + 40 + 128 + 88, 3757 .vdisplay = 480, 3758 .vsync_start = 480 + 10, 3759 .vsync_end = 480 + 10 + 2, 3760 .vtotal = 480 + 10 + 2 + 33, 3761 }; 3762 3763 static const struct panel_desc tpk_f07a_0102 = { 3764 .modes = &tpk_f07a_0102_mode, 3765 .num_modes = 1, 3766 .size = { 3767 .width = 152, 3768 .height = 91, 3769 }, 3770 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3771 }; 3772 3773 static const struct drm_display_mode tpk_f10a_0102_mode = { 3774 .clock = 45000, 3775 .hdisplay = 1024, 3776 .hsync_start = 1024 + 176, 3777 .hsync_end = 1024 + 176 + 5, 3778 .htotal = 1024 + 176 + 5 + 88, 3779 .vdisplay = 600, 3780 .vsync_start = 600 + 20, 3781 .vsync_end = 600 + 20 + 5, 3782 .vtotal = 600 + 20 + 5 + 25, 3783 }; 3784 3785 static const struct panel_desc tpk_f10a_0102 = { 3786 .modes = &tpk_f10a_0102_mode, 3787 .num_modes = 1, 3788 .size = { 3789 .width = 223, 3790 .height = 125, 3791 }, 3792 }; 3793 3794 static const struct display_timing urt_umsh_8596md_timing = { 3795 .pixelclock = { 33260000, 33260000, 33260000 }, 3796 .hactive = { 800, 800, 800 }, 3797 .hfront_porch = { 41, 41, 41 }, 3798 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3799 .hsync_len = { 71, 128, 128 }, 3800 .vactive = { 480, 480, 480 }, 3801 .vfront_porch = { 10, 10, 10 }, 3802 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3803 .vsync_len = { 2, 2, 2 }, 3804 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3805 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3806 }; 3807 3808 static const struct panel_desc urt_umsh_8596md_lvds = { 3809 .timings = &urt_umsh_8596md_timing, 3810 .num_timings = 1, 3811 .bpc = 6, 3812 .size = { 3813 .width = 152, 3814 .height = 91, 3815 }, 3816 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3817 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3818 }; 3819 3820 static const struct panel_desc urt_umsh_8596md_parallel = { 3821 .timings = &urt_umsh_8596md_timing, 3822 .num_timings = 1, 3823 .bpc = 6, 3824 .size = { 3825 .width = 152, 3826 .height = 91, 3827 }, 3828 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3829 }; 3830 3831 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3832 .clock = 33333, 3833 .hdisplay = 800, 3834 .hsync_start = 800 + 210, 3835 .hsync_end = 800 + 210 + 20, 3836 .htotal = 800 + 210 + 20 + 46, 3837 .vdisplay = 480, 3838 .vsync_start = 480 + 22, 3839 .vsync_end = 480 + 22 + 10, 3840 .vtotal = 480 + 22 + 10 + 23, 3841 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3842 }; 3843 3844 static const struct panel_desc vl050_8048nt_c01 = { 3845 .modes = &vl050_8048nt_c01_mode, 3846 .num_modes = 1, 3847 .bpc = 8, 3848 .size = { 3849 .width = 120, 3850 .height = 76, 3851 }, 3852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3853 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3854 }; 3855 3856 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3857 .clock = 6410, 3858 .hdisplay = 320, 3859 .hsync_start = 320 + 20, 3860 .hsync_end = 320 + 20 + 30, 3861 .htotal = 320 + 20 + 30 + 38, 3862 .vdisplay = 240, 3863 .vsync_start = 240 + 4, 3864 .vsync_end = 240 + 4 + 3, 3865 .vtotal = 240 + 4 + 3 + 15, 3866 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3867 }; 3868 3869 static const struct panel_desc winstar_wf35ltiacd = { 3870 .modes = &winstar_wf35ltiacd_mode, 3871 .num_modes = 1, 3872 .bpc = 8, 3873 .size = { 3874 .width = 70, 3875 .height = 53, 3876 }, 3877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3878 }; 3879 3880 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3881 .clock = 51200, 3882 .hdisplay = 1024, 3883 .hsync_start = 1024 + 100, 3884 .hsync_end = 1024 + 100 + 100, 3885 .htotal = 1024 + 100 + 100 + 120, 3886 .vdisplay = 600, 3887 .vsync_start = 600 + 10, 3888 .vsync_end = 600 + 10 + 10, 3889 .vtotal = 600 + 10 + 10 + 15, 3890 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3891 }; 3892 3893 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3894 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3895 .num_modes = 1, 3896 .bpc = 6, 3897 .size = { 3898 .width = 154, 3899 .height = 90, 3900 }, 3901 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3902 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3904 }; 3905 3906 static const struct drm_display_mode arm_rtsm_mode[] = { 3907 { 3908 .clock = 65000, 3909 .hdisplay = 1024, 3910 .hsync_start = 1024 + 24, 3911 .hsync_end = 1024 + 24 + 136, 3912 .htotal = 1024 + 24 + 136 + 160, 3913 .vdisplay = 768, 3914 .vsync_start = 768 + 3, 3915 .vsync_end = 768 + 3 + 6, 3916 .vtotal = 768 + 3 + 6 + 29, 3917 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3918 }, 3919 }; 3920 3921 static const struct panel_desc arm_rtsm = { 3922 .modes = arm_rtsm_mode, 3923 .num_modes = 1, 3924 .bpc = 8, 3925 .size = { 3926 .width = 400, 3927 .height = 300, 3928 }, 3929 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3930 }; 3931 3932 static const struct of_device_id platform_of_match[] = { 3933 { 3934 .compatible = "ampire,am-1280800n3tzqw-t00h", 3935 .data = &ire_am_1280800n3tzqw_t00h, 3936 }, { 3937 .compatible = "ampire,am-480272h3tmqw-t01h", 3938 .data = &ire_am_480272h3tmqw_t01h, 3939 }, { 3940 .compatible = "ampire,am800480r3tmqwa1h", 3941 .data = &ire_am800480r3tmqwa1h, 3942 }, { 3943 .compatible = "arm,rtsm-display", 3944 .data = &arm_rtsm, 3945 }, { 3946 .compatible = "armadeus,st0700-adapt", 3947 .data = &armadeus_st0700_adapt, 3948 }, { 3949 .compatible = "auo,b101aw03", 3950 .data = &auo_b101aw03, 3951 }, { 3952 .compatible = "auo,b101ean01", 3953 .data = &auo_b101ean01, 3954 }, { 3955 .compatible = "auo,b101xtn01", 3956 .data = &auo_b101xtn01, 3957 }, { 3958 .compatible = "auo,b116xa01", 3959 .data = &auo_b116xak01, 3960 }, { 3961 .compatible = "auo,b116xw03", 3962 .data = &auo_b116xw03, 3963 }, { 3964 .compatible = "auo,b133htn01", 3965 .data = &auo_b133htn01, 3966 }, { 3967 .compatible = "auo,b133xtn01", 3968 .data = &auo_b133xtn01, 3969 }, { 3970 .compatible = "auo,g070vvn01", 3971 .data = &auo_g070vvn01, 3972 }, { 3973 .compatible = "auo,g101evn010", 3974 .data = &auo_g101evn010, 3975 }, { 3976 .compatible = "auo,g104sn02", 3977 .data = &auo_g104sn02, 3978 }, { 3979 .compatible = "auo,g121ean01", 3980 .data = &auo_g121ean01, 3981 }, { 3982 .compatible = "auo,g133han01", 3983 .data = &auo_g133han01, 3984 }, { 3985 .compatible = "auo,g156xtn01", 3986 .data = &auo_g156xtn01, 3987 }, { 3988 .compatible = "auo,g185han01", 3989 .data = &auo_g185han01, 3990 }, { 3991 .compatible = "auo,g190ean01", 3992 .data = &auo_g190ean01, 3993 }, { 3994 .compatible = "auo,p320hvn03", 3995 .data = &auo_p320hvn03, 3996 }, { 3997 .compatible = "auo,t215hvn01", 3998 .data = &auo_t215hvn01, 3999 }, { 4000 .compatible = "avic,tm070ddh03", 4001 .data = &avic_tm070ddh03, 4002 }, { 4003 .compatible = "bananapi,s070wv20-ct16", 4004 .data = &bananapi_s070wv20_ct16, 4005 }, { 4006 .compatible = "boe,hv070wsa-100", 4007 .data = &boe_hv070wsa 4008 }, { 4009 .compatible = "boe,nv101wxmn51", 4010 .data = &boe_nv101wxmn51, 4011 }, { 4012 .compatible = "boe,nv133fhm-n61", 4013 .data = &boe_nv133fhm_n61, 4014 }, { 4015 .compatible = "boe,nv133fhm-n62", 4016 .data = &boe_nv133fhm_n61, 4017 }, { 4018 .compatible = "boe,nv140fhmn49", 4019 .data = &boe_nv140fhmn49, 4020 }, { 4021 .compatible = "cdtech,s043wq26h-ct7", 4022 .data = &cdtech_s043wq26h_ct7, 4023 }, { 4024 .compatible = "cdtech,s070pws19hp-fc21", 4025 .data = &cdtech_s070pws19hp_fc21, 4026 }, { 4027 .compatible = "cdtech,s070swv29hg-dc44", 4028 .data = &cdtech_s070swv29hg_dc44, 4029 }, { 4030 .compatible = "cdtech,s070wv95-ct16", 4031 .data = &cdtech_s070wv95_ct16, 4032 }, { 4033 .compatible = "chefree,ch101olhlwh-002", 4034 .data = &chefree_ch101olhlwh_002, 4035 }, { 4036 .compatible = "chunghwa,claa070wp03xg", 4037 .data = &chunghwa_claa070wp03xg, 4038 }, { 4039 .compatible = "chunghwa,claa101wa01a", 4040 .data = &chunghwa_claa101wa01a 4041 }, { 4042 .compatible = "chunghwa,claa101wb01", 4043 .data = &chunghwa_claa101wb01 4044 }, { 4045 .compatible = "dataimage,scf0700c48ggu18", 4046 .data = &dataimage_scf0700c48ggu18, 4047 }, { 4048 .compatible = "dlc,dlc0700yzg-1", 4049 .data = &dlc_dlc0700yzg_1, 4050 }, { 4051 .compatible = "dlc,dlc1010gig", 4052 .data = &dlc_dlc1010gig, 4053 }, { 4054 .compatible = "edt,et035012dm6", 4055 .data = &edt_et035012dm6, 4056 }, { 4057 .compatible = "edt,etm043080dh6gp", 4058 .data = &edt_etm043080dh6gp, 4059 }, { 4060 .compatible = "edt,etm0430g0dh6", 4061 .data = &edt_etm0430g0dh6, 4062 }, { 4063 .compatible = "edt,et057090dhu", 4064 .data = &edt_et057090dhu, 4065 }, { 4066 .compatible = "edt,et070080dh6", 4067 .data = &edt_etm0700g0dh6, 4068 }, { 4069 .compatible = "edt,etm0700g0dh6", 4070 .data = &edt_etm0700g0dh6, 4071 }, { 4072 .compatible = "edt,etm0700g0bdh6", 4073 .data = &edt_etm0700g0bdh6, 4074 }, { 4075 .compatible = "edt,etm0700g0edh6", 4076 .data = &edt_etm0700g0bdh6, 4077 }, { 4078 .compatible = "evervision,vgg804821", 4079 .data = &evervision_vgg804821, 4080 }, { 4081 .compatible = "foxlink,fl500wvr00-a0t", 4082 .data = &foxlink_fl500wvr00_a0t, 4083 }, { 4084 .compatible = "frida,frd350h54004", 4085 .data = &frida_frd350h54004, 4086 }, { 4087 .compatible = "friendlyarm,hd702e", 4088 .data = &friendlyarm_hd702e, 4089 }, { 4090 .compatible = "giantplus,gpg482739qs5", 4091 .data = &giantplus_gpg482739qs5 4092 }, { 4093 .compatible = "giantplus,gpm940b0", 4094 .data = &giantplus_gpm940b0, 4095 }, { 4096 .compatible = "hannstar,hsd070pww1", 4097 .data = &hannstar_hsd070pww1, 4098 }, { 4099 .compatible = "hannstar,hsd100pxn1", 4100 .data = &hannstar_hsd100pxn1, 4101 }, { 4102 .compatible = "hit,tx23d38vm0caa", 4103 .data = &hitachi_tx23d38vm0caa 4104 }, { 4105 .compatible = "innolux,at043tn24", 4106 .data = &innolux_at043tn24, 4107 }, { 4108 .compatible = "innolux,at070tn92", 4109 .data = &innolux_at070tn92, 4110 }, { 4111 .compatible = "innolux,g070y2-l01", 4112 .data = &innolux_g070y2_l01, 4113 }, { 4114 .compatible = "innolux,g101ice-l01", 4115 .data = &innolux_g101ice_l01 4116 }, { 4117 .compatible = "innolux,g121i1-l01", 4118 .data = &innolux_g121i1_l01 4119 }, { 4120 .compatible = "innolux,g121x1-l03", 4121 .data = &innolux_g121x1_l03, 4122 }, { 4123 .compatible = "innolux,n116bge", 4124 .data = &innolux_n116bge, 4125 }, { 4126 .compatible = "innolux,n156bge-l21", 4127 .data = &innolux_n156bge_l21, 4128 }, { 4129 .compatible = "innolux,p120zdg-bf1", 4130 .data = &innolux_p120zdg_bf1, 4131 }, { 4132 .compatible = "innolux,zj070na-01p", 4133 .data = &innolux_zj070na_01p, 4134 }, { 4135 .compatible = "ivo,m133nwf4-r0", 4136 .data = &ivo_m133nwf4_r0, 4137 }, { 4138 .compatible = "kingdisplay,kd116n21-30nv-a010", 4139 .data = &kingdisplay_kd116n21_30nv_a010, 4140 }, { 4141 .compatible = "koe,tx14d24vm1bpa", 4142 .data = &koe_tx14d24vm1bpa, 4143 }, { 4144 .compatible = "koe,tx26d202vm0bwa", 4145 .data = &koe_tx26d202vm0bwa, 4146 }, { 4147 .compatible = "koe,tx31d200vm0baa", 4148 .data = &koe_tx31d200vm0baa, 4149 }, { 4150 .compatible = "kyo,tcg121xglp", 4151 .data = &kyo_tcg121xglp, 4152 }, { 4153 .compatible = "lemaker,bl035-rgb-002", 4154 .data = &lemaker_bl035_rgb_002, 4155 }, { 4156 .compatible = "lg,lb070wv8", 4157 .data = &lg_lb070wv8, 4158 }, { 4159 .compatible = "lg,lp079qx1-sp0v", 4160 .data = &lg_lp079qx1_sp0v, 4161 }, { 4162 .compatible = "lg,lp097qx1-spa1", 4163 .data = &lg_lp097qx1_spa1, 4164 }, { 4165 .compatible = "lg,lp120up1", 4166 .data = &lg_lp120up1, 4167 }, { 4168 .compatible = "lg,lp129qe", 4169 .data = &lg_lp129qe, 4170 }, { 4171 .compatible = "logicpd,type28", 4172 .data = &logicpd_type_28, 4173 }, { 4174 .compatible = "logictechno,lt161010-2nhc", 4175 .data = &logictechno_lt161010_2nh, 4176 }, { 4177 .compatible = "logictechno,lt161010-2nhr", 4178 .data = &logictechno_lt161010_2nh, 4179 }, { 4180 .compatible = "logictechno,lt170410-2whc", 4181 .data = &logictechno_lt170410_2whc, 4182 }, { 4183 .compatible = "mitsubishi,aa070mc01-ca1", 4184 .data = &mitsubishi_aa070mc01, 4185 }, { 4186 .compatible = "nec,nl12880bc20-05", 4187 .data = &nec_nl12880bc20_05, 4188 }, { 4189 .compatible = "nec,nl4827hc19-05b", 4190 .data = &nec_nl4827hc19_05b, 4191 }, { 4192 .compatible = "netron-dy,e231732", 4193 .data = &netron_dy_e231732, 4194 }, { 4195 .compatible = "neweast,wjfh116008a", 4196 .data = &neweast_wjfh116008a, 4197 }, { 4198 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4199 .data = &newhaven_nhd_43_480272ef_atxl, 4200 }, { 4201 .compatible = "nlt,nl192108ac18-02d", 4202 .data = &nlt_nl192108ac18_02d, 4203 }, { 4204 .compatible = "nvd,9128", 4205 .data = &nvd_9128, 4206 }, { 4207 .compatible = "okaya,rs800480t-7x0gp", 4208 .data = &okaya_rs800480t_7x0gp, 4209 }, { 4210 .compatible = "olimex,lcd-olinuxino-43-ts", 4211 .data = &olimex_lcd_olinuxino_43ts, 4212 }, { 4213 .compatible = "ontat,yx700wv03", 4214 .data = &ontat_yx700wv03, 4215 }, { 4216 .compatible = "ortustech,com37h3m05dtc", 4217 .data = &ortustech_com37h3m, 4218 }, { 4219 .compatible = "ortustech,com37h3m99dtc", 4220 .data = &ortustech_com37h3m, 4221 }, { 4222 .compatible = "ortustech,com43h4m85ulc", 4223 .data = &ortustech_com43h4m85ulc, 4224 }, { 4225 .compatible = "osddisplays,osd070t1718-19ts", 4226 .data = &osddisplays_osd070t1718_19ts, 4227 }, { 4228 .compatible = "pda,91-00156-a0", 4229 .data = &pda_91_00156_a0, 4230 }, { 4231 .compatible = "powertip,ph800480t013-idf02", 4232 .data = &powertip_ph800480t013_idf02, 4233 }, { 4234 .compatible = "qiaodian,qd43003c0-40", 4235 .data = &qd43003c0_40, 4236 }, { 4237 .compatible = "rocktech,rk070er9427", 4238 .data = &rocktech_rk070er9427, 4239 }, { 4240 .compatible = "rocktech,rk101ii01d-ct", 4241 .data = &rocktech_rk101ii01d_ct, 4242 }, { 4243 .compatible = "samsung,lsn122dl01-c01", 4244 .data = &samsung_lsn122dl01_c01, 4245 }, { 4246 .compatible = "samsung,ltn101nt05", 4247 .data = &samsung_ltn101nt05, 4248 }, { 4249 .compatible = "samsung,ltn140at29-301", 4250 .data = &samsung_ltn140at29_301, 4251 }, { 4252 .compatible = "satoz,sat050at40h12r2", 4253 .data = &satoz_sat050at40h12r2, 4254 }, { 4255 .compatible = "sharp,ld-d5116z01b", 4256 .data = &sharp_ld_d5116z01b, 4257 }, { 4258 .compatible = "sharp,lq035q7db03", 4259 .data = &sharp_lq035q7db03, 4260 }, { 4261 .compatible = "sharp,lq070y3dg3b", 4262 .data = &sharp_lq070y3dg3b, 4263 }, { 4264 .compatible = "sharp,lq101k1ly04", 4265 .data = &sharp_lq101k1ly04, 4266 }, { 4267 .compatible = "sharp,lq123p1jx31", 4268 .data = &sharp_lq123p1jx31, 4269 }, { 4270 .compatible = "sharp,ls020b1dd01d", 4271 .data = &sharp_ls020b1dd01d, 4272 }, { 4273 .compatible = "shelly,sca07010-bfn-lnn", 4274 .data = &shelly_sca07010_bfn_lnn, 4275 }, { 4276 .compatible = "starry,kr070pe2t", 4277 .data = &starry_kr070pe2t, 4278 }, { 4279 .compatible = "starry,kr122ea0sra", 4280 .data = &starry_kr122ea0sra, 4281 }, { 4282 .compatible = "tfc,s9700rtwv43tr-01b", 4283 .data = &tfc_s9700rtwv43tr_01b, 4284 }, { 4285 .compatible = "tianma,tm070jdhg30", 4286 .data = &tianma_tm070jdhg30, 4287 }, { 4288 .compatible = "tianma,tm070jvhg33", 4289 .data = &tianma_tm070jvhg33, 4290 }, { 4291 .compatible = "tianma,tm070rvhg71", 4292 .data = &tianma_tm070rvhg71, 4293 }, { 4294 .compatible = "ti,nspire-cx-lcd-panel", 4295 .data = &ti_nspire_cx_lcd_panel, 4296 }, { 4297 .compatible = "ti,nspire-classic-lcd-panel", 4298 .data = &ti_nspire_classic_lcd_panel, 4299 }, { 4300 .compatible = "toshiba,lt089ac29000", 4301 .data = &toshiba_lt089ac29000, 4302 }, { 4303 .compatible = "tpk,f07a-0102", 4304 .data = &tpk_f07a_0102, 4305 }, { 4306 .compatible = "tpk,f10a-0102", 4307 .data = &tpk_f10a_0102, 4308 }, { 4309 .compatible = "urt,umsh-8596md-t", 4310 .data = &urt_umsh_8596md_parallel, 4311 }, { 4312 .compatible = "urt,umsh-8596md-1t", 4313 .data = &urt_umsh_8596md_parallel, 4314 }, { 4315 .compatible = "urt,umsh-8596md-7t", 4316 .data = &urt_umsh_8596md_parallel, 4317 }, { 4318 .compatible = "urt,umsh-8596md-11t", 4319 .data = &urt_umsh_8596md_lvds, 4320 }, { 4321 .compatible = "urt,umsh-8596md-19t", 4322 .data = &urt_umsh_8596md_lvds, 4323 }, { 4324 .compatible = "urt,umsh-8596md-20t", 4325 .data = &urt_umsh_8596md_parallel, 4326 }, { 4327 .compatible = "vxt,vl050-8048nt-c01", 4328 .data = &vl050_8048nt_c01, 4329 }, { 4330 .compatible = "winstar,wf35ltiacd", 4331 .data = &winstar_wf35ltiacd, 4332 }, { 4333 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4334 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4335 }, { 4336 /* Must be the last entry */ 4337 .compatible = "panel-dpi", 4338 .data = &panel_dpi, 4339 }, { 4340 /* sentinel */ 4341 } 4342 }; 4343 MODULE_DEVICE_TABLE(of, platform_of_match); 4344 4345 static int panel_simple_platform_probe(struct platform_device *pdev) 4346 { 4347 const struct of_device_id *id; 4348 4349 id = of_match_node(platform_of_match, pdev->dev.of_node); 4350 if (!id) 4351 return -ENODEV; 4352 4353 return panel_simple_probe(&pdev->dev, id->data); 4354 } 4355 4356 static int panel_simple_platform_remove(struct platform_device *pdev) 4357 { 4358 return panel_simple_remove(&pdev->dev); 4359 } 4360 4361 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4362 { 4363 panel_simple_shutdown(&pdev->dev); 4364 } 4365 4366 static struct platform_driver panel_simple_platform_driver = { 4367 .driver = { 4368 .name = "panel-simple", 4369 .of_match_table = platform_of_match, 4370 }, 4371 .probe = panel_simple_platform_probe, 4372 .remove = panel_simple_platform_remove, 4373 .shutdown = panel_simple_platform_shutdown, 4374 }; 4375 4376 struct panel_desc_dsi { 4377 struct panel_desc desc; 4378 4379 unsigned long flags; 4380 enum mipi_dsi_pixel_format format; 4381 unsigned int lanes; 4382 }; 4383 4384 static const struct drm_display_mode auo_b080uan01_mode = { 4385 .clock = 154500, 4386 .hdisplay = 1200, 4387 .hsync_start = 1200 + 62, 4388 .hsync_end = 1200 + 62 + 4, 4389 .htotal = 1200 + 62 + 4 + 62, 4390 .vdisplay = 1920, 4391 .vsync_start = 1920 + 9, 4392 .vsync_end = 1920 + 9 + 2, 4393 .vtotal = 1920 + 9 + 2 + 8, 4394 }; 4395 4396 static const struct panel_desc_dsi auo_b080uan01 = { 4397 .desc = { 4398 .modes = &auo_b080uan01_mode, 4399 .num_modes = 1, 4400 .bpc = 8, 4401 .size = { 4402 .width = 108, 4403 .height = 272, 4404 }, 4405 .connector_type = DRM_MODE_CONNECTOR_DSI, 4406 }, 4407 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4408 .format = MIPI_DSI_FMT_RGB888, 4409 .lanes = 4, 4410 }; 4411 4412 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4413 .clock = 160000, 4414 .hdisplay = 1200, 4415 .hsync_start = 1200 + 120, 4416 .hsync_end = 1200 + 120 + 20, 4417 .htotal = 1200 + 120 + 20 + 21, 4418 .vdisplay = 1920, 4419 .vsync_start = 1920 + 21, 4420 .vsync_end = 1920 + 21 + 3, 4421 .vtotal = 1920 + 21 + 3 + 18, 4422 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4423 }; 4424 4425 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4426 .desc = { 4427 .modes = &boe_tv080wum_nl0_mode, 4428 .num_modes = 1, 4429 .size = { 4430 .width = 107, 4431 .height = 172, 4432 }, 4433 .connector_type = DRM_MODE_CONNECTOR_DSI, 4434 }, 4435 .flags = MIPI_DSI_MODE_VIDEO | 4436 MIPI_DSI_MODE_VIDEO_BURST | 4437 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4438 .format = MIPI_DSI_FMT_RGB888, 4439 .lanes = 4, 4440 }; 4441 4442 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4443 .clock = 71000, 4444 .hdisplay = 800, 4445 .hsync_start = 800 + 32, 4446 .hsync_end = 800 + 32 + 1, 4447 .htotal = 800 + 32 + 1 + 57, 4448 .vdisplay = 1280, 4449 .vsync_start = 1280 + 28, 4450 .vsync_end = 1280 + 28 + 1, 4451 .vtotal = 1280 + 28 + 1 + 14, 4452 }; 4453 4454 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4455 .desc = { 4456 .modes = &lg_ld070wx3_sl01_mode, 4457 .num_modes = 1, 4458 .bpc = 8, 4459 .size = { 4460 .width = 94, 4461 .height = 151, 4462 }, 4463 .connector_type = DRM_MODE_CONNECTOR_DSI, 4464 }, 4465 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4466 .format = MIPI_DSI_FMT_RGB888, 4467 .lanes = 4, 4468 }; 4469 4470 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4471 .clock = 67000, 4472 .hdisplay = 720, 4473 .hsync_start = 720 + 12, 4474 .hsync_end = 720 + 12 + 4, 4475 .htotal = 720 + 12 + 4 + 112, 4476 .vdisplay = 1280, 4477 .vsync_start = 1280 + 8, 4478 .vsync_end = 1280 + 8 + 4, 4479 .vtotal = 1280 + 8 + 4 + 12, 4480 }; 4481 4482 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4483 .desc = { 4484 .modes = &lg_lh500wx1_sd03_mode, 4485 .num_modes = 1, 4486 .bpc = 8, 4487 .size = { 4488 .width = 62, 4489 .height = 110, 4490 }, 4491 .connector_type = DRM_MODE_CONNECTOR_DSI, 4492 }, 4493 .flags = MIPI_DSI_MODE_VIDEO, 4494 .format = MIPI_DSI_FMT_RGB888, 4495 .lanes = 4, 4496 }; 4497 4498 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4499 .clock = 157200, 4500 .hdisplay = 1920, 4501 .hsync_start = 1920 + 154, 4502 .hsync_end = 1920 + 154 + 16, 4503 .htotal = 1920 + 154 + 16 + 32, 4504 .vdisplay = 1200, 4505 .vsync_start = 1200 + 17, 4506 .vsync_end = 1200 + 17 + 2, 4507 .vtotal = 1200 + 17 + 2 + 16, 4508 }; 4509 4510 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4511 .desc = { 4512 .modes = &panasonic_vvx10f004b00_mode, 4513 .num_modes = 1, 4514 .bpc = 8, 4515 .size = { 4516 .width = 217, 4517 .height = 136, 4518 }, 4519 .connector_type = DRM_MODE_CONNECTOR_DSI, 4520 }, 4521 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4522 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4523 .format = MIPI_DSI_FMT_RGB888, 4524 .lanes = 4, 4525 }; 4526 4527 static const struct drm_display_mode lg_acx467akm_7_mode = { 4528 .clock = 150000, 4529 .hdisplay = 1080, 4530 .hsync_start = 1080 + 2, 4531 .hsync_end = 1080 + 2 + 2, 4532 .htotal = 1080 + 2 + 2 + 2, 4533 .vdisplay = 1920, 4534 .vsync_start = 1920 + 2, 4535 .vsync_end = 1920 + 2 + 2, 4536 .vtotal = 1920 + 2 + 2 + 2, 4537 }; 4538 4539 static const struct panel_desc_dsi lg_acx467akm_7 = { 4540 .desc = { 4541 .modes = &lg_acx467akm_7_mode, 4542 .num_modes = 1, 4543 .bpc = 8, 4544 .size = { 4545 .width = 62, 4546 .height = 110, 4547 }, 4548 .connector_type = DRM_MODE_CONNECTOR_DSI, 4549 }, 4550 .flags = 0, 4551 .format = MIPI_DSI_FMT_RGB888, 4552 .lanes = 4, 4553 }; 4554 4555 static const struct drm_display_mode osd101t2045_53ts_mode = { 4556 .clock = 154500, 4557 .hdisplay = 1920, 4558 .hsync_start = 1920 + 112, 4559 .hsync_end = 1920 + 112 + 16, 4560 .htotal = 1920 + 112 + 16 + 32, 4561 .vdisplay = 1200, 4562 .vsync_start = 1200 + 16, 4563 .vsync_end = 1200 + 16 + 2, 4564 .vtotal = 1200 + 16 + 2 + 16, 4565 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4566 }; 4567 4568 static const struct panel_desc_dsi osd101t2045_53ts = { 4569 .desc = { 4570 .modes = &osd101t2045_53ts_mode, 4571 .num_modes = 1, 4572 .bpc = 8, 4573 .size = { 4574 .width = 217, 4575 .height = 136, 4576 }, 4577 .connector_type = DRM_MODE_CONNECTOR_DSI, 4578 }, 4579 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4580 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4581 MIPI_DSI_MODE_EOT_PACKET, 4582 .format = MIPI_DSI_FMT_RGB888, 4583 .lanes = 4, 4584 }; 4585 4586 static const struct of_device_id dsi_of_match[] = { 4587 { 4588 .compatible = "auo,b080uan01", 4589 .data = &auo_b080uan01 4590 }, { 4591 .compatible = "boe,tv080wum-nl0", 4592 .data = &boe_tv080wum_nl0 4593 }, { 4594 .compatible = "lg,ld070wx3-sl01", 4595 .data = &lg_ld070wx3_sl01 4596 }, { 4597 .compatible = "lg,lh500wx1-sd03", 4598 .data = &lg_lh500wx1_sd03 4599 }, { 4600 .compatible = "panasonic,vvx10f004b00", 4601 .data = &panasonic_vvx10f004b00 4602 }, { 4603 .compatible = "lg,acx467akm-7", 4604 .data = &lg_acx467akm_7 4605 }, { 4606 .compatible = "osddisplays,osd101t2045-53ts", 4607 .data = &osd101t2045_53ts 4608 }, { 4609 /* sentinel */ 4610 } 4611 }; 4612 MODULE_DEVICE_TABLE(of, dsi_of_match); 4613 4614 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4615 { 4616 const struct panel_desc_dsi *desc; 4617 const struct of_device_id *id; 4618 int err; 4619 4620 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4621 if (!id) 4622 return -ENODEV; 4623 4624 desc = id->data; 4625 4626 err = panel_simple_probe(&dsi->dev, &desc->desc); 4627 if (err < 0) 4628 return err; 4629 4630 dsi->mode_flags = desc->flags; 4631 dsi->format = desc->format; 4632 dsi->lanes = desc->lanes; 4633 4634 err = mipi_dsi_attach(dsi); 4635 if (err) { 4636 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4637 4638 drm_panel_remove(&panel->base); 4639 } 4640 4641 return err; 4642 } 4643 4644 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4645 { 4646 int err; 4647 4648 err = mipi_dsi_detach(dsi); 4649 if (err < 0) 4650 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4651 4652 return panel_simple_remove(&dsi->dev); 4653 } 4654 4655 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4656 { 4657 panel_simple_shutdown(&dsi->dev); 4658 } 4659 4660 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4661 .driver = { 4662 .name = "panel-simple-dsi", 4663 .of_match_table = dsi_of_match, 4664 }, 4665 .probe = panel_simple_dsi_probe, 4666 .remove = panel_simple_dsi_remove, 4667 .shutdown = panel_simple_dsi_shutdown, 4668 }; 4669 4670 static int __init panel_simple_init(void) 4671 { 4672 int err; 4673 4674 err = platform_driver_register(&panel_simple_platform_driver); 4675 if (err < 0) 4676 return err; 4677 4678 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4679 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4680 if (err < 0) { 4681 platform_driver_unregister(&panel_simple_platform_driver); 4682 return err; 4683 } 4684 } 4685 4686 return 0; 4687 } 4688 module_init(panel_simple_init); 4689 4690 static void __exit panel_simple_exit(void) 4691 { 4692 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4693 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4694 4695 platform_driver_unregister(&panel_simple_platform_driver); 4696 } 4697 module_exit(panel_simple_exit); 4698 4699 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4700 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4701 MODULE_LICENSE("GPL and additional rights"); 4702