1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/regulator/consumer.h> 32 33 #include <video/display_timing.h> 34 #include <video/of_display_timing.h> 35 #include <video/videomode.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_device.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_panel.h> 41 42 /** 43 * struct panel_desc - Describes a simple panel. 44 */ 45 struct panel_desc { 46 /** 47 * @modes: Pointer to array of fixed modes appropriate for this panel. 48 * 49 * If only one mode then this can just be the address of the mode. 50 * NOTE: cannot be used with "timings" and also if this is specified 51 * then you cannot override the mode in the device tree. 52 */ 53 const struct drm_display_mode *modes; 54 55 /** @num_modes: Number of elements in modes array. */ 56 unsigned int num_modes; 57 58 /** 59 * @timings: Pointer to array of display timings 60 * 61 * NOTE: cannot be used with "modes" and also these will be used to 62 * validate a device tree override if one is present. 63 */ 64 const struct display_timing *timings; 65 66 /** @num_timings: Number of elements in timings array. */ 67 unsigned int num_timings; 68 69 /** @bpc: Bits per color. */ 70 unsigned int bpc; 71 72 /** @size: Structure containing the physical size of this panel. */ 73 struct { 74 /** 75 * @size.width: Width (in mm) of the active display area. 76 */ 77 unsigned int width; 78 79 /** 80 * @size.height: Height (in mm) of the active display area. 81 */ 82 unsigned int height; 83 } size; 84 85 /** @delay: Structure containing various delay values for this panel. */ 86 struct { 87 /** 88 * @delay.prepare: Time for the panel to become ready. 89 * 90 * The time (in milliseconds) that it takes for the panel to 91 * become ready and start receiving video data 92 */ 93 unsigned int prepare; 94 95 /** 96 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up. 97 * 98 * Add this to the prepare delay if we know Hot Plug Detect 99 * isn't used. 100 */ 101 unsigned int hpd_absent_delay; 102 103 /** 104 * @delay.prepare_to_enable: Time between prepare and enable. 105 * 106 * The minimum time, in milliseconds, that needs to have passed 107 * between when prepare finished and enable may begin. If at 108 * enable time less time has passed since prepare finished, 109 * the driver waits for the remaining time. 110 * 111 * If a fixed enable delay is also specified, we'll start 112 * counting before delaying for the fixed delay. 113 * 114 * If a fixed prepare delay is also specified, we won't start 115 * counting until after the fixed delay. We can't overlap this 116 * fixed delay with the min time because the fixed delay 117 * doesn't happen at the end of the function if a HPD GPIO was 118 * specified. 119 * 120 * In other words: 121 * prepare() 122 * ... 123 * // do fixed prepare delay 124 * // wait for HPD GPIO if applicable 125 * // start counting for prepare_to_enable 126 * 127 * enable() 128 * // do fixed enable delay 129 * // enforce prepare_to_enable min time 130 */ 131 unsigned int prepare_to_enable; 132 133 /** 134 * @delay.enable: Time for the panel to display a valid frame. 135 * 136 * The time (in milliseconds) that it takes for the panel to 137 * display the first valid frame after starting to receive 138 * video data. 139 */ 140 unsigned int enable; 141 142 /** 143 * @delay.disable: Time for the panel to turn the display off. 144 * 145 * The time (in milliseconds) that it takes for the panel to 146 * turn the display off (no content is visible). 147 */ 148 unsigned int disable; 149 150 /** 151 * @delay.unprepare: Time to power down completely. 152 * 153 * The time (in milliseconds) that it takes for the panel 154 * to power itself down completely. 155 * 156 * This time is used to prevent a future "prepare" from 157 * starting until at least this many milliseconds has passed. 158 * If at prepare time less time has passed since unprepare 159 * finished, the driver waits for the remaining time. 160 */ 161 unsigned int unprepare; 162 } delay; 163 164 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 165 u32 bus_format; 166 167 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 168 u32 bus_flags; 169 170 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 171 int connector_type; 172 }; 173 174 struct panel_simple { 175 struct drm_panel base; 176 bool enabled; 177 bool no_hpd; 178 179 bool prepared; 180 181 ktime_t prepared_time; 182 ktime_t unprepared_time; 183 184 const struct panel_desc *desc; 185 186 struct regulator *supply; 187 struct i2c_adapter *ddc; 188 189 struct gpio_desc *enable_gpio; 190 struct gpio_desc *hpd_gpio; 191 192 struct edid *edid; 193 194 struct drm_display_mode override_mode; 195 196 enum drm_panel_orientation orientation; 197 }; 198 199 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 200 { 201 return container_of(panel, struct panel_simple, base); 202 } 203 204 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_timings; i++) { 211 const struct display_timing *dt = &panel->desc->timings[i]; 212 struct videomode vm; 213 214 videomode_from_timing(dt, &vm); 215 mode = drm_mode_create(connector->dev); 216 if (!mode) { 217 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 218 dt->hactive.typ, dt->vactive.typ); 219 continue; 220 } 221 222 drm_display_mode_from_videomode(&vm, mode); 223 224 mode->type |= DRM_MODE_TYPE_DRIVER; 225 226 if (panel->desc->num_timings == 1) 227 mode->type |= DRM_MODE_TYPE_PREFERRED; 228 229 drm_mode_probed_add(connector, mode); 230 num++; 231 } 232 233 return num; 234 } 235 236 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 237 struct drm_connector *connector) 238 { 239 struct drm_display_mode *mode; 240 unsigned int i, num = 0; 241 242 for (i = 0; i < panel->desc->num_modes; i++) { 243 const struct drm_display_mode *m = &panel->desc->modes[i]; 244 245 mode = drm_mode_duplicate(connector->dev, m); 246 if (!mode) { 247 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 248 m->hdisplay, m->vdisplay, 249 drm_mode_vrefresh(m)); 250 continue; 251 } 252 253 mode->type |= DRM_MODE_TYPE_DRIVER; 254 255 if (panel->desc->num_modes == 1) 256 mode->type |= DRM_MODE_TYPE_PREFERRED; 257 258 drm_mode_set_name(mode); 259 260 drm_mode_probed_add(connector, mode); 261 num++; 262 } 263 264 return num; 265 } 266 267 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 268 struct drm_connector *connector) 269 { 270 struct drm_display_mode *mode; 271 bool has_override = panel->override_mode.type; 272 unsigned int num = 0; 273 274 if (!panel->desc) 275 return 0; 276 277 if (has_override) { 278 mode = drm_mode_duplicate(connector->dev, 279 &panel->override_mode); 280 if (mode) { 281 drm_mode_probed_add(connector, mode); 282 num = 1; 283 } else { 284 dev_err(panel->base.dev, "failed to add override mode\n"); 285 } 286 } 287 288 /* Only add timings if override was not there or failed to validate */ 289 if (num == 0 && panel->desc->num_timings) 290 num = panel_simple_get_timings_modes(panel, connector); 291 292 /* 293 * Only add fixed modes if timings/override added no mode. 294 * 295 * We should only ever have either the display timings specified 296 * or a fixed mode. Anything else is rather bogus. 297 */ 298 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 299 if (num == 0) 300 num = panel_simple_get_display_modes(panel, connector); 301 302 connector->display_info.bpc = panel->desc->bpc; 303 connector->display_info.width_mm = panel->desc->size.width; 304 connector->display_info.height_mm = panel->desc->size.height; 305 if (panel->desc->bus_format) 306 drm_display_info_set_bus_formats(&connector->display_info, 307 &panel->desc->bus_format, 1); 308 connector->display_info.bus_flags = panel->desc->bus_flags; 309 310 return num; 311 } 312 313 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 314 { 315 ktime_t now_ktime, min_ktime; 316 317 if (!min_ms) 318 return; 319 320 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 321 now_ktime = ktime_get(); 322 323 if (ktime_before(now_ktime, min_ktime)) 324 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 325 } 326 327 static int panel_simple_disable(struct drm_panel *panel) 328 { 329 struct panel_simple *p = to_panel_simple(panel); 330 331 if (!p->enabled) 332 return 0; 333 334 if (p->desc->delay.disable) 335 msleep(p->desc->delay.disable); 336 337 p->enabled = false; 338 339 return 0; 340 } 341 342 static int panel_simple_suspend(struct device *dev) 343 { 344 struct panel_simple *p = dev_get_drvdata(dev); 345 346 gpiod_set_value_cansleep(p->enable_gpio, 0); 347 regulator_disable(p->supply); 348 p->unprepared_time = ktime_get(); 349 350 kfree(p->edid); 351 p->edid = NULL; 352 353 return 0; 354 } 355 356 static int panel_simple_unprepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Unpreparing when already unprepared is a no-op */ 362 if (!p->prepared) 363 return 0; 364 365 pm_runtime_mark_last_busy(panel->dev); 366 ret = pm_runtime_put_autosuspend(panel->dev); 367 if (ret < 0) 368 return ret; 369 p->prepared = false; 370 371 return 0; 372 } 373 374 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p) 375 { 376 int err; 377 378 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 379 if (IS_ERR(p->hpd_gpio)) { 380 err = PTR_ERR(p->hpd_gpio); 381 382 if (err != -EPROBE_DEFER) 383 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 384 385 return err; 386 } 387 388 return 0; 389 } 390 391 static int panel_simple_prepare_once(struct panel_simple *p) 392 { 393 struct device *dev = p->base.dev; 394 unsigned int delay; 395 int err; 396 int hpd_asserted; 397 unsigned long hpd_wait_us; 398 399 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 400 401 err = regulator_enable(p->supply); 402 if (err < 0) { 403 dev_err(dev, "failed to enable supply: %d\n", err); 404 return err; 405 } 406 407 gpiod_set_value_cansleep(p->enable_gpio, 1); 408 409 delay = p->desc->delay.prepare; 410 if (p->no_hpd) 411 delay += p->desc->delay.hpd_absent_delay; 412 if (delay) 413 msleep(delay); 414 415 if (p->hpd_gpio) { 416 if (p->desc->delay.hpd_absent_delay) 417 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL; 418 else 419 hpd_wait_us = 2000000; 420 421 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 422 hpd_asserted, hpd_asserted, 423 1000, hpd_wait_us); 424 if (hpd_asserted < 0) 425 err = hpd_asserted; 426 427 if (err) { 428 if (err != -ETIMEDOUT) 429 dev_err(dev, 430 "error waiting for hpd GPIO: %d\n", err); 431 goto error; 432 } 433 } 434 435 p->prepared_time = ktime_get(); 436 437 return 0; 438 439 error: 440 gpiod_set_value_cansleep(p->enable_gpio, 0); 441 regulator_disable(p->supply); 442 p->unprepared_time = ktime_get(); 443 444 return err; 445 } 446 447 /* 448 * Some panels simply don't always come up and need to be power cycled to 449 * work properly. We'll allow for a handful of retries. 450 */ 451 #define MAX_PANEL_PREPARE_TRIES 5 452 453 static int panel_simple_resume(struct device *dev) 454 { 455 struct panel_simple *p = dev_get_drvdata(dev); 456 int ret; 457 int try; 458 459 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) { 460 ret = panel_simple_prepare_once(p); 461 if (ret != -ETIMEDOUT) 462 break; 463 } 464 465 if (ret == -ETIMEDOUT) 466 dev_err(dev, "Prepare timeout after %d tries\n", try); 467 else if (try) 468 dev_warn(dev, "Prepare needed %d retries\n", try); 469 470 return ret; 471 } 472 473 static int panel_simple_prepare(struct drm_panel *panel) 474 { 475 struct panel_simple *p = to_panel_simple(panel); 476 int ret; 477 478 /* Preparing when already prepared is a no-op */ 479 if (p->prepared) 480 return 0; 481 482 ret = pm_runtime_get_sync(panel->dev); 483 if (ret < 0) { 484 pm_runtime_put_autosuspend(panel->dev); 485 return ret; 486 } 487 488 p->prepared = true; 489 490 return 0; 491 } 492 493 static int panel_simple_enable(struct drm_panel *panel) 494 { 495 struct panel_simple *p = to_panel_simple(panel); 496 497 if (p->enabled) 498 return 0; 499 500 if (p->desc->delay.enable) 501 msleep(p->desc->delay.enable); 502 503 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable); 504 505 p->enabled = true; 506 507 return 0; 508 } 509 510 static int panel_simple_get_modes(struct drm_panel *panel, 511 struct drm_connector *connector) 512 { 513 struct panel_simple *p = to_panel_simple(panel); 514 int num = 0; 515 516 /* probe EDID if a DDC bus is available */ 517 if (p->ddc) { 518 pm_runtime_get_sync(panel->dev); 519 520 if (!p->edid) 521 p->edid = drm_get_edid(connector, p->ddc); 522 523 if (p->edid) 524 num += drm_add_edid_modes(connector, p->edid); 525 526 pm_runtime_mark_last_busy(panel->dev); 527 pm_runtime_put_autosuspend(panel->dev); 528 } 529 530 /* add hard-coded panel modes */ 531 num += panel_simple_get_non_edid_modes(p, connector); 532 533 /* set up connector's "panel orientation" property */ 534 drm_connector_set_panel_orientation(connector, p->orientation); 535 536 return num; 537 } 538 539 static int panel_simple_get_timings(struct drm_panel *panel, 540 unsigned int num_timings, 541 struct display_timing *timings) 542 { 543 struct panel_simple *p = to_panel_simple(panel); 544 unsigned int i; 545 546 if (p->desc->num_timings < num_timings) 547 num_timings = p->desc->num_timings; 548 549 if (timings) 550 for (i = 0; i < num_timings; i++) 551 timings[i] = p->desc->timings[i]; 552 553 return p->desc->num_timings; 554 } 555 556 static const struct drm_panel_funcs panel_simple_funcs = { 557 .disable = panel_simple_disable, 558 .unprepare = panel_simple_unprepare, 559 .prepare = panel_simple_prepare, 560 .enable = panel_simple_enable, 561 .get_modes = panel_simple_get_modes, 562 .get_timings = panel_simple_get_timings, 563 }; 564 565 static struct panel_desc panel_dpi; 566 567 static int panel_dpi_probe(struct device *dev, 568 struct panel_simple *panel) 569 { 570 struct display_timing *timing; 571 const struct device_node *np; 572 struct panel_desc *desc; 573 unsigned int bus_flags; 574 struct videomode vm; 575 int ret; 576 577 np = dev->of_node; 578 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 579 if (!desc) 580 return -ENOMEM; 581 582 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 583 if (!timing) 584 return -ENOMEM; 585 586 ret = of_get_display_timing(np, "panel-timing", timing); 587 if (ret < 0) { 588 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 589 np); 590 return ret; 591 } 592 593 desc->timings = timing; 594 desc->num_timings = 1; 595 596 of_property_read_u32(np, "width-mm", &desc->size.width); 597 of_property_read_u32(np, "height-mm", &desc->size.height); 598 599 /* Extract bus_flags from display_timing */ 600 bus_flags = 0; 601 vm.flags = timing->flags; 602 drm_bus_flags_from_videomode(&vm, &bus_flags); 603 desc->bus_flags = bus_flags; 604 605 /* We do not know the connector for the DT node, so guess it */ 606 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 607 608 panel->desc = desc; 609 610 return 0; 611 } 612 613 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 614 (to_check->field.typ >= bounds->field.min && \ 615 to_check->field.typ <= bounds->field.max) 616 static void panel_simple_parse_panel_timing_node(struct device *dev, 617 struct panel_simple *panel, 618 const struct display_timing *ot) 619 { 620 const struct panel_desc *desc = panel->desc; 621 struct videomode vm; 622 unsigned int i; 623 624 if (WARN_ON(desc->num_modes)) { 625 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 626 return; 627 } 628 if (WARN_ON(!desc->num_timings)) { 629 dev_err(dev, "Reject override mode: no timings specified\n"); 630 return; 631 } 632 633 for (i = 0; i < panel->desc->num_timings; i++) { 634 const struct display_timing *dt = &panel->desc->timings[i]; 635 636 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 637 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 638 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 639 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 640 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 641 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 642 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 643 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 644 continue; 645 646 if (ot->flags != dt->flags) 647 continue; 648 649 videomode_from_timing(ot, &vm); 650 drm_display_mode_from_videomode(&vm, &panel->override_mode); 651 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 652 DRM_MODE_TYPE_PREFERRED; 653 break; 654 } 655 656 if (WARN_ON(!panel->override_mode.type)) 657 dev_err(dev, "Reject override mode: No display_timing found\n"); 658 } 659 660 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 661 { 662 struct panel_simple *panel; 663 struct display_timing dt; 664 struct device_node *ddc; 665 int connector_type; 666 u32 bus_flags; 667 int err; 668 669 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 670 if (!panel) 671 return -ENOMEM; 672 673 panel->enabled = false; 674 panel->prepared_time = 0; 675 panel->desc = desc; 676 677 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 678 if (!panel->no_hpd) { 679 err = panel_simple_get_hpd_gpio(dev, panel); 680 if (err) 681 return err; 682 } 683 684 panel->supply = devm_regulator_get(dev, "power"); 685 if (IS_ERR(panel->supply)) 686 return PTR_ERR(panel->supply); 687 688 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 689 GPIOD_OUT_LOW); 690 if (IS_ERR(panel->enable_gpio)) { 691 err = PTR_ERR(panel->enable_gpio); 692 if (err != -EPROBE_DEFER) 693 dev_err(dev, "failed to request GPIO: %d\n", err); 694 return err; 695 } 696 697 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 698 if (err) { 699 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 700 return err; 701 } 702 703 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 704 if (ddc) { 705 panel->ddc = of_find_i2c_adapter_by_node(ddc); 706 of_node_put(ddc); 707 708 if (!panel->ddc) 709 return -EPROBE_DEFER; 710 } 711 712 if (desc == &panel_dpi) { 713 /* Handle the generic panel-dpi binding */ 714 err = panel_dpi_probe(dev, panel); 715 if (err) 716 goto free_ddc; 717 } else { 718 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 719 panel_simple_parse_panel_timing_node(dev, panel, &dt); 720 } 721 722 connector_type = desc->connector_type; 723 /* Catch common mistakes for panels. */ 724 switch (connector_type) { 725 case 0: 726 dev_warn(dev, "Specify missing connector_type\n"); 727 connector_type = DRM_MODE_CONNECTOR_DPI; 728 break; 729 case DRM_MODE_CONNECTOR_LVDS: 730 WARN_ON(desc->bus_flags & 731 ~(DRM_BUS_FLAG_DE_LOW | 732 DRM_BUS_FLAG_DE_HIGH | 733 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 734 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 735 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 736 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 737 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 738 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 739 desc->bpc != 6); 740 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 741 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 742 desc->bpc != 8); 743 break; 744 case DRM_MODE_CONNECTOR_eDP: 745 if (desc->bus_format == 0) 746 dev_warn(dev, "Specify missing bus_format\n"); 747 if (desc->bpc != 6 && desc->bpc != 8) 748 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 749 break; 750 case DRM_MODE_CONNECTOR_DSI: 751 if (desc->bpc != 6 && desc->bpc != 8) 752 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 753 break; 754 case DRM_MODE_CONNECTOR_DPI: 755 bus_flags = DRM_BUS_FLAG_DE_LOW | 756 DRM_BUS_FLAG_DE_HIGH | 757 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 758 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 759 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 760 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 761 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 762 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 763 if (desc->bus_flags & ~bus_flags) 764 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 765 if (!(desc->bus_flags & bus_flags)) 766 dev_warn(dev, "Specify missing bus_flags\n"); 767 if (desc->bus_format == 0) 768 dev_warn(dev, "Specify missing bus_format\n"); 769 if (desc->bpc != 6 && desc->bpc != 8) 770 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 771 break; 772 default: 773 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 774 connector_type = DRM_MODE_CONNECTOR_DPI; 775 break; 776 } 777 778 dev_set_drvdata(dev, panel); 779 780 /* 781 * We use runtime PM for prepare / unprepare since those power the panel 782 * on and off and those can be very slow operations. This is important 783 * to optimize powering the panel on briefly to read the EDID before 784 * fully enabling the panel. 785 */ 786 pm_runtime_enable(dev); 787 pm_runtime_set_autosuspend_delay(dev, 1000); 788 pm_runtime_use_autosuspend(dev); 789 790 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 791 792 err = drm_panel_of_backlight(&panel->base); 793 if (err) 794 goto disable_pm_runtime; 795 796 drm_panel_add(&panel->base); 797 798 return 0; 799 800 disable_pm_runtime: 801 pm_runtime_dont_use_autosuspend(dev); 802 pm_runtime_disable(dev); 803 free_ddc: 804 if (panel->ddc) 805 put_device(&panel->ddc->dev); 806 807 return err; 808 } 809 810 static int panel_simple_remove(struct device *dev) 811 { 812 struct panel_simple *panel = dev_get_drvdata(dev); 813 814 drm_panel_remove(&panel->base); 815 drm_panel_disable(&panel->base); 816 drm_panel_unprepare(&panel->base); 817 818 pm_runtime_dont_use_autosuspend(dev); 819 pm_runtime_disable(dev); 820 if (panel->ddc) 821 put_device(&panel->ddc->dev); 822 823 return 0; 824 } 825 826 static void panel_simple_shutdown(struct device *dev) 827 { 828 struct panel_simple *panel = dev_get_drvdata(dev); 829 830 drm_panel_disable(&panel->base); 831 drm_panel_unprepare(&panel->base); 832 } 833 834 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 835 .clock = 71100, 836 .hdisplay = 1280, 837 .hsync_start = 1280 + 40, 838 .hsync_end = 1280 + 40 + 80, 839 .htotal = 1280 + 40 + 80 + 40, 840 .vdisplay = 800, 841 .vsync_start = 800 + 3, 842 .vsync_end = 800 + 3 + 10, 843 .vtotal = 800 + 3 + 10 + 10, 844 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 845 }; 846 847 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 848 .modes = &ire_am_1280800n3tzqw_t00h_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 217, 853 .height = 136, 854 }, 855 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 856 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 857 .connector_type = DRM_MODE_CONNECTOR_LVDS, 858 }; 859 860 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 861 .clock = 9000, 862 .hdisplay = 480, 863 .hsync_start = 480 + 2, 864 .hsync_end = 480 + 2 + 41, 865 .htotal = 480 + 2 + 41 + 2, 866 .vdisplay = 272, 867 .vsync_start = 272 + 2, 868 .vsync_end = 272 + 2 + 10, 869 .vtotal = 272 + 2 + 10 + 2, 870 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 871 }; 872 873 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 874 .modes = &ire_am_480272h3tmqw_t01h_mode, 875 .num_modes = 1, 876 .bpc = 8, 877 .size = { 878 .width = 105, 879 .height = 67, 880 }, 881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 882 }; 883 884 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 885 .clock = 33333, 886 .hdisplay = 800, 887 .hsync_start = 800 + 0, 888 .hsync_end = 800 + 0 + 255, 889 .htotal = 800 + 0 + 255 + 0, 890 .vdisplay = 480, 891 .vsync_start = 480 + 2, 892 .vsync_end = 480 + 2 + 45, 893 .vtotal = 480 + 2 + 45 + 0, 894 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 895 }; 896 897 static const struct panel_desc ampire_am800480r3tmqwa1h = { 898 .modes = &ire_am800480r3tmqwa1h_mode, 899 .num_modes = 1, 900 .bpc = 6, 901 .size = { 902 .width = 152, 903 .height = 91, 904 }, 905 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 906 }; 907 908 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 909 .pixelclock = { 26400000, 33300000, 46800000 }, 910 .hactive = { 800, 800, 800 }, 911 .hfront_porch = { 16, 210, 354 }, 912 .hback_porch = { 45, 36, 6 }, 913 .hsync_len = { 1, 10, 40 }, 914 .vactive = { 480, 480, 480 }, 915 .vfront_porch = { 7, 22, 147 }, 916 .vback_porch = { 22, 13, 3 }, 917 .vsync_len = { 1, 10, 20 }, 918 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 919 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 920 }; 921 922 static const struct panel_desc armadeus_st0700_adapt = { 923 .timings = &santek_st0700i5y_rbslw_f_timing, 924 .num_timings = 1, 925 .bpc = 6, 926 .size = { 927 .width = 154, 928 .height = 86, 929 }, 930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 932 }; 933 934 static const struct drm_display_mode auo_b101aw03_mode = { 935 .clock = 51450, 936 .hdisplay = 1024, 937 .hsync_start = 1024 + 156, 938 .hsync_end = 1024 + 156 + 8, 939 .htotal = 1024 + 156 + 8 + 156, 940 .vdisplay = 600, 941 .vsync_start = 600 + 16, 942 .vsync_end = 600 + 16 + 6, 943 .vtotal = 600 + 16 + 6 + 16, 944 }; 945 946 static const struct panel_desc auo_b101aw03 = { 947 .modes = &auo_b101aw03_mode, 948 .num_modes = 1, 949 .bpc = 6, 950 .size = { 951 .width = 223, 952 .height = 125, 953 }, 954 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 955 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 956 .connector_type = DRM_MODE_CONNECTOR_LVDS, 957 }; 958 959 static const struct display_timing auo_b101ean01_timing = { 960 .pixelclock = { 65300000, 72500000, 75000000 }, 961 .hactive = { 1280, 1280, 1280 }, 962 .hfront_porch = { 18, 119, 119 }, 963 .hback_porch = { 21, 21, 21 }, 964 .hsync_len = { 32, 32, 32 }, 965 .vactive = { 800, 800, 800 }, 966 .vfront_porch = { 4, 4, 4 }, 967 .vback_porch = { 8, 8, 8 }, 968 .vsync_len = { 18, 20, 20 }, 969 }; 970 971 static const struct panel_desc auo_b101ean01 = { 972 .timings = &auo_b101ean01_timing, 973 .num_timings = 1, 974 .bpc = 6, 975 .size = { 976 .width = 217, 977 .height = 136, 978 }, 979 }; 980 981 static const struct drm_display_mode auo_b101xtn01_mode = { 982 .clock = 72000, 983 .hdisplay = 1366, 984 .hsync_start = 1366 + 20, 985 .hsync_end = 1366 + 20 + 70, 986 .htotal = 1366 + 20 + 70, 987 .vdisplay = 768, 988 .vsync_start = 768 + 14, 989 .vsync_end = 768 + 14 + 42, 990 .vtotal = 768 + 14 + 42, 991 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 992 }; 993 994 static const struct panel_desc auo_b101xtn01 = { 995 .modes = &auo_b101xtn01_mode, 996 .num_modes = 1, 997 .bpc = 6, 998 .size = { 999 .width = 223, 1000 .height = 125, 1001 }, 1002 }; 1003 1004 static const struct drm_display_mode auo_b116xak01_mode = { 1005 .clock = 69300, 1006 .hdisplay = 1366, 1007 .hsync_start = 1366 + 48, 1008 .hsync_end = 1366 + 48 + 32, 1009 .htotal = 1366 + 48 + 32 + 10, 1010 .vdisplay = 768, 1011 .vsync_start = 768 + 4, 1012 .vsync_end = 768 + 4 + 6, 1013 .vtotal = 768 + 4 + 6 + 15, 1014 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1015 }; 1016 1017 static const struct panel_desc auo_b116xak01 = { 1018 .modes = &auo_b116xak01_mode, 1019 .num_modes = 1, 1020 .bpc = 6, 1021 .size = { 1022 .width = 256, 1023 .height = 144, 1024 }, 1025 .delay = { 1026 .hpd_absent_delay = 200, 1027 }, 1028 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1029 .connector_type = DRM_MODE_CONNECTOR_eDP, 1030 }; 1031 1032 static const struct drm_display_mode auo_b116xw03_mode = { 1033 .clock = 70589, 1034 .hdisplay = 1366, 1035 .hsync_start = 1366 + 40, 1036 .hsync_end = 1366 + 40 + 40, 1037 .htotal = 1366 + 40 + 40 + 32, 1038 .vdisplay = 768, 1039 .vsync_start = 768 + 10, 1040 .vsync_end = 768 + 10 + 12, 1041 .vtotal = 768 + 10 + 12 + 6, 1042 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1043 }; 1044 1045 static const struct panel_desc auo_b116xw03 = { 1046 .modes = &auo_b116xw03_mode, 1047 .num_modes = 1, 1048 .bpc = 6, 1049 .size = { 1050 .width = 256, 1051 .height = 144, 1052 }, 1053 .delay = { 1054 .enable = 400, 1055 }, 1056 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 1057 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1058 .connector_type = DRM_MODE_CONNECTOR_eDP, 1059 }; 1060 1061 static const struct drm_display_mode auo_b133xtn01_mode = { 1062 .clock = 69500, 1063 .hdisplay = 1366, 1064 .hsync_start = 1366 + 48, 1065 .hsync_end = 1366 + 48 + 32, 1066 .htotal = 1366 + 48 + 32 + 20, 1067 .vdisplay = 768, 1068 .vsync_start = 768 + 3, 1069 .vsync_end = 768 + 3 + 6, 1070 .vtotal = 768 + 3 + 6 + 13, 1071 }; 1072 1073 static const struct panel_desc auo_b133xtn01 = { 1074 .modes = &auo_b133xtn01_mode, 1075 .num_modes = 1, 1076 .bpc = 6, 1077 .size = { 1078 .width = 293, 1079 .height = 165, 1080 }, 1081 }; 1082 1083 static const struct drm_display_mode auo_b133htn01_mode = { 1084 .clock = 150660, 1085 .hdisplay = 1920, 1086 .hsync_start = 1920 + 172, 1087 .hsync_end = 1920 + 172 + 80, 1088 .htotal = 1920 + 172 + 80 + 60, 1089 .vdisplay = 1080, 1090 .vsync_start = 1080 + 25, 1091 .vsync_end = 1080 + 25 + 10, 1092 .vtotal = 1080 + 25 + 10 + 10, 1093 }; 1094 1095 static const struct panel_desc auo_b133htn01 = { 1096 .modes = &auo_b133htn01_mode, 1097 .num_modes = 1, 1098 .bpc = 6, 1099 .size = { 1100 .width = 293, 1101 .height = 165, 1102 }, 1103 .delay = { 1104 .prepare = 105, 1105 .enable = 20, 1106 .unprepare = 50, 1107 }, 1108 }; 1109 1110 static const struct display_timing auo_g070vvn01_timings = { 1111 .pixelclock = { 33300000, 34209000, 45000000 }, 1112 .hactive = { 800, 800, 800 }, 1113 .hfront_porch = { 20, 40, 200 }, 1114 .hback_porch = { 87, 40, 1 }, 1115 .hsync_len = { 1, 48, 87 }, 1116 .vactive = { 480, 480, 480 }, 1117 .vfront_porch = { 5, 13, 200 }, 1118 .vback_porch = { 31, 31, 29 }, 1119 .vsync_len = { 1, 1, 3 }, 1120 }; 1121 1122 static const struct panel_desc auo_g070vvn01 = { 1123 .timings = &auo_g070vvn01_timings, 1124 .num_timings = 1, 1125 .bpc = 8, 1126 .size = { 1127 .width = 152, 1128 .height = 91, 1129 }, 1130 .delay = { 1131 .prepare = 200, 1132 .enable = 50, 1133 .disable = 50, 1134 .unprepare = 1000, 1135 }, 1136 }; 1137 1138 static const struct drm_display_mode auo_g101evn010_mode = { 1139 .clock = 68930, 1140 .hdisplay = 1280, 1141 .hsync_start = 1280 + 82, 1142 .hsync_end = 1280 + 82 + 2, 1143 .htotal = 1280 + 82 + 2 + 84, 1144 .vdisplay = 800, 1145 .vsync_start = 800 + 8, 1146 .vsync_end = 800 + 8 + 2, 1147 .vtotal = 800 + 8 + 2 + 6, 1148 }; 1149 1150 static const struct panel_desc auo_g101evn010 = { 1151 .modes = &auo_g101evn010_mode, 1152 .num_modes = 1, 1153 .bpc = 6, 1154 .size = { 1155 .width = 216, 1156 .height = 135, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160 }; 1161 1162 static const struct drm_display_mode auo_g104sn02_mode = { 1163 .clock = 40000, 1164 .hdisplay = 800, 1165 .hsync_start = 800 + 40, 1166 .hsync_end = 800 + 40 + 216, 1167 .htotal = 800 + 40 + 216 + 128, 1168 .vdisplay = 600, 1169 .vsync_start = 600 + 10, 1170 .vsync_end = 600 + 10 + 35, 1171 .vtotal = 600 + 10 + 35 + 2, 1172 }; 1173 1174 static const struct panel_desc auo_g104sn02 = { 1175 .modes = &auo_g104sn02_mode, 1176 .num_modes = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 211, 1180 .height = 158, 1181 }, 1182 }; 1183 1184 static const struct drm_display_mode auo_g121ean01_mode = { 1185 .clock = 66700, 1186 .hdisplay = 1280, 1187 .hsync_start = 1280 + 58, 1188 .hsync_end = 1280 + 58 + 8, 1189 .htotal = 1280 + 58 + 8 + 70, 1190 .vdisplay = 800, 1191 .vsync_start = 800 + 6, 1192 .vsync_end = 800 + 6 + 4, 1193 .vtotal = 800 + 6 + 4 + 10, 1194 }; 1195 1196 static const struct panel_desc auo_g121ean01 = { 1197 .modes = &auo_g121ean01_mode, 1198 .num_modes = 1, 1199 .bpc = 8, 1200 .size = { 1201 .width = 261, 1202 .height = 163, 1203 }, 1204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1205 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1206 }; 1207 1208 static const struct display_timing auo_g133han01_timings = { 1209 .pixelclock = { 134000000, 141200000, 149000000 }, 1210 .hactive = { 1920, 1920, 1920 }, 1211 .hfront_porch = { 39, 58, 77 }, 1212 .hback_porch = { 59, 88, 117 }, 1213 .hsync_len = { 28, 42, 56 }, 1214 .vactive = { 1080, 1080, 1080 }, 1215 .vfront_porch = { 3, 8, 11 }, 1216 .vback_porch = { 5, 14, 19 }, 1217 .vsync_len = { 4, 14, 19 }, 1218 }; 1219 1220 static const struct panel_desc auo_g133han01 = { 1221 .timings = &auo_g133han01_timings, 1222 .num_timings = 1, 1223 .bpc = 8, 1224 .size = { 1225 .width = 293, 1226 .height = 165, 1227 }, 1228 .delay = { 1229 .prepare = 200, 1230 .enable = 50, 1231 .disable = 50, 1232 .unprepare = 1000, 1233 }, 1234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1235 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1236 }; 1237 1238 static const struct drm_display_mode auo_g156xtn01_mode = { 1239 .clock = 76000, 1240 .hdisplay = 1366, 1241 .hsync_start = 1366 + 33, 1242 .hsync_end = 1366 + 33 + 67, 1243 .htotal = 1560, 1244 .vdisplay = 768, 1245 .vsync_start = 768 + 4, 1246 .vsync_end = 768 + 4 + 4, 1247 .vtotal = 806, 1248 }; 1249 1250 static const struct panel_desc auo_g156xtn01 = { 1251 .modes = &auo_g156xtn01_mode, 1252 .num_modes = 1, 1253 .bpc = 8, 1254 .size = { 1255 .width = 344, 1256 .height = 194, 1257 }, 1258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1259 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1260 }; 1261 1262 static const struct display_timing auo_g185han01_timings = { 1263 .pixelclock = { 120000000, 144000000, 175000000 }, 1264 .hactive = { 1920, 1920, 1920 }, 1265 .hfront_porch = { 36, 120, 148 }, 1266 .hback_porch = { 24, 88, 108 }, 1267 .hsync_len = { 20, 48, 64 }, 1268 .vactive = { 1080, 1080, 1080 }, 1269 .vfront_porch = { 6, 10, 40 }, 1270 .vback_porch = { 2, 5, 20 }, 1271 .vsync_len = { 2, 5, 20 }, 1272 }; 1273 1274 static const struct panel_desc auo_g185han01 = { 1275 .timings = &auo_g185han01_timings, 1276 .num_timings = 1, 1277 .bpc = 8, 1278 .size = { 1279 .width = 409, 1280 .height = 230, 1281 }, 1282 .delay = { 1283 .prepare = 50, 1284 .enable = 200, 1285 .disable = 110, 1286 .unprepare = 1000, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1289 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1290 }; 1291 1292 static const struct display_timing auo_g190ean01_timings = { 1293 .pixelclock = { 90000000, 108000000, 135000000 }, 1294 .hactive = { 1280, 1280, 1280 }, 1295 .hfront_porch = { 126, 184, 1266 }, 1296 .hback_porch = { 84, 122, 844 }, 1297 .hsync_len = { 70, 102, 704 }, 1298 .vactive = { 1024, 1024, 1024 }, 1299 .vfront_porch = { 4, 26, 76 }, 1300 .vback_porch = { 2, 8, 25 }, 1301 .vsync_len = { 2, 8, 25 }, 1302 }; 1303 1304 static const struct panel_desc auo_g190ean01 = { 1305 .timings = &auo_g190ean01_timings, 1306 .num_timings = 1, 1307 .bpc = 8, 1308 .size = { 1309 .width = 376, 1310 .height = 301, 1311 }, 1312 .delay = { 1313 .prepare = 50, 1314 .enable = 200, 1315 .disable = 110, 1316 .unprepare = 1000, 1317 }, 1318 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1319 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1320 }; 1321 1322 static const struct display_timing auo_p320hvn03_timings = { 1323 .pixelclock = { 106000000, 148500000, 164000000 }, 1324 .hactive = { 1920, 1920, 1920 }, 1325 .hfront_porch = { 25, 50, 130 }, 1326 .hback_porch = { 25, 50, 130 }, 1327 .hsync_len = { 20, 40, 105 }, 1328 .vactive = { 1080, 1080, 1080 }, 1329 .vfront_porch = { 8, 17, 150 }, 1330 .vback_porch = { 8, 17, 150 }, 1331 .vsync_len = { 4, 11, 100 }, 1332 }; 1333 1334 static const struct panel_desc auo_p320hvn03 = { 1335 .timings = &auo_p320hvn03_timings, 1336 .num_timings = 1, 1337 .bpc = 8, 1338 .size = { 1339 .width = 698, 1340 .height = 393, 1341 }, 1342 .delay = { 1343 .prepare = 1, 1344 .enable = 450, 1345 .unprepare = 500, 1346 }, 1347 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1349 }; 1350 1351 static const struct drm_display_mode auo_t215hvn01_mode = { 1352 .clock = 148800, 1353 .hdisplay = 1920, 1354 .hsync_start = 1920 + 88, 1355 .hsync_end = 1920 + 88 + 44, 1356 .htotal = 1920 + 88 + 44 + 148, 1357 .vdisplay = 1080, 1358 .vsync_start = 1080 + 4, 1359 .vsync_end = 1080 + 4 + 5, 1360 .vtotal = 1080 + 4 + 5 + 36, 1361 }; 1362 1363 static const struct panel_desc auo_t215hvn01 = { 1364 .modes = &auo_t215hvn01_mode, 1365 .num_modes = 1, 1366 .bpc = 8, 1367 .size = { 1368 .width = 430, 1369 .height = 270, 1370 }, 1371 .delay = { 1372 .disable = 5, 1373 .unprepare = 1000, 1374 } 1375 }; 1376 1377 static const struct drm_display_mode avic_tm070ddh03_mode = { 1378 .clock = 51200, 1379 .hdisplay = 1024, 1380 .hsync_start = 1024 + 160, 1381 .hsync_end = 1024 + 160 + 4, 1382 .htotal = 1024 + 160 + 4 + 156, 1383 .vdisplay = 600, 1384 .vsync_start = 600 + 17, 1385 .vsync_end = 600 + 17 + 1, 1386 .vtotal = 600 + 17 + 1 + 17, 1387 }; 1388 1389 static const struct panel_desc avic_tm070ddh03 = { 1390 .modes = &avic_tm070ddh03_mode, 1391 .num_modes = 1, 1392 .bpc = 8, 1393 .size = { 1394 .width = 154, 1395 .height = 90, 1396 }, 1397 .delay = { 1398 .prepare = 20, 1399 .enable = 200, 1400 .disable = 200, 1401 }, 1402 }; 1403 1404 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1405 .clock = 30000, 1406 .hdisplay = 800, 1407 .hsync_start = 800 + 40, 1408 .hsync_end = 800 + 40 + 48, 1409 .htotal = 800 + 40 + 48 + 40, 1410 .vdisplay = 480, 1411 .vsync_start = 480 + 13, 1412 .vsync_end = 480 + 13 + 3, 1413 .vtotal = 480 + 13 + 3 + 29, 1414 }; 1415 1416 static const struct panel_desc bananapi_s070wv20_ct16 = { 1417 .modes = &bananapi_s070wv20_ct16_mode, 1418 .num_modes = 1, 1419 .bpc = 6, 1420 .size = { 1421 .width = 154, 1422 .height = 86, 1423 }, 1424 }; 1425 1426 static const struct drm_display_mode boe_hv070wsa_mode = { 1427 .clock = 42105, 1428 .hdisplay = 1024, 1429 .hsync_start = 1024 + 30, 1430 .hsync_end = 1024 + 30 + 30, 1431 .htotal = 1024 + 30 + 30 + 30, 1432 .vdisplay = 600, 1433 .vsync_start = 600 + 10, 1434 .vsync_end = 600 + 10 + 10, 1435 .vtotal = 600 + 10 + 10 + 10, 1436 }; 1437 1438 static const struct panel_desc boe_hv070wsa = { 1439 .modes = &boe_hv070wsa_mode, 1440 .num_modes = 1, 1441 .bpc = 8, 1442 .size = { 1443 .width = 154, 1444 .height = 90, 1445 }, 1446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1447 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1448 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1449 }; 1450 1451 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1452 { 1453 .clock = 71900, 1454 .hdisplay = 1280, 1455 .hsync_start = 1280 + 48, 1456 .hsync_end = 1280 + 48 + 32, 1457 .htotal = 1280 + 48 + 32 + 80, 1458 .vdisplay = 800, 1459 .vsync_start = 800 + 3, 1460 .vsync_end = 800 + 3 + 5, 1461 .vtotal = 800 + 3 + 5 + 24, 1462 }, 1463 { 1464 .clock = 57500, 1465 .hdisplay = 1280, 1466 .hsync_start = 1280 + 48, 1467 .hsync_end = 1280 + 48 + 32, 1468 .htotal = 1280 + 48 + 32 + 80, 1469 .vdisplay = 800, 1470 .vsync_start = 800 + 3, 1471 .vsync_end = 800 + 3 + 5, 1472 .vtotal = 800 + 3 + 5 + 24, 1473 }, 1474 }; 1475 1476 static const struct panel_desc boe_nv101wxmn51 = { 1477 .modes = boe_nv101wxmn51_modes, 1478 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1479 .bpc = 8, 1480 .size = { 1481 .width = 217, 1482 .height = 136, 1483 }, 1484 .delay = { 1485 .prepare = 210, 1486 .enable = 50, 1487 .unprepare = 160, 1488 }, 1489 }; 1490 1491 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = { 1492 { 1493 .clock = 207800, 1494 .hdisplay = 2160, 1495 .hsync_start = 2160 + 48, 1496 .hsync_end = 2160 + 48 + 32, 1497 .htotal = 2160 + 48 + 32 + 100, 1498 .vdisplay = 1440, 1499 .vsync_start = 1440 + 3, 1500 .vsync_end = 1440 + 3 + 6, 1501 .vtotal = 1440 + 3 + 6 + 31, 1502 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1503 }, 1504 { 1505 .clock = 138500, 1506 .hdisplay = 2160, 1507 .hsync_start = 2160 + 48, 1508 .hsync_end = 2160 + 48 + 32, 1509 .htotal = 2160 + 48 + 32 + 100, 1510 .vdisplay = 1440, 1511 .vsync_start = 1440 + 3, 1512 .vsync_end = 1440 + 3 + 6, 1513 .vtotal = 1440 + 3 + 6 + 31, 1514 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1515 }, 1516 }; 1517 1518 static const struct panel_desc boe_nv110wtm_n61 = { 1519 .modes = boe_nv110wtm_n61_modes, 1520 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes), 1521 .bpc = 8, 1522 .size = { 1523 .width = 233, 1524 .height = 155, 1525 }, 1526 .delay = { 1527 .hpd_absent_delay = 200, 1528 .prepare_to_enable = 80, 1529 .enable = 50, 1530 .unprepare = 500, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1533 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1534 .connector_type = DRM_MODE_CONNECTOR_eDP, 1535 }; 1536 1537 /* Also used for boe_nv133fhm_n62 */ 1538 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1539 .clock = 147840, 1540 .hdisplay = 1920, 1541 .hsync_start = 1920 + 48, 1542 .hsync_end = 1920 + 48 + 32, 1543 .htotal = 1920 + 48 + 32 + 200, 1544 .vdisplay = 1080, 1545 .vsync_start = 1080 + 3, 1546 .vsync_end = 1080 + 3 + 6, 1547 .vtotal = 1080 + 3 + 6 + 31, 1548 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1549 }; 1550 1551 /* Also used for boe_nv133fhm_n62 */ 1552 static const struct panel_desc boe_nv133fhm_n61 = { 1553 .modes = &boe_nv133fhm_n61_modes, 1554 .num_modes = 1, 1555 .bpc = 6, 1556 .size = { 1557 .width = 294, 1558 .height = 165, 1559 }, 1560 .delay = { 1561 /* 1562 * When power is first given to the panel there's a short 1563 * spike on the HPD line. It was explained that this spike 1564 * was until the TCON data download was complete. On 1565 * one system this was measured at 8 ms. We'll put 15 ms 1566 * in the prepare delay just to be safe and take it away 1567 * from the hpd_absent_delay (which would otherwise be 200 ms) 1568 * to handle this. That means: 1569 * - If HPD isn't hooked up you still have 200 ms delay. 1570 * - If HPD is hooked up we won't try to look at it for the 1571 * first 15 ms. 1572 */ 1573 .prepare = 15, 1574 .hpd_absent_delay = 185, 1575 1576 .unprepare = 500, 1577 }, 1578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1579 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1580 .connector_type = DRM_MODE_CONNECTOR_eDP, 1581 }; 1582 1583 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1584 { 1585 .clock = 148500, 1586 .hdisplay = 1920, 1587 .hsync_start = 1920 + 48, 1588 .hsync_end = 1920 + 48 + 32, 1589 .htotal = 2200, 1590 .vdisplay = 1080, 1591 .vsync_start = 1080 + 3, 1592 .vsync_end = 1080 + 3 + 5, 1593 .vtotal = 1125, 1594 }, 1595 }; 1596 1597 static const struct panel_desc boe_nv140fhmn49 = { 1598 .modes = boe_nv140fhmn49_modes, 1599 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1600 .bpc = 6, 1601 .size = { 1602 .width = 309, 1603 .height = 174, 1604 }, 1605 .delay = { 1606 .prepare = 210, 1607 .enable = 50, 1608 .unprepare = 160, 1609 }, 1610 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1611 .connector_type = DRM_MODE_CONNECTOR_eDP, 1612 }; 1613 1614 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1615 .clock = 9000, 1616 .hdisplay = 480, 1617 .hsync_start = 480 + 5, 1618 .hsync_end = 480 + 5 + 5, 1619 .htotal = 480 + 5 + 5 + 40, 1620 .vdisplay = 272, 1621 .vsync_start = 272 + 8, 1622 .vsync_end = 272 + 8 + 8, 1623 .vtotal = 272 + 8 + 8 + 8, 1624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1625 }; 1626 1627 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1628 .modes = &cdtech_s043wq26h_ct7_mode, 1629 .num_modes = 1, 1630 .bpc = 8, 1631 .size = { 1632 .width = 95, 1633 .height = 54, 1634 }, 1635 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1636 }; 1637 1638 /* S070PWS19HP-FC21 2017/04/22 */ 1639 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1640 .clock = 51200, 1641 .hdisplay = 1024, 1642 .hsync_start = 1024 + 160, 1643 .hsync_end = 1024 + 160 + 20, 1644 .htotal = 1024 + 160 + 20 + 140, 1645 .vdisplay = 600, 1646 .vsync_start = 600 + 12, 1647 .vsync_end = 600 + 12 + 3, 1648 .vtotal = 600 + 12 + 3 + 20, 1649 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1650 }; 1651 1652 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1653 .modes = &cdtech_s070pws19hp_fc21_mode, 1654 .num_modes = 1, 1655 .bpc = 6, 1656 .size = { 1657 .width = 154, 1658 .height = 86, 1659 }, 1660 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1661 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1662 .connector_type = DRM_MODE_CONNECTOR_DPI, 1663 }; 1664 1665 /* S070SWV29HG-DC44 2017/09/21 */ 1666 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1667 .clock = 33300, 1668 .hdisplay = 800, 1669 .hsync_start = 800 + 210, 1670 .hsync_end = 800 + 210 + 2, 1671 .htotal = 800 + 210 + 2 + 44, 1672 .vdisplay = 480, 1673 .vsync_start = 480 + 22, 1674 .vsync_end = 480 + 22 + 2, 1675 .vtotal = 480 + 22 + 2 + 21, 1676 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1677 }; 1678 1679 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1680 .modes = &cdtech_s070swv29hg_dc44_mode, 1681 .num_modes = 1, 1682 .bpc = 6, 1683 .size = { 1684 .width = 154, 1685 .height = 86, 1686 }, 1687 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1688 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1689 .connector_type = DRM_MODE_CONNECTOR_DPI, 1690 }; 1691 1692 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1693 .clock = 35000, 1694 .hdisplay = 800, 1695 .hsync_start = 800 + 40, 1696 .hsync_end = 800 + 40 + 40, 1697 .htotal = 800 + 40 + 40 + 48, 1698 .vdisplay = 480, 1699 .vsync_start = 480 + 29, 1700 .vsync_end = 480 + 29 + 13, 1701 .vtotal = 480 + 29 + 13 + 3, 1702 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1703 }; 1704 1705 static const struct panel_desc cdtech_s070wv95_ct16 = { 1706 .modes = &cdtech_s070wv95_ct16_mode, 1707 .num_modes = 1, 1708 .bpc = 8, 1709 .size = { 1710 .width = 154, 1711 .height = 85, 1712 }, 1713 }; 1714 1715 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1716 .pixelclock = { 68900000, 71100000, 73400000 }, 1717 .hactive = { 1280, 1280, 1280 }, 1718 .hfront_porch = { 65, 80, 95 }, 1719 .hback_porch = { 64, 79, 94 }, 1720 .hsync_len = { 1, 1, 1 }, 1721 .vactive = { 800, 800, 800 }, 1722 .vfront_porch = { 7, 11, 14 }, 1723 .vback_porch = { 7, 11, 14 }, 1724 .vsync_len = { 1, 1, 1 }, 1725 .flags = DISPLAY_FLAGS_DE_HIGH, 1726 }; 1727 1728 static const struct panel_desc chefree_ch101olhlwh_002 = { 1729 .timings = &chefree_ch101olhlwh_002_timing, 1730 .num_timings = 1, 1731 .bpc = 8, 1732 .size = { 1733 .width = 217, 1734 .height = 135, 1735 }, 1736 .delay = { 1737 .enable = 200, 1738 .disable = 200, 1739 }, 1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1741 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1742 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1743 }; 1744 1745 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1746 .clock = 66770, 1747 .hdisplay = 800, 1748 .hsync_start = 800 + 49, 1749 .hsync_end = 800 + 49 + 33, 1750 .htotal = 800 + 49 + 33 + 17, 1751 .vdisplay = 1280, 1752 .vsync_start = 1280 + 1, 1753 .vsync_end = 1280 + 1 + 7, 1754 .vtotal = 1280 + 1 + 7 + 15, 1755 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1756 }; 1757 1758 static const struct panel_desc chunghwa_claa070wp03xg = { 1759 .modes = &chunghwa_claa070wp03xg_mode, 1760 .num_modes = 1, 1761 .bpc = 6, 1762 .size = { 1763 .width = 94, 1764 .height = 150, 1765 }, 1766 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1767 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1768 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1769 }; 1770 1771 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1772 .clock = 72070, 1773 .hdisplay = 1366, 1774 .hsync_start = 1366 + 58, 1775 .hsync_end = 1366 + 58 + 58, 1776 .htotal = 1366 + 58 + 58 + 58, 1777 .vdisplay = 768, 1778 .vsync_start = 768 + 4, 1779 .vsync_end = 768 + 4 + 4, 1780 .vtotal = 768 + 4 + 4 + 4, 1781 }; 1782 1783 static const struct panel_desc chunghwa_claa101wa01a = { 1784 .modes = &chunghwa_claa101wa01a_mode, 1785 .num_modes = 1, 1786 .bpc = 6, 1787 .size = { 1788 .width = 220, 1789 .height = 120, 1790 }, 1791 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1792 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1794 }; 1795 1796 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1797 .clock = 69300, 1798 .hdisplay = 1366, 1799 .hsync_start = 1366 + 48, 1800 .hsync_end = 1366 + 48 + 32, 1801 .htotal = 1366 + 48 + 32 + 20, 1802 .vdisplay = 768, 1803 .vsync_start = 768 + 16, 1804 .vsync_end = 768 + 16 + 8, 1805 .vtotal = 768 + 16 + 8 + 16, 1806 }; 1807 1808 static const struct panel_desc chunghwa_claa101wb01 = { 1809 .modes = &chunghwa_claa101wb01_mode, 1810 .num_modes = 1, 1811 .bpc = 6, 1812 .size = { 1813 .width = 223, 1814 .height = 125, 1815 }, 1816 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1818 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1819 }; 1820 1821 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1822 .clock = 33260, 1823 .hdisplay = 800, 1824 .hsync_start = 800 + 40, 1825 .hsync_end = 800 + 40 + 128, 1826 .htotal = 800 + 40 + 128 + 88, 1827 .vdisplay = 480, 1828 .vsync_start = 480 + 10, 1829 .vsync_end = 480 + 10 + 2, 1830 .vtotal = 480 + 10 + 2 + 33, 1831 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1832 }; 1833 1834 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1835 .modes = &dataimage_scf0700c48ggu18_mode, 1836 .num_modes = 1, 1837 .bpc = 8, 1838 .size = { 1839 .width = 152, 1840 .height = 91, 1841 }, 1842 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1843 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1844 }; 1845 1846 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1847 .pixelclock = { 45000000, 51200000, 57000000 }, 1848 .hactive = { 1024, 1024, 1024 }, 1849 .hfront_porch = { 100, 106, 113 }, 1850 .hback_porch = { 100, 106, 113 }, 1851 .hsync_len = { 100, 108, 114 }, 1852 .vactive = { 600, 600, 600 }, 1853 .vfront_porch = { 8, 11, 15 }, 1854 .vback_porch = { 8, 11, 15 }, 1855 .vsync_len = { 9, 13, 15 }, 1856 .flags = DISPLAY_FLAGS_DE_HIGH, 1857 }; 1858 1859 static const struct panel_desc dlc_dlc0700yzg_1 = { 1860 .timings = &dlc_dlc0700yzg_1_timing, 1861 .num_timings = 1, 1862 .bpc = 6, 1863 .size = { 1864 .width = 154, 1865 .height = 86, 1866 }, 1867 .delay = { 1868 .prepare = 30, 1869 .enable = 200, 1870 .disable = 200, 1871 }, 1872 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1873 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1874 }; 1875 1876 static const struct display_timing dlc_dlc1010gig_timing = { 1877 .pixelclock = { 68900000, 71100000, 73400000 }, 1878 .hactive = { 1280, 1280, 1280 }, 1879 .hfront_porch = { 43, 53, 63 }, 1880 .hback_porch = { 43, 53, 63 }, 1881 .hsync_len = { 44, 54, 64 }, 1882 .vactive = { 800, 800, 800 }, 1883 .vfront_porch = { 5, 8, 11 }, 1884 .vback_porch = { 5, 8, 11 }, 1885 .vsync_len = { 5, 7, 11 }, 1886 .flags = DISPLAY_FLAGS_DE_HIGH, 1887 }; 1888 1889 static const struct panel_desc dlc_dlc1010gig = { 1890 .timings = &dlc_dlc1010gig_timing, 1891 .num_timings = 1, 1892 .bpc = 8, 1893 .size = { 1894 .width = 216, 1895 .height = 135, 1896 }, 1897 .delay = { 1898 .prepare = 60, 1899 .enable = 150, 1900 .disable = 100, 1901 .unprepare = 60, 1902 }, 1903 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1904 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1905 }; 1906 1907 static const struct drm_display_mode edt_et035012dm6_mode = { 1908 .clock = 6500, 1909 .hdisplay = 320, 1910 .hsync_start = 320 + 20, 1911 .hsync_end = 320 + 20 + 30, 1912 .htotal = 320 + 20 + 68, 1913 .vdisplay = 240, 1914 .vsync_start = 240 + 4, 1915 .vsync_end = 240 + 4 + 4, 1916 .vtotal = 240 + 4 + 4 + 14, 1917 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1918 }; 1919 1920 static const struct panel_desc edt_et035012dm6 = { 1921 .modes = &edt_et035012dm6_mode, 1922 .num_modes = 1, 1923 .bpc = 8, 1924 .size = { 1925 .width = 70, 1926 .height = 52, 1927 }, 1928 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1929 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1930 }; 1931 1932 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1933 .clock = 10870, 1934 .hdisplay = 480, 1935 .hsync_start = 480 + 8, 1936 .hsync_end = 480 + 8 + 4, 1937 .htotal = 480 + 8 + 4 + 41, 1938 1939 /* 1940 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1941 * fb_align 1942 */ 1943 1944 .vdisplay = 288, 1945 .vsync_start = 288 + 2, 1946 .vsync_end = 288 + 2 + 4, 1947 .vtotal = 288 + 2 + 4 + 10, 1948 }; 1949 1950 static const struct panel_desc edt_etm043080dh6gp = { 1951 .modes = &edt_etm043080dh6gp_mode, 1952 .num_modes = 1, 1953 .bpc = 8, 1954 .size = { 1955 .width = 100, 1956 .height = 65, 1957 }, 1958 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1959 .connector_type = DRM_MODE_CONNECTOR_DPI, 1960 }; 1961 1962 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1963 .clock = 9000, 1964 .hdisplay = 480, 1965 .hsync_start = 480 + 2, 1966 .hsync_end = 480 + 2 + 41, 1967 .htotal = 480 + 2 + 41 + 2, 1968 .vdisplay = 272, 1969 .vsync_start = 272 + 2, 1970 .vsync_end = 272 + 2 + 10, 1971 .vtotal = 272 + 2 + 10 + 2, 1972 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1973 }; 1974 1975 static const struct panel_desc edt_etm0430g0dh6 = { 1976 .modes = &edt_etm0430g0dh6_mode, 1977 .num_modes = 1, 1978 .bpc = 6, 1979 .size = { 1980 .width = 95, 1981 .height = 54, 1982 }, 1983 }; 1984 1985 static const struct drm_display_mode edt_et057090dhu_mode = { 1986 .clock = 25175, 1987 .hdisplay = 640, 1988 .hsync_start = 640 + 16, 1989 .hsync_end = 640 + 16 + 30, 1990 .htotal = 640 + 16 + 30 + 114, 1991 .vdisplay = 480, 1992 .vsync_start = 480 + 10, 1993 .vsync_end = 480 + 10 + 3, 1994 .vtotal = 480 + 10 + 3 + 32, 1995 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1996 }; 1997 1998 static const struct panel_desc edt_et057090dhu = { 1999 .modes = &edt_et057090dhu_mode, 2000 .num_modes = 1, 2001 .bpc = 6, 2002 .size = { 2003 .width = 115, 2004 .height = 86, 2005 }, 2006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2007 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2008 .connector_type = DRM_MODE_CONNECTOR_DPI, 2009 }; 2010 2011 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2012 .clock = 33260, 2013 .hdisplay = 800, 2014 .hsync_start = 800 + 40, 2015 .hsync_end = 800 + 40 + 128, 2016 .htotal = 800 + 40 + 128 + 88, 2017 .vdisplay = 480, 2018 .vsync_start = 480 + 10, 2019 .vsync_end = 480 + 10 + 2, 2020 .vtotal = 480 + 10 + 2 + 33, 2021 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2022 }; 2023 2024 static const struct panel_desc edt_etm0700g0dh6 = { 2025 .modes = &edt_etm0700g0dh6_mode, 2026 .num_modes = 1, 2027 .bpc = 6, 2028 .size = { 2029 .width = 152, 2030 .height = 91, 2031 }, 2032 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2033 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2034 .connector_type = DRM_MODE_CONNECTOR_DPI, 2035 }; 2036 2037 static const struct panel_desc edt_etm0700g0bdh6 = { 2038 .modes = &edt_etm0700g0dh6_mode, 2039 .num_modes = 1, 2040 .bpc = 6, 2041 .size = { 2042 .width = 152, 2043 .height = 91, 2044 }, 2045 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2047 }; 2048 2049 static const struct display_timing evervision_vgg804821_timing = { 2050 .pixelclock = { 27600000, 33300000, 50000000 }, 2051 .hactive = { 800, 800, 800 }, 2052 .hfront_porch = { 40, 66, 70 }, 2053 .hback_porch = { 40, 67, 70 }, 2054 .hsync_len = { 40, 67, 70 }, 2055 .vactive = { 480, 480, 480 }, 2056 .vfront_porch = { 6, 10, 10 }, 2057 .vback_porch = { 7, 11, 11 }, 2058 .vsync_len = { 7, 11, 11 }, 2059 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2060 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2061 DISPLAY_FLAGS_SYNC_NEGEDGE, 2062 }; 2063 2064 static const struct panel_desc evervision_vgg804821 = { 2065 .timings = &evervision_vgg804821_timing, 2066 .num_timings = 1, 2067 .bpc = 8, 2068 .size = { 2069 .width = 108, 2070 .height = 64, 2071 }, 2072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2074 }; 2075 2076 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2077 .clock = 32260, 2078 .hdisplay = 800, 2079 .hsync_start = 800 + 168, 2080 .hsync_end = 800 + 168 + 64, 2081 .htotal = 800 + 168 + 64 + 88, 2082 .vdisplay = 480, 2083 .vsync_start = 480 + 37, 2084 .vsync_end = 480 + 37 + 2, 2085 .vtotal = 480 + 37 + 2 + 8, 2086 }; 2087 2088 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2089 .modes = &foxlink_fl500wvr00_a0t_mode, 2090 .num_modes = 1, 2091 .bpc = 8, 2092 .size = { 2093 .width = 108, 2094 .height = 65, 2095 }, 2096 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2097 }; 2098 2099 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2100 { /* 60 Hz */ 2101 .clock = 6000, 2102 .hdisplay = 320, 2103 .hsync_start = 320 + 44, 2104 .hsync_end = 320 + 44 + 16, 2105 .htotal = 320 + 44 + 16 + 20, 2106 .vdisplay = 240, 2107 .vsync_start = 240 + 2, 2108 .vsync_end = 240 + 2 + 6, 2109 .vtotal = 240 + 2 + 6 + 2, 2110 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2111 }, 2112 { /* 50 Hz */ 2113 .clock = 5400, 2114 .hdisplay = 320, 2115 .hsync_start = 320 + 56, 2116 .hsync_end = 320 + 56 + 16, 2117 .htotal = 320 + 56 + 16 + 40, 2118 .vdisplay = 240, 2119 .vsync_start = 240 + 2, 2120 .vsync_end = 240 + 2 + 6, 2121 .vtotal = 240 + 2 + 6 + 2, 2122 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2123 }, 2124 }; 2125 2126 static const struct panel_desc frida_frd350h54004 = { 2127 .modes = frida_frd350h54004_modes, 2128 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2129 .bpc = 8, 2130 .size = { 2131 .width = 77, 2132 .height = 64, 2133 }, 2134 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2135 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2136 .connector_type = DRM_MODE_CONNECTOR_DPI, 2137 }; 2138 2139 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2140 .clock = 67185, 2141 .hdisplay = 800, 2142 .hsync_start = 800 + 20, 2143 .hsync_end = 800 + 20 + 24, 2144 .htotal = 800 + 20 + 24 + 20, 2145 .vdisplay = 1280, 2146 .vsync_start = 1280 + 4, 2147 .vsync_end = 1280 + 4 + 8, 2148 .vtotal = 1280 + 4 + 8 + 4, 2149 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2150 }; 2151 2152 static const struct panel_desc friendlyarm_hd702e = { 2153 .modes = &friendlyarm_hd702e_mode, 2154 .num_modes = 1, 2155 .size = { 2156 .width = 94, 2157 .height = 151, 2158 }, 2159 }; 2160 2161 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2162 .clock = 9000, 2163 .hdisplay = 480, 2164 .hsync_start = 480 + 5, 2165 .hsync_end = 480 + 5 + 1, 2166 .htotal = 480 + 5 + 1 + 40, 2167 .vdisplay = 272, 2168 .vsync_start = 272 + 8, 2169 .vsync_end = 272 + 8 + 1, 2170 .vtotal = 272 + 8 + 1 + 8, 2171 }; 2172 2173 static const struct panel_desc giantplus_gpg482739qs5 = { 2174 .modes = &giantplus_gpg482739qs5_mode, 2175 .num_modes = 1, 2176 .bpc = 8, 2177 .size = { 2178 .width = 95, 2179 .height = 54, 2180 }, 2181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2182 }; 2183 2184 static const struct display_timing giantplus_gpm940b0_timing = { 2185 .pixelclock = { 13500000, 27000000, 27500000 }, 2186 .hactive = { 320, 320, 320 }, 2187 .hfront_porch = { 14, 686, 718 }, 2188 .hback_porch = { 50, 70, 255 }, 2189 .hsync_len = { 1, 1, 1 }, 2190 .vactive = { 240, 240, 240 }, 2191 .vfront_porch = { 1, 1, 179 }, 2192 .vback_porch = { 1, 21, 31 }, 2193 .vsync_len = { 1, 1, 6 }, 2194 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2195 }; 2196 2197 static const struct panel_desc giantplus_gpm940b0 = { 2198 .timings = &giantplus_gpm940b0_timing, 2199 .num_timings = 1, 2200 .bpc = 8, 2201 .size = { 2202 .width = 60, 2203 .height = 45, 2204 }, 2205 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2206 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2207 }; 2208 2209 static const struct display_timing hannstar_hsd070pww1_timing = { 2210 .pixelclock = { 64300000, 71100000, 82000000 }, 2211 .hactive = { 1280, 1280, 1280 }, 2212 .hfront_porch = { 1, 1, 10 }, 2213 .hback_porch = { 1, 1, 10 }, 2214 /* 2215 * According to the data sheet, the minimum horizontal blanking interval 2216 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2217 * minimum working horizontal blanking interval to be 60 clocks. 2218 */ 2219 .hsync_len = { 58, 158, 661 }, 2220 .vactive = { 800, 800, 800 }, 2221 .vfront_porch = { 1, 1, 10 }, 2222 .vback_porch = { 1, 1, 10 }, 2223 .vsync_len = { 1, 21, 203 }, 2224 .flags = DISPLAY_FLAGS_DE_HIGH, 2225 }; 2226 2227 static const struct panel_desc hannstar_hsd070pww1 = { 2228 .timings = &hannstar_hsd070pww1_timing, 2229 .num_timings = 1, 2230 .bpc = 6, 2231 .size = { 2232 .width = 151, 2233 .height = 94, 2234 }, 2235 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2236 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2237 }; 2238 2239 static const struct display_timing hannstar_hsd100pxn1_timing = { 2240 .pixelclock = { 55000000, 65000000, 75000000 }, 2241 .hactive = { 1024, 1024, 1024 }, 2242 .hfront_porch = { 40, 40, 40 }, 2243 .hback_porch = { 220, 220, 220 }, 2244 .hsync_len = { 20, 60, 100 }, 2245 .vactive = { 768, 768, 768 }, 2246 .vfront_porch = { 7, 7, 7 }, 2247 .vback_porch = { 21, 21, 21 }, 2248 .vsync_len = { 10, 10, 10 }, 2249 .flags = DISPLAY_FLAGS_DE_HIGH, 2250 }; 2251 2252 static const struct panel_desc hannstar_hsd100pxn1 = { 2253 .timings = &hannstar_hsd100pxn1_timing, 2254 .num_timings = 1, 2255 .bpc = 6, 2256 .size = { 2257 .width = 203, 2258 .height = 152, 2259 }, 2260 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2261 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2262 }; 2263 2264 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2265 .clock = 33333, 2266 .hdisplay = 800, 2267 .hsync_start = 800 + 85, 2268 .hsync_end = 800 + 85 + 86, 2269 .htotal = 800 + 85 + 86 + 85, 2270 .vdisplay = 480, 2271 .vsync_start = 480 + 16, 2272 .vsync_end = 480 + 16 + 13, 2273 .vtotal = 480 + 16 + 13 + 16, 2274 }; 2275 2276 static const struct panel_desc hitachi_tx23d38vm0caa = { 2277 .modes = &hitachi_tx23d38vm0caa_mode, 2278 .num_modes = 1, 2279 .bpc = 6, 2280 .size = { 2281 .width = 195, 2282 .height = 117, 2283 }, 2284 .delay = { 2285 .enable = 160, 2286 .disable = 160, 2287 }, 2288 }; 2289 2290 static const struct drm_display_mode innolux_at043tn24_mode = { 2291 .clock = 9000, 2292 .hdisplay = 480, 2293 .hsync_start = 480 + 2, 2294 .hsync_end = 480 + 2 + 41, 2295 .htotal = 480 + 2 + 41 + 2, 2296 .vdisplay = 272, 2297 .vsync_start = 272 + 2, 2298 .vsync_end = 272 + 2 + 10, 2299 .vtotal = 272 + 2 + 10 + 2, 2300 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2301 }; 2302 2303 static const struct panel_desc innolux_at043tn24 = { 2304 .modes = &innolux_at043tn24_mode, 2305 .num_modes = 1, 2306 .bpc = 8, 2307 .size = { 2308 .width = 95, 2309 .height = 54, 2310 }, 2311 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2312 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2313 }; 2314 2315 static const struct drm_display_mode innolux_at070tn92_mode = { 2316 .clock = 33333, 2317 .hdisplay = 800, 2318 .hsync_start = 800 + 210, 2319 .hsync_end = 800 + 210 + 20, 2320 .htotal = 800 + 210 + 20 + 46, 2321 .vdisplay = 480, 2322 .vsync_start = 480 + 22, 2323 .vsync_end = 480 + 22 + 10, 2324 .vtotal = 480 + 22 + 23 + 10, 2325 }; 2326 2327 static const struct panel_desc innolux_at070tn92 = { 2328 .modes = &innolux_at070tn92_mode, 2329 .num_modes = 1, 2330 .size = { 2331 .width = 154, 2332 .height = 86, 2333 }, 2334 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2335 }; 2336 2337 static const struct display_timing innolux_g070y2_l01_timing = { 2338 .pixelclock = { 28000000, 29500000, 32000000 }, 2339 .hactive = { 800, 800, 800 }, 2340 .hfront_porch = { 61, 91, 141 }, 2341 .hback_porch = { 60, 90, 140 }, 2342 .hsync_len = { 12, 12, 12 }, 2343 .vactive = { 480, 480, 480 }, 2344 .vfront_porch = { 4, 9, 30 }, 2345 .vback_porch = { 4, 8, 28 }, 2346 .vsync_len = { 2, 2, 2 }, 2347 .flags = DISPLAY_FLAGS_DE_HIGH, 2348 }; 2349 2350 static const struct panel_desc innolux_g070y2_l01 = { 2351 .timings = &innolux_g070y2_l01_timing, 2352 .num_timings = 1, 2353 .bpc = 6, 2354 .size = { 2355 .width = 152, 2356 .height = 91, 2357 }, 2358 .delay = { 2359 .prepare = 10, 2360 .enable = 100, 2361 .disable = 100, 2362 .unprepare = 800, 2363 }, 2364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2365 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2366 }; 2367 2368 static const struct display_timing innolux_g101ice_l01_timing = { 2369 .pixelclock = { 60400000, 71100000, 74700000 }, 2370 .hactive = { 1280, 1280, 1280 }, 2371 .hfront_porch = { 41, 80, 100 }, 2372 .hback_porch = { 40, 79, 99 }, 2373 .hsync_len = { 1, 1, 1 }, 2374 .vactive = { 800, 800, 800 }, 2375 .vfront_porch = { 5, 11, 14 }, 2376 .vback_porch = { 4, 11, 14 }, 2377 .vsync_len = { 1, 1, 1 }, 2378 .flags = DISPLAY_FLAGS_DE_HIGH, 2379 }; 2380 2381 static const struct panel_desc innolux_g101ice_l01 = { 2382 .timings = &innolux_g101ice_l01_timing, 2383 .num_timings = 1, 2384 .bpc = 8, 2385 .size = { 2386 .width = 217, 2387 .height = 135, 2388 }, 2389 .delay = { 2390 .enable = 200, 2391 .disable = 200, 2392 }, 2393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2394 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2395 }; 2396 2397 static const struct display_timing innolux_g121i1_l01_timing = { 2398 .pixelclock = { 67450000, 71000000, 74550000 }, 2399 .hactive = { 1280, 1280, 1280 }, 2400 .hfront_porch = { 40, 80, 160 }, 2401 .hback_porch = { 39, 79, 159 }, 2402 .hsync_len = { 1, 1, 1 }, 2403 .vactive = { 800, 800, 800 }, 2404 .vfront_porch = { 5, 11, 100 }, 2405 .vback_porch = { 4, 11, 99 }, 2406 .vsync_len = { 1, 1, 1 }, 2407 }; 2408 2409 static const struct panel_desc innolux_g121i1_l01 = { 2410 .timings = &innolux_g121i1_l01_timing, 2411 .num_timings = 1, 2412 .bpc = 6, 2413 .size = { 2414 .width = 261, 2415 .height = 163, 2416 }, 2417 .delay = { 2418 .enable = 200, 2419 .disable = 20, 2420 }, 2421 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2422 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2423 }; 2424 2425 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2426 .clock = 65000, 2427 .hdisplay = 1024, 2428 .hsync_start = 1024 + 0, 2429 .hsync_end = 1024 + 1, 2430 .htotal = 1024 + 0 + 1 + 320, 2431 .vdisplay = 768, 2432 .vsync_start = 768 + 38, 2433 .vsync_end = 768 + 38 + 1, 2434 .vtotal = 768 + 38 + 1 + 0, 2435 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2436 }; 2437 2438 static const struct panel_desc innolux_g121x1_l03 = { 2439 .modes = &innolux_g121x1_l03_mode, 2440 .num_modes = 1, 2441 .bpc = 6, 2442 .size = { 2443 .width = 246, 2444 .height = 185, 2445 }, 2446 .delay = { 2447 .enable = 200, 2448 .unprepare = 200, 2449 .disable = 400, 2450 }, 2451 }; 2452 2453 static const struct drm_display_mode innolux_n116bca_ea1_mode = { 2454 .clock = 76420, 2455 .hdisplay = 1366, 2456 .hsync_start = 1366 + 136, 2457 .hsync_end = 1366 + 136 + 30, 2458 .htotal = 1366 + 136 + 30 + 60, 2459 .vdisplay = 768, 2460 .vsync_start = 768 + 8, 2461 .vsync_end = 768 + 8 + 12, 2462 .vtotal = 768 + 8 + 12 + 12, 2463 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2464 }; 2465 2466 static const struct panel_desc innolux_n116bca_ea1 = { 2467 .modes = &innolux_n116bca_ea1_mode, 2468 .num_modes = 1, 2469 .bpc = 6, 2470 .size = { 2471 .width = 256, 2472 .height = 144, 2473 }, 2474 .delay = { 2475 .hpd_absent_delay = 200, 2476 .prepare_to_enable = 80, 2477 .unprepare = 500, 2478 }, 2479 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2480 .connector_type = DRM_MODE_CONNECTOR_eDP, 2481 }; 2482 2483 /* 2484 * Datasheet specifies that at 60 Hz refresh rate: 2485 * - total horizontal time: { 1506, 1592, 1716 } 2486 * - total vertical time: { 788, 800, 868 } 2487 * 2488 * ...but doesn't go into exactly how that should be split into a front 2489 * porch, back porch, or sync length. For now we'll leave a single setting 2490 * here which allows a bit of tweaking of the pixel clock at the expense of 2491 * refresh rate. 2492 */ 2493 static const struct display_timing innolux_n116bge_timing = { 2494 .pixelclock = { 72600000, 76420000, 80240000 }, 2495 .hactive = { 1366, 1366, 1366 }, 2496 .hfront_porch = { 136, 136, 136 }, 2497 .hback_porch = { 60, 60, 60 }, 2498 .hsync_len = { 30, 30, 30 }, 2499 .vactive = { 768, 768, 768 }, 2500 .vfront_porch = { 8, 8, 8 }, 2501 .vback_porch = { 12, 12, 12 }, 2502 .vsync_len = { 12, 12, 12 }, 2503 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2504 }; 2505 2506 static const struct panel_desc innolux_n116bge = { 2507 .timings = &innolux_n116bge_timing, 2508 .num_timings = 1, 2509 .bpc = 6, 2510 .size = { 2511 .width = 256, 2512 .height = 144, 2513 }, 2514 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2515 .connector_type = DRM_MODE_CONNECTOR_eDP, 2516 }; 2517 2518 static const struct drm_display_mode innolux_n125hce_gn1_mode = { 2519 .clock = 162000, 2520 .hdisplay = 1920, 2521 .hsync_start = 1920 + 40, 2522 .hsync_end = 1920 + 40 + 40, 2523 .htotal = 1920 + 40 + 40 + 80, 2524 .vdisplay = 1080, 2525 .vsync_start = 1080 + 4, 2526 .vsync_end = 1080 + 4 + 4, 2527 .vtotal = 1080 + 4 + 4 + 24, 2528 }; 2529 2530 static const struct panel_desc innolux_n125hce_gn1 = { 2531 .modes = &innolux_n125hce_gn1_mode, 2532 .num_modes = 1, 2533 .bpc = 8, 2534 .size = { 2535 .width = 276, 2536 .height = 155, 2537 }, 2538 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2539 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2540 .connector_type = DRM_MODE_CONNECTOR_eDP, 2541 }; 2542 2543 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2544 .clock = 69300, 2545 .hdisplay = 1366, 2546 .hsync_start = 1366 + 16, 2547 .hsync_end = 1366 + 16 + 34, 2548 .htotal = 1366 + 16 + 34 + 50, 2549 .vdisplay = 768, 2550 .vsync_start = 768 + 2, 2551 .vsync_end = 768 + 2 + 6, 2552 .vtotal = 768 + 2 + 6 + 12, 2553 }; 2554 2555 static const struct panel_desc innolux_n156bge_l21 = { 2556 .modes = &innolux_n156bge_l21_mode, 2557 .num_modes = 1, 2558 .bpc = 6, 2559 .size = { 2560 .width = 344, 2561 .height = 193, 2562 }, 2563 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2564 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2565 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2566 }; 2567 2568 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2569 .clock = 206016, 2570 .hdisplay = 2160, 2571 .hsync_start = 2160 + 48, 2572 .hsync_end = 2160 + 48 + 32, 2573 .htotal = 2160 + 48 + 32 + 80, 2574 .vdisplay = 1440, 2575 .vsync_start = 1440 + 3, 2576 .vsync_end = 1440 + 3 + 10, 2577 .vtotal = 1440 + 3 + 10 + 27, 2578 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2579 }; 2580 2581 static const struct panel_desc innolux_p120zdg_bf1 = { 2582 .modes = &innolux_p120zdg_bf1_mode, 2583 .num_modes = 1, 2584 .bpc = 8, 2585 .size = { 2586 .width = 254, 2587 .height = 169, 2588 }, 2589 .delay = { 2590 .hpd_absent_delay = 200, 2591 .unprepare = 500, 2592 }, 2593 }; 2594 2595 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2596 .clock = 51501, 2597 .hdisplay = 1024, 2598 .hsync_start = 1024 + 128, 2599 .hsync_end = 1024 + 128 + 64, 2600 .htotal = 1024 + 128 + 64 + 128, 2601 .vdisplay = 600, 2602 .vsync_start = 600 + 16, 2603 .vsync_end = 600 + 16 + 4, 2604 .vtotal = 600 + 16 + 4 + 16, 2605 }; 2606 2607 static const struct panel_desc innolux_zj070na_01p = { 2608 .modes = &innolux_zj070na_01p_mode, 2609 .num_modes = 1, 2610 .bpc = 6, 2611 .size = { 2612 .width = 154, 2613 .height = 90, 2614 }, 2615 }; 2616 2617 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2618 .clock = 138778, 2619 .hdisplay = 1920, 2620 .hsync_start = 1920 + 24, 2621 .hsync_end = 1920 + 24 + 48, 2622 .htotal = 1920 + 24 + 48 + 88, 2623 .vdisplay = 1080, 2624 .vsync_start = 1080 + 3, 2625 .vsync_end = 1080 + 3 + 12, 2626 .vtotal = 1080 + 3 + 12 + 17, 2627 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2628 }; 2629 2630 static const struct panel_desc ivo_m133nwf4_r0 = { 2631 .modes = &ivo_m133nwf4_r0_mode, 2632 .num_modes = 1, 2633 .bpc = 8, 2634 .size = { 2635 .width = 294, 2636 .height = 165, 2637 }, 2638 .delay = { 2639 .hpd_absent_delay = 200, 2640 .unprepare = 500, 2641 }, 2642 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2643 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2644 .connector_type = DRM_MODE_CONNECTOR_eDP, 2645 }; 2646 2647 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2648 .clock = 81000, 2649 .hdisplay = 1366, 2650 .hsync_start = 1366 + 40, 2651 .hsync_end = 1366 + 40 + 32, 2652 .htotal = 1366 + 40 + 32 + 62, 2653 .vdisplay = 768, 2654 .vsync_start = 768 + 5, 2655 .vsync_end = 768 + 5 + 5, 2656 .vtotal = 768 + 5 + 5 + 122, 2657 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2658 }; 2659 2660 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2661 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2662 .num_modes = 1, 2663 .bpc = 6, 2664 .size = { 2665 .width = 256, 2666 .height = 144, 2667 }, 2668 .delay = { 2669 .hpd_absent_delay = 200, 2670 }, 2671 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2672 .connector_type = DRM_MODE_CONNECTOR_eDP, 2673 }; 2674 2675 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2676 .pixelclock = { 5580000, 5850000, 6200000 }, 2677 .hactive = { 320, 320, 320 }, 2678 .hfront_porch = { 30, 30, 30 }, 2679 .hback_porch = { 30, 30, 30 }, 2680 .hsync_len = { 1, 5, 17 }, 2681 .vactive = { 240, 240, 240 }, 2682 .vfront_porch = { 6, 6, 6 }, 2683 .vback_porch = { 5, 5, 5 }, 2684 .vsync_len = { 1, 2, 11 }, 2685 .flags = DISPLAY_FLAGS_DE_HIGH, 2686 }; 2687 2688 static const struct panel_desc koe_tx14d24vm1bpa = { 2689 .timings = &koe_tx14d24vm1bpa_timing, 2690 .num_timings = 1, 2691 .bpc = 6, 2692 .size = { 2693 .width = 115, 2694 .height = 86, 2695 }, 2696 }; 2697 2698 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2699 .pixelclock = { 151820000, 156720000, 159780000 }, 2700 .hactive = { 1920, 1920, 1920 }, 2701 .hfront_porch = { 105, 130, 142 }, 2702 .hback_porch = { 45, 70, 82 }, 2703 .hsync_len = { 30, 30, 30 }, 2704 .vactive = { 1200, 1200, 1200}, 2705 .vfront_porch = { 3, 5, 10 }, 2706 .vback_porch = { 2, 5, 10 }, 2707 .vsync_len = { 5, 5, 5 }, 2708 }; 2709 2710 static const struct panel_desc koe_tx26d202vm0bwa = { 2711 .timings = &koe_tx26d202vm0bwa_timing, 2712 .num_timings = 1, 2713 .bpc = 8, 2714 .size = { 2715 .width = 217, 2716 .height = 136, 2717 }, 2718 .delay = { 2719 .prepare = 1000, 2720 .enable = 1000, 2721 .unprepare = 1000, 2722 .disable = 1000, 2723 }, 2724 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2725 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2726 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2727 }; 2728 2729 static const struct display_timing koe_tx31d200vm0baa_timing = { 2730 .pixelclock = { 39600000, 43200000, 48000000 }, 2731 .hactive = { 1280, 1280, 1280 }, 2732 .hfront_porch = { 16, 36, 56 }, 2733 .hback_porch = { 16, 36, 56 }, 2734 .hsync_len = { 8, 8, 8 }, 2735 .vactive = { 480, 480, 480 }, 2736 .vfront_porch = { 6, 21, 33 }, 2737 .vback_porch = { 6, 21, 33 }, 2738 .vsync_len = { 8, 8, 8 }, 2739 .flags = DISPLAY_FLAGS_DE_HIGH, 2740 }; 2741 2742 static const struct panel_desc koe_tx31d200vm0baa = { 2743 .timings = &koe_tx31d200vm0baa_timing, 2744 .num_timings = 1, 2745 .bpc = 6, 2746 .size = { 2747 .width = 292, 2748 .height = 109, 2749 }, 2750 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2752 }; 2753 2754 static const struct display_timing kyo_tcg121xglp_timing = { 2755 .pixelclock = { 52000000, 65000000, 71000000 }, 2756 .hactive = { 1024, 1024, 1024 }, 2757 .hfront_porch = { 2, 2, 2 }, 2758 .hback_porch = { 2, 2, 2 }, 2759 .hsync_len = { 86, 124, 244 }, 2760 .vactive = { 768, 768, 768 }, 2761 .vfront_porch = { 2, 2, 2 }, 2762 .vback_porch = { 2, 2, 2 }, 2763 .vsync_len = { 6, 34, 73 }, 2764 .flags = DISPLAY_FLAGS_DE_HIGH, 2765 }; 2766 2767 static const struct panel_desc kyo_tcg121xglp = { 2768 .timings = &kyo_tcg121xglp_timing, 2769 .num_timings = 1, 2770 .bpc = 8, 2771 .size = { 2772 .width = 246, 2773 .height = 184, 2774 }, 2775 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2776 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2777 }; 2778 2779 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2780 .clock = 7000, 2781 .hdisplay = 320, 2782 .hsync_start = 320 + 20, 2783 .hsync_end = 320 + 20 + 30, 2784 .htotal = 320 + 20 + 30 + 38, 2785 .vdisplay = 240, 2786 .vsync_start = 240 + 4, 2787 .vsync_end = 240 + 4 + 3, 2788 .vtotal = 240 + 4 + 3 + 15, 2789 }; 2790 2791 static const struct panel_desc lemaker_bl035_rgb_002 = { 2792 .modes = &lemaker_bl035_rgb_002_mode, 2793 .num_modes = 1, 2794 .size = { 2795 .width = 70, 2796 .height = 52, 2797 }, 2798 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2799 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2800 }; 2801 2802 static const struct drm_display_mode lg_lb070wv8_mode = { 2803 .clock = 33246, 2804 .hdisplay = 800, 2805 .hsync_start = 800 + 88, 2806 .hsync_end = 800 + 88 + 80, 2807 .htotal = 800 + 88 + 80 + 88, 2808 .vdisplay = 480, 2809 .vsync_start = 480 + 10, 2810 .vsync_end = 480 + 10 + 25, 2811 .vtotal = 480 + 10 + 25 + 10, 2812 }; 2813 2814 static const struct panel_desc lg_lb070wv8 = { 2815 .modes = &lg_lb070wv8_mode, 2816 .num_modes = 1, 2817 .bpc = 8, 2818 .size = { 2819 .width = 151, 2820 .height = 91, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2823 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2824 }; 2825 2826 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2827 .clock = 200000, 2828 .hdisplay = 1536, 2829 .hsync_start = 1536 + 12, 2830 .hsync_end = 1536 + 12 + 16, 2831 .htotal = 1536 + 12 + 16 + 48, 2832 .vdisplay = 2048, 2833 .vsync_start = 2048 + 8, 2834 .vsync_end = 2048 + 8 + 4, 2835 .vtotal = 2048 + 8 + 4 + 8, 2836 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2837 }; 2838 2839 static const struct panel_desc lg_lp079qx1_sp0v = { 2840 .modes = &lg_lp079qx1_sp0v_mode, 2841 .num_modes = 1, 2842 .size = { 2843 .width = 129, 2844 .height = 171, 2845 }, 2846 }; 2847 2848 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2849 .clock = 205210, 2850 .hdisplay = 2048, 2851 .hsync_start = 2048 + 150, 2852 .hsync_end = 2048 + 150 + 5, 2853 .htotal = 2048 + 150 + 5 + 5, 2854 .vdisplay = 1536, 2855 .vsync_start = 1536 + 3, 2856 .vsync_end = 1536 + 3 + 1, 2857 .vtotal = 1536 + 3 + 1 + 9, 2858 }; 2859 2860 static const struct panel_desc lg_lp097qx1_spa1 = { 2861 .modes = &lg_lp097qx1_spa1_mode, 2862 .num_modes = 1, 2863 .size = { 2864 .width = 208, 2865 .height = 147, 2866 }, 2867 }; 2868 2869 static const struct drm_display_mode lg_lp120up1_mode = { 2870 .clock = 162300, 2871 .hdisplay = 1920, 2872 .hsync_start = 1920 + 40, 2873 .hsync_end = 1920 + 40 + 40, 2874 .htotal = 1920 + 40 + 40+ 80, 2875 .vdisplay = 1280, 2876 .vsync_start = 1280 + 4, 2877 .vsync_end = 1280 + 4 + 4, 2878 .vtotal = 1280 + 4 + 4 + 12, 2879 }; 2880 2881 static const struct panel_desc lg_lp120up1 = { 2882 .modes = &lg_lp120up1_mode, 2883 .num_modes = 1, 2884 .bpc = 8, 2885 .size = { 2886 .width = 267, 2887 .height = 183, 2888 }, 2889 .connector_type = DRM_MODE_CONNECTOR_eDP, 2890 }; 2891 2892 static const struct drm_display_mode lg_lp129qe_mode = { 2893 .clock = 285250, 2894 .hdisplay = 2560, 2895 .hsync_start = 2560 + 48, 2896 .hsync_end = 2560 + 48 + 32, 2897 .htotal = 2560 + 48 + 32 + 80, 2898 .vdisplay = 1700, 2899 .vsync_start = 1700 + 3, 2900 .vsync_end = 1700 + 3 + 10, 2901 .vtotal = 1700 + 3 + 10 + 36, 2902 }; 2903 2904 static const struct panel_desc lg_lp129qe = { 2905 .modes = &lg_lp129qe_mode, 2906 .num_modes = 1, 2907 .bpc = 8, 2908 .size = { 2909 .width = 272, 2910 .height = 181, 2911 }, 2912 }; 2913 2914 static const struct display_timing logictechno_lt161010_2nh_timing = { 2915 .pixelclock = { 26400000, 33300000, 46800000 }, 2916 .hactive = { 800, 800, 800 }, 2917 .hfront_porch = { 16, 210, 354 }, 2918 .hback_porch = { 46, 46, 46 }, 2919 .hsync_len = { 1, 20, 40 }, 2920 .vactive = { 480, 480, 480 }, 2921 .vfront_porch = { 7, 22, 147 }, 2922 .vback_porch = { 23, 23, 23 }, 2923 .vsync_len = { 1, 10, 20 }, 2924 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2925 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2926 DISPLAY_FLAGS_SYNC_POSEDGE, 2927 }; 2928 2929 static const struct panel_desc logictechno_lt161010_2nh = { 2930 .timings = &logictechno_lt161010_2nh_timing, 2931 .num_timings = 1, 2932 .size = { 2933 .width = 154, 2934 .height = 86, 2935 }, 2936 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2937 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2938 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2939 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2940 .connector_type = DRM_MODE_CONNECTOR_DPI, 2941 }; 2942 2943 static const struct display_timing logictechno_lt170410_2whc_timing = { 2944 .pixelclock = { 68900000, 71100000, 73400000 }, 2945 .hactive = { 1280, 1280, 1280 }, 2946 .hfront_porch = { 23, 60, 71 }, 2947 .hback_porch = { 23, 60, 71 }, 2948 .hsync_len = { 15, 40, 47 }, 2949 .vactive = { 800, 800, 800 }, 2950 .vfront_porch = { 5, 7, 10 }, 2951 .vback_porch = { 5, 7, 10 }, 2952 .vsync_len = { 6, 9, 12 }, 2953 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2954 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2955 DISPLAY_FLAGS_SYNC_POSEDGE, 2956 }; 2957 2958 static const struct panel_desc logictechno_lt170410_2whc = { 2959 .timings = &logictechno_lt170410_2whc_timing, 2960 .num_timings = 1, 2961 .size = { 2962 .width = 217, 2963 .height = 136, 2964 }, 2965 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2966 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2967 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2968 }; 2969 2970 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2971 .clock = 30400, 2972 .hdisplay = 800, 2973 .hsync_start = 800 + 0, 2974 .hsync_end = 800 + 1, 2975 .htotal = 800 + 0 + 1 + 160, 2976 .vdisplay = 480, 2977 .vsync_start = 480 + 0, 2978 .vsync_end = 480 + 48 + 1, 2979 .vtotal = 480 + 48 + 1 + 0, 2980 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2981 }; 2982 2983 static const struct drm_display_mode logicpd_type_28_mode = { 2984 .clock = 9107, 2985 .hdisplay = 480, 2986 .hsync_start = 480 + 3, 2987 .hsync_end = 480 + 3 + 42, 2988 .htotal = 480 + 3 + 42 + 2, 2989 2990 .vdisplay = 272, 2991 .vsync_start = 272 + 2, 2992 .vsync_end = 272 + 2 + 11, 2993 .vtotal = 272 + 2 + 11 + 3, 2994 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2995 }; 2996 2997 static const struct panel_desc logicpd_type_28 = { 2998 .modes = &logicpd_type_28_mode, 2999 .num_modes = 1, 3000 .bpc = 8, 3001 .size = { 3002 .width = 105, 3003 .height = 67, 3004 }, 3005 .delay = { 3006 .prepare = 200, 3007 .enable = 200, 3008 .unprepare = 200, 3009 .disable = 200, 3010 }, 3011 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3012 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3013 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3014 .connector_type = DRM_MODE_CONNECTOR_DPI, 3015 }; 3016 3017 static const struct panel_desc mitsubishi_aa070mc01 = { 3018 .modes = &mitsubishi_aa070mc01_mode, 3019 .num_modes = 1, 3020 .bpc = 8, 3021 .size = { 3022 .width = 152, 3023 .height = 91, 3024 }, 3025 3026 .delay = { 3027 .enable = 200, 3028 .unprepare = 200, 3029 .disable = 400, 3030 }, 3031 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3032 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3034 }; 3035 3036 static const struct display_timing nec_nl12880bc20_05_timing = { 3037 .pixelclock = { 67000000, 71000000, 75000000 }, 3038 .hactive = { 1280, 1280, 1280 }, 3039 .hfront_porch = { 2, 30, 30 }, 3040 .hback_porch = { 6, 100, 100 }, 3041 .hsync_len = { 2, 30, 30 }, 3042 .vactive = { 800, 800, 800 }, 3043 .vfront_porch = { 5, 5, 5 }, 3044 .vback_porch = { 11, 11, 11 }, 3045 .vsync_len = { 7, 7, 7 }, 3046 }; 3047 3048 static const struct panel_desc nec_nl12880bc20_05 = { 3049 .timings = &nec_nl12880bc20_05_timing, 3050 .num_timings = 1, 3051 .bpc = 8, 3052 .size = { 3053 .width = 261, 3054 .height = 163, 3055 }, 3056 .delay = { 3057 .enable = 50, 3058 .disable = 50, 3059 }, 3060 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3061 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3062 }; 3063 3064 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3065 .clock = 10870, 3066 .hdisplay = 480, 3067 .hsync_start = 480 + 2, 3068 .hsync_end = 480 + 2 + 41, 3069 .htotal = 480 + 2 + 41 + 2, 3070 .vdisplay = 272, 3071 .vsync_start = 272 + 2, 3072 .vsync_end = 272 + 2 + 4, 3073 .vtotal = 272 + 2 + 4 + 2, 3074 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3075 }; 3076 3077 static const struct panel_desc nec_nl4827hc19_05b = { 3078 .modes = &nec_nl4827hc19_05b_mode, 3079 .num_modes = 1, 3080 .bpc = 8, 3081 .size = { 3082 .width = 95, 3083 .height = 54, 3084 }, 3085 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3086 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3087 }; 3088 3089 static const struct drm_display_mode netron_dy_e231732_mode = { 3090 .clock = 66000, 3091 .hdisplay = 1024, 3092 .hsync_start = 1024 + 160, 3093 .hsync_end = 1024 + 160 + 70, 3094 .htotal = 1024 + 160 + 70 + 90, 3095 .vdisplay = 600, 3096 .vsync_start = 600 + 127, 3097 .vsync_end = 600 + 127 + 20, 3098 .vtotal = 600 + 127 + 20 + 3, 3099 }; 3100 3101 static const struct panel_desc netron_dy_e231732 = { 3102 .modes = &netron_dy_e231732_mode, 3103 .num_modes = 1, 3104 .size = { 3105 .width = 154, 3106 .height = 87, 3107 }, 3108 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3109 }; 3110 3111 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 3112 { 3113 .clock = 138500, 3114 .hdisplay = 1920, 3115 .hsync_start = 1920 + 48, 3116 .hsync_end = 1920 + 48 + 32, 3117 .htotal = 1920 + 48 + 32 + 80, 3118 .vdisplay = 1080, 3119 .vsync_start = 1080 + 3, 3120 .vsync_end = 1080 + 3 + 5, 3121 .vtotal = 1080 + 3 + 5 + 23, 3122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3123 }, { 3124 .clock = 110920, 3125 .hdisplay = 1920, 3126 .hsync_start = 1920 + 48, 3127 .hsync_end = 1920 + 48 + 32, 3128 .htotal = 1920 + 48 + 32 + 80, 3129 .vdisplay = 1080, 3130 .vsync_start = 1080 + 3, 3131 .vsync_end = 1080 + 3 + 5, 3132 .vtotal = 1080 + 3 + 5 + 23, 3133 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3134 } 3135 }; 3136 3137 static const struct panel_desc neweast_wjfh116008a = { 3138 .modes = neweast_wjfh116008a_modes, 3139 .num_modes = 2, 3140 .bpc = 6, 3141 .size = { 3142 .width = 260, 3143 .height = 150, 3144 }, 3145 .delay = { 3146 .prepare = 110, 3147 .enable = 20, 3148 .unprepare = 500, 3149 }, 3150 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3151 .connector_type = DRM_MODE_CONNECTOR_eDP, 3152 }; 3153 3154 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3155 .clock = 9000, 3156 .hdisplay = 480, 3157 .hsync_start = 480 + 2, 3158 .hsync_end = 480 + 2 + 41, 3159 .htotal = 480 + 2 + 41 + 2, 3160 .vdisplay = 272, 3161 .vsync_start = 272 + 2, 3162 .vsync_end = 272 + 2 + 10, 3163 .vtotal = 272 + 2 + 10 + 2, 3164 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3165 }; 3166 3167 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3168 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3169 .num_modes = 1, 3170 .bpc = 8, 3171 .size = { 3172 .width = 95, 3173 .height = 54, 3174 }, 3175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3176 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3177 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3178 .connector_type = DRM_MODE_CONNECTOR_DPI, 3179 }; 3180 3181 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3182 .pixelclock = { 130000000, 148350000, 163000000 }, 3183 .hactive = { 1920, 1920, 1920 }, 3184 .hfront_porch = { 80, 100, 100 }, 3185 .hback_porch = { 100, 120, 120 }, 3186 .hsync_len = { 50, 60, 60 }, 3187 .vactive = { 1080, 1080, 1080 }, 3188 .vfront_porch = { 12, 30, 30 }, 3189 .vback_porch = { 4, 10, 10 }, 3190 .vsync_len = { 4, 5, 5 }, 3191 }; 3192 3193 static const struct panel_desc nlt_nl192108ac18_02d = { 3194 .timings = &nlt_nl192108ac18_02d_timing, 3195 .num_timings = 1, 3196 .bpc = 8, 3197 .size = { 3198 .width = 344, 3199 .height = 194, 3200 }, 3201 .delay = { 3202 .unprepare = 500, 3203 }, 3204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3205 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3206 }; 3207 3208 static const struct drm_display_mode nvd_9128_mode = { 3209 .clock = 29500, 3210 .hdisplay = 800, 3211 .hsync_start = 800 + 130, 3212 .hsync_end = 800 + 130 + 98, 3213 .htotal = 800 + 0 + 130 + 98, 3214 .vdisplay = 480, 3215 .vsync_start = 480 + 10, 3216 .vsync_end = 480 + 10 + 50, 3217 .vtotal = 480 + 0 + 10 + 50, 3218 }; 3219 3220 static const struct panel_desc nvd_9128 = { 3221 .modes = &nvd_9128_mode, 3222 .num_modes = 1, 3223 .bpc = 8, 3224 .size = { 3225 .width = 156, 3226 .height = 88, 3227 }, 3228 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3229 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3230 }; 3231 3232 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3233 .pixelclock = { 30000000, 30000000, 40000000 }, 3234 .hactive = { 800, 800, 800 }, 3235 .hfront_porch = { 40, 40, 40 }, 3236 .hback_porch = { 40, 40, 40 }, 3237 .hsync_len = { 1, 48, 48 }, 3238 .vactive = { 480, 480, 480 }, 3239 .vfront_porch = { 13, 13, 13 }, 3240 .vback_porch = { 29, 29, 29 }, 3241 .vsync_len = { 3, 3, 3 }, 3242 .flags = DISPLAY_FLAGS_DE_HIGH, 3243 }; 3244 3245 static const struct panel_desc okaya_rs800480t_7x0gp = { 3246 .timings = &okaya_rs800480t_7x0gp_timing, 3247 .num_timings = 1, 3248 .bpc = 6, 3249 .size = { 3250 .width = 154, 3251 .height = 87, 3252 }, 3253 .delay = { 3254 .prepare = 41, 3255 .enable = 50, 3256 .unprepare = 41, 3257 .disable = 50, 3258 }, 3259 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3260 }; 3261 3262 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3263 .clock = 9000, 3264 .hdisplay = 480, 3265 .hsync_start = 480 + 5, 3266 .hsync_end = 480 + 5 + 30, 3267 .htotal = 480 + 5 + 30 + 10, 3268 .vdisplay = 272, 3269 .vsync_start = 272 + 8, 3270 .vsync_end = 272 + 8 + 5, 3271 .vtotal = 272 + 8 + 5 + 3, 3272 }; 3273 3274 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3275 .modes = &olimex_lcd_olinuxino_43ts_mode, 3276 .num_modes = 1, 3277 .size = { 3278 .width = 95, 3279 .height = 54, 3280 }, 3281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3282 }; 3283 3284 /* 3285 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3286 * pixel clocks, but this is the timing that was being used in the Adafruit 3287 * installation instructions. 3288 */ 3289 static const struct drm_display_mode ontat_yx700wv03_mode = { 3290 .clock = 29500, 3291 .hdisplay = 800, 3292 .hsync_start = 824, 3293 .hsync_end = 896, 3294 .htotal = 992, 3295 .vdisplay = 480, 3296 .vsync_start = 483, 3297 .vsync_end = 493, 3298 .vtotal = 500, 3299 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3300 }; 3301 3302 /* 3303 * Specification at: 3304 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3305 */ 3306 static const struct panel_desc ontat_yx700wv03 = { 3307 .modes = &ontat_yx700wv03_mode, 3308 .num_modes = 1, 3309 .bpc = 8, 3310 .size = { 3311 .width = 154, 3312 .height = 83, 3313 }, 3314 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3315 }; 3316 3317 static const struct drm_display_mode ortustech_com37h3m_mode = { 3318 .clock = 22230, 3319 .hdisplay = 480, 3320 .hsync_start = 480 + 40, 3321 .hsync_end = 480 + 40 + 10, 3322 .htotal = 480 + 40 + 10 + 40, 3323 .vdisplay = 640, 3324 .vsync_start = 640 + 4, 3325 .vsync_end = 640 + 4 + 2, 3326 .vtotal = 640 + 4 + 2 + 4, 3327 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3328 }; 3329 3330 static const struct panel_desc ortustech_com37h3m = { 3331 .modes = &ortustech_com37h3m_mode, 3332 .num_modes = 1, 3333 .bpc = 8, 3334 .size = { 3335 .width = 56, /* 56.16mm */ 3336 .height = 75, /* 74.88mm */ 3337 }, 3338 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3339 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3340 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3341 }; 3342 3343 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3344 .clock = 25000, 3345 .hdisplay = 480, 3346 .hsync_start = 480 + 10, 3347 .hsync_end = 480 + 10 + 10, 3348 .htotal = 480 + 10 + 10 + 15, 3349 .vdisplay = 800, 3350 .vsync_start = 800 + 3, 3351 .vsync_end = 800 + 3 + 3, 3352 .vtotal = 800 + 3 + 3 + 3, 3353 }; 3354 3355 static const struct panel_desc ortustech_com43h4m85ulc = { 3356 .modes = &ortustech_com43h4m85ulc_mode, 3357 .num_modes = 1, 3358 .bpc = 6, 3359 .size = { 3360 .width = 56, 3361 .height = 93, 3362 }, 3363 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3364 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3365 .connector_type = DRM_MODE_CONNECTOR_DPI, 3366 }; 3367 3368 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3369 .clock = 33000, 3370 .hdisplay = 800, 3371 .hsync_start = 800 + 210, 3372 .hsync_end = 800 + 210 + 30, 3373 .htotal = 800 + 210 + 30 + 16, 3374 .vdisplay = 480, 3375 .vsync_start = 480 + 22, 3376 .vsync_end = 480 + 22 + 13, 3377 .vtotal = 480 + 22 + 13 + 10, 3378 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3379 }; 3380 3381 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3382 .modes = &osddisplays_osd070t1718_19ts_mode, 3383 .num_modes = 1, 3384 .bpc = 8, 3385 .size = { 3386 .width = 152, 3387 .height = 91, 3388 }, 3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3390 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3391 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3392 .connector_type = DRM_MODE_CONNECTOR_DPI, 3393 }; 3394 3395 static const struct drm_display_mode pda_91_00156_a0_mode = { 3396 .clock = 33300, 3397 .hdisplay = 800, 3398 .hsync_start = 800 + 1, 3399 .hsync_end = 800 + 1 + 64, 3400 .htotal = 800 + 1 + 64 + 64, 3401 .vdisplay = 480, 3402 .vsync_start = 480 + 1, 3403 .vsync_end = 480 + 1 + 23, 3404 .vtotal = 480 + 1 + 23 + 22, 3405 }; 3406 3407 static const struct panel_desc pda_91_00156_a0 = { 3408 .modes = &pda_91_00156_a0_mode, 3409 .num_modes = 1, 3410 .size = { 3411 .width = 152, 3412 .height = 91, 3413 }, 3414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3415 }; 3416 3417 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3418 .clock = 24750, 3419 .hdisplay = 800, 3420 .hsync_start = 800 + 54, 3421 .hsync_end = 800 + 54 + 2, 3422 .htotal = 800 + 54 + 2 + 44, 3423 .vdisplay = 480, 3424 .vsync_start = 480 + 49, 3425 .vsync_end = 480 + 49 + 2, 3426 .vtotal = 480 + 49 + 2 + 22, 3427 }; 3428 3429 static const struct panel_desc powertip_ph800480t013_idf02 = { 3430 .modes = &powertip_ph800480t013_idf02_mode, 3431 .num_modes = 1, 3432 .size = { 3433 .width = 152, 3434 .height = 91, 3435 }, 3436 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3437 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3438 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3439 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3440 .connector_type = DRM_MODE_CONNECTOR_DPI, 3441 }; 3442 3443 static const struct drm_display_mode qd43003c0_40_mode = { 3444 .clock = 9000, 3445 .hdisplay = 480, 3446 .hsync_start = 480 + 8, 3447 .hsync_end = 480 + 8 + 4, 3448 .htotal = 480 + 8 + 4 + 39, 3449 .vdisplay = 272, 3450 .vsync_start = 272 + 4, 3451 .vsync_end = 272 + 4 + 10, 3452 .vtotal = 272 + 4 + 10 + 2, 3453 }; 3454 3455 static const struct panel_desc qd43003c0_40 = { 3456 .modes = &qd43003c0_40_mode, 3457 .num_modes = 1, 3458 .bpc = 8, 3459 .size = { 3460 .width = 95, 3461 .height = 53, 3462 }, 3463 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3464 }; 3465 3466 static const struct display_timing rocktech_rk070er9427_timing = { 3467 .pixelclock = { 26400000, 33300000, 46800000 }, 3468 .hactive = { 800, 800, 800 }, 3469 .hfront_porch = { 16, 210, 354 }, 3470 .hback_porch = { 46, 46, 46 }, 3471 .hsync_len = { 1, 1, 1 }, 3472 .vactive = { 480, 480, 480 }, 3473 .vfront_porch = { 7, 22, 147 }, 3474 .vback_porch = { 23, 23, 23 }, 3475 .vsync_len = { 1, 1, 1 }, 3476 .flags = DISPLAY_FLAGS_DE_HIGH, 3477 }; 3478 3479 static const struct panel_desc rocktech_rk070er9427 = { 3480 .timings = &rocktech_rk070er9427_timing, 3481 .num_timings = 1, 3482 .bpc = 6, 3483 .size = { 3484 .width = 154, 3485 .height = 86, 3486 }, 3487 .delay = { 3488 .prepare = 41, 3489 .enable = 50, 3490 .unprepare = 41, 3491 .disable = 50, 3492 }, 3493 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3494 }; 3495 3496 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3497 .clock = 71100, 3498 .hdisplay = 1280, 3499 .hsync_start = 1280 + 48, 3500 .hsync_end = 1280 + 48 + 32, 3501 .htotal = 1280 + 48 + 32 + 80, 3502 .vdisplay = 800, 3503 .vsync_start = 800 + 2, 3504 .vsync_end = 800 + 2 + 5, 3505 .vtotal = 800 + 2 + 5 + 16, 3506 }; 3507 3508 static const struct panel_desc rocktech_rk101ii01d_ct = { 3509 .modes = &rocktech_rk101ii01d_ct_mode, 3510 .num_modes = 1, 3511 .size = { 3512 .width = 217, 3513 .height = 136, 3514 }, 3515 .delay = { 3516 .prepare = 50, 3517 .disable = 50, 3518 }, 3519 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3520 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3522 }; 3523 3524 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3525 .clock = 271560, 3526 .hdisplay = 2560, 3527 .hsync_start = 2560 + 48, 3528 .hsync_end = 2560 + 48 + 32, 3529 .htotal = 2560 + 48 + 32 + 80, 3530 .vdisplay = 1600, 3531 .vsync_start = 1600 + 2, 3532 .vsync_end = 1600 + 2 + 5, 3533 .vtotal = 1600 + 2 + 5 + 57, 3534 }; 3535 3536 static const struct panel_desc samsung_lsn122dl01_c01 = { 3537 .modes = &samsung_lsn122dl01_c01_mode, 3538 .num_modes = 1, 3539 .size = { 3540 .width = 263, 3541 .height = 164, 3542 }, 3543 }; 3544 3545 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3546 .clock = 54030, 3547 .hdisplay = 1024, 3548 .hsync_start = 1024 + 24, 3549 .hsync_end = 1024 + 24 + 136, 3550 .htotal = 1024 + 24 + 136 + 160, 3551 .vdisplay = 600, 3552 .vsync_start = 600 + 3, 3553 .vsync_end = 600 + 3 + 6, 3554 .vtotal = 600 + 3 + 6 + 61, 3555 }; 3556 3557 static const struct panel_desc samsung_ltn101nt05 = { 3558 .modes = &samsung_ltn101nt05_mode, 3559 .num_modes = 1, 3560 .bpc = 6, 3561 .size = { 3562 .width = 223, 3563 .height = 125, 3564 }, 3565 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3566 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3567 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3568 }; 3569 3570 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3571 .clock = 76300, 3572 .hdisplay = 1366, 3573 .hsync_start = 1366 + 64, 3574 .hsync_end = 1366 + 64 + 48, 3575 .htotal = 1366 + 64 + 48 + 128, 3576 .vdisplay = 768, 3577 .vsync_start = 768 + 2, 3578 .vsync_end = 768 + 2 + 5, 3579 .vtotal = 768 + 2 + 5 + 17, 3580 }; 3581 3582 static const struct panel_desc samsung_ltn140at29_301 = { 3583 .modes = &samsung_ltn140at29_301_mode, 3584 .num_modes = 1, 3585 .bpc = 6, 3586 .size = { 3587 .width = 320, 3588 .height = 187, 3589 }, 3590 }; 3591 3592 static const struct display_timing satoz_sat050at40h12r2_timing = { 3593 .pixelclock = {33300000, 33300000, 50000000}, 3594 .hactive = {800, 800, 800}, 3595 .hfront_porch = {16, 210, 354}, 3596 .hback_porch = {46, 46, 46}, 3597 .hsync_len = {1, 1, 40}, 3598 .vactive = {480, 480, 480}, 3599 .vfront_porch = {7, 22, 147}, 3600 .vback_porch = {23, 23, 23}, 3601 .vsync_len = {1, 1, 20}, 3602 }; 3603 3604 static const struct panel_desc satoz_sat050at40h12r2 = { 3605 .timings = &satoz_sat050at40h12r2_timing, 3606 .num_timings = 1, 3607 .bpc = 8, 3608 .size = { 3609 .width = 108, 3610 .height = 65, 3611 }, 3612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3613 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3614 }; 3615 3616 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3617 .clock = 168480, 3618 .hdisplay = 1920, 3619 .hsync_start = 1920 + 48, 3620 .hsync_end = 1920 + 48 + 32, 3621 .htotal = 1920 + 48 + 32 + 80, 3622 .vdisplay = 1280, 3623 .vsync_start = 1280 + 3, 3624 .vsync_end = 1280 + 3 + 10, 3625 .vtotal = 1280 + 3 + 10 + 57, 3626 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3627 }; 3628 3629 static const struct panel_desc sharp_ld_d5116z01b = { 3630 .modes = &sharp_ld_d5116z01b_mode, 3631 .num_modes = 1, 3632 .bpc = 8, 3633 .size = { 3634 .width = 260, 3635 .height = 120, 3636 }, 3637 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3638 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3639 }; 3640 3641 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3642 .clock = 33260, 3643 .hdisplay = 800, 3644 .hsync_start = 800 + 64, 3645 .hsync_end = 800 + 64 + 128, 3646 .htotal = 800 + 64 + 128 + 64, 3647 .vdisplay = 480, 3648 .vsync_start = 480 + 8, 3649 .vsync_end = 480 + 8 + 2, 3650 .vtotal = 480 + 8 + 2 + 35, 3651 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3652 }; 3653 3654 static const struct panel_desc sharp_lq070y3dg3b = { 3655 .modes = &sharp_lq070y3dg3b_mode, 3656 .num_modes = 1, 3657 .bpc = 8, 3658 .size = { 3659 .width = 152, /* 152.4mm */ 3660 .height = 91, /* 91.4mm */ 3661 }, 3662 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3663 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3664 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3665 }; 3666 3667 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3668 .clock = 5500, 3669 .hdisplay = 240, 3670 .hsync_start = 240 + 16, 3671 .hsync_end = 240 + 16 + 7, 3672 .htotal = 240 + 16 + 7 + 5, 3673 .vdisplay = 320, 3674 .vsync_start = 320 + 9, 3675 .vsync_end = 320 + 9 + 1, 3676 .vtotal = 320 + 9 + 1 + 7, 3677 }; 3678 3679 static const struct panel_desc sharp_lq035q7db03 = { 3680 .modes = &sharp_lq035q7db03_mode, 3681 .num_modes = 1, 3682 .bpc = 6, 3683 .size = { 3684 .width = 54, 3685 .height = 72, 3686 }, 3687 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3688 }; 3689 3690 static const struct display_timing sharp_lq101k1ly04_timing = { 3691 .pixelclock = { 60000000, 65000000, 80000000 }, 3692 .hactive = { 1280, 1280, 1280 }, 3693 .hfront_porch = { 20, 20, 20 }, 3694 .hback_porch = { 20, 20, 20 }, 3695 .hsync_len = { 10, 10, 10 }, 3696 .vactive = { 800, 800, 800 }, 3697 .vfront_porch = { 4, 4, 4 }, 3698 .vback_porch = { 4, 4, 4 }, 3699 .vsync_len = { 4, 4, 4 }, 3700 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3701 }; 3702 3703 static const struct panel_desc sharp_lq101k1ly04 = { 3704 .timings = &sharp_lq101k1ly04_timing, 3705 .num_timings = 1, 3706 .bpc = 8, 3707 .size = { 3708 .width = 217, 3709 .height = 136, 3710 }, 3711 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3712 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3713 }; 3714 3715 static const struct display_timing sharp_lq123p1jx31_timing = { 3716 .pixelclock = { 252750000, 252750000, 266604720 }, 3717 .hactive = { 2400, 2400, 2400 }, 3718 .hfront_porch = { 48, 48, 48 }, 3719 .hback_porch = { 80, 80, 84 }, 3720 .hsync_len = { 32, 32, 32 }, 3721 .vactive = { 1600, 1600, 1600 }, 3722 .vfront_porch = { 3, 3, 3 }, 3723 .vback_porch = { 33, 33, 120 }, 3724 .vsync_len = { 10, 10, 10 }, 3725 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3726 }; 3727 3728 static const struct panel_desc sharp_lq123p1jx31 = { 3729 .timings = &sharp_lq123p1jx31_timing, 3730 .num_timings = 1, 3731 .bpc = 8, 3732 .size = { 3733 .width = 259, 3734 .height = 173, 3735 }, 3736 .delay = { 3737 .prepare = 110, 3738 .enable = 50, 3739 .unprepare = 550, 3740 }, 3741 }; 3742 3743 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3744 { /* 50 Hz */ 3745 .clock = 3000, 3746 .hdisplay = 240, 3747 .hsync_start = 240 + 58, 3748 .hsync_end = 240 + 58 + 1, 3749 .htotal = 240 + 58 + 1 + 1, 3750 .vdisplay = 160, 3751 .vsync_start = 160 + 24, 3752 .vsync_end = 160 + 24 + 10, 3753 .vtotal = 160 + 24 + 10 + 6, 3754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3755 }, 3756 { /* 60 Hz */ 3757 .clock = 3000, 3758 .hdisplay = 240, 3759 .hsync_start = 240 + 8, 3760 .hsync_end = 240 + 8 + 1, 3761 .htotal = 240 + 8 + 1 + 1, 3762 .vdisplay = 160, 3763 .vsync_start = 160 + 24, 3764 .vsync_end = 160 + 24 + 10, 3765 .vtotal = 160 + 24 + 10 + 6, 3766 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3767 }, 3768 }; 3769 3770 static const struct panel_desc sharp_ls020b1dd01d = { 3771 .modes = sharp_ls020b1dd01d_modes, 3772 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3773 .bpc = 6, 3774 .size = { 3775 .width = 42, 3776 .height = 28, 3777 }, 3778 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3779 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3780 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3781 | DRM_BUS_FLAG_SHARP_SIGNALS, 3782 }; 3783 3784 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3785 .clock = 33300, 3786 .hdisplay = 800, 3787 .hsync_start = 800 + 1, 3788 .hsync_end = 800 + 1 + 64, 3789 .htotal = 800 + 1 + 64 + 64, 3790 .vdisplay = 480, 3791 .vsync_start = 480 + 1, 3792 .vsync_end = 480 + 1 + 23, 3793 .vtotal = 480 + 1 + 23 + 22, 3794 }; 3795 3796 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3797 .modes = &shelly_sca07010_bfn_lnn_mode, 3798 .num_modes = 1, 3799 .size = { 3800 .width = 152, 3801 .height = 91, 3802 }, 3803 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3804 }; 3805 3806 static const struct drm_display_mode starry_kr070pe2t_mode = { 3807 .clock = 33000, 3808 .hdisplay = 800, 3809 .hsync_start = 800 + 209, 3810 .hsync_end = 800 + 209 + 1, 3811 .htotal = 800 + 209 + 1 + 45, 3812 .vdisplay = 480, 3813 .vsync_start = 480 + 22, 3814 .vsync_end = 480 + 22 + 1, 3815 .vtotal = 480 + 22 + 1 + 22, 3816 }; 3817 3818 static const struct panel_desc starry_kr070pe2t = { 3819 .modes = &starry_kr070pe2t_mode, 3820 .num_modes = 1, 3821 .bpc = 8, 3822 .size = { 3823 .width = 152, 3824 .height = 86, 3825 }, 3826 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3828 .connector_type = DRM_MODE_CONNECTOR_DPI, 3829 }; 3830 3831 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3832 .clock = 147000, 3833 .hdisplay = 1920, 3834 .hsync_start = 1920 + 16, 3835 .hsync_end = 1920 + 16 + 16, 3836 .htotal = 1920 + 16 + 16 + 32, 3837 .vdisplay = 1200, 3838 .vsync_start = 1200 + 15, 3839 .vsync_end = 1200 + 15 + 2, 3840 .vtotal = 1200 + 15 + 2 + 18, 3841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3842 }; 3843 3844 static const struct panel_desc starry_kr122ea0sra = { 3845 .modes = &starry_kr122ea0sra_mode, 3846 .num_modes = 1, 3847 .size = { 3848 .width = 263, 3849 .height = 164, 3850 }, 3851 .delay = { 3852 .prepare = 10 + 200, 3853 .enable = 50, 3854 .unprepare = 10 + 500, 3855 }, 3856 }; 3857 3858 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3859 .clock = 30000, 3860 .hdisplay = 800, 3861 .hsync_start = 800 + 39, 3862 .hsync_end = 800 + 39 + 47, 3863 .htotal = 800 + 39 + 47 + 39, 3864 .vdisplay = 480, 3865 .vsync_start = 480 + 13, 3866 .vsync_end = 480 + 13 + 2, 3867 .vtotal = 480 + 13 + 2 + 29, 3868 }; 3869 3870 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3871 .modes = &tfc_s9700rtwv43tr_01b_mode, 3872 .num_modes = 1, 3873 .bpc = 8, 3874 .size = { 3875 .width = 155, 3876 .height = 90, 3877 }, 3878 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3879 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3880 }; 3881 3882 static const struct display_timing tianma_tm070jdhg30_timing = { 3883 .pixelclock = { 62600000, 68200000, 78100000 }, 3884 .hactive = { 1280, 1280, 1280 }, 3885 .hfront_porch = { 15, 64, 159 }, 3886 .hback_porch = { 5, 5, 5 }, 3887 .hsync_len = { 1, 1, 256 }, 3888 .vactive = { 800, 800, 800 }, 3889 .vfront_porch = { 3, 40, 99 }, 3890 .vback_porch = { 2, 2, 2 }, 3891 .vsync_len = { 1, 1, 128 }, 3892 .flags = DISPLAY_FLAGS_DE_HIGH, 3893 }; 3894 3895 static const struct panel_desc tianma_tm070jdhg30 = { 3896 .timings = &tianma_tm070jdhg30_timing, 3897 .num_timings = 1, 3898 .bpc = 8, 3899 .size = { 3900 .width = 151, 3901 .height = 95, 3902 }, 3903 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3904 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3905 }; 3906 3907 static const struct panel_desc tianma_tm070jvhg33 = { 3908 .timings = &tianma_tm070jdhg30_timing, 3909 .num_timings = 1, 3910 .bpc = 8, 3911 .size = { 3912 .width = 150, 3913 .height = 94, 3914 }, 3915 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3916 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3917 }; 3918 3919 static const struct display_timing tianma_tm070rvhg71_timing = { 3920 .pixelclock = { 27700000, 29200000, 39600000 }, 3921 .hactive = { 800, 800, 800 }, 3922 .hfront_porch = { 12, 40, 212 }, 3923 .hback_porch = { 88, 88, 88 }, 3924 .hsync_len = { 1, 1, 40 }, 3925 .vactive = { 480, 480, 480 }, 3926 .vfront_porch = { 1, 13, 88 }, 3927 .vback_porch = { 32, 32, 32 }, 3928 .vsync_len = { 1, 1, 3 }, 3929 .flags = DISPLAY_FLAGS_DE_HIGH, 3930 }; 3931 3932 static const struct panel_desc tianma_tm070rvhg71 = { 3933 .timings = &tianma_tm070rvhg71_timing, 3934 .num_timings = 1, 3935 .bpc = 8, 3936 .size = { 3937 .width = 154, 3938 .height = 86, 3939 }, 3940 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3941 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3942 }; 3943 3944 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3945 { 3946 .clock = 10000, 3947 .hdisplay = 320, 3948 .hsync_start = 320 + 50, 3949 .hsync_end = 320 + 50 + 6, 3950 .htotal = 320 + 50 + 6 + 38, 3951 .vdisplay = 240, 3952 .vsync_start = 240 + 3, 3953 .vsync_end = 240 + 3 + 1, 3954 .vtotal = 240 + 3 + 1 + 17, 3955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3956 }, 3957 }; 3958 3959 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3960 .modes = ti_nspire_cx_lcd_mode, 3961 .num_modes = 1, 3962 .bpc = 8, 3963 .size = { 3964 .width = 65, 3965 .height = 49, 3966 }, 3967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3968 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3969 }; 3970 3971 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3972 { 3973 .clock = 10000, 3974 .hdisplay = 320, 3975 .hsync_start = 320 + 6, 3976 .hsync_end = 320 + 6 + 6, 3977 .htotal = 320 + 6 + 6 + 6, 3978 .vdisplay = 240, 3979 .vsync_start = 240 + 0, 3980 .vsync_end = 240 + 0 + 1, 3981 .vtotal = 240 + 0 + 1 + 0, 3982 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3983 }, 3984 }; 3985 3986 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3987 .modes = ti_nspire_classic_lcd_mode, 3988 .num_modes = 1, 3989 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3990 .bpc = 8, 3991 .size = { 3992 .width = 71, 3993 .height = 53, 3994 }, 3995 /* This is the grayscale bus format */ 3996 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3997 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3998 }; 3999 4000 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4001 .clock = 79500, 4002 .hdisplay = 1280, 4003 .hsync_start = 1280 + 192, 4004 .hsync_end = 1280 + 192 + 128, 4005 .htotal = 1280 + 192 + 128 + 64, 4006 .vdisplay = 768, 4007 .vsync_start = 768 + 20, 4008 .vsync_end = 768 + 20 + 7, 4009 .vtotal = 768 + 20 + 7 + 3, 4010 }; 4011 4012 static const struct panel_desc toshiba_lt089ac29000 = { 4013 .modes = &toshiba_lt089ac29000_mode, 4014 .num_modes = 1, 4015 .size = { 4016 .width = 194, 4017 .height = 116, 4018 }, 4019 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4020 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4021 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4022 }; 4023 4024 static const struct drm_display_mode tpk_f07a_0102_mode = { 4025 .clock = 33260, 4026 .hdisplay = 800, 4027 .hsync_start = 800 + 40, 4028 .hsync_end = 800 + 40 + 128, 4029 .htotal = 800 + 40 + 128 + 88, 4030 .vdisplay = 480, 4031 .vsync_start = 480 + 10, 4032 .vsync_end = 480 + 10 + 2, 4033 .vtotal = 480 + 10 + 2 + 33, 4034 }; 4035 4036 static const struct panel_desc tpk_f07a_0102 = { 4037 .modes = &tpk_f07a_0102_mode, 4038 .num_modes = 1, 4039 .size = { 4040 .width = 152, 4041 .height = 91, 4042 }, 4043 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4044 }; 4045 4046 static const struct drm_display_mode tpk_f10a_0102_mode = { 4047 .clock = 45000, 4048 .hdisplay = 1024, 4049 .hsync_start = 1024 + 176, 4050 .hsync_end = 1024 + 176 + 5, 4051 .htotal = 1024 + 176 + 5 + 88, 4052 .vdisplay = 600, 4053 .vsync_start = 600 + 20, 4054 .vsync_end = 600 + 20 + 5, 4055 .vtotal = 600 + 20 + 5 + 25, 4056 }; 4057 4058 static const struct panel_desc tpk_f10a_0102 = { 4059 .modes = &tpk_f10a_0102_mode, 4060 .num_modes = 1, 4061 .size = { 4062 .width = 223, 4063 .height = 125, 4064 }, 4065 }; 4066 4067 static const struct display_timing urt_umsh_8596md_timing = { 4068 .pixelclock = { 33260000, 33260000, 33260000 }, 4069 .hactive = { 800, 800, 800 }, 4070 .hfront_porch = { 41, 41, 41 }, 4071 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4072 .hsync_len = { 71, 128, 128 }, 4073 .vactive = { 480, 480, 480 }, 4074 .vfront_porch = { 10, 10, 10 }, 4075 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4076 .vsync_len = { 2, 2, 2 }, 4077 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4078 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4079 }; 4080 4081 static const struct panel_desc urt_umsh_8596md_lvds = { 4082 .timings = &urt_umsh_8596md_timing, 4083 .num_timings = 1, 4084 .bpc = 6, 4085 .size = { 4086 .width = 152, 4087 .height = 91, 4088 }, 4089 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4090 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4091 }; 4092 4093 static const struct panel_desc urt_umsh_8596md_parallel = { 4094 .timings = &urt_umsh_8596md_timing, 4095 .num_timings = 1, 4096 .bpc = 6, 4097 .size = { 4098 .width = 152, 4099 .height = 91, 4100 }, 4101 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4102 }; 4103 4104 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4105 .clock = 33333, 4106 .hdisplay = 800, 4107 .hsync_start = 800 + 210, 4108 .hsync_end = 800 + 210 + 20, 4109 .htotal = 800 + 210 + 20 + 46, 4110 .vdisplay = 480, 4111 .vsync_start = 480 + 22, 4112 .vsync_end = 480 + 22 + 10, 4113 .vtotal = 480 + 22 + 10 + 23, 4114 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4115 }; 4116 4117 static const struct panel_desc vl050_8048nt_c01 = { 4118 .modes = &vl050_8048nt_c01_mode, 4119 .num_modes = 1, 4120 .bpc = 8, 4121 .size = { 4122 .width = 120, 4123 .height = 76, 4124 }, 4125 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4126 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4127 }; 4128 4129 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4130 .clock = 6410, 4131 .hdisplay = 320, 4132 .hsync_start = 320 + 20, 4133 .hsync_end = 320 + 20 + 30, 4134 .htotal = 320 + 20 + 30 + 38, 4135 .vdisplay = 240, 4136 .vsync_start = 240 + 4, 4137 .vsync_end = 240 + 4 + 3, 4138 .vtotal = 240 + 4 + 3 + 15, 4139 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4140 }; 4141 4142 static const struct panel_desc winstar_wf35ltiacd = { 4143 .modes = &winstar_wf35ltiacd_mode, 4144 .num_modes = 1, 4145 .bpc = 8, 4146 .size = { 4147 .width = 70, 4148 .height = 53, 4149 }, 4150 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4151 }; 4152 4153 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4154 .clock = 51200, 4155 .hdisplay = 1024, 4156 .hsync_start = 1024 + 100, 4157 .hsync_end = 1024 + 100 + 100, 4158 .htotal = 1024 + 100 + 100 + 120, 4159 .vdisplay = 600, 4160 .vsync_start = 600 + 10, 4161 .vsync_end = 600 + 10 + 10, 4162 .vtotal = 600 + 10 + 10 + 15, 4163 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4164 }; 4165 4166 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4167 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4168 .num_modes = 1, 4169 .bpc = 6, 4170 .size = { 4171 .width = 154, 4172 .height = 90, 4173 }, 4174 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4177 }; 4178 4179 static const struct drm_display_mode arm_rtsm_mode[] = { 4180 { 4181 .clock = 65000, 4182 .hdisplay = 1024, 4183 .hsync_start = 1024 + 24, 4184 .hsync_end = 1024 + 24 + 136, 4185 .htotal = 1024 + 24 + 136 + 160, 4186 .vdisplay = 768, 4187 .vsync_start = 768 + 3, 4188 .vsync_end = 768 + 3 + 6, 4189 .vtotal = 768 + 3 + 6 + 29, 4190 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4191 }, 4192 }; 4193 4194 static const struct panel_desc arm_rtsm = { 4195 .modes = arm_rtsm_mode, 4196 .num_modes = 1, 4197 .bpc = 8, 4198 .size = { 4199 .width = 400, 4200 .height = 300, 4201 }, 4202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4203 }; 4204 4205 static const struct of_device_id platform_of_match[] = { 4206 { 4207 .compatible = "ampire,am-1280800n3tzqw-t00h", 4208 .data = &ire_am_1280800n3tzqw_t00h, 4209 }, { 4210 .compatible = "ampire,am-480272h3tmqw-t01h", 4211 .data = &ire_am_480272h3tmqw_t01h, 4212 }, { 4213 .compatible = "ampire,am800480r3tmqwa1h", 4214 .data = &ire_am800480r3tmqwa1h, 4215 }, { 4216 .compatible = "arm,rtsm-display", 4217 .data = &arm_rtsm, 4218 }, { 4219 .compatible = "armadeus,st0700-adapt", 4220 .data = &armadeus_st0700_adapt, 4221 }, { 4222 .compatible = "auo,b101aw03", 4223 .data = &auo_b101aw03, 4224 }, { 4225 .compatible = "auo,b101ean01", 4226 .data = &auo_b101ean01, 4227 }, { 4228 .compatible = "auo,b101xtn01", 4229 .data = &auo_b101xtn01, 4230 }, { 4231 .compatible = "auo,b116xa01", 4232 .data = &auo_b116xak01, 4233 }, { 4234 .compatible = "auo,b116xw03", 4235 .data = &auo_b116xw03, 4236 }, { 4237 .compatible = "auo,b133htn01", 4238 .data = &auo_b133htn01, 4239 }, { 4240 .compatible = "auo,b133xtn01", 4241 .data = &auo_b133xtn01, 4242 }, { 4243 .compatible = "auo,g070vvn01", 4244 .data = &auo_g070vvn01, 4245 }, { 4246 .compatible = "auo,g101evn010", 4247 .data = &auo_g101evn010, 4248 }, { 4249 .compatible = "auo,g104sn02", 4250 .data = &auo_g104sn02, 4251 }, { 4252 .compatible = "auo,g121ean01", 4253 .data = &auo_g121ean01, 4254 }, { 4255 .compatible = "auo,g133han01", 4256 .data = &auo_g133han01, 4257 }, { 4258 .compatible = "auo,g156xtn01", 4259 .data = &auo_g156xtn01, 4260 }, { 4261 .compatible = "auo,g185han01", 4262 .data = &auo_g185han01, 4263 }, { 4264 .compatible = "auo,g190ean01", 4265 .data = &auo_g190ean01, 4266 }, { 4267 .compatible = "auo,p320hvn03", 4268 .data = &auo_p320hvn03, 4269 }, { 4270 .compatible = "auo,t215hvn01", 4271 .data = &auo_t215hvn01, 4272 }, { 4273 .compatible = "avic,tm070ddh03", 4274 .data = &avic_tm070ddh03, 4275 }, { 4276 .compatible = "bananapi,s070wv20-ct16", 4277 .data = &bananapi_s070wv20_ct16, 4278 }, { 4279 .compatible = "boe,hv070wsa-100", 4280 .data = &boe_hv070wsa 4281 }, { 4282 .compatible = "boe,nv101wxmn51", 4283 .data = &boe_nv101wxmn51, 4284 }, { 4285 .compatible = "boe,nv110wtm-n61", 4286 .data = &boe_nv110wtm_n61, 4287 }, { 4288 .compatible = "boe,nv133fhm-n61", 4289 .data = &boe_nv133fhm_n61, 4290 }, { 4291 .compatible = "boe,nv133fhm-n62", 4292 .data = &boe_nv133fhm_n61, 4293 }, { 4294 .compatible = "boe,nv140fhmn49", 4295 .data = &boe_nv140fhmn49, 4296 }, { 4297 .compatible = "cdtech,s043wq26h-ct7", 4298 .data = &cdtech_s043wq26h_ct7, 4299 }, { 4300 .compatible = "cdtech,s070pws19hp-fc21", 4301 .data = &cdtech_s070pws19hp_fc21, 4302 }, { 4303 .compatible = "cdtech,s070swv29hg-dc44", 4304 .data = &cdtech_s070swv29hg_dc44, 4305 }, { 4306 .compatible = "cdtech,s070wv95-ct16", 4307 .data = &cdtech_s070wv95_ct16, 4308 }, { 4309 .compatible = "chefree,ch101olhlwh-002", 4310 .data = &chefree_ch101olhlwh_002, 4311 }, { 4312 .compatible = "chunghwa,claa070wp03xg", 4313 .data = &chunghwa_claa070wp03xg, 4314 }, { 4315 .compatible = "chunghwa,claa101wa01a", 4316 .data = &chunghwa_claa101wa01a 4317 }, { 4318 .compatible = "chunghwa,claa101wb01", 4319 .data = &chunghwa_claa101wb01 4320 }, { 4321 .compatible = "dataimage,scf0700c48ggu18", 4322 .data = &dataimage_scf0700c48ggu18, 4323 }, { 4324 .compatible = "dlc,dlc0700yzg-1", 4325 .data = &dlc_dlc0700yzg_1, 4326 }, { 4327 .compatible = "dlc,dlc1010gig", 4328 .data = &dlc_dlc1010gig, 4329 }, { 4330 .compatible = "edt,et035012dm6", 4331 .data = &edt_et035012dm6, 4332 }, { 4333 .compatible = "edt,etm043080dh6gp", 4334 .data = &edt_etm043080dh6gp, 4335 }, { 4336 .compatible = "edt,etm0430g0dh6", 4337 .data = &edt_etm0430g0dh6, 4338 }, { 4339 .compatible = "edt,et057090dhu", 4340 .data = &edt_et057090dhu, 4341 }, { 4342 .compatible = "edt,et070080dh6", 4343 .data = &edt_etm0700g0dh6, 4344 }, { 4345 .compatible = "edt,etm0700g0dh6", 4346 .data = &edt_etm0700g0dh6, 4347 }, { 4348 .compatible = "edt,etm0700g0bdh6", 4349 .data = &edt_etm0700g0bdh6, 4350 }, { 4351 .compatible = "edt,etm0700g0edh6", 4352 .data = &edt_etm0700g0bdh6, 4353 }, { 4354 .compatible = "evervision,vgg804821", 4355 .data = &evervision_vgg804821, 4356 }, { 4357 .compatible = "foxlink,fl500wvr00-a0t", 4358 .data = &foxlink_fl500wvr00_a0t, 4359 }, { 4360 .compatible = "frida,frd350h54004", 4361 .data = &frida_frd350h54004, 4362 }, { 4363 .compatible = "friendlyarm,hd702e", 4364 .data = &friendlyarm_hd702e, 4365 }, { 4366 .compatible = "giantplus,gpg482739qs5", 4367 .data = &giantplus_gpg482739qs5 4368 }, { 4369 .compatible = "giantplus,gpm940b0", 4370 .data = &giantplus_gpm940b0, 4371 }, { 4372 .compatible = "hannstar,hsd070pww1", 4373 .data = &hannstar_hsd070pww1, 4374 }, { 4375 .compatible = "hannstar,hsd100pxn1", 4376 .data = &hannstar_hsd100pxn1, 4377 }, { 4378 .compatible = "hit,tx23d38vm0caa", 4379 .data = &hitachi_tx23d38vm0caa 4380 }, { 4381 .compatible = "innolux,at043tn24", 4382 .data = &innolux_at043tn24, 4383 }, { 4384 .compatible = "innolux,at070tn92", 4385 .data = &innolux_at070tn92, 4386 }, { 4387 .compatible = "innolux,g070y2-l01", 4388 .data = &innolux_g070y2_l01, 4389 }, { 4390 .compatible = "innolux,g101ice-l01", 4391 .data = &innolux_g101ice_l01 4392 }, { 4393 .compatible = "innolux,g121i1-l01", 4394 .data = &innolux_g121i1_l01 4395 }, { 4396 .compatible = "innolux,g121x1-l03", 4397 .data = &innolux_g121x1_l03, 4398 }, { 4399 .compatible = "innolux,n116bca-ea1", 4400 .data = &innolux_n116bca_ea1, 4401 }, { 4402 .compatible = "innolux,n116bge", 4403 .data = &innolux_n116bge, 4404 }, { 4405 .compatible = "innolux,n125hce-gn1", 4406 .data = &innolux_n125hce_gn1, 4407 }, { 4408 .compatible = "innolux,n156bge-l21", 4409 .data = &innolux_n156bge_l21, 4410 }, { 4411 .compatible = "innolux,p120zdg-bf1", 4412 .data = &innolux_p120zdg_bf1, 4413 }, { 4414 .compatible = "innolux,zj070na-01p", 4415 .data = &innolux_zj070na_01p, 4416 }, { 4417 .compatible = "ivo,m133nwf4-r0", 4418 .data = &ivo_m133nwf4_r0, 4419 }, { 4420 .compatible = "kingdisplay,kd116n21-30nv-a010", 4421 .data = &kingdisplay_kd116n21_30nv_a010, 4422 }, { 4423 .compatible = "koe,tx14d24vm1bpa", 4424 .data = &koe_tx14d24vm1bpa, 4425 }, { 4426 .compatible = "koe,tx26d202vm0bwa", 4427 .data = &koe_tx26d202vm0bwa, 4428 }, { 4429 .compatible = "koe,tx31d200vm0baa", 4430 .data = &koe_tx31d200vm0baa, 4431 }, { 4432 .compatible = "kyo,tcg121xglp", 4433 .data = &kyo_tcg121xglp, 4434 }, { 4435 .compatible = "lemaker,bl035-rgb-002", 4436 .data = &lemaker_bl035_rgb_002, 4437 }, { 4438 .compatible = "lg,lb070wv8", 4439 .data = &lg_lb070wv8, 4440 }, { 4441 .compatible = "lg,lp079qx1-sp0v", 4442 .data = &lg_lp079qx1_sp0v, 4443 }, { 4444 .compatible = "lg,lp097qx1-spa1", 4445 .data = &lg_lp097qx1_spa1, 4446 }, { 4447 .compatible = "lg,lp120up1", 4448 .data = &lg_lp120up1, 4449 }, { 4450 .compatible = "lg,lp129qe", 4451 .data = &lg_lp129qe, 4452 }, { 4453 .compatible = "logicpd,type28", 4454 .data = &logicpd_type_28, 4455 }, { 4456 .compatible = "logictechno,lt161010-2nhc", 4457 .data = &logictechno_lt161010_2nh, 4458 }, { 4459 .compatible = "logictechno,lt161010-2nhr", 4460 .data = &logictechno_lt161010_2nh, 4461 }, { 4462 .compatible = "logictechno,lt170410-2whc", 4463 .data = &logictechno_lt170410_2whc, 4464 }, { 4465 .compatible = "mitsubishi,aa070mc01-ca1", 4466 .data = &mitsubishi_aa070mc01, 4467 }, { 4468 .compatible = "nec,nl12880bc20-05", 4469 .data = &nec_nl12880bc20_05, 4470 }, { 4471 .compatible = "nec,nl4827hc19-05b", 4472 .data = &nec_nl4827hc19_05b, 4473 }, { 4474 .compatible = "netron-dy,e231732", 4475 .data = &netron_dy_e231732, 4476 }, { 4477 .compatible = "neweast,wjfh116008a", 4478 .data = &neweast_wjfh116008a, 4479 }, { 4480 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4481 .data = &newhaven_nhd_43_480272ef_atxl, 4482 }, { 4483 .compatible = "nlt,nl192108ac18-02d", 4484 .data = &nlt_nl192108ac18_02d, 4485 }, { 4486 .compatible = "nvd,9128", 4487 .data = &nvd_9128, 4488 }, { 4489 .compatible = "okaya,rs800480t-7x0gp", 4490 .data = &okaya_rs800480t_7x0gp, 4491 }, { 4492 .compatible = "olimex,lcd-olinuxino-43-ts", 4493 .data = &olimex_lcd_olinuxino_43ts, 4494 }, { 4495 .compatible = "ontat,yx700wv03", 4496 .data = &ontat_yx700wv03, 4497 }, { 4498 .compatible = "ortustech,com37h3m05dtc", 4499 .data = &ortustech_com37h3m, 4500 }, { 4501 .compatible = "ortustech,com37h3m99dtc", 4502 .data = &ortustech_com37h3m, 4503 }, { 4504 .compatible = "ortustech,com43h4m85ulc", 4505 .data = &ortustech_com43h4m85ulc, 4506 }, { 4507 .compatible = "osddisplays,osd070t1718-19ts", 4508 .data = &osddisplays_osd070t1718_19ts, 4509 }, { 4510 .compatible = "pda,91-00156-a0", 4511 .data = &pda_91_00156_a0, 4512 }, { 4513 .compatible = "powertip,ph800480t013-idf02", 4514 .data = &powertip_ph800480t013_idf02, 4515 }, { 4516 .compatible = "qiaodian,qd43003c0-40", 4517 .data = &qd43003c0_40, 4518 }, { 4519 .compatible = "rocktech,rk070er9427", 4520 .data = &rocktech_rk070er9427, 4521 }, { 4522 .compatible = "rocktech,rk101ii01d-ct", 4523 .data = &rocktech_rk101ii01d_ct, 4524 }, { 4525 .compatible = "samsung,lsn122dl01-c01", 4526 .data = &samsung_lsn122dl01_c01, 4527 }, { 4528 .compatible = "samsung,ltn101nt05", 4529 .data = &samsung_ltn101nt05, 4530 }, { 4531 .compatible = "samsung,ltn140at29-301", 4532 .data = &samsung_ltn140at29_301, 4533 }, { 4534 .compatible = "satoz,sat050at40h12r2", 4535 .data = &satoz_sat050at40h12r2, 4536 }, { 4537 .compatible = "sharp,ld-d5116z01b", 4538 .data = &sharp_ld_d5116z01b, 4539 }, { 4540 .compatible = "sharp,lq035q7db03", 4541 .data = &sharp_lq035q7db03, 4542 }, { 4543 .compatible = "sharp,lq070y3dg3b", 4544 .data = &sharp_lq070y3dg3b, 4545 }, { 4546 .compatible = "sharp,lq101k1ly04", 4547 .data = &sharp_lq101k1ly04, 4548 }, { 4549 .compatible = "sharp,lq123p1jx31", 4550 .data = &sharp_lq123p1jx31, 4551 }, { 4552 .compatible = "sharp,ls020b1dd01d", 4553 .data = &sharp_ls020b1dd01d, 4554 }, { 4555 .compatible = "shelly,sca07010-bfn-lnn", 4556 .data = &shelly_sca07010_bfn_lnn, 4557 }, { 4558 .compatible = "starry,kr070pe2t", 4559 .data = &starry_kr070pe2t, 4560 }, { 4561 .compatible = "starry,kr122ea0sra", 4562 .data = &starry_kr122ea0sra, 4563 }, { 4564 .compatible = "tfc,s9700rtwv43tr-01b", 4565 .data = &tfc_s9700rtwv43tr_01b, 4566 }, { 4567 .compatible = "tianma,tm070jdhg30", 4568 .data = &tianma_tm070jdhg30, 4569 }, { 4570 .compatible = "tianma,tm070jvhg33", 4571 .data = &tianma_tm070jvhg33, 4572 }, { 4573 .compatible = "tianma,tm070rvhg71", 4574 .data = &tianma_tm070rvhg71, 4575 }, { 4576 .compatible = "ti,nspire-cx-lcd-panel", 4577 .data = &ti_nspire_cx_lcd_panel, 4578 }, { 4579 .compatible = "ti,nspire-classic-lcd-panel", 4580 .data = &ti_nspire_classic_lcd_panel, 4581 }, { 4582 .compatible = "toshiba,lt089ac29000", 4583 .data = &toshiba_lt089ac29000, 4584 }, { 4585 .compatible = "tpk,f07a-0102", 4586 .data = &tpk_f07a_0102, 4587 }, { 4588 .compatible = "tpk,f10a-0102", 4589 .data = &tpk_f10a_0102, 4590 }, { 4591 .compatible = "urt,umsh-8596md-t", 4592 .data = &urt_umsh_8596md_parallel, 4593 }, { 4594 .compatible = "urt,umsh-8596md-1t", 4595 .data = &urt_umsh_8596md_parallel, 4596 }, { 4597 .compatible = "urt,umsh-8596md-7t", 4598 .data = &urt_umsh_8596md_parallel, 4599 }, { 4600 .compatible = "urt,umsh-8596md-11t", 4601 .data = &urt_umsh_8596md_lvds, 4602 }, { 4603 .compatible = "urt,umsh-8596md-19t", 4604 .data = &urt_umsh_8596md_lvds, 4605 }, { 4606 .compatible = "urt,umsh-8596md-20t", 4607 .data = &urt_umsh_8596md_parallel, 4608 }, { 4609 .compatible = "vxt,vl050-8048nt-c01", 4610 .data = &vl050_8048nt_c01, 4611 }, { 4612 .compatible = "winstar,wf35ltiacd", 4613 .data = &winstar_wf35ltiacd, 4614 }, { 4615 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4616 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4617 }, { 4618 /* Must be the last entry */ 4619 .compatible = "panel-dpi", 4620 .data = &panel_dpi, 4621 }, { 4622 /* sentinel */ 4623 } 4624 }; 4625 MODULE_DEVICE_TABLE(of, platform_of_match); 4626 4627 static int panel_simple_platform_probe(struct platform_device *pdev) 4628 { 4629 const struct of_device_id *id; 4630 4631 id = of_match_node(platform_of_match, pdev->dev.of_node); 4632 if (!id) 4633 return -ENODEV; 4634 4635 return panel_simple_probe(&pdev->dev, id->data); 4636 } 4637 4638 static int panel_simple_platform_remove(struct platform_device *pdev) 4639 { 4640 return panel_simple_remove(&pdev->dev); 4641 } 4642 4643 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4644 { 4645 panel_simple_shutdown(&pdev->dev); 4646 } 4647 4648 static const struct dev_pm_ops panel_simple_pm_ops = { 4649 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4650 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4651 pm_runtime_force_resume) 4652 }; 4653 4654 static struct platform_driver panel_simple_platform_driver = { 4655 .driver = { 4656 .name = "panel-simple", 4657 .of_match_table = platform_of_match, 4658 .pm = &panel_simple_pm_ops, 4659 }, 4660 .probe = panel_simple_platform_probe, 4661 .remove = panel_simple_platform_remove, 4662 .shutdown = panel_simple_platform_shutdown, 4663 }; 4664 4665 struct panel_desc_dsi { 4666 struct panel_desc desc; 4667 4668 unsigned long flags; 4669 enum mipi_dsi_pixel_format format; 4670 unsigned int lanes; 4671 }; 4672 4673 static const struct drm_display_mode auo_b080uan01_mode = { 4674 .clock = 154500, 4675 .hdisplay = 1200, 4676 .hsync_start = 1200 + 62, 4677 .hsync_end = 1200 + 62 + 4, 4678 .htotal = 1200 + 62 + 4 + 62, 4679 .vdisplay = 1920, 4680 .vsync_start = 1920 + 9, 4681 .vsync_end = 1920 + 9 + 2, 4682 .vtotal = 1920 + 9 + 2 + 8, 4683 }; 4684 4685 static const struct panel_desc_dsi auo_b080uan01 = { 4686 .desc = { 4687 .modes = &auo_b080uan01_mode, 4688 .num_modes = 1, 4689 .bpc = 8, 4690 .size = { 4691 .width = 108, 4692 .height = 272, 4693 }, 4694 .connector_type = DRM_MODE_CONNECTOR_DSI, 4695 }, 4696 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4697 .format = MIPI_DSI_FMT_RGB888, 4698 .lanes = 4, 4699 }; 4700 4701 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4702 .clock = 160000, 4703 .hdisplay = 1200, 4704 .hsync_start = 1200 + 120, 4705 .hsync_end = 1200 + 120 + 20, 4706 .htotal = 1200 + 120 + 20 + 21, 4707 .vdisplay = 1920, 4708 .vsync_start = 1920 + 21, 4709 .vsync_end = 1920 + 21 + 3, 4710 .vtotal = 1920 + 21 + 3 + 18, 4711 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4712 }; 4713 4714 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4715 .desc = { 4716 .modes = &boe_tv080wum_nl0_mode, 4717 .num_modes = 1, 4718 .size = { 4719 .width = 107, 4720 .height = 172, 4721 }, 4722 .connector_type = DRM_MODE_CONNECTOR_DSI, 4723 }, 4724 .flags = MIPI_DSI_MODE_VIDEO | 4725 MIPI_DSI_MODE_VIDEO_BURST | 4726 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4727 .format = MIPI_DSI_FMT_RGB888, 4728 .lanes = 4, 4729 }; 4730 4731 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4732 .clock = 71000, 4733 .hdisplay = 800, 4734 .hsync_start = 800 + 32, 4735 .hsync_end = 800 + 32 + 1, 4736 .htotal = 800 + 32 + 1 + 57, 4737 .vdisplay = 1280, 4738 .vsync_start = 1280 + 28, 4739 .vsync_end = 1280 + 28 + 1, 4740 .vtotal = 1280 + 28 + 1 + 14, 4741 }; 4742 4743 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4744 .desc = { 4745 .modes = &lg_ld070wx3_sl01_mode, 4746 .num_modes = 1, 4747 .bpc = 8, 4748 .size = { 4749 .width = 94, 4750 .height = 151, 4751 }, 4752 .connector_type = DRM_MODE_CONNECTOR_DSI, 4753 }, 4754 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4755 .format = MIPI_DSI_FMT_RGB888, 4756 .lanes = 4, 4757 }; 4758 4759 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4760 .clock = 67000, 4761 .hdisplay = 720, 4762 .hsync_start = 720 + 12, 4763 .hsync_end = 720 + 12 + 4, 4764 .htotal = 720 + 12 + 4 + 112, 4765 .vdisplay = 1280, 4766 .vsync_start = 1280 + 8, 4767 .vsync_end = 1280 + 8 + 4, 4768 .vtotal = 1280 + 8 + 4 + 12, 4769 }; 4770 4771 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4772 .desc = { 4773 .modes = &lg_lh500wx1_sd03_mode, 4774 .num_modes = 1, 4775 .bpc = 8, 4776 .size = { 4777 .width = 62, 4778 .height = 110, 4779 }, 4780 .connector_type = DRM_MODE_CONNECTOR_DSI, 4781 }, 4782 .flags = MIPI_DSI_MODE_VIDEO, 4783 .format = MIPI_DSI_FMT_RGB888, 4784 .lanes = 4, 4785 }; 4786 4787 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4788 .clock = 157200, 4789 .hdisplay = 1920, 4790 .hsync_start = 1920 + 154, 4791 .hsync_end = 1920 + 154 + 16, 4792 .htotal = 1920 + 154 + 16 + 32, 4793 .vdisplay = 1200, 4794 .vsync_start = 1200 + 17, 4795 .vsync_end = 1200 + 17 + 2, 4796 .vtotal = 1200 + 17 + 2 + 16, 4797 }; 4798 4799 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4800 .desc = { 4801 .modes = &panasonic_vvx10f004b00_mode, 4802 .num_modes = 1, 4803 .bpc = 8, 4804 .size = { 4805 .width = 217, 4806 .height = 136, 4807 }, 4808 .connector_type = DRM_MODE_CONNECTOR_DSI, 4809 }, 4810 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4811 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4812 .format = MIPI_DSI_FMT_RGB888, 4813 .lanes = 4, 4814 }; 4815 4816 static const struct drm_display_mode lg_acx467akm_7_mode = { 4817 .clock = 150000, 4818 .hdisplay = 1080, 4819 .hsync_start = 1080 + 2, 4820 .hsync_end = 1080 + 2 + 2, 4821 .htotal = 1080 + 2 + 2 + 2, 4822 .vdisplay = 1920, 4823 .vsync_start = 1920 + 2, 4824 .vsync_end = 1920 + 2 + 2, 4825 .vtotal = 1920 + 2 + 2 + 2, 4826 }; 4827 4828 static const struct panel_desc_dsi lg_acx467akm_7 = { 4829 .desc = { 4830 .modes = &lg_acx467akm_7_mode, 4831 .num_modes = 1, 4832 .bpc = 8, 4833 .size = { 4834 .width = 62, 4835 .height = 110, 4836 }, 4837 .connector_type = DRM_MODE_CONNECTOR_DSI, 4838 }, 4839 .flags = 0, 4840 .format = MIPI_DSI_FMT_RGB888, 4841 .lanes = 4, 4842 }; 4843 4844 static const struct drm_display_mode osd101t2045_53ts_mode = { 4845 .clock = 154500, 4846 .hdisplay = 1920, 4847 .hsync_start = 1920 + 112, 4848 .hsync_end = 1920 + 112 + 16, 4849 .htotal = 1920 + 112 + 16 + 32, 4850 .vdisplay = 1200, 4851 .vsync_start = 1200 + 16, 4852 .vsync_end = 1200 + 16 + 2, 4853 .vtotal = 1200 + 16 + 2 + 16, 4854 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4855 }; 4856 4857 static const struct panel_desc_dsi osd101t2045_53ts = { 4858 .desc = { 4859 .modes = &osd101t2045_53ts_mode, 4860 .num_modes = 1, 4861 .bpc = 8, 4862 .size = { 4863 .width = 217, 4864 .height = 136, 4865 }, 4866 .connector_type = DRM_MODE_CONNECTOR_DSI, 4867 }, 4868 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4869 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4870 MIPI_DSI_MODE_EOT_PACKET, 4871 .format = MIPI_DSI_FMT_RGB888, 4872 .lanes = 4, 4873 }; 4874 4875 static const struct of_device_id dsi_of_match[] = { 4876 { 4877 .compatible = "auo,b080uan01", 4878 .data = &auo_b080uan01 4879 }, { 4880 .compatible = "boe,tv080wum-nl0", 4881 .data = &boe_tv080wum_nl0 4882 }, { 4883 .compatible = "lg,ld070wx3-sl01", 4884 .data = &lg_ld070wx3_sl01 4885 }, { 4886 .compatible = "lg,lh500wx1-sd03", 4887 .data = &lg_lh500wx1_sd03 4888 }, { 4889 .compatible = "panasonic,vvx10f004b00", 4890 .data = &panasonic_vvx10f004b00 4891 }, { 4892 .compatible = "lg,acx467akm-7", 4893 .data = &lg_acx467akm_7 4894 }, { 4895 .compatible = "osddisplays,osd101t2045-53ts", 4896 .data = &osd101t2045_53ts 4897 }, { 4898 /* sentinel */ 4899 } 4900 }; 4901 MODULE_DEVICE_TABLE(of, dsi_of_match); 4902 4903 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4904 { 4905 const struct panel_desc_dsi *desc; 4906 const struct of_device_id *id; 4907 int err; 4908 4909 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4910 if (!id) 4911 return -ENODEV; 4912 4913 desc = id->data; 4914 4915 err = panel_simple_probe(&dsi->dev, &desc->desc); 4916 if (err < 0) 4917 return err; 4918 4919 dsi->mode_flags = desc->flags; 4920 dsi->format = desc->format; 4921 dsi->lanes = desc->lanes; 4922 4923 err = mipi_dsi_attach(dsi); 4924 if (err) { 4925 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4926 4927 drm_panel_remove(&panel->base); 4928 } 4929 4930 return err; 4931 } 4932 4933 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4934 { 4935 int err; 4936 4937 err = mipi_dsi_detach(dsi); 4938 if (err < 0) 4939 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4940 4941 return panel_simple_remove(&dsi->dev); 4942 } 4943 4944 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4945 { 4946 panel_simple_shutdown(&dsi->dev); 4947 } 4948 4949 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4950 .driver = { 4951 .name = "panel-simple-dsi", 4952 .of_match_table = dsi_of_match, 4953 .pm = &panel_simple_pm_ops, 4954 }, 4955 .probe = panel_simple_dsi_probe, 4956 .remove = panel_simple_dsi_remove, 4957 .shutdown = panel_simple_dsi_shutdown, 4958 }; 4959 4960 static int __init panel_simple_init(void) 4961 { 4962 int err; 4963 4964 err = platform_driver_register(&panel_simple_platform_driver); 4965 if (err < 0) 4966 return err; 4967 4968 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4969 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4970 if (err < 0) { 4971 platform_driver_unregister(&panel_simple_platform_driver); 4972 return err; 4973 } 4974 } 4975 4976 return 0; 4977 } 4978 module_init(panel_simple_init); 4979 4980 static void __exit panel_simple_exit(void) 4981 { 4982 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4983 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4984 4985 platform_driver_unregister(&panel_simple_platform_driver); 4986 } 4987 module_exit(panel_simple_exit); 4988 4989 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4990 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4991 MODULE_LICENSE("GPL and additional rights"); 4992