1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, 167 drm_mode_vrefresh(m)); 168 continue; 169 } 170 171 mode->type |= DRM_MODE_TYPE_DRIVER; 172 173 if (panel->desc->num_modes == 1) 174 mode->type |= DRM_MODE_TYPE_PREFERRED; 175 176 drm_mode_set_name(mode); 177 178 drm_mode_probed_add(connector, mode); 179 num++; 180 } 181 182 return num; 183 } 184 185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 186 struct drm_connector *connector) 187 { 188 struct drm_display_mode *mode; 189 bool has_override = panel->override_mode.type; 190 unsigned int num = 0; 191 192 if (!panel->desc) 193 return 0; 194 195 if (has_override) { 196 mode = drm_mode_duplicate(connector->dev, 197 &panel->override_mode); 198 if (mode) { 199 drm_mode_probed_add(connector, mode); 200 num = 1; 201 } else { 202 dev_err(panel->base.dev, "failed to add override mode\n"); 203 } 204 } 205 206 /* Only add timings if override was not there or failed to validate */ 207 if (num == 0 && panel->desc->num_timings) 208 num = panel_simple_get_timings_modes(panel, connector); 209 210 /* 211 * Only add fixed modes if timings/override added no mode. 212 * 213 * We should only ever have either the display timings specified 214 * or a fixed mode. Anything else is rather bogus. 215 */ 216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 217 if (num == 0) 218 num = panel_simple_get_display_modes(panel, connector); 219 220 connector->display_info.bpc = panel->desc->bpc; 221 connector->display_info.width_mm = panel->desc->size.width; 222 connector->display_info.height_mm = panel->desc->size.height; 223 if (panel->desc->bus_format) 224 drm_display_info_set_bus_formats(&connector->display_info, 225 &panel->desc->bus_format, 1); 226 connector->display_info.bus_flags = panel->desc->bus_flags; 227 228 return num; 229 } 230 231 static int panel_simple_disable(struct drm_panel *panel) 232 { 233 struct panel_simple *p = to_panel_simple(panel); 234 235 if (!p->enabled) 236 return 0; 237 238 if (p->desc->delay.disable) 239 msleep(p->desc->delay.disable); 240 241 p->enabled = false; 242 243 return 0; 244 } 245 246 static int panel_simple_unprepare(struct drm_panel *panel) 247 { 248 struct panel_simple *p = to_panel_simple(panel); 249 250 if (!p->prepared) 251 return 0; 252 253 gpiod_set_value_cansleep(p->enable_gpio, 0); 254 255 regulator_disable(p->supply); 256 257 if (p->desc->delay.unprepare) 258 msleep(p->desc->delay.unprepare); 259 260 p->prepared = false; 261 262 return 0; 263 } 264 265 static int panel_simple_get_hpd_gpio(struct device *dev, 266 struct panel_simple *p, bool from_probe) 267 { 268 int err; 269 270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 271 if (IS_ERR(p->hpd_gpio)) { 272 err = PTR_ERR(p->hpd_gpio); 273 274 /* 275 * If we're called from probe we won't consider '-EPROBE_DEFER' 276 * to be an error--we'll leave the error code in "hpd_gpio". 277 * When we try to use it we'll try again. This allows for 278 * circular dependencies where the component providing the 279 * hpd gpio needs the panel to init before probing. 280 */ 281 if (err != -EPROBE_DEFER || !from_probe) { 282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 283 return err; 284 } 285 } 286 287 return 0; 288 } 289 290 static int panel_simple_prepare(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 unsigned int delay; 294 int err; 295 int hpd_asserted; 296 297 if (p->prepared) 298 return 0; 299 300 err = regulator_enable(p->supply); 301 if (err < 0) { 302 dev_err(panel->dev, "failed to enable supply: %d\n", err); 303 return err; 304 } 305 306 gpiod_set_value_cansleep(p->enable_gpio, 1); 307 308 delay = p->desc->delay.prepare; 309 if (p->no_hpd) 310 delay += p->desc->delay.hpd_absent_delay; 311 if (delay) 312 msleep(delay); 313 314 if (p->hpd_gpio) { 315 if (IS_ERR(p->hpd_gpio)) { 316 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 317 if (err) 318 return err; 319 } 320 321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 322 hpd_asserted, hpd_asserted, 323 1000, 2000000); 324 if (hpd_asserted < 0) 325 err = hpd_asserted; 326 327 if (err) { 328 dev_err(panel->dev, 329 "error waiting for hpd GPIO: %d\n", err); 330 return err; 331 } 332 } 333 334 p->prepared = true; 335 336 return 0; 337 } 338 339 static int panel_simple_enable(struct drm_panel *panel) 340 { 341 struct panel_simple *p = to_panel_simple(panel); 342 343 if (p->enabled) 344 return 0; 345 346 if (p->desc->delay.enable) 347 msleep(p->desc->delay.enable); 348 349 p->enabled = true; 350 351 return 0; 352 } 353 354 static int panel_simple_get_modes(struct drm_panel *panel, 355 struct drm_connector *connector) 356 { 357 struct panel_simple *p = to_panel_simple(panel); 358 int num = 0; 359 360 /* probe EDID if a DDC bus is available */ 361 if (p->ddc) { 362 struct edid *edid = drm_get_edid(connector, p->ddc); 363 364 drm_connector_update_edid_property(connector, edid); 365 if (edid) { 366 num += drm_add_edid_modes(connector, edid); 367 kfree(edid); 368 } 369 } 370 371 /* add hard-coded panel modes */ 372 num += panel_simple_get_non_edid_modes(p, connector); 373 374 return num; 375 } 376 377 static int panel_simple_get_timings(struct drm_panel *panel, 378 unsigned int num_timings, 379 struct display_timing *timings) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 unsigned int i; 383 384 if (p->desc->num_timings < num_timings) 385 num_timings = p->desc->num_timings; 386 387 if (timings) 388 for (i = 0; i < num_timings; i++) 389 timings[i] = p->desc->timings[i]; 390 391 return p->desc->num_timings; 392 } 393 394 static const struct drm_panel_funcs panel_simple_funcs = { 395 .disable = panel_simple_disable, 396 .unprepare = panel_simple_unprepare, 397 .prepare = panel_simple_prepare, 398 .enable = panel_simple_enable, 399 .get_modes = panel_simple_get_modes, 400 .get_timings = panel_simple_get_timings, 401 }; 402 403 static struct panel_desc panel_dpi; 404 405 static int panel_dpi_probe(struct device *dev, 406 struct panel_simple *panel) 407 { 408 struct display_timing *timing; 409 const struct device_node *np; 410 struct panel_desc *desc; 411 unsigned int bus_flags; 412 struct videomode vm; 413 int ret; 414 415 np = dev->of_node; 416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 417 if (!desc) 418 return -ENOMEM; 419 420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 421 if (!timing) 422 return -ENOMEM; 423 424 ret = of_get_display_timing(np, "panel-timing", timing); 425 if (ret < 0) { 426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 427 np); 428 return ret; 429 } 430 431 desc->timings = timing; 432 desc->num_timings = 1; 433 434 of_property_read_u32(np, "width-mm", &desc->size.width); 435 of_property_read_u32(np, "height-mm", &desc->size.height); 436 437 /* Extract bus_flags from display_timing */ 438 bus_flags = 0; 439 vm.flags = timing->flags; 440 drm_bus_flags_from_videomode(&vm, &bus_flags); 441 desc->bus_flags = bus_flags; 442 443 /* We do not know the connector for the DT node, so guess it */ 444 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 445 446 panel->desc = desc; 447 448 return 0; 449 } 450 451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 452 (to_check->field.typ >= bounds->field.min && \ 453 to_check->field.typ <= bounds->field.max) 454 static void panel_simple_parse_panel_timing_node(struct device *dev, 455 struct panel_simple *panel, 456 const struct display_timing *ot) 457 { 458 const struct panel_desc *desc = panel->desc; 459 struct videomode vm; 460 unsigned int i; 461 462 if (WARN_ON(desc->num_modes)) { 463 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 464 return; 465 } 466 if (WARN_ON(!desc->num_timings)) { 467 dev_err(dev, "Reject override mode: no timings specified\n"); 468 return; 469 } 470 471 for (i = 0; i < panel->desc->num_timings; i++) { 472 const struct display_timing *dt = &panel->desc->timings[i]; 473 474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 482 continue; 483 484 if (ot->flags != dt->flags) 485 continue; 486 487 videomode_from_timing(ot, &vm); 488 drm_display_mode_from_videomode(&vm, &panel->override_mode); 489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 490 DRM_MODE_TYPE_PREFERRED; 491 break; 492 } 493 494 if (WARN_ON(!panel->override_mode.type)) 495 dev_err(dev, "Reject override mode: No display_timing found\n"); 496 } 497 498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 499 { 500 struct panel_simple *panel; 501 struct display_timing dt; 502 struct device_node *ddc; 503 int connector_type; 504 u32 bus_flags; 505 int err; 506 507 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 508 if (!panel) 509 return -ENOMEM; 510 511 panel->enabled = false; 512 panel->prepared = false; 513 panel->desc = desc; 514 515 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 516 if (!panel->no_hpd) { 517 err = panel_simple_get_hpd_gpio(dev, panel, true); 518 if (err) 519 return err; 520 } 521 522 panel->supply = devm_regulator_get(dev, "power"); 523 if (IS_ERR(panel->supply)) 524 return PTR_ERR(panel->supply); 525 526 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 527 GPIOD_OUT_LOW); 528 if (IS_ERR(panel->enable_gpio)) { 529 err = PTR_ERR(panel->enable_gpio); 530 if (err != -EPROBE_DEFER) 531 dev_err(dev, "failed to request GPIO: %d\n", err); 532 return err; 533 } 534 535 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 536 if (ddc) { 537 panel->ddc = of_find_i2c_adapter_by_node(ddc); 538 of_node_put(ddc); 539 540 if (!panel->ddc) 541 return -EPROBE_DEFER; 542 } 543 544 if (desc == &panel_dpi) { 545 /* Handle the generic panel-dpi binding */ 546 err = panel_dpi_probe(dev, panel); 547 if (err) 548 goto free_ddc; 549 } else { 550 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 551 panel_simple_parse_panel_timing_node(dev, panel, &dt); 552 } 553 554 connector_type = desc->connector_type; 555 /* Catch common mistakes for panels. */ 556 switch (connector_type) { 557 case 0: 558 dev_warn(dev, "Specify missing connector_type\n"); 559 connector_type = DRM_MODE_CONNECTOR_DPI; 560 break; 561 case DRM_MODE_CONNECTOR_LVDS: 562 WARN_ON(desc->bus_flags & 563 ~(DRM_BUS_FLAG_DE_LOW | 564 DRM_BUS_FLAG_DE_HIGH | 565 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 566 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 567 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 568 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 569 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 570 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 571 desc->bpc != 6); 572 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 573 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 574 desc->bpc != 8); 575 break; 576 case DRM_MODE_CONNECTOR_eDP: 577 if (desc->bus_format == 0) 578 dev_warn(dev, "Specify missing bus_format\n"); 579 if (desc->bpc != 6 && desc->bpc != 8) 580 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 581 break; 582 case DRM_MODE_CONNECTOR_DSI: 583 if (desc->bpc != 6 && desc->bpc != 8) 584 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 585 break; 586 case DRM_MODE_CONNECTOR_DPI: 587 bus_flags = DRM_BUS_FLAG_DE_LOW | 588 DRM_BUS_FLAG_DE_HIGH | 589 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 590 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 591 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 592 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 593 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 594 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 595 if (desc->bus_flags & ~bus_flags) 596 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 597 if (!(desc->bus_flags & bus_flags)) 598 dev_warn(dev, "Specify missing bus_flags\n"); 599 if (desc->bus_format == 0) 600 dev_warn(dev, "Specify missing bus_format\n"); 601 if (desc->bpc != 6 && desc->bpc != 8) 602 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 603 break; 604 default: 605 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 606 connector_type = DRM_MODE_CONNECTOR_DPI; 607 break; 608 } 609 610 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 611 612 err = drm_panel_of_backlight(&panel->base); 613 if (err) 614 goto free_ddc; 615 616 drm_panel_add(&panel->base); 617 618 dev_set_drvdata(dev, panel); 619 620 return 0; 621 622 free_ddc: 623 if (panel->ddc) 624 put_device(&panel->ddc->dev); 625 626 return err; 627 } 628 629 static int panel_simple_remove(struct device *dev) 630 { 631 struct panel_simple *panel = dev_get_drvdata(dev); 632 633 drm_panel_remove(&panel->base); 634 drm_panel_disable(&panel->base); 635 drm_panel_unprepare(&panel->base); 636 637 if (panel->ddc) 638 put_device(&panel->ddc->dev); 639 640 return 0; 641 } 642 643 static void panel_simple_shutdown(struct device *dev) 644 { 645 struct panel_simple *panel = dev_get_drvdata(dev); 646 647 drm_panel_disable(&panel->base); 648 drm_panel_unprepare(&panel->base); 649 } 650 651 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 652 .clock = 9000, 653 .hdisplay = 480, 654 .hsync_start = 480 + 2, 655 .hsync_end = 480 + 2 + 41, 656 .htotal = 480 + 2 + 41 + 2, 657 .vdisplay = 272, 658 .vsync_start = 272 + 2, 659 .vsync_end = 272 + 2 + 10, 660 .vtotal = 272 + 2 + 10 + 2, 661 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 662 }; 663 664 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 665 .modes = &ire_am_480272h3tmqw_t01h_mode, 666 .num_modes = 1, 667 .bpc = 8, 668 .size = { 669 .width = 105, 670 .height = 67, 671 }, 672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 673 }; 674 675 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 676 .clock = 33333, 677 .hdisplay = 800, 678 .hsync_start = 800 + 0, 679 .hsync_end = 800 + 0 + 255, 680 .htotal = 800 + 0 + 255 + 0, 681 .vdisplay = 480, 682 .vsync_start = 480 + 2, 683 .vsync_end = 480 + 2 + 45, 684 .vtotal = 480 + 2 + 45 + 0, 685 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 686 }; 687 688 static const struct panel_desc ampire_am800480r3tmqwa1h = { 689 .modes = &ire_am800480r3tmqwa1h_mode, 690 .num_modes = 1, 691 .bpc = 6, 692 .size = { 693 .width = 152, 694 .height = 91, 695 }, 696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 697 }; 698 699 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 700 .pixelclock = { 26400000, 33300000, 46800000 }, 701 .hactive = { 800, 800, 800 }, 702 .hfront_porch = { 16, 210, 354 }, 703 .hback_porch = { 45, 36, 6 }, 704 .hsync_len = { 1, 10, 40 }, 705 .vactive = { 480, 480, 480 }, 706 .vfront_porch = { 7, 22, 147 }, 707 .vback_porch = { 22, 13, 3 }, 708 .vsync_len = { 1, 10, 20 }, 709 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 710 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 711 }; 712 713 static const struct panel_desc armadeus_st0700_adapt = { 714 .timings = &santek_st0700i5y_rbslw_f_timing, 715 .num_timings = 1, 716 .bpc = 6, 717 .size = { 718 .width = 154, 719 .height = 86, 720 }, 721 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 722 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 723 }; 724 725 static const struct drm_display_mode auo_b101aw03_mode = { 726 .clock = 51450, 727 .hdisplay = 1024, 728 .hsync_start = 1024 + 156, 729 .hsync_end = 1024 + 156 + 8, 730 .htotal = 1024 + 156 + 8 + 156, 731 .vdisplay = 600, 732 .vsync_start = 600 + 16, 733 .vsync_end = 600 + 16 + 6, 734 .vtotal = 600 + 16 + 6 + 16, 735 }; 736 737 static const struct panel_desc auo_b101aw03 = { 738 .modes = &auo_b101aw03_mode, 739 .num_modes = 1, 740 .bpc = 6, 741 .size = { 742 .width = 223, 743 .height = 125, 744 }, 745 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 746 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 748 }; 749 750 static const struct display_timing auo_b101ean01_timing = { 751 .pixelclock = { 65300000, 72500000, 75000000 }, 752 .hactive = { 1280, 1280, 1280 }, 753 .hfront_porch = { 18, 119, 119 }, 754 .hback_porch = { 21, 21, 21 }, 755 .hsync_len = { 32, 32, 32 }, 756 .vactive = { 800, 800, 800 }, 757 .vfront_porch = { 4, 4, 4 }, 758 .vback_porch = { 8, 8, 8 }, 759 .vsync_len = { 18, 20, 20 }, 760 }; 761 762 static const struct panel_desc auo_b101ean01 = { 763 .timings = &auo_b101ean01_timing, 764 .num_timings = 1, 765 .bpc = 6, 766 .size = { 767 .width = 217, 768 .height = 136, 769 }, 770 }; 771 772 static const struct drm_display_mode auo_b101xtn01_mode = { 773 .clock = 72000, 774 .hdisplay = 1366, 775 .hsync_start = 1366 + 20, 776 .hsync_end = 1366 + 20 + 70, 777 .htotal = 1366 + 20 + 70, 778 .vdisplay = 768, 779 .vsync_start = 768 + 14, 780 .vsync_end = 768 + 14 + 42, 781 .vtotal = 768 + 14 + 42, 782 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 783 }; 784 785 static const struct panel_desc auo_b101xtn01 = { 786 .modes = &auo_b101xtn01_mode, 787 .num_modes = 1, 788 .bpc = 6, 789 .size = { 790 .width = 223, 791 .height = 125, 792 }, 793 }; 794 795 static const struct drm_display_mode auo_b116xak01_mode = { 796 .clock = 69300, 797 .hdisplay = 1366, 798 .hsync_start = 1366 + 48, 799 .hsync_end = 1366 + 48 + 32, 800 .htotal = 1366 + 48 + 32 + 10, 801 .vdisplay = 768, 802 .vsync_start = 768 + 4, 803 .vsync_end = 768 + 4 + 6, 804 .vtotal = 768 + 4 + 6 + 15, 805 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 806 }; 807 808 static const struct panel_desc auo_b116xak01 = { 809 .modes = &auo_b116xak01_mode, 810 .num_modes = 1, 811 .bpc = 6, 812 .size = { 813 .width = 256, 814 .height = 144, 815 }, 816 .delay = { 817 .hpd_absent_delay = 200, 818 }, 819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 820 .connector_type = DRM_MODE_CONNECTOR_eDP, 821 }; 822 823 static const struct drm_display_mode auo_b116xw03_mode = { 824 .clock = 70589, 825 .hdisplay = 1366, 826 .hsync_start = 1366 + 40, 827 .hsync_end = 1366 + 40 + 40, 828 .htotal = 1366 + 40 + 40 + 32, 829 .vdisplay = 768, 830 .vsync_start = 768 + 10, 831 .vsync_end = 768 + 10 + 12, 832 .vtotal = 768 + 10 + 12 + 6, 833 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 834 }; 835 836 static const struct panel_desc auo_b116xw03 = { 837 .modes = &auo_b116xw03_mode, 838 .num_modes = 1, 839 .bpc = 6, 840 .size = { 841 .width = 256, 842 .height = 144, 843 }, 844 .delay = { 845 .enable = 400, 846 }, 847 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 848 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 849 .connector_type = DRM_MODE_CONNECTOR_eDP, 850 }; 851 852 static const struct drm_display_mode auo_b133xtn01_mode = { 853 .clock = 69500, 854 .hdisplay = 1366, 855 .hsync_start = 1366 + 48, 856 .hsync_end = 1366 + 48 + 32, 857 .htotal = 1366 + 48 + 32 + 20, 858 .vdisplay = 768, 859 .vsync_start = 768 + 3, 860 .vsync_end = 768 + 3 + 6, 861 .vtotal = 768 + 3 + 6 + 13, 862 }; 863 864 static const struct panel_desc auo_b133xtn01 = { 865 .modes = &auo_b133xtn01_mode, 866 .num_modes = 1, 867 .bpc = 6, 868 .size = { 869 .width = 293, 870 .height = 165, 871 }, 872 }; 873 874 static const struct drm_display_mode auo_b133htn01_mode = { 875 .clock = 150660, 876 .hdisplay = 1920, 877 .hsync_start = 1920 + 172, 878 .hsync_end = 1920 + 172 + 80, 879 .htotal = 1920 + 172 + 80 + 60, 880 .vdisplay = 1080, 881 .vsync_start = 1080 + 25, 882 .vsync_end = 1080 + 25 + 10, 883 .vtotal = 1080 + 25 + 10 + 10, 884 }; 885 886 static const struct panel_desc auo_b133htn01 = { 887 .modes = &auo_b133htn01_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 293, 892 .height = 165, 893 }, 894 .delay = { 895 .prepare = 105, 896 .enable = 20, 897 .unprepare = 50, 898 }, 899 }; 900 901 static const struct display_timing auo_g070vvn01_timings = { 902 .pixelclock = { 33300000, 34209000, 45000000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 20, 40, 200 }, 905 .hback_porch = { 87, 40, 1 }, 906 .hsync_len = { 1, 48, 87 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 5, 13, 200 }, 909 .vback_porch = { 31, 31, 29 }, 910 .vsync_len = { 1, 1, 3 }, 911 }; 912 913 static const struct panel_desc auo_g070vvn01 = { 914 .timings = &auo_g070vvn01_timings, 915 .num_timings = 1, 916 .bpc = 8, 917 .size = { 918 .width = 152, 919 .height = 91, 920 }, 921 .delay = { 922 .prepare = 200, 923 .enable = 50, 924 .disable = 50, 925 .unprepare = 1000, 926 }, 927 }; 928 929 static const struct drm_display_mode auo_g101evn010_mode = { 930 .clock = 68930, 931 .hdisplay = 1280, 932 .hsync_start = 1280 + 82, 933 .hsync_end = 1280 + 82 + 2, 934 .htotal = 1280 + 82 + 2 + 84, 935 .vdisplay = 800, 936 .vsync_start = 800 + 8, 937 .vsync_end = 800 + 8 + 2, 938 .vtotal = 800 + 8 + 2 + 6, 939 }; 940 941 static const struct panel_desc auo_g101evn010 = { 942 .modes = &auo_g101evn010_mode, 943 .num_modes = 1, 944 .bpc = 6, 945 .size = { 946 .width = 216, 947 .height = 135, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 950 .connector_type = DRM_MODE_CONNECTOR_LVDS, 951 }; 952 953 static const struct drm_display_mode auo_g104sn02_mode = { 954 .clock = 40000, 955 .hdisplay = 800, 956 .hsync_start = 800 + 40, 957 .hsync_end = 800 + 40 + 216, 958 .htotal = 800 + 40 + 216 + 128, 959 .vdisplay = 600, 960 .vsync_start = 600 + 10, 961 .vsync_end = 600 + 10 + 35, 962 .vtotal = 600 + 10 + 35 + 2, 963 }; 964 965 static const struct panel_desc auo_g104sn02 = { 966 .modes = &auo_g104sn02_mode, 967 .num_modes = 1, 968 .bpc = 8, 969 .size = { 970 .width = 211, 971 .height = 158, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_g121ean01_mode = { 976 .clock = 66700, 977 .hdisplay = 1280, 978 .hsync_start = 1280 + 58, 979 .hsync_end = 1280 + 58 + 8, 980 .htotal = 1280 + 58 + 8 + 70, 981 .vdisplay = 800, 982 .vsync_start = 800 + 6, 983 .vsync_end = 800 + 6 + 4, 984 .vtotal = 800 + 6 + 4 + 10, 985 }; 986 987 static const struct panel_desc auo_g121ean01 = { 988 .modes = &auo_g121ean01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 261, 993 .height = 163, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g133han01_timings = { 1000 .pixelclock = { 134000000, 141200000, 149000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 39, 58, 77 }, 1003 .hback_porch = { 59, 88, 117 }, 1004 .hsync_len = { 28, 42, 56 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 3, 8, 11 }, 1007 .vback_porch = { 5, 14, 19 }, 1008 .vsync_len = { 4, 14, 19 }, 1009 }; 1010 1011 static const struct panel_desc auo_g133han01 = { 1012 .timings = &auo_g133han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 293, 1017 .height = 165, 1018 }, 1019 .delay = { 1020 .prepare = 200, 1021 .enable = 50, 1022 .disable = 50, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct drm_display_mode auo_g156xtn01_mode = { 1030 .clock = 76000, 1031 .hdisplay = 1366, 1032 .hsync_start = 1366 + 33, 1033 .hsync_end = 1366 + 33 + 67, 1034 .htotal = 1560, 1035 .vdisplay = 768, 1036 .vsync_start = 768 + 4, 1037 .vsync_end = 768 + 4 + 4, 1038 .vtotal = 806, 1039 }; 1040 1041 static const struct panel_desc auo_g156xtn01 = { 1042 .modes = &auo_g156xtn01_mode, 1043 .num_modes = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 344, 1047 .height = 194, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1051 }; 1052 1053 static const struct display_timing auo_g185han01_timings = { 1054 .pixelclock = { 120000000, 144000000, 175000000 }, 1055 .hactive = { 1920, 1920, 1920 }, 1056 .hfront_porch = { 36, 120, 148 }, 1057 .hback_porch = { 24, 88, 108 }, 1058 .hsync_len = { 20, 48, 64 }, 1059 .vactive = { 1080, 1080, 1080 }, 1060 .vfront_porch = { 6, 10, 40 }, 1061 .vback_porch = { 2, 5, 20 }, 1062 .vsync_len = { 2, 5, 20 }, 1063 }; 1064 1065 static const struct panel_desc auo_g185han01 = { 1066 .timings = &auo_g185han01_timings, 1067 .num_timings = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 409, 1071 .height = 230, 1072 }, 1073 .delay = { 1074 .prepare = 50, 1075 .enable = 200, 1076 .disable = 110, 1077 .unprepare = 1000, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g190ean01_timings = { 1084 .pixelclock = { 90000000, 108000000, 135000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 126, 184, 1266 }, 1087 .hback_porch = { 84, 122, 844 }, 1088 .hsync_len = { 70, 102, 704 }, 1089 .vactive = { 1024, 1024, 1024 }, 1090 .vfront_porch = { 4, 26, 76 }, 1091 .vback_porch = { 2, 8, 25 }, 1092 .vsync_len = { 2, 8, 25 }, 1093 }; 1094 1095 static const struct panel_desc auo_g190ean01 = { 1096 .timings = &auo_g190ean01_timings, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 376, 1101 .height = 301, 1102 }, 1103 .delay = { 1104 .prepare = 50, 1105 .enable = 200, 1106 .disable = 110, 1107 .unprepare = 1000, 1108 }, 1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1111 }; 1112 1113 static const struct display_timing auo_p320hvn03_timings = { 1114 .pixelclock = { 106000000, 148500000, 164000000 }, 1115 .hactive = { 1920, 1920, 1920 }, 1116 .hfront_porch = { 25, 50, 130 }, 1117 .hback_porch = { 25, 50, 130 }, 1118 .hsync_len = { 20, 40, 105 }, 1119 .vactive = { 1080, 1080, 1080 }, 1120 .vfront_porch = { 8, 17, 150 }, 1121 .vback_porch = { 8, 17, 150 }, 1122 .vsync_len = { 4, 11, 100 }, 1123 }; 1124 1125 static const struct panel_desc auo_p320hvn03 = { 1126 .timings = &auo_p320hvn03_timings, 1127 .num_timings = 1, 1128 .bpc = 8, 1129 .size = { 1130 .width = 698, 1131 .height = 393, 1132 }, 1133 .delay = { 1134 .prepare = 1, 1135 .enable = 450, 1136 .unprepare = 500, 1137 }, 1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1139 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1140 }; 1141 1142 static const struct drm_display_mode auo_t215hvn01_mode = { 1143 .clock = 148800, 1144 .hdisplay = 1920, 1145 .hsync_start = 1920 + 88, 1146 .hsync_end = 1920 + 88 + 44, 1147 .htotal = 1920 + 88 + 44 + 148, 1148 .vdisplay = 1080, 1149 .vsync_start = 1080 + 4, 1150 .vsync_end = 1080 + 4 + 5, 1151 .vtotal = 1080 + 4 + 5 + 36, 1152 }; 1153 1154 static const struct panel_desc auo_t215hvn01 = { 1155 .modes = &auo_t215hvn01_mode, 1156 .num_modes = 1, 1157 .bpc = 8, 1158 .size = { 1159 .width = 430, 1160 .height = 270, 1161 }, 1162 .delay = { 1163 .disable = 5, 1164 .unprepare = 1000, 1165 } 1166 }; 1167 1168 static const struct drm_display_mode avic_tm070ddh03_mode = { 1169 .clock = 51200, 1170 .hdisplay = 1024, 1171 .hsync_start = 1024 + 160, 1172 .hsync_end = 1024 + 160 + 4, 1173 .htotal = 1024 + 160 + 4 + 156, 1174 .vdisplay = 600, 1175 .vsync_start = 600 + 17, 1176 .vsync_end = 600 + 17 + 1, 1177 .vtotal = 600 + 17 + 1 + 17, 1178 }; 1179 1180 static const struct panel_desc avic_tm070ddh03 = { 1181 .modes = &avic_tm070ddh03_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 154, 1186 .height = 90, 1187 }, 1188 .delay = { 1189 .prepare = 20, 1190 .enable = 200, 1191 .disable = 200, 1192 }, 1193 }; 1194 1195 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1196 .clock = 30000, 1197 .hdisplay = 800, 1198 .hsync_start = 800 + 40, 1199 .hsync_end = 800 + 40 + 48, 1200 .htotal = 800 + 40 + 48 + 40, 1201 .vdisplay = 480, 1202 .vsync_start = 480 + 13, 1203 .vsync_end = 480 + 13 + 3, 1204 .vtotal = 480 + 13 + 3 + 29, 1205 }; 1206 1207 static const struct panel_desc bananapi_s070wv20_ct16 = { 1208 .modes = &bananapi_s070wv20_ct16_mode, 1209 .num_modes = 1, 1210 .bpc = 6, 1211 .size = { 1212 .width = 154, 1213 .height = 86, 1214 }, 1215 }; 1216 1217 static const struct drm_display_mode boe_hv070wsa_mode = { 1218 .clock = 42105, 1219 .hdisplay = 1024, 1220 .hsync_start = 1024 + 30, 1221 .hsync_end = 1024 + 30 + 30, 1222 .htotal = 1024 + 30 + 30 + 30, 1223 .vdisplay = 600, 1224 .vsync_start = 600 + 10, 1225 .vsync_end = 600 + 10 + 10, 1226 .vtotal = 600 + 10 + 10 + 10, 1227 }; 1228 1229 static const struct panel_desc boe_hv070wsa = { 1230 .modes = &boe_hv070wsa_mode, 1231 .num_modes = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 154, 1235 .height = 90, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1240 }; 1241 1242 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1243 { 1244 .clock = 71900, 1245 .hdisplay = 1280, 1246 .hsync_start = 1280 + 48, 1247 .hsync_end = 1280 + 48 + 32, 1248 .htotal = 1280 + 48 + 32 + 80, 1249 .vdisplay = 800, 1250 .vsync_start = 800 + 3, 1251 .vsync_end = 800 + 3 + 5, 1252 .vtotal = 800 + 3 + 5 + 24, 1253 }, 1254 { 1255 .clock = 57500, 1256 .hdisplay = 1280, 1257 .hsync_start = 1280 + 48, 1258 .hsync_end = 1280 + 48 + 32, 1259 .htotal = 1280 + 48 + 32 + 80, 1260 .vdisplay = 800, 1261 .vsync_start = 800 + 3, 1262 .vsync_end = 800 + 3 + 5, 1263 .vtotal = 800 + 3 + 5 + 24, 1264 }, 1265 }; 1266 1267 static const struct panel_desc boe_nv101wxmn51 = { 1268 .modes = boe_nv101wxmn51_modes, 1269 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1270 .bpc = 8, 1271 .size = { 1272 .width = 217, 1273 .height = 136, 1274 }, 1275 .delay = { 1276 .prepare = 210, 1277 .enable = 50, 1278 .unprepare = 160, 1279 }, 1280 }; 1281 1282 /* Also used for boe_nv133fhm_n62 */ 1283 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1284 .clock = 147840, 1285 .hdisplay = 1920, 1286 .hsync_start = 1920 + 48, 1287 .hsync_end = 1920 + 48 + 32, 1288 .htotal = 1920 + 48 + 32 + 200, 1289 .vdisplay = 1080, 1290 .vsync_start = 1080 + 3, 1291 .vsync_end = 1080 + 3 + 6, 1292 .vtotal = 1080 + 3 + 6 + 31, 1293 }; 1294 1295 /* Also used for boe_nv133fhm_n62 */ 1296 static const struct panel_desc boe_nv133fhm_n61 = { 1297 .modes = &boe_nv133fhm_n61_modes, 1298 .num_modes = 1, 1299 .bpc = 6, 1300 .size = { 1301 .width = 294, 1302 .height = 165, 1303 }, 1304 .delay = { 1305 .hpd_absent_delay = 200, 1306 .unprepare = 500, 1307 }, 1308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1309 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1310 .connector_type = DRM_MODE_CONNECTOR_eDP, 1311 }; 1312 1313 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1314 { 1315 .clock = 148500, 1316 .hdisplay = 1920, 1317 .hsync_start = 1920 + 48, 1318 .hsync_end = 1920 + 48 + 32, 1319 .htotal = 2200, 1320 .vdisplay = 1080, 1321 .vsync_start = 1080 + 3, 1322 .vsync_end = 1080 + 3 + 5, 1323 .vtotal = 1125, 1324 }, 1325 }; 1326 1327 static const struct panel_desc boe_nv140fhmn49 = { 1328 .modes = boe_nv140fhmn49_modes, 1329 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1330 .bpc = 6, 1331 .size = { 1332 .width = 309, 1333 .height = 174, 1334 }, 1335 .delay = { 1336 .prepare = 210, 1337 .enable = 50, 1338 .unprepare = 160, 1339 }, 1340 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1341 .connector_type = DRM_MODE_CONNECTOR_eDP, 1342 }; 1343 1344 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1345 .clock = 9000, 1346 .hdisplay = 480, 1347 .hsync_start = 480 + 5, 1348 .hsync_end = 480 + 5 + 5, 1349 .htotal = 480 + 5 + 5 + 40, 1350 .vdisplay = 272, 1351 .vsync_start = 272 + 8, 1352 .vsync_end = 272 + 8 + 8, 1353 .vtotal = 272 + 8 + 8 + 8, 1354 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1355 }; 1356 1357 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1358 .modes = &cdtech_s043wq26h_ct7_mode, 1359 .num_modes = 1, 1360 .bpc = 8, 1361 .size = { 1362 .width = 95, 1363 .height = 54, 1364 }, 1365 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1366 }; 1367 1368 /* S070PWS19HP-FC21 2017/04/22 */ 1369 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1370 .clock = 51200, 1371 .hdisplay = 1024, 1372 .hsync_start = 1024 + 160, 1373 .hsync_end = 1024 + 160 + 20, 1374 .htotal = 1024 + 160 + 20 + 140, 1375 .vdisplay = 600, 1376 .vsync_start = 600 + 12, 1377 .vsync_end = 600 + 12 + 3, 1378 .vtotal = 600 + 12 + 3 + 20, 1379 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1380 }; 1381 1382 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1383 .modes = &cdtech_s070pws19hp_fc21_mode, 1384 .num_modes = 1, 1385 .bpc = 6, 1386 .size = { 1387 .width = 154, 1388 .height = 86, 1389 }, 1390 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1391 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1392 .connector_type = DRM_MODE_CONNECTOR_DPI, 1393 }; 1394 1395 /* S070SWV29HG-DC44 2017/09/21 */ 1396 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1397 .clock = 33300, 1398 .hdisplay = 800, 1399 .hsync_start = 800 + 210, 1400 .hsync_end = 800 + 210 + 2, 1401 .htotal = 800 + 210 + 2 + 44, 1402 .vdisplay = 480, 1403 .vsync_start = 480 + 22, 1404 .vsync_end = 480 + 22 + 2, 1405 .vtotal = 480 + 22 + 2 + 21, 1406 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1407 }; 1408 1409 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1410 .modes = &cdtech_s070swv29hg_dc44_mode, 1411 .num_modes = 1, 1412 .bpc = 6, 1413 .size = { 1414 .width = 154, 1415 .height = 86, 1416 }, 1417 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1418 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1419 .connector_type = DRM_MODE_CONNECTOR_DPI, 1420 }; 1421 1422 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1423 .clock = 35000, 1424 .hdisplay = 800, 1425 .hsync_start = 800 + 40, 1426 .hsync_end = 800 + 40 + 40, 1427 .htotal = 800 + 40 + 40 + 48, 1428 .vdisplay = 480, 1429 .vsync_start = 480 + 29, 1430 .vsync_end = 480 + 29 + 13, 1431 .vtotal = 480 + 29 + 13 + 3, 1432 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1433 }; 1434 1435 static const struct panel_desc cdtech_s070wv95_ct16 = { 1436 .modes = &cdtech_s070wv95_ct16_mode, 1437 .num_modes = 1, 1438 .bpc = 8, 1439 .size = { 1440 .width = 154, 1441 .height = 85, 1442 }, 1443 }; 1444 1445 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1446 .pixelclock = { 68900000, 71100000, 73400000 }, 1447 .hactive = { 1280, 1280, 1280 }, 1448 .hfront_porch = { 65, 80, 95 }, 1449 .hback_porch = { 64, 79, 94 }, 1450 .hsync_len = { 1, 1, 1 }, 1451 .vactive = { 800, 800, 800 }, 1452 .vfront_porch = { 7, 11, 14 }, 1453 .vback_porch = { 7, 11, 14 }, 1454 .vsync_len = { 1, 1, 1 }, 1455 .flags = DISPLAY_FLAGS_DE_HIGH, 1456 }; 1457 1458 static const struct panel_desc chefree_ch101olhlwh_002 = { 1459 .timings = &chefree_ch101olhlwh_002_timing, 1460 .num_timings = 1, 1461 .bpc = 8, 1462 .size = { 1463 .width = 217, 1464 .height = 135, 1465 }, 1466 .delay = { 1467 .enable = 200, 1468 .disable = 200, 1469 }, 1470 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1471 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1472 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1473 }; 1474 1475 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1476 .clock = 66770, 1477 .hdisplay = 800, 1478 .hsync_start = 800 + 49, 1479 .hsync_end = 800 + 49 + 33, 1480 .htotal = 800 + 49 + 33 + 17, 1481 .vdisplay = 1280, 1482 .vsync_start = 1280 + 1, 1483 .vsync_end = 1280 + 1 + 7, 1484 .vtotal = 1280 + 1 + 7 + 15, 1485 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1486 }; 1487 1488 static const struct panel_desc chunghwa_claa070wp03xg = { 1489 .modes = &chunghwa_claa070wp03xg_mode, 1490 .num_modes = 1, 1491 .bpc = 6, 1492 .size = { 1493 .width = 94, 1494 .height = 150, 1495 }, 1496 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1497 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1498 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1499 }; 1500 1501 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1502 .clock = 72070, 1503 .hdisplay = 1366, 1504 .hsync_start = 1366 + 58, 1505 .hsync_end = 1366 + 58 + 58, 1506 .htotal = 1366 + 58 + 58 + 58, 1507 .vdisplay = 768, 1508 .vsync_start = 768 + 4, 1509 .vsync_end = 768 + 4 + 4, 1510 .vtotal = 768 + 4 + 4 + 4, 1511 }; 1512 1513 static const struct panel_desc chunghwa_claa101wa01a = { 1514 .modes = &chunghwa_claa101wa01a_mode, 1515 .num_modes = 1, 1516 .bpc = 6, 1517 .size = { 1518 .width = 220, 1519 .height = 120, 1520 }, 1521 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1522 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1523 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1524 }; 1525 1526 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1527 .clock = 69300, 1528 .hdisplay = 1366, 1529 .hsync_start = 1366 + 48, 1530 .hsync_end = 1366 + 48 + 32, 1531 .htotal = 1366 + 48 + 32 + 20, 1532 .vdisplay = 768, 1533 .vsync_start = 768 + 16, 1534 .vsync_end = 768 + 16 + 8, 1535 .vtotal = 768 + 16 + 8 + 16, 1536 }; 1537 1538 static const struct panel_desc chunghwa_claa101wb01 = { 1539 .modes = &chunghwa_claa101wb01_mode, 1540 .num_modes = 1, 1541 .bpc = 6, 1542 .size = { 1543 .width = 223, 1544 .height = 125, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1547 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1549 }; 1550 1551 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1552 .clock = 33260, 1553 .hdisplay = 800, 1554 .hsync_start = 800 + 40, 1555 .hsync_end = 800 + 40 + 128, 1556 .htotal = 800 + 40 + 128 + 88, 1557 .vdisplay = 480, 1558 .vsync_start = 480 + 10, 1559 .vsync_end = 480 + 10 + 2, 1560 .vtotal = 480 + 10 + 2 + 33, 1561 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1562 }; 1563 1564 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1565 .modes = &dataimage_scf0700c48ggu18_mode, 1566 .num_modes = 1, 1567 .bpc = 8, 1568 .size = { 1569 .width = 152, 1570 .height = 91, 1571 }, 1572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1573 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1574 }; 1575 1576 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1577 .pixelclock = { 45000000, 51200000, 57000000 }, 1578 .hactive = { 1024, 1024, 1024 }, 1579 .hfront_porch = { 100, 106, 113 }, 1580 .hback_porch = { 100, 106, 113 }, 1581 .hsync_len = { 100, 108, 114 }, 1582 .vactive = { 600, 600, 600 }, 1583 .vfront_porch = { 8, 11, 15 }, 1584 .vback_porch = { 8, 11, 15 }, 1585 .vsync_len = { 9, 13, 15 }, 1586 .flags = DISPLAY_FLAGS_DE_HIGH, 1587 }; 1588 1589 static const struct panel_desc dlc_dlc0700yzg_1 = { 1590 .timings = &dlc_dlc0700yzg_1_timing, 1591 .num_timings = 1, 1592 .bpc = 6, 1593 .size = { 1594 .width = 154, 1595 .height = 86, 1596 }, 1597 .delay = { 1598 .prepare = 30, 1599 .enable = 200, 1600 .disable = 200, 1601 }, 1602 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1603 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1604 }; 1605 1606 static const struct display_timing dlc_dlc1010gig_timing = { 1607 .pixelclock = { 68900000, 71100000, 73400000 }, 1608 .hactive = { 1280, 1280, 1280 }, 1609 .hfront_porch = { 43, 53, 63 }, 1610 .hback_porch = { 43, 53, 63 }, 1611 .hsync_len = { 44, 54, 64 }, 1612 .vactive = { 800, 800, 800 }, 1613 .vfront_porch = { 5, 8, 11 }, 1614 .vback_porch = { 5, 8, 11 }, 1615 .vsync_len = { 5, 7, 11 }, 1616 .flags = DISPLAY_FLAGS_DE_HIGH, 1617 }; 1618 1619 static const struct panel_desc dlc_dlc1010gig = { 1620 .timings = &dlc_dlc1010gig_timing, 1621 .num_timings = 1, 1622 .bpc = 8, 1623 .size = { 1624 .width = 216, 1625 .height = 135, 1626 }, 1627 .delay = { 1628 .prepare = 60, 1629 .enable = 150, 1630 .disable = 100, 1631 .unprepare = 60, 1632 }, 1633 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1634 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1635 }; 1636 1637 static const struct drm_display_mode edt_et035012dm6_mode = { 1638 .clock = 6500, 1639 .hdisplay = 320, 1640 .hsync_start = 320 + 20, 1641 .hsync_end = 320 + 20 + 30, 1642 .htotal = 320 + 20 + 68, 1643 .vdisplay = 240, 1644 .vsync_start = 240 + 4, 1645 .vsync_end = 240 + 4 + 4, 1646 .vtotal = 240 + 4 + 4 + 14, 1647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1648 }; 1649 1650 static const struct panel_desc edt_et035012dm6 = { 1651 .modes = &edt_et035012dm6_mode, 1652 .num_modes = 1, 1653 .bpc = 8, 1654 .size = { 1655 .width = 70, 1656 .height = 52, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1659 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1660 }; 1661 1662 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1663 .clock = 10870, 1664 .hdisplay = 480, 1665 .hsync_start = 480 + 8, 1666 .hsync_end = 480 + 8 + 4, 1667 .htotal = 480 + 8 + 4 + 41, 1668 1669 /* 1670 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1671 * fb_align 1672 */ 1673 1674 .vdisplay = 288, 1675 .vsync_start = 288 + 2, 1676 .vsync_end = 288 + 2 + 4, 1677 .vtotal = 288 + 2 + 4 + 10, 1678 }; 1679 1680 static const struct panel_desc edt_etm043080dh6gp = { 1681 .modes = &edt_etm043080dh6gp_mode, 1682 .num_modes = 1, 1683 .bpc = 8, 1684 .size = { 1685 .width = 100, 1686 .height = 65, 1687 }, 1688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1689 .connector_type = DRM_MODE_CONNECTOR_DPI, 1690 }; 1691 1692 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1693 .clock = 9000, 1694 .hdisplay = 480, 1695 .hsync_start = 480 + 2, 1696 .hsync_end = 480 + 2 + 41, 1697 .htotal = 480 + 2 + 41 + 2, 1698 .vdisplay = 272, 1699 .vsync_start = 272 + 2, 1700 .vsync_end = 272 + 2 + 10, 1701 .vtotal = 272 + 2 + 10 + 2, 1702 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1703 }; 1704 1705 static const struct panel_desc edt_etm0430g0dh6 = { 1706 .modes = &edt_etm0430g0dh6_mode, 1707 .num_modes = 1, 1708 .bpc = 6, 1709 .size = { 1710 .width = 95, 1711 .height = 54, 1712 }, 1713 }; 1714 1715 static const struct drm_display_mode edt_et057090dhu_mode = { 1716 .clock = 25175, 1717 .hdisplay = 640, 1718 .hsync_start = 640 + 16, 1719 .hsync_end = 640 + 16 + 30, 1720 .htotal = 640 + 16 + 30 + 114, 1721 .vdisplay = 480, 1722 .vsync_start = 480 + 10, 1723 .vsync_end = 480 + 10 + 3, 1724 .vtotal = 480 + 10 + 3 + 32, 1725 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1726 }; 1727 1728 static const struct panel_desc edt_et057090dhu = { 1729 .modes = &edt_et057090dhu_mode, 1730 .num_modes = 1, 1731 .bpc = 6, 1732 .size = { 1733 .width = 115, 1734 .height = 86, 1735 }, 1736 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1737 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1738 .connector_type = DRM_MODE_CONNECTOR_DPI, 1739 }; 1740 1741 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1742 .clock = 33260, 1743 .hdisplay = 800, 1744 .hsync_start = 800 + 40, 1745 .hsync_end = 800 + 40 + 128, 1746 .htotal = 800 + 40 + 128 + 88, 1747 .vdisplay = 480, 1748 .vsync_start = 480 + 10, 1749 .vsync_end = 480 + 10 + 2, 1750 .vtotal = 480 + 10 + 2 + 33, 1751 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1752 }; 1753 1754 static const struct panel_desc edt_etm0700g0dh6 = { 1755 .modes = &edt_etm0700g0dh6_mode, 1756 .num_modes = 1, 1757 .bpc = 6, 1758 .size = { 1759 .width = 152, 1760 .height = 91, 1761 }, 1762 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1763 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1764 }; 1765 1766 static const struct panel_desc edt_etm0700g0bdh6 = { 1767 .modes = &edt_etm0700g0dh6_mode, 1768 .num_modes = 1, 1769 .bpc = 6, 1770 .size = { 1771 .width = 152, 1772 .height = 91, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1776 }; 1777 1778 static const struct display_timing evervision_vgg804821_timing = { 1779 .pixelclock = { 27600000, 33300000, 50000000 }, 1780 .hactive = { 800, 800, 800 }, 1781 .hfront_porch = { 40, 66, 70 }, 1782 .hback_porch = { 40, 67, 70 }, 1783 .hsync_len = { 40, 67, 70 }, 1784 .vactive = { 480, 480, 480 }, 1785 .vfront_porch = { 6, 10, 10 }, 1786 .vback_porch = { 7, 11, 11 }, 1787 .vsync_len = { 7, 11, 11 }, 1788 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1789 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1790 DISPLAY_FLAGS_SYNC_NEGEDGE, 1791 }; 1792 1793 static const struct panel_desc evervision_vgg804821 = { 1794 .timings = &evervision_vgg804821_timing, 1795 .num_timings = 1, 1796 .bpc = 8, 1797 .size = { 1798 .width = 108, 1799 .height = 64, 1800 }, 1801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1803 }; 1804 1805 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1806 .clock = 32260, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 168, 1809 .hsync_end = 800 + 168 + 64, 1810 .htotal = 800 + 168 + 64 + 88, 1811 .vdisplay = 480, 1812 .vsync_start = 480 + 37, 1813 .vsync_end = 480 + 37 + 2, 1814 .vtotal = 480 + 37 + 2 + 8, 1815 }; 1816 1817 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1818 .modes = &foxlink_fl500wvr00_a0t_mode, 1819 .num_modes = 1, 1820 .bpc = 8, 1821 .size = { 1822 .width = 108, 1823 .height = 65, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1826 }; 1827 1828 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1829 { /* 60 Hz */ 1830 .clock = 6000, 1831 .hdisplay = 320, 1832 .hsync_start = 320 + 44, 1833 .hsync_end = 320 + 44 + 16, 1834 .htotal = 320 + 44 + 16 + 20, 1835 .vdisplay = 240, 1836 .vsync_start = 240 + 2, 1837 .vsync_end = 240 + 2 + 6, 1838 .vtotal = 240 + 2 + 6 + 2, 1839 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1840 }, 1841 { /* 50 Hz */ 1842 .clock = 5400, 1843 .hdisplay = 320, 1844 .hsync_start = 320 + 56, 1845 .hsync_end = 320 + 56 + 16, 1846 .htotal = 320 + 56 + 16 + 40, 1847 .vdisplay = 240, 1848 .vsync_start = 240 + 2, 1849 .vsync_end = 240 + 2 + 6, 1850 .vtotal = 240 + 2 + 6 + 2, 1851 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1852 }, 1853 }; 1854 1855 static const struct panel_desc frida_frd350h54004 = { 1856 .modes = frida_frd350h54004_modes, 1857 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1858 .bpc = 8, 1859 .size = { 1860 .width = 77, 1861 .height = 64, 1862 }, 1863 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1864 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1865 .connector_type = DRM_MODE_CONNECTOR_DPI, 1866 }; 1867 1868 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1869 .clock = 67185, 1870 .hdisplay = 800, 1871 .hsync_start = 800 + 20, 1872 .hsync_end = 800 + 20 + 24, 1873 .htotal = 800 + 20 + 24 + 20, 1874 .vdisplay = 1280, 1875 .vsync_start = 1280 + 4, 1876 .vsync_end = 1280 + 4 + 8, 1877 .vtotal = 1280 + 4 + 8 + 4, 1878 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1879 }; 1880 1881 static const struct panel_desc friendlyarm_hd702e = { 1882 .modes = &friendlyarm_hd702e_mode, 1883 .num_modes = 1, 1884 .size = { 1885 .width = 94, 1886 .height = 151, 1887 }, 1888 }; 1889 1890 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1891 .clock = 9000, 1892 .hdisplay = 480, 1893 .hsync_start = 480 + 5, 1894 .hsync_end = 480 + 5 + 1, 1895 .htotal = 480 + 5 + 1 + 40, 1896 .vdisplay = 272, 1897 .vsync_start = 272 + 8, 1898 .vsync_end = 272 + 8 + 1, 1899 .vtotal = 272 + 8 + 1 + 8, 1900 }; 1901 1902 static const struct panel_desc giantplus_gpg482739qs5 = { 1903 .modes = &giantplus_gpg482739qs5_mode, 1904 .num_modes = 1, 1905 .bpc = 8, 1906 .size = { 1907 .width = 95, 1908 .height = 54, 1909 }, 1910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1911 }; 1912 1913 static const struct display_timing giantplus_gpm940b0_timing = { 1914 .pixelclock = { 13500000, 27000000, 27500000 }, 1915 .hactive = { 320, 320, 320 }, 1916 .hfront_porch = { 14, 686, 718 }, 1917 .hback_porch = { 50, 70, 255 }, 1918 .hsync_len = { 1, 1, 1 }, 1919 .vactive = { 240, 240, 240 }, 1920 .vfront_porch = { 1, 1, 179 }, 1921 .vback_porch = { 1, 21, 31 }, 1922 .vsync_len = { 1, 1, 6 }, 1923 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1924 }; 1925 1926 static const struct panel_desc giantplus_gpm940b0 = { 1927 .timings = &giantplus_gpm940b0_timing, 1928 .num_timings = 1, 1929 .bpc = 8, 1930 .size = { 1931 .width = 60, 1932 .height = 45, 1933 }, 1934 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1935 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1936 }; 1937 1938 static const struct display_timing hannstar_hsd070pww1_timing = { 1939 .pixelclock = { 64300000, 71100000, 82000000 }, 1940 .hactive = { 1280, 1280, 1280 }, 1941 .hfront_porch = { 1, 1, 10 }, 1942 .hback_porch = { 1, 1, 10 }, 1943 /* 1944 * According to the data sheet, the minimum horizontal blanking interval 1945 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1946 * minimum working horizontal blanking interval to be 60 clocks. 1947 */ 1948 .hsync_len = { 58, 158, 661 }, 1949 .vactive = { 800, 800, 800 }, 1950 .vfront_porch = { 1, 1, 10 }, 1951 .vback_porch = { 1, 1, 10 }, 1952 .vsync_len = { 1, 21, 203 }, 1953 .flags = DISPLAY_FLAGS_DE_HIGH, 1954 }; 1955 1956 static const struct panel_desc hannstar_hsd070pww1 = { 1957 .timings = &hannstar_hsd070pww1_timing, 1958 .num_timings = 1, 1959 .bpc = 6, 1960 .size = { 1961 .width = 151, 1962 .height = 94, 1963 }, 1964 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1965 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1966 }; 1967 1968 static const struct display_timing hannstar_hsd100pxn1_timing = { 1969 .pixelclock = { 55000000, 65000000, 75000000 }, 1970 .hactive = { 1024, 1024, 1024 }, 1971 .hfront_porch = { 40, 40, 40 }, 1972 .hback_porch = { 220, 220, 220 }, 1973 .hsync_len = { 20, 60, 100 }, 1974 .vactive = { 768, 768, 768 }, 1975 .vfront_porch = { 7, 7, 7 }, 1976 .vback_porch = { 21, 21, 21 }, 1977 .vsync_len = { 10, 10, 10 }, 1978 .flags = DISPLAY_FLAGS_DE_HIGH, 1979 }; 1980 1981 static const struct panel_desc hannstar_hsd100pxn1 = { 1982 .timings = &hannstar_hsd100pxn1_timing, 1983 .num_timings = 1, 1984 .bpc = 6, 1985 .size = { 1986 .width = 203, 1987 .height = 152, 1988 }, 1989 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1990 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1991 }; 1992 1993 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1994 .clock = 33333, 1995 .hdisplay = 800, 1996 .hsync_start = 800 + 85, 1997 .hsync_end = 800 + 85 + 86, 1998 .htotal = 800 + 85 + 86 + 85, 1999 .vdisplay = 480, 2000 .vsync_start = 480 + 16, 2001 .vsync_end = 480 + 16 + 13, 2002 .vtotal = 480 + 16 + 13 + 16, 2003 }; 2004 2005 static const struct panel_desc hitachi_tx23d38vm0caa = { 2006 .modes = &hitachi_tx23d38vm0caa_mode, 2007 .num_modes = 1, 2008 .bpc = 6, 2009 .size = { 2010 .width = 195, 2011 .height = 117, 2012 }, 2013 .delay = { 2014 .enable = 160, 2015 .disable = 160, 2016 }, 2017 }; 2018 2019 static const struct drm_display_mode innolux_at043tn24_mode = { 2020 .clock = 9000, 2021 .hdisplay = 480, 2022 .hsync_start = 480 + 2, 2023 .hsync_end = 480 + 2 + 41, 2024 .htotal = 480 + 2 + 41 + 2, 2025 .vdisplay = 272, 2026 .vsync_start = 272 + 2, 2027 .vsync_end = 272 + 2 + 10, 2028 .vtotal = 272 + 2 + 10 + 2, 2029 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2030 }; 2031 2032 static const struct panel_desc innolux_at043tn24 = { 2033 .modes = &innolux_at043tn24_mode, 2034 .num_modes = 1, 2035 .bpc = 8, 2036 .size = { 2037 .width = 95, 2038 .height = 54, 2039 }, 2040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2041 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2042 }; 2043 2044 static const struct drm_display_mode innolux_at070tn92_mode = { 2045 .clock = 33333, 2046 .hdisplay = 800, 2047 .hsync_start = 800 + 210, 2048 .hsync_end = 800 + 210 + 20, 2049 .htotal = 800 + 210 + 20 + 46, 2050 .vdisplay = 480, 2051 .vsync_start = 480 + 22, 2052 .vsync_end = 480 + 22 + 10, 2053 .vtotal = 480 + 22 + 23 + 10, 2054 }; 2055 2056 static const struct panel_desc innolux_at070tn92 = { 2057 .modes = &innolux_at070tn92_mode, 2058 .num_modes = 1, 2059 .size = { 2060 .width = 154, 2061 .height = 86, 2062 }, 2063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2064 }; 2065 2066 static const struct display_timing innolux_g070y2_l01_timing = { 2067 .pixelclock = { 28000000, 29500000, 32000000 }, 2068 .hactive = { 800, 800, 800 }, 2069 .hfront_porch = { 61, 91, 141 }, 2070 .hback_porch = { 60, 90, 140 }, 2071 .hsync_len = { 12, 12, 12 }, 2072 .vactive = { 480, 480, 480 }, 2073 .vfront_porch = { 4, 9, 30 }, 2074 .vback_porch = { 4, 8, 28 }, 2075 .vsync_len = { 2, 2, 2 }, 2076 .flags = DISPLAY_FLAGS_DE_HIGH, 2077 }; 2078 2079 static const struct panel_desc innolux_g070y2_l01 = { 2080 .timings = &innolux_g070y2_l01_timing, 2081 .num_timings = 1, 2082 .bpc = 6, 2083 .size = { 2084 .width = 152, 2085 .height = 91, 2086 }, 2087 .delay = { 2088 .prepare = 10, 2089 .enable = 100, 2090 .disable = 100, 2091 .unprepare = 800, 2092 }, 2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2094 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2095 }; 2096 2097 static const struct display_timing innolux_g101ice_l01_timing = { 2098 .pixelclock = { 60400000, 71100000, 74700000 }, 2099 .hactive = { 1280, 1280, 1280 }, 2100 .hfront_porch = { 41, 80, 100 }, 2101 .hback_porch = { 40, 79, 99 }, 2102 .hsync_len = { 1, 1, 1 }, 2103 .vactive = { 800, 800, 800 }, 2104 .vfront_porch = { 5, 11, 14 }, 2105 .vback_porch = { 4, 11, 14 }, 2106 .vsync_len = { 1, 1, 1 }, 2107 .flags = DISPLAY_FLAGS_DE_HIGH, 2108 }; 2109 2110 static const struct panel_desc innolux_g101ice_l01 = { 2111 .timings = &innolux_g101ice_l01_timing, 2112 .num_timings = 1, 2113 .bpc = 8, 2114 .size = { 2115 .width = 217, 2116 .height = 135, 2117 }, 2118 .delay = { 2119 .enable = 200, 2120 .disable = 200, 2121 }, 2122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2124 }; 2125 2126 static const struct display_timing innolux_g121i1_l01_timing = { 2127 .pixelclock = { 67450000, 71000000, 74550000 }, 2128 .hactive = { 1280, 1280, 1280 }, 2129 .hfront_porch = { 40, 80, 160 }, 2130 .hback_porch = { 39, 79, 159 }, 2131 .hsync_len = { 1, 1, 1 }, 2132 .vactive = { 800, 800, 800 }, 2133 .vfront_porch = { 5, 11, 100 }, 2134 .vback_porch = { 4, 11, 99 }, 2135 .vsync_len = { 1, 1, 1 }, 2136 }; 2137 2138 static const struct panel_desc innolux_g121i1_l01 = { 2139 .timings = &innolux_g121i1_l01_timing, 2140 .num_timings = 1, 2141 .bpc = 6, 2142 .size = { 2143 .width = 261, 2144 .height = 163, 2145 }, 2146 .delay = { 2147 .enable = 200, 2148 .disable = 20, 2149 }, 2150 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2151 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2152 }; 2153 2154 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2155 .clock = 65000, 2156 .hdisplay = 1024, 2157 .hsync_start = 1024 + 0, 2158 .hsync_end = 1024 + 1, 2159 .htotal = 1024 + 0 + 1 + 320, 2160 .vdisplay = 768, 2161 .vsync_start = 768 + 38, 2162 .vsync_end = 768 + 38 + 1, 2163 .vtotal = 768 + 38 + 1 + 0, 2164 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2165 }; 2166 2167 static const struct panel_desc innolux_g121x1_l03 = { 2168 .modes = &innolux_g121x1_l03_mode, 2169 .num_modes = 1, 2170 .bpc = 6, 2171 .size = { 2172 .width = 246, 2173 .height = 185, 2174 }, 2175 .delay = { 2176 .enable = 200, 2177 .unprepare = 200, 2178 .disable = 400, 2179 }, 2180 }; 2181 2182 /* 2183 * Datasheet specifies that at 60 Hz refresh rate: 2184 * - total horizontal time: { 1506, 1592, 1716 } 2185 * - total vertical time: { 788, 800, 868 } 2186 * 2187 * ...but doesn't go into exactly how that should be split into a front 2188 * porch, back porch, or sync length. For now we'll leave a single setting 2189 * here which allows a bit of tweaking of the pixel clock at the expense of 2190 * refresh rate. 2191 */ 2192 static const struct display_timing innolux_n116bge_timing = { 2193 .pixelclock = { 72600000, 76420000, 80240000 }, 2194 .hactive = { 1366, 1366, 1366 }, 2195 .hfront_porch = { 136, 136, 136 }, 2196 .hback_porch = { 60, 60, 60 }, 2197 .hsync_len = { 30, 30, 30 }, 2198 .vactive = { 768, 768, 768 }, 2199 .vfront_porch = { 8, 8, 8 }, 2200 .vback_porch = { 12, 12, 12 }, 2201 .vsync_len = { 12, 12, 12 }, 2202 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2203 }; 2204 2205 static const struct panel_desc innolux_n116bge = { 2206 .timings = &innolux_n116bge_timing, 2207 .num_timings = 1, 2208 .bpc = 6, 2209 .size = { 2210 .width = 256, 2211 .height = 144, 2212 }, 2213 }; 2214 2215 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2216 .clock = 69300, 2217 .hdisplay = 1366, 2218 .hsync_start = 1366 + 16, 2219 .hsync_end = 1366 + 16 + 34, 2220 .htotal = 1366 + 16 + 34 + 50, 2221 .vdisplay = 768, 2222 .vsync_start = 768 + 2, 2223 .vsync_end = 768 + 2 + 6, 2224 .vtotal = 768 + 2 + 6 + 12, 2225 }; 2226 2227 static const struct panel_desc innolux_n156bge_l21 = { 2228 .modes = &innolux_n156bge_l21_mode, 2229 .num_modes = 1, 2230 .bpc = 6, 2231 .size = { 2232 .width = 344, 2233 .height = 193, 2234 }, 2235 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2236 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2237 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2238 }; 2239 2240 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2241 .clock = 206016, 2242 .hdisplay = 2160, 2243 .hsync_start = 2160 + 48, 2244 .hsync_end = 2160 + 48 + 32, 2245 .htotal = 2160 + 48 + 32 + 80, 2246 .vdisplay = 1440, 2247 .vsync_start = 1440 + 3, 2248 .vsync_end = 1440 + 3 + 10, 2249 .vtotal = 1440 + 3 + 10 + 27, 2250 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2251 }; 2252 2253 static const struct panel_desc innolux_p120zdg_bf1 = { 2254 .modes = &innolux_p120zdg_bf1_mode, 2255 .num_modes = 1, 2256 .bpc = 8, 2257 .size = { 2258 .width = 254, 2259 .height = 169, 2260 }, 2261 .delay = { 2262 .hpd_absent_delay = 200, 2263 .unprepare = 500, 2264 }, 2265 }; 2266 2267 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2268 .clock = 51501, 2269 .hdisplay = 1024, 2270 .hsync_start = 1024 + 128, 2271 .hsync_end = 1024 + 128 + 64, 2272 .htotal = 1024 + 128 + 64 + 128, 2273 .vdisplay = 600, 2274 .vsync_start = 600 + 16, 2275 .vsync_end = 600 + 16 + 4, 2276 .vtotal = 600 + 16 + 4 + 16, 2277 }; 2278 2279 static const struct panel_desc innolux_zj070na_01p = { 2280 .modes = &innolux_zj070na_01p_mode, 2281 .num_modes = 1, 2282 .bpc = 6, 2283 .size = { 2284 .width = 154, 2285 .height = 90, 2286 }, 2287 }; 2288 2289 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2290 .clock = 138778, 2291 .hdisplay = 1920, 2292 .hsync_start = 1920 + 24, 2293 .hsync_end = 1920 + 24 + 48, 2294 .htotal = 1920 + 24 + 48 + 88, 2295 .vdisplay = 1080, 2296 .vsync_start = 1080 + 3, 2297 .vsync_end = 1080 + 3 + 12, 2298 .vtotal = 1080 + 3 + 12 + 17, 2299 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2300 }; 2301 2302 static const struct panel_desc ivo_m133nwf4_r0 = { 2303 .modes = &ivo_m133nwf4_r0_mode, 2304 .num_modes = 1, 2305 .bpc = 8, 2306 .size = { 2307 .width = 294, 2308 .height = 165, 2309 }, 2310 .delay = { 2311 .hpd_absent_delay = 200, 2312 .unprepare = 500, 2313 }, 2314 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2315 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2316 .connector_type = DRM_MODE_CONNECTOR_eDP, 2317 }; 2318 2319 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2320 .pixelclock = { 5580000, 5850000, 6200000 }, 2321 .hactive = { 320, 320, 320 }, 2322 .hfront_porch = { 30, 30, 30 }, 2323 .hback_porch = { 30, 30, 30 }, 2324 .hsync_len = { 1, 5, 17 }, 2325 .vactive = { 240, 240, 240 }, 2326 .vfront_porch = { 6, 6, 6 }, 2327 .vback_porch = { 5, 5, 5 }, 2328 .vsync_len = { 1, 2, 11 }, 2329 .flags = DISPLAY_FLAGS_DE_HIGH, 2330 }; 2331 2332 static const struct panel_desc koe_tx14d24vm1bpa = { 2333 .timings = &koe_tx14d24vm1bpa_timing, 2334 .num_timings = 1, 2335 .bpc = 6, 2336 .size = { 2337 .width = 115, 2338 .height = 86, 2339 }, 2340 }; 2341 2342 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2343 .pixelclock = { 151820000, 156720000, 159780000 }, 2344 .hactive = { 1920, 1920, 1920 }, 2345 .hfront_porch = { 105, 130, 142 }, 2346 .hback_porch = { 45, 70, 82 }, 2347 .hsync_len = { 30, 30, 30 }, 2348 .vactive = { 1200, 1200, 1200}, 2349 .vfront_porch = { 3, 5, 10 }, 2350 .vback_porch = { 2, 5, 10 }, 2351 .vsync_len = { 5, 5, 5 }, 2352 }; 2353 2354 static const struct panel_desc koe_tx26d202vm0bwa = { 2355 .timings = &koe_tx26d202vm0bwa_timing, 2356 .num_timings = 1, 2357 .bpc = 8, 2358 .size = { 2359 .width = 217, 2360 .height = 136, 2361 }, 2362 .delay = { 2363 .prepare = 1000, 2364 .enable = 1000, 2365 .unprepare = 1000, 2366 .disable = 1000, 2367 }, 2368 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2369 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2371 }; 2372 2373 static const struct display_timing koe_tx31d200vm0baa_timing = { 2374 .pixelclock = { 39600000, 43200000, 48000000 }, 2375 .hactive = { 1280, 1280, 1280 }, 2376 .hfront_porch = { 16, 36, 56 }, 2377 .hback_porch = { 16, 36, 56 }, 2378 .hsync_len = { 8, 8, 8 }, 2379 .vactive = { 480, 480, 480 }, 2380 .vfront_porch = { 6, 21, 33 }, 2381 .vback_porch = { 6, 21, 33 }, 2382 .vsync_len = { 8, 8, 8 }, 2383 .flags = DISPLAY_FLAGS_DE_HIGH, 2384 }; 2385 2386 static const struct panel_desc koe_tx31d200vm0baa = { 2387 .timings = &koe_tx31d200vm0baa_timing, 2388 .num_timings = 1, 2389 .bpc = 6, 2390 .size = { 2391 .width = 292, 2392 .height = 109, 2393 }, 2394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2396 }; 2397 2398 static const struct display_timing kyo_tcg121xglp_timing = { 2399 .pixelclock = { 52000000, 65000000, 71000000 }, 2400 .hactive = { 1024, 1024, 1024 }, 2401 .hfront_porch = { 2, 2, 2 }, 2402 .hback_porch = { 2, 2, 2 }, 2403 .hsync_len = { 86, 124, 244 }, 2404 .vactive = { 768, 768, 768 }, 2405 .vfront_porch = { 2, 2, 2 }, 2406 .vback_porch = { 2, 2, 2 }, 2407 .vsync_len = { 6, 34, 73 }, 2408 .flags = DISPLAY_FLAGS_DE_HIGH, 2409 }; 2410 2411 static const struct panel_desc kyo_tcg121xglp = { 2412 .timings = &kyo_tcg121xglp_timing, 2413 .num_timings = 1, 2414 .bpc = 8, 2415 .size = { 2416 .width = 246, 2417 .height = 184, 2418 }, 2419 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2420 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2421 }; 2422 2423 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2424 .clock = 7000, 2425 .hdisplay = 320, 2426 .hsync_start = 320 + 20, 2427 .hsync_end = 320 + 20 + 30, 2428 .htotal = 320 + 20 + 30 + 38, 2429 .vdisplay = 240, 2430 .vsync_start = 240 + 4, 2431 .vsync_end = 240 + 4 + 3, 2432 .vtotal = 240 + 4 + 3 + 15, 2433 }; 2434 2435 static const struct panel_desc lemaker_bl035_rgb_002 = { 2436 .modes = &lemaker_bl035_rgb_002_mode, 2437 .num_modes = 1, 2438 .size = { 2439 .width = 70, 2440 .height = 52, 2441 }, 2442 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2443 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2444 }; 2445 2446 static const struct drm_display_mode lg_lb070wv8_mode = { 2447 .clock = 33246, 2448 .hdisplay = 800, 2449 .hsync_start = 800 + 88, 2450 .hsync_end = 800 + 88 + 80, 2451 .htotal = 800 + 88 + 80 + 88, 2452 .vdisplay = 480, 2453 .vsync_start = 480 + 10, 2454 .vsync_end = 480 + 10 + 25, 2455 .vtotal = 480 + 10 + 25 + 10, 2456 }; 2457 2458 static const struct panel_desc lg_lb070wv8 = { 2459 .modes = &lg_lb070wv8_mode, 2460 .num_modes = 1, 2461 .bpc = 8, 2462 .size = { 2463 .width = 151, 2464 .height = 91, 2465 }, 2466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2467 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2468 }; 2469 2470 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2471 .clock = 200000, 2472 .hdisplay = 1536, 2473 .hsync_start = 1536 + 12, 2474 .hsync_end = 1536 + 12 + 16, 2475 .htotal = 1536 + 12 + 16 + 48, 2476 .vdisplay = 2048, 2477 .vsync_start = 2048 + 8, 2478 .vsync_end = 2048 + 8 + 4, 2479 .vtotal = 2048 + 8 + 4 + 8, 2480 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2481 }; 2482 2483 static const struct panel_desc lg_lp079qx1_sp0v = { 2484 .modes = &lg_lp079qx1_sp0v_mode, 2485 .num_modes = 1, 2486 .size = { 2487 .width = 129, 2488 .height = 171, 2489 }, 2490 }; 2491 2492 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2493 .clock = 205210, 2494 .hdisplay = 2048, 2495 .hsync_start = 2048 + 150, 2496 .hsync_end = 2048 + 150 + 5, 2497 .htotal = 2048 + 150 + 5 + 5, 2498 .vdisplay = 1536, 2499 .vsync_start = 1536 + 3, 2500 .vsync_end = 1536 + 3 + 1, 2501 .vtotal = 1536 + 3 + 1 + 9, 2502 }; 2503 2504 static const struct panel_desc lg_lp097qx1_spa1 = { 2505 .modes = &lg_lp097qx1_spa1_mode, 2506 .num_modes = 1, 2507 .size = { 2508 .width = 208, 2509 .height = 147, 2510 }, 2511 }; 2512 2513 static const struct drm_display_mode lg_lp120up1_mode = { 2514 .clock = 162300, 2515 .hdisplay = 1920, 2516 .hsync_start = 1920 + 40, 2517 .hsync_end = 1920 + 40 + 40, 2518 .htotal = 1920 + 40 + 40+ 80, 2519 .vdisplay = 1280, 2520 .vsync_start = 1280 + 4, 2521 .vsync_end = 1280 + 4 + 4, 2522 .vtotal = 1280 + 4 + 4 + 12, 2523 }; 2524 2525 static const struct panel_desc lg_lp120up1 = { 2526 .modes = &lg_lp120up1_mode, 2527 .num_modes = 1, 2528 .bpc = 8, 2529 .size = { 2530 .width = 267, 2531 .height = 183, 2532 }, 2533 .connector_type = DRM_MODE_CONNECTOR_eDP, 2534 }; 2535 2536 static const struct drm_display_mode lg_lp129qe_mode = { 2537 .clock = 285250, 2538 .hdisplay = 2560, 2539 .hsync_start = 2560 + 48, 2540 .hsync_end = 2560 + 48 + 32, 2541 .htotal = 2560 + 48 + 32 + 80, 2542 .vdisplay = 1700, 2543 .vsync_start = 1700 + 3, 2544 .vsync_end = 1700 + 3 + 10, 2545 .vtotal = 1700 + 3 + 10 + 36, 2546 }; 2547 2548 static const struct panel_desc lg_lp129qe = { 2549 .modes = &lg_lp129qe_mode, 2550 .num_modes = 1, 2551 .bpc = 8, 2552 .size = { 2553 .width = 272, 2554 .height = 181, 2555 }, 2556 }; 2557 2558 static const struct display_timing logictechno_lt161010_2nh_timing = { 2559 .pixelclock = { 26400000, 33300000, 46800000 }, 2560 .hactive = { 800, 800, 800 }, 2561 .hfront_porch = { 16, 210, 354 }, 2562 .hback_porch = { 46, 46, 46 }, 2563 .hsync_len = { 1, 20, 40 }, 2564 .vactive = { 480, 480, 480 }, 2565 .vfront_porch = { 7, 22, 147 }, 2566 .vback_porch = { 23, 23, 23 }, 2567 .vsync_len = { 1, 10, 20 }, 2568 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2569 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2570 DISPLAY_FLAGS_SYNC_POSEDGE, 2571 }; 2572 2573 static const struct panel_desc logictechno_lt161010_2nh = { 2574 .timings = &logictechno_lt161010_2nh_timing, 2575 .num_timings = 1, 2576 .size = { 2577 .width = 154, 2578 .height = 86, 2579 }, 2580 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2581 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2582 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2583 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2584 .connector_type = DRM_MODE_CONNECTOR_DPI, 2585 }; 2586 2587 static const struct display_timing logictechno_lt170410_2whc_timing = { 2588 .pixelclock = { 68900000, 71100000, 73400000 }, 2589 .hactive = { 1280, 1280, 1280 }, 2590 .hfront_porch = { 23, 60, 71 }, 2591 .hback_porch = { 23, 60, 71 }, 2592 .hsync_len = { 15, 40, 47 }, 2593 .vactive = { 800, 800, 800 }, 2594 .vfront_porch = { 5, 7, 10 }, 2595 .vback_porch = { 5, 7, 10 }, 2596 .vsync_len = { 6, 9, 12 }, 2597 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2598 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2599 DISPLAY_FLAGS_SYNC_POSEDGE, 2600 }; 2601 2602 static const struct panel_desc logictechno_lt170410_2whc = { 2603 .timings = &logictechno_lt170410_2whc_timing, 2604 .num_timings = 1, 2605 .size = { 2606 .width = 217, 2607 .height = 136, 2608 }, 2609 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2610 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2611 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2612 }; 2613 2614 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2615 .clock = 30400, 2616 .hdisplay = 800, 2617 .hsync_start = 800 + 0, 2618 .hsync_end = 800 + 1, 2619 .htotal = 800 + 0 + 1 + 160, 2620 .vdisplay = 480, 2621 .vsync_start = 480 + 0, 2622 .vsync_end = 480 + 48 + 1, 2623 .vtotal = 480 + 48 + 1 + 0, 2624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2625 }; 2626 2627 static const struct drm_display_mode logicpd_type_28_mode = { 2628 .clock = 9107, 2629 .hdisplay = 480, 2630 .hsync_start = 480 + 3, 2631 .hsync_end = 480 + 3 + 42, 2632 .htotal = 480 + 3 + 42 + 2, 2633 2634 .vdisplay = 272, 2635 .vsync_start = 272 + 2, 2636 .vsync_end = 272 + 2 + 11, 2637 .vtotal = 272 + 2 + 11 + 3, 2638 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2639 }; 2640 2641 static const struct panel_desc logicpd_type_28 = { 2642 .modes = &logicpd_type_28_mode, 2643 .num_modes = 1, 2644 .bpc = 8, 2645 .size = { 2646 .width = 105, 2647 .height = 67, 2648 }, 2649 .delay = { 2650 .prepare = 200, 2651 .enable = 200, 2652 .unprepare = 200, 2653 .disable = 200, 2654 }, 2655 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2656 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2657 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2658 }; 2659 2660 static const struct panel_desc mitsubishi_aa070mc01 = { 2661 .modes = &mitsubishi_aa070mc01_mode, 2662 .num_modes = 1, 2663 .bpc = 8, 2664 .size = { 2665 .width = 152, 2666 .height = 91, 2667 }, 2668 2669 .delay = { 2670 .enable = 200, 2671 .unprepare = 200, 2672 .disable = 400, 2673 }, 2674 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2675 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2676 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2677 }; 2678 2679 static const struct display_timing nec_nl12880bc20_05_timing = { 2680 .pixelclock = { 67000000, 71000000, 75000000 }, 2681 .hactive = { 1280, 1280, 1280 }, 2682 .hfront_porch = { 2, 30, 30 }, 2683 .hback_porch = { 6, 100, 100 }, 2684 .hsync_len = { 2, 30, 30 }, 2685 .vactive = { 800, 800, 800 }, 2686 .vfront_porch = { 5, 5, 5 }, 2687 .vback_porch = { 11, 11, 11 }, 2688 .vsync_len = { 7, 7, 7 }, 2689 }; 2690 2691 static const struct panel_desc nec_nl12880bc20_05 = { 2692 .timings = &nec_nl12880bc20_05_timing, 2693 .num_timings = 1, 2694 .bpc = 8, 2695 .size = { 2696 .width = 261, 2697 .height = 163, 2698 }, 2699 .delay = { 2700 .enable = 50, 2701 .disable = 50, 2702 }, 2703 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2704 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2705 }; 2706 2707 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2708 .clock = 10870, 2709 .hdisplay = 480, 2710 .hsync_start = 480 + 2, 2711 .hsync_end = 480 + 2 + 41, 2712 .htotal = 480 + 2 + 41 + 2, 2713 .vdisplay = 272, 2714 .vsync_start = 272 + 2, 2715 .vsync_end = 272 + 2 + 4, 2716 .vtotal = 272 + 2 + 4 + 2, 2717 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2718 }; 2719 2720 static const struct panel_desc nec_nl4827hc19_05b = { 2721 .modes = &nec_nl4827hc19_05b_mode, 2722 .num_modes = 1, 2723 .bpc = 8, 2724 .size = { 2725 .width = 95, 2726 .height = 54, 2727 }, 2728 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2729 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2730 }; 2731 2732 static const struct drm_display_mode netron_dy_e231732_mode = { 2733 .clock = 66000, 2734 .hdisplay = 1024, 2735 .hsync_start = 1024 + 160, 2736 .hsync_end = 1024 + 160 + 70, 2737 .htotal = 1024 + 160 + 70 + 90, 2738 .vdisplay = 600, 2739 .vsync_start = 600 + 127, 2740 .vsync_end = 600 + 127 + 20, 2741 .vtotal = 600 + 127 + 20 + 3, 2742 }; 2743 2744 static const struct panel_desc netron_dy_e231732 = { 2745 .modes = &netron_dy_e231732_mode, 2746 .num_modes = 1, 2747 .size = { 2748 .width = 154, 2749 .height = 87, 2750 }, 2751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2752 }; 2753 2754 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2755 { 2756 .clock = 138500, 2757 .hdisplay = 1920, 2758 .hsync_start = 1920 + 48, 2759 .hsync_end = 1920 + 48 + 32, 2760 .htotal = 1920 + 48 + 32 + 80, 2761 .vdisplay = 1080, 2762 .vsync_start = 1080 + 3, 2763 .vsync_end = 1080 + 3 + 5, 2764 .vtotal = 1080 + 3 + 5 + 23, 2765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2766 }, { 2767 .clock = 110920, 2768 .hdisplay = 1920, 2769 .hsync_start = 1920 + 48, 2770 .hsync_end = 1920 + 48 + 32, 2771 .htotal = 1920 + 48 + 32 + 80, 2772 .vdisplay = 1080, 2773 .vsync_start = 1080 + 3, 2774 .vsync_end = 1080 + 3 + 5, 2775 .vtotal = 1080 + 3 + 5 + 23, 2776 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2777 } 2778 }; 2779 2780 static const struct panel_desc neweast_wjfh116008a = { 2781 .modes = neweast_wjfh116008a_modes, 2782 .num_modes = 2, 2783 .bpc = 6, 2784 .size = { 2785 .width = 260, 2786 .height = 150, 2787 }, 2788 .delay = { 2789 .prepare = 110, 2790 .enable = 20, 2791 .unprepare = 500, 2792 }, 2793 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2794 .connector_type = DRM_MODE_CONNECTOR_eDP, 2795 }; 2796 2797 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2798 .clock = 9000, 2799 .hdisplay = 480, 2800 .hsync_start = 480 + 2, 2801 .hsync_end = 480 + 2 + 41, 2802 .htotal = 480 + 2 + 41 + 2, 2803 .vdisplay = 272, 2804 .vsync_start = 272 + 2, 2805 .vsync_end = 272 + 2 + 10, 2806 .vtotal = 272 + 2 + 10 + 2, 2807 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2808 }; 2809 2810 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2811 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2812 .num_modes = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 95, 2816 .height = 54, 2817 }, 2818 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2819 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2820 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2821 }; 2822 2823 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2824 .pixelclock = { 130000000, 148350000, 163000000 }, 2825 .hactive = { 1920, 1920, 1920 }, 2826 .hfront_porch = { 80, 100, 100 }, 2827 .hback_porch = { 100, 120, 120 }, 2828 .hsync_len = { 50, 60, 60 }, 2829 .vactive = { 1080, 1080, 1080 }, 2830 .vfront_porch = { 12, 30, 30 }, 2831 .vback_porch = { 4, 10, 10 }, 2832 .vsync_len = { 4, 5, 5 }, 2833 }; 2834 2835 static const struct panel_desc nlt_nl192108ac18_02d = { 2836 .timings = &nlt_nl192108ac18_02d_timing, 2837 .num_timings = 1, 2838 .bpc = 8, 2839 .size = { 2840 .width = 344, 2841 .height = 194, 2842 }, 2843 .delay = { 2844 .unprepare = 500, 2845 }, 2846 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2847 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2848 }; 2849 2850 static const struct drm_display_mode nvd_9128_mode = { 2851 .clock = 29500, 2852 .hdisplay = 800, 2853 .hsync_start = 800 + 130, 2854 .hsync_end = 800 + 130 + 98, 2855 .htotal = 800 + 0 + 130 + 98, 2856 .vdisplay = 480, 2857 .vsync_start = 480 + 10, 2858 .vsync_end = 480 + 10 + 50, 2859 .vtotal = 480 + 0 + 10 + 50, 2860 }; 2861 2862 static const struct panel_desc nvd_9128 = { 2863 .modes = &nvd_9128_mode, 2864 .num_modes = 1, 2865 .bpc = 8, 2866 .size = { 2867 .width = 156, 2868 .height = 88, 2869 }, 2870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2872 }; 2873 2874 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2875 .pixelclock = { 30000000, 30000000, 40000000 }, 2876 .hactive = { 800, 800, 800 }, 2877 .hfront_porch = { 40, 40, 40 }, 2878 .hback_porch = { 40, 40, 40 }, 2879 .hsync_len = { 1, 48, 48 }, 2880 .vactive = { 480, 480, 480 }, 2881 .vfront_porch = { 13, 13, 13 }, 2882 .vback_porch = { 29, 29, 29 }, 2883 .vsync_len = { 3, 3, 3 }, 2884 .flags = DISPLAY_FLAGS_DE_HIGH, 2885 }; 2886 2887 static const struct panel_desc okaya_rs800480t_7x0gp = { 2888 .timings = &okaya_rs800480t_7x0gp_timing, 2889 .num_timings = 1, 2890 .bpc = 6, 2891 .size = { 2892 .width = 154, 2893 .height = 87, 2894 }, 2895 .delay = { 2896 .prepare = 41, 2897 .enable = 50, 2898 .unprepare = 41, 2899 .disable = 50, 2900 }, 2901 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2902 }; 2903 2904 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2905 .clock = 9000, 2906 .hdisplay = 480, 2907 .hsync_start = 480 + 5, 2908 .hsync_end = 480 + 5 + 30, 2909 .htotal = 480 + 5 + 30 + 10, 2910 .vdisplay = 272, 2911 .vsync_start = 272 + 8, 2912 .vsync_end = 272 + 8 + 5, 2913 .vtotal = 272 + 8 + 5 + 3, 2914 }; 2915 2916 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2917 .modes = &olimex_lcd_olinuxino_43ts_mode, 2918 .num_modes = 1, 2919 .size = { 2920 .width = 95, 2921 .height = 54, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2924 }; 2925 2926 /* 2927 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2928 * pixel clocks, but this is the timing that was being used in the Adafruit 2929 * installation instructions. 2930 */ 2931 static const struct drm_display_mode ontat_yx700wv03_mode = { 2932 .clock = 29500, 2933 .hdisplay = 800, 2934 .hsync_start = 824, 2935 .hsync_end = 896, 2936 .htotal = 992, 2937 .vdisplay = 480, 2938 .vsync_start = 483, 2939 .vsync_end = 493, 2940 .vtotal = 500, 2941 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2942 }; 2943 2944 /* 2945 * Specification at: 2946 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2947 */ 2948 static const struct panel_desc ontat_yx700wv03 = { 2949 .modes = &ontat_yx700wv03_mode, 2950 .num_modes = 1, 2951 .bpc = 8, 2952 .size = { 2953 .width = 154, 2954 .height = 83, 2955 }, 2956 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2957 }; 2958 2959 static const struct drm_display_mode ortustech_com37h3m_mode = { 2960 .clock = 22230, 2961 .hdisplay = 480, 2962 .hsync_start = 480 + 40, 2963 .hsync_end = 480 + 40 + 10, 2964 .htotal = 480 + 40 + 10 + 40, 2965 .vdisplay = 640, 2966 .vsync_start = 640 + 4, 2967 .vsync_end = 640 + 4 + 2, 2968 .vtotal = 640 + 4 + 2 + 4, 2969 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2970 }; 2971 2972 static const struct panel_desc ortustech_com37h3m = { 2973 .modes = &ortustech_com37h3m_mode, 2974 .num_modes = 1, 2975 .bpc = 8, 2976 .size = { 2977 .width = 56, /* 56.16mm */ 2978 .height = 75, /* 74.88mm */ 2979 }, 2980 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2981 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2982 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2983 }; 2984 2985 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2986 .clock = 25000, 2987 .hdisplay = 480, 2988 .hsync_start = 480 + 10, 2989 .hsync_end = 480 + 10 + 10, 2990 .htotal = 480 + 10 + 10 + 15, 2991 .vdisplay = 800, 2992 .vsync_start = 800 + 3, 2993 .vsync_end = 800 + 3 + 3, 2994 .vtotal = 800 + 3 + 3 + 3, 2995 }; 2996 2997 static const struct panel_desc ortustech_com43h4m85ulc = { 2998 .modes = &ortustech_com43h4m85ulc_mode, 2999 .num_modes = 1, 3000 .bpc = 8, 3001 .size = { 3002 .width = 56, 3003 .height = 93, 3004 }, 3005 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3006 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3007 .connector_type = DRM_MODE_CONNECTOR_DPI, 3008 }; 3009 3010 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3011 .clock = 33000, 3012 .hdisplay = 800, 3013 .hsync_start = 800 + 210, 3014 .hsync_end = 800 + 210 + 30, 3015 .htotal = 800 + 210 + 30 + 16, 3016 .vdisplay = 480, 3017 .vsync_start = 480 + 22, 3018 .vsync_end = 480 + 22 + 13, 3019 .vtotal = 480 + 22 + 13 + 10, 3020 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3021 }; 3022 3023 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3024 .modes = &osddisplays_osd070t1718_19ts_mode, 3025 .num_modes = 1, 3026 .bpc = 8, 3027 .size = { 3028 .width = 152, 3029 .height = 91, 3030 }, 3031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3033 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3034 .connector_type = DRM_MODE_CONNECTOR_DPI, 3035 }; 3036 3037 static const struct drm_display_mode pda_91_00156_a0_mode = { 3038 .clock = 33300, 3039 .hdisplay = 800, 3040 .hsync_start = 800 + 1, 3041 .hsync_end = 800 + 1 + 64, 3042 .htotal = 800 + 1 + 64 + 64, 3043 .vdisplay = 480, 3044 .vsync_start = 480 + 1, 3045 .vsync_end = 480 + 1 + 23, 3046 .vtotal = 480 + 1 + 23 + 22, 3047 }; 3048 3049 static const struct panel_desc pda_91_00156_a0 = { 3050 .modes = &pda_91_00156_a0_mode, 3051 .num_modes = 1, 3052 .size = { 3053 .width = 152, 3054 .height = 91, 3055 }, 3056 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3057 }; 3058 3059 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3060 .clock = 24750, 3061 .hdisplay = 800, 3062 .hsync_start = 800 + 54, 3063 .hsync_end = 800 + 54 + 2, 3064 .htotal = 800 + 54 + 2 + 44, 3065 .vdisplay = 480, 3066 .vsync_start = 480 + 49, 3067 .vsync_end = 480 + 49 + 2, 3068 .vtotal = 480 + 49 + 2 + 22, 3069 }; 3070 3071 static const struct panel_desc powertip_ph800480t013_idf02 = { 3072 .modes = &powertip_ph800480t013_idf02_mode, 3073 .num_modes = 1, 3074 .size = { 3075 .width = 152, 3076 .height = 91, 3077 }, 3078 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3079 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3080 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3081 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3082 .connector_type = DRM_MODE_CONNECTOR_DPI, 3083 }; 3084 3085 static const struct drm_display_mode qd43003c0_40_mode = { 3086 .clock = 9000, 3087 .hdisplay = 480, 3088 .hsync_start = 480 + 8, 3089 .hsync_end = 480 + 8 + 4, 3090 .htotal = 480 + 8 + 4 + 39, 3091 .vdisplay = 272, 3092 .vsync_start = 272 + 4, 3093 .vsync_end = 272 + 4 + 10, 3094 .vtotal = 272 + 4 + 10 + 2, 3095 }; 3096 3097 static const struct panel_desc qd43003c0_40 = { 3098 .modes = &qd43003c0_40_mode, 3099 .num_modes = 1, 3100 .bpc = 8, 3101 .size = { 3102 .width = 95, 3103 .height = 53, 3104 }, 3105 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3106 }; 3107 3108 static const struct display_timing rocktech_rk070er9427_timing = { 3109 .pixelclock = { 26400000, 33300000, 46800000 }, 3110 .hactive = { 800, 800, 800 }, 3111 .hfront_porch = { 16, 210, 354 }, 3112 .hback_porch = { 46, 46, 46 }, 3113 .hsync_len = { 1, 1, 1 }, 3114 .vactive = { 480, 480, 480 }, 3115 .vfront_porch = { 7, 22, 147 }, 3116 .vback_porch = { 23, 23, 23 }, 3117 .vsync_len = { 1, 1, 1 }, 3118 .flags = DISPLAY_FLAGS_DE_HIGH, 3119 }; 3120 3121 static const struct panel_desc rocktech_rk070er9427 = { 3122 .timings = &rocktech_rk070er9427_timing, 3123 .num_timings = 1, 3124 .bpc = 6, 3125 .size = { 3126 .width = 154, 3127 .height = 86, 3128 }, 3129 .delay = { 3130 .prepare = 41, 3131 .enable = 50, 3132 .unprepare = 41, 3133 .disable = 50, 3134 }, 3135 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3136 }; 3137 3138 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3139 .clock = 71100, 3140 .hdisplay = 1280, 3141 .hsync_start = 1280 + 48, 3142 .hsync_end = 1280 + 48 + 32, 3143 .htotal = 1280 + 48 + 32 + 80, 3144 .vdisplay = 800, 3145 .vsync_start = 800 + 2, 3146 .vsync_end = 800 + 2 + 5, 3147 .vtotal = 800 + 2 + 5 + 16, 3148 }; 3149 3150 static const struct panel_desc rocktech_rk101ii01d_ct = { 3151 .modes = &rocktech_rk101ii01d_ct_mode, 3152 .num_modes = 1, 3153 .size = { 3154 .width = 217, 3155 .height = 136, 3156 }, 3157 .delay = { 3158 .prepare = 50, 3159 .disable = 50, 3160 }, 3161 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3164 }; 3165 3166 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3167 .clock = 271560, 3168 .hdisplay = 2560, 3169 .hsync_start = 2560 + 48, 3170 .hsync_end = 2560 + 48 + 32, 3171 .htotal = 2560 + 48 + 32 + 80, 3172 .vdisplay = 1600, 3173 .vsync_start = 1600 + 2, 3174 .vsync_end = 1600 + 2 + 5, 3175 .vtotal = 1600 + 2 + 5 + 57, 3176 }; 3177 3178 static const struct panel_desc samsung_lsn122dl01_c01 = { 3179 .modes = &samsung_lsn122dl01_c01_mode, 3180 .num_modes = 1, 3181 .size = { 3182 .width = 263, 3183 .height = 164, 3184 }, 3185 }; 3186 3187 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3188 .clock = 54030, 3189 .hdisplay = 1024, 3190 .hsync_start = 1024 + 24, 3191 .hsync_end = 1024 + 24 + 136, 3192 .htotal = 1024 + 24 + 136 + 160, 3193 .vdisplay = 600, 3194 .vsync_start = 600 + 3, 3195 .vsync_end = 600 + 3 + 6, 3196 .vtotal = 600 + 3 + 6 + 61, 3197 }; 3198 3199 static const struct panel_desc samsung_ltn101nt05 = { 3200 .modes = &samsung_ltn101nt05_mode, 3201 .num_modes = 1, 3202 .bpc = 6, 3203 .size = { 3204 .width = 223, 3205 .height = 125, 3206 }, 3207 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3208 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3209 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3210 }; 3211 3212 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3213 .clock = 76300, 3214 .hdisplay = 1366, 3215 .hsync_start = 1366 + 64, 3216 .hsync_end = 1366 + 64 + 48, 3217 .htotal = 1366 + 64 + 48 + 128, 3218 .vdisplay = 768, 3219 .vsync_start = 768 + 2, 3220 .vsync_end = 768 + 2 + 5, 3221 .vtotal = 768 + 2 + 5 + 17, 3222 }; 3223 3224 static const struct panel_desc samsung_ltn140at29_301 = { 3225 .modes = &samsung_ltn140at29_301_mode, 3226 .num_modes = 1, 3227 .bpc = 6, 3228 .size = { 3229 .width = 320, 3230 .height = 187, 3231 }, 3232 }; 3233 3234 static const struct display_timing satoz_sat050at40h12r2_timing = { 3235 .pixelclock = {33300000, 33300000, 50000000}, 3236 .hactive = {800, 800, 800}, 3237 .hfront_porch = {16, 210, 354}, 3238 .hback_porch = {46, 46, 46}, 3239 .hsync_len = {1, 1, 40}, 3240 .vactive = {480, 480, 480}, 3241 .vfront_porch = {7, 22, 147}, 3242 .vback_porch = {23, 23, 23}, 3243 .vsync_len = {1, 1, 20}, 3244 }; 3245 3246 static const struct panel_desc satoz_sat050at40h12r2 = { 3247 .timings = &satoz_sat050at40h12r2_timing, 3248 .num_timings = 1, 3249 .bpc = 8, 3250 .size = { 3251 .width = 108, 3252 .height = 65, 3253 }, 3254 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3255 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3256 }; 3257 3258 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3259 .clock = 168480, 3260 .hdisplay = 1920, 3261 .hsync_start = 1920 + 48, 3262 .hsync_end = 1920 + 48 + 32, 3263 .htotal = 1920 + 48 + 32 + 80, 3264 .vdisplay = 1280, 3265 .vsync_start = 1280 + 3, 3266 .vsync_end = 1280 + 3 + 10, 3267 .vtotal = 1280 + 3 + 10 + 57, 3268 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3269 }; 3270 3271 static const struct panel_desc sharp_ld_d5116z01b = { 3272 .modes = &sharp_ld_d5116z01b_mode, 3273 .num_modes = 1, 3274 .bpc = 8, 3275 .size = { 3276 .width = 260, 3277 .height = 120, 3278 }, 3279 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3280 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3281 }; 3282 3283 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3284 .clock = 33260, 3285 .hdisplay = 800, 3286 .hsync_start = 800 + 64, 3287 .hsync_end = 800 + 64 + 128, 3288 .htotal = 800 + 64 + 128 + 64, 3289 .vdisplay = 480, 3290 .vsync_start = 480 + 8, 3291 .vsync_end = 480 + 8 + 2, 3292 .vtotal = 480 + 8 + 2 + 35, 3293 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3294 }; 3295 3296 static const struct panel_desc sharp_lq070y3dg3b = { 3297 .modes = &sharp_lq070y3dg3b_mode, 3298 .num_modes = 1, 3299 .bpc = 8, 3300 .size = { 3301 .width = 152, /* 152.4mm */ 3302 .height = 91, /* 91.4mm */ 3303 }, 3304 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3305 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3306 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3307 }; 3308 3309 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3310 .clock = 5500, 3311 .hdisplay = 240, 3312 .hsync_start = 240 + 16, 3313 .hsync_end = 240 + 16 + 7, 3314 .htotal = 240 + 16 + 7 + 5, 3315 .vdisplay = 320, 3316 .vsync_start = 320 + 9, 3317 .vsync_end = 320 + 9 + 1, 3318 .vtotal = 320 + 9 + 1 + 7, 3319 }; 3320 3321 static const struct panel_desc sharp_lq035q7db03 = { 3322 .modes = &sharp_lq035q7db03_mode, 3323 .num_modes = 1, 3324 .bpc = 6, 3325 .size = { 3326 .width = 54, 3327 .height = 72, 3328 }, 3329 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3330 }; 3331 3332 static const struct display_timing sharp_lq101k1ly04_timing = { 3333 .pixelclock = { 60000000, 65000000, 80000000 }, 3334 .hactive = { 1280, 1280, 1280 }, 3335 .hfront_porch = { 20, 20, 20 }, 3336 .hback_porch = { 20, 20, 20 }, 3337 .hsync_len = { 10, 10, 10 }, 3338 .vactive = { 800, 800, 800 }, 3339 .vfront_porch = { 4, 4, 4 }, 3340 .vback_porch = { 4, 4, 4 }, 3341 .vsync_len = { 4, 4, 4 }, 3342 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3343 }; 3344 3345 static const struct panel_desc sharp_lq101k1ly04 = { 3346 .timings = &sharp_lq101k1ly04_timing, 3347 .num_timings = 1, 3348 .bpc = 8, 3349 .size = { 3350 .width = 217, 3351 .height = 136, 3352 }, 3353 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3354 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3355 }; 3356 3357 static const struct display_timing sharp_lq123p1jx31_timing = { 3358 .pixelclock = { 252750000, 252750000, 266604720 }, 3359 .hactive = { 2400, 2400, 2400 }, 3360 .hfront_porch = { 48, 48, 48 }, 3361 .hback_porch = { 80, 80, 84 }, 3362 .hsync_len = { 32, 32, 32 }, 3363 .vactive = { 1600, 1600, 1600 }, 3364 .vfront_porch = { 3, 3, 3 }, 3365 .vback_porch = { 33, 33, 120 }, 3366 .vsync_len = { 10, 10, 10 }, 3367 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3368 }; 3369 3370 static const struct panel_desc sharp_lq123p1jx31 = { 3371 .timings = &sharp_lq123p1jx31_timing, 3372 .num_timings = 1, 3373 .bpc = 8, 3374 .size = { 3375 .width = 259, 3376 .height = 173, 3377 }, 3378 .delay = { 3379 .prepare = 110, 3380 .enable = 50, 3381 .unprepare = 550, 3382 }, 3383 }; 3384 3385 static const struct display_timing sharp_ls020b1dd01d_timing = { 3386 .pixelclock = { 2000000, 4200000, 5000000 }, 3387 .hactive = { 240, 240, 240 }, 3388 .hfront_porch = { 66, 66, 66 }, 3389 .hback_porch = { 1, 1, 1 }, 3390 .hsync_len = { 1, 1, 1 }, 3391 .vactive = { 160, 160, 160 }, 3392 .vfront_porch = { 52, 52, 52 }, 3393 .vback_porch = { 6, 6, 6 }, 3394 .vsync_len = { 10, 10, 10 }, 3395 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3396 }; 3397 3398 static const struct panel_desc sharp_ls020b1dd01d = { 3399 .timings = &sharp_ls020b1dd01d_timing, 3400 .num_timings = 1, 3401 .bpc = 6, 3402 .size = { 3403 .width = 42, 3404 .height = 28, 3405 }, 3406 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3407 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3408 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3409 | DRM_BUS_FLAG_SHARP_SIGNALS, 3410 }; 3411 3412 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3413 .clock = 33300, 3414 .hdisplay = 800, 3415 .hsync_start = 800 + 1, 3416 .hsync_end = 800 + 1 + 64, 3417 .htotal = 800 + 1 + 64 + 64, 3418 .vdisplay = 480, 3419 .vsync_start = 480 + 1, 3420 .vsync_end = 480 + 1 + 23, 3421 .vtotal = 480 + 1 + 23 + 22, 3422 }; 3423 3424 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3425 .modes = &shelly_sca07010_bfn_lnn_mode, 3426 .num_modes = 1, 3427 .size = { 3428 .width = 152, 3429 .height = 91, 3430 }, 3431 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3432 }; 3433 3434 static const struct drm_display_mode starry_kr070pe2t_mode = { 3435 .clock = 33000, 3436 .hdisplay = 800, 3437 .hsync_start = 800 + 209, 3438 .hsync_end = 800 + 209 + 1, 3439 .htotal = 800 + 209 + 1 + 45, 3440 .vdisplay = 480, 3441 .vsync_start = 480 + 22, 3442 .vsync_end = 480 + 22 + 1, 3443 .vtotal = 480 + 22 + 1 + 22, 3444 }; 3445 3446 static const struct panel_desc starry_kr070pe2t = { 3447 .modes = &starry_kr070pe2t_mode, 3448 .num_modes = 1, 3449 .bpc = 8, 3450 .size = { 3451 .width = 152, 3452 .height = 86, 3453 }, 3454 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3455 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3456 .connector_type = DRM_MODE_CONNECTOR_DPI, 3457 }; 3458 3459 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3460 .clock = 147000, 3461 .hdisplay = 1920, 3462 .hsync_start = 1920 + 16, 3463 .hsync_end = 1920 + 16 + 16, 3464 .htotal = 1920 + 16 + 16 + 32, 3465 .vdisplay = 1200, 3466 .vsync_start = 1200 + 15, 3467 .vsync_end = 1200 + 15 + 2, 3468 .vtotal = 1200 + 15 + 2 + 18, 3469 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3470 }; 3471 3472 static const struct panel_desc starry_kr122ea0sra = { 3473 .modes = &starry_kr122ea0sra_mode, 3474 .num_modes = 1, 3475 .size = { 3476 .width = 263, 3477 .height = 164, 3478 }, 3479 .delay = { 3480 .prepare = 10 + 200, 3481 .enable = 50, 3482 .unprepare = 10 + 500, 3483 }, 3484 }; 3485 3486 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3487 .clock = 30000, 3488 .hdisplay = 800, 3489 .hsync_start = 800 + 39, 3490 .hsync_end = 800 + 39 + 47, 3491 .htotal = 800 + 39 + 47 + 39, 3492 .vdisplay = 480, 3493 .vsync_start = 480 + 13, 3494 .vsync_end = 480 + 13 + 2, 3495 .vtotal = 480 + 13 + 2 + 29, 3496 }; 3497 3498 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3499 .modes = &tfc_s9700rtwv43tr_01b_mode, 3500 .num_modes = 1, 3501 .bpc = 8, 3502 .size = { 3503 .width = 155, 3504 .height = 90, 3505 }, 3506 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3507 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3508 }; 3509 3510 static const struct display_timing tianma_tm070jdhg30_timing = { 3511 .pixelclock = { 62600000, 68200000, 78100000 }, 3512 .hactive = { 1280, 1280, 1280 }, 3513 .hfront_porch = { 15, 64, 159 }, 3514 .hback_porch = { 5, 5, 5 }, 3515 .hsync_len = { 1, 1, 256 }, 3516 .vactive = { 800, 800, 800 }, 3517 .vfront_porch = { 3, 40, 99 }, 3518 .vback_porch = { 2, 2, 2 }, 3519 .vsync_len = { 1, 1, 128 }, 3520 .flags = DISPLAY_FLAGS_DE_HIGH, 3521 }; 3522 3523 static const struct panel_desc tianma_tm070jdhg30 = { 3524 .timings = &tianma_tm070jdhg30_timing, 3525 .num_timings = 1, 3526 .bpc = 8, 3527 .size = { 3528 .width = 151, 3529 .height = 95, 3530 }, 3531 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3532 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3533 }; 3534 3535 static const struct panel_desc tianma_tm070jvhg33 = { 3536 .timings = &tianma_tm070jdhg30_timing, 3537 .num_timings = 1, 3538 .bpc = 8, 3539 .size = { 3540 .width = 150, 3541 .height = 94, 3542 }, 3543 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3544 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3545 }; 3546 3547 static const struct display_timing tianma_tm070rvhg71_timing = { 3548 .pixelclock = { 27700000, 29200000, 39600000 }, 3549 .hactive = { 800, 800, 800 }, 3550 .hfront_porch = { 12, 40, 212 }, 3551 .hback_porch = { 88, 88, 88 }, 3552 .hsync_len = { 1, 1, 40 }, 3553 .vactive = { 480, 480, 480 }, 3554 .vfront_porch = { 1, 13, 88 }, 3555 .vback_porch = { 32, 32, 32 }, 3556 .vsync_len = { 1, 1, 3 }, 3557 .flags = DISPLAY_FLAGS_DE_HIGH, 3558 }; 3559 3560 static const struct panel_desc tianma_tm070rvhg71 = { 3561 .timings = &tianma_tm070rvhg71_timing, 3562 .num_timings = 1, 3563 .bpc = 8, 3564 .size = { 3565 .width = 154, 3566 .height = 86, 3567 }, 3568 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3570 }; 3571 3572 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3573 { 3574 .clock = 10000, 3575 .hdisplay = 320, 3576 .hsync_start = 320 + 50, 3577 .hsync_end = 320 + 50 + 6, 3578 .htotal = 320 + 50 + 6 + 38, 3579 .vdisplay = 240, 3580 .vsync_start = 240 + 3, 3581 .vsync_end = 240 + 3 + 1, 3582 .vtotal = 240 + 3 + 1 + 17, 3583 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3584 }, 3585 }; 3586 3587 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3588 .modes = ti_nspire_cx_lcd_mode, 3589 .num_modes = 1, 3590 .bpc = 8, 3591 .size = { 3592 .width = 65, 3593 .height = 49, 3594 }, 3595 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3596 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3597 }; 3598 3599 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3600 { 3601 .clock = 10000, 3602 .hdisplay = 320, 3603 .hsync_start = 320 + 6, 3604 .hsync_end = 320 + 6 + 6, 3605 .htotal = 320 + 6 + 6 + 6, 3606 .vdisplay = 240, 3607 .vsync_start = 240 + 0, 3608 .vsync_end = 240 + 0 + 1, 3609 .vtotal = 240 + 0 + 1 + 0, 3610 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3611 }, 3612 }; 3613 3614 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3615 .modes = ti_nspire_classic_lcd_mode, 3616 .num_modes = 1, 3617 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3618 .bpc = 8, 3619 .size = { 3620 .width = 71, 3621 .height = 53, 3622 }, 3623 /* This is the grayscale bus format */ 3624 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3625 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3626 }; 3627 3628 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3629 .clock = 79500, 3630 .hdisplay = 1280, 3631 .hsync_start = 1280 + 192, 3632 .hsync_end = 1280 + 192 + 128, 3633 .htotal = 1280 + 192 + 128 + 64, 3634 .vdisplay = 768, 3635 .vsync_start = 768 + 20, 3636 .vsync_end = 768 + 20 + 7, 3637 .vtotal = 768 + 20 + 7 + 3, 3638 }; 3639 3640 static const struct panel_desc toshiba_lt089ac29000 = { 3641 .modes = &toshiba_lt089ac29000_mode, 3642 .num_modes = 1, 3643 .size = { 3644 .width = 194, 3645 .height = 116, 3646 }, 3647 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3648 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3649 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3650 }; 3651 3652 static const struct drm_display_mode tpk_f07a_0102_mode = { 3653 .clock = 33260, 3654 .hdisplay = 800, 3655 .hsync_start = 800 + 40, 3656 .hsync_end = 800 + 40 + 128, 3657 .htotal = 800 + 40 + 128 + 88, 3658 .vdisplay = 480, 3659 .vsync_start = 480 + 10, 3660 .vsync_end = 480 + 10 + 2, 3661 .vtotal = 480 + 10 + 2 + 33, 3662 }; 3663 3664 static const struct panel_desc tpk_f07a_0102 = { 3665 .modes = &tpk_f07a_0102_mode, 3666 .num_modes = 1, 3667 .size = { 3668 .width = 152, 3669 .height = 91, 3670 }, 3671 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3672 }; 3673 3674 static const struct drm_display_mode tpk_f10a_0102_mode = { 3675 .clock = 45000, 3676 .hdisplay = 1024, 3677 .hsync_start = 1024 + 176, 3678 .hsync_end = 1024 + 176 + 5, 3679 .htotal = 1024 + 176 + 5 + 88, 3680 .vdisplay = 600, 3681 .vsync_start = 600 + 20, 3682 .vsync_end = 600 + 20 + 5, 3683 .vtotal = 600 + 20 + 5 + 25, 3684 }; 3685 3686 static const struct panel_desc tpk_f10a_0102 = { 3687 .modes = &tpk_f10a_0102_mode, 3688 .num_modes = 1, 3689 .size = { 3690 .width = 223, 3691 .height = 125, 3692 }, 3693 }; 3694 3695 static const struct display_timing urt_umsh_8596md_timing = { 3696 .pixelclock = { 33260000, 33260000, 33260000 }, 3697 .hactive = { 800, 800, 800 }, 3698 .hfront_porch = { 41, 41, 41 }, 3699 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3700 .hsync_len = { 71, 128, 128 }, 3701 .vactive = { 480, 480, 480 }, 3702 .vfront_porch = { 10, 10, 10 }, 3703 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3704 .vsync_len = { 2, 2, 2 }, 3705 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3706 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3707 }; 3708 3709 static const struct panel_desc urt_umsh_8596md_lvds = { 3710 .timings = &urt_umsh_8596md_timing, 3711 .num_timings = 1, 3712 .bpc = 6, 3713 .size = { 3714 .width = 152, 3715 .height = 91, 3716 }, 3717 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3718 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3719 }; 3720 3721 static const struct panel_desc urt_umsh_8596md_parallel = { 3722 .timings = &urt_umsh_8596md_timing, 3723 .num_timings = 1, 3724 .bpc = 6, 3725 .size = { 3726 .width = 152, 3727 .height = 91, 3728 }, 3729 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3730 }; 3731 3732 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3733 .clock = 33333, 3734 .hdisplay = 800, 3735 .hsync_start = 800 + 210, 3736 .hsync_end = 800 + 210 + 20, 3737 .htotal = 800 + 210 + 20 + 46, 3738 .vdisplay = 480, 3739 .vsync_start = 480 + 22, 3740 .vsync_end = 480 + 22 + 10, 3741 .vtotal = 480 + 22 + 10 + 23, 3742 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3743 }; 3744 3745 static const struct panel_desc vl050_8048nt_c01 = { 3746 .modes = &vl050_8048nt_c01_mode, 3747 .num_modes = 1, 3748 .bpc = 8, 3749 .size = { 3750 .width = 120, 3751 .height = 76, 3752 }, 3753 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3754 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3755 }; 3756 3757 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3758 .clock = 6410, 3759 .hdisplay = 320, 3760 .hsync_start = 320 + 20, 3761 .hsync_end = 320 + 20 + 30, 3762 .htotal = 320 + 20 + 30 + 38, 3763 .vdisplay = 240, 3764 .vsync_start = 240 + 4, 3765 .vsync_end = 240 + 4 + 3, 3766 .vtotal = 240 + 4 + 3 + 15, 3767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3768 }; 3769 3770 static const struct panel_desc winstar_wf35ltiacd = { 3771 .modes = &winstar_wf35ltiacd_mode, 3772 .num_modes = 1, 3773 .bpc = 8, 3774 .size = { 3775 .width = 70, 3776 .height = 53, 3777 }, 3778 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3779 }; 3780 3781 static const struct drm_display_mode arm_rtsm_mode[] = { 3782 { 3783 .clock = 65000, 3784 .hdisplay = 1024, 3785 .hsync_start = 1024 + 24, 3786 .hsync_end = 1024 + 24 + 136, 3787 .htotal = 1024 + 24 + 136 + 160, 3788 .vdisplay = 768, 3789 .vsync_start = 768 + 3, 3790 .vsync_end = 768 + 3 + 6, 3791 .vtotal = 768 + 3 + 6 + 29, 3792 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3793 }, 3794 }; 3795 3796 static const struct panel_desc arm_rtsm = { 3797 .modes = arm_rtsm_mode, 3798 .num_modes = 1, 3799 .bpc = 8, 3800 .size = { 3801 .width = 400, 3802 .height = 300, 3803 }, 3804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3805 }; 3806 3807 static const struct of_device_id platform_of_match[] = { 3808 { 3809 .compatible = "ampire,am-480272h3tmqw-t01h", 3810 .data = &ire_am_480272h3tmqw_t01h, 3811 }, { 3812 .compatible = "ampire,am800480r3tmqwa1h", 3813 .data = &ire_am800480r3tmqwa1h, 3814 }, { 3815 .compatible = "arm,rtsm-display", 3816 .data = &arm_rtsm, 3817 }, { 3818 .compatible = "armadeus,st0700-adapt", 3819 .data = &armadeus_st0700_adapt, 3820 }, { 3821 .compatible = "auo,b101aw03", 3822 .data = &auo_b101aw03, 3823 }, { 3824 .compatible = "auo,b101ean01", 3825 .data = &auo_b101ean01, 3826 }, { 3827 .compatible = "auo,b101xtn01", 3828 .data = &auo_b101xtn01, 3829 }, { 3830 .compatible = "auo,b116xa01", 3831 .data = &auo_b116xak01, 3832 }, { 3833 .compatible = "auo,b116xw03", 3834 .data = &auo_b116xw03, 3835 }, { 3836 .compatible = "auo,b133htn01", 3837 .data = &auo_b133htn01, 3838 }, { 3839 .compatible = "auo,b133xtn01", 3840 .data = &auo_b133xtn01, 3841 }, { 3842 .compatible = "auo,g070vvn01", 3843 .data = &auo_g070vvn01, 3844 }, { 3845 .compatible = "auo,g101evn010", 3846 .data = &auo_g101evn010, 3847 }, { 3848 .compatible = "auo,g104sn02", 3849 .data = &auo_g104sn02, 3850 }, { 3851 .compatible = "auo,g121ean01", 3852 .data = &auo_g121ean01, 3853 }, { 3854 .compatible = "auo,g133han01", 3855 .data = &auo_g133han01, 3856 }, { 3857 .compatible = "auo,g156xtn01", 3858 .data = &auo_g156xtn01, 3859 }, { 3860 .compatible = "auo,g185han01", 3861 .data = &auo_g185han01, 3862 }, { 3863 .compatible = "auo,g190ean01", 3864 .data = &auo_g190ean01, 3865 }, { 3866 .compatible = "auo,p320hvn03", 3867 .data = &auo_p320hvn03, 3868 }, { 3869 .compatible = "auo,t215hvn01", 3870 .data = &auo_t215hvn01, 3871 }, { 3872 .compatible = "avic,tm070ddh03", 3873 .data = &avic_tm070ddh03, 3874 }, { 3875 .compatible = "bananapi,s070wv20-ct16", 3876 .data = &bananapi_s070wv20_ct16, 3877 }, { 3878 .compatible = "boe,hv070wsa-100", 3879 .data = &boe_hv070wsa 3880 }, { 3881 .compatible = "boe,nv101wxmn51", 3882 .data = &boe_nv101wxmn51, 3883 }, { 3884 .compatible = "boe,nv133fhm-n61", 3885 .data = &boe_nv133fhm_n61, 3886 }, { 3887 .compatible = "boe,nv133fhm-n62", 3888 .data = &boe_nv133fhm_n61, 3889 }, { 3890 .compatible = "boe,nv140fhmn49", 3891 .data = &boe_nv140fhmn49, 3892 }, { 3893 .compatible = "cdtech,s043wq26h-ct7", 3894 .data = &cdtech_s043wq26h_ct7, 3895 }, { 3896 .compatible = "cdtech,s070pws19hp-fc21", 3897 .data = &cdtech_s070pws19hp_fc21, 3898 }, { 3899 .compatible = "cdtech,s070swv29hg-dc44", 3900 .data = &cdtech_s070swv29hg_dc44, 3901 }, { 3902 .compatible = "cdtech,s070wv95-ct16", 3903 .data = &cdtech_s070wv95_ct16, 3904 }, { 3905 .compatible = "chefree,ch101olhlwh-002", 3906 .data = &chefree_ch101olhlwh_002, 3907 }, { 3908 .compatible = "chunghwa,claa070wp03xg", 3909 .data = &chunghwa_claa070wp03xg, 3910 }, { 3911 .compatible = "chunghwa,claa101wa01a", 3912 .data = &chunghwa_claa101wa01a 3913 }, { 3914 .compatible = "chunghwa,claa101wb01", 3915 .data = &chunghwa_claa101wb01 3916 }, { 3917 .compatible = "dataimage,scf0700c48ggu18", 3918 .data = &dataimage_scf0700c48ggu18, 3919 }, { 3920 .compatible = "dlc,dlc0700yzg-1", 3921 .data = &dlc_dlc0700yzg_1, 3922 }, { 3923 .compatible = "dlc,dlc1010gig", 3924 .data = &dlc_dlc1010gig, 3925 }, { 3926 .compatible = "edt,et035012dm6", 3927 .data = &edt_et035012dm6, 3928 }, { 3929 .compatible = "edt,etm043080dh6gp", 3930 .data = &edt_etm043080dh6gp, 3931 }, { 3932 .compatible = "edt,etm0430g0dh6", 3933 .data = &edt_etm0430g0dh6, 3934 }, { 3935 .compatible = "edt,et057090dhu", 3936 .data = &edt_et057090dhu, 3937 }, { 3938 .compatible = "edt,et070080dh6", 3939 .data = &edt_etm0700g0dh6, 3940 }, { 3941 .compatible = "edt,etm0700g0dh6", 3942 .data = &edt_etm0700g0dh6, 3943 }, { 3944 .compatible = "edt,etm0700g0bdh6", 3945 .data = &edt_etm0700g0bdh6, 3946 }, { 3947 .compatible = "edt,etm0700g0edh6", 3948 .data = &edt_etm0700g0bdh6, 3949 }, { 3950 .compatible = "evervision,vgg804821", 3951 .data = &evervision_vgg804821, 3952 }, { 3953 .compatible = "foxlink,fl500wvr00-a0t", 3954 .data = &foxlink_fl500wvr00_a0t, 3955 }, { 3956 .compatible = "frida,frd350h54004", 3957 .data = &frida_frd350h54004, 3958 }, { 3959 .compatible = "friendlyarm,hd702e", 3960 .data = &friendlyarm_hd702e, 3961 }, { 3962 .compatible = "giantplus,gpg482739qs5", 3963 .data = &giantplus_gpg482739qs5 3964 }, { 3965 .compatible = "giantplus,gpm940b0", 3966 .data = &giantplus_gpm940b0, 3967 }, { 3968 .compatible = "hannstar,hsd070pww1", 3969 .data = &hannstar_hsd070pww1, 3970 }, { 3971 .compatible = "hannstar,hsd100pxn1", 3972 .data = &hannstar_hsd100pxn1, 3973 }, { 3974 .compatible = "hit,tx23d38vm0caa", 3975 .data = &hitachi_tx23d38vm0caa 3976 }, { 3977 .compatible = "innolux,at043tn24", 3978 .data = &innolux_at043tn24, 3979 }, { 3980 .compatible = "innolux,at070tn92", 3981 .data = &innolux_at070tn92, 3982 }, { 3983 .compatible = "innolux,g070y2-l01", 3984 .data = &innolux_g070y2_l01, 3985 }, { 3986 .compatible = "innolux,g101ice-l01", 3987 .data = &innolux_g101ice_l01 3988 }, { 3989 .compatible = "innolux,g121i1-l01", 3990 .data = &innolux_g121i1_l01 3991 }, { 3992 .compatible = "innolux,g121x1-l03", 3993 .data = &innolux_g121x1_l03, 3994 }, { 3995 .compatible = "innolux,n116bge", 3996 .data = &innolux_n116bge, 3997 }, { 3998 .compatible = "innolux,n156bge-l21", 3999 .data = &innolux_n156bge_l21, 4000 }, { 4001 .compatible = "innolux,p120zdg-bf1", 4002 .data = &innolux_p120zdg_bf1, 4003 }, { 4004 .compatible = "innolux,zj070na-01p", 4005 .data = &innolux_zj070na_01p, 4006 }, { 4007 .compatible = "ivo,m133nwf4-r0", 4008 .data = &ivo_m133nwf4_r0, 4009 }, { 4010 .compatible = "koe,tx14d24vm1bpa", 4011 .data = &koe_tx14d24vm1bpa, 4012 }, { 4013 .compatible = "koe,tx26d202vm0bwa", 4014 .data = &koe_tx26d202vm0bwa, 4015 }, { 4016 .compatible = "koe,tx31d200vm0baa", 4017 .data = &koe_tx31d200vm0baa, 4018 }, { 4019 .compatible = "kyo,tcg121xglp", 4020 .data = &kyo_tcg121xglp, 4021 }, { 4022 .compatible = "lemaker,bl035-rgb-002", 4023 .data = &lemaker_bl035_rgb_002, 4024 }, { 4025 .compatible = "lg,lb070wv8", 4026 .data = &lg_lb070wv8, 4027 }, { 4028 .compatible = "lg,lp079qx1-sp0v", 4029 .data = &lg_lp079qx1_sp0v, 4030 }, { 4031 .compatible = "lg,lp097qx1-spa1", 4032 .data = &lg_lp097qx1_spa1, 4033 }, { 4034 .compatible = "lg,lp120up1", 4035 .data = &lg_lp120up1, 4036 }, { 4037 .compatible = "lg,lp129qe", 4038 .data = &lg_lp129qe, 4039 }, { 4040 .compatible = "logicpd,type28", 4041 .data = &logicpd_type_28, 4042 }, { 4043 .compatible = "logictechno,lt161010-2nhc", 4044 .data = &logictechno_lt161010_2nh, 4045 }, { 4046 .compatible = "logictechno,lt161010-2nhr", 4047 .data = &logictechno_lt161010_2nh, 4048 }, { 4049 .compatible = "logictechno,lt170410-2whc", 4050 .data = &logictechno_lt170410_2whc, 4051 }, { 4052 .compatible = "mitsubishi,aa070mc01-ca1", 4053 .data = &mitsubishi_aa070mc01, 4054 }, { 4055 .compatible = "nec,nl12880bc20-05", 4056 .data = &nec_nl12880bc20_05, 4057 }, { 4058 .compatible = "nec,nl4827hc19-05b", 4059 .data = &nec_nl4827hc19_05b, 4060 }, { 4061 .compatible = "netron-dy,e231732", 4062 .data = &netron_dy_e231732, 4063 }, { 4064 .compatible = "neweast,wjfh116008a", 4065 .data = &neweast_wjfh116008a, 4066 }, { 4067 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4068 .data = &newhaven_nhd_43_480272ef_atxl, 4069 }, { 4070 .compatible = "nlt,nl192108ac18-02d", 4071 .data = &nlt_nl192108ac18_02d, 4072 }, { 4073 .compatible = "nvd,9128", 4074 .data = &nvd_9128, 4075 }, { 4076 .compatible = "okaya,rs800480t-7x0gp", 4077 .data = &okaya_rs800480t_7x0gp, 4078 }, { 4079 .compatible = "olimex,lcd-olinuxino-43-ts", 4080 .data = &olimex_lcd_olinuxino_43ts, 4081 }, { 4082 .compatible = "ontat,yx700wv03", 4083 .data = &ontat_yx700wv03, 4084 }, { 4085 .compatible = "ortustech,com37h3m05dtc", 4086 .data = &ortustech_com37h3m, 4087 }, { 4088 .compatible = "ortustech,com37h3m99dtc", 4089 .data = &ortustech_com37h3m, 4090 }, { 4091 .compatible = "ortustech,com43h4m85ulc", 4092 .data = &ortustech_com43h4m85ulc, 4093 }, { 4094 .compatible = "osddisplays,osd070t1718-19ts", 4095 .data = &osddisplays_osd070t1718_19ts, 4096 }, { 4097 .compatible = "pda,91-00156-a0", 4098 .data = &pda_91_00156_a0, 4099 }, { 4100 .compatible = "powertip,ph800480t013-idf02", 4101 .data = &powertip_ph800480t013_idf02, 4102 }, { 4103 .compatible = "qiaodian,qd43003c0-40", 4104 .data = &qd43003c0_40, 4105 }, { 4106 .compatible = "rocktech,rk070er9427", 4107 .data = &rocktech_rk070er9427, 4108 }, { 4109 .compatible = "rocktech,rk101ii01d-ct", 4110 .data = &rocktech_rk101ii01d_ct, 4111 }, { 4112 .compatible = "samsung,lsn122dl01-c01", 4113 .data = &samsung_lsn122dl01_c01, 4114 }, { 4115 .compatible = "samsung,ltn101nt05", 4116 .data = &samsung_ltn101nt05, 4117 }, { 4118 .compatible = "samsung,ltn140at29-301", 4119 .data = &samsung_ltn140at29_301, 4120 }, { 4121 .compatible = "satoz,sat050at40h12r2", 4122 .data = &satoz_sat050at40h12r2, 4123 }, { 4124 .compatible = "sharp,ld-d5116z01b", 4125 .data = &sharp_ld_d5116z01b, 4126 }, { 4127 .compatible = "sharp,lq035q7db03", 4128 .data = &sharp_lq035q7db03, 4129 }, { 4130 .compatible = "sharp,lq070y3dg3b", 4131 .data = &sharp_lq070y3dg3b, 4132 }, { 4133 .compatible = "sharp,lq101k1ly04", 4134 .data = &sharp_lq101k1ly04, 4135 }, { 4136 .compatible = "sharp,lq123p1jx31", 4137 .data = &sharp_lq123p1jx31, 4138 }, { 4139 .compatible = "sharp,ls020b1dd01d", 4140 .data = &sharp_ls020b1dd01d, 4141 }, { 4142 .compatible = "shelly,sca07010-bfn-lnn", 4143 .data = &shelly_sca07010_bfn_lnn, 4144 }, { 4145 .compatible = "starry,kr070pe2t", 4146 .data = &starry_kr070pe2t, 4147 }, { 4148 .compatible = "starry,kr122ea0sra", 4149 .data = &starry_kr122ea0sra, 4150 }, { 4151 .compatible = "tfc,s9700rtwv43tr-01b", 4152 .data = &tfc_s9700rtwv43tr_01b, 4153 }, { 4154 .compatible = "tianma,tm070jdhg30", 4155 .data = &tianma_tm070jdhg30, 4156 }, { 4157 .compatible = "tianma,tm070jvhg33", 4158 .data = &tianma_tm070jvhg33, 4159 }, { 4160 .compatible = "tianma,tm070rvhg71", 4161 .data = &tianma_tm070rvhg71, 4162 }, { 4163 .compatible = "ti,nspire-cx-lcd-panel", 4164 .data = &ti_nspire_cx_lcd_panel, 4165 }, { 4166 .compatible = "ti,nspire-classic-lcd-panel", 4167 .data = &ti_nspire_classic_lcd_panel, 4168 }, { 4169 .compatible = "toshiba,lt089ac29000", 4170 .data = &toshiba_lt089ac29000, 4171 }, { 4172 .compatible = "tpk,f07a-0102", 4173 .data = &tpk_f07a_0102, 4174 }, { 4175 .compatible = "tpk,f10a-0102", 4176 .data = &tpk_f10a_0102, 4177 }, { 4178 .compatible = "urt,umsh-8596md-t", 4179 .data = &urt_umsh_8596md_parallel, 4180 }, { 4181 .compatible = "urt,umsh-8596md-1t", 4182 .data = &urt_umsh_8596md_parallel, 4183 }, { 4184 .compatible = "urt,umsh-8596md-7t", 4185 .data = &urt_umsh_8596md_parallel, 4186 }, { 4187 .compatible = "urt,umsh-8596md-11t", 4188 .data = &urt_umsh_8596md_lvds, 4189 }, { 4190 .compatible = "urt,umsh-8596md-19t", 4191 .data = &urt_umsh_8596md_lvds, 4192 }, { 4193 .compatible = "urt,umsh-8596md-20t", 4194 .data = &urt_umsh_8596md_parallel, 4195 }, { 4196 .compatible = "vxt,vl050-8048nt-c01", 4197 .data = &vl050_8048nt_c01, 4198 }, { 4199 .compatible = "winstar,wf35ltiacd", 4200 .data = &winstar_wf35ltiacd, 4201 }, { 4202 /* Must be the last entry */ 4203 .compatible = "panel-dpi", 4204 .data = &panel_dpi, 4205 }, { 4206 /* sentinel */ 4207 } 4208 }; 4209 MODULE_DEVICE_TABLE(of, platform_of_match); 4210 4211 static int panel_simple_platform_probe(struct platform_device *pdev) 4212 { 4213 const struct of_device_id *id; 4214 4215 id = of_match_node(platform_of_match, pdev->dev.of_node); 4216 if (!id) 4217 return -ENODEV; 4218 4219 return panel_simple_probe(&pdev->dev, id->data); 4220 } 4221 4222 static int panel_simple_platform_remove(struct platform_device *pdev) 4223 { 4224 return panel_simple_remove(&pdev->dev); 4225 } 4226 4227 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4228 { 4229 panel_simple_shutdown(&pdev->dev); 4230 } 4231 4232 static struct platform_driver panel_simple_platform_driver = { 4233 .driver = { 4234 .name = "panel-simple", 4235 .of_match_table = platform_of_match, 4236 }, 4237 .probe = panel_simple_platform_probe, 4238 .remove = panel_simple_platform_remove, 4239 .shutdown = panel_simple_platform_shutdown, 4240 }; 4241 4242 struct panel_desc_dsi { 4243 struct panel_desc desc; 4244 4245 unsigned long flags; 4246 enum mipi_dsi_pixel_format format; 4247 unsigned int lanes; 4248 }; 4249 4250 static const struct drm_display_mode auo_b080uan01_mode = { 4251 .clock = 154500, 4252 .hdisplay = 1200, 4253 .hsync_start = 1200 + 62, 4254 .hsync_end = 1200 + 62 + 4, 4255 .htotal = 1200 + 62 + 4 + 62, 4256 .vdisplay = 1920, 4257 .vsync_start = 1920 + 9, 4258 .vsync_end = 1920 + 9 + 2, 4259 .vtotal = 1920 + 9 + 2 + 8, 4260 }; 4261 4262 static const struct panel_desc_dsi auo_b080uan01 = { 4263 .desc = { 4264 .modes = &auo_b080uan01_mode, 4265 .num_modes = 1, 4266 .bpc = 8, 4267 .size = { 4268 .width = 108, 4269 .height = 272, 4270 }, 4271 .connector_type = DRM_MODE_CONNECTOR_DSI, 4272 }, 4273 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4274 .format = MIPI_DSI_FMT_RGB888, 4275 .lanes = 4, 4276 }; 4277 4278 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4279 .clock = 160000, 4280 .hdisplay = 1200, 4281 .hsync_start = 1200 + 120, 4282 .hsync_end = 1200 + 120 + 20, 4283 .htotal = 1200 + 120 + 20 + 21, 4284 .vdisplay = 1920, 4285 .vsync_start = 1920 + 21, 4286 .vsync_end = 1920 + 21 + 3, 4287 .vtotal = 1920 + 21 + 3 + 18, 4288 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4289 }; 4290 4291 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4292 .desc = { 4293 .modes = &boe_tv080wum_nl0_mode, 4294 .num_modes = 1, 4295 .size = { 4296 .width = 107, 4297 .height = 172, 4298 }, 4299 .connector_type = DRM_MODE_CONNECTOR_DSI, 4300 }, 4301 .flags = MIPI_DSI_MODE_VIDEO | 4302 MIPI_DSI_MODE_VIDEO_BURST | 4303 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4304 .format = MIPI_DSI_FMT_RGB888, 4305 .lanes = 4, 4306 }; 4307 4308 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4309 .clock = 71000, 4310 .hdisplay = 800, 4311 .hsync_start = 800 + 32, 4312 .hsync_end = 800 + 32 + 1, 4313 .htotal = 800 + 32 + 1 + 57, 4314 .vdisplay = 1280, 4315 .vsync_start = 1280 + 28, 4316 .vsync_end = 1280 + 28 + 1, 4317 .vtotal = 1280 + 28 + 1 + 14, 4318 }; 4319 4320 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4321 .desc = { 4322 .modes = &lg_ld070wx3_sl01_mode, 4323 .num_modes = 1, 4324 .bpc = 8, 4325 .size = { 4326 .width = 94, 4327 .height = 151, 4328 }, 4329 .connector_type = DRM_MODE_CONNECTOR_DSI, 4330 }, 4331 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4332 .format = MIPI_DSI_FMT_RGB888, 4333 .lanes = 4, 4334 }; 4335 4336 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4337 .clock = 67000, 4338 .hdisplay = 720, 4339 .hsync_start = 720 + 12, 4340 .hsync_end = 720 + 12 + 4, 4341 .htotal = 720 + 12 + 4 + 112, 4342 .vdisplay = 1280, 4343 .vsync_start = 1280 + 8, 4344 .vsync_end = 1280 + 8 + 4, 4345 .vtotal = 1280 + 8 + 4 + 12, 4346 }; 4347 4348 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4349 .desc = { 4350 .modes = &lg_lh500wx1_sd03_mode, 4351 .num_modes = 1, 4352 .bpc = 8, 4353 .size = { 4354 .width = 62, 4355 .height = 110, 4356 }, 4357 .connector_type = DRM_MODE_CONNECTOR_DSI, 4358 }, 4359 .flags = MIPI_DSI_MODE_VIDEO, 4360 .format = MIPI_DSI_FMT_RGB888, 4361 .lanes = 4, 4362 }; 4363 4364 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4365 .clock = 157200, 4366 .hdisplay = 1920, 4367 .hsync_start = 1920 + 154, 4368 .hsync_end = 1920 + 154 + 16, 4369 .htotal = 1920 + 154 + 16 + 32, 4370 .vdisplay = 1200, 4371 .vsync_start = 1200 + 17, 4372 .vsync_end = 1200 + 17 + 2, 4373 .vtotal = 1200 + 17 + 2 + 16, 4374 }; 4375 4376 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4377 .desc = { 4378 .modes = &panasonic_vvx10f004b00_mode, 4379 .num_modes = 1, 4380 .bpc = 8, 4381 .size = { 4382 .width = 217, 4383 .height = 136, 4384 }, 4385 .connector_type = DRM_MODE_CONNECTOR_DSI, 4386 }, 4387 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4388 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4389 .format = MIPI_DSI_FMT_RGB888, 4390 .lanes = 4, 4391 }; 4392 4393 static const struct drm_display_mode lg_acx467akm_7_mode = { 4394 .clock = 150000, 4395 .hdisplay = 1080, 4396 .hsync_start = 1080 + 2, 4397 .hsync_end = 1080 + 2 + 2, 4398 .htotal = 1080 + 2 + 2 + 2, 4399 .vdisplay = 1920, 4400 .vsync_start = 1920 + 2, 4401 .vsync_end = 1920 + 2 + 2, 4402 .vtotal = 1920 + 2 + 2 + 2, 4403 }; 4404 4405 static const struct panel_desc_dsi lg_acx467akm_7 = { 4406 .desc = { 4407 .modes = &lg_acx467akm_7_mode, 4408 .num_modes = 1, 4409 .bpc = 8, 4410 .size = { 4411 .width = 62, 4412 .height = 110, 4413 }, 4414 .connector_type = DRM_MODE_CONNECTOR_DSI, 4415 }, 4416 .flags = 0, 4417 .format = MIPI_DSI_FMT_RGB888, 4418 .lanes = 4, 4419 }; 4420 4421 static const struct drm_display_mode osd101t2045_53ts_mode = { 4422 .clock = 154500, 4423 .hdisplay = 1920, 4424 .hsync_start = 1920 + 112, 4425 .hsync_end = 1920 + 112 + 16, 4426 .htotal = 1920 + 112 + 16 + 32, 4427 .vdisplay = 1200, 4428 .vsync_start = 1200 + 16, 4429 .vsync_end = 1200 + 16 + 2, 4430 .vtotal = 1200 + 16 + 2 + 16, 4431 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4432 }; 4433 4434 static const struct panel_desc_dsi osd101t2045_53ts = { 4435 .desc = { 4436 .modes = &osd101t2045_53ts_mode, 4437 .num_modes = 1, 4438 .bpc = 8, 4439 .size = { 4440 .width = 217, 4441 .height = 136, 4442 }, 4443 .connector_type = DRM_MODE_CONNECTOR_DSI, 4444 }, 4445 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4446 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4447 MIPI_DSI_MODE_EOT_PACKET, 4448 .format = MIPI_DSI_FMT_RGB888, 4449 .lanes = 4, 4450 }; 4451 4452 static const struct of_device_id dsi_of_match[] = { 4453 { 4454 .compatible = "auo,b080uan01", 4455 .data = &auo_b080uan01 4456 }, { 4457 .compatible = "boe,tv080wum-nl0", 4458 .data = &boe_tv080wum_nl0 4459 }, { 4460 .compatible = "lg,ld070wx3-sl01", 4461 .data = &lg_ld070wx3_sl01 4462 }, { 4463 .compatible = "lg,lh500wx1-sd03", 4464 .data = &lg_lh500wx1_sd03 4465 }, { 4466 .compatible = "panasonic,vvx10f004b00", 4467 .data = &panasonic_vvx10f004b00 4468 }, { 4469 .compatible = "lg,acx467akm-7", 4470 .data = &lg_acx467akm_7 4471 }, { 4472 .compatible = "osddisplays,osd101t2045-53ts", 4473 .data = &osd101t2045_53ts 4474 }, { 4475 /* sentinel */ 4476 } 4477 }; 4478 MODULE_DEVICE_TABLE(of, dsi_of_match); 4479 4480 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4481 { 4482 const struct panel_desc_dsi *desc; 4483 const struct of_device_id *id; 4484 int err; 4485 4486 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4487 if (!id) 4488 return -ENODEV; 4489 4490 desc = id->data; 4491 4492 err = panel_simple_probe(&dsi->dev, &desc->desc); 4493 if (err < 0) 4494 return err; 4495 4496 dsi->mode_flags = desc->flags; 4497 dsi->format = desc->format; 4498 dsi->lanes = desc->lanes; 4499 4500 err = mipi_dsi_attach(dsi); 4501 if (err) { 4502 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4503 4504 drm_panel_remove(&panel->base); 4505 } 4506 4507 return err; 4508 } 4509 4510 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4511 { 4512 int err; 4513 4514 err = mipi_dsi_detach(dsi); 4515 if (err < 0) 4516 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4517 4518 return panel_simple_remove(&dsi->dev); 4519 } 4520 4521 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4522 { 4523 panel_simple_shutdown(&dsi->dev); 4524 } 4525 4526 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4527 .driver = { 4528 .name = "panel-simple-dsi", 4529 .of_match_table = dsi_of_match, 4530 }, 4531 .probe = panel_simple_dsi_probe, 4532 .remove = panel_simple_dsi_remove, 4533 .shutdown = panel_simple_dsi_shutdown, 4534 }; 4535 4536 static int __init panel_simple_init(void) 4537 { 4538 int err; 4539 4540 err = platform_driver_register(&panel_simple_platform_driver); 4541 if (err < 0) 4542 return err; 4543 4544 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4545 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4546 if (err < 0) 4547 return err; 4548 } 4549 4550 return 0; 4551 } 4552 module_init(panel_simple_init); 4553 4554 static void __exit panel_simple_exit(void) 4555 { 4556 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4557 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4558 4559 platform_driver_unregister(&panel_simple_platform_driver); 4560 } 4561 module_exit(panel_simple_exit); 4562 4563 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4564 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4565 MODULE_LICENSE("GPL and additional rights"); 4566