1 /*
2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the
12  * next paragraph) shall be included in all copies or substantial portions
13  * of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/backlight.h>
25 #include <linux/delay.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31 
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35 
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40 
41 /**
42  * @modes: Pointer to array of fixed modes appropriate for this panel.  If
43  *         only one mode then this can just be the address of this the mode.
44  *         NOTE: cannot be used with "timings" and also if this is specified
45  *         then you cannot override the mode in the device tree.
46  * @num_modes: Number of elements in modes array.
47  * @timings: Pointer to array of display timings.  NOTE: cannot be used with
48  *           "modes" and also these will be used to validate a device tree
49  *           override if one is present.
50  * @num_timings: Number of elements in timings array.
51  * @bpc: Bits per color.
52  * @size: Structure containing the physical size of this panel.
53  * @delay: Structure containing various delay values for this panel.
54  * @bus_format: See MEDIA_BUS_FMT_... defines.
55  * @bus_flags: See DRM_BUS_FLAG_... defines.
56  */
57 struct panel_desc {
58 	const struct drm_display_mode *modes;
59 	unsigned int num_modes;
60 	const struct display_timing *timings;
61 	unsigned int num_timings;
62 
63 	unsigned int bpc;
64 
65 	/**
66 	 * @width: width (in millimeters) of the panel's active display area
67 	 * @height: height (in millimeters) of the panel's active display area
68 	 */
69 	struct {
70 		unsigned int width;
71 		unsigned int height;
72 	} size;
73 
74 	/**
75 	 * @prepare: the time (in milliseconds) that it takes for the panel to
76 	 *           become ready and start receiving video data
77 	 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 	 *                    Plug Detect isn't used.
79 	 * @enable: the time (in milliseconds) that it takes for the panel to
80 	 *          display the first valid frame after starting to receive
81 	 *          video data
82 	 * @disable: the time (in milliseconds) that it takes for the panel to
83 	 *           turn the display off (no content is visible)
84 	 * @unprepare: the time (in milliseconds) that it takes for the panel
85 	 *             to power itself down completely
86 	 */
87 	struct {
88 		unsigned int prepare;
89 		unsigned int hpd_absent_delay;
90 		unsigned int enable;
91 		unsigned int disable;
92 		unsigned int unprepare;
93 	} delay;
94 
95 	u32 bus_format;
96 	u32 bus_flags;
97 };
98 
99 struct panel_simple {
100 	struct drm_panel base;
101 	bool prepared;
102 	bool enabled;
103 	bool no_hpd;
104 
105 	const struct panel_desc *desc;
106 
107 	struct backlight_device *backlight;
108 	struct regulator *supply;
109 	struct i2c_adapter *ddc;
110 
111 	struct gpio_desc *enable_gpio;
112 
113 	struct drm_display_mode override_mode;
114 };
115 
116 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117 {
118 	return container_of(panel, struct panel_simple, base);
119 }
120 
121 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
122 {
123 	struct drm_connector *connector = panel->base.connector;
124 	struct drm_device *drm = panel->base.drm;
125 	struct drm_display_mode *mode;
126 	unsigned int i, num = 0;
127 
128 	for (i = 0; i < panel->desc->num_timings; i++) {
129 		const struct display_timing *dt = &panel->desc->timings[i];
130 		struct videomode vm;
131 
132 		videomode_from_timing(dt, &vm);
133 		mode = drm_mode_create(drm);
134 		if (!mode) {
135 			dev_err(drm->dev, "failed to add mode %ux%u\n",
136 				dt->hactive.typ, dt->vactive.typ);
137 			continue;
138 		}
139 
140 		drm_display_mode_from_videomode(&vm, mode);
141 
142 		mode->type |= DRM_MODE_TYPE_DRIVER;
143 
144 		if (panel->desc->num_timings == 1)
145 			mode->type |= DRM_MODE_TYPE_PREFERRED;
146 
147 		drm_mode_probed_add(connector, mode);
148 		num++;
149 	}
150 
151 	return num;
152 }
153 
154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
155 {
156 	struct drm_connector *connector = panel->base.connector;
157 	struct drm_device *drm = panel->base.drm;
158 	struct drm_display_mode *mode;
159 	unsigned int i, num = 0;
160 
161 	for (i = 0; i < panel->desc->num_modes; i++) {
162 		const struct drm_display_mode *m = &panel->desc->modes[i];
163 
164 		mode = drm_mode_duplicate(drm, m);
165 		if (!mode) {
166 			dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
167 				m->hdisplay, m->vdisplay, m->vrefresh);
168 			continue;
169 		}
170 
171 		mode->type |= DRM_MODE_TYPE_DRIVER;
172 
173 		if (panel->desc->num_modes == 1)
174 			mode->type |= DRM_MODE_TYPE_PREFERRED;
175 
176 		drm_mode_set_name(mode);
177 
178 		drm_mode_probed_add(connector, mode);
179 		num++;
180 	}
181 
182 	return num;
183 }
184 
185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
186 {
187 	struct drm_connector *connector = panel->base.connector;
188 	struct drm_device *drm = panel->base.drm;
189 	struct drm_display_mode *mode;
190 	bool has_override = panel->override_mode.type;
191 	unsigned int num = 0;
192 
193 	if (!panel->desc)
194 		return 0;
195 
196 	if (has_override) {
197 		mode = drm_mode_duplicate(drm, &panel->override_mode);
198 		if (mode) {
199 			drm_mode_probed_add(connector, mode);
200 			num = 1;
201 		} else {
202 			dev_err(drm->dev, "failed to add override mode\n");
203 		}
204 	}
205 
206 	/* Only add timings if override was not there or failed to validate */
207 	if (num == 0 && panel->desc->num_timings)
208 		num = panel_simple_get_timings_modes(panel);
209 
210 	/*
211 	 * Only add fixed modes if timings/override added no mode.
212 	 *
213 	 * We should only ever have either the display timings specified
214 	 * or a fixed mode. Anything else is rather bogus.
215 	 */
216 	WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 	if (num == 0)
218 		num = panel_simple_get_display_modes(panel);
219 
220 	connector->display_info.bpc = panel->desc->bpc;
221 	connector->display_info.width_mm = panel->desc->size.width;
222 	connector->display_info.height_mm = panel->desc->size.height;
223 	if (panel->desc->bus_format)
224 		drm_display_info_set_bus_formats(&connector->display_info,
225 						 &panel->desc->bus_format, 1);
226 	connector->display_info.bus_flags = panel->desc->bus_flags;
227 
228 	return num;
229 }
230 
231 static int panel_simple_disable(struct drm_panel *panel)
232 {
233 	struct panel_simple *p = to_panel_simple(panel);
234 
235 	if (!p->enabled)
236 		return 0;
237 
238 	if (p->backlight) {
239 		p->backlight->props.power = FB_BLANK_POWERDOWN;
240 		p->backlight->props.state |= BL_CORE_FBBLANK;
241 		backlight_update_status(p->backlight);
242 	}
243 
244 	if (p->desc->delay.disable)
245 		msleep(p->desc->delay.disable);
246 
247 	p->enabled = false;
248 
249 	return 0;
250 }
251 
252 static int panel_simple_unprepare(struct drm_panel *panel)
253 {
254 	struct panel_simple *p = to_panel_simple(panel);
255 
256 	if (!p->prepared)
257 		return 0;
258 
259 	gpiod_set_value_cansleep(p->enable_gpio, 0);
260 
261 	regulator_disable(p->supply);
262 
263 	if (p->desc->delay.unprepare)
264 		msleep(p->desc->delay.unprepare);
265 
266 	p->prepared = false;
267 
268 	return 0;
269 }
270 
271 static int panel_simple_prepare(struct drm_panel *panel)
272 {
273 	struct panel_simple *p = to_panel_simple(panel);
274 	unsigned int delay;
275 	int err;
276 
277 	if (p->prepared)
278 		return 0;
279 
280 	err = regulator_enable(p->supply);
281 	if (err < 0) {
282 		dev_err(panel->dev, "failed to enable supply: %d\n", err);
283 		return err;
284 	}
285 
286 	gpiod_set_value_cansleep(p->enable_gpio, 1);
287 
288 	delay = p->desc->delay.prepare;
289 	if (p->no_hpd)
290 		delay += p->desc->delay.hpd_absent_delay;
291 	if (delay)
292 		msleep(delay);
293 
294 	p->prepared = true;
295 
296 	return 0;
297 }
298 
299 static int panel_simple_enable(struct drm_panel *panel)
300 {
301 	struct panel_simple *p = to_panel_simple(panel);
302 
303 	if (p->enabled)
304 		return 0;
305 
306 	if (p->desc->delay.enable)
307 		msleep(p->desc->delay.enable);
308 
309 	if (p->backlight) {
310 		p->backlight->props.state &= ~BL_CORE_FBBLANK;
311 		p->backlight->props.power = FB_BLANK_UNBLANK;
312 		backlight_update_status(p->backlight);
313 	}
314 
315 	p->enabled = true;
316 
317 	return 0;
318 }
319 
320 static int panel_simple_get_modes(struct drm_panel *panel)
321 {
322 	struct panel_simple *p = to_panel_simple(panel);
323 	int num = 0;
324 
325 	/* probe EDID if a DDC bus is available */
326 	if (p->ddc) {
327 		struct edid *edid = drm_get_edid(panel->connector, p->ddc);
328 		drm_connector_update_edid_property(panel->connector, edid);
329 		if (edid) {
330 			num += drm_add_edid_modes(panel->connector, edid);
331 			kfree(edid);
332 		}
333 	}
334 
335 	/* add hard-coded panel modes */
336 	num += panel_simple_get_non_edid_modes(p);
337 
338 	return num;
339 }
340 
341 static int panel_simple_get_timings(struct drm_panel *panel,
342 				    unsigned int num_timings,
343 				    struct display_timing *timings)
344 {
345 	struct panel_simple *p = to_panel_simple(panel);
346 	unsigned int i;
347 
348 	if (p->desc->num_timings < num_timings)
349 		num_timings = p->desc->num_timings;
350 
351 	if (timings)
352 		for (i = 0; i < num_timings; i++)
353 			timings[i] = p->desc->timings[i];
354 
355 	return p->desc->num_timings;
356 }
357 
358 static const struct drm_panel_funcs panel_simple_funcs = {
359 	.disable = panel_simple_disable,
360 	.unprepare = panel_simple_unprepare,
361 	.prepare = panel_simple_prepare,
362 	.enable = panel_simple_enable,
363 	.get_modes = panel_simple_get_modes,
364 	.get_timings = panel_simple_get_timings,
365 };
366 
367 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
368 	(to_check->field.typ >= bounds->field.min && \
369 	 to_check->field.typ <= bounds->field.max)
370 static void panel_simple_parse_panel_timing_node(struct device *dev,
371 						 struct panel_simple *panel,
372 						 const struct display_timing *ot)
373 {
374 	const struct panel_desc *desc = panel->desc;
375 	struct videomode vm;
376 	unsigned int i;
377 
378 	if (WARN_ON(desc->num_modes)) {
379 		dev_err(dev, "Reject override mode: panel has a fixed mode\n");
380 		return;
381 	}
382 	if (WARN_ON(!desc->num_timings)) {
383 		dev_err(dev, "Reject override mode: no timings specified\n");
384 		return;
385 	}
386 
387 	for (i = 0; i < panel->desc->num_timings; i++) {
388 		const struct display_timing *dt = &panel->desc->timings[i];
389 
390 		if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
391 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
392 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
393 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
394 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
395 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
396 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
397 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
398 			continue;
399 
400 		if (ot->flags != dt->flags)
401 			continue;
402 
403 		videomode_from_timing(ot, &vm);
404 		drm_display_mode_from_videomode(&vm, &panel->override_mode);
405 		panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
406 					     DRM_MODE_TYPE_PREFERRED;
407 		break;
408 	}
409 
410 	if (WARN_ON(!panel->override_mode.type))
411 		dev_err(dev, "Reject override mode: No display_timing found\n");
412 }
413 
414 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
415 {
416 	struct device_node *backlight, *ddc;
417 	struct panel_simple *panel;
418 	struct display_timing dt;
419 	int err;
420 
421 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
422 	if (!panel)
423 		return -ENOMEM;
424 
425 	panel->enabled = false;
426 	panel->prepared = false;
427 	panel->desc = desc;
428 
429 	panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
430 
431 	panel->supply = devm_regulator_get(dev, "power");
432 	if (IS_ERR(panel->supply))
433 		return PTR_ERR(panel->supply);
434 
435 	panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
436 						     GPIOD_OUT_LOW);
437 	if (IS_ERR(panel->enable_gpio)) {
438 		err = PTR_ERR(panel->enable_gpio);
439 		if (err != -EPROBE_DEFER)
440 			dev_err(dev, "failed to request GPIO: %d\n", err);
441 		return err;
442 	}
443 
444 	backlight = of_parse_phandle(dev->of_node, "backlight", 0);
445 	if (backlight) {
446 		panel->backlight = of_find_backlight_by_node(backlight);
447 		of_node_put(backlight);
448 
449 		if (!panel->backlight)
450 			return -EPROBE_DEFER;
451 	}
452 
453 	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
454 	if (ddc) {
455 		panel->ddc = of_find_i2c_adapter_by_node(ddc);
456 		of_node_put(ddc);
457 
458 		if (!panel->ddc) {
459 			err = -EPROBE_DEFER;
460 			goto free_backlight;
461 		}
462 	}
463 
464 	if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
465 		panel_simple_parse_panel_timing_node(dev, panel, &dt);
466 
467 	drm_panel_init(&panel->base);
468 	panel->base.dev = dev;
469 	panel->base.funcs = &panel_simple_funcs;
470 
471 	err = drm_panel_add(&panel->base);
472 	if (err < 0)
473 		goto free_ddc;
474 
475 	dev_set_drvdata(dev, panel);
476 
477 	return 0;
478 
479 free_ddc:
480 	if (panel->ddc)
481 		put_device(&panel->ddc->dev);
482 free_backlight:
483 	if (panel->backlight)
484 		put_device(&panel->backlight->dev);
485 
486 	return err;
487 }
488 
489 static int panel_simple_remove(struct device *dev)
490 {
491 	struct panel_simple *panel = dev_get_drvdata(dev);
492 
493 	drm_panel_remove(&panel->base);
494 
495 	panel_simple_disable(&panel->base);
496 	panel_simple_unprepare(&panel->base);
497 
498 	if (panel->ddc)
499 		put_device(&panel->ddc->dev);
500 
501 	if (panel->backlight)
502 		put_device(&panel->backlight->dev);
503 
504 	return 0;
505 }
506 
507 static void panel_simple_shutdown(struct device *dev)
508 {
509 	struct panel_simple *panel = dev_get_drvdata(dev);
510 
511 	panel_simple_disable(&panel->base);
512 	panel_simple_unprepare(&panel->base);
513 }
514 
515 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
516 	.clock = 9000,
517 	.hdisplay = 480,
518 	.hsync_start = 480 + 2,
519 	.hsync_end = 480 + 2 + 41,
520 	.htotal = 480 + 2 + 41 + 2,
521 	.vdisplay = 272,
522 	.vsync_start = 272 + 2,
523 	.vsync_end = 272 + 2 + 10,
524 	.vtotal = 272 + 2 + 10 + 2,
525 	.vrefresh = 60,
526 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
527 };
528 
529 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
530 	.modes = &ampire_am_480272h3tmqw_t01h_mode,
531 	.num_modes = 1,
532 	.bpc = 8,
533 	.size = {
534 		.width = 105,
535 		.height = 67,
536 	},
537 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
538 };
539 
540 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
541 	.clock = 33333,
542 	.hdisplay = 800,
543 	.hsync_start = 800 + 0,
544 	.hsync_end = 800 + 0 + 255,
545 	.htotal = 800 + 0 + 255 + 0,
546 	.vdisplay = 480,
547 	.vsync_start = 480 + 2,
548 	.vsync_end = 480 + 2 + 45,
549 	.vtotal = 480 + 2 + 45 + 0,
550 	.vrefresh = 60,
551 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
552 };
553 
554 static const struct panel_desc ampire_am800480r3tmqwa1h = {
555 	.modes = &ampire_am800480r3tmqwa1h_mode,
556 	.num_modes = 1,
557 	.bpc = 6,
558 	.size = {
559 		.width = 152,
560 		.height = 91,
561 	},
562 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
563 };
564 
565 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
566 	.pixelclock = { 26400000, 33300000, 46800000 },
567 	.hactive = { 800, 800, 800 },
568 	.hfront_porch = { 16, 210, 354 },
569 	.hback_porch = { 45, 36, 6 },
570 	.hsync_len = { 1, 10, 40 },
571 	.vactive = { 480, 480, 480 },
572 	.vfront_porch = { 7, 22, 147 },
573 	.vback_porch = { 22, 13, 3 },
574 	.vsync_len = { 1, 10, 20 },
575 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
576 		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
577 };
578 
579 static const struct panel_desc armadeus_st0700_adapt = {
580 	.timings = &santek_st0700i5y_rbslw_f_timing,
581 	.num_timings = 1,
582 	.bpc = 6,
583 	.size = {
584 		.width = 154,
585 		.height = 86,
586 	},
587 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
588 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
589 };
590 
591 static const struct drm_display_mode auo_b101aw03_mode = {
592 	.clock = 51450,
593 	.hdisplay = 1024,
594 	.hsync_start = 1024 + 156,
595 	.hsync_end = 1024 + 156 + 8,
596 	.htotal = 1024 + 156 + 8 + 156,
597 	.vdisplay = 600,
598 	.vsync_start = 600 + 16,
599 	.vsync_end = 600 + 16 + 6,
600 	.vtotal = 600 + 16 + 6 + 16,
601 	.vrefresh = 60,
602 };
603 
604 static const struct panel_desc auo_b101aw03 = {
605 	.modes = &auo_b101aw03_mode,
606 	.num_modes = 1,
607 	.bpc = 6,
608 	.size = {
609 		.width = 223,
610 		.height = 125,
611 	},
612 };
613 
614 static const struct display_timing auo_b101ean01_timing = {
615 	.pixelclock = { 65300000, 72500000, 75000000 },
616 	.hactive = { 1280, 1280, 1280 },
617 	.hfront_porch = { 18, 119, 119 },
618 	.hback_porch = { 21, 21, 21 },
619 	.hsync_len = { 32, 32, 32 },
620 	.vactive = { 800, 800, 800 },
621 	.vfront_porch = { 4, 4, 4 },
622 	.vback_porch = { 8, 8, 8 },
623 	.vsync_len = { 18, 20, 20 },
624 };
625 
626 static const struct panel_desc auo_b101ean01 = {
627 	.timings = &auo_b101ean01_timing,
628 	.num_timings = 1,
629 	.bpc = 6,
630 	.size = {
631 		.width = 217,
632 		.height = 136,
633 	},
634 };
635 
636 static const struct drm_display_mode auo_b101xtn01_mode = {
637 	.clock = 72000,
638 	.hdisplay = 1366,
639 	.hsync_start = 1366 + 20,
640 	.hsync_end = 1366 + 20 + 70,
641 	.htotal = 1366 + 20 + 70,
642 	.vdisplay = 768,
643 	.vsync_start = 768 + 14,
644 	.vsync_end = 768 + 14 + 42,
645 	.vtotal = 768 + 14 + 42,
646 	.vrefresh = 60,
647 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
648 };
649 
650 static const struct panel_desc auo_b101xtn01 = {
651 	.modes = &auo_b101xtn01_mode,
652 	.num_modes = 1,
653 	.bpc = 6,
654 	.size = {
655 		.width = 223,
656 		.height = 125,
657 	},
658 };
659 
660 static const struct drm_display_mode auo_b116xw03_mode = {
661 	.clock = 70589,
662 	.hdisplay = 1366,
663 	.hsync_start = 1366 + 40,
664 	.hsync_end = 1366 + 40 + 40,
665 	.htotal = 1366 + 40 + 40 + 32,
666 	.vdisplay = 768,
667 	.vsync_start = 768 + 10,
668 	.vsync_end = 768 + 10 + 12,
669 	.vtotal = 768 + 10 + 12 + 6,
670 	.vrefresh = 60,
671 };
672 
673 static const struct panel_desc auo_b116xw03 = {
674 	.modes = &auo_b116xw03_mode,
675 	.num_modes = 1,
676 	.bpc = 6,
677 	.size = {
678 		.width = 256,
679 		.height = 144,
680 	},
681 };
682 
683 static const struct drm_display_mode auo_b133xtn01_mode = {
684 	.clock = 69500,
685 	.hdisplay = 1366,
686 	.hsync_start = 1366 + 48,
687 	.hsync_end = 1366 + 48 + 32,
688 	.htotal = 1366 + 48 + 32 + 20,
689 	.vdisplay = 768,
690 	.vsync_start = 768 + 3,
691 	.vsync_end = 768 + 3 + 6,
692 	.vtotal = 768 + 3 + 6 + 13,
693 	.vrefresh = 60,
694 };
695 
696 static const struct panel_desc auo_b133xtn01 = {
697 	.modes = &auo_b133xtn01_mode,
698 	.num_modes = 1,
699 	.bpc = 6,
700 	.size = {
701 		.width = 293,
702 		.height = 165,
703 	},
704 };
705 
706 static const struct drm_display_mode auo_b133htn01_mode = {
707 	.clock = 150660,
708 	.hdisplay = 1920,
709 	.hsync_start = 1920 + 172,
710 	.hsync_end = 1920 + 172 + 80,
711 	.htotal = 1920 + 172 + 80 + 60,
712 	.vdisplay = 1080,
713 	.vsync_start = 1080 + 25,
714 	.vsync_end = 1080 + 25 + 10,
715 	.vtotal = 1080 + 25 + 10 + 10,
716 	.vrefresh = 60,
717 };
718 
719 static const struct panel_desc auo_b133htn01 = {
720 	.modes = &auo_b133htn01_mode,
721 	.num_modes = 1,
722 	.bpc = 6,
723 	.size = {
724 		.width = 293,
725 		.height = 165,
726 	},
727 	.delay = {
728 		.prepare = 105,
729 		.enable = 20,
730 		.unprepare = 50,
731 	},
732 };
733 
734 static const struct display_timing auo_g070vvn01_timings = {
735 	.pixelclock = { 33300000, 34209000, 45000000 },
736 	.hactive = { 800, 800, 800 },
737 	.hfront_porch = { 20, 40, 200 },
738 	.hback_porch = { 87, 40, 1 },
739 	.hsync_len = { 1, 48, 87 },
740 	.vactive = { 480, 480, 480 },
741 	.vfront_porch = { 5, 13, 200 },
742 	.vback_porch = { 31, 31, 29 },
743 	.vsync_len = { 1, 1, 3 },
744 };
745 
746 static const struct panel_desc auo_g070vvn01 = {
747 	.timings = &auo_g070vvn01_timings,
748 	.num_timings = 1,
749 	.bpc = 8,
750 	.size = {
751 		.width = 152,
752 		.height = 91,
753 	},
754 	.delay = {
755 		.prepare = 200,
756 		.enable = 50,
757 		.disable = 50,
758 		.unprepare = 1000,
759 	},
760 };
761 
762 static const struct drm_display_mode auo_g101evn010_mode = {
763 	.clock = 68930,
764 	.hdisplay = 1280,
765 	.hsync_start = 1280 + 82,
766 	.hsync_end = 1280 + 82 + 2,
767 	.htotal = 1280 + 82 + 2 + 84,
768 	.vdisplay = 800,
769 	.vsync_start = 800 + 8,
770 	.vsync_end = 800 + 8 + 2,
771 	.vtotal = 800 + 8 + 2 + 6,
772 	.vrefresh = 60,
773 };
774 
775 static const struct panel_desc auo_g101evn010 = {
776 	.modes = &auo_g101evn010_mode,
777 	.num_modes = 1,
778 	.bpc = 6,
779 	.size = {
780 		.width = 216,
781 		.height = 135,
782 	},
783 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
784 };
785 
786 static const struct drm_display_mode auo_g104sn02_mode = {
787 	.clock = 40000,
788 	.hdisplay = 800,
789 	.hsync_start = 800 + 40,
790 	.hsync_end = 800 + 40 + 216,
791 	.htotal = 800 + 40 + 216 + 128,
792 	.vdisplay = 600,
793 	.vsync_start = 600 + 10,
794 	.vsync_end = 600 + 10 + 35,
795 	.vtotal = 600 + 10 + 35 + 2,
796 	.vrefresh = 60,
797 };
798 
799 static const struct panel_desc auo_g104sn02 = {
800 	.modes = &auo_g104sn02_mode,
801 	.num_modes = 1,
802 	.bpc = 8,
803 	.size = {
804 		.width = 211,
805 		.height = 158,
806 	},
807 };
808 
809 static const struct display_timing auo_g133han01_timings = {
810 	.pixelclock = { 134000000, 141200000, 149000000 },
811 	.hactive = { 1920, 1920, 1920 },
812 	.hfront_porch = { 39, 58, 77 },
813 	.hback_porch = { 59, 88, 117 },
814 	.hsync_len = { 28, 42, 56 },
815 	.vactive = { 1080, 1080, 1080 },
816 	.vfront_porch = { 3, 8, 11 },
817 	.vback_porch = { 5, 14, 19 },
818 	.vsync_len = { 4, 14, 19 },
819 };
820 
821 static const struct panel_desc auo_g133han01 = {
822 	.timings = &auo_g133han01_timings,
823 	.num_timings = 1,
824 	.bpc = 8,
825 	.size = {
826 		.width = 293,
827 		.height = 165,
828 	},
829 	.delay = {
830 		.prepare = 200,
831 		.enable = 50,
832 		.disable = 50,
833 		.unprepare = 1000,
834 	},
835 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
836 };
837 
838 static const struct display_timing auo_g185han01_timings = {
839 	.pixelclock = { 120000000, 144000000, 175000000 },
840 	.hactive = { 1920, 1920, 1920 },
841 	.hfront_porch = { 36, 120, 148 },
842 	.hback_porch = { 24, 88, 108 },
843 	.hsync_len = { 20, 48, 64 },
844 	.vactive = { 1080, 1080, 1080 },
845 	.vfront_porch = { 6, 10, 40 },
846 	.vback_porch = { 2, 5, 20 },
847 	.vsync_len = { 2, 5, 20 },
848 };
849 
850 static const struct panel_desc auo_g185han01 = {
851 	.timings = &auo_g185han01_timings,
852 	.num_timings = 1,
853 	.bpc = 8,
854 	.size = {
855 		.width = 409,
856 		.height = 230,
857 	},
858 	.delay = {
859 		.prepare = 50,
860 		.enable = 200,
861 		.disable = 110,
862 		.unprepare = 1000,
863 	},
864 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
865 };
866 
867 static const struct display_timing auo_p320hvn03_timings = {
868 	.pixelclock = { 106000000, 148500000, 164000000 },
869 	.hactive = { 1920, 1920, 1920 },
870 	.hfront_porch = { 25, 50, 130 },
871 	.hback_porch = { 25, 50, 130 },
872 	.hsync_len = { 20, 40, 105 },
873 	.vactive = { 1080, 1080, 1080 },
874 	.vfront_porch = { 8, 17, 150 },
875 	.vback_porch = { 8, 17, 150 },
876 	.vsync_len = { 4, 11, 100 },
877 };
878 
879 static const struct panel_desc auo_p320hvn03 = {
880 	.timings = &auo_p320hvn03_timings,
881 	.num_timings = 1,
882 	.bpc = 8,
883 	.size = {
884 		.width = 698,
885 		.height = 393,
886 	},
887 	.delay = {
888 		.prepare = 1,
889 		.enable = 450,
890 		.unprepare = 500,
891 	},
892 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
893 };
894 
895 static const struct drm_display_mode auo_t215hvn01_mode = {
896 	.clock = 148800,
897 	.hdisplay = 1920,
898 	.hsync_start = 1920 + 88,
899 	.hsync_end = 1920 + 88 + 44,
900 	.htotal = 1920 + 88 + 44 + 148,
901 	.vdisplay = 1080,
902 	.vsync_start = 1080 + 4,
903 	.vsync_end = 1080 + 4 + 5,
904 	.vtotal = 1080 + 4 + 5 + 36,
905 	.vrefresh = 60,
906 };
907 
908 static const struct panel_desc auo_t215hvn01 = {
909 	.modes = &auo_t215hvn01_mode,
910 	.num_modes = 1,
911 	.bpc = 8,
912 	.size = {
913 		.width = 430,
914 		.height = 270,
915 	},
916 	.delay = {
917 		.disable = 5,
918 		.unprepare = 1000,
919 	}
920 };
921 
922 static const struct drm_display_mode avic_tm070ddh03_mode = {
923 	.clock = 51200,
924 	.hdisplay = 1024,
925 	.hsync_start = 1024 + 160,
926 	.hsync_end = 1024 + 160 + 4,
927 	.htotal = 1024 + 160 + 4 + 156,
928 	.vdisplay = 600,
929 	.vsync_start = 600 + 17,
930 	.vsync_end = 600 + 17 + 1,
931 	.vtotal = 600 + 17 + 1 + 17,
932 	.vrefresh = 60,
933 };
934 
935 static const struct panel_desc avic_tm070ddh03 = {
936 	.modes = &avic_tm070ddh03_mode,
937 	.num_modes = 1,
938 	.bpc = 8,
939 	.size = {
940 		.width = 154,
941 		.height = 90,
942 	},
943 	.delay = {
944 		.prepare = 20,
945 		.enable = 200,
946 		.disable = 200,
947 	},
948 };
949 
950 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
951 	.clock = 30000,
952 	.hdisplay = 800,
953 	.hsync_start = 800 + 40,
954 	.hsync_end = 800 + 40 + 48,
955 	.htotal = 800 + 40 + 48 + 40,
956 	.vdisplay = 480,
957 	.vsync_start = 480 + 13,
958 	.vsync_end = 480 + 13 + 3,
959 	.vtotal = 480 + 13 + 3 + 29,
960 };
961 
962 static const struct panel_desc bananapi_s070wv20_ct16 = {
963 	.modes = &bananapi_s070wv20_ct16_mode,
964 	.num_modes = 1,
965 	.bpc = 6,
966 	.size = {
967 		.width = 154,
968 		.height = 86,
969 	},
970 };
971 
972 static const struct drm_display_mode boe_hv070wsa_mode = {
973 	.clock = 42105,
974 	.hdisplay = 1024,
975 	.hsync_start = 1024 + 30,
976 	.hsync_end = 1024 + 30 + 30,
977 	.htotal = 1024 + 30 + 30 + 30,
978 	.vdisplay = 600,
979 	.vsync_start = 600 + 10,
980 	.vsync_end = 600 + 10 + 10,
981 	.vtotal = 600 + 10 + 10 + 10,
982 	.vrefresh = 60,
983 };
984 
985 static const struct panel_desc boe_hv070wsa = {
986 	.modes = &boe_hv070wsa_mode,
987 	.num_modes = 1,
988 	.size = {
989 		.width = 154,
990 		.height = 90,
991 	},
992 };
993 
994 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
995 	{
996 		.clock = 71900,
997 		.hdisplay = 1280,
998 		.hsync_start = 1280 + 48,
999 		.hsync_end = 1280 + 48 + 32,
1000 		.htotal = 1280 + 48 + 32 + 80,
1001 		.vdisplay = 800,
1002 		.vsync_start = 800 + 3,
1003 		.vsync_end = 800 + 3 + 5,
1004 		.vtotal = 800 + 3 + 5 + 24,
1005 		.vrefresh = 60,
1006 	},
1007 	{
1008 		.clock = 57500,
1009 		.hdisplay = 1280,
1010 		.hsync_start = 1280 + 48,
1011 		.hsync_end = 1280 + 48 + 32,
1012 		.htotal = 1280 + 48 + 32 + 80,
1013 		.vdisplay = 800,
1014 		.vsync_start = 800 + 3,
1015 		.vsync_end = 800 + 3 + 5,
1016 		.vtotal = 800 + 3 + 5 + 24,
1017 		.vrefresh = 48,
1018 	},
1019 };
1020 
1021 static const struct panel_desc boe_nv101wxmn51 = {
1022 	.modes = boe_nv101wxmn51_modes,
1023 	.num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1024 	.bpc = 8,
1025 	.size = {
1026 		.width = 217,
1027 		.height = 136,
1028 	},
1029 	.delay = {
1030 		.prepare = 210,
1031 		.enable = 50,
1032 		.unprepare = 160,
1033 	},
1034 };
1035 
1036 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1037 	.clock = 9000,
1038 	.hdisplay = 480,
1039 	.hsync_start = 480 + 5,
1040 	.hsync_end = 480 + 5 + 5,
1041 	.htotal = 480 + 5 + 5 + 40,
1042 	.vdisplay = 272,
1043 	.vsync_start = 272 + 8,
1044 	.vsync_end = 272 + 8 + 8,
1045 	.vtotal = 272 + 8 + 8 + 8,
1046 	.vrefresh = 60,
1047 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1048 };
1049 
1050 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1051 	.modes = &cdtech_s043wq26h_ct7_mode,
1052 	.num_modes = 1,
1053 	.bpc = 8,
1054 	.size = {
1055 		.width = 95,
1056 		.height = 54,
1057 	},
1058 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1059 };
1060 
1061 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1062 	.clock = 35000,
1063 	.hdisplay = 800,
1064 	.hsync_start = 800 + 40,
1065 	.hsync_end = 800 + 40 + 40,
1066 	.htotal = 800 + 40 + 40 + 48,
1067 	.vdisplay = 480,
1068 	.vsync_start = 480 + 29,
1069 	.vsync_end = 480 + 29 + 13,
1070 	.vtotal = 480 + 29 + 13 + 3,
1071 	.vrefresh = 60,
1072 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1073 };
1074 
1075 static const struct panel_desc cdtech_s070wv95_ct16 = {
1076 	.modes = &cdtech_s070wv95_ct16_mode,
1077 	.num_modes = 1,
1078 	.bpc = 8,
1079 	.size = {
1080 		.width = 154,
1081 		.height = 85,
1082 	},
1083 };
1084 
1085 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1086 	.clock = 66770,
1087 	.hdisplay = 800,
1088 	.hsync_start = 800 + 49,
1089 	.hsync_end = 800 + 49 + 33,
1090 	.htotal = 800 + 49 + 33 + 17,
1091 	.vdisplay = 1280,
1092 	.vsync_start = 1280 + 1,
1093 	.vsync_end = 1280 + 1 + 7,
1094 	.vtotal = 1280 + 1 + 7 + 15,
1095 	.vrefresh = 60,
1096 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1097 };
1098 
1099 static const struct panel_desc chunghwa_claa070wp03xg = {
1100 	.modes = &chunghwa_claa070wp03xg_mode,
1101 	.num_modes = 1,
1102 	.bpc = 6,
1103 	.size = {
1104 		.width = 94,
1105 		.height = 150,
1106 	},
1107 };
1108 
1109 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1110 	.clock = 72070,
1111 	.hdisplay = 1366,
1112 	.hsync_start = 1366 + 58,
1113 	.hsync_end = 1366 + 58 + 58,
1114 	.htotal = 1366 + 58 + 58 + 58,
1115 	.vdisplay = 768,
1116 	.vsync_start = 768 + 4,
1117 	.vsync_end = 768 + 4 + 4,
1118 	.vtotal = 768 + 4 + 4 + 4,
1119 	.vrefresh = 60,
1120 };
1121 
1122 static const struct panel_desc chunghwa_claa101wa01a = {
1123 	.modes = &chunghwa_claa101wa01a_mode,
1124 	.num_modes = 1,
1125 	.bpc = 6,
1126 	.size = {
1127 		.width = 220,
1128 		.height = 120,
1129 	},
1130 };
1131 
1132 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1133 	.clock = 69300,
1134 	.hdisplay = 1366,
1135 	.hsync_start = 1366 + 48,
1136 	.hsync_end = 1366 + 48 + 32,
1137 	.htotal = 1366 + 48 + 32 + 20,
1138 	.vdisplay = 768,
1139 	.vsync_start = 768 + 16,
1140 	.vsync_end = 768 + 16 + 8,
1141 	.vtotal = 768 + 16 + 8 + 16,
1142 	.vrefresh = 60,
1143 };
1144 
1145 static const struct panel_desc chunghwa_claa101wb01 = {
1146 	.modes = &chunghwa_claa101wb01_mode,
1147 	.num_modes = 1,
1148 	.bpc = 6,
1149 	.size = {
1150 		.width = 223,
1151 		.height = 125,
1152 	},
1153 };
1154 
1155 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1156 	.clock = 33260,
1157 	.hdisplay = 800,
1158 	.hsync_start = 800 + 40,
1159 	.hsync_end = 800 + 40 + 128,
1160 	.htotal = 800 + 40 + 128 + 88,
1161 	.vdisplay = 480,
1162 	.vsync_start = 480 + 10,
1163 	.vsync_end = 480 + 10 + 2,
1164 	.vtotal = 480 + 10 + 2 + 33,
1165 	.vrefresh = 60,
1166 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1167 };
1168 
1169 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1170 	.modes = &dataimage_scf0700c48ggu18_mode,
1171 	.num_modes = 1,
1172 	.bpc = 8,
1173 	.size = {
1174 		.width = 152,
1175 		.height = 91,
1176 	},
1177 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1178 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1179 };
1180 
1181 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1182 	.pixelclock = { 45000000, 51200000, 57000000 },
1183 	.hactive = { 1024, 1024, 1024 },
1184 	.hfront_porch = { 100, 106, 113 },
1185 	.hback_porch = { 100, 106, 113 },
1186 	.hsync_len = { 100, 108, 114 },
1187 	.vactive = { 600, 600, 600 },
1188 	.vfront_porch = { 8, 11, 15 },
1189 	.vback_porch = { 8, 11, 15 },
1190 	.vsync_len = { 9, 13, 15 },
1191 	.flags = DISPLAY_FLAGS_DE_HIGH,
1192 };
1193 
1194 static const struct panel_desc dlc_dlc0700yzg_1 = {
1195 	.timings = &dlc_dlc0700yzg_1_timing,
1196 	.num_timings = 1,
1197 	.bpc = 6,
1198 	.size = {
1199 		.width = 154,
1200 		.height = 86,
1201 	},
1202 	.delay = {
1203 		.prepare = 30,
1204 		.enable = 200,
1205 		.disable = 200,
1206 	},
1207 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1208 };
1209 
1210 static const struct display_timing dlc_dlc1010gig_timing = {
1211 	.pixelclock = { 68900000, 71100000, 73400000 },
1212 	.hactive = { 1280, 1280, 1280 },
1213 	.hfront_porch = { 43, 53, 63 },
1214 	.hback_porch = { 43, 53, 63 },
1215 	.hsync_len = { 44, 54, 64 },
1216 	.vactive = { 800, 800, 800 },
1217 	.vfront_porch = { 5, 8, 11 },
1218 	.vback_porch = { 5, 8, 11 },
1219 	.vsync_len = { 5, 7, 11 },
1220 	.flags = DISPLAY_FLAGS_DE_HIGH,
1221 };
1222 
1223 static const struct panel_desc dlc_dlc1010gig = {
1224 	.timings = &dlc_dlc1010gig_timing,
1225 	.num_timings = 1,
1226 	.bpc = 8,
1227 	.size = {
1228 		.width = 216,
1229 		.height = 135,
1230 	},
1231 	.delay = {
1232 		.prepare = 60,
1233 		.enable = 150,
1234 		.disable = 100,
1235 		.unprepare = 60,
1236 	},
1237 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 };
1239 
1240 static const struct drm_display_mode edt_et035012dm6_mode = {
1241 	.clock = 6500,
1242 	.hdisplay = 320,
1243 	.hsync_start = 320 + 20,
1244 	.hsync_end = 320 + 20 + 30,
1245 	.htotal = 320 + 20 + 68,
1246 	.vdisplay = 240,
1247 	.vsync_start = 240 + 4,
1248 	.vsync_end = 240 + 4 + 4,
1249 	.vtotal = 240 + 4 + 4 + 14,
1250 	.vrefresh = 60,
1251 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1252 };
1253 
1254 static const struct panel_desc edt_et035012dm6 = {
1255 	.modes = &edt_et035012dm6_mode,
1256 	.num_modes = 1,
1257 	.bpc = 8,
1258 	.size = {
1259 		.width = 70,
1260 		.height = 52,
1261 	},
1262 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1263 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1264 };
1265 
1266 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1267 	.clock = 9000,
1268 	.hdisplay = 480,
1269 	.hsync_start = 480 + 2,
1270 	.hsync_end = 480 + 2 + 41,
1271 	.htotal = 480 + 2 + 41 + 2,
1272 	.vdisplay = 272,
1273 	.vsync_start = 272 + 2,
1274 	.vsync_end = 272 + 2 + 10,
1275 	.vtotal = 272 + 2 + 10 + 2,
1276 	.vrefresh = 60,
1277 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1278 };
1279 
1280 static const struct panel_desc edt_etm0430g0dh6 = {
1281 	.modes = &edt_etm0430g0dh6_mode,
1282 	.num_modes = 1,
1283 	.bpc = 6,
1284 	.size = {
1285 		.width = 95,
1286 		.height = 54,
1287 	},
1288 };
1289 
1290 static const struct drm_display_mode edt_et057090dhu_mode = {
1291 	.clock = 25175,
1292 	.hdisplay = 640,
1293 	.hsync_start = 640 + 16,
1294 	.hsync_end = 640 + 16 + 30,
1295 	.htotal = 640 + 16 + 30 + 114,
1296 	.vdisplay = 480,
1297 	.vsync_start = 480 + 10,
1298 	.vsync_end = 480 + 10 + 3,
1299 	.vtotal = 480 + 10 + 3 + 32,
1300 	.vrefresh = 60,
1301 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1302 };
1303 
1304 static const struct panel_desc edt_et057090dhu = {
1305 	.modes = &edt_et057090dhu_mode,
1306 	.num_modes = 1,
1307 	.bpc = 6,
1308 	.size = {
1309 		.width = 115,
1310 		.height = 86,
1311 	},
1312 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1313 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1314 };
1315 
1316 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1317 	.clock = 33260,
1318 	.hdisplay = 800,
1319 	.hsync_start = 800 + 40,
1320 	.hsync_end = 800 + 40 + 128,
1321 	.htotal = 800 + 40 + 128 + 88,
1322 	.vdisplay = 480,
1323 	.vsync_start = 480 + 10,
1324 	.vsync_end = 480 + 10 + 2,
1325 	.vtotal = 480 + 10 + 2 + 33,
1326 	.vrefresh = 60,
1327 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1328 };
1329 
1330 static const struct panel_desc edt_etm0700g0dh6 = {
1331 	.modes = &edt_etm0700g0dh6_mode,
1332 	.num_modes = 1,
1333 	.bpc = 6,
1334 	.size = {
1335 		.width = 152,
1336 		.height = 91,
1337 	},
1338 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1339 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1340 };
1341 
1342 static const struct panel_desc edt_etm0700g0bdh6 = {
1343 	.modes = &edt_etm0700g0dh6_mode,
1344 	.num_modes = 1,
1345 	.bpc = 6,
1346 	.size = {
1347 		.width = 152,
1348 		.height = 91,
1349 	},
1350 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1351 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1352 };
1353 
1354 static const struct display_timing evervision_vgg804821_timing = {
1355 	.pixelclock = { 27600000, 33300000, 50000000 },
1356 	.hactive = { 800, 800, 800 },
1357 	.hfront_porch = { 40, 66, 70 },
1358 	.hback_porch = { 40, 67, 70 },
1359 	.hsync_len = { 40, 67, 70 },
1360 	.vactive = { 480, 480, 480 },
1361 	.vfront_porch = { 6, 10, 10 },
1362 	.vback_porch = { 7, 11, 11 },
1363 	.vsync_len = { 7, 11, 11 },
1364 	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1365 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1366 		 DISPLAY_FLAGS_SYNC_NEGEDGE,
1367 };
1368 
1369 static const struct panel_desc evervision_vgg804821 = {
1370 	.timings = &evervision_vgg804821_timing,
1371 	.num_timings = 1,
1372 	.bpc = 8,
1373 	.size = {
1374 		.width = 108,
1375 		.height = 64,
1376 	},
1377 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1378 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1379 };
1380 
1381 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1382 	.clock = 32260,
1383 	.hdisplay = 800,
1384 	.hsync_start = 800 + 168,
1385 	.hsync_end = 800 + 168 + 64,
1386 	.htotal = 800 + 168 + 64 + 88,
1387 	.vdisplay = 480,
1388 	.vsync_start = 480 + 37,
1389 	.vsync_end = 480 + 37 + 2,
1390 	.vtotal = 480 + 37 + 2 + 8,
1391 	.vrefresh = 60,
1392 };
1393 
1394 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1395 	.modes = &foxlink_fl500wvr00_a0t_mode,
1396 	.num_modes = 1,
1397 	.bpc = 8,
1398 	.size = {
1399 		.width = 108,
1400 		.height = 65,
1401 	},
1402 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1403 };
1404 
1405 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1406 	.clock		= 67185,
1407 	.hdisplay	= 800,
1408 	.hsync_start	= 800 + 20,
1409 	.hsync_end	= 800 + 20 + 24,
1410 	.htotal		= 800 + 20 + 24 + 20,
1411 	.vdisplay	= 1280,
1412 	.vsync_start	= 1280 + 4,
1413 	.vsync_end	= 1280 + 4 + 8,
1414 	.vtotal		= 1280 + 4 + 8 + 4,
1415 	.vrefresh	= 60,
1416 	.flags		= DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1417 };
1418 
1419 static const struct panel_desc friendlyarm_hd702e = {
1420 	.modes = &friendlyarm_hd702e_mode,
1421 	.num_modes = 1,
1422 	.size = {
1423 		.width	= 94,
1424 		.height	= 151,
1425 	},
1426 };
1427 
1428 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1429 	.clock = 9000,
1430 	.hdisplay = 480,
1431 	.hsync_start = 480 + 5,
1432 	.hsync_end = 480 + 5 + 1,
1433 	.htotal = 480 + 5 + 1 + 40,
1434 	.vdisplay = 272,
1435 	.vsync_start = 272 + 8,
1436 	.vsync_end = 272 + 8 + 1,
1437 	.vtotal = 272 + 8 + 1 + 8,
1438 	.vrefresh = 60,
1439 };
1440 
1441 static const struct panel_desc giantplus_gpg482739qs5 = {
1442 	.modes = &giantplus_gpg482739qs5_mode,
1443 	.num_modes = 1,
1444 	.bpc = 8,
1445 	.size = {
1446 		.width = 95,
1447 		.height = 54,
1448 	},
1449 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1450 };
1451 
1452 static const struct display_timing giantplus_gpm940b0_timing = {
1453 	.pixelclock = { 13500000, 27000000, 27500000 },
1454 	.hactive = { 320, 320, 320 },
1455 	.hfront_porch = { 14, 686, 718 },
1456 	.hback_porch = { 50, 70, 255 },
1457 	.hsync_len = { 1, 1, 1 },
1458 	.vactive = { 240, 240, 240 },
1459 	.vfront_porch = { 1, 1, 179 },
1460 	.vback_porch = { 1, 21, 31 },
1461 	.vsync_len = { 1, 1, 6 },
1462 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1463 };
1464 
1465 static const struct panel_desc giantplus_gpm940b0 = {
1466 	.timings = &giantplus_gpm940b0_timing,
1467 	.num_timings = 1,
1468 	.bpc = 8,
1469 	.size = {
1470 		.width = 60,
1471 		.height = 45,
1472 	},
1473 	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1474 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1475 };
1476 
1477 static const struct display_timing hannstar_hsd070pww1_timing = {
1478 	.pixelclock = { 64300000, 71100000, 82000000 },
1479 	.hactive = { 1280, 1280, 1280 },
1480 	.hfront_porch = { 1, 1, 10 },
1481 	.hback_porch = { 1, 1, 10 },
1482 	/*
1483 	 * According to the data sheet, the minimum horizontal blanking interval
1484 	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1485 	 * minimum working horizontal blanking interval to be 60 clocks.
1486 	 */
1487 	.hsync_len = { 58, 158, 661 },
1488 	.vactive = { 800, 800, 800 },
1489 	.vfront_porch = { 1, 1, 10 },
1490 	.vback_porch = { 1, 1, 10 },
1491 	.vsync_len = { 1, 21, 203 },
1492 	.flags = DISPLAY_FLAGS_DE_HIGH,
1493 };
1494 
1495 static const struct panel_desc hannstar_hsd070pww1 = {
1496 	.timings = &hannstar_hsd070pww1_timing,
1497 	.num_timings = 1,
1498 	.bpc = 6,
1499 	.size = {
1500 		.width = 151,
1501 		.height = 94,
1502 	},
1503 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1504 };
1505 
1506 static const struct display_timing hannstar_hsd100pxn1_timing = {
1507 	.pixelclock = { 55000000, 65000000, 75000000 },
1508 	.hactive = { 1024, 1024, 1024 },
1509 	.hfront_porch = { 40, 40, 40 },
1510 	.hback_porch = { 220, 220, 220 },
1511 	.hsync_len = { 20, 60, 100 },
1512 	.vactive = { 768, 768, 768 },
1513 	.vfront_porch = { 7, 7, 7 },
1514 	.vback_porch = { 21, 21, 21 },
1515 	.vsync_len = { 10, 10, 10 },
1516 	.flags = DISPLAY_FLAGS_DE_HIGH,
1517 };
1518 
1519 static const struct panel_desc hannstar_hsd100pxn1 = {
1520 	.timings = &hannstar_hsd100pxn1_timing,
1521 	.num_timings = 1,
1522 	.bpc = 6,
1523 	.size = {
1524 		.width = 203,
1525 		.height = 152,
1526 	},
1527 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1528 };
1529 
1530 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1531 	.clock = 33333,
1532 	.hdisplay = 800,
1533 	.hsync_start = 800 + 85,
1534 	.hsync_end = 800 + 85 + 86,
1535 	.htotal = 800 + 85 + 86 + 85,
1536 	.vdisplay = 480,
1537 	.vsync_start = 480 + 16,
1538 	.vsync_end = 480 + 16 + 13,
1539 	.vtotal = 480 + 16 + 13 + 16,
1540 	.vrefresh = 60,
1541 };
1542 
1543 static const struct panel_desc hitachi_tx23d38vm0caa = {
1544 	.modes = &hitachi_tx23d38vm0caa_mode,
1545 	.num_modes = 1,
1546 	.bpc = 6,
1547 	.size = {
1548 		.width = 195,
1549 		.height = 117,
1550 	},
1551 	.delay = {
1552 		.enable = 160,
1553 		.disable = 160,
1554 	},
1555 };
1556 
1557 static const struct drm_display_mode innolux_at043tn24_mode = {
1558 	.clock = 9000,
1559 	.hdisplay = 480,
1560 	.hsync_start = 480 + 2,
1561 	.hsync_end = 480 + 2 + 41,
1562 	.htotal = 480 + 2 + 41 + 2,
1563 	.vdisplay = 272,
1564 	.vsync_start = 272 + 2,
1565 	.vsync_end = 272 + 2 + 10,
1566 	.vtotal = 272 + 2 + 10 + 2,
1567 	.vrefresh = 60,
1568 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1569 };
1570 
1571 static const struct panel_desc innolux_at043tn24 = {
1572 	.modes = &innolux_at043tn24_mode,
1573 	.num_modes = 1,
1574 	.bpc = 8,
1575 	.size = {
1576 		.width = 95,
1577 		.height = 54,
1578 	},
1579 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1580 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1581 };
1582 
1583 static const struct drm_display_mode innolux_at070tn92_mode = {
1584 	.clock = 33333,
1585 	.hdisplay = 800,
1586 	.hsync_start = 800 + 210,
1587 	.hsync_end = 800 + 210 + 20,
1588 	.htotal = 800 + 210 + 20 + 46,
1589 	.vdisplay = 480,
1590 	.vsync_start = 480 + 22,
1591 	.vsync_end = 480 + 22 + 10,
1592 	.vtotal = 480 + 22 + 23 + 10,
1593 	.vrefresh = 60,
1594 };
1595 
1596 static const struct panel_desc innolux_at070tn92 = {
1597 	.modes = &innolux_at070tn92_mode,
1598 	.num_modes = 1,
1599 	.size = {
1600 		.width = 154,
1601 		.height = 86,
1602 	},
1603 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1604 };
1605 
1606 static const struct display_timing innolux_g070y2_l01_timing = {
1607 	.pixelclock = { 28000000, 29500000, 32000000 },
1608 	.hactive = { 800, 800, 800 },
1609 	.hfront_porch = { 61, 91, 141 },
1610 	.hback_porch = { 60, 90, 140 },
1611 	.hsync_len = { 12, 12, 12 },
1612 	.vactive = { 480, 480, 480 },
1613 	.vfront_porch = { 4, 9, 30 },
1614 	.vback_porch = { 4, 8, 28 },
1615 	.vsync_len = { 2, 2, 2 },
1616 	.flags = DISPLAY_FLAGS_DE_HIGH,
1617 };
1618 
1619 static const struct panel_desc innolux_g070y2_l01 = {
1620 	.timings = &innolux_g070y2_l01_timing,
1621 	.num_timings = 1,
1622 	.bpc = 6,
1623 	.size = {
1624 		.width = 152,
1625 		.height = 91,
1626 	},
1627 	.delay = {
1628 		.prepare = 10,
1629 		.enable = 100,
1630 		.disable = 100,
1631 		.unprepare = 800,
1632 	},
1633 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1634 };
1635 
1636 static const struct display_timing innolux_g101ice_l01_timing = {
1637 	.pixelclock = { 60400000, 71100000, 74700000 },
1638 	.hactive = { 1280, 1280, 1280 },
1639 	.hfront_porch = { 41, 80, 100 },
1640 	.hback_porch = { 40, 79, 99 },
1641 	.hsync_len = { 1, 1, 1 },
1642 	.vactive = { 800, 800, 800 },
1643 	.vfront_porch = { 5, 11, 14 },
1644 	.vback_porch = { 4, 11, 14 },
1645 	.vsync_len = { 1, 1, 1 },
1646 	.flags = DISPLAY_FLAGS_DE_HIGH,
1647 };
1648 
1649 static const struct panel_desc innolux_g101ice_l01 = {
1650 	.timings = &innolux_g101ice_l01_timing,
1651 	.num_timings = 1,
1652 	.bpc = 8,
1653 	.size = {
1654 		.width = 217,
1655 		.height = 135,
1656 	},
1657 	.delay = {
1658 		.enable = 200,
1659 		.disable = 200,
1660 	},
1661 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1662 };
1663 
1664 static const struct display_timing innolux_g121i1_l01_timing = {
1665 	.pixelclock = { 67450000, 71000000, 74550000 },
1666 	.hactive = { 1280, 1280, 1280 },
1667 	.hfront_porch = { 40, 80, 160 },
1668 	.hback_porch = { 39, 79, 159 },
1669 	.hsync_len = { 1, 1, 1 },
1670 	.vactive = { 800, 800, 800 },
1671 	.vfront_porch = { 5, 11, 100 },
1672 	.vback_porch = { 4, 11, 99 },
1673 	.vsync_len = { 1, 1, 1 },
1674 };
1675 
1676 static const struct panel_desc innolux_g121i1_l01 = {
1677 	.timings = &innolux_g121i1_l01_timing,
1678 	.num_timings = 1,
1679 	.bpc = 6,
1680 	.size = {
1681 		.width = 261,
1682 		.height = 163,
1683 	},
1684 	.delay = {
1685 		.enable = 200,
1686 		.disable = 20,
1687 	},
1688 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1689 };
1690 
1691 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1692 	.clock = 65000,
1693 	.hdisplay = 1024,
1694 	.hsync_start = 1024 + 0,
1695 	.hsync_end = 1024 + 1,
1696 	.htotal = 1024 + 0 + 1 + 320,
1697 	.vdisplay = 768,
1698 	.vsync_start = 768 + 38,
1699 	.vsync_end = 768 + 38 + 1,
1700 	.vtotal = 768 + 38 + 1 + 0,
1701 	.vrefresh = 60,
1702 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1703 };
1704 
1705 static const struct panel_desc innolux_g121x1_l03 = {
1706 	.modes = &innolux_g121x1_l03_mode,
1707 	.num_modes = 1,
1708 	.bpc = 6,
1709 	.size = {
1710 		.width = 246,
1711 		.height = 185,
1712 	},
1713 	.delay = {
1714 		.enable = 200,
1715 		.unprepare = 200,
1716 		.disable = 400,
1717 	},
1718 };
1719 
1720 /*
1721  * Datasheet specifies that at 60 Hz refresh rate:
1722  * - total horizontal time: { 1506, 1592, 1716 }
1723  * - total vertical time: { 788, 800, 868 }
1724  *
1725  * ...but doesn't go into exactly how that should be split into a front
1726  * porch, back porch, or sync length.  For now we'll leave a single setting
1727  * here which allows a bit of tweaking of the pixel clock at the expense of
1728  * refresh rate.
1729  */
1730 static const struct display_timing innolux_n116bge_timing = {
1731 	.pixelclock = { 72600000, 76420000, 80240000 },
1732 	.hactive = { 1366, 1366, 1366 },
1733 	.hfront_porch = { 136, 136, 136 },
1734 	.hback_porch = { 60, 60, 60 },
1735 	.hsync_len = { 30, 30, 30 },
1736 	.vactive = { 768, 768, 768 },
1737 	.vfront_porch = { 8, 8, 8 },
1738 	.vback_porch = { 12, 12, 12 },
1739 	.vsync_len = { 12, 12, 12 },
1740 	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1741 };
1742 
1743 static const struct panel_desc innolux_n116bge = {
1744 	.timings = &innolux_n116bge_timing,
1745 	.num_timings = 1,
1746 	.bpc = 6,
1747 	.size = {
1748 		.width = 256,
1749 		.height = 144,
1750 	},
1751 };
1752 
1753 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1754 	.clock = 69300,
1755 	.hdisplay = 1366,
1756 	.hsync_start = 1366 + 16,
1757 	.hsync_end = 1366 + 16 + 34,
1758 	.htotal = 1366 + 16 + 34 + 50,
1759 	.vdisplay = 768,
1760 	.vsync_start = 768 + 2,
1761 	.vsync_end = 768 + 2 + 6,
1762 	.vtotal = 768 + 2 + 6 + 12,
1763 	.vrefresh = 60,
1764 };
1765 
1766 static const struct panel_desc innolux_n156bge_l21 = {
1767 	.modes = &innolux_n156bge_l21_mode,
1768 	.num_modes = 1,
1769 	.bpc = 6,
1770 	.size = {
1771 		.width = 344,
1772 		.height = 193,
1773 	},
1774 };
1775 
1776 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1777 	.clock = 206016,
1778 	.hdisplay = 2160,
1779 	.hsync_start = 2160 + 48,
1780 	.hsync_end = 2160 + 48 + 32,
1781 	.htotal = 2160 + 48 + 32 + 80,
1782 	.vdisplay = 1440,
1783 	.vsync_start = 1440 + 3,
1784 	.vsync_end = 1440 + 3 + 10,
1785 	.vtotal = 1440 + 3 + 10 + 27,
1786 	.vrefresh = 60,
1787 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1788 };
1789 
1790 static const struct panel_desc innolux_p120zdg_bf1 = {
1791 	.modes = &innolux_p120zdg_bf1_mode,
1792 	.num_modes = 1,
1793 	.bpc = 8,
1794 	.size = {
1795 		.width = 254,
1796 		.height = 169,
1797 	},
1798 	.delay = {
1799 		.hpd_absent_delay = 200,
1800 		.unprepare = 500,
1801 	},
1802 };
1803 
1804 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1805 	.clock = 51501,
1806 	.hdisplay = 1024,
1807 	.hsync_start = 1024 + 128,
1808 	.hsync_end = 1024 + 128 + 64,
1809 	.htotal = 1024 + 128 + 64 + 128,
1810 	.vdisplay = 600,
1811 	.vsync_start = 600 + 16,
1812 	.vsync_end = 600 + 16 + 4,
1813 	.vtotal = 600 + 16 + 4 + 16,
1814 	.vrefresh = 60,
1815 };
1816 
1817 static const struct panel_desc innolux_zj070na_01p = {
1818 	.modes = &innolux_zj070na_01p_mode,
1819 	.num_modes = 1,
1820 	.bpc = 6,
1821 	.size = {
1822 		.width = 154,
1823 		.height = 90,
1824 	},
1825 };
1826 
1827 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1828 	.pixelclock = { 5580000, 5850000, 6200000 },
1829 	.hactive = { 320, 320, 320 },
1830 	.hfront_porch = { 30, 30, 30 },
1831 	.hback_porch = { 30, 30, 30 },
1832 	.hsync_len = { 1, 5, 17 },
1833 	.vactive = { 240, 240, 240 },
1834 	.vfront_porch = { 6, 6, 6 },
1835 	.vback_porch = { 5, 5, 5 },
1836 	.vsync_len = { 1, 2, 11 },
1837 	.flags = DISPLAY_FLAGS_DE_HIGH,
1838 };
1839 
1840 static const struct panel_desc koe_tx14d24vm1bpa = {
1841 	.timings = &koe_tx14d24vm1bpa_timing,
1842 	.num_timings = 1,
1843 	.bpc = 6,
1844 	.size = {
1845 		.width = 115,
1846 		.height = 86,
1847 	},
1848 };
1849 
1850 static const struct display_timing koe_tx31d200vm0baa_timing = {
1851 	.pixelclock = { 39600000, 43200000, 48000000 },
1852 	.hactive = { 1280, 1280, 1280 },
1853 	.hfront_porch = { 16, 36, 56 },
1854 	.hback_porch = { 16, 36, 56 },
1855 	.hsync_len = { 8, 8, 8 },
1856 	.vactive = { 480, 480, 480 },
1857 	.vfront_porch = { 6, 21, 33 },
1858 	.vback_porch = { 6, 21, 33 },
1859 	.vsync_len = { 8, 8, 8 },
1860 	.flags = DISPLAY_FLAGS_DE_HIGH,
1861 };
1862 
1863 static const struct panel_desc koe_tx31d200vm0baa = {
1864 	.timings = &koe_tx31d200vm0baa_timing,
1865 	.num_timings = 1,
1866 	.bpc = 6,
1867 	.size = {
1868 		.width = 292,
1869 		.height = 109,
1870 	},
1871 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1872 };
1873 
1874 static const struct display_timing kyo_tcg121xglp_timing = {
1875 	.pixelclock = { 52000000, 65000000, 71000000 },
1876 	.hactive = { 1024, 1024, 1024 },
1877 	.hfront_porch = { 2, 2, 2 },
1878 	.hback_porch = { 2, 2, 2 },
1879 	.hsync_len = { 86, 124, 244 },
1880 	.vactive = { 768, 768, 768 },
1881 	.vfront_porch = { 2, 2, 2 },
1882 	.vback_porch = { 2, 2, 2 },
1883 	.vsync_len = { 6, 34, 73 },
1884 	.flags = DISPLAY_FLAGS_DE_HIGH,
1885 };
1886 
1887 static const struct panel_desc kyo_tcg121xglp = {
1888 	.timings = &kyo_tcg121xglp_timing,
1889 	.num_timings = 1,
1890 	.bpc = 8,
1891 	.size = {
1892 		.width = 246,
1893 		.height = 184,
1894 	},
1895 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1896 };
1897 
1898 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1899 	.clock = 7000,
1900 	.hdisplay = 320,
1901 	.hsync_start = 320 + 20,
1902 	.hsync_end = 320 + 20 + 30,
1903 	.htotal = 320 + 20 + 30 + 38,
1904 	.vdisplay = 240,
1905 	.vsync_start = 240 + 4,
1906 	.vsync_end = 240 + 4 + 3,
1907 	.vtotal = 240 + 4 + 3 + 15,
1908 	.vrefresh = 60,
1909 };
1910 
1911 static const struct panel_desc lemaker_bl035_rgb_002 = {
1912 	.modes = &lemaker_bl035_rgb_002_mode,
1913 	.num_modes = 1,
1914 	.size = {
1915 		.width = 70,
1916 		.height = 52,
1917 	},
1918 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1919 	.bus_flags = DRM_BUS_FLAG_DE_LOW,
1920 };
1921 
1922 static const struct drm_display_mode lg_lb070wv8_mode = {
1923 	.clock = 33246,
1924 	.hdisplay = 800,
1925 	.hsync_start = 800 + 88,
1926 	.hsync_end = 800 + 88 + 80,
1927 	.htotal = 800 + 88 + 80 + 88,
1928 	.vdisplay = 480,
1929 	.vsync_start = 480 + 10,
1930 	.vsync_end = 480 + 10 + 25,
1931 	.vtotal = 480 + 10 + 25 + 10,
1932 	.vrefresh = 60,
1933 };
1934 
1935 static const struct panel_desc lg_lb070wv8 = {
1936 	.modes = &lg_lb070wv8_mode,
1937 	.num_modes = 1,
1938 	.bpc = 16,
1939 	.size = {
1940 		.width = 151,
1941 		.height = 91,
1942 	},
1943 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1944 };
1945 
1946 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1947 	.clock = 200000,
1948 	.hdisplay = 1536,
1949 	.hsync_start = 1536 + 12,
1950 	.hsync_end = 1536 + 12 + 16,
1951 	.htotal = 1536 + 12 + 16 + 48,
1952 	.vdisplay = 2048,
1953 	.vsync_start = 2048 + 8,
1954 	.vsync_end = 2048 + 8 + 4,
1955 	.vtotal = 2048 + 8 + 4 + 8,
1956 	.vrefresh = 60,
1957 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1958 };
1959 
1960 static const struct panel_desc lg_lp079qx1_sp0v = {
1961 	.modes = &lg_lp079qx1_sp0v_mode,
1962 	.num_modes = 1,
1963 	.size = {
1964 		.width = 129,
1965 		.height = 171,
1966 	},
1967 };
1968 
1969 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1970 	.clock = 205210,
1971 	.hdisplay = 2048,
1972 	.hsync_start = 2048 + 150,
1973 	.hsync_end = 2048 + 150 + 5,
1974 	.htotal = 2048 + 150 + 5 + 5,
1975 	.vdisplay = 1536,
1976 	.vsync_start = 1536 + 3,
1977 	.vsync_end = 1536 + 3 + 1,
1978 	.vtotal = 1536 + 3 + 1 + 9,
1979 	.vrefresh = 60,
1980 };
1981 
1982 static const struct panel_desc lg_lp097qx1_spa1 = {
1983 	.modes = &lg_lp097qx1_spa1_mode,
1984 	.num_modes = 1,
1985 	.size = {
1986 		.width = 208,
1987 		.height = 147,
1988 	},
1989 };
1990 
1991 static const struct drm_display_mode lg_lp120up1_mode = {
1992 	.clock = 162300,
1993 	.hdisplay = 1920,
1994 	.hsync_start = 1920 + 40,
1995 	.hsync_end = 1920 + 40 + 40,
1996 	.htotal = 1920 + 40 + 40+ 80,
1997 	.vdisplay = 1280,
1998 	.vsync_start = 1280 + 4,
1999 	.vsync_end = 1280 + 4 + 4,
2000 	.vtotal = 1280 + 4 + 4 + 12,
2001 	.vrefresh = 60,
2002 };
2003 
2004 static const struct panel_desc lg_lp120up1 = {
2005 	.modes = &lg_lp120up1_mode,
2006 	.num_modes = 1,
2007 	.bpc = 8,
2008 	.size = {
2009 		.width = 267,
2010 		.height = 183,
2011 	},
2012 };
2013 
2014 static const struct drm_display_mode lg_lp129qe_mode = {
2015 	.clock = 285250,
2016 	.hdisplay = 2560,
2017 	.hsync_start = 2560 + 48,
2018 	.hsync_end = 2560 + 48 + 32,
2019 	.htotal = 2560 + 48 + 32 + 80,
2020 	.vdisplay = 1700,
2021 	.vsync_start = 1700 + 3,
2022 	.vsync_end = 1700 + 3 + 10,
2023 	.vtotal = 1700 + 3 + 10 + 36,
2024 	.vrefresh = 60,
2025 };
2026 
2027 static const struct panel_desc lg_lp129qe = {
2028 	.modes = &lg_lp129qe_mode,
2029 	.num_modes = 1,
2030 	.bpc = 8,
2031 	.size = {
2032 		.width = 272,
2033 		.height = 181,
2034 	},
2035 };
2036 
2037 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2038 	.clock = 30400,
2039 	.hdisplay = 800,
2040 	.hsync_start = 800 + 0,
2041 	.hsync_end = 800 + 1,
2042 	.htotal = 800 + 0 + 1 + 160,
2043 	.vdisplay = 480,
2044 	.vsync_start = 480 + 0,
2045 	.vsync_end = 480 + 48 + 1,
2046 	.vtotal = 480 + 48 + 1 + 0,
2047 	.vrefresh = 60,
2048 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2049 };
2050 
2051 static const struct panel_desc mitsubishi_aa070mc01 = {
2052 	.modes = &mitsubishi_aa070mc01_mode,
2053 	.num_modes = 1,
2054 	.bpc = 8,
2055 	.size = {
2056 		.width = 152,
2057 		.height = 91,
2058 	},
2059 
2060 	.delay = {
2061 		.enable = 200,
2062 		.unprepare = 200,
2063 		.disable = 400,
2064 	},
2065 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2066 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2067 };
2068 
2069 static const struct display_timing nec_nl12880bc20_05_timing = {
2070 	.pixelclock = { 67000000, 71000000, 75000000 },
2071 	.hactive = { 1280, 1280, 1280 },
2072 	.hfront_porch = { 2, 30, 30 },
2073 	.hback_porch = { 6, 100, 100 },
2074 	.hsync_len = { 2, 30, 30 },
2075 	.vactive = { 800, 800, 800 },
2076 	.vfront_porch = { 5, 5, 5 },
2077 	.vback_porch = { 11, 11, 11 },
2078 	.vsync_len = { 7, 7, 7 },
2079 };
2080 
2081 static const struct panel_desc nec_nl12880bc20_05 = {
2082 	.timings = &nec_nl12880bc20_05_timing,
2083 	.num_timings = 1,
2084 	.bpc = 8,
2085 	.size = {
2086 		.width = 261,
2087 		.height = 163,
2088 	},
2089 	.delay = {
2090 		.enable = 50,
2091 		.disable = 50,
2092 	},
2093 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2094 };
2095 
2096 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2097 	.clock = 10870,
2098 	.hdisplay = 480,
2099 	.hsync_start = 480 + 2,
2100 	.hsync_end = 480 + 2 + 41,
2101 	.htotal = 480 + 2 + 41 + 2,
2102 	.vdisplay = 272,
2103 	.vsync_start = 272 + 2,
2104 	.vsync_end = 272 + 2 + 4,
2105 	.vtotal = 272 + 2 + 4 + 2,
2106 	.vrefresh = 74,
2107 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2108 };
2109 
2110 static const struct panel_desc nec_nl4827hc19_05b = {
2111 	.modes = &nec_nl4827hc19_05b_mode,
2112 	.num_modes = 1,
2113 	.bpc = 8,
2114 	.size = {
2115 		.width = 95,
2116 		.height = 54,
2117 	},
2118 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2119 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2120 };
2121 
2122 static const struct drm_display_mode netron_dy_e231732_mode = {
2123 	.clock = 66000,
2124 	.hdisplay = 1024,
2125 	.hsync_start = 1024 + 160,
2126 	.hsync_end = 1024 + 160 + 70,
2127 	.htotal = 1024 + 160 + 70 + 90,
2128 	.vdisplay = 600,
2129 	.vsync_start = 600 + 127,
2130 	.vsync_end = 600 + 127 + 20,
2131 	.vtotal = 600 + 127 + 20 + 3,
2132 	.vrefresh = 60,
2133 };
2134 
2135 static const struct panel_desc netron_dy_e231732 = {
2136 	.modes = &netron_dy_e231732_mode,
2137 	.num_modes = 1,
2138 	.size = {
2139 		.width = 154,
2140 		.height = 87,
2141 	},
2142 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2143 };
2144 
2145 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2146 	.clock = 9000,
2147 	.hdisplay = 480,
2148 	.hsync_start = 480 + 2,
2149 	.hsync_end = 480 + 2 + 41,
2150 	.htotal = 480 + 2 + 41 + 2,
2151 	.vdisplay = 272,
2152 	.vsync_start = 272 + 2,
2153 	.vsync_end = 272 + 2 + 10,
2154 	.vtotal = 272 + 2 + 10 + 2,
2155 	.vrefresh = 60,
2156 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2157 };
2158 
2159 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2160 	.modes = &newhaven_nhd_43_480272ef_atxl_mode,
2161 	.num_modes = 1,
2162 	.bpc = 8,
2163 	.size = {
2164 		.width = 95,
2165 		.height = 54,
2166 	},
2167 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2168 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2169 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2170 };
2171 
2172 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2173 	.pixelclock = { 130000000, 148350000, 163000000 },
2174 	.hactive = { 1920, 1920, 1920 },
2175 	.hfront_porch = { 80, 100, 100 },
2176 	.hback_porch = { 100, 120, 120 },
2177 	.hsync_len = { 50, 60, 60 },
2178 	.vactive = { 1080, 1080, 1080 },
2179 	.vfront_porch = { 12, 30, 30 },
2180 	.vback_porch = { 4, 10, 10 },
2181 	.vsync_len = { 4, 5, 5 },
2182 };
2183 
2184 static const struct panel_desc nlt_nl192108ac18_02d = {
2185 	.timings = &nlt_nl192108ac18_02d_timing,
2186 	.num_timings = 1,
2187 	.bpc = 8,
2188 	.size = {
2189 		.width = 344,
2190 		.height = 194,
2191 	},
2192 	.delay = {
2193 		.unprepare = 500,
2194 	},
2195 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2196 };
2197 
2198 static const struct drm_display_mode nvd_9128_mode = {
2199 	.clock = 29500,
2200 	.hdisplay = 800,
2201 	.hsync_start = 800 + 130,
2202 	.hsync_end = 800 + 130 + 98,
2203 	.htotal = 800 + 0 + 130 + 98,
2204 	.vdisplay = 480,
2205 	.vsync_start = 480 + 10,
2206 	.vsync_end = 480 + 10 + 50,
2207 	.vtotal = 480 + 0 + 10 + 50,
2208 };
2209 
2210 static const struct panel_desc nvd_9128 = {
2211 	.modes = &nvd_9128_mode,
2212 	.num_modes = 1,
2213 	.bpc = 8,
2214 	.size = {
2215 		.width = 156,
2216 		.height = 88,
2217 	},
2218 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2219 };
2220 
2221 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2222 	.pixelclock = { 30000000, 30000000, 40000000 },
2223 	.hactive = { 800, 800, 800 },
2224 	.hfront_porch = { 40, 40, 40 },
2225 	.hback_porch = { 40, 40, 40 },
2226 	.hsync_len = { 1, 48, 48 },
2227 	.vactive = { 480, 480, 480 },
2228 	.vfront_porch = { 13, 13, 13 },
2229 	.vback_porch = { 29, 29, 29 },
2230 	.vsync_len = { 3, 3, 3 },
2231 	.flags = DISPLAY_FLAGS_DE_HIGH,
2232 };
2233 
2234 static const struct panel_desc okaya_rs800480t_7x0gp = {
2235 	.timings = &okaya_rs800480t_7x0gp_timing,
2236 	.num_timings = 1,
2237 	.bpc = 6,
2238 	.size = {
2239 		.width = 154,
2240 		.height = 87,
2241 	},
2242 	.delay = {
2243 		.prepare = 41,
2244 		.enable = 50,
2245 		.unprepare = 41,
2246 		.disable = 50,
2247 	},
2248 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2249 };
2250 
2251 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2252 	.clock = 9000,
2253 	.hdisplay = 480,
2254 	.hsync_start = 480 + 5,
2255 	.hsync_end = 480 + 5 + 30,
2256 	.htotal = 480 + 5 + 30 + 10,
2257 	.vdisplay = 272,
2258 	.vsync_start = 272 + 8,
2259 	.vsync_end = 272 + 8 + 5,
2260 	.vtotal = 272 + 8 + 5 + 3,
2261 	.vrefresh = 60,
2262 };
2263 
2264 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2265 	.modes = &olimex_lcd_olinuxino_43ts_mode,
2266 	.num_modes = 1,
2267 	.size = {
2268 		.width = 95,
2269 		.height = 54,
2270 	},
2271 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2272 };
2273 
2274 /*
2275  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2276  * pixel clocks, but this is the timing that was being used in the Adafruit
2277  * installation instructions.
2278  */
2279 static const struct drm_display_mode ontat_yx700wv03_mode = {
2280 	.clock = 29500,
2281 	.hdisplay = 800,
2282 	.hsync_start = 824,
2283 	.hsync_end = 896,
2284 	.htotal = 992,
2285 	.vdisplay = 480,
2286 	.vsync_start = 483,
2287 	.vsync_end = 493,
2288 	.vtotal = 500,
2289 	.vrefresh = 60,
2290 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2291 };
2292 
2293 /*
2294  * Specification at:
2295  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2296  */
2297 static const struct panel_desc ontat_yx700wv03 = {
2298 	.modes = &ontat_yx700wv03_mode,
2299 	.num_modes = 1,
2300 	.bpc = 8,
2301 	.size = {
2302 		.width = 154,
2303 		.height = 83,
2304 	},
2305 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2306 };
2307 
2308 static const struct drm_display_mode ortustech_com37h3m_mode  = {
2309 	.clock = 22153,
2310 	.hdisplay = 480,
2311 	.hsync_start = 480 + 8,
2312 	.hsync_end = 480 + 8 + 10,
2313 	.htotal = 480 + 8 + 10 + 10,
2314 	.vdisplay = 640,
2315 	.vsync_start = 640 + 4,
2316 	.vsync_end = 640 + 4 + 3,
2317 	.vtotal = 640 + 4 + 3 + 4,
2318 	.vrefresh = 60,
2319 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2320 };
2321 
2322 static const struct panel_desc ortustech_com37h3m = {
2323 	.modes = &ortustech_com37h3m_mode,
2324 	.num_modes = 1,
2325 	.bpc = 8,
2326 	.size = {
2327 		.width = 56,	/* 56.16mm */
2328 		.height = 75,	/* 74.88mm */
2329 	},
2330 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2331 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2332 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2333 };
2334 
2335 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
2336 	.clock = 25000,
2337 	.hdisplay = 480,
2338 	.hsync_start = 480 + 10,
2339 	.hsync_end = 480 + 10 + 10,
2340 	.htotal = 480 + 10 + 10 + 15,
2341 	.vdisplay = 800,
2342 	.vsync_start = 800 + 3,
2343 	.vsync_end = 800 + 3 + 3,
2344 	.vtotal = 800 + 3 + 3 + 3,
2345 	.vrefresh = 60,
2346 };
2347 
2348 static const struct panel_desc ortustech_com43h4m85ulc = {
2349 	.modes = &ortustech_com43h4m85ulc_mode,
2350 	.num_modes = 1,
2351 	.bpc = 8,
2352 	.size = {
2353 		.width = 56,
2354 		.height = 93,
2355 	},
2356 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2357 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2358 };
2359 
2360 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
2361 	.clock = 33000,
2362 	.hdisplay = 800,
2363 	.hsync_start = 800 + 210,
2364 	.hsync_end = 800 + 210 + 30,
2365 	.htotal = 800 + 210 + 30 + 16,
2366 	.vdisplay = 480,
2367 	.vsync_start = 480 + 22,
2368 	.vsync_end = 480 + 22 + 13,
2369 	.vtotal = 480 + 22 + 13 + 10,
2370 	.vrefresh = 60,
2371 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2372 };
2373 
2374 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2375 	.modes = &osddisplays_osd070t1718_19ts_mode,
2376 	.num_modes = 1,
2377 	.bpc = 8,
2378 	.size = {
2379 		.width = 152,
2380 		.height = 91,
2381 	},
2382 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2383 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2384 };
2385 
2386 static const struct drm_display_mode pda_91_00156_a0_mode = {
2387 	.clock = 33300,
2388 	.hdisplay = 800,
2389 	.hsync_start = 800 + 1,
2390 	.hsync_end = 800 + 1 + 64,
2391 	.htotal = 800 + 1 + 64 + 64,
2392 	.vdisplay = 480,
2393 	.vsync_start = 480 + 1,
2394 	.vsync_end = 480 + 1 + 23,
2395 	.vtotal = 480 + 1 + 23 + 22,
2396 	.vrefresh = 60,
2397 };
2398 
2399 static const struct panel_desc pda_91_00156_a0  = {
2400 	.modes = &pda_91_00156_a0_mode,
2401 	.num_modes = 1,
2402 	.size = {
2403 		.width = 152,
2404 		.height = 91,
2405 	},
2406 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2407 };
2408 
2409 
2410 static const struct drm_display_mode qd43003c0_40_mode = {
2411 	.clock = 9000,
2412 	.hdisplay = 480,
2413 	.hsync_start = 480 + 8,
2414 	.hsync_end = 480 + 8 + 4,
2415 	.htotal = 480 + 8 + 4 + 39,
2416 	.vdisplay = 272,
2417 	.vsync_start = 272 + 4,
2418 	.vsync_end = 272 + 4 + 10,
2419 	.vtotal = 272 + 4 + 10 + 2,
2420 	.vrefresh = 60,
2421 };
2422 
2423 static const struct panel_desc qd43003c0_40 = {
2424 	.modes = &qd43003c0_40_mode,
2425 	.num_modes = 1,
2426 	.bpc = 8,
2427 	.size = {
2428 		.width = 95,
2429 		.height = 53,
2430 	},
2431 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2432 };
2433 
2434 static const struct display_timing rocktech_rk070er9427_timing = {
2435 	.pixelclock = { 26400000, 33300000, 46800000 },
2436 	.hactive = { 800, 800, 800 },
2437 	.hfront_porch = { 16, 210, 354 },
2438 	.hback_porch = { 46, 46, 46 },
2439 	.hsync_len = { 1, 1, 1 },
2440 	.vactive = { 480, 480, 480 },
2441 	.vfront_porch = { 7, 22, 147 },
2442 	.vback_porch = { 23, 23, 23 },
2443 	.vsync_len = { 1, 1, 1 },
2444 	.flags = DISPLAY_FLAGS_DE_HIGH,
2445 };
2446 
2447 static const struct panel_desc rocktech_rk070er9427 = {
2448 	.timings = &rocktech_rk070er9427_timing,
2449 	.num_timings = 1,
2450 	.bpc = 6,
2451 	.size = {
2452 		.width = 154,
2453 		.height = 86,
2454 	},
2455 	.delay = {
2456 		.prepare = 41,
2457 		.enable = 50,
2458 		.unprepare = 41,
2459 		.disable = 50,
2460 	},
2461 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2462 };
2463 
2464 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2465 	.clock = 271560,
2466 	.hdisplay = 2560,
2467 	.hsync_start = 2560 + 48,
2468 	.hsync_end = 2560 + 48 + 32,
2469 	.htotal = 2560 + 48 + 32 + 80,
2470 	.vdisplay = 1600,
2471 	.vsync_start = 1600 + 2,
2472 	.vsync_end = 1600 + 2 + 5,
2473 	.vtotal = 1600 + 2 + 5 + 57,
2474 	.vrefresh = 60,
2475 };
2476 
2477 static const struct panel_desc samsung_lsn122dl01_c01 = {
2478 	.modes = &samsung_lsn122dl01_c01_mode,
2479 	.num_modes = 1,
2480 	.size = {
2481 		.width = 263,
2482 		.height = 164,
2483 	},
2484 };
2485 
2486 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2487 	.clock = 54030,
2488 	.hdisplay = 1024,
2489 	.hsync_start = 1024 + 24,
2490 	.hsync_end = 1024 + 24 + 136,
2491 	.htotal = 1024 + 24 + 136 + 160,
2492 	.vdisplay = 600,
2493 	.vsync_start = 600 + 3,
2494 	.vsync_end = 600 + 3 + 6,
2495 	.vtotal = 600 + 3 + 6 + 61,
2496 	.vrefresh = 60,
2497 };
2498 
2499 static const struct panel_desc samsung_ltn101nt05 = {
2500 	.modes = &samsung_ltn101nt05_mode,
2501 	.num_modes = 1,
2502 	.bpc = 6,
2503 	.size = {
2504 		.width = 223,
2505 		.height = 125,
2506 	},
2507 };
2508 
2509 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2510 	.clock = 76300,
2511 	.hdisplay = 1366,
2512 	.hsync_start = 1366 + 64,
2513 	.hsync_end = 1366 + 64 + 48,
2514 	.htotal = 1366 + 64 + 48 + 128,
2515 	.vdisplay = 768,
2516 	.vsync_start = 768 + 2,
2517 	.vsync_end = 768 + 2 + 5,
2518 	.vtotal = 768 + 2 + 5 + 17,
2519 	.vrefresh = 60,
2520 };
2521 
2522 static const struct panel_desc samsung_ltn140at29_301 = {
2523 	.modes = &samsung_ltn140at29_301_mode,
2524 	.num_modes = 1,
2525 	.bpc = 6,
2526 	.size = {
2527 		.width = 320,
2528 		.height = 187,
2529 	},
2530 };
2531 
2532 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2533 	.clock = 168480,
2534 	.hdisplay = 1920,
2535 	.hsync_start = 1920 + 48,
2536 	.hsync_end = 1920 + 48 + 32,
2537 	.htotal = 1920 + 48 + 32 + 80,
2538 	.vdisplay = 1280,
2539 	.vsync_start = 1280 + 3,
2540 	.vsync_end = 1280 + 3 + 10,
2541 	.vtotal = 1280 + 3 + 10 + 57,
2542 	.vrefresh = 60,
2543 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2544 };
2545 
2546 static const struct panel_desc sharp_ld_d5116z01b = {
2547 	.modes = &sharp_ld_d5116z01b_mode,
2548 	.num_modes = 1,
2549 	.bpc = 8,
2550 	.size = {
2551 		.width = 260,
2552 		.height = 120,
2553 	},
2554 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2555 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2556 };
2557 
2558 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2559 	.clock = 33260,
2560 	.hdisplay = 800,
2561 	.hsync_start = 800 + 64,
2562 	.hsync_end = 800 + 64 + 128,
2563 	.htotal = 800 + 64 + 128 + 64,
2564 	.vdisplay = 480,
2565 	.vsync_start = 480 + 8,
2566 	.vsync_end = 480 + 8 + 2,
2567 	.vtotal = 480 + 8 + 2 + 35,
2568 	.vrefresh = 60,
2569 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2570 };
2571 
2572 static const struct panel_desc sharp_lq070y3dg3b = {
2573 	.modes = &sharp_lq070y3dg3b_mode,
2574 	.num_modes = 1,
2575 	.bpc = 8,
2576 	.size = {
2577 		.width = 152,	/* 152.4mm */
2578 		.height = 91,	/* 91.4mm */
2579 	},
2580 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2581 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2582 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2583 };
2584 
2585 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2586 	.clock = 5500,
2587 	.hdisplay = 240,
2588 	.hsync_start = 240 + 16,
2589 	.hsync_end = 240 + 16 + 7,
2590 	.htotal = 240 + 16 + 7 + 5,
2591 	.vdisplay = 320,
2592 	.vsync_start = 320 + 9,
2593 	.vsync_end = 320 + 9 + 1,
2594 	.vtotal = 320 + 9 + 1 + 7,
2595 	.vrefresh = 60,
2596 };
2597 
2598 static const struct panel_desc sharp_lq035q7db03 = {
2599 	.modes = &sharp_lq035q7db03_mode,
2600 	.num_modes = 1,
2601 	.bpc = 6,
2602 	.size = {
2603 		.width = 54,
2604 		.height = 72,
2605 	},
2606 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2607 };
2608 
2609 static const struct display_timing sharp_lq101k1ly04_timing = {
2610 	.pixelclock = { 60000000, 65000000, 80000000 },
2611 	.hactive = { 1280, 1280, 1280 },
2612 	.hfront_porch = { 20, 20, 20 },
2613 	.hback_porch = { 20, 20, 20 },
2614 	.hsync_len = { 10, 10, 10 },
2615 	.vactive = { 800, 800, 800 },
2616 	.vfront_porch = { 4, 4, 4 },
2617 	.vback_porch = { 4, 4, 4 },
2618 	.vsync_len = { 4, 4, 4 },
2619 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2620 };
2621 
2622 static const struct panel_desc sharp_lq101k1ly04 = {
2623 	.timings = &sharp_lq101k1ly04_timing,
2624 	.num_timings = 1,
2625 	.bpc = 8,
2626 	.size = {
2627 		.width = 217,
2628 		.height = 136,
2629 	},
2630 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2631 };
2632 
2633 static const struct display_timing sharp_lq123p1jx31_timing = {
2634 	.pixelclock = { 252750000, 252750000, 266604720 },
2635 	.hactive = { 2400, 2400, 2400 },
2636 	.hfront_porch = { 48, 48, 48 },
2637 	.hback_porch = { 80, 80, 84 },
2638 	.hsync_len = { 32, 32, 32 },
2639 	.vactive = { 1600, 1600, 1600 },
2640 	.vfront_porch = { 3, 3, 3 },
2641 	.vback_porch = { 33, 33, 120 },
2642 	.vsync_len = { 10, 10, 10 },
2643 	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2644 };
2645 
2646 static const struct panel_desc sharp_lq123p1jx31 = {
2647 	.timings = &sharp_lq123p1jx31_timing,
2648 	.num_timings = 1,
2649 	.bpc = 8,
2650 	.size = {
2651 		.width = 259,
2652 		.height = 173,
2653 	},
2654 	.delay = {
2655 		.prepare = 110,
2656 		.enable = 50,
2657 		.unprepare = 550,
2658 	},
2659 };
2660 
2661 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2662 	.clock = 71100,
2663 	.hdisplay = 1024,
2664 	.hsync_start = 1024 + 168,
2665 	.hsync_end = 1024 + 168 + 64,
2666 	.htotal = 1024 + 168 + 64 + 88,
2667 	.vdisplay = 768,
2668 	.vsync_start = 768 + 37,
2669 	.vsync_end = 768 + 37 + 2,
2670 	.vtotal = 768 + 37 + 2 + 8,
2671 	.vrefresh = 60,
2672 };
2673 
2674 static const struct panel_desc sharp_lq150x1lg11 = {
2675 	.modes = &sharp_lq150x1lg11_mode,
2676 	.num_modes = 1,
2677 	.bpc = 6,
2678 	.size = {
2679 		.width = 304,
2680 		.height = 228,
2681 	},
2682 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2683 };
2684 
2685 static const struct display_timing sharp_ls020b1dd01d_timing = {
2686 	.pixelclock = { 2000000, 4200000, 5000000 },
2687 	.hactive = { 240, 240, 240 },
2688 	.hfront_porch = { 66, 66, 66 },
2689 	.hback_porch = { 1, 1, 1 },
2690 	.hsync_len = { 1, 1, 1 },
2691 	.vactive = { 160, 160, 160 },
2692 	.vfront_porch = { 52, 52, 52 },
2693 	.vback_porch = { 6, 6, 6 },
2694 	.vsync_len = { 10, 10, 10 },
2695 	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2696 };
2697 
2698 static const struct panel_desc sharp_ls020b1dd01d = {
2699 	.timings = &sharp_ls020b1dd01d_timing,
2700 	.num_timings = 1,
2701 	.bpc = 6,
2702 	.size = {
2703 		.width = 42,
2704 		.height = 28,
2705 	},
2706 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2707 	.bus_flags = DRM_BUS_FLAG_DE_HIGH
2708 		   | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2709 		   | DRM_BUS_FLAG_SHARP_SIGNALS,
2710 };
2711 
2712 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2713 	.clock = 33300,
2714 	.hdisplay = 800,
2715 	.hsync_start = 800 + 1,
2716 	.hsync_end = 800 + 1 + 64,
2717 	.htotal = 800 + 1 + 64 + 64,
2718 	.vdisplay = 480,
2719 	.vsync_start = 480 + 1,
2720 	.vsync_end = 480 + 1 + 23,
2721 	.vtotal = 480 + 1 + 23 + 22,
2722 	.vrefresh = 60,
2723 };
2724 
2725 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2726 	.modes = &shelly_sca07010_bfn_lnn_mode,
2727 	.num_modes = 1,
2728 	.size = {
2729 		.width = 152,
2730 		.height = 91,
2731 	},
2732 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2733 };
2734 
2735 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2736 	.clock = 147000,
2737 	.hdisplay = 1920,
2738 	.hsync_start = 1920 + 16,
2739 	.hsync_end = 1920 + 16 + 16,
2740 	.htotal = 1920 + 16 + 16 + 32,
2741 	.vdisplay = 1200,
2742 	.vsync_start = 1200 + 15,
2743 	.vsync_end = 1200 + 15 + 2,
2744 	.vtotal = 1200 + 15 + 2 + 18,
2745 	.vrefresh = 60,
2746 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2747 };
2748 
2749 static const struct panel_desc starry_kr122ea0sra = {
2750 	.modes = &starry_kr122ea0sra_mode,
2751 	.num_modes = 1,
2752 	.size = {
2753 		.width = 263,
2754 		.height = 164,
2755 	},
2756 	.delay = {
2757 		.prepare = 10 + 200,
2758 		.enable = 50,
2759 		.unprepare = 10 + 500,
2760 	},
2761 };
2762 
2763 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2764 	.clock = 30000,
2765 	.hdisplay = 800,
2766 	.hsync_start = 800 + 39,
2767 	.hsync_end = 800 + 39 + 47,
2768 	.htotal = 800 + 39 + 47 + 39,
2769 	.vdisplay = 480,
2770 	.vsync_start = 480 + 13,
2771 	.vsync_end = 480 + 13 + 2,
2772 	.vtotal = 480 + 13 + 2 + 29,
2773 	.vrefresh = 62,
2774 };
2775 
2776 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2777 	.modes = &tfc_s9700rtwv43tr_01b_mode,
2778 	.num_modes = 1,
2779 	.bpc = 8,
2780 	.size = {
2781 		.width = 155,
2782 		.height = 90,
2783 	},
2784 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2785 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2786 };
2787 
2788 static const struct display_timing tianma_tm070jdhg30_timing = {
2789 	.pixelclock = { 62600000, 68200000, 78100000 },
2790 	.hactive = { 1280, 1280, 1280 },
2791 	.hfront_porch = { 15, 64, 159 },
2792 	.hback_porch = { 5, 5, 5 },
2793 	.hsync_len = { 1, 1, 256 },
2794 	.vactive = { 800, 800, 800 },
2795 	.vfront_porch = { 3, 40, 99 },
2796 	.vback_porch = { 2, 2, 2 },
2797 	.vsync_len = { 1, 1, 128 },
2798 	.flags = DISPLAY_FLAGS_DE_HIGH,
2799 };
2800 
2801 static const struct panel_desc tianma_tm070jdhg30 = {
2802 	.timings = &tianma_tm070jdhg30_timing,
2803 	.num_timings = 1,
2804 	.bpc = 8,
2805 	.size = {
2806 		.width = 151,
2807 		.height = 95,
2808 	},
2809 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2810 };
2811 
2812 static const struct display_timing tianma_tm070rvhg71_timing = {
2813 	.pixelclock = { 27700000, 29200000, 39600000 },
2814 	.hactive = { 800, 800, 800 },
2815 	.hfront_porch = { 12, 40, 212 },
2816 	.hback_porch = { 88, 88, 88 },
2817 	.hsync_len = { 1, 1, 40 },
2818 	.vactive = { 480, 480, 480 },
2819 	.vfront_porch = { 1, 13, 88 },
2820 	.vback_porch = { 32, 32, 32 },
2821 	.vsync_len = { 1, 1, 3 },
2822 	.flags = DISPLAY_FLAGS_DE_HIGH,
2823 };
2824 
2825 static const struct panel_desc tianma_tm070rvhg71 = {
2826 	.timings = &tianma_tm070rvhg71_timing,
2827 	.num_timings = 1,
2828 	.bpc = 8,
2829 	.size = {
2830 		.width = 154,
2831 		.height = 86,
2832 	},
2833 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2834 };
2835 
2836 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2837 	{
2838 		.clock = 10000,
2839 		.hdisplay = 320,
2840 		.hsync_start = 320 + 50,
2841 		.hsync_end = 320 + 50 + 6,
2842 		.htotal = 320 + 50 + 6 + 38,
2843 		.vdisplay = 240,
2844 		.vsync_start = 240 + 3,
2845 		.vsync_end = 240 + 3 + 1,
2846 		.vtotal = 240 + 3 + 1 + 17,
2847 		.vrefresh = 60,
2848 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2849 	},
2850 };
2851 
2852 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2853 	.modes = ti_nspire_cx_lcd_mode,
2854 	.num_modes = 1,
2855 	.bpc = 8,
2856 	.size = {
2857 		.width = 65,
2858 		.height = 49,
2859 	},
2860 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2861 	.bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2862 };
2863 
2864 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2865 	{
2866 		.clock = 10000,
2867 		.hdisplay = 320,
2868 		.hsync_start = 320 + 6,
2869 		.hsync_end = 320 + 6 + 6,
2870 		.htotal = 320 + 6 + 6 + 6,
2871 		.vdisplay = 240,
2872 		.vsync_start = 240 + 0,
2873 		.vsync_end = 240 + 0 + 1,
2874 		.vtotal = 240 + 0 + 1 + 0,
2875 		.vrefresh = 60,
2876 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2877 	},
2878 };
2879 
2880 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2881 	.modes = ti_nspire_classic_lcd_mode,
2882 	.num_modes = 1,
2883 	/* The grayscale panel has 8 bit for the color .. Y (black) */
2884 	.bpc = 8,
2885 	.size = {
2886 		.width = 71,
2887 		.height = 53,
2888 	},
2889 	/* This is the grayscale bus format */
2890 	.bus_format = MEDIA_BUS_FMT_Y8_1X8,
2891 	.bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2892 };
2893 
2894 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2895 	.clock = 79500,
2896 	.hdisplay = 1280,
2897 	.hsync_start = 1280 + 192,
2898 	.hsync_end = 1280 + 192 + 128,
2899 	.htotal = 1280 + 192 + 128 + 64,
2900 	.vdisplay = 768,
2901 	.vsync_start = 768 + 20,
2902 	.vsync_end = 768 + 20 + 7,
2903 	.vtotal = 768 + 20 + 7 + 3,
2904 	.vrefresh = 60,
2905 };
2906 
2907 static const struct panel_desc toshiba_lt089ac29000 = {
2908 	.modes = &toshiba_lt089ac29000_mode,
2909 	.num_modes = 1,
2910 	.size = {
2911 		.width = 194,
2912 		.height = 116,
2913 	},
2914 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2915 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2916 };
2917 
2918 static const struct drm_display_mode tpk_f07a_0102_mode = {
2919 	.clock = 33260,
2920 	.hdisplay = 800,
2921 	.hsync_start = 800 + 40,
2922 	.hsync_end = 800 + 40 + 128,
2923 	.htotal = 800 + 40 + 128 + 88,
2924 	.vdisplay = 480,
2925 	.vsync_start = 480 + 10,
2926 	.vsync_end = 480 + 10 + 2,
2927 	.vtotal = 480 + 10 + 2 + 33,
2928 	.vrefresh = 60,
2929 };
2930 
2931 static const struct panel_desc tpk_f07a_0102 = {
2932 	.modes = &tpk_f07a_0102_mode,
2933 	.num_modes = 1,
2934 	.size = {
2935 		.width = 152,
2936 		.height = 91,
2937 	},
2938 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2939 };
2940 
2941 static const struct drm_display_mode tpk_f10a_0102_mode = {
2942 	.clock = 45000,
2943 	.hdisplay = 1024,
2944 	.hsync_start = 1024 + 176,
2945 	.hsync_end = 1024 + 176 + 5,
2946 	.htotal = 1024 + 176 + 5 + 88,
2947 	.vdisplay = 600,
2948 	.vsync_start = 600 + 20,
2949 	.vsync_end = 600 + 20 + 5,
2950 	.vtotal = 600 + 20 + 5 + 25,
2951 	.vrefresh = 60,
2952 };
2953 
2954 static const struct panel_desc tpk_f10a_0102 = {
2955 	.modes = &tpk_f10a_0102_mode,
2956 	.num_modes = 1,
2957 	.size = {
2958 		.width = 223,
2959 		.height = 125,
2960 	},
2961 };
2962 
2963 static const struct display_timing urt_umsh_8596md_timing = {
2964 	.pixelclock = { 33260000, 33260000, 33260000 },
2965 	.hactive = { 800, 800, 800 },
2966 	.hfront_porch = { 41, 41, 41 },
2967 	.hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2968 	.hsync_len = { 71, 128, 128 },
2969 	.vactive = { 480, 480, 480 },
2970 	.vfront_porch = { 10, 10, 10 },
2971 	.vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2972 	.vsync_len = { 2, 2, 2 },
2973 	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2974 		DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2975 };
2976 
2977 static const struct panel_desc urt_umsh_8596md_lvds = {
2978 	.timings = &urt_umsh_8596md_timing,
2979 	.num_timings = 1,
2980 	.bpc = 6,
2981 	.size = {
2982 		.width = 152,
2983 		.height = 91,
2984 	},
2985 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2986 };
2987 
2988 static const struct panel_desc urt_umsh_8596md_parallel = {
2989 	.timings = &urt_umsh_8596md_timing,
2990 	.num_timings = 1,
2991 	.bpc = 6,
2992 	.size = {
2993 		.width = 152,
2994 		.height = 91,
2995 	},
2996 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2997 };
2998 
2999 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3000 	.clock = 33333,
3001 	.hdisplay = 800,
3002 	.hsync_start = 800 + 210,
3003 	.hsync_end = 800 + 210 + 20,
3004 	.htotal = 800 + 210 + 20 + 46,
3005 	.vdisplay =  480,
3006 	.vsync_start = 480 + 22,
3007 	.vsync_end = 480 + 22 + 10,
3008 	.vtotal = 480 + 22 + 10 + 23,
3009 	.vrefresh = 60,
3010 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3011 };
3012 
3013 static const struct panel_desc vl050_8048nt_c01 = {
3014 	.modes = &vl050_8048nt_c01_mode,
3015 	.num_modes = 1,
3016 	.bpc = 8,
3017 	.size = {
3018 		.width = 120,
3019 		.height = 76,
3020 	},
3021 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3022 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3023 };
3024 
3025 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3026 	.clock = 6410,
3027 	.hdisplay = 320,
3028 	.hsync_start = 320 + 20,
3029 	.hsync_end = 320 + 20 + 30,
3030 	.htotal = 320 + 20 + 30 + 38,
3031 	.vdisplay = 240,
3032 	.vsync_start = 240 + 4,
3033 	.vsync_end = 240 + 4 + 3,
3034 	.vtotal = 240 + 4 + 3 + 15,
3035 	.vrefresh = 60,
3036 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3037 };
3038 
3039 static const struct panel_desc winstar_wf35ltiacd = {
3040 	.modes = &winstar_wf35ltiacd_mode,
3041 	.num_modes = 1,
3042 	.bpc = 8,
3043 	.size = {
3044 		.width = 70,
3045 		.height = 53,
3046 	},
3047 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3048 };
3049 
3050 static const struct drm_display_mode arm_rtsm_mode[] = {
3051 	{
3052 		.clock = 65000,
3053 		.hdisplay = 1024,
3054 		.hsync_start = 1024 + 24,
3055 		.hsync_end = 1024 + 24 + 136,
3056 		.htotal = 1024 + 24 + 136 + 160,
3057 		.vdisplay = 768,
3058 		.vsync_start = 768 + 3,
3059 		.vsync_end = 768 + 3 + 6,
3060 		.vtotal = 768 + 3 + 6 + 29,
3061 		.vrefresh = 60,
3062 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3063 	},
3064 };
3065 
3066 static const struct panel_desc arm_rtsm = {
3067 	.modes = arm_rtsm_mode,
3068 	.num_modes = 1,
3069 	.bpc = 8,
3070 	.size = {
3071 		.width = 400,
3072 		.height = 300,
3073 	},
3074 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3075 };
3076 
3077 static const struct of_device_id platform_of_match[] = {
3078 	{
3079 		.compatible = "ampire,am-480272h3tmqw-t01h",
3080 		.data = &ampire_am_480272h3tmqw_t01h,
3081 	}, {
3082 		.compatible = "ampire,am800480r3tmqwa1h",
3083 		.data = &ampire_am800480r3tmqwa1h,
3084 	}, {
3085 		.compatible = "arm,rtsm-display",
3086 		.data = &arm_rtsm,
3087 	}, {
3088 		.compatible = "armadeus,st0700-adapt",
3089 		.data = &armadeus_st0700_adapt,
3090 	}, {
3091 		.compatible = "auo,b101aw03",
3092 		.data = &auo_b101aw03,
3093 	}, {
3094 		.compatible = "auo,b101ean01",
3095 		.data = &auo_b101ean01,
3096 	}, {
3097 		.compatible = "auo,b101xtn01",
3098 		.data = &auo_b101xtn01,
3099 	}, {
3100 		.compatible = "auo,b116xw03",
3101 		.data = &auo_b116xw03,
3102 	}, {
3103 		.compatible = "auo,b133htn01",
3104 		.data = &auo_b133htn01,
3105 	}, {
3106 		.compatible = "auo,b133xtn01",
3107 		.data = &auo_b133xtn01,
3108 	}, {
3109 		.compatible = "auo,g070vvn01",
3110 		.data = &auo_g070vvn01,
3111 	}, {
3112 		.compatible = "auo,g101evn010",
3113 		.data = &auo_g101evn010,
3114 	}, {
3115 		.compatible = "auo,g104sn02",
3116 		.data = &auo_g104sn02,
3117 	}, {
3118 		.compatible = "auo,g133han01",
3119 		.data = &auo_g133han01,
3120 	}, {
3121 		.compatible = "auo,g185han01",
3122 		.data = &auo_g185han01,
3123 	}, {
3124 		.compatible = "auo,p320hvn03",
3125 		.data = &auo_p320hvn03,
3126 	}, {
3127 		.compatible = "auo,t215hvn01",
3128 		.data = &auo_t215hvn01,
3129 	}, {
3130 		.compatible = "avic,tm070ddh03",
3131 		.data = &avic_tm070ddh03,
3132 	}, {
3133 		.compatible = "bananapi,s070wv20-ct16",
3134 		.data = &bananapi_s070wv20_ct16,
3135 	}, {
3136 		.compatible = "boe,hv070wsa-100",
3137 		.data = &boe_hv070wsa
3138 	}, {
3139 		.compatible = "boe,nv101wxmn51",
3140 		.data = &boe_nv101wxmn51,
3141 	}, {
3142 		.compatible = "cdtech,s043wq26h-ct7",
3143 		.data = &cdtech_s043wq26h_ct7,
3144 	}, {
3145 		.compatible = "cdtech,s070wv95-ct16",
3146 		.data = &cdtech_s070wv95_ct16,
3147 	}, {
3148 		.compatible = "chunghwa,claa070wp03xg",
3149 		.data = &chunghwa_claa070wp03xg,
3150 	}, {
3151 		.compatible = "chunghwa,claa101wa01a",
3152 		.data = &chunghwa_claa101wa01a
3153 	}, {
3154 		.compatible = "chunghwa,claa101wb01",
3155 		.data = &chunghwa_claa101wb01
3156 	}, {
3157 		.compatible = "dataimage,scf0700c48ggu18",
3158 		.data = &dataimage_scf0700c48ggu18,
3159 	}, {
3160 		.compatible = "dlc,dlc0700yzg-1",
3161 		.data = &dlc_dlc0700yzg_1,
3162 	}, {
3163 		.compatible = "dlc,dlc1010gig",
3164 		.data = &dlc_dlc1010gig,
3165 	}, {
3166 		.compatible = "edt,et035012dm6",
3167 		.data = &edt_et035012dm6,
3168 	}, {
3169 		.compatible = "edt,etm0430g0dh6",
3170 		.data = &edt_etm0430g0dh6,
3171 	}, {
3172 		.compatible = "edt,et057090dhu",
3173 		.data = &edt_et057090dhu,
3174 	}, {
3175 		.compatible = "edt,et070080dh6",
3176 		.data = &edt_etm0700g0dh6,
3177 	}, {
3178 		.compatible = "edt,etm0700g0dh6",
3179 		.data = &edt_etm0700g0dh6,
3180 	}, {
3181 		.compatible = "edt,etm0700g0bdh6",
3182 		.data = &edt_etm0700g0bdh6,
3183 	}, {
3184 		.compatible = "edt,etm0700g0edh6",
3185 		.data = &edt_etm0700g0bdh6,
3186 	}, {
3187 		.compatible = "evervision,vgg804821",
3188 		.data = &evervision_vgg804821,
3189 	}, {
3190 		.compatible = "foxlink,fl500wvr00-a0t",
3191 		.data = &foxlink_fl500wvr00_a0t,
3192 	}, {
3193 		.compatible = "friendlyarm,hd702e",
3194 		.data = &friendlyarm_hd702e,
3195 	}, {
3196 		.compatible = "giantplus,gpg482739qs5",
3197 		.data = &giantplus_gpg482739qs5
3198 	}, {
3199 		.compatible = "giantplus,gpm940b0",
3200 		.data = &giantplus_gpm940b0,
3201 	}, {
3202 		.compatible = "hannstar,hsd070pww1",
3203 		.data = &hannstar_hsd070pww1,
3204 	}, {
3205 		.compatible = "hannstar,hsd100pxn1",
3206 		.data = &hannstar_hsd100pxn1,
3207 	}, {
3208 		.compatible = "hit,tx23d38vm0caa",
3209 		.data = &hitachi_tx23d38vm0caa
3210 	}, {
3211 		.compatible = "innolux,at043tn24",
3212 		.data = &innolux_at043tn24,
3213 	}, {
3214 		.compatible = "innolux,at070tn92",
3215 		.data = &innolux_at070tn92,
3216 	}, {
3217 		.compatible = "innolux,g070y2-l01",
3218 		.data = &innolux_g070y2_l01,
3219 	}, {
3220 		.compatible = "innolux,g101ice-l01",
3221 		.data = &innolux_g101ice_l01
3222 	}, {
3223 		.compatible = "innolux,g121i1-l01",
3224 		.data = &innolux_g121i1_l01
3225 	}, {
3226 		.compatible = "innolux,g121x1-l03",
3227 		.data = &innolux_g121x1_l03,
3228 	}, {
3229 		.compatible = "innolux,n116bge",
3230 		.data = &innolux_n116bge,
3231 	}, {
3232 		.compatible = "innolux,n156bge-l21",
3233 		.data = &innolux_n156bge_l21,
3234 	}, {
3235 		.compatible = "innolux,p120zdg-bf1",
3236 		.data = &innolux_p120zdg_bf1,
3237 	}, {
3238 		.compatible = "innolux,zj070na-01p",
3239 		.data = &innolux_zj070na_01p,
3240 	}, {
3241 		.compatible = "koe,tx14d24vm1bpa",
3242 		.data = &koe_tx14d24vm1bpa,
3243 	}, {
3244 		.compatible = "koe,tx31d200vm0baa",
3245 		.data = &koe_tx31d200vm0baa,
3246 	}, {
3247 		.compatible = "kyo,tcg121xglp",
3248 		.data = &kyo_tcg121xglp,
3249 	}, {
3250 		.compatible = "lemaker,bl035-rgb-002",
3251 		.data = &lemaker_bl035_rgb_002,
3252 	}, {
3253 		.compatible = "lg,lb070wv8",
3254 		.data = &lg_lb070wv8,
3255 	}, {
3256 		.compatible = "lg,lp079qx1-sp0v",
3257 		.data = &lg_lp079qx1_sp0v,
3258 	}, {
3259 		.compatible = "lg,lp097qx1-spa1",
3260 		.data = &lg_lp097qx1_spa1,
3261 	}, {
3262 		.compatible = "lg,lp120up1",
3263 		.data = &lg_lp120up1,
3264 	}, {
3265 		.compatible = "lg,lp129qe",
3266 		.data = &lg_lp129qe,
3267 	}, {
3268 		.compatible = "mitsubishi,aa070mc01-ca1",
3269 		.data = &mitsubishi_aa070mc01,
3270 	}, {
3271 		.compatible = "nec,nl12880bc20-05",
3272 		.data = &nec_nl12880bc20_05,
3273 	}, {
3274 		.compatible = "nec,nl4827hc19-05b",
3275 		.data = &nec_nl4827hc19_05b,
3276 	}, {
3277 		.compatible = "netron-dy,e231732",
3278 		.data = &netron_dy_e231732,
3279 	}, {
3280 		.compatible = "newhaven,nhd-4.3-480272ef-atxl",
3281 		.data = &newhaven_nhd_43_480272ef_atxl,
3282 	}, {
3283 		.compatible = "nlt,nl192108ac18-02d",
3284 		.data = &nlt_nl192108ac18_02d,
3285 	}, {
3286 		.compatible = "nvd,9128",
3287 		.data = &nvd_9128,
3288 	}, {
3289 		.compatible = "okaya,rs800480t-7x0gp",
3290 		.data = &okaya_rs800480t_7x0gp,
3291 	}, {
3292 		.compatible = "olimex,lcd-olinuxino-43-ts",
3293 		.data = &olimex_lcd_olinuxino_43ts,
3294 	}, {
3295 		.compatible = "ontat,yx700wv03",
3296 		.data = &ontat_yx700wv03,
3297 	}, {
3298 		.compatible = "ortustech,com37h3m05dtc",
3299 		.data = &ortustech_com37h3m,
3300 	}, {
3301 		.compatible = "ortustech,com37h3m99dtc",
3302 		.data = &ortustech_com37h3m,
3303 	}, {
3304 		.compatible = "ortustech,com43h4m85ulc",
3305 		.data = &ortustech_com43h4m85ulc,
3306 	}, {
3307 		.compatible = "osddisplays,osd070t1718-19ts",
3308 		.data = &osddisplays_osd070t1718_19ts,
3309 	}, {
3310 		.compatible = "pda,91-00156-a0",
3311 		.data = &pda_91_00156_a0,
3312 	}, {
3313 		.compatible = "qiaodian,qd43003c0-40",
3314 		.data = &qd43003c0_40,
3315 	}, {
3316 		.compatible = "rocktech,rk070er9427",
3317 		.data = &rocktech_rk070er9427,
3318 	}, {
3319 		.compatible = "samsung,lsn122dl01-c01",
3320 		.data = &samsung_lsn122dl01_c01,
3321 	}, {
3322 		.compatible = "samsung,ltn101nt05",
3323 		.data = &samsung_ltn101nt05,
3324 	}, {
3325 		.compatible = "samsung,ltn140at29-301",
3326 		.data = &samsung_ltn140at29_301,
3327 	}, {
3328 		.compatible = "sharp,ld-d5116z01b",
3329 		.data = &sharp_ld_d5116z01b,
3330 	}, {
3331 		.compatible = "sharp,lq035q7db03",
3332 		.data = &sharp_lq035q7db03,
3333 	}, {
3334 		.compatible = "sharp,lq070y3dg3b",
3335 		.data = &sharp_lq070y3dg3b,
3336 	}, {
3337 		.compatible = "sharp,lq101k1ly04",
3338 		.data = &sharp_lq101k1ly04,
3339 	}, {
3340 		.compatible = "sharp,lq123p1jx31",
3341 		.data = &sharp_lq123p1jx31,
3342 	}, {
3343 		.compatible = "sharp,lq150x1lg11",
3344 		.data = &sharp_lq150x1lg11,
3345 	}, {
3346 		.compatible = "sharp,ls020b1dd01d",
3347 		.data = &sharp_ls020b1dd01d,
3348 	}, {
3349 		.compatible = "shelly,sca07010-bfn-lnn",
3350 		.data = &shelly_sca07010_bfn_lnn,
3351 	}, {
3352 		.compatible = "starry,kr122ea0sra",
3353 		.data = &starry_kr122ea0sra,
3354 	}, {
3355 		.compatible = "tfc,s9700rtwv43tr-01b",
3356 		.data = &tfc_s9700rtwv43tr_01b,
3357 	}, {
3358 		.compatible = "tianma,tm070jdhg30",
3359 		.data = &tianma_tm070jdhg30,
3360 	}, {
3361 		.compatible = "tianma,tm070rvhg71",
3362 		.data = &tianma_tm070rvhg71,
3363 	}, {
3364 		.compatible = "ti,nspire-cx-lcd-panel",
3365 		.data = &ti_nspire_cx_lcd_panel,
3366 	}, {
3367 		.compatible = "ti,nspire-classic-lcd-panel",
3368 		.data = &ti_nspire_classic_lcd_panel,
3369 	}, {
3370 		.compatible = "toshiba,lt089ac29000",
3371 		.data = &toshiba_lt089ac29000,
3372 	}, {
3373 		.compatible = "tpk,f07a-0102",
3374 		.data = &tpk_f07a_0102,
3375 	}, {
3376 		.compatible = "tpk,f10a-0102",
3377 		.data = &tpk_f10a_0102,
3378 	}, {
3379 		.compatible = "urt,umsh-8596md-t",
3380 		.data = &urt_umsh_8596md_parallel,
3381 	}, {
3382 		.compatible = "urt,umsh-8596md-1t",
3383 		.data = &urt_umsh_8596md_parallel,
3384 	}, {
3385 		.compatible = "urt,umsh-8596md-7t",
3386 		.data = &urt_umsh_8596md_parallel,
3387 	}, {
3388 		.compatible = "urt,umsh-8596md-11t",
3389 		.data = &urt_umsh_8596md_lvds,
3390 	}, {
3391 		.compatible = "urt,umsh-8596md-19t",
3392 		.data = &urt_umsh_8596md_lvds,
3393 	}, {
3394 		.compatible = "urt,umsh-8596md-20t",
3395 		.data = &urt_umsh_8596md_parallel,
3396 	}, {
3397 		.compatible = "vxt,vl050-8048nt-c01",
3398 		.data = &vl050_8048nt_c01,
3399 	}, {
3400 		.compatible = "winstar,wf35ltiacd",
3401 		.data = &winstar_wf35ltiacd,
3402 	}, {
3403 		/* sentinel */
3404 	}
3405 };
3406 MODULE_DEVICE_TABLE(of, platform_of_match);
3407 
3408 static int panel_simple_platform_probe(struct platform_device *pdev)
3409 {
3410 	const struct of_device_id *id;
3411 
3412 	id = of_match_node(platform_of_match, pdev->dev.of_node);
3413 	if (!id)
3414 		return -ENODEV;
3415 
3416 	return panel_simple_probe(&pdev->dev, id->data);
3417 }
3418 
3419 static int panel_simple_platform_remove(struct platform_device *pdev)
3420 {
3421 	return panel_simple_remove(&pdev->dev);
3422 }
3423 
3424 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3425 {
3426 	panel_simple_shutdown(&pdev->dev);
3427 }
3428 
3429 static struct platform_driver panel_simple_platform_driver = {
3430 	.driver = {
3431 		.name = "panel-simple",
3432 		.of_match_table = platform_of_match,
3433 	},
3434 	.probe = panel_simple_platform_probe,
3435 	.remove = panel_simple_platform_remove,
3436 	.shutdown = panel_simple_platform_shutdown,
3437 };
3438 
3439 struct panel_desc_dsi {
3440 	struct panel_desc desc;
3441 
3442 	unsigned long flags;
3443 	enum mipi_dsi_pixel_format format;
3444 	unsigned int lanes;
3445 };
3446 
3447 static const struct drm_display_mode auo_b080uan01_mode = {
3448 	.clock = 154500,
3449 	.hdisplay = 1200,
3450 	.hsync_start = 1200 + 62,
3451 	.hsync_end = 1200 + 62 + 4,
3452 	.htotal = 1200 + 62 + 4 + 62,
3453 	.vdisplay = 1920,
3454 	.vsync_start = 1920 + 9,
3455 	.vsync_end = 1920 + 9 + 2,
3456 	.vtotal = 1920 + 9 + 2 + 8,
3457 	.vrefresh = 60,
3458 };
3459 
3460 static const struct panel_desc_dsi auo_b080uan01 = {
3461 	.desc = {
3462 		.modes = &auo_b080uan01_mode,
3463 		.num_modes = 1,
3464 		.bpc = 8,
3465 		.size = {
3466 			.width = 108,
3467 			.height = 272,
3468 		},
3469 	},
3470 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3471 	.format = MIPI_DSI_FMT_RGB888,
3472 	.lanes = 4,
3473 };
3474 
3475 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3476 	.clock = 160000,
3477 	.hdisplay = 1200,
3478 	.hsync_start = 1200 + 120,
3479 	.hsync_end = 1200 + 120 + 20,
3480 	.htotal = 1200 + 120 + 20 + 21,
3481 	.vdisplay = 1920,
3482 	.vsync_start = 1920 + 21,
3483 	.vsync_end = 1920 + 21 + 3,
3484 	.vtotal = 1920 + 21 + 3 + 18,
3485 	.vrefresh = 60,
3486 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3487 };
3488 
3489 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3490 	.desc = {
3491 		.modes = &boe_tv080wum_nl0_mode,
3492 		.num_modes = 1,
3493 		.size = {
3494 			.width = 107,
3495 			.height = 172,
3496 		},
3497 	},
3498 	.flags = MIPI_DSI_MODE_VIDEO |
3499 		 MIPI_DSI_MODE_VIDEO_BURST |
3500 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3501 	.format = MIPI_DSI_FMT_RGB888,
3502 	.lanes = 4,
3503 };
3504 
3505 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3506 	.clock = 71000,
3507 	.hdisplay = 800,
3508 	.hsync_start = 800 + 32,
3509 	.hsync_end = 800 + 32 + 1,
3510 	.htotal = 800 + 32 + 1 + 57,
3511 	.vdisplay = 1280,
3512 	.vsync_start = 1280 + 28,
3513 	.vsync_end = 1280 + 28 + 1,
3514 	.vtotal = 1280 + 28 + 1 + 14,
3515 	.vrefresh = 60,
3516 };
3517 
3518 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3519 	.desc = {
3520 		.modes = &lg_ld070wx3_sl01_mode,
3521 		.num_modes = 1,
3522 		.bpc = 8,
3523 		.size = {
3524 			.width = 94,
3525 			.height = 151,
3526 		},
3527 	},
3528 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3529 	.format = MIPI_DSI_FMT_RGB888,
3530 	.lanes = 4,
3531 };
3532 
3533 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3534 	.clock = 67000,
3535 	.hdisplay = 720,
3536 	.hsync_start = 720 + 12,
3537 	.hsync_end = 720 + 12 + 4,
3538 	.htotal = 720 + 12 + 4 + 112,
3539 	.vdisplay = 1280,
3540 	.vsync_start = 1280 + 8,
3541 	.vsync_end = 1280 + 8 + 4,
3542 	.vtotal = 1280 + 8 + 4 + 12,
3543 	.vrefresh = 60,
3544 };
3545 
3546 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3547 	.desc = {
3548 		.modes = &lg_lh500wx1_sd03_mode,
3549 		.num_modes = 1,
3550 		.bpc = 8,
3551 		.size = {
3552 			.width = 62,
3553 			.height = 110,
3554 		},
3555 	},
3556 	.flags = MIPI_DSI_MODE_VIDEO,
3557 	.format = MIPI_DSI_FMT_RGB888,
3558 	.lanes = 4,
3559 };
3560 
3561 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3562 	.clock = 157200,
3563 	.hdisplay = 1920,
3564 	.hsync_start = 1920 + 154,
3565 	.hsync_end = 1920 + 154 + 16,
3566 	.htotal = 1920 + 154 + 16 + 32,
3567 	.vdisplay = 1200,
3568 	.vsync_start = 1200 + 17,
3569 	.vsync_end = 1200 + 17 + 2,
3570 	.vtotal = 1200 + 17 + 2 + 16,
3571 	.vrefresh = 60,
3572 };
3573 
3574 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3575 	.desc = {
3576 		.modes = &panasonic_vvx10f004b00_mode,
3577 		.num_modes = 1,
3578 		.bpc = 8,
3579 		.size = {
3580 			.width = 217,
3581 			.height = 136,
3582 		},
3583 	},
3584 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3585 		 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3586 	.format = MIPI_DSI_FMT_RGB888,
3587 	.lanes = 4,
3588 };
3589 
3590 static const struct drm_display_mode lg_acx467akm_7_mode = {
3591 	.clock = 150000,
3592 	.hdisplay = 1080,
3593 	.hsync_start = 1080 + 2,
3594 	.hsync_end = 1080 + 2 + 2,
3595 	.htotal = 1080 + 2 + 2 + 2,
3596 	.vdisplay = 1920,
3597 	.vsync_start = 1920 + 2,
3598 	.vsync_end = 1920 + 2 + 2,
3599 	.vtotal = 1920 + 2 + 2 + 2,
3600 	.vrefresh = 60,
3601 };
3602 
3603 static const struct panel_desc_dsi lg_acx467akm_7 = {
3604 	.desc = {
3605 		.modes = &lg_acx467akm_7_mode,
3606 		.num_modes = 1,
3607 		.bpc = 8,
3608 		.size = {
3609 			.width = 62,
3610 			.height = 110,
3611 		},
3612 	},
3613 	.flags = 0,
3614 	.format = MIPI_DSI_FMT_RGB888,
3615 	.lanes = 4,
3616 };
3617 
3618 static const struct drm_display_mode osd101t2045_53ts_mode = {
3619 	.clock = 154500,
3620 	.hdisplay = 1920,
3621 	.hsync_start = 1920 + 112,
3622 	.hsync_end = 1920 + 112 + 16,
3623 	.htotal = 1920 + 112 + 16 + 32,
3624 	.vdisplay = 1200,
3625 	.vsync_start = 1200 + 16,
3626 	.vsync_end = 1200 + 16 + 2,
3627 	.vtotal = 1200 + 16 + 2 + 16,
3628 	.vrefresh = 60,
3629 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3630 };
3631 
3632 static const struct panel_desc_dsi osd101t2045_53ts = {
3633 	.desc = {
3634 		.modes = &osd101t2045_53ts_mode,
3635 		.num_modes = 1,
3636 		.bpc = 8,
3637 		.size = {
3638 			.width = 217,
3639 			.height = 136,
3640 		},
3641 	},
3642 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3643 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3644 		 MIPI_DSI_MODE_EOT_PACKET,
3645 	.format = MIPI_DSI_FMT_RGB888,
3646 	.lanes = 4,
3647 };
3648 
3649 static const struct of_device_id dsi_of_match[] = {
3650 	{
3651 		.compatible = "auo,b080uan01",
3652 		.data = &auo_b080uan01
3653 	}, {
3654 		.compatible = "boe,tv080wum-nl0",
3655 		.data = &boe_tv080wum_nl0
3656 	}, {
3657 		.compatible = "lg,ld070wx3-sl01",
3658 		.data = &lg_ld070wx3_sl01
3659 	}, {
3660 		.compatible = "lg,lh500wx1-sd03",
3661 		.data = &lg_lh500wx1_sd03
3662 	}, {
3663 		.compatible = "panasonic,vvx10f004b00",
3664 		.data = &panasonic_vvx10f004b00
3665 	}, {
3666 		.compatible = "lg,acx467akm-7",
3667 		.data = &lg_acx467akm_7
3668 	}, {
3669 		.compatible = "osddisplays,osd101t2045-53ts",
3670 		.data = &osd101t2045_53ts
3671 	}, {
3672 		/* sentinel */
3673 	}
3674 };
3675 MODULE_DEVICE_TABLE(of, dsi_of_match);
3676 
3677 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3678 {
3679 	const struct panel_desc_dsi *desc;
3680 	const struct of_device_id *id;
3681 	int err;
3682 
3683 	id = of_match_node(dsi_of_match, dsi->dev.of_node);
3684 	if (!id)
3685 		return -ENODEV;
3686 
3687 	desc = id->data;
3688 
3689 	err = panel_simple_probe(&dsi->dev, &desc->desc);
3690 	if (err < 0)
3691 		return err;
3692 
3693 	dsi->mode_flags = desc->flags;
3694 	dsi->format = desc->format;
3695 	dsi->lanes = desc->lanes;
3696 
3697 	err = mipi_dsi_attach(dsi);
3698 	if (err) {
3699 		struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3700 
3701 		drm_panel_remove(&panel->base);
3702 	}
3703 
3704 	return err;
3705 }
3706 
3707 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3708 {
3709 	int err;
3710 
3711 	err = mipi_dsi_detach(dsi);
3712 	if (err < 0)
3713 		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3714 
3715 	return panel_simple_remove(&dsi->dev);
3716 }
3717 
3718 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3719 {
3720 	panel_simple_shutdown(&dsi->dev);
3721 }
3722 
3723 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3724 	.driver = {
3725 		.name = "panel-simple-dsi",
3726 		.of_match_table = dsi_of_match,
3727 	},
3728 	.probe = panel_simple_dsi_probe,
3729 	.remove = panel_simple_dsi_remove,
3730 	.shutdown = panel_simple_dsi_shutdown,
3731 };
3732 
3733 static int __init panel_simple_init(void)
3734 {
3735 	int err;
3736 
3737 	err = platform_driver_register(&panel_simple_platform_driver);
3738 	if (err < 0)
3739 		return err;
3740 
3741 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3742 		err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3743 		if (err < 0)
3744 			return err;
3745 	}
3746 
3747 	return 0;
3748 }
3749 module_init(panel_simple_init);
3750 
3751 static void __exit panel_simple_exit(void)
3752 {
3753 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3754 		mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3755 
3756 	platform_driver_unregister(&panel_simple_platform_driver);
3757 }
3758 module_exit(panel_simple_exit);
3759 
3760 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3761 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3762 MODULE_LICENSE("GPL and additional rights");
3763