1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <video/display_timing.h> 32 #include <video/of_display_timing.h> 33 #include <video/videomode.h> 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_device.h> 37 #include <drm/drm_mipi_dsi.h> 38 #include <drm/drm_panel.h> 39 40 /** 41 * @modes: Pointer to array of fixed modes appropriate for this panel. If 42 * only one mode then this can just be the address of this the mode. 43 * NOTE: cannot be used with "timings" and also if this is specified 44 * then you cannot override the mode in the device tree. 45 * @num_modes: Number of elements in modes array. 46 * @timings: Pointer to array of display timings. NOTE: cannot be used with 47 * "modes" and also these will be used to validate a device tree 48 * override if one is present. 49 * @num_timings: Number of elements in timings array. 50 * @bpc: Bits per color. 51 * @size: Structure containing the physical size of this panel. 52 * @delay: Structure containing various delay values for this panel. 53 * @bus_format: See MEDIA_BUS_FMT_... defines. 54 * @bus_flags: See DRM_BUS_FLAG_... defines. 55 */ 56 struct panel_desc { 57 const struct drm_display_mode *modes; 58 unsigned int num_modes; 59 const struct display_timing *timings; 60 unsigned int num_timings; 61 62 unsigned int bpc; 63 64 /** 65 * @width: width (in millimeters) of the panel's active display area 66 * @height: height (in millimeters) of the panel's active display area 67 */ 68 struct { 69 unsigned int width; 70 unsigned int height; 71 } size; 72 73 /** 74 * @prepare: the time (in milliseconds) that it takes for the panel to 75 * become ready and start receiving video data 76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 77 * Plug Detect isn't used. 78 * @enable: the time (in milliseconds) that it takes for the panel to 79 * display the first valid frame after starting to receive 80 * video data 81 * @disable: the time (in milliseconds) that it takes for the panel to 82 * turn the display off (no content is visible) 83 * @unprepare: the time (in milliseconds) that it takes for the panel 84 * to power itself down completely 85 */ 86 struct { 87 unsigned int prepare; 88 unsigned int hpd_absent_delay; 89 unsigned int enable; 90 unsigned int disable; 91 unsigned int unprepare; 92 } delay; 93 94 u32 bus_format; 95 u32 bus_flags; 96 int connector_type; 97 }; 98 99 struct panel_simple { 100 struct drm_panel base; 101 bool prepared; 102 bool enabled; 103 bool no_hpd; 104 105 const struct panel_desc *desc; 106 107 struct regulator *supply; 108 struct i2c_adapter *ddc; 109 110 struct gpio_desc *enable_gpio; 111 112 struct drm_display_mode override_mode; 113 }; 114 115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 116 { 117 return container_of(panel, struct panel_simple, base); 118 } 119 120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 121 struct drm_connector *connector) 122 { 123 struct drm_display_mode *mode; 124 unsigned int i, num = 0; 125 126 for (i = 0; i < panel->desc->num_timings; i++) { 127 const struct display_timing *dt = &panel->desc->timings[i]; 128 struct videomode vm; 129 130 videomode_from_timing(dt, &vm); 131 mode = drm_mode_create(connector->dev); 132 if (!mode) { 133 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 134 dt->hactive.typ, dt->vactive.typ); 135 continue; 136 } 137 138 drm_display_mode_from_videomode(&vm, mode); 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_timings == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_probed_add(connector, mode); 146 num++; 147 } 148 149 return num; 150 } 151 152 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 153 struct drm_connector *connector) 154 { 155 struct drm_display_mode *mode; 156 unsigned int i, num = 0; 157 158 for (i = 0; i < panel->desc->num_modes; i++) { 159 const struct drm_display_mode *m = &panel->desc->modes[i]; 160 161 mode = drm_mode_duplicate(connector->dev, m); 162 if (!mode) { 163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 164 m->hdisplay, m->vdisplay, m->vrefresh); 165 continue; 166 } 167 168 mode->type |= DRM_MODE_TYPE_DRIVER; 169 170 if (panel->desc->num_modes == 1) 171 mode->type |= DRM_MODE_TYPE_PREFERRED; 172 173 drm_mode_set_name(mode); 174 175 drm_mode_probed_add(connector, mode); 176 num++; 177 } 178 179 return num; 180 } 181 182 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 183 struct drm_connector *connector) 184 { 185 struct drm_display_mode *mode; 186 bool has_override = panel->override_mode.type; 187 unsigned int num = 0; 188 189 if (!panel->desc) 190 return 0; 191 192 if (has_override) { 193 mode = drm_mode_duplicate(connector->dev, 194 &panel->override_mode); 195 if (mode) { 196 drm_mode_probed_add(connector, mode); 197 num = 1; 198 } else { 199 dev_err(panel->base.dev, "failed to add override mode\n"); 200 } 201 } 202 203 /* Only add timings if override was not there or failed to validate */ 204 if (num == 0 && panel->desc->num_timings) 205 num = panel_simple_get_timings_modes(panel, connector); 206 207 /* 208 * Only add fixed modes if timings/override added no mode. 209 * 210 * We should only ever have either the display timings specified 211 * or a fixed mode. Anything else is rather bogus. 212 */ 213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 214 if (num == 0) 215 num = panel_simple_get_display_modes(panel, connector); 216 217 connector->display_info.bpc = panel->desc->bpc; 218 connector->display_info.width_mm = panel->desc->size.width; 219 connector->display_info.height_mm = panel->desc->size.height; 220 if (panel->desc->bus_format) 221 drm_display_info_set_bus_formats(&connector->display_info, 222 &panel->desc->bus_format, 1); 223 connector->display_info.bus_flags = panel->desc->bus_flags; 224 225 return num; 226 } 227 228 static int panel_simple_disable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (!p->enabled) 233 return 0; 234 235 if (p->desc->delay.disable) 236 msleep(p->desc->delay.disable); 237 238 p->enabled = false; 239 240 return 0; 241 } 242 243 static int panel_simple_unprepare(struct drm_panel *panel) 244 { 245 struct panel_simple *p = to_panel_simple(panel); 246 247 if (!p->prepared) 248 return 0; 249 250 gpiod_set_value_cansleep(p->enable_gpio, 0); 251 252 regulator_disable(p->supply); 253 254 if (p->desc->delay.unprepare) 255 msleep(p->desc->delay.unprepare); 256 257 p->prepared = false; 258 259 return 0; 260 } 261 262 static int panel_simple_prepare(struct drm_panel *panel) 263 { 264 struct panel_simple *p = to_panel_simple(panel); 265 unsigned int delay; 266 int err; 267 268 if (p->prepared) 269 return 0; 270 271 err = regulator_enable(p->supply); 272 if (err < 0) { 273 dev_err(panel->dev, "failed to enable supply: %d\n", err); 274 return err; 275 } 276 277 gpiod_set_value_cansleep(p->enable_gpio, 1); 278 279 delay = p->desc->delay.prepare; 280 if (p->no_hpd) 281 delay += p->desc->delay.hpd_absent_delay; 282 if (delay) 283 msleep(delay); 284 285 p->prepared = true; 286 287 return 0; 288 } 289 290 static int panel_simple_enable(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 294 if (p->enabled) 295 return 0; 296 297 if (p->desc->delay.enable) 298 msleep(p->desc->delay.enable); 299 300 p->enabled = true; 301 302 return 0; 303 } 304 305 static int panel_simple_get_modes(struct drm_panel *panel, 306 struct drm_connector *connector) 307 { 308 struct panel_simple *p = to_panel_simple(panel); 309 int num = 0; 310 311 /* probe EDID if a DDC bus is available */ 312 if (p->ddc) { 313 struct edid *edid = drm_get_edid(connector, p->ddc); 314 315 drm_connector_update_edid_property(connector, edid); 316 if (edid) { 317 num += drm_add_edid_modes(connector, edid); 318 kfree(edid); 319 } 320 } 321 322 /* add hard-coded panel modes */ 323 num += panel_simple_get_non_edid_modes(p, connector); 324 325 return num; 326 } 327 328 static int panel_simple_get_timings(struct drm_panel *panel, 329 unsigned int num_timings, 330 struct display_timing *timings) 331 { 332 struct panel_simple *p = to_panel_simple(panel); 333 unsigned int i; 334 335 if (p->desc->num_timings < num_timings) 336 num_timings = p->desc->num_timings; 337 338 if (timings) 339 for (i = 0; i < num_timings; i++) 340 timings[i] = p->desc->timings[i]; 341 342 return p->desc->num_timings; 343 } 344 345 static const struct drm_panel_funcs panel_simple_funcs = { 346 .disable = panel_simple_disable, 347 .unprepare = panel_simple_unprepare, 348 .prepare = panel_simple_prepare, 349 .enable = panel_simple_enable, 350 .get_modes = panel_simple_get_modes, 351 .get_timings = panel_simple_get_timings, 352 }; 353 354 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 355 (to_check->field.typ >= bounds->field.min && \ 356 to_check->field.typ <= bounds->field.max) 357 static void panel_simple_parse_panel_timing_node(struct device *dev, 358 struct panel_simple *panel, 359 const struct display_timing *ot) 360 { 361 const struct panel_desc *desc = panel->desc; 362 struct videomode vm; 363 unsigned int i; 364 365 if (WARN_ON(desc->num_modes)) { 366 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 367 return; 368 } 369 if (WARN_ON(!desc->num_timings)) { 370 dev_err(dev, "Reject override mode: no timings specified\n"); 371 return; 372 } 373 374 for (i = 0; i < panel->desc->num_timings; i++) { 375 const struct display_timing *dt = &panel->desc->timings[i]; 376 377 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 378 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 379 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 385 continue; 386 387 if (ot->flags != dt->flags) 388 continue; 389 390 videomode_from_timing(ot, &vm); 391 drm_display_mode_from_videomode(&vm, &panel->override_mode); 392 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 393 DRM_MODE_TYPE_PREFERRED; 394 break; 395 } 396 397 if (WARN_ON(!panel->override_mode.type)) 398 dev_err(dev, "Reject override mode: No display_timing found\n"); 399 } 400 401 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 402 { 403 struct panel_simple *panel; 404 struct display_timing dt; 405 struct device_node *ddc; 406 int err; 407 408 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 409 if (!panel) 410 return -ENOMEM; 411 412 panel->enabled = false; 413 panel->prepared = false; 414 panel->desc = desc; 415 416 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 417 418 panel->supply = devm_regulator_get(dev, "power"); 419 if (IS_ERR(panel->supply)) 420 return PTR_ERR(panel->supply); 421 422 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 423 GPIOD_OUT_LOW); 424 if (IS_ERR(panel->enable_gpio)) { 425 err = PTR_ERR(panel->enable_gpio); 426 if (err != -EPROBE_DEFER) 427 dev_err(dev, "failed to request GPIO: %d\n", err); 428 return err; 429 } 430 431 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 432 if (ddc) { 433 panel->ddc = of_find_i2c_adapter_by_node(ddc); 434 of_node_put(ddc); 435 436 if (!panel->ddc) 437 return -EPROBE_DEFER; 438 } 439 440 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 441 panel_simple_parse_panel_timing_node(dev, panel, &dt); 442 443 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 444 desc->connector_type); 445 446 err = drm_panel_of_backlight(&panel->base); 447 if (err) 448 goto free_ddc; 449 450 err = drm_panel_add(&panel->base); 451 if (err < 0) 452 goto free_ddc; 453 454 dev_set_drvdata(dev, panel); 455 456 return 0; 457 458 free_ddc: 459 if (panel->ddc) 460 put_device(&panel->ddc->dev); 461 462 return err; 463 } 464 465 static int panel_simple_remove(struct device *dev) 466 { 467 struct panel_simple *panel = dev_get_drvdata(dev); 468 469 drm_panel_remove(&panel->base); 470 drm_panel_disable(&panel->base); 471 drm_panel_unprepare(&panel->base); 472 473 if (panel->ddc) 474 put_device(&panel->ddc->dev); 475 476 return 0; 477 } 478 479 static void panel_simple_shutdown(struct device *dev) 480 { 481 struct panel_simple *panel = dev_get_drvdata(dev); 482 483 drm_panel_disable(&panel->base); 484 drm_panel_unprepare(&panel->base); 485 } 486 487 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 488 .clock = 9000, 489 .hdisplay = 480, 490 .hsync_start = 480 + 2, 491 .hsync_end = 480 + 2 + 41, 492 .htotal = 480 + 2 + 41 + 2, 493 .vdisplay = 272, 494 .vsync_start = 272 + 2, 495 .vsync_end = 272 + 2 + 10, 496 .vtotal = 272 + 2 + 10 + 2, 497 .vrefresh = 60, 498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 499 }; 500 501 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 502 .modes = &ire_am_480272h3tmqw_t01h_mode, 503 .num_modes = 1, 504 .bpc = 8, 505 .size = { 506 .width = 105, 507 .height = 67, 508 }, 509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 510 }; 511 512 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 513 .clock = 33333, 514 .hdisplay = 800, 515 .hsync_start = 800 + 0, 516 .hsync_end = 800 + 0 + 255, 517 .htotal = 800 + 0 + 255 + 0, 518 .vdisplay = 480, 519 .vsync_start = 480 + 2, 520 .vsync_end = 480 + 2 + 45, 521 .vtotal = 480 + 2 + 45 + 0, 522 .vrefresh = 60, 523 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 524 }; 525 526 static const struct panel_desc ampire_am800480r3tmqwa1h = { 527 .modes = &ire_am800480r3tmqwa1h_mode, 528 .num_modes = 1, 529 .bpc = 6, 530 .size = { 531 .width = 152, 532 .height = 91, 533 }, 534 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 535 }; 536 537 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 538 .pixelclock = { 26400000, 33300000, 46800000 }, 539 .hactive = { 800, 800, 800 }, 540 .hfront_porch = { 16, 210, 354 }, 541 .hback_porch = { 45, 36, 6 }, 542 .hsync_len = { 1, 10, 40 }, 543 .vactive = { 480, 480, 480 }, 544 .vfront_porch = { 7, 22, 147 }, 545 .vback_porch = { 22, 13, 3 }, 546 .vsync_len = { 1, 10, 20 }, 547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 548 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 549 }; 550 551 static const struct panel_desc armadeus_st0700_adapt = { 552 .timings = &santek_st0700i5y_rbslw_f_timing, 553 .num_timings = 1, 554 .bpc = 6, 555 .size = { 556 .width = 154, 557 .height = 86, 558 }, 559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 561 }; 562 563 static const struct drm_display_mode auo_b101aw03_mode = { 564 .clock = 51450, 565 .hdisplay = 1024, 566 .hsync_start = 1024 + 156, 567 .hsync_end = 1024 + 156 + 8, 568 .htotal = 1024 + 156 + 8 + 156, 569 .vdisplay = 600, 570 .vsync_start = 600 + 16, 571 .vsync_end = 600 + 16 + 6, 572 .vtotal = 600 + 16 + 6 + 16, 573 .vrefresh = 60, 574 }; 575 576 static const struct panel_desc auo_b101aw03 = { 577 .modes = &auo_b101aw03_mode, 578 .num_modes = 1, 579 .bpc = 6, 580 .size = { 581 .width = 223, 582 .height = 125, 583 }, 584 }; 585 586 static const struct display_timing auo_b101ean01_timing = { 587 .pixelclock = { 65300000, 72500000, 75000000 }, 588 .hactive = { 1280, 1280, 1280 }, 589 .hfront_porch = { 18, 119, 119 }, 590 .hback_porch = { 21, 21, 21 }, 591 .hsync_len = { 32, 32, 32 }, 592 .vactive = { 800, 800, 800 }, 593 .vfront_porch = { 4, 4, 4 }, 594 .vback_porch = { 8, 8, 8 }, 595 .vsync_len = { 18, 20, 20 }, 596 }; 597 598 static const struct panel_desc auo_b101ean01 = { 599 .timings = &auo_b101ean01_timing, 600 .num_timings = 1, 601 .bpc = 6, 602 .size = { 603 .width = 217, 604 .height = 136, 605 }, 606 }; 607 608 static const struct drm_display_mode auo_b101xtn01_mode = { 609 .clock = 72000, 610 .hdisplay = 1366, 611 .hsync_start = 1366 + 20, 612 .hsync_end = 1366 + 20 + 70, 613 .htotal = 1366 + 20 + 70, 614 .vdisplay = 768, 615 .vsync_start = 768 + 14, 616 .vsync_end = 768 + 14 + 42, 617 .vtotal = 768 + 14 + 42, 618 .vrefresh = 60, 619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 620 }; 621 622 static const struct panel_desc auo_b101xtn01 = { 623 .modes = &auo_b101xtn01_mode, 624 .num_modes = 1, 625 .bpc = 6, 626 .size = { 627 .width = 223, 628 .height = 125, 629 }, 630 }; 631 632 static const struct drm_display_mode auo_b116xak01_mode = { 633 .clock = 69300, 634 .hdisplay = 1366, 635 .hsync_start = 1366 + 48, 636 .hsync_end = 1366 + 48 + 32, 637 .htotal = 1366 + 48 + 32 + 10, 638 .vdisplay = 768, 639 .vsync_start = 768 + 4, 640 .vsync_end = 768 + 4 + 6, 641 .vtotal = 768 + 4 + 6 + 15, 642 .vrefresh = 60, 643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 644 }; 645 646 static const struct panel_desc auo_b116xak01 = { 647 .modes = &auo_b116xak01_mode, 648 .num_modes = 1, 649 .bpc = 6, 650 .size = { 651 .width = 256, 652 .height = 144, 653 }, 654 .delay = { 655 .hpd_absent_delay = 200, 656 }, 657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 658 .connector_type = DRM_MODE_CONNECTOR_eDP, 659 }; 660 661 static const struct drm_display_mode auo_b116xw03_mode = { 662 .clock = 70589, 663 .hdisplay = 1366, 664 .hsync_start = 1366 + 40, 665 .hsync_end = 1366 + 40 + 40, 666 .htotal = 1366 + 40 + 40 + 32, 667 .vdisplay = 768, 668 .vsync_start = 768 + 10, 669 .vsync_end = 768 + 10 + 12, 670 .vtotal = 768 + 10 + 12 + 6, 671 .vrefresh = 60, 672 }; 673 674 static const struct panel_desc auo_b116xw03 = { 675 .modes = &auo_b116xw03_mode, 676 .num_modes = 1, 677 .bpc = 6, 678 .size = { 679 .width = 256, 680 .height = 144, 681 }, 682 }; 683 684 static const struct drm_display_mode auo_b133xtn01_mode = { 685 .clock = 69500, 686 .hdisplay = 1366, 687 .hsync_start = 1366 + 48, 688 .hsync_end = 1366 + 48 + 32, 689 .htotal = 1366 + 48 + 32 + 20, 690 .vdisplay = 768, 691 .vsync_start = 768 + 3, 692 .vsync_end = 768 + 3 + 6, 693 .vtotal = 768 + 3 + 6 + 13, 694 .vrefresh = 60, 695 }; 696 697 static const struct panel_desc auo_b133xtn01 = { 698 .modes = &auo_b133xtn01_mode, 699 .num_modes = 1, 700 .bpc = 6, 701 .size = { 702 .width = 293, 703 .height = 165, 704 }, 705 }; 706 707 static const struct drm_display_mode auo_b133htn01_mode = { 708 .clock = 150660, 709 .hdisplay = 1920, 710 .hsync_start = 1920 + 172, 711 .hsync_end = 1920 + 172 + 80, 712 .htotal = 1920 + 172 + 80 + 60, 713 .vdisplay = 1080, 714 .vsync_start = 1080 + 25, 715 .vsync_end = 1080 + 25 + 10, 716 .vtotal = 1080 + 25 + 10 + 10, 717 .vrefresh = 60, 718 }; 719 720 static const struct panel_desc auo_b133htn01 = { 721 .modes = &auo_b133htn01_mode, 722 .num_modes = 1, 723 .bpc = 6, 724 .size = { 725 .width = 293, 726 .height = 165, 727 }, 728 .delay = { 729 .prepare = 105, 730 .enable = 20, 731 .unprepare = 50, 732 }, 733 }; 734 735 static const struct display_timing auo_g070vvn01_timings = { 736 .pixelclock = { 33300000, 34209000, 45000000 }, 737 .hactive = { 800, 800, 800 }, 738 .hfront_porch = { 20, 40, 200 }, 739 .hback_porch = { 87, 40, 1 }, 740 .hsync_len = { 1, 48, 87 }, 741 .vactive = { 480, 480, 480 }, 742 .vfront_porch = { 5, 13, 200 }, 743 .vback_porch = { 31, 31, 29 }, 744 .vsync_len = { 1, 1, 3 }, 745 }; 746 747 static const struct panel_desc auo_g070vvn01 = { 748 .timings = &auo_g070vvn01_timings, 749 .num_timings = 1, 750 .bpc = 8, 751 .size = { 752 .width = 152, 753 .height = 91, 754 }, 755 .delay = { 756 .prepare = 200, 757 .enable = 50, 758 .disable = 50, 759 .unprepare = 1000, 760 }, 761 }; 762 763 static const struct drm_display_mode auo_g101evn010_mode = { 764 .clock = 68930, 765 .hdisplay = 1280, 766 .hsync_start = 1280 + 82, 767 .hsync_end = 1280 + 82 + 2, 768 .htotal = 1280 + 82 + 2 + 84, 769 .vdisplay = 800, 770 .vsync_start = 800 + 8, 771 .vsync_end = 800 + 8 + 2, 772 .vtotal = 800 + 8 + 2 + 6, 773 .vrefresh = 60, 774 }; 775 776 static const struct panel_desc auo_g101evn010 = { 777 .modes = &auo_g101evn010_mode, 778 .num_modes = 1, 779 .bpc = 6, 780 .size = { 781 .width = 216, 782 .height = 135, 783 }, 784 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 785 }; 786 787 static const struct drm_display_mode auo_g104sn02_mode = { 788 .clock = 40000, 789 .hdisplay = 800, 790 .hsync_start = 800 + 40, 791 .hsync_end = 800 + 40 + 216, 792 .htotal = 800 + 40 + 216 + 128, 793 .vdisplay = 600, 794 .vsync_start = 600 + 10, 795 .vsync_end = 600 + 10 + 35, 796 .vtotal = 600 + 10 + 35 + 2, 797 .vrefresh = 60, 798 }; 799 800 static const struct panel_desc auo_g104sn02 = { 801 .modes = &auo_g104sn02_mode, 802 .num_modes = 1, 803 .bpc = 8, 804 .size = { 805 .width = 211, 806 .height = 158, 807 }, 808 }; 809 810 static const struct display_timing auo_g133han01_timings = { 811 .pixelclock = { 134000000, 141200000, 149000000 }, 812 .hactive = { 1920, 1920, 1920 }, 813 .hfront_porch = { 39, 58, 77 }, 814 .hback_porch = { 59, 88, 117 }, 815 .hsync_len = { 28, 42, 56 }, 816 .vactive = { 1080, 1080, 1080 }, 817 .vfront_porch = { 3, 8, 11 }, 818 .vback_porch = { 5, 14, 19 }, 819 .vsync_len = { 4, 14, 19 }, 820 }; 821 822 static const struct panel_desc auo_g133han01 = { 823 .timings = &auo_g133han01_timings, 824 .num_timings = 1, 825 .bpc = 8, 826 .size = { 827 .width = 293, 828 .height = 165, 829 }, 830 .delay = { 831 .prepare = 200, 832 .enable = 50, 833 .disable = 50, 834 .unprepare = 1000, 835 }, 836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 837 .connector_type = DRM_MODE_CONNECTOR_LVDS, 838 }; 839 840 static const struct display_timing auo_g185han01_timings = { 841 .pixelclock = { 120000000, 144000000, 175000000 }, 842 .hactive = { 1920, 1920, 1920 }, 843 .hfront_porch = { 36, 120, 148 }, 844 .hback_porch = { 24, 88, 108 }, 845 .hsync_len = { 20, 48, 64 }, 846 .vactive = { 1080, 1080, 1080 }, 847 .vfront_porch = { 6, 10, 40 }, 848 .vback_porch = { 2, 5, 20 }, 849 .vsync_len = { 2, 5, 20 }, 850 }; 851 852 static const struct panel_desc auo_g185han01 = { 853 .timings = &auo_g185han01_timings, 854 .num_timings = 1, 855 .bpc = 8, 856 .size = { 857 .width = 409, 858 .height = 230, 859 }, 860 .delay = { 861 .prepare = 50, 862 .enable = 200, 863 .disable = 110, 864 .unprepare = 1000, 865 }, 866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 868 }; 869 870 static const struct display_timing auo_p320hvn03_timings = { 871 .pixelclock = { 106000000, 148500000, 164000000 }, 872 .hactive = { 1920, 1920, 1920 }, 873 .hfront_porch = { 25, 50, 130 }, 874 .hback_porch = { 25, 50, 130 }, 875 .hsync_len = { 20, 40, 105 }, 876 .vactive = { 1080, 1080, 1080 }, 877 .vfront_porch = { 8, 17, 150 }, 878 .vback_porch = { 8, 17, 150 }, 879 .vsync_len = { 4, 11, 100 }, 880 }; 881 882 static const struct panel_desc auo_p320hvn03 = { 883 .timings = &auo_p320hvn03_timings, 884 .num_timings = 1, 885 .bpc = 8, 886 .size = { 887 .width = 698, 888 .height = 393, 889 }, 890 .delay = { 891 .prepare = 1, 892 .enable = 450, 893 .unprepare = 500, 894 }, 895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897 }; 898 899 static const struct drm_display_mode auo_t215hvn01_mode = { 900 .clock = 148800, 901 .hdisplay = 1920, 902 .hsync_start = 1920 + 88, 903 .hsync_end = 1920 + 88 + 44, 904 .htotal = 1920 + 88 + 44 + 148, 905 .vdisplay = 1080, 906 .vsync_start = 1080 + 4, 907 .vsync_end = 1080 + 4 + 5, 908 .vtotal = 1080 + 4 + 5 + 36, 909 .vrefresh = 60, 910 }; 911 912 static const struct panel_desc auo_t215hvn01 = { 913 .modes = &auo_t215hvn01_mode, 914 .num_modes = 1, 915 .bpc = 8, 916 .size = { 917 .width = 430, 918 .height = 270, 919 }, 920 .delay = { 921 .disable = 5, 922 .unprepare = 1000, 923 } 924 }; 925 926 static const struct drm_display_mode avic_tm070ddh03_mode = { 927 .clock = 51200, 928 .hdisplay = 1024, 929 .hsync_start = 1024 + 160, 930 .hsync_end = 1024 + 160 + 4, 931 .htotal = 1024 + 160 + 4 + 156, 932 .vdisplay = 600, 933 .vsync_start = 600 + 17, 934 .vsync_end = 600 + 17 + 1, 935 .vtotal = 600 + 17 + 1 + 17, 936 .vrefresh = 60, 937 }; 938 939 static const struct panel_desc avic_tm070ddh03 = { 940 .modes = &avic_tm070ddh03_mode, 941 .num_modes = 1, 942 .bpc = 8, 943 .size = { 944 .width = 154, 945 .height = 90, 946 }, 947 .delay = { 948 .prepare = 20, 949 .enable = 200, 950 .disable = 200, 951 }, 952 }; 953 954 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 955 .clock = 30000, 956 .hdisplay = 800, 957 .hsync_start = 800 + 40, 958 .hsync_end = 800 + 40 + 48, 959 .htotal = 800 + 40 + 48 + 40, 960 .vdisplay = 480, 961 .vsync_start = 480 + 13, 962 .vsync_end = 480 + 13 + 3, 963 .vtotal = 480 + 13 + 3 + 29, 964 }; 965 966 static const struct panel_desc bananapi_s070wv20_ct16 = { 967 .modes = &bananapi_s070wv20_ct16_mode, 968 .num_modes = 1, 969 .bpc = 6, 970 .size = { 971 .width = 154, 972 .height = 86, 973 }, 974 }; 975 976 static const struct drm_display_mode boe_hv070wsa_mode = { 977 .clock = 42105, 978 .hdisplay = 1024, 979 .hsync_start = 1024 + 30, 980 .hsync_end = 1024 + 30 + 30, 981 .htotal = 1024 + 30 + 30 + 30, 982 .vdisplay = 600, 983 .vsync_start = 600 + 10, 984 .vsync_end = 600 + 10 + 10, 985 .vtotal = 600 + 10 + 10 + 10, 986 .vrefresh = 60, 987 }; 988 989 static const struct panel_desc boe_hv070wsa = { 990 .modes = &boe_hv070wsa_mode, 991 .num_modes = 1, 992 .size = { 993 .width = 154, 994 .height = 90, 995 }, 996 }; 997 998 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 999 { 1000 .clock = 71900, 1001 .hdisplay = 1280, 1002 .hsync_start = 1280 + 48, 1003 .hsync_end = 1280 + 48 + 32, 1004 .htotal = 1280 + 48 + 32 + 80, 1005 .vdisplay = 800, 1006 .vsync_start = 800 + 3, 1007 .vsync_end = 800 + 3 + 5, 1008 .vtotal = 800 + 3 + 5 + 24, 1009 .vrefresh = 60, 1010 }, 1011 { 1012 .clock = 57500, 1013 .hdisplay = 1280, 1014 .hsync_start = 1280 + 48, 1015 .hsync_end = 1280 + 48 + 32, 1016 .htotal = 1280 + 48 + 32 + 80, 1017 .vdisplay = 800, 1018 .vsync_start = 800 + 3, 1019 .vsync_end = 800 + 3 + 5, 1020 .vtotal = 800 + 3 + 5 + 24, 1021 .vrefresh = 48, 1022 }, 1023 }; 1024 1025 static const struct panel_desc boe_nv101wxmn51 = { 1026 .modes = boe_nv101wxmn51_modes, 1027 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1028 .bpc = 8, 1029 .size = { 1030 .width = 217, 1031 .height = 136, 1032 }, 1033 .delay = { 1034 .prepare = 210, 1035 .enable = 50, 1036 .unprepare = 160, 1037 }, 1038 }; 1039 1040 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1041 { 1042 .clock = 148500, 1043 .hdisplay = 1920, 1044 .hsync_start = 1920 + 48, 1045 .hsync_end = 1920 + 48 + 32, 1046 .htotal = 2200, 1047 .vdisplay = 1080, 1048 .vsync_start = 1080 + 3, 1049 .vsync_end = 1080 + 3 + 5, 1050 .vtotal = 1125, 1051 .vrefresh = 60, 1052 }, 1053 }; 1054 1055 static const struct panel_desc boe_nv140fhmn49 = { 1056 .modes = boe_nv140fhmn49_modes, 1057 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1058 .bpc = 6, 1059 .size = { 1060 .width = 309, 1061 .height = 174, 1062 }, 1063 .delay = { 1064 .prepare = 210, 1065 .enable = 50, 1066 .unprepare = 160, 1067 }, 1068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1069 .connector_type = DRM_MODE_CONNECTOR_eDP, 1070 }; 1071 1072 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1073 .clock = 9000, 1074 .hdisplay = 480, 1075 .hsync_start = 480 + 5, 1076 .hsync_end = 480 + 5 + 5, 1077 .htotal = 480 + 5 + 5 + 40, 1078 .vdisplay = 272, 1079 .vsync_start = 272 + 8, 1080 .vsync_end = 272 + 8 + 8, 1081 .vtotal = 272 + 8 + 8 + 8, 1082 .vrefresh = 60, 1083 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1084 }; 1085 1086 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1087 .modes = &cdtech_s043wq26h_ct7_mode, 1088 .num_modes = 1, 1089 .bpc = 8, 1090 .size = { 1091 .width = 95, 1092 .height = 54, 1093 }, 1094 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1095 }; 1096 1097 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1098 .clock = 35000, 1099 .hdisplay = 800, 1100 .hsync_start = 800 + 40, 1101 .hsync_end = 800 + 40 + 40, 1102 .htotal = 800 + 40 + 40 + 48, 1103 .vdisplay = 480, 1104 .vsync_start = 480 + 29, 1105 .vsync_end = 480 + 29 + 13, 1106 .vtotal = 480 + 29 + 13 + 3, 1107 .vrefresh = 60, 1108 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1109 }; 1110 1111 static const struct panel_desc cdtech_s070wv95_ct16 = { 1112 .modes = &cdtech_s070wv95_ct16_mode, 1113 .num_modes = 1, 1114 .bpc = 8, 1115 .size = { 1116 .width = 154, 1117 .height = 85, 1118 }, 1119 }; 1120 1121 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1122 .clock = 66770, 1123 .hdisplay = 800, 1124 .hsync_start = 800 + 49, 1125 .hsync_end = 800 + 49 + 33, 1126 .htotal = 800 + 49 + 33 + 17, 1127 .vdisplay = 1280, 1128 .vsync_start = 1280 + 1, 1129 .vsync_end = 1280 + 1 + 7, 1130 .vtotal = 1280 + 1 + 7 + 15, 1131 .vrefresh = 60, 1132 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1133 }; 1134 1135 static const struct panel_desc chunghwa_claa070wp03xg = { 1136 .modes = &chunghwa_claa070wp03xg_mode, 1137 .num_modes = 1, 1138 .bpc = 6, 1139 .size = { 1140 .width = 94, 1141 .height = 150, 1142 }, 1143 }; 1144 1145 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1146 .clock = 72070, 1147 .hdisplay = 1366, 1148 .hsync_start = 1366 + 58, 1149 .hsync_end = 1366 + 58 + 58, 1150 .htotal = 1366 + 58 + 58 + 58, 1151 .vdisplay = 768, 1152 .vsync_start = 768 + 4, 1153 .vsync_end = 768 + 4 + 4, 1154 .vtotal = 768 + 4 + 4 + 4, 1155 .vrefresh = 60, 1156 }; 1157 1158 static const struct panel_desc chunghwa_claa101wa01a = { 1159 .modes = &chunghwa_claa101wa01a_mode, 1160 .num_modes = 1, 1161 .bpc = 6, 1162 .size = { 1163 .width = 220, 1164 .height = 120, 1165 }, 1166 }; 1167 1168 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1169 .clock = 69300, 1170 .hdisplay = 1366, 1171 .hsync_start = 1366 + 48, 1172 .hsync_end = 1366 + 48 + 32, 1173 .htotal = 1366 + 48 + 32 + 20, 1174 .vdisplay = 768, 1175 .vsync_start = 768 + 16, 1176 .vsync_end = 768 + 16 + 8, 1177 .vtotal = 768 + 16 + 8 + 16, 1178 .vrefresh = 60, 1179 }; 1180 1181 static const struct panel_desc chunghwa_claa101wb01 = { 1182 .modes = &chunghwa_claa101wb01_mode, 1183 .num_modes = 1, 1184 .bpc = 6, 1185 .size = { 1186 .width = 223, 1187 .height = 125, 1188 }, 1189 }; 1190 1191 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1192 .clock = 33260, 1193 .hdisplay = 800, 1194 .hsync_start = 800 + 40, 1195 .hsync_end = 800 + 40 + 128, 1196 .htotal = 800 + 40 + 128 + 88, 1197 .vdisplay = 480, 1198 .vsync_start = 480 + 10, 1199 .vsync_end = 480 + 10 + 2, 1200 .vtotal = 480 + 10 + 2 + 33, 1201 .vrefresh = 60, 1202 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1203 }; 1204 1205 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1206 .modes = &dataimage_scf0700c48ggu18_mode, 1207 .num_modes = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 152, 1211 .height = 91, 1212 }, 1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1214 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1215 }; 1216 1217 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1218 .pixelclock = { 45000000, 51200000, 57000000 }, 1219 .hactive = { 1024, 1024, 1024 }, 1220 .hfront_porch = { 100, 106, 113 }, 1221 .hback_porch = { 100, 106, 113 }, 1222 .hsync_len = { 100, 108, 114 }, 1223 .vactive = { 600, 600, 600 }, 1224 .vfront_porch = { 8, 11, 15 }, 1225 .vback_porch = { 8, 11, 15 }, 1226 .vsync_len = { 9, 13, 15 }, 1227 .flags = DISPLAY_FLAGS_DE_HIGH, 1228 }; 1229 1230 static const struct panel_desc dlc_dlc0700yzg_1 = { 1231 .timings = &dlc_dlc0700yzg_1_timing, 1232 .num_timings = 1, 1233 .bpc = 6, 1234 .size = { 1235 .width = 154, 1236 .height = 86, 1237 }, 1238 .delay = { 1239 .prepare = 30, 1240 .enable = 200, 1241 .disable = 200, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing dlc_dlc1010gig_timing = { 1248 .pixelclock = { 68900000, 71100000, 73400000 }, 1249 .hactive = { 1280, 1280, 1280 }, 1250 .hfront_porch = { 43, 53, 63 }, 1251 .hback_porch = { 43, 53, 63 }, 1252 .hsync_len = { 44, 54, 64 }, 1253 .vactive = { 800, 800, 800 }, 1254 .vfront_porch = { 5, 8, 11 }, 1255 .vback_porch = { 5, 8, 11 }, 1256 .vsync_len = { 5, 7, 11 }, 1257 .flags = DISPLAY_FLAGS_DE_HIGH, 1258 }; 1259 1260 static const struct panel_desc dlc_dlc1010gig = { 1261 .timings = &dlc_dlc1010gig_timing, 1262 .num_timings = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 216, 1266 .height = 135, 1267 }, 1268 .delay = { 1269 .prepare = 60, 1270 .enable = 150, 1271 .disable = 100, 1272 .unprepare = 60, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct drm_display_mode edt_et035012dm6_mode = { 1279 .clock = 6500, 1280 .hdisplay = 320, 1281 .hsync_start = 320 + 20, 1282 .hsync_end = 320 + 20 + 30, 1283 .htotal = 320 + 20 + 68, 1284 .vdisplay = 240, 1285 .vsync_start = 240 + 4, 1286 .vsync_end = 240 + 4 + 4, 1287 .vtotal = 240 + 4 + 4 + 14, 1288 .vrefresh = 60, 1289 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1290 }; 1291 1292 static const struct panel_desc edt_et035012dm6 = { 1293 .modes = &edt_et035012dm6_mode, 1294 .num_modes = 1, 1295 .bpc = 8, 1296 .size = { 1297 .width = 70, 1298 .height = 52, 1299 }, 1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1301 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1302 }; 1303 1304 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1305 .clock = 10870, 1306 .hdisplay = 480, 1307 .hsync_start = 480 + 8, 1308 .hsync_end = 480 + 8 + 4, 1309 .htotal = 480 + 8 + 4 + 41, 1310 1311 /* 1312 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1313 * fb_align 1314 */ 1315 1316 .vdisplay = 288, 1317 .vsync_start = 288 + 2, 1318 .vsync_end = 288 + 2 + 4, 1319 .vtotal = 288 + 2 + 4 + 10, 1320 .vrefresh = 60, 1321 }; 1322 1323 static const struct panel_desc edt_etm043080dh6gp = { 1324 .modes = &edt_etm043080dh6gp_mode, 1325 .num_modes = 1, 1326 .bpc = 8, 1327 .size = { 1328 .width = 100, 1329 .height = 65, 1330 }, 1331 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1332 .connector_type = DRM_MODE_CONNECTOR_DPI, 1333 }; 1334 1335 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1336 .clock = 9000, 1337 .hdisplay = 480, 1338 .hsync_start = 480 + 2, 1339 .hsync_end = 480 + 2 + 41, 1340 .htotal = 480 + 2 + 41 + 2, 1341 .vdisplay = 272, 1342 .vsync_start = 272 + 2, 1343 .vsync_end = 272 + 2 + 10, 1344 .vtotal = 272 + 2 + 10 + 2, 1345 .vrefresh = 60, 1346 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1347 }; 1348 1349 static const struct panel_desc edt_etm0430g0dh6 = { 1350 .modes = &edt_etm0430g0dh6_mode, 1351 .num_modes = 1, 1352 .bpc = 6, 1353 .size = { 1354 .width = 95, 1355 .height = 54, 1356 }, 1357 }; 1358 1359 static const struct drm_display_mode edt_et057090dhu_mode = { 1360 .clock = 25175, 1361 .hdisplay = 640, 1362 .hsync_start = 640 + 16, 1363 .hsync_end = 640 + 16 + 30, 1364 .htotal = 640 + 16 + 30 + 114, 1365 .vdisplay = 480, 1366 .vsync_start = 480 + 10, 1367 .vsync_end = 480 + 10 + 3, 1368 .vtotal = 480 + 10 + 3 + 32, 1369 .vrefresh = 60, 1370 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1371 }; 1372 1373 static const struct panel_desc edt_et057090dhu = { 1374 .modes = &edt_et057090dhu_mode, 1375 .num_modes = 1, 1376 .bpc = 6, 1377 .size = { 1378 .width = 115, 1379 .height = 86, 1380 }, 1381 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1382 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1383 }; 1384 1385 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1386 .clock = 33260, 1387 .hdisplay = 800, 1388 .hsync_start = 800 + 40, 1389 .hsync_end = 800 + 40 + 128, 1390 .htotal = 800 + 40 + 128 + 88, 1391 .vdisplay = 480, 1392 .vsync_start = 480 + 10, 1393 .vsync_end = 480 + 10 + 2, 1394 .vtotal = 480 + 10 + 2 + 33, 1395 .vrefresh = 60, 1396 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1397 }; 1398 1399 static const struct panel_desc edt_etm0700g0dh6 = { 1400 .modes = &edt_etm0700g0dh6_mode, 1401 .num_modes = 1, 1402 .bpc = 6, 1403 .size = { 1404 .width = 152, 1405 .height = 91, 1406 }, 1407 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1408 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1409 }; 1410 1411 static const struct panel_desc edt_etm0700g0bdh6 = { 1412 .modes = &edt_etm0700g0dh6_mode, 1413 .num_modes = 1, 1414 .bpc = 6, 1415 .size = { 1416 .width = 152, 1417 .height = 91, 1418 }, 1419 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1420 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1421 }; 1422 1423 static const struct display_timing evervision_vgg804821_timing = { 1424 .pixelclock = { 27600000, 33300000, 50000000 }, 1425 .hactive = { 800, 800, 800 }, 1426 .hfront_porch = { 40, 66, 70 }, 1427 .hback_porch = { 40, 67, 70 }, 1428 .hsync_len = { 40, 67, 70 }, 1429 .vactive = { 480, 480, 480 }, 1430 .vfront_porch = { 6, 10, 10 }, 1431 .vback_porch = { 7, 11, 11 }, 1432 .vsync_len = { 7, 11, 11 }, 1433 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1434 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1435 DISPLAY_FLAGS_SYNC_NEGEDGE, 1436 }; 1437 1438 static const struct panel_desc evervision_vgg804821 = { 1439 .timings = &evervision_vgg804821_timing, 1440 .num_timings = 1, 1441 .bpc = 8, 1442 .size = { 1443 .width = 108, 1444 .height = 64, 1445 }, 1446 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1447 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1448 }; 1449 1450 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1451 .clock = 32260, 1452 .hdisplay = 800, 1453 .hsync_start = 800 + 168, 1454 .hsync_end = 800 + 168 + 64, 1455 .htotal = 800 + 168 + 64 + 88, 1456 .vdisplay = 480, 1457 .vsync_start = 480 + 37, 1458 .vsync_end = 480 + 37 + 2, 1459 .vtotal = 480 + 37 + 2 + 8, 1460 .vrefresh = 60, 1461 }; 1462 1463 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1464 .modes = &foxlink_fl500wvr00_a0t_mode, 1465 .num_modes = 1, 1466 .bpc = 8, 1467 .size = { 1468 .width = 108, 1469 .height = 65, 1470 }, 1471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1472 }; 1473 1474 static const struct drm_display_mode frida_frd350h54004_mode = { 1475 .clock = 6000, 1476 .hdisplay = 320, 1477 .hsync_start = 320 + 44, 1478 .hsync_end = 320 + 44 + 16, 1479 .htotal = 320 + 44 + 16 + 20, 1480 .vdisplay = 240, 1481 .vsync_start = 240 + 2, 1482 .vsync_end = 240 + 2 + 6, 1483 .vtotal = 240 + 2 + 6 + 2, 1484 .vrefresh = 60, 1485 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1486 }; 1487 1488 static const struct panel_desc frida_frd350h54004 = { 1489 .modes = &frida_frd350h54004_mode, 1490 .num_modes = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 77, 1494 .height = 64, 1495 }, 1496 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1497 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1498 .connector_type = DRM_MODE_CONNECTOR_DPI, 1499 }; 1500 1501 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1502 .clock = 67185, 1503 .hdisplay = 800, 1504 .hsync_start = 800 + 20, 1505 .hsync_end = 800 + 20 + 24, 1506 .htotal = 800 + 20 + 24 + 20, 1507 .vdisplay = 1280, 1508 .vsync_start = 1280 + 4, 1509 .vsync_end = 1280 + 4 + 8, 1510 .vtotal = 1280 + 4 + 8 + 4, 1511 .vrefresh = 60, 1512 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1513 }; 1514 1515 static const struct panel_desc friendlyarm_hd702e = { 1516 .modes = &friendlyarm_hd702e_mode, 1517 .num_modes = 1, 1518 .size = { 1519 .width = 94, 1520 .height = 151, 1521 }, 1522 }; 1523 1524 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1525 .clock = 9000, 1526 .hdisplay = 480, 1527 .hsync_start = 480 + 5, 1528 .hsync_end = 480 + 5 + 1, 1529 .htotal = 480 + 5 + 1 + 40, 1530 .vdisplay = 272, 1531 .vsync_start = 272 + 8, 1532 .vsync_end = 272 + 8 + 1, 1533 .vtotal = 272 + 8 + 1 + 8, 1534 .vrefresh = 60, 1535 }; 1536 1537 static const struct panel_desc giantplus_gpg482739qs5 = { 1538 .modes = &giantplus_gpg482739qs5_mode, 1539 .num_modes = 1, 1540 .bpc = 8, 1541 .size = { 1542 .width = 95, 1543 .height = 54, 1544 }, 1545 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1546 }; 1547 1548 static const struct display_timing giantplus_gpm940b0_timing = { 1549 .pixelclock = { 13500000, 27000000, 27500000 }, 1550 .hactive = { 320, 320, 320 }, 1551 .hfront_porch = { 14, 686, 718 }, 1552 .hback_porch = { 50, 70, 255 }, 1553 .hsync_len = { 1, 1, 1 }, 1554 .vactive = { 240, 240, 240 }, 1555 .vfront_porch = { 1, 1, 179 }, 1556 .vback_porch = { 1, 21, 31 }, 1557 .vsync_len = { 1, 1, 6 }, 1558 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1559 }; 1560 1561 static const struct panel_desc giantplus_gpm940b0 = { 1562 .timings = &giantplus_gpm940b0_timing, 1563 .num_timings = 1, 1564 .bpc = 8, 1565 .size = { 1566 .width = 60, 1567 .height = 45, 1568 }, 1569 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1570 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1571 }; 1572 1573 static const struct display_timing hannstar_hsd070pww1_timing = { 1574 .pixelclock = { 64300000, 71100000, 82000000 }, 1575 .hactive = { 1280, 1280, 1280 }, 1576 .hfront_porch = { 1, 1, 10 }, 1577 .hback_porch = { 1, 1, 10 }, 1578 /* 1579 * According to the data sheet, the minimum horizontal blanking interval 1580 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1581 * minimum working horizontal blanking interval to be 60 clocks. 1582 */ 1583 .hsync_len = { 58, 158, 661 }, 1584 .vactive = { 800, 800, 800 }, 1585 .vfront_porch = { 1, 1, 10 }, 1586 .vback_porch = { 1, 1, 10 }, 1587 .vsync_len = { 1, 21, 203 }, 1588 .flags = DISPLAY_FLAGS_DE_HIGH, 1589 }; 1590 1591 static const struct panel_desc hannstar_hsd070pww1 = { 1592 .timings = &hannstar_hsd070pww1_timing, 1593 .num_timings = 1, 1594 .bpc = 6, 1595 .size = { 1596 .width = 151, 1597 .height = 94, 1598 }, 1599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1600 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1601 }; 1602 1603 static const struct display_timing hannstar_hsd100pxn1_timing = { 1604 .pixelclock = { 55000000, 65000000, 75000000 }, 1605 .hactive = { 1024, 1024, 1024 }, 1606 .hfront_porch = { 40, 40, 40 }, 1607 .hback_porch = { 220, 220, 220 }, 1608 .hsync_len = { 20, 60, 100 }, 1609 .vactive = { 768, 768, 768 }, 1610 .vfront_porch = { 7, 7, 7 }, 1611 .vback_porch = { 21, 21, 21 }, 1612 .vsync_len = { 10, 10, 10 }, 1613 .flags = DISPLAY_FLAGS_DE_HIGH, 1614 }; 1615 1616 static const struct panel_desc hannstar_hsd100pxn1 = { 1617 .timings = &hannstar_hsd100pxn1_timing, 1618 .num_timings = 1, 1619 .bpc = 6, 1620 .size = { 1621 .width = 203, 1622 .height = 152, 1623 }, 1624 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1625 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1626 }; 1627 1628 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1629 .clock = 33333, 1630 .hdisplay = 800, 1631 .hsync_start = 800 + 85, 1632 .hsync_end = 800 + 85 + 86, 1633 .htotal = 800 + 85 + 86 + 85, 1634 .vdisplay = 480, 1635 .vsync_start = 480 + 16, 1636 .vsync_end = 480 + 16 + 13, 1637 .vtotal = 480 + 16 + 13 + 16, 1638 .vrefresh = 60, 1639 }; 1640 1641 static const struct panel_desc hitachi_tx23d38vm0caa = { 1642 .modes = &hitachi_tx23d38vm0caa_mode, 1643 .num_modes = 1, 1644 .bpc = 6, 1645 .size = { 1646 .width = 195, 1647 .height = 117, 1648 }, 1649 .delay = { 1650 .enable = 160, 1651 .disable = 160, 1652 }, 1653 }; 1654 1655 static const struct drm_display_mode innolux_at043tn24_mode = { 1656 .clock = 9000, 1657 .hdisplay = 480, 1658 .hsync_start = 480 + 2, 1659 .hsync_end = 480 + 2 + 41, 1660 .htotal = 480 + 2 + 41 + 2, 1661 .vdisplay = 272, 1662 .vsync_start = 272 + 2, 1663 .vsync_end = 272 + 2 + 10, 1664 .vtotal = 272 + 2 + 10 + 2, 1665 .vrefresh = 60, 1666 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1667 }; 1668 1669 static const struct panel_desc innolux_at043tn24 = { 1670 .modes = &innolux_at043tn24_mode, 1671 .num_modes = 1, 1672 .bpc = 8, 1673 .size = { 1674 .width = 95, 1675 .height = 54, 1676 }, 1677 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1678 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1679 }; 1680 1681 static const struct drm_display_mode innolux_at070tn92_mode = { 1682 .clock = 33333, 1683 .hdisplay = 800, 1684 .hsync_start = 800 + 210, 1685 .hsync_end = 800 + 210 + 20, 1686 .htotal = 800 + 210 + 20 + 46, 1687 .vdisplay = 480, 1688 .vsync_start = 480 + 22, 1689 .vsync_end = 480 + 22 + 10, 1690 .vtotal = 480 + 22 + 23 + 10, 1691 .vrefresh = 60, 1692 }; 1693 1694 static const struct panel_desc innolux_at070tn92 = { 1695 .modes = &innolux_at070tn92_mode, 1696 .num_modes = 1, 1697 .size = { 1698 .width = 154, 1699 .height = 86, 1700 }, 1701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1702 }; 1703 1704 static const struct display_timing innolux_g070y2_l01_timing = { 1705 .pixelclock = { 28000000, 29500000, 32000000 }, 1706 .hactive = { 800, 800, 800 }, 1707 .hfront_porch = { 61, 91, 141 }, 1708 .hback_porch = { 60, 90, 140 }, 1709 .hsync_len = { 12, 12, 12 }, 1710 .vactive = { 480, 480, 480 }, 1711 .vfront_porch = { 4, 9, 30 }, 1712 .vback_porch = { 4, 8, 28 }, 1713 .vsync_len = { 2, 2, 2 }, 1714 .flags = DISPLAY_FLAGS_DE_HIGH, 1715 }; 1716 1717 static const struct panel_desc innolux_g070y2_l01 = { 1718 .timings = &innolux_g070y2_l01_timing, 1719 .num_timings = 1, 1720 .bpc = 6, 1721 .size = { 1722 .width = 152, 1723 .height = 91, 1724 }, 1725 .delay = { 1726 .prepare = 10, 1727 .enable = 100, 1728 .disable = 100, 1729 .unprepare = 800, 1730 }, 1731 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1733 }; 1734 1735 static const struct display_timing innolux_g101ice_l01_timing = { 1736 .pixelclock = { 60400000, 71100000, 74700000 }, 1737 .hactive = { 1280, 1280, 1280 }, 1738 .hfront_porch = { 41, 80, 100 }, 1739 .hback_porch = { 40, 79, 99 }, 1740 .hsync_len = { 1, 1, 1 }, 1741 .vactive = { 800, 800, 800 }, 1742 .vfront_porch = { 5, 11, 14 }, 1743 .vback_porch = { 4, 11, 14 }, 1744 .vsync_len = { 1, 1, 1 }, 1745 .flags = DISPLAY_FLAGS_DE_HIGH, 1746 }; 1747 1748 static const struct panel_desc innolux_g101ice_l01 = { 1749 .timings = &innolux_g101ice_l01_timing, 1750 .num_timings = 1, 1751 .bpc = 8, 1752 .size = { 1753 .width = 217, 1754 .height = 135, 1755 }, 1756 .delay = { 1757 .enable = 200, 1758 .disable = 200, 1759 }, 1760 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1761 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1762 }; 1763 1764 static const struct display_timing innolux_g121i1_l01_timing = { 1765 .pixelclock = { 67450000, 71000000, 74550000 }, 1766 .hactive = { 1280, 1280, 1280 }, 1767 .hfront_porch = { 40, 80, 160 }, 1768 .hback_porch = { 39, 79, 159 }, 1769 .hsync_len = { 1, 1, 1 }, 1770 .vactive = { 800, 800, 800 }, 1771 .vfront_porch = { 5, 11, 100 }, 1772 .vback_porch = { 4, 11, 99 }, 1773 .vsync_len = { 1, 1, 1 }, 1774 }; 1775 1776 static const struct panel_desc innolux_g121i1_l01 = { 1777 .timings = &innolux_g121i1_l01_timing, 1778 .num_timings = 1, 1779 .bpc = 6, 1780 .size = { 1781 .width = 261, 1782 .height = 163, 1783 }, 1784 .delay = { 1785 .enable = 200, 1786 .disable = 20, 1787 }, 1788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1789 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1790 }; 1791 1792 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1793 .clock = 65000, 1794 .hdisplay = 1024, 1795 .hsync_start = 1024 + 0, 1796 .hsync_end = 1024 + 1, 1797 .htotal = 1024 + 0 + 1 + 320, 1798 .vdisplay = 768, 1799 .vsync_start = 768 + 38, 1800 .vsync_end = 768 + 38 + 1, 1801 .vtotal = 768 + 38 + 1 + 0, 1802 .vrefresh = 60, 1803 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1804 }; 1805 1806 static const struct panel_desc innolux_g121x1_l03 = { 1807 .modes = &innolux_g121x1_l03_mode, 1808 .num_modes = 1, 1809 .bpc = 6, 1810 .size = { 1811 .width = 246, 1812 .height = 185, 1813 }, 1814 .delay = { 1815 .enable = 200, 1816 .unprepare = 200, 1817 .disable = 400, 1818 }, 1819 }; 1820 1821 /* 1822 * Datasheet specifies that at 60 Hz refresh rate: 1823 * - total horizontal time: { 1506, 1592, 1716 } 1824 * - total vertical time: { 788, 800, 868 } 1825 * 1826 * ...but doesn't go into exactly how that should be split into a front 1827 * porch, back porch, or sync length. For now we'll leave a single setting 1828 * here which allows a bit of tweaking of the pixel clock at the expense of 1829 * refresh rate. 1830 */ 1831 static const struct display_timing innolux_n116bge_timing = { 1832 .pixelclock = { 72600000, 76420000, 80240000 }, 1833 .hactive = { 1366, 1366, 1366 }, 1834 .hfront_porch = { 136, 136, 136 }, 1835 .hback_porch = { 60, 60, 60 }, 1836 .hsync_len = { 30, 30, 30 }, 1837 .vactive = { 768, 768, 768 }, 1838 .vfront_porch = { 8, 8, 8 }, 1839 .vback_porch = { 12, 12, 12 }, 1840 .vsync_len = { 12, 12, 12 }, 1841 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 1842 }; 1843 1844 static const struct panel_desc innolux_n116bge = { 1845 .timings = &innolux_n116bge_timing, 1846 .num_timings = 1, 1847 .bpc = 6, 1848 .size = { 1849 .width = 256, 1850 .height = 144, 1851 }, 1852 }; 1853 1854 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1855 .clock = 69300, 1856 .hdisplay = 1366, 1857 .hsync_start = 1366 + 16, 1858 .hsync_end = 1366 + 16 + 34, 1859 .htotal = 1366 + 16 + 34 + 50, 1860 .vdisplay = 768, 1861 .vsync_start = 768 + 2, 1862 .vsync_end = 768 + 2 + 6, 1863 .vtotal = 768 + 2 + 6 + 12, 1864 .vrefresh = 60, 1865 }; 1866 1867 static const struct panel_desc innolux_n156bge_l21 = { 1868 .modes = &innolux_n156bge_l21_mode, 1869 .num_modes = 1, 1870 .bpc = 6, 1871 .size = { 1872 .width = 344, 1873 .height = 193, 1874 }, 1875 }; 1876 1877 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1878 .clock = 206016, 1879 .hdisplay = 2160, 1880 .hsync_start = 2160 + 48, 1881 .hsync_end = 2160 + 48 + 32, 1882 .htotal = 2160 + 48 + 32 + 80, 1883 .vdisplay = 1440, 1884 .vsync_start = 1440 + 3, 1885 .vsync_end = 1440 + 3 + 10, 1886 .vtotal = 1440 + 3 + 10 + 27, 1887 .vrefresh = 60, 1888 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1889 }; 1890 1891 static const struct panel_desc innolux_p120zdg_bf1 = { 1892 .modes = &innolux_p120zdg_bf1_mode, 1893 .num_modes = 1, 1894 .bpc = 8, 1895 .size = { 1896 .width = 254, 1897 .height = 169, 1898 }, 1899 .delay = { 1900 .hpd_absent_delay = 200, 1901 .unprepare = 500, 1902 }, 1903 }; 1904 1905 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1906 .clock = 51501, 1907 .hdisplay = 1024, 1908 .hsync_start = 1024 + 128, 1909 .hsync_end = 1024 + 128 + 64, 1910 .htotal = 1024 + 128 + 64 + 128, 1911 .vdisplay = 600, 1912 .vsync_start = 600 + 16, 1913 .vsync_end = 600 + 16 + 4, 1914 .vtotal = 600 + 16 + 4 + 16, 1915 .vrefresh = 60, 1916 }; 1917 1918 static const struct panel_desc innolux_zj070na_01p = { 1919 .modes = &innolux_zj070na_01p_mode, 1920 .num_modes = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 90, 1925 }, 1926 }; 1927 1928 static const struct display_timing koe_tx14d24vm1bpa_timing = { 1929 .pixelclock = { 5580000, 5850000, 6200000 }, 1930 .hactive = { 320, 320, 320 }, 1931 .hfront_porch = { 30, 30, 30 }, 1932 .hback_porch = { 30, 30, 30 }, 1933 .hsync_len = { 1, 5, 17 }, 1934 .vactive = { 240, 240, 240 }, 1935 .vfront_porch = { 6, 6, 6 }, 1936 .vback_porch = { 5, 5, 5 }, 1937 .vsync_len = { 1, 2, 11 }, 1938 .flags = DISPLAY_FLAGS_DE_HIGH, 1939 }; 1940 1941 static const struct panel_desc koe_tx14d24vm1bpa = { 1942 .timings = &koe_tx14d24vm1bpa_timing, 1943 .num_timings = 1, 1944 .bpc = 6, 1945 .size = { 1946 .width = 115, 1947 .height = 86, 1948 }, 1949 }; 1950 1951 static const struct display_timing koe_tx31d200vm0baa_timing = { 1952 .pixelclock = { 39600000, 43200000, 48000000 }, 1953 .hactive = { 1280, 1280, 1280 }, 1954 .hfront_porch = { 16, 36, 56 }, 1955 .hback_porch = { 16, 36, 56 }, 1956 .hsync_len = { 8, 8, 8 }, 1957 .vactive = { 480, 480, 480 }, 1958 .vfront_porch = { 6, 21, 33 }, 1959 .vback_porch = { 6, 21, 33 }, 1960 .vsync_len = { 8, 8, 8 }, 1961 .flags = DISPLAY_FLAGS_DE_HIGH, 1962 }; 1963 1964 static const struct panel_desc koe_tx31d200vm0baa = { 1965 .timings = &koe_tx31d200vm0baa_timing, 1966 .num_timings = 1, 1967 .bpc = 6, 1968 .size = { 1969 .width = 292, 1970 .height = 109, 1971 }, 1972 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1973 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1974 }; 1975 1976 static const struct display_timing kyo_tcg121xglp_timing = { 1977 .pixelclock = { 52000000, 65000000, 71000000 }, 1978 .hactive = { 1024, 1024, 1024 }, 1979 .hfront_porch = { 2, 2, 2 }, 1980 .hback_porch = { 2, 2, 2 }, 1981 .hsync_len = { 86, 124, 244 }, 1982 .vactive = { 768, 768, 768 }, 1983 .vfront_porch = { 2, 2, 2 }, 1984 .vback_porch = { 2, 2, 2 }, 1985 .vsync_len = { 6, 34, 73 }, 1986 .flags = DISPLAY_FLAGS_DE_HIGH, 1987 }; 1988 1989 static const struct panel_desc kyo_tcg121xglp = { 1990 .timings = &kyo_tcg121xglp_timing, 1991 .num_timings = 1, 1992 .bpc = 8, 1993 .size = { 1994 .width = 246, 1995 .height = 184, 1996 }, 1997 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1999 }; 2000 2001 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2002 .clock = 7000, 2003 .hdisplay = 320, 2004 .hsync_start = 320 + 20, 2005 .hsync_end = 320 + 20 + 30, 2006 .htotal = 320 + 20 + 30 + 38, 2007 .vdisplay = 240, 2008 .vsync_start = 240 + 4, 2009 .vsync_end = 240 + 4 + 3, 2010 .vtotal = 240 + 4 + 3 + 15, 2011 .vrefresh = 60, 2012 }; 2013 2014 static const struct panel_desc lemaker_bl035_rgb_002 = { 2015 .modes = &lemaker_bl035_rgb_002_mode, 2016 .num_modes = 1, 2017 .size = { 2018 .width = 70, 2019 .height = 52, 2020 }, 2021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2022 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2023 }; 2024 2025 static const struct drm_display_mode lg_lb070wv8_mode = { 2026 .clock = 33246, 2027 .hdisplay = 800, 2028 .hsync_start = 800 + 88, 2029 .hsync_end = 800 + 88 + 80, 2030 .htotal = 800 + 88 + 80 + 88, 2031 .vdisplay = 480, 2032 .vsync_start = 480 + 10, 2033 .vsync_end = 480 + 10 + 25, 2034 .vtotal = 480 + 10 + 25 + 10, 2035 .vrefresh = 60, 2036 }; 2037 2038 static const struct panel_desc lg_lb070wv8 = { 2039 .modes = &lg_lb070wv8_mode, 2040 .num_modes = 1, 2041 .bpc = 16, 2042 .size = { 2043 .width = 151, 2044 .height = 91, 2045 }, 2046 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2048 }; 2049 2050 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2051 .clock = 200000, 2052 .hdisplay = 1536, 2053 .hsync_start = 1536 + 12, 2054 .hsync_end = 1536 + 12 + 16, 2055 .htotal = 1536 + 12 + 16 + 48, 2056 .vdisplay = 2048, 2057 .vsync_start = 2048 + 8, 2058 .vsync_end = 2048 + 8 + 4, 2059 .vtotal = 2048 + 8 + 4 + 8, 2060 .vrefresh = 60, 2061 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2062 }; 2063 2064 static const struct panel_desc lg_lp079qx1_sp0v = { 2065 .modes = &lg_lp079qx1_sp0v_mode, 2066 .num_modes = 1, 2067 .size = { 2068 .width = 129, 2069 .height = 171, 2070 }, 2071 }; 2072 2073 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2074 .clock = 205210, 2075 .hdisplay = 2048, 2076 .hsync_start = 2048 + 150, 2077 .hsync_end = 2048 + 150 + 5, 2078 .htotal = 2048 + 150 + 5 + 5, 2079 .vdisplay = 1536, 2080 .vsync_start = 1536 + 3, 2081 .vsync_end = 1536 + 3 + 1, 2082 .vtotal = 1536 + 3 + 1 + 9, 2083 .vrefresh = 60, 2084 }; 2085 2086 static const struct panel_desc lg_lp097qx1_spa1 = { 2087 .modes = &lg_lp097qx1_spa1_mode, 2088 .num_modes = 1, 2089 .size = { 2090 .width = 208, 2091 .height = 147, 2092 }, 2093 }; 2094 2095 static const struct drm_display_mode lg_lp120up1_mode = { 2096 .clock = 162300, 2097 .hdisplay = 1920, 2098 .hsync_start = 1920 + 40, 2099 .hsync_end = 1920 + 40 + 40, 2100 .htotal = 1920 + 40 + 40+ 80, 2101 .vdisplay = 1280, 2102 .vsync_start = 1280 + 4, 2103 .vsync_end = 1280 + 4 + 4, 2104 .vtotal = 1280 + 4 + 4 + 12, 2105 .vrefresh = 60, 2106 }; 2107 2108 static const struct panel_desc lg_lp120up1 = { 2109 .modes = &lg_lp120up1_mode, 2110 .num_modes = 1, 2111 .bpc = 8, 2112 .size = { 2113 .width = 267, 2114 .height = 183, 2115 }, 2116 }; 2117 2118 static const struct drm_display_mode lg_lp129qe_mode = { 2119 .clock = 285250, 2120 .hdisplay = 2560, 2121 .hsync_start = 2560 + 48, 2122 .hsync_end = 2560 + 48 + 32, 2123 .htotal = 2560 + 48 + 32 + 80, 2124 .vdisplay = 1700, 2125 .vsync_start = 1700 + 3, 2126 .vsync_end = 1700 + 3 + 10, 2127 .vtotal = 1700 + 3 + 10 + 36, 2128 .vrefresh = 60, 2129 }; 2130 2131 static const struct panel_desc lg_lp129qe = { 2132 .modes = &lg_lp129qe_mode, 2133 .num_modes = 1, 2134 .bpc = 8, 2135 .size = { 2136 .width = 272, 2137 .height = 181, 2138 }, 2139 }; 2140 2141 static const struct display_timing logictechno_lt161010_2nh_timing = { 2142 .pixelclock = { 26400000, 33300000, 46800000 }, 2143 .hactive = { 800, 800, 800 }, 2144 .hfront_porch = { 16, 210, 354 }, 2145 .hback_porch = { 46, 46, 46 }, 2146 .hsync_len = { 1, 20, 40 }, 2147 .vactive = { 480, 480, 480 }, 2148 .vfront_porch = { 7, 22, 147 }, 2149 .vback_porch = { 23, 23, 23 }, 2150 .vsync_len = { 1, 10, 20 }, 2151 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2152 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2153 DISPLAY_FLAGS_SYNC_POSEDGE, 2154 }; 2155 2156 static const struct panel_desc logictechno_lt161010_2nh = { 2157 .timings = &logictechno_lt161010_2nh_timing, 2158 .num_timings = 1, 2159 .size = { 2160 .width = 154, 2161 .height = 86, 2162 }, 2163 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2164 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2165 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2166 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2167 .connector_type = DRM_MODE_CONNECTOR_DPI, 2168 }; 2169 2170 static const struct display_timing logictechno_lt170410_2whc_timing = { 2171 .pixelclock = { 68900000, 71100000, 73400000 }, 2172 .hactive = { 1280, 1280, 1280 }, 2173 .hfront_porch = { 23, 60, 71 }, 2174 .hback_porch = { 23, 60, 71 }, 2175 .hsync_len = { 15, 40, 47 }, 2176 .vactive = { 800, 800, 800 }, 2177 .vfront_porch = { 5, 7, 10 }, 2178 .vback_porch = { 5, 7, 10 }, 2179 .vsync_len = { 6, 9, 12 }, 2180 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2181 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2182 DISPLAY_FLAGS_SYNC_POSEDGE, 2183 }; 2184 2185 static const struct panel_desc logictechno_lt170410_2whc = { 2186 .timings = &logictechno_lt170410_2whc_timing, 2187 .num_timings = 1, 2188 .size = { 2189 .width = 217, 2190 .height = 136, 2191 }, 2192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2193 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2194 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2195 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2196 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2197 }; 2198 2199 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2200 .clock = 30400, 2201 .hdisplay = 800, 2202 .hsync_start = 800 + 0, 2203 .hsync_end = 800 + 1, 2204 .htotal = 800 + 0 + 1 + 160, 2205 .vdisplay = 480, 2206 .vsync_start = 480 + 0, 2207 .vsync_end = 480 + 48 + 1, 2208 .vtotal = 480 + 48 + 1 + 0, 2209 .vrefresh = 60, 2210 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2211 }; 2212 2213 static const struct drm_display_mode logicpd_type_28_mode = { 2214 .clock = 9000, 2215 .hdisplay = 480, 2216 .hsync_start = 480 + 3, 2217 .hsync_end = 480 + 3 + 42, 2218 .htotal = 480 + 3 + 42 + 2, 2219 2220 .vdisplay = 272, 2221 .vsync_start = 272 + 2, 2222 .vsync_end = 272 + 2 + 11, 2223 .vtotal = 272 + 2 + 11 + 3, 2224 .vrefresh = 60, 2225 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2226 }; 2227 2228 static const struct panel_desc logicpd_type_28 = { 2229 .modes = &logicpd_type_28_mode, 2230 .num_modes = 1, 2231 .bpc = 8, 2232 .size = { 2233 .width = 105, 2234 .height = 67, 2235 }, 2236 .delay = { 2237 .prepare = 200, 2238 .enable = 200, 2239 .unprepare = 200, 2240 .disable = 200, 2241 }, 2242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2243 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2244 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2245 }; 2246 2247 static const struct panel_desc mitsubishi_aa070mc01 = { 2248 .modes = &mitsubishi_aa070mc01_mode, 2249 .num_modes = 1, 2250 .bpc = 8, 2251 .size = { 2252 .width = 152, 2253 .height = 91, 2254 }, 2255 2256 .delay = { 2257 .enable = 200, 2258 .unprepare = 200, 2259 .disable = 400, 2260 }, 2261 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2262 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2263 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2264 }; 2265 2266 static const struct display_timing nec_nl12880bc20_05_timing = { 2267 .pixelclock = { 67000000, 71000000, 75000000 }, 2268 .hactive = { 1280, 1280, 1280 }, 2269 .hfront_porch = { 2, 30, 30 }, 2270 .hback_porch = { 6, 100, 100 }, 2271 .hsync_len = { 2, 30, 30 }, 2272 .vactive = { 800, 800, 800 }, 2273 .vfront_porch = { 5, 5, 5 }, 2274 .vback_porch = { 11, 11, 11 }, 2275 .vsync_len = { 7, 7, 7 }, 2276 }; 2277 2278 static const struct panel_desc nec_nl12880bc20_05 = { 2279 .timings = &nec_nl12880bc20_05_timing, 2280 .num_timings = 1, 2281 .bpc = 8, 2282 .size = { 2283 .width = 261, 2284 .height = 163, 2285 }, 2286 .delay = { 2287 .enable = 50, 2288 .disable = 50, 2289 }, 2290 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2291 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2292 }; 2293 2294 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2295 .clock = 10870, 2296 .hdisplay = 480, 2297 .hsync_start = 480 + 2, 2298 .hsync_end = 480 + 2 + 41, 2299 .htotal = 480 + 2 + 41 + 2, 2300 .vdisplay = 272, 2301 .vsync_start = 272 + 2, 2302 .vsync_end = 272 + 2 + 4, 2303 .vtotal = 272 + 2 + 4 + 2, 2304 .vrefresh = 74, 2305 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2306 }; 2307 2308 static const struct panel_desc nec_nl4827hc19_05b = { 2309 .modes = &nec_nl4827hc19_05b_mode, 2310 .num_modes = 1, 2311 .bpc = 8, 2312 .size = { 2313 .width = 95, 2314 .height = 54, 2315 }, 2316 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2317 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2318 }; 2319 2320 static const struct drm_display_mode netron_dy_e231732_mode = { 2321 .clock = 66000, 2322 .hdisplay = 1024, 2323 .hsync_start = 1024 + 160, 2324 .hsync_end = 1024 + 160 + 70, 2325 .htotal = 1024 + 160 + 70 + 90, 2326 .vdisplay = 600, 2327 .vsync_start = 600 + 127, 2328 .vsync_end = 600 + 127 + 20, 2329 .vtotal = 600 + 127 + 20 + 3, 2330 .vrefresh = 60, 2331 }; 2332 2333 static const struct panel_desc netron_dy_e231732 = { 2334 .modes = &netron_dy_e231732_mode, 2335 .num_modes = 1, 2336 .size = { 2337 .width = 154, 2338 .height = 87, 2339 }, 2340 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2341 }; 2342 2343 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2344 .clock = 9000, 2345 .hdisplay = 480, 2346 .hsync_start = 480 + 2, 2347 .hsync_end = 480 + 2 + 41, 2348 .htotal = 480 + 2 + 41 + 2, 2349 .vdisplay = 272, 2350 .vsync_start = 272 + 2, 2351 .vsync_end = 272 + 2 + 10, 2352 .vtotal = 272 + 2 + 10 + 2, 2353 .vrefresh = 60, 2354 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2355 }; 2356 2357 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2358 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2359 .num_modes = 1, 2360 .bpc = 8, 2361 .size = { 2362 .width = 95, 2363 .height = 54, 2364 }, 2365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2367 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2368 }; 2369 2370 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2371 .pixelclock = { 130000000, 148350000, 163000000 }, 2372 .hactive = { 1920, 1920, 1920 }, 2373 .hfront_porch = { 80, 100, 100 }, 2374 .hback_porch = { 100, 120, 120 }, 2375 .hsync_len = { 50, 60, 60 }, 2376 .vactive = { 1080, 1080, 1080 }, 2377 .vfront_porch = { 12, 30, 30 }, 2378 .vback_porch = { 4, 10, 10 }, 2379 .vsync_len = { 4, 5, 5 }, 2380 }; 2381 2382 static const struct panel_desc nlt_nl192108ac18_02d = { 2383 .timings = &nlt_nl192108ac18_02d_timing, 2384 .num_timings = 1, 2385 .bpc = 8, 2386 .size = { 2387 .width = 344, 2388 .height = 194, 2389 }, 2390 .delay = { 2391 .unprepare = 500, 2392 }, 2393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2394 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2395 }; 2396 2397 static const struct drm_display_mode nvd_9128_mode = { 2398 .clock = 29500, 2399 .hdisplay = 800, 2400 .hsync_start = 800 + 130, 2401 .hsync_end = 800 + 130 + 98, 2402 .htotal = 800 + 0 + 130 + 98, 2403 .vdisplay = 480, 2404 .vsync_start = 480 + 10, 2405 .vsync_end = 480 + 10 + 50, 2406 .vtotal = 480 + 0 + 10 + 50, 2407 }; 2408 2409 static const struct panel_desc nvd_9128 = { 2410 .modes = &nvd_9128_mode, 2411 .num_modes = 1, 2412 .bpc = 8, 2413 .size = { 2414 .width = 156, 2415 .height = 88, 2416 }, 2417 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2418 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2419 }; 2420 2421 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2422 .pixelclock = { 30000000, 30000000, 40000000 }, 2423 .hactive = { 800, 800, 800 }, 2424 .hfront_porch = { 40, 40, 40 }, 2425 .hback_porch = { 40, 40, 40 }, 2426 .hsync_len = { 1, 48, 48 }, 2427 .vactive = { 480, 480, 480 }, 2428 .vfront_porch = { 13, 13, 13 }, 2429 .vback_porch = { 29, 29, 29 }, 2430 .vsync_len = { 3, 3, 3 }, 2431 .flags = DISPLAY_FLAGS_DE_HIGH, 2432 }; 2433 2434 static const struct panel_desc okaya_rs800480t_7x0gp = { 2435 .timings = &okaya_rs800480t_7x0gp_timing, 2436 .num_timings = 1, 2437 .bpc = 6, 2438 .size = { 2439 .width = 154, 2440 .height = 87, 2441 }, 2442 .delay = { 2443 .prepare = 41, 2444 .enable = 50, 2445 .unprepare = 41, 2446 .disable = 50, 2447 }, 2448 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2449 }; 2450 2451 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2452 .clock = 9000, 2453 .hdisplay = 480, 2454 .hsync_start = 480 + 5, 2455 .hsync_end = 480 + 5 + 30, 2456 .htotal = 480 + 5 + 30 + 10, 2457 .vdisplay = 272, 2458 .vsync_start = 272 + 8, 2459 .vsync_end = 272 + 8 + 5, 2460 .vtotal = 272 + 8 + 5 + 3, 2461 .vrefresh = 60, 2462 }; 2463 2464 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2465 .modes = &olimex_lcd_olinuxino_43ts_mode, 2466 .num_modes = 1, 2467 .size = { 2468 .width = 95, 2469 .height = 54, 2470 }, 2471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2472 }; 2473 2474 /* 2475 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2476 * pixel clocks, but this is the timing that was being used in the Adafruit 2477 * installation instructions. 2478 */ 2479 static const struct drm_display_mode ontat_yx700wv03_mode = { 2480 .clock = 29500, 2481 .hdisplay = 800, 2482 .hsync_start = 824, 2483 .hsync_end = 896, 2484 .htotal = 992, 2485 .vdisplay = 480, 2486 .vsync_start = 483, 2487 .vsync_end = 493, 2488 .vtotal = 500, 2489 .vrefresh = 60, 2490 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2491 }; 2492 2493 /* 2494 * Specification at: 2495 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2496 */ 2497 static const struct panel_desc ontat_yx700wv03 = { 2498 .modes = &ontat_yx700wv03_mode, 2499 .num_modes = 1, 2500 .bpc = 8, 2501 .size = { 2502 .width = 154, 2503 .height = 83, 2504 }, 2505 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2506 }; 2507 2508 static const struct drm_display_mode ortustech_com37h3m_mode = { 2509 .clock = 22153, 2510 .hdisplay = 480, 2511 .hsync_start = 480 + 8, 2512 .hsync_end = 480 + 8 + 10, 2513 .htotal = 480 + 8 + 10 + 10, 2514 .vdisplay = 640, 2515 .vsync_start = 640 + 4, 2516 .vsync_end = 640 + 4 + 3, 2517 .vtotal = 640 + 4 + 3 + 4, 2518 .vrefresh = 60, 2519 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2520 }; 2521 2522 static const struct panel_desc ortustech_com37h3m = { 2523 .modes = &ortustech_com37h3m_mode, 2524 .num_modes = 1, 2525 .bpc = 8, 2526 .size = { 2527 .width = 56, /* 56.16mm */ 2528 .height = 75, /* 74.88mm */ 2529 }, 2530 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2531 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2532 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2533 }; 2534 2535 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2536 .clock = 25000, 2537 .hdisplay = 480, 2538 .hsync_start = 480 + 10, 2539 .hsync_end = 480 + 10 + 10, 2540 .htotal = 480 + 10 + 10 + 15, 2541 .vdisplay = 800, 2542 .vsync_start = 800 + 3, 2543 .vsync_end = 800 + 3 + 3, 2544 .vtotal = 800 + 3 + 3 + 3, 2545 .vrefresh = 60, 2546 }; 2547 2548 static const struct panel_desc ortustech_com43h4m85ulc = { 2549 .modes = &ortustech_com43h4m85ulc_mode, 2550 .num_modes = 1, 2551 .bpc = 8, 2552 .size = { 2553 .width = 56, 2554 .height = 93, 2555 }, 2556 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2557 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2558 }; 2559 2560 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2561 .clock = 33000, 2562 .hdisplay = 800, 2563 .hsync_start = 800 + 210, 2564 .hsync_end = 800 + 210 + 30, 2565 .htotal = 800 + 210 + 30 + 16, 2566 .vdisplay = 480, 2567 .vsync_start = 480 + 22, 2568 .vsync_end = 480 + 22 + 13, 2569 .vtotal = 480 + 22 + 13 + 10, 2570 .vrefresh = 60, 2571 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2572 }; 2573 2574 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2575 .modes = &osddisplays_osd070t1718_19ts_mode, 2576 .num_modes = 1, 2577 .bpc = 8, 2578 .size = { 2579 .width = 152, 2580 .height = 91, 2581 }, 2582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2583 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2584 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2585 .connector_type = DRM_MODE_CONNECTOR_DPI, 2586 }; 2587 2588 static const struct drm_display_mode pda_91_00156_a0_mode = { 2589 .clock = 33300, 2590 .hdisplay = 800, 2591 .hsync_start = 800 + 1, 2592 .hsync_end = 800 + 1 + 64, 2593 .htotal = 800 + 1 + 64 + 64, 2594 .vdisplay = 480, 2595 .vsync_start = 480 + 1, 2596 .vsync_end = 480 + 1 + 23, 2597 .vtotal = 480 + 1 + 23 + 22, 2598 .vrefresh = 60, 2599 }; 2600 2601 static const struct panel_desc pda_91_00156_a0 = { 2602 .modes = &pda_91_00156_a0_mode, 2603 .num_modes = 1, 2604 .size = { 2605 .width = 152, 2606 .height = 91, 2607 }, 2608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2609 }; 2610 2611 2612 static const struct drm_display_mode qd43003c0_40_mode = { 2613 .clock = 9000, 2614 .hdisplay = 480, 2615 .hsync_start = 480 + 8, 2616 .hsync_end = 480 + 8 + 4, 2617 .htotal = 480 + 8 + 4 + 39, 2618 .vdisplay = 272, 2619 .vsync_start = 272 + 4, 2620 .vsync_end = 272 + 4 + 10, 2621 .vtotal = 272 + 4 + 10 + 2, 2622 .vrefresh = 60, 2623 }; 2624 2625 static const struct panel_desc qd43003c0_40 = { 2626 .modes = &qd43003c0_40_mode, 2627 .num_modes = 1, 2628 .bpc = 8, 2629 .size = { 2630 .width = 95, 2631 .height = 53, 2632 }, 2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2634 }; 2635 2636 static const struct display_timing rocktech_rk070er9427_timing = { 2637 .pixelclock = { 26400000, 33300000, 46800000 }, 2638 .hactive = { 800, 800, 800 }, 2639 .hfront_porch = { 16, 210, 354 }, 2640 .hback_porch = { 46, 46, 46 }, 2641 .hsync_len = { 1, 1, 1 }, 2642 .vactive = { 480, 480, 480 }, 2643 .vfront_porch = { 7, 22, 147 }, 2644 .vback_porch = { 23, 23, 23 }, 2645 .vsync_len = { 1, 1, 1 }, 2646 .flags = DISPLAY_FLAGS_DE_HIGH, 2647 }; 2648 2649 static const struct panel_desc rocktech_rk070er9427 = { 2650 .timings = &rocktech_rk070er9427_timing, 2651 .num_timings = 1, 2652 .bpc = 6, 2653 .size = { 2654 .width = 154, 2655 .height = 86, 2656 }, 2657 .delay = { 2658 .prepare = 41, 2659 .enable = 50, 2660 .unprepare = 41, 2661 .disable = 50, 2662 }, 2663 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2664 }; 2665 2666 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2667 .clock = 71100, 2668 .hdisplay = 1280, 2669 .hsync_start = 1280 + 48, 2670 .hsync_end = 1280 + 48 + 32, 2671 .htotal = 1280 + 48 + 32 + 80, 2672 .vdisplay = 800, 2673 .vsync_start = 800 + 2, 2674 .vsync_end = 800 + 2 + 5, 2675 .vtotal = 800 + 2 + 5 + 16, 2676 .vrefresh = 60, 2677 }; 2678 2679 static const struct panel_desc rocktech_rk101ii01d_ct = { 2680 .modes = &rocktech_rk101ii01d_ct_mode, 2681 .num_modes = 1, 2682 .size = { 2683 .width = 217, 2684 .height = 136, 2685 }, 2686 .delay = { 2687 .prepare = 50, 2688 .disable = 50, 2689 }, 2690 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2692 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2693 }; 2694 2695 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2696 .clock = 271560, 2697 .hdisplay = 2560, 2698 .hsync_start = 2560 + 48, 2699 .hsync_end = 2560 + 48 + 32, 2700 .htotal = 2560 + 48 + 32 + 80, 2701 .vdisplay = 1600, 2702 .vsync_start = 1600 + 2, 2703 .vsync_end = 1600 + 2 + 5, 2704 .vtotal = 1600 + 2 + 5 + 57, 2705 .vrefresh = 60, 2706 }; 2707 2708 static const struct panel_desc samsung_lsn122dl01_c01 = { 2709 .modes = &samsung_lsn122dl01_c01_mode, 2710 .num_modes = 1, 2711 .size = { 2712 .width = 263, 2713 .height = 164, 2714 }, 2715 }; 2716 2717 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2718 .clock = 54030, 2719 .hdisplay = 1024, 2720 .hsync_start = 1024 + 24, 2721 .hsync_end = 1024 + 24 + 136, 2722 .htotal = 1024 + 24 + 136 + 160, 2723 .vdisplay = 600, 2724 .vsync_start = 600 + 3, 2725 .vsync_end = 600 + 3 + 6, 2726 .vtotal = 600 + 3 + 6 + 61, 2727 .vrefresh = 60, 2728 }; 2729 2730 static const struct panel_desc samsung_ltn101nt05 = { 2731 .modes = &samsung_ltn101nt05_mode, 2732 .num_modes = 1, 2733 .bpc = 6, 2734 .size = { 2735 .width = 223, 2736 .height = 125, 2737 }, 2738 }; 2739 2740 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2741 .clock = 76300, 2742 .hdisplay = 1366, 2743 .hsync_start = 1366 + 64, 2744 .hsync_end = 1366 + 64 + 48, 2745 .htotal = 1366 + 64 + 48 + 128, 2746 .vdisplay = 768, 2747 .vsync_start = 768 + 2, 2748 .vsync_end = 768 + 2 + 5, 2749 .vtotal = 768 + 2 + 5 + 17, 2750 .vrefresh = 60, 2751 }; 2752 2753 static const struct panel_desc samsung_ltn140at29_301 = { 2754 .modes = &samsung_ltn140at29_301_mode, 2755 .num_modes = 1, 2756 .bpc = 6, 2757 .size = { 2758 .width = 320, 2759 .height = 187, 2760 }, 2761 }; 2762 2763 static const struct display_timing satoz_sat050at40h12r2_timing = { 2764 .pixelclock = {33300000, 33300000, 50000000}, 2765 .hactive = {800, 800, 800}, 2766 .hfront_porch = {16, 210, 354}, 2767 .hback_porch = {46, 46, 46}, 2768 .hsync_len = {1, 1, 40}, 2769 .vactive = {480, 480, 480}, 2770 .vfront_porch = {7, 22, 147}, 2771 .vback_porch = {23, 23, 23}, 2772 .vsync_len = {1, 1, 20}, 2773 }; 2774 2775 static const struct panel_desc satoz_sat050at40h12r2 = { 2776 .timings = &satoz_sat050at40h12r2_timing, 2777 .num_timings = 1, 2778 .bpc = 8, 2779 .size = { 2780 .width = 108, 2781 .height = 65, 2782 }, 2783 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2785 }; 2786 2787 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 2788 .clock = 168480, 2789 .hdisplay = 1920, 2790 .hsync_start = 1920 + 48, 2791 .hsync_end = 1920 + 48 + 32, 2792 .htotal = 1920 + 48 + 32 + 80, 2793 .vdisplay = 1280, 2794 .vsync_start = 1280 + 3, 2795 .vsync_end = 1280 + 3 + 10, 2796 .vtotal = 1280 + 3 + 10 + 57, 2797 .vrefresh = 60, 2798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2799 }; 2800 2801 static const struct panel_desc sharp_ld_d5116z01b = { 2802 .modes = &sharp_ld_d5116z01b_mode, 2803 .num_modes = 1, 2804 .bpc = 8, 2805 .size = { 2806 .width = 260, 2807 .height = 120, 2808 }, 2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2810 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2811 }; 2812 2813 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 2814 .clock = 33260, 2815 .hdisplay = 800, 2816 .hsync_start = 800 + 64, 2817 .hsync_end = 800 + 64 + 128, 2818 .htotal = 800 + 64 + 128 + 64, 2819 .vdisplay = 480, 2820 .vsync_start = 480 + 8, 2821 .vsync_end = 480 + 8 + 2, 2822 .vtotal = 480 + 8 + 2 + 35, 2823 .vrefresh = 60, 2824 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2825 }; 2826 2827 static const struct panel_desc sharp_lq070y3dg3b = { 2828 .modes = &sharp_lq070y3dg3b_mode, 2829 .num_modes = 1, 2830 .bpc = 8, 2831 .size = { 2832 .width = 152, /* 152.4mm */ 2833 .height = 91, /* 91.4mm */ 2834 }, 2835 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2836 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2837 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2838 }; 2839 2840 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2841 .clock = 5500, 2842 .hdisplay = 240, 2843 .hsync_start = 240 + 16, 2844 .hsync_end = 240 + 16 + 7, 2845 .htotal = 240 + 16 + 7 + 5, 2846 .vdisplay = 320, 2847 .vsync_start = 320 + 9, 2848 .vsync_end = 320 + 9 + 1, 2849 .vtotal = 320 + 9 + 1 + 7, 2850 .vrefresh = 60, 2851 }; 2852 2853 static const struct panel_desc sharp_lq035q7db03 = { 2854 .modes = &sharp_lq035q7db03_mode, 2855 .num_modes = 1, 2856 .bpc = 6, 2857 .size = { 2858 .width = 54, 2859 .height = 72, 2860 }, 2861 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2862 }; 2863 2864 static const struct display_timing sharp_lq101k1ly04_timing = { 2865 .pixelclock = { 60000000, 65000000, 80000000 }, 2866 .hactive = { 1280, 1280, 1280 }, 2867 .hfront_porch = { 20, 20, 20 }, 2868 .hback_porch = { 20, 20, 20 }, 2869 .hsync_len = { 10, 10, 10 }, 2870 .vactive = { 800, 800, 800 }, 2871 .vfront_porch = { 4, 4, 4 }, 2872 .vback_porch = { 4, 4, 4 }, 2873 .vsync_len = { 4, 4, 4 }, 2874 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2875 }; 2876 2877 static const struct panel_desc sharp_lq101k1ly04 = { 2878 .timings = &sharp_lq101k1ly04_timing, 2879 .num_timings = 1, 2880 .bpc = 8, 2881 .size = { 2882 .width = 217, 2883 .height = 136, 2884 }, 2885 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2886 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2887 }; 2888 2889 static const struct display_timing sharp_lq123p1jx31_timing = { 2890 .pixelclock = { 252750000, 252750000, 266604720 }, 2891 .hactive = { 2400, 2400, 2400 }, 2892 .hfront_porch = { 48, 48, 48 }, 2893 .hback_porch = { 80, 80, 84 }, 2894 .hsync_len = { 32, 32, 32 }, 2895 .vactive = { 1600, 1600, 1600 }, 2896 .vfront_porch = { 3, 3, 3 }, 2897 .vback_porch = { 33, 33, 120 }, 2898 .vsync_len = { 10, 10, 10 }, 2899 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2900 }; 2901 2902 static const struct panel_desc sharp_lq123p1jx31 = { 2903 .timings = &sharp_lq123p1jx31_timing, 2904 .num_timings = 1, 2905 .bpc = 8, 2906 .size = { 2907 .width = 259, 2908 .height = 173, 2909 }, 2910 .delay = { 2911 .prepare = 110, 2912 .enable = 50, 2913 .unprepare = 550, 2914 }, 2915 }; 2916 2917 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2918 .clock = 71100, 2919 .hdisplay = 1024, 2920 .hsync_start = 1024 + 168, 2921 .hsync_end = 1024 + 168 + 64, 2922 .htotal = 1024 + 168 + 64 + 88, 2923 .vdisplay = 768, 2924 .vsync_start = 768 + 37, 2925 .vsync_end = 768 + 37 + 2, 2926 .vtotal = 768 + 37 + 2 + 8, 2927 .vrefresh = 60, 2928 }; 2929 2930 static const struct panel_desc sharp_lq150x1lg11 = { 2931 .modes = &sharp_lq150x1lg11_mode, 2932 .num_modes = 1, 2933 .bpc = 6, 2934 .size = { 2935 .width = 304, 2936 .height = 228, 2937 }, 2938 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2939 }; 2940 2941 static const struct display_timing sharp_ls020b1dd01d_timing = { 2942 .pixelclock = { 2000000, 4200000, 5000000 }, 2943 .hactive = { 240, 240, 240 }, 2944 .hfront_porch = { 66, 66, 66 }, 2945 .hback_porch = { 1, 1, 1 }, 2946 .hsync_len = { 1, 1, 1 }, 2947 .vactive = { 160, 160, 160 }, 2948 .vfront_porch = { 52, 52, 52 }, 2949 .vback_porch = { 6, 6, 6 }, 2950 .vsync_len = { 10, 10, 10 }, 2951 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 2952 }; 2953 2954 static const struct panel_desc sharp_ls020b1dd01d = { 2955 .timings = &sharp_ls020b1dd01d_timing, 2956 .num_timings = 1, 2957 .bpc = 6, 2958 .size = { 2959 .width = 42, 2960 .height = 28, 2961 }, 2962 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2963 .bus_flags = DRM_BUS_FLAG_DE_HIGH 2964 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 2965 | DRM_BUS_FLAG_SHARP_SIGNALS, 2966 }; 2967 2968 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2969 .clock = 33300, 2970 .hdisplay = 800, 2971 .hsync_start = 800 + 1, 2972 .hsync_end = 800 + 1 + 64, 2973 .htotal = 800 + 1 + 64 + 64, 2974 .vdisplay = 480, 2975 .vsync_start = 480 + 1, 2976 .vsync_end = 480 + 1 + 23, 2977 .vtotal = 480 + 1 + 23 + 22, 2978 .vrefresh = 60, 2979 }; 2980 2981 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2982 .modes = &shelly_sca07010_bfn_lnn_mode, 2983 .num_modes = 1, 2984 .size = { 2985 .width = 152, 2986 .height = 91, 2987 }, 2988 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2989 }; 2990 2991 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2992 .clock = 147000, 2993 .hdisplay = 1920, 2994 .hsync_start = 1920 + 16, 2995 .hsync_end = 1920 + 16 + 16, 2996 .htotal = 1920 + 16 + 16 + 32, 2997 .vdisplay = 1200, 2998 .vsync_start = 1200 + 15, 2999 .vsync_end = 1200 + 15 + 2, 3000 .vtotal = 1200 + 15 + 2 + 18, 3001 .vrefresh = 60, 3002 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3003 }; 3004 3005 static const struct panel_desc starry_kr122ea0sra = { 3006 .modes = &starry_kr122ea0sra_mode, 3007 .num_modes = 1, 3008 .size = { 3009 .width = 263, 3010 .height = 164, 3011 }, 3012 .delay = { 3013 .prepare = 10 + 200, 3014 .enable = 50, 3015 .unprepare = 10 + 500, 3016 }, 3017 }; 3018 3019 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3020 .clock = 30000, 3021 .hdisplay = 800, 3022 .hsync_start = 800 + 39, 3023 .hsync_end = 800 + 39 + 47, 3024 .htotal = 800 + 39 + 47 + 39, 3025 .vdisplay = 480, 3026 .vsync_start = 480 + 13, 3027 .vsync_end = 480 + 13 + 2, 3028 .vtotal = 480 + 13 + 2 + 29, 3029 .vrefresh = 62, 3030 }; 3031 3032 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3033 .modes = &tfc_s9700rtwv43tr_01b_mode, 3034 .num_modes = 1, 3035 .bpc = 8, 3036 .size = { 3037 .width = 155, 3038 .height = 90, 3039 }, 3040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3041 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3042 }; 3043 3044 static const struct display_timing tianma_tm070jdhg30_timing = { 3045 .pixelclock = { 62600000, 68200000, 78100000 }, 3046 .hactive = { 1280, 1280, 1280 }, 3047 .hfront_porch = { 15, 64, 159 }, 3048 .hback_porch = { 5, 5, 5 }, 3049 .hsync_len = { 1, 1, 256 }, 3050 .vactive = { 800, 800, 800 }, 3051 .vfront_porch = { 3, 40, 99 }, 3052 .vback_porch = { 2, 2, 2 }, 3053 .vsync_len = { 1, 1, 128 }, 3054 .flags = DISPLAY_FLAGS_DE_HIGH, 3055 }; 3056 3057 static const struct panel_desc tianma_tm070jdhg30 = { 3058 .timings = &tianma_tm070jdhg30_timing, 3059 .num_timings = 1, 3060 .bpc = 8, 3061 .size = { 3062 .width = 151, 3063 .height = 95, 3064 }, 3065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3066 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3067 }; 3068 3069 static const struct display_timing tianma_tm070rvhg71_timing = { 3070 .pixelclock = { 27700000, 29200000, 39600000 }, 3071 .hactive = { 800, 800, 800 }, 3072 .hfront_porch = { 12, 40, 212 }, 3073 .hback_porch = { 88, 88, 88 }, 3074 .hsync_len = { 1, 1, 40 }, 3075 .vactive = { 480, 480, 480 }, 3076 .vfront_porch = { 1, 13, 88 }, 3077 .vback_porch = { 32, 32, 32 }, 3078 .vsync_len = { 1, 1, 3 }, 3079 .flags = DISPLAY_FLAGS_DE_HIGH, 3080 }; 3081 3082 static const struct panel_desc tianma_tm070rvhg71 = { 3083 .timings = &tianma_tm070rvhg71_timing, 3084 .num_timings = 1, 3085 .bpc = 8, 3086 .size = { 3087 .width = 154, 3088 .height = 86, 3089 }, 3090 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3091 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3092 }; 3093 3094 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3095 { 3096 .clock = 10000, 3097 .hdisplay = 320, 3098 .hsync_start = 320 + 50, 3099 .hsync_end = 320 + 50 + 6, 3100 .htotal = 320 + 50 + 6 + 38, 3101 .vdisplay = 240, 3102 .vsync_start = 240 + 3, 3103 .vsync_end = 240 + 3 + 1, 3104 .vtotal = 240 + 3 + 1 + 17, 3105 .vrefresh = 60, 3106 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3107 }, 3108 }; 3109 3110 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3111 .modes = ti_nspire_cx_lcd_mode, 3112 .num_modes = 1, 3113 .bpc = 8, 3114 .size = { 3115 .width = 65, 3116 .height = 49, 3117 }, 3118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3119 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3120 }; 3121 3122 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3123 { 3124 .clock = 10000, 3125 .hdisplay = 320, 3126 .hsync_start = 320 + 6, 3127 .hsync_end = 320 + 6 + 6, 3128 .htotal = 320 + 6 + 6 + 6, 3129 .vdisplay = 240, 3130 .vsync_start = 240 + 0, 3131 .vsync_end = 240 + 0 + 1, 3132 .vtotal = 240 + 0 + 1 + 0, 3133 .vrefresh = 60, 3134 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3135 }, 3136 }; 3137 3138 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3139 .modes = ti_nspire_classic_lcd_mode, 3140 .num_modes = 1, 3141 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3142 .bpc = 8, 3143 .size = { 3144 .width = 71, 3145 .height = 53, 3146 }, 3147 /* This is the grayscale bus format */ 3148 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3149 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3150 }; 3151 3152 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3153 .clock = 79500, 3154 .hdisplay = 1280, 3155 .hsync_start = 1280 + 192, 3156 .hsync_end = 1280 + 192 + 128, 3157 .htotal = 1280 + 192 + 128 + 64, 3158 .vdisplay = 768, 3159 .vsync_start = 768 + 20, 3160 .vsync_end = 768 + 20 + 7, 3161 .vtotal = 768 + 20 + 7 + 3, 3162 .vrefresh = 60, 3163 }; 3164 3165 static const struct panel_desc toshiba_lt089ac29000 = { 3166 .modes = &toshiba_lt089ac29000_mode, 3167 .num_modes = 1, 3168 .size = { 3169 .width = 194, 3170 .height = 116, 3171 }, 3172 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3173 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3174 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3175 }; 3176 3177 static const struct drm_display_mode tpk_f07a_0102_mode = { 3178 .clock = 33260, 3179 .hdisplay = 800, 3180 .hsync_start = 800 + 40, 3181 .hsync_end = 800 + 40 + 128, 3182 .htotal = 800 + 40 + 128 + 88, 3183 .vdisplay = 480, 3184 .vsync_start = 480 + 10, 3185 .vsync_end = 480 + 10 + 2, 3186 .vtotal = 480 + 10 + 2 + 33, 3187 .vrefresh = 60, 3188 }; 3189 3190 static const struct panel_desc tpk_f07a_0102 = { 3191 .modes = &tpk_f07a_0102_mode, 3192 .num_modes = 1, 3193 .size = { 3194 .width = 152, 3195 .height = 91, 3196 }, 3197 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3198 }; 3199 3200 static const struct drm_display_mode tpk_f10a_0102_mode = { 3201 .clock = 45000, 3202 .hdisplay = 1024, 3203 .hsync_start = 1024 + 176, 3204 .hsync_end = 1024 + 176 + 5, 3205 .htotal = 1024 + 176 + 5 + 88, 3206 .vdisplay = 600, 3207 .vsync_start = 600 + 20, 3208 .vsync_end = 600 + 20 + 5, 3209 .vtotal = 600 + 20 + 5 + 25, 3210 .vrefresh = 60, 3211 }; 3212 3213 static const struct panel_desc tpk_f10a_0102 = { 3214 .modes = &tpk_f10a_0102_mode, 3215 .num_modes = 1, 3216 .size = { 3217 .width = 223, 3218 .height = 125, 3219 }, 3220 }; 3221 3222 static const struct display_timing urt_umsh_8596md_timing = { 3223 .pixelclock = { 33260000, 33260000, 33260000 }, 3224 .hactive = { 800, 800, 800 }, 3225 .hfront_porch = { 41, 41, 41 }, 3226 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3227 .hsync_len = { 71, 128, 128 }, 3228 .vactive = { 480, 480, 480 }, 3229 .vfront_porch = { 10, 10, 10 }, 3230 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3231 .vsync_len = { 2, 2, 2 }, 3232 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3233 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3234 }; 3235 3236 static const struct panel_desc urt_umsh_8596md_lvds = { 3237 .timings = &urt_umsh_8596md_timing, 3238 .num_timings = 1, 3239 .bpc = 6, 3240 .size = { 3241 .width = 152, 3242 .height = 91, 3243 }, 3244 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3246 }; 3247 3248 static const struct panel_desc urt_umsh_8596md_parallel = { 3249 .timings = &urt_umsh_8596md_timing, 3250 .num_timings = 1, 3251 .bpc = 6, 3252 .size = { 3253 .width = 152, 3254 .height = 91, 3255 }, 3256 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3257 }; 3258 3259 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3260 .clock = 33333, 3261 .hdisplay = 800, 3262 .hsync_start = 800 + 210, 3263 .hsync_end = 800 + 210 + 20, 3264 .htotal = 800 + 210 + 20 + 46, 3265 .vdisplay = 480, 3266 .vsync_start = 480 + 22, 3267 .vsync_end = 480 + 22 + 10, 3268 .vtotal = 480 + 22 + 10 + 23, 3269 .vrefresh = 60, 3270 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3271 }; 3272 3273 static const struct panel_desc vl050_8048nt_c01 = { 3274 .modes = &vl050_8048nt_c01_mode, 3275 .num_modes = 1, 3276 .bpc = 8, 3277 .size = { 3278 .width = 120, 3279 .height = 76, 3280 }, 3281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3283 }; 3284 3285 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3286 .clock = 6410, 3287 .hdisplay = 320, 3288 .hsync_start = 320 + 20, 3289 .hsync_end = 320 + 20 + 30, 3290 .htotal = 320 + 20 + 30 + 38, 3291 .vdisplay = 240, 3292 .vsync_start = 240 + 4, 3293 .vsync_end = 240 + 4 + 3, 3294 .vtotal = 240 + 4 + 3 + 15, 3295 .vrefresh = 60, 3296 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3297 }; 3298 3299 static const struct panel_desc winstar_wf35ltiacd = { 3300 .modes = &winstar_wf35ltiacd_mode, 3301 .num_modes = 1, 3302 .bpc = 8, 3303 .size = { 3304 .width = 70, 3305 .height = 53, 3306 }, 3307 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3308 }; 3309 3310 static const struct drm_display_mode arm_rtsm_mode[] = { 3311 { 3312 .clock = 65000, 3313 .hdisplay = 1024, 3314 .hsync_start = 1024 + 24, 3315 .hsync_end = 1024 + 24 + 136, 3316 .htotal = 1024 + 24 + 136 + 160, 3317 .vdisplay = 768, 3318 .vsync_start = 768 + 3, 3319 .vsync_end = 768 + 3 + 6, 3320 .vtotal = 768 + 3 + 6 + 29, 3321 .vrefresh = 60, 3322 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3323 }, 3324 }; 3325 3326 static const struct panel_desc arm_rtsm = { 3327 .modes = arm_rtsm_mode, 3328 .num_modes = 1, 3329 .bpc = 8, 3330 .size = { 3331 .width = 400, 3332 .height = 300, 3333 }, 3334 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3335 }; 3336 3337 static const struct of_device_id platform_of_match[] = { 3338 { 3339 .compatible = "ampire,am-480272h3tmqw-t01h", 3340 .data = &ire_am_480272h3tmqw_t01h, 3341 }, { 3342 .compatible = "ampire,am800480r3tmqwa1h", 3343 .data = &ire_am800480r3tmqwa1h, 3344 }, { 3345 .compatible = "arm,rtsm-display", 3346 .data = &arm_rtsm, 3347 }, { 3348 .compatible = "armadeus,st0700-adapt", 3349 .data = &armadeus_st0700_adapt, 3350 }, { 3351 .compatible = "auo,b101aw03", 3352 .data = &auo_b101aw03, 3353 }, { 3354 .compatible = "auo,b101ean01", 3355 .data = &auo_b101ean01, 3356 }, { 3357 .compatible = "auo,b101xtn01", 3358 .data = &auo_b101xtn01, 3359 }, { 3360 .compatible = "auo,b116xa01", 3361 .data = &auo_b116xak01, 3362 }, { 3363 .compatible = "auo,b116xw03", 3364 .data = &auo_b116xw03, 3365 }, { 3366 .compatible = "auo,b133htn01", 3367 .data = &auo_b133htn01, 3368 }, { 3369 .compatible = "auo,b133xtn01", 3370 .data = &auo_b133xtn01, 3371 }, { 3372 .compatible = "auo,g070vvn01", 3373 .data = &auo_g070vvn01, 3374 }, { 3375 .compatible = "auo,g101evn010", 3376 .data = &auo_g101evn010, 3377 }, { 3378 .compatible = "auo,g104sn02", 3379 .data = &auo_g104sn02, 3380 }, { 3381 .compatible = "auo,g133han01", 3382 .data = &auo_g133han01, 3383 }, { 3384 .compatible = "auo,g185han01", 3385 .data = &auo_g185han01, 3386 }, { 3387 .compatible = "auo,p320hvn03", 3388 .data = &auo_p320hvn03, 3389 }, { 3390 .compatible = "auo,t215hvn01", 3391 .data = &auo_t215hvn01, 3392 }, { 3393 .compatible = "avic,tm070ddh03", 3394 .data = &avic_tm070ddh03, 3395 }, { 3396 .compatible = "bananapi,s070wv20-ct16", 3397 .data = &bananapi_s070wv20_ct16, 3398 }, { 3399 .compatible = "boe,hv070wsa-100", 3400 .data = &boe_hv070wsa 3401 }, { 3402 .compatible = "boe,nv101wxmn51", 3403 .data = &boe_nv101wxmn51, 3404 }, { 3405 .compatible = "boe,nv140fhmn49", 3406 .data = &boe_nv140fhmn49, 3407 }, { 3408 .compatible = "cdtech,s043wq26h-ct7", 3409 .data = &cdtech_s043wq26h_ct7, 3410 }, { 3411 .compatible = "cdtech,s070wv95-ct16", 3412 .data = &cdtech_s070wv95_ct16, 3413 }, { 3414 .compatible = "chunghwa,claa070wp03xg", 3415 .data = &chunghwa_claa070wp03xg, 3416 }, { 3417 .compatible = "chunghwa,claa101wa01a", 3418 .data = &chunghwa_claa101wa01a 3419 }, { 3420 .compatible = "chunghwa,claa101wb01", 3421 .data = &chunghwa_claa101wb01 3422 }, { 3423 .compatible = "dataimage,scf0700c48ggu18", 3424 .data = &dataimage_scf0700c48ggu18, 3425 }, { 3426 .compatible = "dlc,dlc0700yzg-1", 3427 .data = &dlc_dlc0700yzg_1, 3428 }, { 3429 .compatible = "dlc,dlc1010gig", 3430 .data = &dlc_dlc1010gig, 3431 }, { 3432 .compatible = "edt,et035012dm6", 3433 .data = &edt_et035012dm6, 3434 }, { 3435 .compatible = "edt,etm043080dh6gp", 3436 .data = &edt_etm043080dh6gp, 3437 }, { 3438 .compatible = "edt,etm0430g0dh6", 3439 .data = &edt_etm0430g0dh6, 3440 }, { 3441 .compatible = "edt,et057090dhu", 3442 .data = &edt_et057090dhu, 3443 }, { 3444 .compatible = "edt,et070080dh6", 3445 .data = &edt_etm0700g0dh6, 3446 }, { 3447 .compatible = "edt,etm0700g0dh6", 3448 .data = &edt_etm0700g0dh6, 3449 }, { 3450 .compatible = "edt,etm0700g0bdh6", 3451 .data = &edt_etm0700g0bdh6, 3452 }, { 3453 .compatible = "edt,etm0700g0edh6", 3454 .data = &edt_etm0700g0bdh6, 3455 }, { 3456 .compatible = "evervision,vgg804821", 3457 .data = &evervision_vgg804821, 3458 }, { 3459 .compatible = "foxlink,fl500wvr00-a0t", 3460 .data = &foxlink_fl500wvr00_a0t, 3461 }, { 3462 .compatible = "frida,frd350h54004", 3463 .data = &frida_frd350h54004, 3464 }, { 3465 .compatible = "friendlyarm,hd702e", 3466 .data = &friendlyarm_hd702e, 3467 }, { 3468 .compatible = "giantplus,gpg482739qs5", 3469 .data = &giantplus_gpg482739qs5 3470 }, { 3471 .compatible = "giantplus,gpm940b0", 3472 .data = &giantplus_gpm940b0, 3473 }, { 3474 .compatible = "hannstar,hsd070pww1", 3475 .data = &hannstar_hsd070pww1, 3476 }, { 3477 .compatible = "hannstar,hsd100pxn1", 3478 .data = &hannstar_hsd100pxn1, 3479 }, { 3480 .compatible = "hit,tx23d38vm0caa", 3481 .data = &hitachi_tx23d38vm0caa 3482 }, { 3483 .compatible = "innolux,at043tn24", 3484 .data = &innolux_at043tn24, 3485 }, { 3486 .compatible = "innolux,at070tn92", 3487 .data = &innolux_at070tn92, 3488 }, { 3489 .compatible = "innolux,g070y2-l01", 3490 .data = &innolux_g070y2_l01, 3491 }, { 3492 .compatible = "innolux,g101ice-l01", 3493 .data = &innolux_g101ice_l01 3494 }, { 3495 .compatible = "innolux,g121i1-l01", 3496 .data = &innolux_g121i1_l01 3497 }, { 3498 .compatible = "innolux,g121x1-l03", 3499 .data = &innolux_g121x1_l03, 3500 }, { 3501 .compatible = "innolux,n116bge", 3502 .data = &innolux_n116bge, 3503 }, { 3504 .compatible = "innolux,n156bge-l21", 3505 .data = &innolux_n156bge_l21, 3506 }, { 3507 .compatible = "innolux,p120zdg-bf1", 3508 .data = &innolux_p120zdg_bf1, 3509 }, { 3510 .compatible = "innolux,zj070na-01p", 3511 .data = &innolux_zj070na_01p, 3512 }, { 3513 .compatible = "koe,tx14d24vm1bpa", 3514 .data = &koe_tx14d24vm1bpa, 3515 }, { 3516 .compatible = "koe,tx31d200vm0baa", 3517 .data = &koe_tx31d200vm0baa, 3518 }, { 3519 .compatible = "kyo,tcg121xglp", 3520 .data = &kyo_tcg121xglp, 3521 }, { 3522 .compatible = "lemaker,bl035-rgb-002", 3523 .data = &lemaker_bl035_rgb_002, 3524 }, { 3525 .compatible = "lg,lb070wv8", 3526 .data = &lg_lb070wv8, 3527 }, { 3528 .compatible = "lg,lp079qx1-sp0v", 3529 .data = &lg_lp079qx1_sp0v, 3530 }, { 3531 .compatible = "lg,lp097qx1-spa1", 3532 .data = &lg_lp097qx1_spa1, 3533 }, { 3534 .compatible = "lg,lp120up1", 3535 .data = &lg_lp120up1, 3536 }, { 3537 .compatible = "lg,lp129qe", 3538 .data = &lg_lp129qe, 3539 }, { 3540 .compatible = "logicpd,type28", 3541 .data = &logicpd_type_28, 3542 }, { 3543 .compatible = "logictechno,lt161010-2nhc", 3544 .data = &logictechno_lt161010_2nh, 3545 }, { 3546 .compatible = "logictechno,lt161010-2nhr", 3547 .data = &logictechno_lt161010_2nh, 3548 }, { 3549 .compatible = "logictechno,lt170410-2whc", 3550 .data = &logictechno_lt170410_2whc, 3551 }, { 3552 .compatible = "mitsubishi,aa070mc01-ca1", 3553 .data = &mitsubishi_aa070mc01, 3554 }, { 3555 .compatible = "nec,nl12880bc20-05", 3556 .data = &nec_nl12880bc20_05, 3557 }, { 3558 .compatible = "nec,nl4827hc19-05b", 3559 .data = &nec_nl4827hc19_05b, 3560 }, { 3561 .compatible = "netron-dy,e231732", 3562 .data = &netron_dy_e231732, 3563 }, { 3564 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3565 .data = &newhaven_nhd_43_480272ef_atxl, 3566 }, { 3567 .compatible = "nlt,nl192108ac18-02d", 3568 .data = &nlt_nl192108ac18_02d, 3569 }, { 3570 .compatible = "nvd,9128", 3571 .data = &nvd_9128, 3572 }, { 3573 .compatible = "okaya,rs800480t-7x0gp", 3574 .data = &okaya_rs800480t_7x0gp, 3575 }, { 3576 .compatible = "olimex,lcd-olinuxino-43-ts", 3577 .data = &olimex_lcd_olinuxino_43ts, 3578 }, { 3579 .compatible = "ontat,yx700wv03", 3580 .data = &ontat_yx700wv03, 3581 }, { 3582 .compatible = "ortustech,com37h3m05dtc", 3583 .data = &ortustech_com37h3m, 3584 }, { 3585 .compatible = "ortustech,com37h3m99dtc", 3586 .data = &ortustech_com37h3m, 3587 }, { 3588 .compatible = "ortustech,com43h4m85ulc", 3589 .data = &ortustech_com43h4m85ulc, 3590 }, { 3591 .compatible = "osddisplays,osd070t1718-19ts", 3592 .data = &osddisplays_osd070t1718_19ts, 3593 }, { 3594 .compatible = "pda,91-00156-a0", 3595 .data = &pda_91_00156_a0, 3596 }, { 3597 .compatible = "qiaodian,qd43003c0-40", 3598 .data = &qd43003c0_40, 3599 }, { 3600 .compatible = "rocktech,rk070er9427", 3601 .data = &rocktech_rk070er9427, 3602 }, { 3603 .compatible = "rocktech,rk101ii01d-ct", 3604 .data = &rocktech_rk101ii01d_ct, 3605 }, { 3606 .compatible = "samsung,lsn122dl01-c01", 3607 .data = &samsung_lsn122dl01_c01, 3608 }, { 3609 .compatible = "samsung,ltn101nt05", 3610 .data = &samsung_ltn101nt05, 3611 }, { 3612 .compatible = "samsung,ltn140at29-301", 3613 .data = &samsung_ltn140at29_301, 3614 }, { 3615 .compatible = "satoz,sat050at40h12r2", 3616 .data = &satoz_sat050at40h12r2, 3617 }, { 3618 .compatible = "sharp,ld-d5116z01b", 3619 .data = &sharp_ld_d5116z01b, 3620 }, { 3621 .compatible = "sharp,lq035q7db03", 3622 .data = &sharp_lq035q7db03, 3623 }, { 3624 .compatible = "sharp,lq070y3dg3b", 3625 .data = &sharp_lq070y3dg3b, 3626 }, { 3627 .compatible = "sharp,lq101k1ly04", 3628 .data = &sharp_lq101k1ly04, 3629 }, { 3630 .compatible = "sharp,lq123p1jx31", 3631 .data = &sharp_lq123p1jx31, 3632 }, { 3633 .compatible = "sharp,lq150x1lg11", 3634 .data = &sharp_lq150x1lg11, 3635 }, { 3636 .compatible = "sharp,ls020b1dd01d", 3637 .data = &sharp_ls020b1dd01d, 3638 }, { 3639 .compatible = "shelly,sca07010-bfn-lnn", 3640 .data = &shelly_sca07010_bfn_lnn, 3641 }, { 3642 .compatible = "starry,kr122ea0sra", 3643 .data = &starry_kr122ea0sra, 3644 }, { 3645 .compatible = "tfc,s9700rtwv43tr-01b", 3646 .data = &tfc_s9700rtwv43tr_01b, 3647 }, { 3648 .compatible = "tianma,tm070jdhg30", 3649 .data = &tianma_tm070jdhg30, 3650 }, { 3651 .compatible = "tianma,tm070rvhg71", 3652 .data = &tianma_tm070rvhg71, 3653 }, { 3654 .compatible = "ti,nspire-cx-lcd-panel", 3655 .data = &ti_nspire_cx_lcd_panel, 3656 }, { 3657 .compatible = "ti,nspire-classic-lcd-panel", 3658 .data = &ti_nspire_classic_lcd_panel, 3659 }, { 3660 .compatible = "toshiba,lt089ac29000", 3661 .data = &toshiba_lt089ac29000, 3662 }, { 3663 .compatible = "tpk,f07a-0102", 3664 .data = &tpk_f07a_0102, 3665 }, { 3666 .compatible = "tpk,f10a-0102", 3667 .data = &tpk_f10a_0102, 3668 }, { 3669 .compatible = "urt,umsh-8596md-t", 3670 .data = &urt_umsh_8596md_parallel, 3671 }, { 3672 .compatible = "urt,umsh-8596md-1t", 3673 .data = &urt_umsh_8596md_parallel, 3674 }, { 3675 .compatible = "urt,umsh-8596md-7t", 3676 .data = &urt_umsh_8596md_parallel, 3677 }, { 3678 .compatible = "urt,umsh-8596md-11t", 3679 .data = &urt_umsh_8596md_lvds, 3680 }, { 3681 .compatible = "urt,umsh-8596md-19t", 3682 .data = &urt_umsh_8596md_lvds, 3683 }, { 3684 .compatible = "urt,umsh-8596md-20t", 3685 .data = &urt_umsh_8596md_parallel, 3686 }, { 3687 .compatible = "vxt,vl050-8048nt-c01", 3688 .data = &vl050_8048nt_c01, 3689 }, { 3690 .compatible = "winstar,wf35ltiacd", 3691 .data = &winstar_wf35ltiacd, 3692 }, { 3693 /* sentinel */ 3694 } 3695 }; 3696 MODULE_DEVICE_TABLE(of, platform_of_match); 3697 3698 static int panel_simple_platform_probe(struct platform_device *pdev) 3699 { 3700 const struct of_device_id *id; 3701 3702 id = of_match_node(platform_of_match, pdev->dev.of_node); 3703 if (!id) 3704 return -ENODEV; 3705 3706 return panel_simple_probe(&pdev->dev, id->data); 3707 } 3708 3709 static int panel_simple_platform_remove(struct platform_device *pdev) 3710 { 3711 return panel_simple_remove(&pdev->dev); 3712 } 3713 3714 static void panel_simple_platform_shutdown(struct platform_device *pdev) 3715 { 3716 panel_simple_shutdown(&pdev->dev); 3717 } 3718 3719 static struct platform_driver panel_simple_platform_driver = { 3720 .driver = { 3721 .name = "panel-simple", 3722 .of_match_table = platform_of_match, 3723 }, 3724 .probe = panel_simple_platform_probe, 3725 .remove = panel_simple_platform_remove, 3726 .shutdown = panel_simple_platform_shutdown, 3727 }; 3728 3729 struct panel_desc_dsi { 3730 struct panel_desc desc; 3731 3732 unsigned long flags; 3733 enum mipi_dsi_pixel_format format; 3734 unsigned int lanes; 3735 }; 3736 3737 static const struct drm_display_mode auo_b080uan01_mode = { 3738 .clock = 154500, 3739 .hdisplay = 1200, 3740 .hsync_start = 1200 + 62, 3741 .hsync_end = 1200 + 62 + 4, 3742 .htotal = 1200 + 62 + 4 + 62, 3743 .vdisplay = 1920, 3744 .vsync_start = 1920 + 9, 3745 .vsync_end = 1920 + 9 + 2, 3746 .vtotal = 1920 + 9 + 2 + 8, 3747 .vrefresh = 60, 3748 }; 3749 3750 static const struct panel_desc_dsi auo_b080uan01 = { 3751 .desc = { 3752 .modes = &auo_b080uan01_mode, 3753 .num_modes = 1, 3754 .bpc = 8, 3755 .size = { 3756 .width = 108, 3757 .height = 272, 3758 }, 3759 }, 3760 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3761 .format = MIPI_DSI_FMT_RGB888, 3762 .lanes = 4, 3763 }; 3764 3765 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 3766 .clock = 160000, 3767 .hdisplay = 1200, 3768 .hsync_start = 1200 + 120, 3769 .hsync_end = 1200 + 120 + 20, 3770 .htotal = 1200 + 120 + 20 + 21, 3771 .vdisplay = 1920, 3772 .vsync_start = 1920 + 21, 3773 .vsync_end = 1920 + 21 + 3, 3774 .vtotal = 1920 + 21 + 3 + 18, 3775 .vrefresh = 60, 3776 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3777 }; 3778 3779 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 3780 .desc = { 3781 .modes = &boe_tv080wum_nl0_mode, 3782 .num_modes = 1, 3783 .size = { 3784 .width = 107, 3785 .height = 172, 3786 }, 3787 }, 3788 .flags = MIPI_DSI_MODE_VIDEO | 3789 MIPI_DSI_MODE_VIDEO_BURST | 3790 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 3791 .format = MIPI_DSI_FMT_RGB888, 3792 .lanes = 4, 3793 }; 3794 3795 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 3796 .clock = 71000, 3797 .hdisplay = 800, 3798 .hsync_start = 800 + 32, 3799 .hsync_end = 800 + 32 + 1, 3800 .htotal = 800 + 32 + 1 + 57, 3801 .vdisplay = 1280, 3802 .vsync_start = 1280 + 28, 3803 .vsync_end = 1280 + 28 + 1, 3804 .vtotal = 1280 + 28 + 1 + 14, 3805 .vrefresh = 60, 3806 }; 3807 3808 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 3809 .desc = { 3810 .modes = &lg_ld070wx3_sl01_mode, 3811 .num_modes = 1, 3812 .bpc = 8, 3813 .size = { 3814 .width = 94, 3815 .height = 151, 3816 }, 3817 }, 3818 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3819 .format = MIPI_DSI_FMT_RGB888, 3820 .lanes = 4, 3821 }; 3822 3823 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 3824 .clock = 67000, 3825 .hdisplay = 720, 3826 .hsync_start = 720 + 12, 3827 .hsync_end = 720 + 12 + 4, 3828 .htotal = 720 + 12 + 4 + 112, 3829 .vdisplay = 1280, 3830 .vsync_start = 1280 + 8, 3831 .vsync_end = 1280 + 8 + 4, 3832 .vtotal = 1280 + 8 + 4 + 12, 3833 .vrefresh = 60, 3834 }; 3835 3836 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 3837 .desc = { 3838 .modes = &lg_lh500wx1_sd03_mode, 3839 .num_modes = 1, 3840 .bpc = 8, 3841 .size = { 3842 .width = 62, 3843 .height = 110, 3844 }, 3845 }, 3846 .flags = MIPI_DSI_MODE_VIDEO, 3847 .format = MIPI_DSI_FMT_RGB888, 3848 .lanes = 4, 3849 }; 3850 3851 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 3852 .clock = 157200, 3853 .hdisplay = 1920, 3854 .hsync_start = 1920 + 154, 3855 .hsync_end = 1920 + 154 + 16, 3856 .htotal = 1920 + 154 + 16 + 32, 3857 .vdisplay = 1200, 3858 .vsync_start = 1200 + 17, 3859 .vsync_end = 1200 + 17 + 2, 3860 .vtotal = 1200 + 17 + 2 + 16, 3861 .vrefresh = 60, 3862 }; 3863 3864 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 3865 .desc = { 3866 .modes = &panasonic_vvx10f004b00_mode, 3867 .num_modes = 1, 3868 .bpc = 8, 3869 .size = { 3870 .width = 217, 3871 .height = 136, 3872 }, 3873 }, 3874 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3875 MIPI_DSI_CLOCK_NON_CONTINUOUS, 3876 .format = MIPI_DSI_FMT_RGB888, 3877 .lanes = 4, 3878 }; 3879 3880 static const struct drm_display_mode lg_acx467akm_7_mode = { 3881 .clock = 150000, 3882 .hdisplay = 1080, 3883 .hsync_start = 1080 + 2, 3884 .hsync_end = 1080 + 2 + 2, 3885 .htotal = 1080 + 2 + 2 + 2, 3886 .vdisplay = 1920, 3887 .vsync_start = 1920 + 2, 3888 .vsync_end = 1920 + 2 + 2, 3889 .vtotal = 1920 + 2 + 2 + 2, 3890 .vrefresh = 60, 3891 }; 3892 3893 static const struct panel_desc_dsi lg_acx467akm_7 = { 3894 .desc = { 3895 .modes = &lg_acx467akm_7_mode, 3896 .num_modes = 1, 3897 .bpc = 8, 3898 .size = { 3899 .width = 62, 3900 .height = 110, 3901 }, 3902 }, 3903 .flags = 0, 3904 .format = MIPI_DSI_FMT_RGB888, 3905 .lanes = 4, 3906 }; 3907 3908 static const struct drm_display_mode osd101t2045_53ts_mode = { 3909 .clock = 154500, 3910 .hdisplay = 1920, 3911 .hsync_start = 1920 + 112, 3912 .hsync_end = 1920 + 112 + 16, 3913 .htotal = 1920 + 112 + 16 + 32, 3914 .vdisplay = 1200, 3915 .vsync_start = 1200 + 16, 3916 .vsync_end = 1200 + 16 + 2, 3917 .vtotal = 1200 + 16 + 2 + 16, 3918 .vrefresh = 60, 3919 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3920 }; 3921 3922 static const struct panel_desc_dsi osd101t2045_53ts = { 3923 .desc = { 3924 .modes = &osd101t2045_53ts_mode, 3925 .num_modes = 1, 3926 .bpc = 8, 3927 .size = { 3928 .width = 217, 3929 .height = 136, 3930 }, 3931 }, 3932 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 3933 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3934 MIPI_DSI_MODE_EOT_PACKET, 3935 .format = MIPI_DSI_FMT_RGB888, 3936 .lanes = 4, 3937 }; 3938 3939 static const struct of_device_id dsi_of_match[] = { 3940 { 3941 .compatible = "auo,b080uan01", 3942 .data = &auo_b080uan01 3943 }, { 3944 .compatible = "boe,tv080wum-nl0", 3945 .data = &boe_tv080wum_nl0 3946 }, { 3947 .compatible = "lg,ld070wx3-sl01", 3948 .data = &lg_ld070wx3_sl01 3949 }, { 3950 .compatible = "lg,lh500wx1-sd03", 3951 .data = &lg_lh500wx1_sd03 3952 }, { 3953 .compatible = "panasonic,vvx10f004b00", 3954 .data = &panasonic_vvx10f004b00 3955 }, { 3956 .compatible = "lg,acx467akm-7", 3957 .data = &lg_acx467akm_7 3958 }, { 3959 .compatible = "osddisplays,osd101t2045-53ts", 3960 .data = &osd101t2045_53ts 3961 }, { 3962 /* sentinel */ 3963 } 3964 }; 3965 MODULE_DEVICE_TABLE(of, dsi_of_match); 3966 3967 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 3968 { 3969 const struct panel_desc_dsi *desc; 3970 const struct of_device_id *id; 3971 int err; 3972 3973 id = of_match_node(dsi_of_match, dsi->dev.of_node); 3974 if (!id) 3975 return -ENODEV; 3976 3977 desc = id->data; 3978 3979 err = panel_simple_probe(&dsi->dev, &desc->desc); 3980 if (err < 0) 3981 return err; 3982 3983 dsi->mode_flags = desc->flags; 3984 dsi->format = desc->format; 3985 dsi->lanes = desc->lanes; 3986 3987 err = mipi_dsi_attach(dsi); 3988 if (err) { 3989 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 3990 3991 drm_panel_remove(&panel->base); 3992 } 3993 3994 return err; 3995 } 3996 3997 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 3998 { 3999 int err; 4000 4001 err = mipi_dsi_detach(dsi); 4002 if (err < 0) 4003 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4004 4005 return panel_simple_remove(&dsi->dev); 4006 } 4007 4008 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4009 { 4010 panel_simple_shutdown(&dsi->dev); 4011 } 4012 4013 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4014 .driver = { 4015 .name = "panel-simple-dsi", 4016 .of_match_table = dsi_of_match, 4017 }, 4018 .probe = panel_simple_dsi_probe, 4019 .remove = panel_simple_dsi_remove, 4020 .shutdown = panel_simple_dsi_shutdown, 4021 }; 4022 4023 static int __init panel_simple_init(void) 4024 { 4025 int err; 4026 4027 err = platform_driver_register(&panel_simple_platform_driver); 4028 if (err < 0) 4029 return err; 4030 4031 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4032 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4033 if (err < 0) 4034 return err; 4035 } 4036 4037 return 0; 4038 } 4039 module_init(panel_simple_init); 4040 4041 static void __exit panel_simple_exit(void) 4042 { 4043 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4044 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4045 4046 platform_driver_unregister(&panel_simple_platform_driver); 4047 } 4048 module_exit(panel_simple_exit); 4049 4050 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4051 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4052 MODULE_LICENSE("GPL and additional rights"); 4053