1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 60 * Plug Detect isn't used. 61 * @enable: the time (in milliseconds) that it takes for the panel to 62 * display the first valid frame after starting to receive 63 * video data 64 * @disable: the time (in milliseconds) that it takes for the panel to 65 * turn the display off (no content is visible) 66 * @unprepare: the time (in milliseconds) that it takes for the panel 67 * to power itself down completely 68 */ 69 struct { 70 unsigned int prepare; 71 unsigned int hpd_absent_delay; 72 unsigned int enable; 73 unsigned int disable; 74 unsigned int unprepare; 75 } delay; 76 77 u32 bus_format; 78 u32 bus_flags; 79 }; 80 81 struct panel_simple { 82 struct drm_panel base; 83 bool prepared; 84 bool enabled; 85 bool no_hpd; 86 87 const struct panel_desc *desc; 88 89 struct backlight_device *backlight; 90 struct regulator *supply; 91 struct i2c_adapter *ddc; 92 93 struct gpio_desc *enable_gpio; 94 }; 95 96 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 97 { 98 return container_of(panel, struct panel_simple, base); 99 } 100 101 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 102 { 103 struct drm_connector *connector = panel->base.connector; 104 struct drm_device *drm = panel->base.drm; 105 struct drm_display_mode *mode; 106 unsigned int i, num = 0; 107 108 if (!panel->desc) 109 return 0; 110 111 for (i = 0; i < panel->desc->num_timings; i++) { 112 const struct display_timing *dt = &panel->desc->timings[i]; 113 struct videomode vm; 114 115 videomode_from_timing(dt, &vm); 116 mode = drm_mode_create(drm); 117 if (!mode) { 118 dev_err(drm->dev, "failed to add mode %ux%u\n", 119 dt->hactive.typ, dt->vactive.typ); 120 continue; 121 } 122 123 drm_display_mode_from_videomode(&vm, mode); 124 125 mode->type |= DRM_MODE_TYPE_DRIVER; 126 127 if (panel->desc->num_timings == 1) 128 mode->type |= DRM_MODE_TYPE_PREFERRED; 129 130 drm_mode_probed_add(connector, mode); 131 num++; 132 } 133 134 for (i = 0; i < panel->desc->num_modes; i++) { 135 const struct drm_display_mode *m = &panel->desc->modes[i]; 136 137 mode = drm_mode_duplicate(drm, m); 138 if (!mode) { 139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 140 m->hdisplay, m->vdisplay, m->vrefresh); 141 continue; 142 } 143 144 mode->type |= DRM_MODE_TYPE_DRIVER; 145 146 if (panel->desc->num_modes == 1) 147 mode->type |= DRM_MODE_TYPE_PREFERRED; 148 149 drm_mode_set_name(mode); 150 151 drm_mode_probed_add(connector, mode); 152 num++; 153 } 154 155 connector->display_info.bpc = panel->desc->bpc; 156 connector->display_info.width_mm = panel->desc->size.width; 157 connector->display_info.height_mm = panel->desc->size.height; 158 if (panel->desc->bus_format) 159 drm_display_info_set_bus_formats(&connector->display_info, 160 &panel->desc->bus_format, 1); 161 connector->display_info.bus_flags = panel->desc->bus_flags; 162 163 return num; 164 } 165 166 static int panel_simple_disable(struct drm_panel *panel) 167 { 168 struct panel_simple *p = to_panel_simple(panel); 169 170 if (!p->enabled) 171 return 0; 172 173 if (p->backlight) { 174 p->backlight->props.power = FB_BLANK_POWERDOWN; 175 p->backlight->props.state |= BL_CORE_FBBLANK; 176 backlight_update_status(p->backlight); 177 } 178 179 if (p->desc->delay.disable) 180 msleep(p->desc->delay.disable); 181 182 p->enabled = false; 183 184 return 0; 185 } 186 187 static int panel_simple_unprepare(struct drm_panel *panel) 188 { 189 struct panel_simple *p = to_panel_simple(panel); 190 191 if (!p->prepared) 192 return 0; 193 194 gpiod_set_value_cansleep(p->enable_gpio, 0); 195 196 regulator_disable(p->supply); 197 198 if (p->desc->delay.unprepare) 199 msleep(p->desc->delay.unprepare); 200 201 p->prepared = false; 202 203 return 0; 204 } 205 206 static int panel_simple_prepare(struct drm_panel *panel) 207 { 208 struct panel_simple *p = to_panel_simple(panel); 209 unsigned int delay; 210 int err; 211 212 if (p->prepared) 213 return 0; 214 215 err = regulator_enable(p->supply); 216 if (err < 0) { 217 dev_err(panel->dev, "failed to enable supply: %d\n", err); 218 return err; 219 } 220 221 gpiod_set_value_cansleep(p->enable_gpio, 1); 222 223 delay = p->desc->delay.prepare; 224 if (p->no_hpd) 225 delay += p->desc->delay.hpd_absent_delay; 226 if (delay) 227 msleep(delay); 228 229 p->prepared = true; 230 231 return 0; 232 } 233 234 static int panel_simple_enable(struct drm_panel *panel) 235 { 236 struct panel_simple *p = to_panel_simple(panel); 237 238 if (p->enabled) 239 return 0; 240 241 if (p->desc->delay.enable) 242 msleep(p->desc->delay.enable); 243 244 if (p->backlight) { 245 p->backlight->props.state &= ~BL_CORE_FBBLANK; 246 p->backlight->props.power = FB_BLANK_UNBLANK; 247 backlight_update_status(p->backlight); 248 } 249 250 p->enabled = true; 251 252 return 0; 253 } 254 255 static int panel_simple_get_modes(struct drm_panel *panel) 256 { 257 struct panel_simple *p = to_panel_simple(panel); 258 int num = 0; 259 260 /* probe EDID if a DDC bus is available */ 261 if (p->ddc) { 262 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 263 drm_connector_update_edid_property(panel->connector, edid); 264 if (edid) { 265 num += drm_add_edid_modes(panel->connector, edid); 266 kfree(edid); 267 } 268 } 269 270 /* add hard-coded panel modes */ 271 num += panel_simple_get_fixed_modes(p); 272 273 return num; 274 } 275 276 static int panel_simple_get_timings(struct drm_panel *panel, 277 unsigned int num_timings, 278 struct display_timing *timings) 279 { 280 struct panel_simple *p = to_panel_simple(panel); 281 unsigned int i; 282 283 if (p->desc->num_timings < num_timings) 284 num_timings = p->desc->num_timings; 285 286 if (timings) 287 for (i = 0; i < num_timings; i++) 288 timings[i] = p->desc->timings[i]; 289 290 return p->desc->num_timings; 291 } 292 293 static const struct drm_panel_funcs panel_simple_funcs = { 294 .disable = panel_simple_disable, 295 .unprepare = panel_simple_unprepare, 296 .prepare = panel_simple_prepare, 297 .enable = panel_simple_enable, 298 .get_modes = panel_simple_get_modes, 299 .get_timings = panel_simple_get_timings, 300 }; 301 302 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 303 { 304 struct device_node *backlight, *ddc; 305 struct panel_simple *panel; 306 int err; 307 308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 309 if (!panel) 310 return -ENOMEM; 311 312 panel->enabled = false; 313 panel->prepared = false; 314 panel->desc = desc; 315 316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 317 318 panel->supply = devm_regulator_get(dev, "power"); 319 if (IS_ERR(panel->supply)) 320 return PTR_ERR(panel->supply); 321 322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 323 GPIOD_OUT_LOW); 324 if (IS_ERR(panel->enable_gpio)) { 325 err = PTR_ERR(panel->enable_gpio); 326 if (err != -EPROBE_DEFER) 327 dev_err(dev, "failed to request GPIO: %d\n", err); 328 return err; 329 } 330 331 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 332 if (backlight) { 333 panel->backlight = of_find_backlight_by_node(backlight); 334 of_node_put(backlight); 335 336 if (!panel->backlight) 337 return -EPROBE_DEFER; 338 } 339 340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 341 if (ddc) { 342 panel->ddc = of_find_i2c_adapter_by_node(ddc); 343 of_node_put(ddc); 344 345 if (!panel->ddc) { 346 err = -EPROBE_DEFER; 347 goto free_backlight; 348 } 349 } 350 351 drm_panel_init(&panel->base); 352 panel->base.dev = dev; 353 panel->base.funcs = &panel_simple_funcs; 354 355 err = drm_panel_add(&panel->base); 356 if (err < 0) 357 goto free_ddc; 358 359 dev_set_drvdata(dev, panel); 360 361 return 0; 362 363 free_ddc: 364 if (panel->ddc) 365 put_device(&panel->ddc->dev); 366 free_backlight: 367 if (panel->backlight) 368 put_device(&panel->backlight->dev); 369 370 return err; 371 } 372 373 static int panel_simple_remove(struct device *dev) 374 { 375 struct panel_simple *panel = dev_get_drvdata(dev); 376 377 drm_panel_remove(&panel->base); 378 379 panel_simple_disable(&panel->base); 380 panel_simple_unprepare(&panel->base); 381 382 if (panel->ddc) 383 put_device(&panel->ddc->dev); 384 385 if (panel->backlight) 386 put_device(&panel->backlight->dev); 387 388 return 0; 389 } 390 391 static void panel_simple_shutdown(struct device *dev) 392 { 393 struct panel_simple *panel = dev_get_drvdata(dev); 394 395 panel_simple_disable(&panel->base); 396 panel_simple_unprepare(&panel->base); 397 } 398 399 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 400 .clock = 9000, 401 .hdisplay = 480, 402 .hsync_start = 480 + 2, 403 .hsync_end = 480 + 2 + 41, 404 .htotal = 480 + 2 + 41 + 2, 405 .vdisplay = 272, 406 .vsync_start = 272 + 2, 407 .vsync_end = 272 + 2 + 10, 408 .vtotal = 272 + 2 + 10 + 2, 409 .vrefresh = 60, 410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 411 }; 412 413 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 414 .modes = &ire_am_480272h3tmqw_t01h_mode, 415 .num_modes = 1, 416 .bpc = 8, 417 .size = { 418 .width = 105, 419 .height = 67, 420 }, 421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 422 }; 423 424 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 425 .clock = 33333, 426 .hdisplay = 800, 427 .hsync_start = 800 + 0, 428 .hsync_end = 800 + 0 + 255, 429 .htotal = 800 + 0 + 255 + 0, 430 .vdisplay = 480, 431 .vsync_start = 480 + 2, 432 .vsync_end = 480 + 2 + 45, 433 .vtotal = 480 + 2 + 45 + 0, 434 .vrefresh = 60, 435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 436 }; 437 438 static const struct panel_desc ampire_am800480r3tmqwa1h = { 439 .modes = &ire_am800480r3tmqwa1h_mode, 440 .num_modes = 1, 441 .bpc = 6, 442 .size = { 443 .width = 152, 444 .height = 91, 445 }, 446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 447 }; 448 449 static const struct drm_display_mode auo_b101aw03_mode = { 450 .clock = 51450, 451 .hdisplay = 1024, 452 .hsync_start = 1024 + 156, 453 .hsync_end = 1024 + 156 + 8, 454 .htotal = 1024 + 156 + 8 + 156, 455 .vdisplay = 600, 456 .vsync_start = 600 + 16, 457 .vsync_end = 600 + 16 + 6, 458 .vtotal = 600 + 16 + 6 + 16, 459 .vrefresh = 60, 460 }; 461 462 static const struct panel_desc auo_b101aw03 = { 463 .modes = &auo_b101aw03_mode, 464 .num_modes = 1, 465 .bpc = 6, 466 .size = { 467 .width = 223, 468 .height = 125, 469 }, 470 }; 471 472 static const struct drm_display_mode auo_b101ean01_mode = { 473 .clock = 72500, 474 .hdisplay = 1280, 475 .hsync_start = 1280 + 119, 476 .hsync_end = 1280 + 119 + 32, 477 .htotal = 1280 + 119 + 32 + 21, 478 .vdisplay = 800, 479 .vsync_start = 800 + 4, 480 .vsync_end = 800 + 4 + 20, 481 .vtotal = 800 + 4 + 20 + 8, 482 .vrefresh = 60, 483 }; 484 485 static const struct panel_desc auo_b101ean01 = { 486 .modes = &auo_b101ean01_mode, 487 .num_modes = 1, 488 .bpc = 6, 489 .size = { 490 .width = 217, 491 .height = 136, 492 }, 493 }; 494 495 static const struct drm_display_mode auo_b101xtn01_mode = { 496 .clock = 72000, 497 .hdisplay = 1366, 498 .hsync_start = 1366 + 20, 499 .hsync_end = 1366 + 20 + 70, 500 .htotal = 1366 + 20 + 70, 501 .vdisplay = 768, 502 .vsync_start = 768 + 14, 503 .vsync_end = 768 + 14 + 42, 504 .vtotal = 768 + 14 + 42, 505 .vrefresh = 60, 506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 507 }; 508 509 static const struct panel_desc auo_b101xtn01 = { 510 .modes = &auo_b101xtn01_mode, 511 .num_modes = 1, 512 .bpc = 6, 513 .size = { 514 .width = 223, 515 .height = 125, 516 }, 517 }; 518 519 static const struct drm_display_mode auo_b116xw03_mode = { 520 .clock = 70589, 521 .hdisplay = 1366, 522 .hsync_start = 1366 + 40, 523 .hsync_end = 1366 + 40 + 40, 524 .htotal = 1366 + 40 + 40 + 32, 525 .vdisplay = 768, 526 .vsync_start = 768 + 10, 527 .vsync_end = 768 + 10 + 12, 528 .vtotal = 768 + 10 + 12 + 6, 529 .vrefresh = 60, 530 }; 531 532 static const struct panel_desc auo_b116xw03 = { 533 .modes = &auo_b116xw03_mode, 534 .num_modes = 1, 535 .bpc = 6, 536 .size = { 537 .width = 256, 538 .height = 144, 539 }, 540 }; 541 542 static const struct drm_display_mode auo_b133xtn01_mode = { 543 .clock = 69500, 544 .hdisplay = 1366, 545 .hsync_start = 1366 + 48, 546 .hsync_end = 1366 + 48 + 32, 547 .htotal = 1366 + 48 + 32 + 20, 548 .vdisplay = 768, 549 .vsync_start = 768 + 3, 550 .vsync_end = 768 + 3 + 6, 551 .vtotal = 768 + 3 + 6 + 13, 552 .vrefresh = 60, 553 }; 554 555 static const struct panel_desc auo_b133xtn01 = { 556 .modes = &auo_b133xtn01_mode, 557 .num_modes = 1, 558 .bpc = 6, 559 .size = { 560 .width = 293, 561 .height = 165, 562 }, 563 }; 564 565 static const struct drm_display_mode auo_b133htn01_mode = { 566 .clock = 150660, 567 .hdisplay = 1920, 568 .hsync_start = 1920 + 172, 569 .hsync_end = 1920 + 172 + 80, 570 .htotal = 1920 + 172 + 80 + 60, 571 .vdisplay = 1080, 572 .vsync_start = 1080 + 25, 573 .vsync_end = 1080 + 25 + 10, 574 .vtotal = 1080 + 25 + 10 + 10, 575 .vrefresh = 60, 576 }; 577 578 static const struct panel_desc auo_b133htn01 = { 579 .modes = &auo_b133htn01_mode, 580 .num_modes = 1, 581 .bpc = 6, 582 .size = { 583 .width = 293, 584 .height = 165, 585 }, 586 .delay = { 587 .prepare = 105, 588 .enable = 20, 589 .unprepare = 50, 590 }, 591 }; 592 593 static const struct display_timing auo_g070vvn01_timings = { 594 .pixelclock = { 33300000, 34209000, 45000000 }, 595 .hactive = { 800, 800, 800 }, 596 .hfront_porch = { 20, 40, 200 }, 597 .hback_porch = { 87, 40, 1 }, 598 .hsync_len = { 1, 48, 87 }, 599 .vactive = { 480, 480, 480 }, 600 .vfront_porch = { 5, 13, 200 }, 601 .vback_porch = { 31, 31, 29 }, 602 .vsync_len = { 1, 1, 3 }, 603 }; 604 605 static const struct panel_desc auo_g070vvn01 = { 606 .timings = &auo_g070vvn01_timings, 607 .num_timings = 1, 608 .bpc = 8, 609 .size = { 610 .width = 152, 611 .height = 91, 612 }, 613 .delay = { 614 .prepare = 200, 615 .enable = 50, 616 .disable = 50, 617 .unprepare = 1000, 618 }, 619 }; 620 621 static const struct drm_display_mode auo_g104sn02_mode = { 622 .clock = 40000, 623 .hdisplay = 800, 624 .hsync_start = 800 + 40, 625 .hsync_end = 800 + 40 + 216, 626 .htotal = 800 + 40 + 216 + 128, 627 .vdisplay = 600, 628 .vsync_start = 600 + 10, 629 .vsync_end = 600 + 10 + 35, 630 .vtotal = 600 + 10 + 35 + 2, 631 .vrefresh = 60, 632 }; 633 634 static const struct panel_desc auo_g104sn02 = { 635 .modes = &auo_g104sn02_mode, 636 .num_modes = 1, 637 .bpc = 8, 638 .size = { 639 .width = 211, 640 .height = 158, 641 }, 642 }; 643 644 static const struct display_timing auo_g133han01_timings = { 645 .pixelclock = { 134000000, 141200000, 149000000 }, 646 .hactive = { 1920, 1920, 1920 }, 647 .hfront_porch = { 39, 58, 77 }, 648 .hback_porch = { 59, 88, 117 }, 649 .hsync_len = { 28, 42, 56 }, 650 .vactive = { 1080, 1080, 1080 }, 651 .vfront_porch = { 3, 8, 11 }, 652 .vback_porch = { 5, 14, 19 }, 653 .vsync_len = { 4, 14, 19 }, 654 }; 655 656 static const struct panel_desc auo_g133han01 = { 657 .timings = &auo_g133han01_timings, 658 .num_timings = 1, 659 .bpc = 8, 660 .size = { 661 .width = 293, 662 .height = 165, 663 }, 664 .delay = { 665 .prepare = 200, 666 .enable = 50, 667 .disable = 50, 668 .unprepare = 1000, 669 }, 670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 671 }; 672 673 static const struct display_timing auo_g185han01_timings = { 674 .pixelclock = { 120000000, 144000000, 175000000 }, 675 .hactive = { 1920, 1920, 1920 }, 676 .hfront_porch = { 18, 60, 74 }, 677 .hback_porch = { 12, 44, 54 }, 678 .hsync_len = { 10, 24, 32 }, 679 .vactive = { 1080, 1080, 1080 }, 680 .vfront_porch = { 6, 10, 40 }, 681 .vback_porch = { 2, 5, 20 }, 682 .vsync_len = { 2, 5, 20 }, 683 }; 684 685 static const struct panel_desc auo_g185han01 = { 686 .timings = &auo_g185han01_timings, 687 .num_timings = 1, 688 .bpc = 8, 689 .size = { 690 .width = 409, 691 .height = 230, 692 }, 693 .delay = { 694 .prepare = 50, 695 .enable = 200, 696 .disable = 110, 697 .unprepare = 1000, 698 }, 699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 700 }; 701 702 static const struct display_timing auo_p320hvn03_timings = { 703 .pixelclock = { 106000000, 148500000, 164000000 }, 704 .hactive = { 1920, 1920, 1920 }, 705 .hfront_porch = { 25, 50, 130 }, 706 .hback_porch = { 25, 50, 130 }, 707 .hsync_len = { 20, 40, 105 }, 708 .vactive = { 1080, 1080, 1080 }, 709 .vfront_porch = { 8, 17, 150 }, 710 .vback_porch = { 8, 17, 150 }, 711 .vsync_len = { 4, 11, 100 }, 712 }; 713 714 static const struct panel_desc auo_p320hvn03 = { 715 .timings = &auo_p320hvn03_timings, 716 .num_timings = 1, 717 .bpc = 8, 718 .size = { 719 .width = 698, 720 .height = 393, 721 }, 722 .delay = { 723 .prepare = 1, 724 .enable = 450, 725 .unprepare = 500, 726 }, 727 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 728 }; 729 730 static const struct drm_display_mode auo_t215hvn01_mode = { 731 .clock = 148800, 732 .hdisplay = 1920, 733 .hsync_start = 1920 + 88, 734 .hsync_end = 1920 + 88 + 44, 735 .htotal = 1920 + 88 + 44 + 148, 736 .vdisplay = 1080, 737 .vsync_start = 1080 + 4, 738 .vsync_end = 1080 + 4 + 5, 739 .vtotal = 1080 + 4 + 5 + 36, 740 .vrefresh = 60, 741 }; 742 743 static const struct panel_desc auo_t215hvn01 = { 744 .modes = &auo_t215hvn01_mode, 745 .num_modes = 1, 746 .bpc = 8, 747 .size = { 748 .width = 430, 749 .height = 270, 750 }, 751 .delay = { 752 .disable = 5, 753 .unprepare = 1000, 754 } 755 }; 756 757 static const struct drm_display_mode avic_tm070ddh03_mode = { 758 .clock = 51200, 759 .hdisplay = 1024, 760 .hsync_start = 1024 + 160, 761 .hsync_end = 1024 + 160 + 4, 762 .htotal = 1024 + 160 + 4 + 156, 763 .vdisplay = 600, 764 .vsync_start = 600 + 17, 765 .vsync_end = 600 + 17 + 1, 766 .vtotal = 600 + 17 + 1 + 17, 767 .vrefresh = 60, 768 }; 769 770 static const struct panel_desc avic_tm070ddh03 = { 771 .modes = &avic_tm070ddh03_mode, 772 .num_modes = 1, 773 .bpc = 8, 774 .size = { 775 .width = 154, 776 .height = 90, 777 }, 778 .delay = { 779 .prepare = 20, 780 .enable = 200, 781 .disable = 200, 782 }, 783 }; 784 785 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 786 .clock = 30000, 787 .hdisplay = 800, 788 .hsync_start = 800 + 40, 789 .hsync_end = 800 + 40 + 48, 790 .htotal = 800 + 40 + 48 + 40, 791 .vdisplay = 480, 792 .vsync_start = 480 + 13, 793 .vsync_end = 480 + 13 + 3, 794 .vtotal = 480 + 13 + 3 + 29, 795 }; 796 797 static const struct panel_desc bananapi_s070wv20_ct16 = { 798 .modes = &bananapi_s070wv20_ct16_mode, 799 .num_modes = 1, 800 .bpc = 6, 801 .size = { 802 .width = 154, 803 .height = 86, 804 }, 805 }; 806 807 static const struct drm_display_mode boe_hv070wsa_mode = { 808 .clock = 42105, 809 .hdisplay = 1024, 810 .hsync_start = 1024 + 30, 811 .hsync_end = 1024 + 30 + 30, 812 .htotal = 1024 + 30 + 30 + 30, 813 .vdisplay = 600, 814 .vsync_start = 600 + 10, 815 .vsync_end = 600 + 10 + 10, 816 .vtotal = 600 + 10 + 10 + 10, 817 .vrefresh = 60, 818 }; 819 820 static const struct panel_desc boe_hv070wsa = { 821 .modes = &boe_hv070wsa_mode, 822 .num_modes = 1, 823 .size = { 824 .width = 154, 825 .height = 90, 826 }, 827 }; 828 829 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 830 { 831 .clock = 71900, 832 .hdisplay = 1280, 833 .hsync_start = 1280 + 48, 834 .hsync_end = 1280 + 48 + 32, 835 .htotal = 1280 + 48 + 32 + 80, 836 .vdisplay = 800, 837 .vsync_start = 800 + 3, 838 .vsync_end = 800 + 3 + 5, 839 .vtotal = 800 + 3 + 5 + 24, 840 .vrefresh = 60, 841 }, 842 { 843 .clock = 57500, 844 .hdisplay = 1280, 845 .hsync_start = 1280 + 48, 846 .hsync_end = 1280 + 48 + 32, 847 .htotal = 1280 + 48 + 32 + 80, 848 .vdisplay = 800, 849 .vsync_start = 800 + 3, 850 .vsync_end = 800 + 3 + 5, 851 .vtotal = 800 + 3 + 5 + 24, 852 .vrefresh = 48, 853 }, 854 }; 855 856 static const struct panel_desc boe_nv101wxmn51 = { 857 .modes = boe_nv101wxmn51_modes, 858 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 859 .bpc = 8, 860 .size = { 861 .width = 217, 862 .height = 136, 863 }, 864 .delay = { 865 .prepare = 210, 866 .enable = 50, 867 .unprepare = 160, 868 }, 869 }; 870 871 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 872 .clock = 9000, 873 .hdisplay = 480, 874 .hsync_start = 480 + 5, 875 .hsync_end = 480 + 5 + 5, 876 .htotal = 480 + 5 + 5 + 40, 877 .vdisplay = 272, 878 .vsync_start = 272 + 8, 879 .vsync_end = 272 + 8 + 8, 880 .vtotal = 272 + 8 + 8 + 8, 881 .vrefresh = 60, 882 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 883 }; 884 885 static const struct panel_desc cdtech_s043wq26h_ct7 = { 886 .modes = &cdtech_s043wq26h_ct7_mode, 887 .num_modes = 1, 888 .bpc = 8, 889 .size = { 890 .width = 95, 891 .height = 54, 892 }, 893 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 894 }; 895 896 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 897 .clock = 35000, 898 .hdisplay = 800, 899 .hsync_start = 800 + 40, 900 .hsync_end = 800 + 40 + 40, 901 .htotal = 800 + 40 + 40 + 48, 902 .vdisplay = 480, 903 .vsync_start = 480 + 29, 904 .vsync_end = 480 + 29 + 13, 905 .vtotal = 480 + 29 + 13 + 3, 906 .vrefresh = 60, 907 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 908 }; 909 910 static const struct panel_desc cdtech_s070wv95_ct16 = { 911 .modes = &cdtech_s070wv95_ct16_mode, 912 .num_modes = 1, 913 .bpc = 8, 914 .size = { 915 .width = 154, 916 .height = 85, 917 }, 918 }; 919 920 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 921 .clock = 66770, 922 .hdisplay = 800, 923 .hsync_start = 800 + 49, 924 .hsync_end = 800 + 49 + 33, 925 .htotal = 800 + 49 + 33 + 17, 926 .vdisplay = 1280, 927 .vsync_start = 1280 + 1, 928 .vsync_end = 1280 + 1 + 7, 929 .vtotal = 1280 + 1 + 7 + 15, 930 .vrefresh = 60, 931 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 932 }; 933 934 static const struct panel_desc chunghwa_claa070wp03xg = { 935 .modes = &chunghwa_claa070wp03xg_mode, 936 .num_modes = 1, 937 .bpc = 6, 938 .size = { 939 .width = 94, 940 .height = 150, 941 }, 942 }; 943 944 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 945 .clock = 72070, 946 .hdisplay = 1366, 947 .hsync_start = 1366 + 58, 948 .hsync_end = 1366 + 58 + 58, 949 .htotal = 1366 + 58 + 58 + 58, 950 .vdisplay = 768, 951 .vsync_start = 768 + 4, 952 .vsync_end = 768 + 4 + 4, 953 .vtotal = 768 + 4 + 4 + 4, 954 .vrefresh = 60, 955 }; 956 957 static const struct panel_desc chunghwa_claa101wa01a = { 958 .modes = &chunghwa_claa101wa01a_mode, 959 .num_modes = 1, 960 .bpc = 6, 961 .size = { 962 .width = 220, 963 .height = 120, 964 }, 965 }; 966 967 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 968 .clock = 69300, 969 .hdisplay = 1366, 970 .hsync_start = 1366 + 48, 971 .hsync_end = 1366 + 48 + 32, 972 .htotal = 1366 + 48 + 32 + 20, 973 .vdisplay = 768, 974 .vsync_start = 768 + 16, 975 .vsync_end = 768 + 16 + 8, 976 .vtotal = 768 + 16 + 8 + 16, 977 .vrefresh = 60, 978 }; 979 980 static const struct panel_desc chunghwa_claa101wb01 = { 981 .modes = &chunghwa_claa101wb01_mode, 982 .num_modes = 1, 983 .bpc = 6, 984 .size = { 985 .width = 223, 986 .height = 125, 987 }, 988 }; 989 990 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 991 .clock = 33260, 992 .hdisplay = 800, 993 .hsync_start = 800 + 40, 994 .hsync_end = 800 + 40 + 128, 995 .htotal = 800 + 40 + 128 + 88, 996 .vdisplay = 480, 997 .vsync_start = 480 + 10, 998 .vsync_end = 480 + 10 + 2, 999 .vtotal = 480 + 10 + 2 + 33, 1000 .vrefresh = 60, 1001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1002 }; 1003 1004 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1005 .modes = &dataimage_scf0700c48ggu18_mode, 1006 .num_modes = 1, 1007 .bpc = 8, 1008 .size = { 1009 .width = 152, 1010 .height = 91, 1011 }, 1012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1014 }; 1015 1016 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1017 .pixelclock = { 45000000, 51200000, 57000000 }, 1018 .hactive = { 1024, 1024, 1024 }, 1019 .hfront_porch = { 100, 106, 113 }, 1020 .hback_porch = { 100, 106, 113 }, 1021 .hsync_len = { 100, 108, 114 }, 1022 .vactive = { 600, 600, 600 }, 1023 .vfront_porch = { 8, 11, 15 }, 1024 .vback_porch = { 8, 11, 15 }, 1025 .vsync_len = { 9, 13, 15 }, 1026 .flags = DISPLAY_FLAGS_DE_HIGH, 1027 }; 1028 1029 static const struct panel_desc dlc_dlc0700yzg_1 = { 1030 .timings = &dlc_dlc0700yzg_1_timing, 1031 .num_timings = 1, 1032 .bpc = 6, 1033 .size = { 1034 .width = 154, 1035 .height = 86, 1036 }, 1037 .delay = { 1038 .prepare = 30, 1039 .enable = 200, 1040 .disable = 200, 1041 }, 1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1043 }; 1044 1045 static const struct display_timing dlc_dlc1010gig_timing = { 1046 .pixelclock = { 68900000, 71100000, 73400000 }, 1047 .hactive = { 1280, 1280, 1280 }, 1048 .hfront_porch = { 43, 53, 63 }, 1049 .hback_porch = { 43, 53, 63 }, 1050 .hsync_len = { 44, 54, 64 }, 1051 .vactive = { 800, 800, 800 }, 1052 .vfront_porch = { 5, 8, 11 }, 1053 .vback_porch = { 5, 8, 11 }, 1054 .vsync_len = { 5, 7, 11 }, 1055 .flags = DISPLAY_FLAGS_DE_HIGH, 1056 }; 1057 1058 static const struct panel_desc dlc_dlc1010gig = { 1059 .timings = &dlc_dlc1010gig_timing, 1060 .num_timings = 1, 1061 .bpc = 8, 1062 .size = { 1063 .width = 216, 1064 .height = 135, 1065 }, 1066 .delay = { 1067 .prepare = 60, 1068 .enable = 150, 1069 .disable = 100, 1070 .unprepare = 60, 1071 }, 1072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1073 }; 1074 1075 static const struct drm_display_mode edt_et057090dhu_mode = { 1076 .clock = 25175, 1077 .hdisplay = 640, 1078 .hsync_start = 640 + 16, 1079 .hsync_end = 640 + 16 + 30, 1080 .htotal = 640 + 16 + 30 + 114, 1081 .vdisplay = 480, 1082 .vsync_start = 480 + 10, 1083 .vsync_end = 480 + 10 + 3, 1084 .vtotal = 480 + 10 + 3 + 32, 1085 .vrefresh = 60, 1086 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1087 }; 1088 1089 static const struct panel_desc edt_et057090dhu = { 1090 .modes = &edt_et057090dhu_mode, 1091 .num_modes = 1, 1092 .bpc = 6, 1093 .size = { 1094 .width = 115, 1095 .height = 86, 1096 }, 1097 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1098 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1099 }; 1100 1101 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1102 .clock = 33260, 1103 .hdisplay = 800, 1104 .hsync_start = 800 + 40, 1105 .hsync_end = 800 + 40 + 128, 1106 .htotal = 800 + 40 + 128 + 88, 1107 .vdisplay = 480, 1108 .vsync_start = 480 + 10, 1109 .vsync_end = 480 + 10 + 2, 1110 .vtotal = 480 + 10 + 2 + 33, 1111 .vrefresh = 60, 1112 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1113 }; 1114 1115 static const struct panel_desc edt_etm0700g0dh6 = { 1116 .modes = &edt_etm0700g0dh6_mode, 1117 .num_modes = 1, 1118 .bpc = 6, 1119 .size = { 1120 .width = 152, 1121 .height = 91, 1122 }, 1123 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1124 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1125 }; 1126 1127 static const struct panel_desc edt_etm0700g0bdh6 = { 1128 .modes = &edt_etm0700g0dh6_mode, 1129 .num_modes = 1, 1130 .bpc = 6, 1131 .size = { 1132 .width = 152, 1133 .height = 91, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1136 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1137 }; 1138 1139 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1140 .clock = 32260, 1141 .hdisplay = 800, 1142 .hsync_start = 800 + 168, 1143 .hsync_end = 800 + 168 + 64, 1144 .htotal = 800 + 168 + 64 + 88, 1145 .vdisplay = 480, 1146 .vsync_start = 480 + 37, 1147 .vsync_end = 480 + 37 + 2, 1148 .vtotal = 480 + 37 + 2 + 8, 1149 .vrefresh = 60, 1150 }; 1151 1152 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1153 .modes = &foxlink_fl500wvr00_a0t_mode, 1154 .num_modes = 1, 1155 .bpc = 8, 1156 .size = { 1157 .width = 108, 1158 .height = 65, 1159 }, 1160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1161 }; 1162 1163 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1164 .clock = 9000, 1165 .hdisplay = 480, 1166 .hsync_start = 480 + 5, 1167 .hsync_end = 480 + 5 + 1, 1168 .htotal = 480 + 5 + 1 + 40, 1169 .vdisplay = 272, 1170 .vsync_start = 272 + 8, 1171 .vsync_end = 272 + 8 + 1, 1172 .vtotal = 272 + 8 + 1 + 8, 1173 .vrefresh = 60, 1174 }; 1175 1176 static const struct panel_desc giantplus_gpg482739qs5 = { 1177 .modes = &giantplus_gpg482739qs5_mode, 1178 .num_modes = 1, 1179 .bpc = 8, 1180 .size = { 1181 .width = 95, 1182 .height = 54, 1183 }, 1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1185 }; 1186 1187 static const struct display_timing hannstar_hsd070pww1_timing = { 1188 .pixelclock = { 64300000, 71100000, 82000000 }, 1189 .hactive = { 1280, 1280, 1280 }, 1190 .hfront_porch = { 1, 1, 10 }, 1191 .hback_porch = { 1, 1, 10 }, 1192 /* 1193 * According to the data sheet, the minimum horizontal blanking interval 1194 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1195 * minimum working horizontal blanking interval to be 60 clocks. 1196 */ 1197 .hsync_len = { 58, 158, 661 }, 1198 .vactive = { 800, 800, 800 }, 1199 .vfront_porch = { 1, 1, 10 }, 1200 .vback_porch = { 1, 1, 10 }, 1201 .vsync_len = { 1, 21, 203 }, 1202 .flags = DISPLAY_FLAGS_DE_HIGH, 1203 }; 1204 1205 static const struct panel_desc hannstar_hsd070pww1 = { 1206 .timings = &hannstar_hsd070pww1_timing, 1207 .num_timings = 1, 1208 .bpc = 6, 1209 .size = { 1210 .width = 151, 1211 .height = 94, 1212 }, 1213 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1214 }; 1215 1216 static const struct display_timing hannstar_hsd100pxn1_timing = { 1217 .pixelclock = { 55000000, 65000000, 75000000 }, 1218 .hactive = { 1024, 1024, 1024 }, 1219 .hfront_porch = { 40, 40, 40 }, 1220 .hback_porch = { 220, 220, 220 }, 1221 .hsync_len = { 20, 60, 100 }, 1222 .vactive = { 768, 768, 768 }, 1223 .vfront_porch = { 7, 7, 7 }, 1224 .vback_porch = { 21, 21, 21 }, 1225 .vsync_len = { 10, 10, 10 }, 1226 .flags = DISPLAY_FLAGS_DE_HIGH, 1227 }; 1228 1229 static const struct panel_desc hannstar_hsd100pxn1 = { 1230 .timings = &hannstar_hsd100pxn1_timing, 1231 .num_timings = 1, 1232 .bpc = 6, 1233 .size = { 1234 .width = 203, 1235 .height = 152, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1238 }; 1239 1240 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1241 .clock = 33333, 1242 .hdisplay = 800, 1243 .hsync_start = 800 + 85, 1244 .hsync_end = 800 + 85 + 86, 1245 .htotal = 800 + 85 + 86 + 85, 1246 .vdisplay = 480, 1247 .vsync_start = 480 + 16, 1248 .vsync_end = 480 + 16 + 13, 1249 .vtotal = 480 + 16 + 13 + 16, 1250 .vrefresh = 60, 1251 }; 1252 1253 static const struct panel_desc hitachi_tx23d38vm0caa = { 1254 .modes = &hitachi_tx23d38vm0caa_mode, 1255 .num_modes = 1, 1256 .bpc = 6, 1257 .size = { 1258 .width = 195, 1259 .height = 117, 1260 }, 1261 .delay = { 1262 .enable = 160, 1263 .disable = 160, 1264 }, 1265 }; 1266 1267 static const struct drm_display_mode innolux_at043tn24_mode = { 1268 .clock = 9000, 1269 .hdisplay = 480, 1270 .hsync_start = 480 + 2, 1271 .hsync_end = 480 + 2 + 41, 1272 .htotal = 480 + 2 + 41 + 2, 1273 .vdisplay = 272, 1274 .vsync_start = 272 + 2, 1275 .vsync_end = 272 + 2 + 10, 1276 .vtotal = 272 + 2 + 10 + 2, 1277 .vrefresh = 60, 1278 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1279 }; 1280 1281 static const struct panel_desc innolux_at043tn24 = { 1282 .modes = &innolux_at043tn24_mode, 1283 .num_modes = 1, 1284 .bpc = 8, 1285 .size = { 1286 .width = 95, 1287 .height = 54, 1288 }, 1289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1291 }; 1292 1293 static const struct drm_display_mode innolux_at070tn92_mode = { 1294 .clock = 33333, 1295 .hdisplay = 800, 1296 .hsync_start = 800 + 210, 1297 .hsync_end = 800 + 210 + 20, 1298 .htotal = 800 + 210 + 20 + 46, 1299 .vdisplay = 480, 1300 .vsync_start = 480 + 22, 1301 .vsync_end = 480 + 22 + 10, 1302 .vtotal = 480 + 22 + 23 + 10, 1303 .vrefresh = 60, 1304 }; 1305 1306 static const struct panel_desc innolux_at070tn92 = { 1307 .modes = &innolux_at070tn92_mode, 1308 .num_modes = 1, 1309 .size = { 1310 .width = 154, 1311 .height = 86, 1312 }, 1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1314 }; 1315 1316 static const struct display_timing innolux_g070y2_l01_timing = { 1317 .pixelclock = { 28000000, 29500000, 32000000 }, 1318 .hactive = { 800, 800, 800 }, 1319 .hfront_porch = { 61, 91, 141 }, 1320 .hback_porch = { 60, 90, 140 }, 1321 .hsync_len = { 12, 12, 12 }, 1322 .vactive = { 480, 480, 480 }, 1323 .vfront_porch = { 4, 9, 30 }, 1324 .vback_porch = { 4, 8, 28 }, 1325 .vsync_len = { 2, 2, 2 }, 1326 .flags = DISPLAY_FLAGS_DE_HIGH, 1327 }; 1328 1329 static const struct panel_desc innolux_g070y2_l01 = { 1330 .timings = &innolux_g070y2_l01_timing, 1331 .num_timings = 1, 1332 .bpc = 6, 1333 .size = { 1334 .width = 152, 1335 .height = 91, 1336 }, 1337 .delay = { 1338 .prepare = 10, 1339 .enable = 100, 1340 .disable = 100, 1341 .unprepare = 800, 1342 }, 1343 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1344 }; 1345 1346 static const struct display_timing innolux_g101ice_l01_timing = { 1347 .pixelclock = { 60400000, 71100000, 74700000 }, 1348 .hactive = { 1280, 1280, 1280 }, 1349 .hfront_porch = { 41, 80, 100 }, 1350 .hback_porch = { 40, 79, 99 }, 1351 .hsync_len = { 1, 1, 1 }, 1352 .vactive = { 800, 800, 800 }, 1353 .vfront_porch = { 5, 11, 14 }, 1354 .vback_porch = { 4, 11, 14 }, 1355 .vsync_len = { 1, 1, 1 }, 1356 .flags = DISPLAY_FLAGS_DE_HIGH, 1357 }; 1358 1359 static const struct panel_desc innolux_g101ice_l01 = { 1360 .timings = &innolux_g101ice_l01_timing, 1361 .num_timings = 1, 1362 .bpc = 8, 1363 .size = { 1364 .width = 217, 1365 .height = 135, 1366 }, 1367 .delay = { 1368 .enable = 200, 1369 .disable = 200, 1370 }, 1371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1372 }; 1373 1374 static const struct display_timing innolux_g121i1_l01_timing = { 1375 .pixelclock = { 67450000, 71000000, 74550000 }, 1376 .hactive = { 1280, 1280, 1280 }, 1377 .hfront_porch = { 40, 80, 160 }, 1378 .hback_porch = { 39, 79, 159 }, 1379 .hsync_len = { 1, 1, 1 }, 1380 .vactive = { 800, 800, 800 }, 1381 .vfront_porch = { 5, 11, 100 }, 1382 .vback_porch = { 4, 11, 99 }, 1383 .vsync_len = { 1, 1, 1 }, 1384 }; 1385 1386 static const struct panel_desc innolux_g121i1_l01 = { 1387 .timings = &innolux_g121i1_l01_timing, 1388 .num_timings = 1, 1389 .bpc = 6, 1390 .size = { 1391 .width = 261, 1392 .height = 163, 1393 }, 1394 .delay = { 1395 .enable = 200, 1396 .disable = 20, 1397 }, 1398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1399 }; 1400 1401 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1402 .clock = 65000, 1403 .hdisplay = 1024, 1404 .hsync_start = 1024 + 0, 1405 .hsync_end = 1024 + 1, 1406 .htotal = 1024 + 0 + 1 + 320, 1407 .vdisplay = 768, 1408 .vsync_start = 768 + 38, 1409 .vsync_end = 768 + 38 + 1, 1410 .vtotal = 768 + 38 + 1 + 0, 1411 .vrefresh = 60, 1412 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1413 }; 1414 1415 static const struct panel_desc innolux_g121x1_l03 = { 1416 .modes = &innolux_g121x1_l03_mode, 1417 .num_modes = 1, 1418 .bpc = 6, 1419 .size = { 1420 .width = 246, 1421 .height = 185, 1422 }, 1423 .delay = { 1424 .enable = 200, 1425 .unprepare = 200, 1426 .disable = 400, 1427 }, 1428 }; 1429 1430 static const struct drm_display_mode innolux_n116bge_mode = { 1431 .clock = 76420, 1432 .hdisplay = 1366, 1433 .hsync_start = 1366 + 136, 1434 .hsync_end = 1366 + 136 + 30, 1435 .htotal = 1366 + 136 + 30 + 60, 1436 .vdisplay = 768, 1437 .vsync_start = 768 + 8, 1438 .vsync_end = 768 + 8 + 12, 1439 .vtotal = 768 + 8 + 12 + 12, 1440 .vrefresh = 60, 1441 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1442 }; 1443 1444 static const struct panel_desc innolux_n116bge = { 1445 .modes = &innolux_n116bge_mode, 1446 .num_modes = 1, 1447 .bpc = 6, 1448 .size = { 1449 .width = 256, 1450 .height = 144, 1451 }, 1452 }; 1453 1454 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1455 .clock = 69300, 1456 .hdisplay = 1366, 1457 .hsync_start = 1366 + 16, 1458 .hsync_end = 1366 + 16 + 34, 1459 .htotal = 1366 + 16 + 34 + 50, 1460 .vdisplay = 768, 1461 .vsync_start = 768 + 2, 1462 .vsync_end = 768 + 2 + 6, 1463 .vtotal = 768 + 2 + 6 + 12, 1464 .vrefresh = 60, 1465 }; 1466 1467 static const struct panel_desc innolux_n156bge_l21 = { 1468 .modes = &innolux_n156bge_l21_mode, 1469 .num_modes = 1, 1470 .bpc = 6, 1471 .size = { 1472 .width = 344, 1473 .height = 193, 1474 }, 1475 }; 1476 1477 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1478 .clock = 206016, 1479 .hdisplay = 2160, 1480 .hsync_start = 2160 + 48, 1481 .hsync_end = 2160 + 48 + 32, 1482 .htotal = 2160 + 48 + 32 + 80, 1483 .vdisplay = 1440, 1484 .vsync_start = 1440 + 3, 1485 .vsync_end = 1440 + 3 + 10, 1486 .vtotal = 1440 + 3 + 10 + 27, 1487 .vrefresh = 60, 1488 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1489 }; 1490 1491 static const struct panel_desc innolux_p120zdg_bf1 = { 1492 .modes = &innolux_p120zdg_bf1_mode, 1493 .num_modes = 1, 1494 .bpc = 8, 1495 .size = { 1496 .width = 254, 1497 .height = 169, 1498 }, 1499 .delay = { 1500 .hpd_absent_delay = 200, 1501 .unprepare = 500, 1502 }, 1503 }; 1504 1505 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1506 .clock = 51501, 1507 .hdisplay = 1024, 1508 .hsync_start = 1024 + 128, 1509 .hsync_end = 1024 + 128 + 64, 1510 .htotal = 1024 + 128 + 64 + 128, 1511 .vdisplay = 600, 1512 .vsync_start = 600 + 16, 1513 .vsync_end = 600 + 16 + 4, 1514 .vtotal = 600 + 16 + 4 + 16, 1515 .vrefresh = 60, 1516 }; 1517 1518 static const struct panel_desc innolux_zj070na_01p = { 1519 .modes = &innolux_zj070na_01p_mode, 1520 .num_modes = 1, 1521 .bpc = 6, 1522 .size = { 1523 .width = 154, 1524 .height = 90, 1525 }, 1526 }; 1527 1528 static const struct display_timing koe_tx31d200vm0baa_timing = { 1529 .pixelclock = { 39600000, 43200000, 48000000 }, 1530 .hactive = { 1280, 1280, 1280 }, 1531 .hfront_porch = { 16, 36, 56 }, 1532 .hback_porch = { 16, 36, 56 }, 1533 .hsync_len = { 8, 8, 8 }, 1534 .vactive = { 480, 480, 480 }, 1535 .vfront_porch = { 6, 21, 33 }, 1536 .vback_porch = { 6, 21, 33 }, 1537 .vsync_len = { 8, 8, 8 }, 1538 .flags = DISPLAY_FLAGS_DE_HIGH, 1539 }; 1540 1541 static const struct panel_desc koe_tx31d200vm0baa = { 1542 .timings = &koe_tx31d200vm0baa_timing, 1543 .num_timings = 1, 1544 .bpc = 6, 1545 .size = { 1546 .width = 292, 1547 .height = 109, 1548 }, 1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1550 }; 1551 1552 static const struct display_timing kyo_tcg121xglp_timing = { 1553 .pixelclock = { 52000000, 65000000, 71000000 }, 1554 .hactive = { 1024, 1024, 1024 }, 1555 .hfront_porch = { 2, 2, 2 }, 1556 .hback_porch = { 2, 2, 2 }, 1557 .hsync_len = { 86, 124, 244 }, 1558 .vactive = { 768, 768, 768 }, 1559 .vfront_porch = { 2, 2, 2 }, 1560 .vback_porch = { 2, 2, 2 }, 1561 .vsync_len = { 6, 34, 73 }, 1562 .flags = DISPLAY_FLAGS_DE_HIGH, 1563 }; 1564 1565 static const struct panel_desc kyo_tcg121xglp = { 1566 .timings = &kyo_tcg121xglp_timing, 1567 .num_timings = 1, 1568 .bpc = 8, 1569 .size = { 1570 .width = 246, 1571 .height = 184, 1572 }, 1573 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1574 }; 1575 1576 static const struct drm_display_mode lg_lb070wv8_mode = { 1577 .clock = 33246, 1578 .hdisplay = 800, 1579 .hsync_start = 800 + 88, 1580 .hsync_end = 800 + 88 + 80, 1581 .htotal = 800 + 88 + 80 + 88, 1582 .vdisplay = 480, 1583 .vsync_start = 480 + 10, 1584 .vsync_end = 480 + 10 + 25, 1585 .vtotal = 480 + 10 + 25 + 10, 1586 .vrefresh = 60, 1587 }; 1588 1589 static const struct panel_desc lg_lb070wv8 = { 1590 .modes = &lg_lb070wv8_mode, 1591 .num_modes = 1, 1592 .bpc = 16, 1593 .size = { 1594 .width = 151, 1595 .height = 91, 1596 }, 1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1598 }; 1599 1600 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1601 .clock = 200000, 1602 .hdisplay = 1536, 1603 .hsync_start = 1536 + 12, 1604 .hsync_end = 1536 + 12 + 16, 1605 .htotal = 1536 + 12 + 16 + 48, 1606 .vdisplay = 2048, 1607 .vsync_start = 2048 + 8, 1608 .vsync_end = 2048 + 8 + 4, 1609 .vtotal = 2048 + 8 + 4 + 8, 1610 .vrefresh = 60, 1611 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1612 }; 1613 1614 static const struct panel_desc lg_lp079qx1_sp0v = { 1615 .modes = &lg_lp079qx1_sp0v_mode, 1616 .num_modes = 1, 1617 .size = { 1618 .width = 129, 1619 .height = 171, 1620 }, 1621 }; 1622 1623 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1624 .clock = 205210, 1625 .hdisplay = 2048, 1626 .hsync_start = 2048 + 150, 1627 .hsync_end = 2048 + 150 + 5, 1628 .htotal = 2048 + 150 + 5 + 5, 1629 .vdisplay = 1536, 1630 .vsync_start = 1536 + 3, 1631 .vsync_end = 1536 + 3 + 1, 1632 .vtotal = 1536 + 3 + 1 + 9, 1633 .vrefresh = 60, 1634 }; 1635 1636 static const struct panel_desc lg_lp097qx1_spa1 = { 1637 .modes = &lg_lp097qx1_spa1_mode, 1638 .num_modes = 1, 1639 .size = { 1640 .width = 208, 1641 .height = 147, 1642 }, 1643 }; 1644 1645 static const struct drm_display_mode lg_lp120up1_mode = { 1646 .clock = 162300, 1647 .hdisplay = 1920, 1648 .hsync_start = 1920 + 40, 1649 .hsync_end = 1920 + 40 + 40, 1650 .htotal = 1920 + 40 + 40+ 80, 1651 .vdisplay = 1280, 1652 .vsync_start = 1280 + 4, 1653 .vsync_end = 1280 + 4 + 4, 1654 .vtotal = 1280 + 4 + 4 + 12, 1655 .vrefresh = 60, 1656 }; 1657 1658 static const struct panel_desc lg_lp120up1 = { 1659 .modes = &lg_lp120up1_mode, 1660 .num_modes = 1, 1661 .bpc = 8, 1662 .size = { 1663 .width = 267, 1664 .height = 183, 1665 }, 1666 }; 1667 1668 static const struct drm_display_mode lg_lp129qe_mode = { 1669 .clock = 285250, 1670 .hdisplay = 2560, 1671 .hsync_start = 2560 + 48, 1672 .hsync_end = 2560 + 48 + 32, 1673 .htotal = 2560 + 48 + 32 + 80, 1674 .vdisplay = 1700, 1675 .vsync_start = 1700 + 3, 1676 .vsync_end = 1700 + 3 + 10, 1677 .vtotal = 1700 + 3 + 10 + 36, 1678 .vrefresh = 60, 1679 }; 1680 1681 static const struct panel_desc lg_lp129qe = { 1682 .modes = &lg_lp129qe_mode, 1683 .num_modes = 1, 1684 .bpc = 8, 1685 .size = { 1686 .width = 272, 1687 .height = 181, 1688 }, 1689 }; 1690 1691 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 1692 .clock = 30400, 1693 .hdisplay = 800, 1694 .hsync_start = 800 + 0, 1695 .hsync_end = 800 + 1, 1696 .htotal = 800 + 0 + 1 + 160, 1697 .vdisplay = 480, 1698 .vsync_start = 480 + 0, 1699 .vsync_end = 480 + 48 + 1, 1700 .vtotal = 480 + 48 + 1 + 0, 1701 .vrefresh = 60, 1702 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1703 }; 1704 1705 static const struct panel_desc mitsubishi_aa070mc01 = { 1706 .modes = &mitsubishi_aa070mc01_mode, 1707 .num_modes = 1, 1708 .bpc = 8, 1709 .size = { 1710 .width = 152, 1711 .height = 91, 1712 }, 1713 1714 .delay = { 1715 .enable = 200, 1716 .unprepare = 200, 1717 .disable = 400, 1718 }, 1719 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1720 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1721 }; 1722 1723 static const struct display_timing nec_nl12880bc20_05_timing = { 1724 .pixelclock = { 67000000, 71000000, 75000000 }, 1725 .hactive = { 1280, 1280, 1280 }, 1726 .hfront_porch = { 2, 30, 30 }, 1727 .hback_porch = { 6, 100, 100 }, 1728 .hsync_len = { 2, 30, 30 }, 1729 .vactive = { 800, 800, 800 }, 1730 .vfront_porch = { 5, 5, 5 }, 1731 .vback_porch = { 11, 11, 11 }, 1732 .vsync_len = { 7, 7, 7 }, 1733 }; 1734 1735 static const struct panel_desc nec_nl12880bc20_05 = { 1736 .timings = &nec_nl12880bc20_05_timing, 1737 .num_timings = 1, 1738 .bpc = 8, 1739 .size = { 1740 .width = 261, 1741 .height = 163, 1742 }, 1743 .delay = { 1744 .enable = 50, 1745 .disable = 50, 1746 }, 1747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1748 }; 1749 1750 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1751 .clock = 10870, 1752 .hdisplay = 480, 1753 .hsync_start = 480 + 2, 1754 .hsync_end = 480 + 2 + 41, 1755 .htotal = 480 + 2 + 41 + 2, 1756 .vdisplay = 272, 1757 .vsync_start = 272 + 2, 1758 .vsync_end = 272 + 2 + 4, 1759 .vtotal = 272 + 2 + 4 + 2, 1760 .vrefresh = 74, 1761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1762 }; 1763 1764 static const struct panel_desc nec_nl4827hc19_05b = { 1765 .modes = &nec_nl4827hc19_05b_mode, 1766 .num_modes = 1, 1767 .bpc = 8, 1768 .size = { 1769 .width = 95, 1770 .height = 54, 1771 }, 1772 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1773 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1774 }; 1775 1776 static const struct drm_display_mode netron_dy_e231732_mode = { 1777 .clock = 66000, 1778 .hdisplay = 1024, 1779 .hsync_start = 1024 + 160, 1780 .hsync_end = 1024 + 160 + 70, 1781 .htotal = 1024 + 160 + 70 + 90, 1782 .vdisplay = 600, 1783 .vsync_start = 600 + 127, 1784 .vsync_end = 600 + 127 + 20, 1785 .vtotal = 600 + 127 + 20 + 3, 1786 .vrefresh = 60, 1787 }; 1788 1789 static const struct panel_desc netron_dy_e231732 = { 1790 .modes = &netron_dy_e231732_mode, 1791 .num_modes = 1, 1792 .size = { 1793 .width = 154, 1794 .height = 87, 1795 }, 1796 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1797 }; 1798 1799 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 1800 .clock = 9000, 1801 .hdisplay = 480, 1802 .hsync_start = 480 + 2, 1803 .hsync_end = 480 + 2 + 41, 1804 .htotal = 480 + 2 + 41 + 2, 1805 .vdisplay = 272, 1806 .vsync_start = 272 + 2, 1807 .vsync_end = 272 + 2 + 10, 1808 .vtotal = 272 + 2 + 10 + 2, 1809 .vrefresh = 60, 1810 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1811 }; 1812 1813 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 1814 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 1815 .num_modes = 1, 1816 .bpc = 8, 1817 .size = { 1818 .width = 95, 1819 .height = 54, 1820 }, 1821 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1822 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 1823 DRM_BUS_FLAG_SYNC_POSEDGE, 1824 }; 1825 1826 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1827 .pixelclock = { 130000000, 148350000, 163000000 }, 1828 .hactive = { 1920, 1920, 1920 }, 1829 .hfront_porch = { 80, 100, 100 }, 1830 .hback_porch = { 100, 120, 120 }, 1831 .hsync_len = { 50, 60, 60 }, 1832 .vactive = { 1080, 1080, 1080 }, 1833 .vfront_porch = { 12, 30, 30 }, 1834 .vback_porch = { 4, 10, 10 }, 1835 .vsync_len = { 4, 5, 5 }, 1836 }; 1837 1838 static const struct panel_desc nlt_nl192108ac18_02d = { 1839 .timings = &nlt_nl192108ac18_02d_timing, 1840 .num_timings = 1, 1841 .bpc = 8, 1842 .size = { 1843 .width = 344, 1844 .height = 194, 1845 }, 1846 .delay = { 1847 .unprepare = 500, 1848 }, 1849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1850 }; 1851 1852 static const struct drm_display_mode nvd_9128_mode = { 1853 .clock = 29500, 1854 .hdisplay = 800, 1855 .hsync_start = 800 + 130, 1856 .hsync_end = 800 + 130 + 98, 1857 .htotal = 800 + 0 + 130 + 98, 1858 .vdisplay = 480, 1859 .vsync_start = 480 + 10, 1860 .vsync_end = 480 + 10 + 50, 1861 .vtotal = 480 + 0 + 10 + 50, 1862 }; 1863 1864 static const struct panel_desc nvd_9128 = { 1865 .modes = &nvd_9128_mode, 1866 .num_modes = 1, 1867 .bpc = 8, 1868 .size = { 1869 .width = 156, 1870 .height = 88, 1871 }, 1872 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1873 }; 1874 1875 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1876 .pixelclock = { 30000000, 30000000, 40000000 }, 1877 .hactive = { 800, 800, 800 }, 1878 .hfront_porch = { 40, 40, 40 }, 1879 .hback_porch = { 40, 40, 40 }, 1880 .hsync_len = { 1, 48, 48 }, 1881 .vactive = { 480, 480, 480 }, 1882 .vfront_porch = { 13, 13, 13 }, 1883 .vback_porch = { 29, 29, 29 }, 1884 .vsync_len = { 3, 3, 3 }, 1885 .flags = DISPLAY_FLAGS_DE_HIGH, 1886 }; 1887 1888 static const struct panel_desc okaya_rs800480t_7x0gp = { 1889 .timings = &okaya_rs800480t_7x0gp_timing, 1890 .num_timings = 1, 1891 .bpc = 6, 1892 .size = { 1893 .width = 154, 1894 .height = 87, 1895 }, 1896 .delay = { 1897 .prepare = 41, 1898 .enable = 50, 1899 .unprepare = 41, 1900 .disable = 50, 1901 }, 1902 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1903 }; 1904 1905 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1906 .clock = 9000, 1907 .hdisplay = 480, 1908 .hsync_start = 480 + 5, 1909 .hsync_end = 480 + 5 + 30, 1910 .htotal = 480 + 5 + 30 + 10, 1911 .vdisplay = 272, 1912 .vsync_start = 272 + 8, 1913 .vsync_end = 272 + 8 + 5, 1914 .vtotal = 272 + 8 + 5 + 3, 1915 .vrefresh = 60, 1916 }; 1917 1918 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1919 .modes = &olimex_lcd_olinuxino_43ts_mode, 1920 .num_modes = 1, 1921 .size = { 1922 .width = 95, 1923 .height = 54, 1924 }, 1925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1926 }; 1927 1928 /* 1929 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1930 * pixel clocks, but this is the timing that was being used in the Adafruit 1931 * installation instructions. 1932 */ 1933 static const struct drm_display_mode ontat_yx700wv03_mode = { 1934 .clock = 29500, 1935 .hdisplay = 800, 1936 .hsync_start = 824, 1937 .hsync_end = 896, 1938 .htotal = 992, 1939 .vdisplay = 480, 1940 .vsync_start = 483, 1941 .vsync_end = 493, 1942 .vtotal = 500, 1943 .vrefresh = 60, 1944 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1945 }; 1946 1947 /* 1948 * Specification at: 1949 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1950 */ 1951 static const struct panel_desc ontat_yx700wv03 = { 1952 .modes = &ontat_yx700wv03_mode, 1953 .num_modes = 1, 1954 .bpc = 8, 1955 .size = { 1956 .width = 154, 1957 .height = 83, 1958 }, 1959 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1960 }; 1961 1962 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1963 .clock = 25000, 1964 .hdisplay = 480, 1965 .hsync_start = 480 + 10, 1966 .hsync_end = 480 + 10 + 10, 1967 .htotal = 480 + 10 + 10 + 15, 1968 .vdisplay = 800, 1969 .vsync_start = 800 + 3, 1970 .vsync_end = 800 + 3 + 3, 1971 .vtotal = 800 + 3 + 3 + 3, 1972 .vrefresh = 60, 1973 }; 1974 1975 static const struct panel_desc ortustech_com43h4m85ulc = { 1976 .modes = &ortustech_com43h4m85ulc_mode, 1977 .num_modes = 1, 1978 .bpc = 8, 1979 .size = { 1980 .width = 56, 1981 .height = 93, 1982 }, 1983 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1984 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1985 }; 1986 1987 static const struct drm_display_mode qd43003c0_40_mode = { 1988 .clock = 9000, 1989 .hdisplay = 480, 1990 .hsync_start = 480 + 8, 1991 .hsync_end = 480 + 8 + 4, 1992 .htotal = 480 + 8 + 4 + 39, 1993 .vdisplay = 272, 1994 .vsync_start = 272 + 4, 1995 .vsync_end = 272 + 4 + 10, 1996 .vtotal = 272 + 4 + 10 + 2, 1997 .vrefresh = 60, 1998 }; 1999 2000 static const struct panel_desc qd43003c0_40 = { 2001 .modes = &qd43003c0_40_mode, 2002 .num_modes = 1, 2003 .bpc = 8, 2004 .size = { 2005 .width = 95, 2006 .height = 53, 2007 }, 2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2009 }; 2010 2011 static const struct display_timing rocktech_rk070er9427_timing = { 2012 .pixelclock = { 26400000, 33300000, 46800000 }, 2013 .hactive = { 800, 800, 800 }, 2014 .hfront_porch = { 16, 210, 354 }, 2015 .hback_porch = { 46, 46, 46 }, 2016 .hsync_len = { 1, 1, 1 }, 2017 .vactive = { 480, 480, 480 }, 2018 .vfront_porch = { 7, 22, 147 }, 2019 .vback_porch = { 23, 23, 23 }, 2020 .vsync_len = { 1, 1, 1 }, 2021 .flags = DISPLAY_FLAGS_DE_HIGH, 2022 }; 2023 2024 static const struct panel_desc rocktech_rk070er9427 = { 2025 .timings = &rocktech_rk070er9427_timing, 2026 .num_timings = 1, 2027 .bpc = 6, 2028 .size = { 2029 .width = 154, 2030 .height = 86, 2031 }, 2032 .delay = { 2033 .prepare = 41, 2034 .enable = 50, 2035 .unprepare = 41, 2036 .disable = 50, 2037 }, 2038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2039 }; 2040 2041 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2042 .clock = 271560, 2043 .hdisplay = 2560, 2044 .hsync_start = 2560 + 48, 2045 .hsync_end = 2560 + 48 + 32, 2046 .htotal = 2560 + 48 + 32 + 80, 2047 .vdisplay = 1600, 2048 .vsync_start = 1600 + 2, 2049 .vsync_end = 1600 + 2 + 5, 2050 .vtotal = 1600 + 2 + 5 + 57, 2051 .vrefresh = 60, 2052 }; 2053 2054 static const struct panel_desc samsung_lsn122dl01_c01 = { 2055 .modes = &samsung_lsn122dl01_c01_mode, 2056 .num_modes = 1, 2057 .size = { 2058 .width = 263, 2059 .height = 164, 2060 }, 2061 }; 2062 2063 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2064 .clock = 54030, 2065 .hdisplay = 1024, 2066 .hsync_start = 1024 + 24, 2067 .hsync_end = 1024 + 24 + 136, 2068 .htotal = 1024 + 24 + 136 + 160, 2069 .vdisplay = 600, 2070 .vsync_start = 600 + 3, 2071 .vsync_end = 600 + 3 + 6, 2072 .vtotal = 600 + 3 + 6 + 61, 2073 .vrefresh = 60, 2074 }; 2075 2076 static const struct panel_desc samsung_ltn101nt05 = { 2077 .modes = &samsung_ltn101nt05_mode, 2078 .num_modes = 1, 2079 .bpc = 6, 2080 .size = { 2081 .width = 223, 2082 .height = 125, 2083 }, 2084 }; 2085 2086 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2087 .clock = 76300, 2088 .hdisplay = 1366, 2089 .hsync_start = 1366 + 64, 2090 .hsync_end = 1366 + 64 + 48, 2091 .htotal = 1366 + 64 + 48 + 128, 2092 .vdisplay = 768, 2093 .vsync_start = 768 + 2, 2094 .vsync_end = 768 + 2 + 5, 2095 .vtotal = 768 + 2 + 5 + 17, 2096 .vrefresh = 60, 2097 }; 2098 2099 static const struct panel_desc samsung_ltn140at29_301 = { 2100 .modes = &samsung_ltn140at29_301_mode, 2101 .num_modes = 1, 2102 .bpc = 6, 2103 .size = { 2104 .width = 320, 2105 .height = 187, 2106 }, 2107 }; 2108 2109 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2110 .clock = 5500, 2111 .hdisplay = 240, 2112 .hsync_start = 240 + 16, 2113 .hsync_end = 240 + 16 + 7, 2114 .htotal = 240 + 16 + 7 + 5, 2115 .vdisplay = 320, 2116 .vsync_start = 320 + 9, 2117 .vsync_end = 320 + 9 + 1, 2118 .vtotal = 320 + 9 + 1 + 7, 2119 .vrefresh = 60, 2120 }; 2121 2122 static const struct panel_desc sharp_lq035q7db03 = { 2123 .modes = &sharp_lq035q7db03_mode, 2124 .num_modes = 1, 2125 .bpc = 6, 2126 .size = { 2127 .width = 54, 2128 .height = 72, 2129 }, 2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2131 }; 2132 2133 static const struct display_timing sharp_lq101k1ly04_timing = { 2134 .pixelclock = { 60000000, 65000000, 80000000 }, 2135 .hactive = { 1280, 1280, 1280 }, 2136 .hfront_porch = { 20, 20, 20 }, 2137 .hback_porch = { 20, 20, 20 }, 2138 .hsync_len = { 10, 10, 10 }, 2139 .vactive = { 800, 800, 800 }, 2140 .vfront_porch = { 4, 4, 4 }, 2141 .vback_porch = { 4, 4, 4 }, 2142 .vsync_len = { 4, 4, 4 }, 2143 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2144 }; 2145 2146 static const struct panel_desc sharp_lq101k1ly04 = { 2147 .timings = &sharp_lq101k1ly04_timing, 2148 .num_timings = 1, 2149 .bpc = 8, 2150 .size = { 2151 .width = 217, 2152 .height = 136, 2153 }, 2154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2155 }; 2156 2157 static const struct display_timing sharp_lq123p1jx31_timing = { 2158 .pixelclock = { 252750000, 252750000, 266604720 }, 2159 .hactive = { 2400, 2400, 2400 }, 2160 .hfront_porch = { 48, 48, 48 }, 2161 .hback_porch = { 80, 80, 84 }, 2162 .hsync_len = { 32, 32, 32 }, 2163 .vactive = { 1600, 1600, 1600 }, 2164 .vfront_porch = { 3, 3, 3 }, 2165 .vback_porch = { 33, 33, 120 }, 2166 .vsync_len = { 10, 10, 10 }, 2167 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2168 }; 2169 2170 static const struct panel_desc sharp_lq123p1jx31 = { 2171 .timings = &sharp_lq123p1jx31_timing, 2172 .num_timings = 1, 2173 .bpc = 8, 2174 .size = { 2175 .width = 259, 2176 .height = 173, 2177 }, 2178 .delay = { 2179 .prepare = 110, 2180 .enable = 50, 2181 .unprepare = 550, 2182 }, 2183 }; 2184 2185 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2186 .clock = 71100, 2187 .hdisplay = 1024, 2188 .hsync_start = 1024 + 168, 2189 .hsync_end = 1024 + 168 + 64, 2190 .htotal = 1024 + 168 + 64 + 88, 2191 .vdisplay = 768, 2192 .vsync_start = 768 + 37, 2193 .vsync_end = 768 + 37 + 2, 2194 .vtotal = 768 + 37 + 2 + 8, 2195 .vrefresh = 60, 2196 }; 2197 2198 static const struct panel_desc sharp_lq150x1lg11 = { 2199 .modes = &sharp_lq150x1lg11_mode, 2200 .num_modes = 1, 2201 .bpc = 6, 2202 .size = { 2203 .width = 304, 2204 .height = 228, 2205 }, 2206 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2207 }; 2208 2209 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2210 .clock = 33300, 2211 .hdisplay = 800, 2212 .hsync_start = 800 + 1, 2213 .hsync_end = 800 + 1 + 64, 2214 .htotal = 800 + 1 + 64 + 64, 2215 .vdisplay = 480, 2216 .vsync_start = 480 + 1, 2217 .vsync_end = 480 + 1 + 23, 2218 .vtotal = 480 + 1 + 23 + 22, 2219 .vrefresh = 60, 2220 }; 2221 2222 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2223 .modes = &shelly_sca07010_bfn_lnn_mode, 2224 .num_modes = 1, 2225 .size = { 2226 .width = 152, 2227 .height = 91, 2228 }, 2229 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2230 }; 2231 2232 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2233 .clock = 147000, 2234 .hdisplay = 1920, 2235 .hsync_start = 1920 + 16, 2236 .hsync_end = 1920 + 16 + 16, 2237 .htotal = 1920 + 16 + 16 + 32, 2238 .vdisplay = 1200, 2239 .vsync_start = 1200 + 15, 2240 .vsync_end = 1200 + 15 + 2, 2241 .vtotal = 1200 + 15 + 2 + 18, 2242 .vrefresh = 60, 2243 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2244 }; 2245 2246 static const struct panel_desc starry_kr122ea0sra = { 2247 .modes = &starry_kr122ea0sra_mode, 2248 .num_modes = 1, 2249 .size = { 2250 .width = 263, 2251 .height = 164, 2252 }, 2253 .delay = { 2254 .prepare = 10 + 200, 2255 .enable = 50, 2256 .unprepare = 10 + 500, 2257 }, 2258 }; 2259 2260 static const struct display_timing tianma_tm070jdhg30_timing = { 2261 .pixelclock = { 62600000, 68200000, 78100000 }, 2262 .hactive = { 1280, 1280, 1280 }, 2263 .hfront_porch = { 15, 64, 159 }, 2264 .hback_porch = { 5, 5, 5 }, 2265 .hsync_len = { 1, 1, 256 }, 2266 .vactive = { 800, 800, 800 }, 2267 .vfront_porch = { 3, 40, 99 }, 2268 .vback_porch = { 2, 2, 2 }, 2269 .vsync_len = { 1, 1, 128 }, 2270 .flags = DISPLAY_FLAGS_DE_HIGH, 2271 }; 2272 2273 static const struct panel_desc tianma_tm070jdhg30 = { 2274 .timings = &tianma_tm070jdhg30_timing, 2275 .num_timings = 1, 2276 .bpc = 8, 2277 .size = { 2278 .width = 151, 2279 .height = 95, 2280 }, 2281 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2282 }; 2283 2284 static const struct display_timing tianma_tm070rvhg71_timing = { 2285 .pixelclock = { 27700000, 29200000, 39600000 }, 2286 .hactive = { 800, 800, 800 }, 2287 .hfront_porch = { 12, 40, 212 }, 2288 .hback_porch = { 88, 88, 88 }, 2289 .hsync_len = { 1, 1, 40 }, 2290 .vactive = { 480, 480, 480 }, 2291 .vfront_porch = { 1, 13, 88 }, 2292 .vback_porch = { 32, 32, 32 }, 2293 .vsync_len = { 1, 1, 3 }, 2294 .flags = DISPLAY_FLAGS_DE_HIGH, 2295 }; 2296 2297 static const struct panel_desc tianma_tm070rvhg71 = { 2298 .timings = &tianma_tm070rvhg71_timing, 2299 .num_timings = 1, 2300 .bpc = 8, 2301 .size = { 2302 .width = 154, 2303 .height = 86, 2304 }, 2305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2306 }; 2307 2308 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 2309 .clock = 79500, 2310 .hdisplay = 1280, 2311 .hsync_start = 1280 + 192, 2312 .hsync_end = 1280 + 192 + 128, 2313 .htotal = 1280 + 192 + 128 + 64, 2314 .vdisplay = 768, 2315 .vsync_start = 768 + 20, 2316 .vsync_end = 768 + 20 + 7, 2317 .vtotal = 768 + 20 + 7 + 3, 2318 .vrefresh = 60, 2319 }; 2320 2321 static const struct panel_desc toshiba_lt089ac29000 = { 2322 .modes = &toshiba_lt089ac29000_mode, 2323 .num_modes = 1, 2324 .size = { 2325 .width = 194, 2326 .height = 116, 2327 }, 2328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2329 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 2330 }; 2331 2332 static const struct drm_display_mode tpk_f07a_0102_mode = { 2333 .clock = 33260, 2334 .hdisplay = 800, 2335 .hsync_start = 800 + 40, 2336 .hsync_end = 800 + 40 + 128, 2337 .htotal = 800 + 40 + 128 + 88, 2338 .vdisplay = 480, 2339 .vsync_start = 480 + 10, 2340 .vsync_end = 480 + 10 + 2, 2341 .vtotal = 480 + 10 + 2 + 33, 2342 .vrefresh = 60, 2343 }; 2344 2345 static const struct panel_desc tpk_f07a_0102 = { 2346 .modes = &tpk_f07a_0102_mode, 2347 .num_modes = 1, 2348 .size = { 2349 .width = 152, 2350 .height = 91, 2351 }, 2352 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 2353 }; 2354 2355 static const struct drm_display_mode tpk_f10a_0102_mode = { 2356 .clock = 45000, 2357 .hdisplay = 1024, 2358 .hsync_start = 1024 + 176, 2359 .hsync_end = 1024 + 176 + 5, 2360 .htotal = 1024 + 176 + 5 + 88, 2361 .vdisplay = 600, 2362 .vsync_start = 600 + 20, 2363 .vsync_end = 600 + 20 + 5, 2364 .vtotal = 600 + 20 + 5 + 25, 2365 .vrefresh = 60, 2366 }; 2367 2368 static const struct panel_desc tpk_f10a_0102 = { 2369 .modes = &tpk_f10a_0102_mode, 2370 .num_modes = 1, 2371 .size = { 2372 .width = 223, 2373 .height = 125, 2374 }, 2375 }; 2376 2377 static const struct display_timing urt_umsh_8596md_timing = { 2378 .pixelclock = { 33260000, 33260000, 33260000 }, 2379 .hactive = { 800, 800, 800 }, 2380 .hfront_porch = { 41, 41, 41 }, 2381 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 2382 .hsync_len = { 71, 128, 128 }, 2383 .vactive = { 480, 480, 480 }, 2384 .vfront_porch = { 10, 10, 10 }, 2385 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 2386 .vsync_len = { 2, 2, 2 }, 2387 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2388 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2389 }; 2390 2391 static const struct panel_desc urt_umsh_8596md_lvds = { 2392 .timings = &urt_umsh_8596md_timing, 2393 .num_timings = 1, 2394 .bpc = 6, 2395 .size = { 2396 .width = 152, 2397 .height = 91, 2398 }, 2399 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2400 }; 2401 2402 static const struct panel_desc urt_umsh_8596md_parallel = { 2403 .timings = &urt_umsh_8596md_timing, 2404 .num_timings = 1, 2405 .bpc = 6, 2406 .size = { 2407 .width = 152, 2408 .height = 91, 2409 }, 2410 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2411 }; 2412 2413 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 2414 .clock = 6410, 2415 .hdisplay = 320, 2416 .hsync_start = 320 + 20, 2417 .hsync_end = 320 + 20 + 30, 2418 .htotal = 320 + 20 + 30 + 38, 2419 .vdisplay = 240, 2420 .vsync_start = 240 + 4, 2421 .vsync_end = 240 + 4 + 3, 2422 .vtotal = 240 + 4 + 3 + 15, 2423 .vrefresh = 60, 2424 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2425 }; 2426 2427 static const struct panel_desc winstar_wf35ltiacd = { 2428 .modes = &winstar_wf35ltiacd_mode, 2429 .num_modes = 1, 2430 .bpc = 8, 2431 .size = { 2432 .width = 70, 2433 .height = 53, 2434 }, 2435 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2436 }; 2437 2438 static const struct drm_display_mode arm_rtsm_mode[] = { 2439 { 2440 .clock = 65000, 2441 .hdisplay = 1024, 2442 .hsync_start = 1024 + 24, 2443 .hsync_end = 1024 + 24 + 136, 2444 .htotal = 1024 + 24 + 136 + 160, 2445 .vdisplay = 768, 2446 .vsync_start = 768 + 3, 2447 .vsync_end = 768 + 3 + 6, 2448 .vtotal = 768 + 3 + 6 + 29, 2449 .vrefresh = 60, 2450 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2451 }, 2452 }; 2453 2454 static const struct panel_desc arm_rtsm = { 2455 .modes = arm_rtsm_mode, 2456 .num_modes = 1, 2457 .bpc = 8, 2458 .size = { 2459 .width = 400, 2460 .height = 300, 2461 }, 2462 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2463 }; 2464 2465 static const struct of_device_id platform_of_match[] = { 2466 { 2467 .compatible = "ampire,am-480272h3tmqw-t01h", 2468 .data = &ire_am_480272h3tmqw_t01h, 2469 }, { 2470 .compatible = "ampire,am800480r3tmqwa1h", 2471 .data = &ire_am800480r3tmqwa1h, 2472 }, { 2473 .compatible = "arm,rtsm-display", 2474 .data = &arm_rtsm, 2475 }, { 2476 .compatible = "auo,b101aw03", 2477 .data = &auo_b101aw03, 2478 }, { 2479 .compatible = "auo,b101ean01", 2480 .data = &auo_b101ean01, 2481 }, { 2482 .compatible = "auo,b101xtn01", 2483 .data = &auo_b101xtn01, 2484 }, { 2485 .compatible = "auo,b116xw03", 2486 .data = &auo_b116xw03, 2487 }, { 2488 .compatible = "auo,b133htn01", 2489 .data = &auo_b133htn01, 2490 }, { 2491 .compatible = "auo,b133xtn01", 2492 .data = &auo_b133xtn01, 2493 }, { 2494 .compatible = "auo,g070vvn01", 2495 .data = &auo_g070vvn01, 2496 }, { 2497 .compatible = "auo,g104sn02", 2498 .data = &auo_g104sn02, 2499 }, { 2500 .compatible = "auo,g133han01", 2501 .data = &auo_g133han01, 2502 }, { 2503 .compatible = "auo,g185han01", 2504 .data = &auo_g185han01, 2505 }, { 2506 .compatible = "auo,p320hvn03", 2507 .data = &auo_p320hvn03, 2508 }, { 2509 .compatible = "auo,t215hvn01", 2510 .data = &auo_t215hvn01, 2511 }, { 2512 .compatible = "avic,tm070ddh03", 2513 .data = &avic_tm070ddh03, 2514 }, { 2515 .compatible = "bananapi,s070wv20-ct16", 2516 .data = &bananapi_s070wv20_ct16, 2517 }, { 2518 .compatible = "boe,hv070wsa-100", 2519 .data = &boe_hv070wsa 2520 }, { 2521 .compatible = "boe,nv101wxmn51", 2522 .data = &boe_nv101wxmn51, 2523 }, { 2524 .compatible = "cdtech,s043wq26h-ct7", 2525 .data = &cdtech_s043wq26h_ct7, 2526 }, { 2527 .compatible = "cdtech,s070wv95-ct16", 2528 .data = &cdtech_s070wv95_ct16, 2529 }, { 2530 .compatible = "chunghwa,claa070wp03xg", 2531 .data = &chunghwa_claa070wp03xg, 2532 }, { 2533 .compatible = "chunghwa,claa101wa01a", 2534 .data = &chunghwa_claa101wa01a 2535 }, { 2536 .compatible = "chunghwa,claa101wb01", 2537 .data = &chunghwa_claa101wb01 2538 }, { 2539 .compatible = "dataimage,scf0700c48ggu18", 2540 .data = &dataimage_scf0700c48ggu18, 2541 }, { 2542 .compatible = "dlc,dlc0700yzg-1", 2543 .data = &dlc_dlc0700yzg_1, 2544 }, { 2545 .compatible = "dlc,dlc1010gig", 2546 .data = &dlc_dlc1010gig, 2547 }, { 2548 .compatible = "edt,et057090dhu", 2549 .data = &edt_et057090dhu, 2550 }, { 2551 .compatible = "edt,et070080dh6", 2552 .data = &edt_etm0700g0dh6, 2553 }, { 2554 .compatible = "edt,etm0700g0dh6", 2555 .data = &edt_etm0700g0dh6, 2556 }, { 2557 .compatible = "edt,etm0700g0bdh6", 2558 .data = &edt_etm0700g0bdh6, 2559 }, { 2560 .compatible = "edt,etm0700g0edh6", 2561 .data = &edt_etm0700g0bdh6, 2562 }, { 2563 .compatible = "foxlink,fl500wvr00-a0t", 2564 .data = &foxlink_fl500wvr00_a0t, 2565 }, { 2566 .compatible = "giantplus,gpg482739qs5", 2567 .data = &giantplus_gpg482739qs5 2568 }, { 2569 .compatible = "hannstar,hsd070pww1", 2570 .data = &hannstar_hsd070pww1, 2571 }, { 2572 .compatible = "hannstar,hsd100pxn1", 2573 .data = &hannstar_hsd100pxn1, 2574 }, { 2575 .compatible = "hit,tx23d38vm0caa", 2576 .data = &hitachi_tx23d38vm0caa 2577 }, { 2578 .compatible = "innolux,at043tn24", 2579 .data = &innolux_at043tn24, 2580 }, { 2581 .compatible = "innolux,at070tn92", 2582 .data = &innolux_at070tn92, 2583 }, { 2584 .compatible = "innolux,g070y2-l01", 2585 .data = &innolux_g070y2_l01, 2586 }, { 2587 .compatible = "innolux,g101ice-l01", 2588 .data = &innolux_g101ice_l01 2589 }, { 2590 .compatible = "innolux,g121i1-l01", 2591 .data = &innolux_g121i1_l01 2592 }, { 2593 .compatible = "innolux,g121x1-l03", 2594 .data = &innolux_g121x1_l03, 2595 }, { 2596 .compatible = "innolux,n116bge", 2597 .data = &innolux_n116bge, 2598 }, { 2599 .compatible = "innolux,n156bge-l21", 2600 .data = &innolux_n156bge_l21, 2601 }, { 2602 .compatible = "innolux,p120zdg-bf1", 2603 .data = &innolux_p120zdg_bf1, 2604 }, { 2605 .compatible = "innolux,zj070na-01p", 2606 .data = &innolux_zj070na_01p, 2607 }, { 2608 .compatible = "koe,tx31d200vm0baa", 2609 .data = &koe_tx31d200vm0baa, 2610 }, { 2611 .compatible = "kyo,tcg121xglp", 2612 .data = &kyo_tcg121xglp, 2613 }, { 2614 .compatible = "lg,lb070wv8", 2615 .data = &lg_lb070wv8, 2616 }, { 2617 .compatible = "lg,lp079qx1-sp0v", 2618 .data = &lg_lp079qx1_sp0v, 2619 }, { 2620 .compatible = "lg,lp097qx1-spa1", 2621 .data = &lg_lp097qx1_spa1, 2622 }, { 2623 .compatible = "lg,lp120up1", 2624 .data = &lg_lp120up1, 2625 }, { 2626 .compatible = "lg,lp129qe", 2627 .data = &lg_lp129qe, 2628 }, { 2629 .compatible = "mitsubishi,aa070mc01-ca1", 2630 .data = &mitsubishi_aa070mc01, 2631 }, { 2632 .compatible = "nec,nl12880bc20-05", 2633 .data = &nec_nl12880bc20_05, 2634 }, { 2635 .compatible = "nec,nl4827hc19-05b", 2636 .data = &nec_nl4827hc19_05b, 2637 }, { 2638 .compatible = "netron-dy,e231732", 2639 .data = &netron_dy_e231732, 2640 }, { 2641 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 2642 .data = &newhaven_nhd_43_480272ef_atxl, 2643 }, { 2644 .compatible = "nlt,nl192108ac18-02d", 2645 .data = &nlt_nl192108ac18_02d, 2646 }, { 2647 .compatible = "nvd,9128", 2648 .data = &nvd_9128, 2649 }, { 2650 .compatible = "okaya,rs800480t-7x0gp", 2651 .data = &okaya_rs800480t_7x0gp, 2652 }, { 2653 .compatible = "olimex,lcd-olinuxino-43-ts", 2654 .data = &olimex_lcd_olinuxino_43ts, 2655 }, { 2656 .compatible = "ontat,yx700wv03", 2657 .data = &ontat_yx700wv03, 2658 }, { 2659 .compatible = "ortustech,com43h4m85ulc", 2660 .data = &ortustech_com43h4m85ulc, 2661 }, { 2662 .compatible = "qiaodian,qd43003c0-40", 2663 .data = &qd43003c0_40, 2664 }, { 2665 .compatible = "rocktech,rk070er9427", 2666 .data = &rocktech_rk070er9427, 2667 }, { 2668 .compatible = "samsung,lsn122dl01-c01", 2669 .data = &samsung_lsn122dl01_c01, 2670 }, { 2671 .compatible = "samsung,ltn101nt05", 2672 .data = &samsung_ltn101nt05, 2673 }, { 2674 .compatible = "samsung,ltn140at29-301", 2675 .data = &samsung_ltn140at29_301, 2676 }, { 2677 .compatible = "sharp,lq035q7db03", 2678 .data = &sharp_lq035q7db03, 2679 }, { 2680 .compatible = "sharp,lq101k1ly04", 2681 .data = &sharp_lq101k1ly04, 2682 }, { 2683 .compatible = "sharp,lq123p1jx31", 2684 .data = &sharp_lq123p1jx31, 2685 }, { 2686 .compatible = "sharp,lq150x1lg11", 2687 .data = &sharp_lq150x1lg11, 2688 }, { 2689 .compatible = "shelly,sca07010-bfn-lnn", 2690 .data = &shelly_sca07010_bfn_lnn, 2691 }, { 2692 .compatible = "starry,kr122ea0sra", 2693 .data = &starry_kr122ea0sra, 2694 }, { 2695 .compatible = "tianma,tm070jdhg30", 2696 .data = &tianma_tm070jdhg30, 2697 }, { 2698 .compatible = "tianma,tm070rvhg71", 2699 .data = &tianma_tm070rvhg71, 2700 }, { 2701 .compatible = "toshiba,lt089ac29000", 2702 .data = &toshiba_lt089ac29000, 2703 }, { 2704 .compatible = "tpk,f07a-0102", 2705 .data = &tpk_f07a_0102, 2706 }, { 2707 .compatible = "tpk,f10a-0102", 2708 .data = &tpk_f10a_0102, 2709 }, { 2710 .compatible = "urt,umsh-8596md-t", 2711 .data = &urt_umsh_8596md_parallel, 2712 }, { 2713 .compatible = "urt,umsh-8596md-1t", 2714 .data = &urt_umsh_8596md_parallel, 2715 }, { 2716 .compatible = "urt,umsh-8596md-7t", 2717 .data = &urt_umsh_8596md_parallel, 2718 }, { 2719 .compatible = "urt,umsh-8596md-11t", 2720 .data = &urt_umsh_8596md_lvds, 2721 }, { 2722 .compatible = "urt,umsh-8596md-19t", 2723 .data = &urt_umsh_8596md_lvds, 2724 }, { 2725 .compatible = "urt,umsh-8596md-20t", 2726 .data = &urt_umsh_8596md_parallel, 2727 }, { 2728 .compatible = "winstar,wf35ltiacd", 2729 .data = &winstar_wf35ltiacd, 2730 }, { 2731 /* sentinel */ 2732 } 2733 }; 2734 MODULE_DEVICE_TABLE(of, platform_of_match); 2735 2736 static int panel_simple_platform_probe(struct platform_device *pdev) 2737 { 2738 const struct of_device_id *id; 2739 2740 id = of_match_node(platform_of_match, pdev->dev.of_node); 2741 if (!id) 2742 return -ENODEV; 2743 2744 return panel_simple_probe(&pdev->dev, id->data); 2745 } 2746 2747 static int panel_simple_platform_remove(struct platform_device *pdev) 2748 { 2749 return panel_simple_remove(&pdev->dev); 2750 } 2751 2752 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2753 { 2754 panel_simple_shutdown(&pdev->dev); 2755 } 2756 2757 static struct platform_driver panel_simple_platform_driver = { 2758 .driver = { 2759 .name = "panel-simple", 2760 .of_match_table = platform_of_match, 2761 }, 2762 .probe = panel_simple_platform_probe, 2763 .remove = panel_simple_platform_remove, 2764 .shutdown = panel_simple_platform_shutdown, 2765 }; 2766 2767 struct panel_desc_dsi { 2768 struct panel_desc desc; 2769 2770 unsigned long flags; 2771 enum mipi_dsi_pixel_format format; 2772 unsigned int lanes; 2773 }; 2774 2775 static const struct drm_display_mode auo_b080uan01_mode = { 2776 .clock = 154500, 2777 .hdisplay = 1200, 2778 .hsync_start = 1200 + 62, 2779 .hsync_end = 1200 + 62 + 4, 2780 .htotal = 1200 + 62 + 4 + 62, 2781 .vdisplay = 1920, 2782 .vsync_start = 1920 + 9, 2783 .vsync_end = 1920 + 9 + 2, 2784 .vtotal = 1920 + 9 + 2 + 8, 2785 .vrefresh = 60, 2786 }; 2787 2788 static const struct panel_desc_dsi auo_b080uan01 = { 2789 .desc = { 2790 .modes = &auo_b080uan01_mode, 2791 .num_modes = 1, 2792 .bpc = 8, 2793 .size = { 2794 .width = 108, 2795 .height = 272, 2796 }, 2797 }, 2798 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2799 .format = MIPI_DSI_FMT_RGB888, 2800 .lanes = 4, 2801 }; 2802 2803 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2804 .clock = 160000, 2805 .hdisplay = 1200, 2806 .hsync_start = 1200 + 120, 2807 .hsync_end = 1200 + 120 + 20, 2808 .htotal = 1200 + 120 + 20 + 21, 2809 .vdisplay = 1920, 2810 .vsync_start = 1920 + 21, 2811 .vsync_end = 1920 + 21 + 3, 2812 .vtotal = 1920 + 21 + 3 + 18, 2813 .vrefresh = 60, 2814 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2815 }; 2816 2817 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2818 .desc = { 2819 .modes = &boe_tv080wum_nl0_mode, 2820 .num_modes = 1, 2821 .size = { 2822 .width = 107, 2823 .height = 172, 2824 }, 2825 }, 2826 .flags = MIPI_DSI_MODE_VIDEO | 2827 MIPI_DSI_MODE_VIDEO_BURST | 2828 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2829 .format = MIPI_DSI_FMT_RGB888, 2830 .lanes = 4, 2831 }; 2832 2833 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2834 .clock = 71000, 2835 .hdisplay = 800, 2836 .hsync_start = 800 + 32, 2837 .hsync_end = 800 + 32 + 1, 2838 .htotal = 800 + 32 + 1 + 57, 2839 .vdisplay = 1280, 2840 .vsync_start = 1280 + 28, 2841 .vsync_end = 1280 + 28 + 1, 2842 .vtotal = 1280 + 28 + 1 + 14, 2843 .vrefresh = 60, 2844 }; 2845 2846 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2847 .desc = { 2848 .modes = &lg_ld070wx3_sl01_mode, 2849 .num_modes = 1, 2850 .bpc = 8, 2851 .size = { 2852 .width = 94, 2853 .height = 151, 2854 }, 2855 }, 2856 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2857 .format = MIPI_DSI_FMT_RGB888, 2858 .lanes = 4, 2859 }; 2860 2861 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2862 .clock = 67000, 2863 .hdisplay = 720, 2864 .hsync_start = 720 + 12, 2865 .hsync_end = 720 + 12 + 4, 2866 .htotal = 720 + 12 + 4 + 112, 2867 .vdisplay = 1280, 2868 .vsync_start = 1280 + 8, 2869 .vsync_end = 1280 + 8 + 4, 2870 .vtotal = 1280 + 8 + 4 + 12, 2871 .vrefresh = 60, 2872 }; 2873 2874 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2875 .desc = { 2876 .modes = &lg_lh500wx1_sd03_mode, 2877 .num_modes = 1, 2878 .bpc = 8, 2879 .size = { 2880 .width = 62, 2881 .height = 110, 2882 }, 2883 }, 2884 .flags = MIPI_DSI_MODE_VIDEO, 2885 .format = MIPI_DSI_FMT_RGB888, 2886 .lanes = 4, 2887 }; 2888 2889 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2890 .clock = 157200, 2891 .hdisplay = 1920, 2892 .hsync_start = 1920 + 154, 2893 .hsync_end = 1920 + 154 + 16, 2894 .htotal = 1920 + 154 + 16 + 32, 2895 .vdisplay = 1200, 2896 .vsync_start = 1200 + 17, 2897 .vsync_end = 1200 + 17 + 2, 2898 .vtotal = 1200 + 17 + 2 + 16, 2899 .vrefresh = 60, 2900 }; 2901 2902 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2903 .desc = { 2904 .modes = &panasonic_vvx10f004b00_mode, 2905 .num_modes = 1, 2906 .bpc = 8, 2907 .size = { 2908 .width = 217, 2909 .height = 136, 2910 }, 2911 }, 2912 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2913 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2914 .format = MIPI_DSI_FMT_RGB888, 2915 .lanes = 4, 2916 }; 2917 2918 static const struct of_device_id dsi_of_match[] = { 2919 { 2920 .compatible = "auo,b080uan01", 2921 .data = &auo_b080uan01 2922 }, { 2923 .compatible = "boe,tv080wum-nl0", 2924 .data = &boe_tv080wum_nl0 2925 }, { 2926 .compatible = "lg,ld070wx3-sl01", 2927 .data = &lg_ld070wx3_sl01 2928 }, { 2929 .compatible = "lg,lh500wx1-sd03", 2930 .data = &lg_lh500wx1_sd03 2931 }, { 2932 .compatible = "panasonic,vvx10f004b00", 2933 .data = &panasonic_vvx10f004b00 2934 }, { 2935 /* sentinel */ 2936 } 2937 }; 2938 MODULE_DEVICE_TABLE(of, dsi_of_match); 2939 2940 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2941 { 2942 const struct panel_desc_dsi *desc; 2943 const struct of_device_id *id; 2944 int err; 2945 2946 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2947 if (!id) 2948 return -ENODEV; 2949 2950 desc = id->data; 2951 2952 err = panel_simple_probe(&dsi->dev, &desc->desc); 2953 if (err < 0) 2954 return err; 2955 2956 dsi->mode_flags = desc->flags; 2957 dsi->format = desc->format; 2958 dsi->lanes = desc->lanes; 2959 2960 return mipi_dsi_attach(dsi); 2961 } 2962 2963 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2964 { 2965 int err; 2966 2967 err = mipi_dsi_detach(dsi); 2968 if (err < 0) 2969 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2970 2971 return panel_simple_remove(&dsi->dev); 2972 } 2973 2974 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2975 { 2976 panel_simple_shutdown(&dsi->dev); 2977 } 2978 2979 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2980 .driver = { 2981 .name = "panel-simple-dsi", 2982 .of_match_table = dsi_of_match, 2983 }, 2984 .probe = panel_simple_dsi_probe, 2985 .remove = panel_simple_dsi_remove, 2986 .shutdown = panel_simple_dsi_shutdown, 2987 }; 2988 2989 static int __init panel_simple_init(void) 2990 { 2991 int err; 2992 2993 err = platform_driver_register(&panel_simple_platform_driver); 2994 if (err < 0) 2995 return err; 2996 2997 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2998 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2999 if (err < 0) 3000 return err; 3001 } 3002 3003 return 0; 3004 } 3005 module_init(panel_simple_init); 3006 3007 static void __exit panel_simple_exit(void) 3008 { 3009 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 3010 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 3011 3012 platform_driver_unregister(&panel_simple_platform_driver); 3013 } 3014 module_exit(panel_simple_exit); 3015 3016 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 3017 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 3018 MODULE_LICENSE("GPL and additional rights"); 3019