1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) { 579 err = PTR_ERR(panel->enable_gpio); 580 if (err != -EPROBE_DEFER) 581 dev_err(dev, "failed to request GPIO: %d\n", err); 582 return err; 583 } 584 585 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 586 if (err) { 587 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 588 return err; 589 } 590 591 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 592 if (ddc) { 593 panel->ddc = of_find_i2c_adapter_by_node(ddc); 594 of_node_put(ddc); 595 596 if (!panel->ddc) 597 return -EPROBE_DEFER; 598 } 599 600 if (desc == &panel_dpi) { 601 /* Handle the generic panel-dpi binding */ 602 err = panel_dpi_probe(dev, panel); 603 if (err) 604 goto free_ddc; 605 desc = panel->desc; 606 } else { 607 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 608 panel_simple_parse_panel_timing_node(dev, panel, &dt); 609 } 610 611 connector_type = desc->connector_type; 612 /* Catch common mistakes for panels. */ 613 switch (connector_type) { 614 case 0: 615 dev_warn(dev, "Specify missing connector_type\n"); 616 connector_type = DRM_MODE_CONNECTOR_DPI; 617 break; 618 case DRM_MODE_CONNECTOR_LVDS: 619 WARN_ON(desc->bus_flags & 620 ~(DRM_BUS_FLAG_DE_LOW | 621 DRM_BUS_FLAG_DE_HIGH | 622 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 623 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 624 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 626 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 627 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 628 desc->bpc != 6); 629 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 630 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 631 desc->bpc != 8); 632 break; 633 case DRM_MODE_CONNECTOR_eDP: 634 dev_warn(dev, "eDP panels moved to panel-edp\n"); 635 err = -EINVAL; 636 goto free_ddc; 637 case DRM_MODE_CONNECTOR_DSI: 638 if (desc->bpc != 6 && desc->bpc != 8) 639 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 640 break; 641 case DRM_MODE_CONNECTOR_DPI: 642 bus_flags = DRM_BUS_FLAG_DE_LOW | 643 DRM_BUS_FLAG_DE_HIGH | 644 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 645 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 646 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 647 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 648 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 649 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 650 if (desc->bus_flags & ~bus_flags) 651 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 652 if (!(desc->bus_flags & bus_flags)) 653 dev_warn(dev, "Specify missing bus_flags\n"); 654 if (desc->bus_format == 0) 655 dev_warn(dev, "Specify missing bus_format\n"); 656 if (desc->bpc != 6 && desc->bpc != 8) 657 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 658 break; 659 default: 660 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 661 connector_type = DRM_MODE_CONNECTOR_DPI; 662 break; 663 } 664 665 dev_set_drvdata(dev, panel); 666 667 /* 668 * We use runtime PM for prepare / unprepare since those power the panel 669 * on and off and those can be very slow operations. This is important 670 * to optimize powering the panel on briefly to read the EDID before 671 * fully enabling the panel. 672 */ 673 pm_runtime_enable(dev); 674 pm_runtime_set_autosuspend_delay(dev, 1000); 675 pm_runtime_use_autosuspend(dev); 676 677 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 678 679 err = drm_panel_of_backlight(&panel->base); 680 if (err) { 681 dev_err_probe(dev, err, "Could not find backlight\n"); 682 goto disable_pm_runtime; 683 } 684 685 drm_panel_add(&panel->base); 686 687 return 0; 688 689 disable_pm_runtime: 690 pm_runtime_dont_use_autosuspend(dev); 691 pm_runtime_disable(dev); 692 free_ddc: 693 if (panel->ddc) 694 put_device(&panel->ddc->dev); 695 696 return err; 697 } 698 699 static void panel_simple_remove(struct device *dev) 700 { 701 struct panel_simple *panel = dev_get_drvdata(dev); 702 703 drm_panel_remove(&panel->base); 704 drm_panel_disable(&panel->base); 705 drm_panel_unprepare(&panel->base); 706 707 pm_runtime_dont_use_autosuspend(dev); 708 pm_runtime_disable(dev); 709 if (panel->ddc) 710 put_device(&panel->ddc->dev); 711 } 712 713 static void panel_simple_shutdown(struct device *dev) 714 { 715 struct panel_simple *panel = dev_get_drvdata(dev); 716 717 drm_panel_disable(&panel->base); 718 drm_panel_unprepare(&panel->base); 719 } 720 721 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 722 .clock = 71100, 723 .hdisplay = 1280, 724 .hsync_start = 1280 + 40, 725 .hsync_end = 1280 + 40 + 80, 726 .htotal = 1280 + 40 + 80 + 40, 727 .vdisplay = 800, 728 .vsync_start = 800 + 3, 729 .vsync_end = 800 + 3 + 10, 730 .vtotal = 800 + 3 + 10 + 10, 731 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 732 }; 733 734 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 735 .modes = &ire_am_1280800n3tzqw_t00h_mode, 736 .num_modes = 1, 737 .bpc = 8, 738 .size = { 739 .width = 217, 740 .height = 136, 741 }, 742 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 744 .connector_type = DRM_MODE_CONNECTOR_LVDS, 745 }; 746 747 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 748 .clock = 9000, 749 .hdisplay = 480, 750 .hsync_start = 480 + 2, 751 .hsync_end = 480 + 2 + 41, 752 .htotal = 480 + 2 + 41 + 2, 753 .vdisplay = 272, 754 .vsync_start = 272 + 2, 755 .vsync_end = 272 + 2 + 10, 756 .vtotal = 272 + 2 + 10 + 2, 757 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 758 }; 759 760 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 761 .modes = &ire_am_480272h3tmqw_t01h_mode, 762 .num_modes = 1, 763 .bpc = 8, 764 .size = { 765 .width = 105, 766 .height = 67, 767 }, 768 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 769 }; 770 771 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 772 .clock = 33333, 773 .hdisplay = 800, 774 .hsync_start = 800 + 0, 775 .hsync_end = 800 + 0 + 255, 776 .htotal = 800 + 0 + 255 + 0, 777 .vdisplay = 480, 778 .vsync_start = 480 + 2, 779 .vsync_end = 480 + 2 + 45, 780 .vtotal = 480 + 2 + 45 + 0, 781 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 782 }; 783 784 static const struct panel_desc ampire_am800480r3tmqwa1h = { 785 .modes = &ire_am800480r3tmqwa1h_mode, 786 .num_modes = 1, 787 .bpc = 6, 788 .size = { 789 .width = 152, 790 .height = 91, 791 }, 792 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 793 }; 794 795 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 796 .pixelclock = { 34500000, 39600000, 50400000 }, 797 .hactive = { 800, 800, 800 }, 798 .hfront_porch = { 12, 112, 312 }, 799 .hback_porch = { 87, 87, 48 }, 800 .hsync_len = { 1, 1, 40 }, 801 .vactive = { 600, 600, 600 }, 802 .vfront_porch = { 1, 21, 61 }, 803 .vback_porch = { 38, 38, 19 }, 804 .vsync_len = { 1, 1, 20 }, 805 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 806 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 807 DISPLAY_FLAGS_SYNC_POSEDGE, 808 }; 809 810 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 811 .timings = &ire_am800600p5tmqw_tb8h_timing, 812 .num_timings = 1, 813 .bpc = 6, 814 .size = { 815 .width = 162, 816 .height = 122, 817 }, 818 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 820 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 821 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 822 .connector_type = DRM_MODE_CONNECTOR_DPI, 823 }; 824 825 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 826 .pixelclock = { 26400000, 33300000, 46800000 }, 827 .hactive = { 800, 800, 800 }, 828 .hfront_porch = { 16, 210, 354 }, 829 .hback_porch = { 45, 36, 6 }, 830 .hsync_len = { 1, 10, 40 }, 831 .vactive = { 480, 480, 480 }, 832 .vfront_porch = { 7, 22, 147 }, 833 .vback_porch = { 22, 13, 3 }, 834 .vsync_len = { 1, 10, 20 }, 835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 837 }; 838 839 static const struct panel_desc armadeus_st0700_adapt = { 840 .timings = &santek_st0700i5y_rbslw_f_timing, 841 .num_timings = 1, 842 .bpc = 6, 843 .size = { 844 .width = 154, 845 .height = 86, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 849 }; 850 851 static const struct drm_display_mode auo_b101aw03_mode = { 852 .clock = 51450, 853 .hdisplay = 1024, 854 .hsync_start = 1024 + 156, 855 .hsync_end = 1024 + 156 + 8, 856 .htotal = 1024 + 156 + 8 + 156, 857 .vdisplay = 600, 858 .vsync_start = 600 + 16, 859 .vsync_end = 600 + 16 + 6, 860 .vtotal = 600 + 16 + 6 + 16, 861 }; 862 863 static const struct panel_desc auo_b101aw03 = { 864 .modes = &auo_b101aw03_mode, 865 .num_modes = 1, 866 .bpc = 6, 867 .size = { 868 .width = 223, 869 .height = 125, 870 }, 871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 872 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 873 .connector_type = DRM_MODE_CONNECTOR_LVDS, 874 }; 875 876 static const struct drm_display_mode auo_b101xtn01_mode = { 877 .clock = 72000, 878 .hdisplay = 1366, 879 .hsync_start = 1366 + 20, 880 .hsync_end = 1366 + 20 + 70, 881 .htotal = 1366 + 20 + 70, 882 .vdisplay = 768, 883 .vsync_start = 768 + 14, 884 .vsync_end = 768 + 14 + 42, 885 .vtotal = 768 + 14 + 42, 886 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 887 }; 888 889 static const struct panel_desc auo_b101xtn01 = { 890 .modes = &auo_b101xtn01_mode, 891 .num_modes = 1, 892 .bpc = 6, 893 .size = { 894 .width = 223, 895 .height = 125, 896 }, 897 }; 898 899 static const struct display_timing auo_g070vvn01_timings = { 900 .pixelclock = { 33300000, 34209000, 45000000 }, 901 .hactive = { 800, 800, 800 }, 902 .hfront_porch = { 20, 40, 200 }, 903 .hback_porch = { 87, 40, 1 }, 904 .hsync_len = { 1, 48, 87 }, 905 .vactive = { 480, 480, 480 }, 906 .vfront_porch = { 5, 13, 200 }, 907 .vback_porch = { 31, 31, 29 }, 908 .vsync_len = { 1, 1, 3 }, 909 }; 910 911 static const struct panel_desc auo_g070vvn01 = { 912 .timings = &auo_g070vvn01_timings, 913 .num_timings = 1, 914 .bpc = 8, 915 .size = { 916 .width = 152, 917 .height = 91, 918 }, 919 .delay = { 920 .prepare = 200, 921 .enable = 50, 922 .disable = 50, 923 .unprepare = 1000, 924 }, 925 }; 926 927 static const struct drm_display_mode auo_g101evn010_mode = { 928 .clock = 68930, 929 .hdisplay = 1280, 930 .hsync_start = 1280 + 82, 931 .hsync_end = 1280 + 82 + 2, 932 .htotal = 1280 + 82 + 2 + 84, 933 .vdisplay = 800, 934 .vsync_start = 800 + 8, 935 .vsync_end = 800 + 8 + 2, 936 .vtotal = 800 + 8 + 2 + 6, 937 }; 938 939 static const struct panel_desc auo_g101evn010 = { 940 .modes = &auo_g101evn010_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 216, 945 .height = 135, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .connector_type = DRM_MODE_CONNECTOR_LVDS, 949 }; 950 951 static const struct drm_display_mode auo_g104sn02_mode = { 952 .clock = 40000, 953 .hdisplay = 800, 954 .hsync_start = 800 + 40, 955 .hsync_end = 800 + 40 + 216, 956 .htotal = 800 + 40 + 216 + 128, 957 .vdisplay = 600, 958 .vsync_start = 600 + 10, 959 .vsync_end = 600 + 10 + 35, 960 .vtotal = 600 + 10 + 35 + 2, 961 }; 962 963 static const struct panel_desc auo_g104sn02 = { 964 .modes = &auo_g104sn02_mode, 965 .num_modes = 1, 966 .bpc = 8, 967 .size = { 968 .width = 211, 969 .height = 158, 970 }, 971 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 972 .connector_type = DRM_MODE_CONNECTOR_LVDS, 973 }; 974 975 static const struct drm_display_mode auo_g121ean01_mode = { 976 .clock = 66700, 977 .hdisplay = 1280, 978 .hsync_start = 1280 + 58, 979 .hsync_end = 1280 + 58 + 8, 980 .htotal = 1280 + 58 + 8 + 70, 981 .vdisplay = 800, 982 .vsync_start = 800 + 6, 983 .vsync_end = 800 + 6 + 4, 984 .vtotal = 800 + 6 + 4 + 10, 985 }; 986 987 static const struct panel_desc auo_g121ean01 = { 988 .modes = &auo_g121ean01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 261, 993 .height = 163, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g133han01_timings = { 1000 .pixelclock = { 134000000, 141200000, 149000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 39, 58, 77 }, 1003 .hback_porch = { 59, 88, 117 }, 1004 .hsync_len = { 28, 42, 56 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 3, 8, 11 }, 1007 .vback_porch = { 5, 14, 19 }, 1008 .vsync_len = { 4, 14, 19 }, 1009 }; 1010 1011 static const struct panel_desc auo_g133han01 = { 1012 .timings = &auo_g133han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 293, 1017 .height = 165, 1018 }, 1019 .delay = { 1020 .prepare = 200, 1021 .enable = 50, 1022 .disable = 50, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct drm_display_mode auo_g156xtn01_mode = { 1030 .clock = 76000, 1031 .hdisplay = 1366, 1032 .hsync_start = 1366 + 33, 1033 .hsync_end = 1366 + 33 + 67, 1034 .htotal = 1560, 1035 .vdisplay = 768, 1036 .vsync_start = 768 + 4, 1037 .vsync_end = 768 + 4 + 4, 1038 .vtotal = 806, 1039 }; 1040 1041 static const struct panel_desc auo_g156xtn01 = { 1042 .modes = &auo_g156xtn01_mode, 1043 .num_modes = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 344, 1047 .height = 194, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1051 }; 1052 1053 static const struct display_timing auo_g185han01_timings = { 1054 .pixelclock = { 120000000, 144000000, 175000000 }, 1055 .hactive = { 1920, 1920, 1920 }, 1056 .hfront_porch = { 36, 120, 148 }, 1057 .hback_porch = { 24, 88, 108 }, 1058 .hsync_len = { 20, 48, 64 }, 1059 .vactive = { 1080, 1080, 1080 }, 1060 .vfront_porch = { 6, 10, 40 }, 1061 .vback_porch = { 2, 5, 20 }, 1062 .vsync_len = { 2, 5, 20 }, 1063 }; 1064 1065 static const struct panel_desc auo_g185han01 = { 1066 .timings = &auo_g185han01_timings, 1067 .num_timings = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 409, 1071 .height = 230, 1072 }, 1073 .delay = { 1074 .prepare = 50, 1075 .enable = 200, 1076 .disable = 110, 1077 .unprepare = 1000, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g190ean01_timings = { 1084 .pixelclock = { 90000000, 108000000, 135000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 126, 184, 1266 }, 1087 .hback_porch = { 84, 122, 844 }, 1088 .hsync_len = { 70, 102, 704 }, 1089 .vactive = { 1024, 1024, 1024 }, 1090 .vfront_porch = { 4, 26, 76 }, 1091 .vback_porch = { 2, 8, 25 }, 1092 .vsync_len = { 2, 8, 25 }, 1093 }; 1094 1095 static const struct panel_desc auo_g190ean01 = { 1096 .timings = &auo_g190ean01_timings, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 376, 1101 .height = 301, 1102 }, 1103 .delay = { 1104 .prepare = 50, 1105 .enable = 200, 1106 .disable = 110, 1107 .unprepare = 1000, 1108 }, 1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1111 }; 1112 1113 static const struct display_timing auo_p320hvn03_timings = { 1114 .pixelclock = { 106000000, 148500000, 164000000 }, 1115 .hactive = { 1920, 1920, 1920 }, 1116 .hfront_porch = { 25, 50, 130 }, 1117 .hback_porch = { 25, 50, 130 }, 1118 .hsync_len = { 20, 40, 105 }, 1119 .vactive = { 1080, 1080, 1080 }, 1120 .vfront_porch = { 8, 17, 150 }, 1121 .vback_porch = { 8, 17, 150 }, 1122 .vsync_len = { 4, 11, 100 }, 1123 }; 1124 1125 static const struct panel_desc auo_p320hvn03 = { 1126 .timings = &auo_p320hvn03_timings, 1127 .num_timings = 1, 1128 .bpc = 8, 1129 .size = { 1130 .width = 698, 1131 .height = 393, 1132 }, 1133 .delay = { 1134 .prepare = 1, 1135 .enable = 450, 1136 .unprepare = 500, 1137 }, 1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1139 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1140 }; 1141 1142 static const struct drm_display_mode auo_t215hvn01_mode = { 1143 .clock = 148800, 1144 .hdisplay = 1920, 1145 .hsync_start = 1920 + 88, 1146 .hsync_end = 1920 + 88 + 44, 1147 .htotal = 1920 + 88 + 44 + 148, 1148 .vdisplay = 1080, 1149 .vsync_start = 1080 + 4, 1150 .vsync_end = 1080 + 4 + 5, 1151 .vtotal = 1080 + 4 + 5 + 36, 1152 }; 1153 1154 static const struct panel_desc auo_t215hvn01 = { 1155 .modes = &auo_t215hvn01_mode, 1156 .num_modes = 1, 1157 .bpc = 8, 1158 .size = { 1159 .width = 430, 1160 .height = 270, 1161 }, 1162 .delay = { 1163 .disable = 5, 1164 .unprepare = 1000, 1165 } 1166 }; 1167 1168 static const struct drm_display_mode avic_tm070ddh03_mode = { 1169 .clock = 51200, 1170 .hdisplay = 1024, 1171 .hsync_start = 1024 + 160, 1172 .hsync_end = 1024 + 160 + 4, 1173 .htotal = 1024 + 160 + 4 + 156, 1174 .vdisplay = 600, 1175 .vsync_start = 600 + 17, 1176 .vsync_end = 600 + 17 + 1, 1177 .vtotal = 600 + 17 + 1 + 17, 1178 }; 1179 1180 static const struct panel_desc avic_tm070ddh03 = { 1181 .modes = &avic_tm070ddh03_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 154, 1186 .height = 90, 1187 }, 1188 .delay = { 1189 .prepare = 20, 1190 .enable = 200, 1191 .disable = 200, 1192 }, 1193 }; 1194 1195 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1196 .clock = 30000, 1197 .hdisplay = 800, 1198 .hsync_start = 800 + 40, 1199 .hsync_end = 800 + 40 + 48, 1200 .htotal = 800 + 40 + 48 + 40, 1201 .vdisplay = 480, 1202 .vsync_start = 480 + 13, 1203 .vsync_end = 480 + 13 + 3, 1204 .vtotal = 480 + 13 + 3 + 29, 1205 }; 1206 1207 static const struct panel_desc bananapi_s070wv20_ct16 = { 1208 .modes = &bananapi_s070wv20_ct16_mode, 1209 .num_modes = 1, 1210 .bpc = 6, 1211 .size = { 1212 .width = 154, 1213 .height = 86, 1214 }, 1215 }; 1216 1217 static const struct drm_display_mode boe_hv070wsa_mode = { 1218 .clock = 42105, 1219 .hdisplay = 1024, 1220 .hsync_start = 1024 + 30, 1221 .hsync_end = 1024 + 30 + 30, 1222 .htotal = 1024 + 30 + 30 + 30, 1223 .vdisplay = 600, 1224 .vsync_start = 600 + 10, 1225 .vsync_end = 600 + 10 + 10, 1226 .vtotal = 600 + 10 + 10 + 10, 1227 }; 1228 1229 static const struct panel_desc boe_hv070wsa = { 1230 .modes = &boe_hv070wsa_mode, 1231 .num_modes = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 154, 1235 .height = 90, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1240 }; 1241 1242 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1243 .clock = 9000, 1244 .hdisplay = 480, 1245 .hsync_start = 480 + 5, 1246 .hsync_end = 480 + 5 + 5, 1247 .htotal = 480 + 5 + 5 + 40, 1248 .vdisplay = 272, 1249 .vsync_start = 272 + 8, 1250 .vsync_end = 272 + 8 + 8, 1251 .vtotal = 272 + 8 + 8 + 8, 1252 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1253 }; 1254 1255 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1256 .modes = &cdtech_s043wq26h_ct7_mode, 1257 .num_modes = 1, 1258 .bpc = 8, 1259 .size = { 1260 .width = 95, 1261 .height = 54, 1262 }, 1263 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1264 }; 1265 1266 /* S070PWS19HP-FC21 2017/04/22 */ 1267 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1268 .clock = 51200, 1269 .hdisplay = 1024, 1270 .hsync_start = 1024 + 160, 1271 .hsync_end = 1024 + 160 + 20, 1272 .htotal = 1024 + 160 + 20 + 140, 1273 .vdisplay = 600, 1274 .vsync_start = 600 + 12, 1275 .vsync_end = 600 + 12 + 3, 1276 .vtotal = 600 + 12 + 3 + 20, 1277 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1278 }; 1279 1280 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1281 .modes = &cdtech_s070pws19hp_fc21_mode, 1282 .num_modes = 1, 1283 .bpc = 6, 1284 .size = { 1285 .width = 154, 1286 .height = 86, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1289 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1290 .connector_type = DRM_MODE_CONNECTOR_DPI, 1291 }; 1292 1293 /* S070SWV29HG-DC44 2017/09/21 */ 1294 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1295 .clock = 33300, 1296 .hdisplay = 800, 1297 .hsync_start = 800 + 210, 1298 .hsync_end = 800 + 210 + 2, 1299 .htotal = 800 + 210 + 2 + 44, 1300 .vdisplay = 480, 1301 .vsync_start = 480 + 22, 1302 .vsync_end = 480 + 22 + 2, 1303 .vtotal = 480 + 22 + 2 + 21, 1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1305 }; 1306 1307 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1308 .modes = &cdtech_s070swv29hg_dc44_mode, 1309 .num_modes = 1, 1310 .bpc = 6, 1311 .size = { 1312 .width = 154, 1313 .height = 86, 1314 }, 1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1317 .connector_type = DRM_MODE_CONNECTOR_DPI, 1318 }; 1319 1320 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1321 .clock = 35000, 1322 .hdisplay = 800, 1323 .hsync_start = 800 + 40, 1324 .hsync_end = 800 + 40 + 40, 1325 .htotal = 800 + 40 + 40 + 48, 1326 .vdisplay = 480, 1327 .vsync_start = 480 + 29, 1328 .vsync_end = 480 + 29 + 13, 1329 .vtotal = 480 + 29 + 13 + 3, 1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1331 }; 1332 1333 static const struct panel_desc cdtech_s070wv95_ct16 = { 1334 .modes = &cdtech_s070wv95_ct16_mode, 1335 .num_modes = 1, 1336 .bpc = 8, 1337 .size = { 1338 .width = 154, 1339 .height = 85, 1340 }, 1341 }; 1342 1343 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1344 .pixelclock = { 68900000, 71100000, 73400000 }, 1345 .hactive = { 1280, 1280, 1280 }, 1346 .hfront_porch = { 65, 80, 95 }, 1347 .hback_porch = { 64, 79, 94 }, 1348 .hsync_len = { 1, 1, 1 }, 1349 .vactive = { 800, 800, 800 }, 1350 .vfront_porch = { 7, 11, 14 }, 1351 .vback_porch = { 7, 11, 14 }, 1352 .vsync_len = { 1, 1, 1 }, 1353 .flags = DISPLAY_FLAGS_DE_HIGH, 1354 }; 1355 1356 static const struct panel_desc chefree_ch101olhlwh_002 = { 1357 .timings = &chefree_ch101olhlwh_002_timing, 1358 .num_timings = 1, 1359 .bpc = 8, 1360 .size = { 1361 .width = 217, 1362 .height = 135, 1363 }, 1364 .delay = { 1365 .enable = 200, 1366 .disable = 200, 1367 }, 1368 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1371 }; 1372 1373 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1374 .clock = 66770, 1375 .hdisplay = 800, 1376 .hsync_start = 800 + 49, 1377 .hsync_end = 800 + 49 + 33, 1378 .htotal = 800 + 49 + 33 + 17, 1379 .vdisplay = 1280, 1380 .vsync_start = 1280 + 1, 1381 .vsync_end = 1280 + 1 + 7, 1382 .vtotal = 1280 + 1 + 7 + 15, 1383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1384 }; 1385 1386 static const struct panel_desc chunghwa_claa070wp03xg = { 1387 .modes = &chunghwa_claa070wp03xg_mode, 1388 .num_modes = 1, 1389 .bpc = 6, 1390 .size = { 1391 .width = 94, 1392 .height = 150, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1395 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1396 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1397 }; 1398 1399 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1400 .clock = 72070, 1401 .hdisplay = 1366, 1402 .hsync_start = 1366 + 58, 1403 .hsync_end = 1366 + 58 + 58, 1404 .htotal = 1366 + 58 + 58 + 58, 1405 .vdisplay = 768, 1406 .vsync_start = 768 + 4, 1407 .vsync_end = 768 + 4 + 4, 1408 .vtotal = 768 + 4 + 4 + 4, 1409 }; 1410 1411 static const struct panel_desc chunghwa_claa101wa01a = { 1412 .modes = &chunghwa_claa101wa01a_mode, 1413 .num_modes = 1, 1414 .bpc = 6, 1415 .size = { 1416 .width = 220, 1417 .height = 120, 1418 }, 1419 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1420 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1421 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1422 }; 1423 1424 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1425 .clock = 69300, 1426 .hdisplay = 1366, 1427 .hsync_start = 1366 + 48, 1428 .hsync_end = 1366 + 48 + 32, 1429 .htotal = 1366 + 48 + 32 + 20, 1430 .vdisplay = 768, 1431 .vsync_start = 768 + 16, 1432 .vsync_end = 768 + 16 + 8, 1433 .vtotal = 768 + 16 + 8 + 16, 1434 }; 1435 1436 static const struct panel_desc chunghwa_claa101wb01 = { 1437 .modes = &chunghwa_claa101wb01_mode, 1438 .num_modes = 1, 1439 .bpc = 6, 1440 .size = { 1441 .width = 223, 1442 .height = 125, 1443 }, 1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1446 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1447 }; 1448 1449 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1450 .pixelclock = { 5000000, 9000000, 12000000 }, 1451 .hactive = { 480, 480, 480 }, 1452 .hfront_porch = { 12, 12, 12 }, 1453 .hback_porch = { 12, 12, 12 }, 1454 .hsync_len = { 21, 21, 21 }, 1455 .vactive = { 272, 272, 272 }, 1456 .vfront_porch = { 4, 4, 4 }, 1457 .vback_porch = { 4, 4, 4 }, 1458 .vsync_len = { 8, 8, 8 }, 1459 }; 1460 1461 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1462 .timings = &dataimage_fg040346dsswbg04_timing, 1463 .num_timings = 1, 1464 .bpc = 8, 1465 .size = { 1466 .width = 95, 1467 .height = 54, 1468 }, 1469 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1470 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1471 .connector_type = DRM_MODE_CONNECTOR_DPI, 1472 }; 1473 1474 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1475 .pixelclock = { 68900000, 71110000, 73400000 }, 1476 .hactive = { 1280, 1280, 1280 }, 1477 .vactive = { 800, 800, 800 }, 1478 .hback_porch = { 100, 100, 100 }, 1479 .hfront_porch = { 100, 100, 100 }, 1480 .vback_porch = { 5, 5, 5 }, 1481 .vfront_porch = { 5, 5, 5 }, 1482 .hsync_len = { 24, 24, 24 }, 1483 .vsync_len = { 3, 3, 3 }, 1484 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1485 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1486 }; 1487 1488 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1489 .timings = &dataimage_fg1001l0dsswmg01_timing, 1490 .num_timings = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 217, 1494 .height = 136, 1495 }, 1496 }; 1497 1498 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1499 .clock = 33260, 1500 .hdisplay = 800, 1501 .hsync_start = 800 + 40, 1502 .hsync_end = 800 + 40 + 128, 1503 .htotal = 800 + 40 + 128 + 88, 1504 .vdisplay = 480, 1505 .vsync_start = 480 + 10, 1506 .vsync_end = 480 + 10 + 2, 1507 .vtotal = 480 + 10 + 2 + 33, 1508 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1509 }; 1510 1511 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1512 .modes = &dataimage_scf0700c48ggu18_mode, 1513 .num_modes = 1, 1514 .bpc = 8, 1515 .size = { 1516 .width = 152, 1517 .height = 91, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1521 }; 1522 1523 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1524 .pixelclock = { 45000000, 51200000, 57000000 }, 1525 .hactive = { 1024, 1024, 1024 }, 1526 .hfront_porch = { 100, 106, 113 }, 1527 .hback_porch = { 100, 106, 113 }, 1528 .hsync_len = { 100, 108, 114 }, 1529 .vactive = { 600, 600, 600 }, 1530 .vfront_porch = { 8, 11, 15 }, 1531 .vback_porch = { 8, 11, 15 }, 1532 .vsync_len = { 9, 13, 15 }, 1533 .flags = DISPLAY_FLAGS_DE_HIGH, 1534 }; 1535 1536 static const struct panel_desc dlc_dlc0700yzg_1 = { 1537 .timings = &dlc_dlc0700yzg_1_timing, 1538 .num_timings = 1, 1539 .bpc = 6, 1540 .size = { 1541 .width = 154, 1542 .height = 86, 1543 }, 1544 .delay = { 1545 .prepare = 30, 1546 .enable = 200, 1547 .disable = 200, 1548 }, 1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1551 }; 1552 1553 static const struct display_timing dlc_dlc1010gig_timing = { 1554 .pixelclock = { 68900000, 71100000, 73400000 }, 1555 .hactive = { 1280, 1280, 1280 }, 1556 .hfront_porch = { 43, 53, 63 }, 1557 .hback_porch = { 43, 53, 63 }, 1558 .hsync_len = { 44, 54, 64 }, 1559 .vactive = { 800, 800, 800 }, 1560 .vfront_porch = { 5, 8, 11 }, 1561 .vback_porch = { 5, 8, 11 }, 1562 .vsync_len = { 5, 7, 11 }, 1563 .flags = DISPLAY_FLAGS_DE_HIGH, 1564 }; 1565 1566 static const struct panel_desc dlc_dlc1010gig = { 1567 .timings = &dlc_dlc1010gig_timing, 1568 .num_timings = 1, 1569 .bpc = 8, 1570 .size = { 1571 .width = 216, 1572 .height = 135, 1573 }, 1574 .delay = { 1575 .prepare = 60, 1576 .enable = 150, 1577 .disable = 100, 1578 .unprepare = 60, 1579 }, 1580 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1581 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1582 }; 1583 1584 static const struct drm_display_mode edt_et035012dm6_mode = { 1585 .clock = 6500, 1586 .hdisplay = 320, 1587 .hsync_start = 320 + 20, 1588 .hsync_end = 320 + 20 + 30, 1589 .htotal = 320 + 20 + 68, 1590 .vdisplay = 240, 1591 .vsync_start = 240 + 4, 1592 .vsync_end = 240 + 4 + 4, 1593 .vtotal = 240 + 4 + 4 + 14, 1594 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1595 }; 1596 1597 static const struct panel_desc edt_et035012dm6 = { 1598 .modes = &edt_et035012dm6_mode, 1599 .num_modes = 1, 1600 .bpc = 8, 1601 .size = { 1602 .width = 70, 1603 .height = 52, 1604 }, 1605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1606 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1607 }; 1608 1609 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1610 .clock = 6520, 1611 .hdisplay = 320, 1612 .hsync_start = 320 + 20, 1613 .hsync_end = 320 + 20 + 68, 1614 .htotal = 320 + 20 + 68, 1615 .vdisplay = 240, 1616 .vsync_start = 240 + 4, 1617 .vsync_end = 240 + 4 + 18, 1618 .vtotal = 240 + 4 + 18, 1619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1620 }; 1621 1622 static const struct panel_desc edt_etm0350g0dh6 = { 1623 .modes = &edt_etm0350g0dh6_mode, 1624 .num_modes = 1, 1625 .bpc = 6, 1626 .size = { 1627 .width = 70, 1628 .height = 53, 1629 }, 1630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1632 .connector_type = DRM_MODE_CONNECTOR_DPI, 1633 }; 1634 1635 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1636 .clock = 10870, 1637 .hdisplay = 480, 1638 .hsync_start = 480 + 8, 1639 .hsync_end = 480 + 8 + 4, 1640 .htotal = 480 + 8 + 4 + 41, 1641 1642 /* 1643 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1644 * fb_align 1645 */ 1646 1647 .vdisplay = 288, 1648 .vsync_start = 288 + 2, 1649 .vsync_end = 288 + 2 + 4, 1650 .vtotal = 288 + 2 + 4 + 10, 1651 }; 1652 1653 static const struct panel_desc edt_etm043080dh6gp = { 1654 .modes = &edt_etm043080dh6gp_mode, 1655 .num_modes = 1, 1656 .bpc = 8, 1657 .size = { 1658 .width = 100, 1659 .height = 65, 1660 }, 1661 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1662 .connector_type = DRM_MODE_CONNECTOR_DPI, 1663 }; 1664 1665 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1666 .clock = 9000, 1667 .hdisplay = 480, 1668 .hsync_start = 480 + 2, 1669 .hsync_end = 480 + 2 + 41, 1670 .htotal = 480 + 2 + 41 + 2, 1671 .vdisplay = 272, 1672 .vsync_start = 272 + 2, 1673 .vsync_end = 272 + 2 + 10, 1674 .vtotal = 272 + 2 + 10 + 2, 1675 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1676 }; 1677 1678 static const struct panel_desc edt_etm0430g0dh6 = { 1679 .modes = &edt_etm0430g0dh6_mode, 1680 .num_modes = 1, 1681 .bpc = 6, 1682 .size = { 1683 .width = 95, 1684 .height = 54, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1687 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1688 .connector_type = DRM_MODE_CONNECTOR_DPI, 1689 }; 1690 1691 static const struct drm_display_mode edt_et057090dhu_mode = { 1692 .clock = 25175, 1693 .hdisplay = 640, 1694 .hsync_start = 640 + 16, 1695 .hsync_end = 640 + 16 + 30, 1696 .htotal = 640 + 16 + 30 + 114, 1697 .vdisplay = 480, 1698 .vsync_start = 480 + 10, 1699 .vsync_end = 480 + 10 + 3, 1700 .vtotal = 480 + 10 + 3 + 32, 1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1702 }; 1703 1704 static const struct panel_desc edt_et057090dhu = { 1705 .modes = &edt_et057090dhu_mode, 1706 .num_modes = 1, 1707 .bpc = 6, 1708 .size = { 1709 .width = 115, 1710 .height = 86, 1711 }, 1712 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1713 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1714 .connector_type = DRM_MODE_CONNECTOR_DPI, 1715 }; 1716 1717 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1718 .clock = 33260, 1719 .hdisplay = 800, 1720 .hsync_start = 800 + 40, 1721 .hsync_end = 800 + 40 + 128, 1722 .htotal = 800 + 40 + 128 + 88, 1723 .vdisplay = 480, 1724 .vsync_start = 480 + 10, 1725 .vsync_end = 480 + 10 + 2, 1726 .vtotal = 480 + 10 + 2 + 33, 1727 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1728 }; 1729 1730 static const struct panel_desc edt_etm0700g0dh6 = { 1731 .modes = &edt_etm0700g0dh6_mode, 1732 .num_modes = 1, 1733 .bpc = 6, 1734 .size = { 1735 .width = 152, 1736 .height = 91, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1740 .connector_type = DRM_MODE_CONNECTOR_DPI, 1741 }; 1742 1743 static const struct panel_desc edt_etm0700g0bdh6 = { 1744 .modes = &edt_etm0700g0dh6_mode, 1745 .num_modes = 1, 1746 .bpc = 6, 1747 .size = { 1748 .width = 152, 1749 .height = 91, 1750 }, 1751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1753 .connector_type = DRM_MODE_CONNECTOR_DPI, 1754 }; 1755 1756 static const struct display_timing edt_etml0700y5dha_timing = { 1757 .pixelclock = { 40800000, 51200000, 67200000 }, 1758 .hactive = { 1024, 1024, 1024 }, 1759 .hfront_porch = { 30, 106, 125 }, 1760 .hback_porch = { 30, 106, 125 }, 1761 .hsync_len = { 30, 108, 126 }, 1762 .vactive = { 600, 600, 600 }, 1763 .vfront_porch = { 3, 12, 67}, 1764 .vback_porch = { 3, 12, 67 }, 1765 .vsync_len = { 4, 11, 66 }, 1766 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1767 DISPLAY_FLAGS_DE_HIGH, 1768 }; 1769 1770 static const struct panel_desc edt_etml0700y5dha = { 1771 .timings = &edt_etml0700y5dha_timing, 1772 .num_timings = 1, 1773 .bpc = 8, 1774 .size = { 1775 .width = 155, 1776 .height = 86, 1777 }, 1778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1779 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1780 }; 1781 1782 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1783 .clock = 25175, 1784 .hdisplay = 640, 1785 .hsync_start = 640, 1786 .hsync_end = 640 + 16, 1787 .htotal = 640 + 16 + 30 + 114, 1788 .vdisplay = 480, 1789 .vsync_start = 480 + 10, 1790 .vsync_end = 480 + 10 + 3, 1791 .vtotal = 480 + 10 + 3 + 35, 1792 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1793 }; 1794 1795 static const struct panel_desc edt_etmv570g2dhu = { 1796 .modes = &edt_etmv570g2dhu_mode, 1797 .num_modes = 1, 1798 .bpc = 6, 1799 .size = { 1800 .width = 115, 1801 .height = 86, 1802 }, 1803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1805 .connector_type = DRM_MODE_CONNECTOR_DPI, 1806 }; 1807 1808 static const struct display_timing eink_vb3300_kca_timing = { 1809 .pixelclock = { 40000000, 40000000, 40000000 }, 1810 .hactive = { 334, 334, 334 }, 1811 .hfront_porch = { 1, 1, 1 }, 1812 .hback_porch = { 1, 1, 1 }, 1813 .hsync_len = { 1, 1, 1 }, 1814 .vactive = { 1405, 1405, 1405 }, 1815 .vfront_porch = { 1, 1, 1 }, 1816 .vback_porch = { 1, 1, 1 }, 1817 .vsync_len = { 1, 1, 1 }, 1818 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1819 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1820 }; 1821 1822 static const struct panel_desc eink_vb3300_kca = { 1823 .timings = &eink_vb3300_kca_timing, 1824 .num_timings = 1, 1825 .bpc = 6, 1826 .size = { 1827 .width = 157, 1828 .height = 209, 1829 }, 1830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1832 .connector_type = DRM_MODE_CONNECTOR_DPI, 1833 }; 1834 1835 static const struct display_timing evervision_vgg804821_timing = { 1836 .pixelclock = { 27600000, 33300000, 50000000 }, 1837 .hactive = { 800, 800, 800 }, 1838 .hfront_porch = { 40, 66, 70 }, 1839 .hback_porch = { 40, 67, 70 }, 1840 .hsync_len = { 40, 67, 70 }, 1841 .vactive = { 480, 480, 480 }, 1842 .vfront_porch = { 6, 10, 10 }, 1843 .vback_porch = { 7, 11, 11 }, 1844 .vsync_len = { 7, 11, 11 }, 1845 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1846 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1847 DISPLAY_FLAGS_SYNC_NEGEDGE, 1848 }; 1849 1850 static const struct panel_desc evervision_vgg804821 = { 1851 .timings = &evervision_vgg804821_timing, 1852 .num_timings = 1, 1853 .bpc = 8, 1854 .size = { 1855 .width = 108, 1856 .height = 64, 1857 }, 1858 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1860 }; 1861 1862 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1863 .clock = 32260, 1864 .hdisplay = 800, 1865 .hsync_start = 800 + 168, 1866 .hsync_end = 800 + 168 + 64, 1867 .htotal = 800 + 168 + 64 + 88, 1868 .vdisplay = 480, 1869 .vsync_start = 480 + 37, 1870 .vsync_end = 480 + 37 + 2, 1871 .vtotal = 480 + 37 + 2 + 8, 1872 }; 1873 1874 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1875 .modes = &foxlink_fl500wvr00_a0t_mode, 1876 .num_modes = 1, 1877 .bpc = 8, 1878 .size = { 1879 .width = 108, 1880 .height = 65, 1881 }, 1882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1883 }; 1884 1885 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1886 { /* 60 Hz */ 1887 .clock = 6000, 1888 .hdisplay = 320, 1889 .hsync_start = 320 + 44, 1890 .hsync_end = 320 + 44 + 16, 1891 .htotal = 320 + 44 + 16 + 20, 1892 .vdisplay = 240, 1893 .vsync_start = 240 + 2, 1894 .vsync_end = 240 + 2 + 6, 1895 .vtotal = 240 + 2 + 6 + 2, 1896 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1897 }, 1898 { /* 50 Hz */ 1899 .clock = 5400, 1900 .hdisplay = 320, 1901 .hsync_start = 320 + 56, 1902 .hsync_end = 320 + 56 + 16, 1903 .htotal = 320 + 56 + 16 + 40, 1904 .vdisplay = 240, 1905 .vsync_start = 240 + 2, 1906 .vsync_end = 240 + 2 + 6, 1907 .vtotal = 240 + 2 + 6 + 2, 1908 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1909 }, 1910 }; 1911 1912 static const struct panel_desc frida_frd350h54004 = { 1913 .modes = frida_frd350h54004_modes, 1914 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1915 .bpc = 8, 1916 .size = { 1917 .width = 77, 1918 .height = 64, 1919 }, 1920 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1921 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1922 .connector_type = DRM_MODE_CONNECTOR_DPI, 1923 }; 1924 1925 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1926 .clock = 67185, 1927 .hdisplay = 800, 1928 .hsync_start = 800 + 20, 1929 .hsync_end = 800 + 20 + 24, 1930 .htotal = 800 + 20 + 24 + 20, 1931 .vdisplay = 1280, 1932 .vsync_start = 1280 + 4, 1933 .vsync_end = 1280 + 4 + 8, 1934 .vtotal = 1280 + 4 + 8 + 4, 1935 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1936 }; 1937 1938 static const struct panel_desc friendlyarm_hd702e = { 1939 .modes = &friendlyarm_hd702e_mode, 1940 .num_modes = 1, 1941 .size = { 1942 .width = 94, 1943 .height = 151, 1944 }, 1945 }; 1946 1947 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1948 .clock = 9000, 1949 .hdisplay = 480, 1950 .hsync_start = 480 + 5, 1951 .hsync_end = 480 + 5 + 1, 1952 .htotal = 480 + 5 + 1 + 40, 1953 .vdisplay = 272, 1954 .vsync_start = 272 + 8, 1955 .vsync_end = 272 + 8 + 1, 1956 .vtotal = 272 + 8 + 1 + 8, 1957 }; 1958 1959 static const struct panel_desc giantplus_gpg482739qs5 = { 1960 .modes = &giantplus_gpg482739qs5_mode, 1961 .num_modes = 1, 1962 .bpc = 8, 1963 .size = { 1964 .width = 95, 1965 .height = 54, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1968 }; 1969 1970 static const struct display_timing giantplus_gpm940b0_timing = { 1971 .pixelclock = { 13500000, 27000000, 27500000 }, 1972 .hactive = { 320, 320, 320 }, 1973 .hfront_porch = { 14, 686, 718 }, 1974 .hback_porch = { 50, 70, 255 }, 1975 .hsync_len = { 1, 1, 1 }, 1976 .vactive = { 240, 240, 240 }, 1977 .vfront_porch = { 1, 1, 179 }, 1978 .vback_porch = { 1, 21, 31 }, 1979 .vsync_len = { 1, 1, 6 }, 1980 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1981 }; 1982 1983 static const struct panel_desc giantplus_gpm940b0 = { 1984 .timings = &giantplus_gpm940b0_timing, 1985 .num_timings = 1, 1986 .bpc = 8, 1987 .size = { 1988 .width = 60, 1989 .height = 45, 1990 }, 1991 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1992 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1993 }; 1994 1995 static const struct display_timing hannstar_hsd070pww1_timing = { 1996 .pixelclock = { 64300000, 71100000, 82000000 }, 1997 .hactive = { 1280, 1280, 1280 }, 1998 .hfront_porch = { 1, 1, 10 }, 1999 .hback_porch = { 1, 1, 10 }, 2000 /* 2001 * According to the data sheet, the minimum horizontal blanking interval 2002 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2003 * minimum working horizontal blanking interval to be 60 clocks. 2004 */ 2005 .hsync_len = { 58, 158, 661 }, 2006 .vactive = { 800, 800, 800 }, 2007 .vfront_porch = { 1, 1, 10 }, 2008 .vback_porch = { 1, 1, 10 }, 2009 .vsync_len = { 1, 21, 203 }, 2010 .flags = DISPLAY_FLAGS_DE_HIGH, 2011 }; 2012 2013 static const struct panel_desc hannstar_hsd070pww1 = { 2014 .timings = &hannstar_hsd070pww1_timing, 2015 .num_timings = 1, 2016 .bpc = 6, 2017 .size = { 2018 .width = 151, 2019 .height = 94, 2020 }, 2021 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2022 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2023 }; 2024 2025 static const struct display_timing hannstar_hsd100pxn1_timing = { 2026 .pixelclock = { 55000000, 65000000, 75000000 }, 2027 .hactive = { 1024, 1024, 1024 }, 2028 .hfront_porch = { 40, 40, 40 }, 2029 .hback_porch = { 220, 220, 220 }, 2030 .hsync_len = { 20, 60, 100 }, 2031 .vactive = { 768, 768, 768 }, 2032 .vfront_porch = { 7, 7, 7 }, 2033 .vback_porch = { 21, 21, 21 }, 2034 .vsync_len = { 10, 10, 10 }, 2035 .flags = DISPLAY_FLAGS_DE_HIGH, 2036 }; 2037 2038 static const struct panel_desc hannstar_hsd100pxn1 = { 2039 .timings = &hannstar_hsd100pxn1_timing, 2040 .num_timings = 1, 2041 .bpc = 6, 2042 .size = { 2043 .width = 203, 2044 .height = 152, 2045 }, 2046 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2048 }; 2049 2050 static const struct display_timing hannstar_hsd101pww2_timing = { 2051 .pixelclock = { 64300000, 71100000, 82000000 }, 2052 .hactive = { 1280, 1280, 1280 }, 2053 .hfront_porch = { 1, 1, 10 }, 2054 .hback_porch = { 1, 1, 10 }, 2055 .hsync_len = { 58, 158, 661 }, 2056 .vactive = { 800, 800, 800 }, 2057 .vfront_porch = { 1, 1, 10 }, 2058 .vback_porch = { 1, 1, 10 }, 2059 .vsync_len = { 1, 21, 203 }, 2060 .flags = DISPLAY_FLAGS_DE_HIGH, 2061 }; 2062 2063 static const struct panel_desc hannstar_hsd101pww2 = { 2064 .timings = &hannstar_hsd101pww2_timing, 2065 .num_timings = 1, 2066 .bpc = 8, 2067 .size = { 2068 .width = 217, 2069 .height = 136, 2070 }, 2071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2072 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2073 }; 2074 2075 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2076 .clock = 33333, 2077 .hdisplay = 800, 2078 .hsync_start = 800 + 85, 2079 .hsync_end = 800 + 85 + 86, 2080 .htotal = 800 + 85 + 86 + 85, 2081 .vdisplay = 480, 2082 .vsync_start = 480 + 16, 2083 .vsync_end = 480 + 16 + 13, 2084 .vtotal = 480 + 16 + 13 + 16, 2085 }; 2086 2087 static const struct panel_desc hitachi_tx23d38vm0caa = { 2088 .modes = &hitachi_tx23d38vm0caa_mode, 2089 .num_modes = 1, 2090 .bpc = 6, 2091 .size = { 2092 .width = 195, 2093 .height = 117, 2094 }, 2095 .delay = { 2096 .enable = 160, 2097 .disable = 160, 2098 }, 2099 }; 2100 2101 static const struct drm_display_mode innolux_at043tn24_mode = { 2102 .clock = 9000, 2103 .hdisplay = 480, 2104 .hsync_start = 480 + 2, 2105 .hsync_end = 480 + 2 + 41, 2106 .htotal = 480 + 2 + 41 + 2, 2107 .vdisplay = 272, 2108 .vsync_start = 272 + 2, 2109 .vsync_end = 272 + 2 + 10, 2110 .vtotal = 272 + 2 + 10 + 2, 2111 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2112 }; 2113 2114 static const struct panel_desc innolux_at043tn24 = { 2115 .modes = &innolux_at043tn24_mode, 2116 .num_modes = 1, 2117 .bpc = 8, 2118 .size = { 2119 .width = 95, 2120 .height = 54, 2121 }, 2122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2123 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2124 }; 2125 2126 static const struct drm_display_mode innolux_at070tn92_mode = { 2127 .clock = 33333, 2128 .hdisplay = 800, 2129 .hsync_start = 800 + 210, 2130 .hsync_end = 800 + 210 + 20, 2131 .htotal = 800 + 210 + 20 + 46, 2132 .vdisplay = 480, 2133 .vsync_start = 480 + 22, 2134 .vsync_end = 480 + 22 + 10, 2135 .vtotal = 480 + 22 + 23 + 10, 2136 }; 2137 2138 static const struct panel_desc innolux_at070tn92 = { 2139 .modes = &innolux_at070tn92_mode, 2140 .num_modes = 1, 2141 .size = { 2142 .width = 154, 2143 .height = 86, 2144 }, 2145 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2146 }; 2147 2148 static const struct display_timing innolux_g070y2_l01_timing = { 2149 .pixelclock = { 28000000, 29500000, 32000000 }, 2150 .hactive = { 800, 800, 800 }, 2151 .hfront_porch = { 61, 91, 141 }, 2152 .hback_porch = { 60, 90, 140 }, 2153 .hsync_len = { 12, 12, 12 }, 2154 .vactive = { 480, 480, 480 }, 2155 .vfront_porch = { 4, 9, 30 }, 2156 .vback_porch = { 4, 8, 28 }, 2157 .vsync_len = { 2, 2, 2 }, 2158 .flags = DISPLAY_FLAGS_DE_HIGH, 2159 }; 2160 2161 static const struct panel_desc innolux_g070y2_l01 = { 2162 .timings = &innolux_g070y2_l01_timing, 2163 .num_timings = 1, 2164 .bpc = 8, 2165 .size = { 2166 .width = 152, 2167 .height = 91, 2168 }, 2169 .delay = { 2170 .prepare = 10, 2171 .enable = 100, 2172 .disable = 100, 2173 .unprepare = 800, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2176 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2177 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2178 }; 2179 2180 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2181 .clock = 33333, 2182 .hdisplay = 800, 2183 .hsync_start = 800 + 210, 2184 .hsync_end = 800 + 210 + 20, 2185 .htotal = 800 + 210 + 20 + 46, 2186 .vdisplay = 480, 2187 .vsync_start = 480 + 22, 2188 .vsync_end = 480 + 22 + 10, 2189 .vtotal = 480 + 22 + 23 + 10, 2190 }; 2191 2192 static const struct panel_desc innolux_g070y2_t02 = { 2193 .modes = &innolux_g070y2_t02_mode, 2194 .num_modes = 1, 2195 .bpc = 8, 2196 .size = { 2197 .width = 152, 2198 .height = 92, 2199 }, 2200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2201 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2202 .connector_type = DRM_MODE_CONNECTOR_DPI, 2203 }; 2204 2205 static const struct display_timing innolux_g101ice_l01_timing = { 2206 .pixelclock = { 60400000, 71100000, 74700000 }, 2207 .hactive = { 1280, 1280, 1280 }, 2208 .hfront_porch = { 41, 80, 100 }, 2209 .hback_porch = { 40, 79, 99 }, 2210 .hsync_len = { 1, 1, 1 }, 2211 .vactive = { 800, 800, 800 }, 2212 .vfront_porch = { 5, 11, 14 }, 2213 .vback_porch = { 4, 11, 14 }, 2214 .vsync_len = { 1, 1, 1 }, 2215 .flags = DISPLAY_FLAGS_DE_HIGH, 2216 }; 2217 2218 static const struct panel_desc innolux_g101ice_l01 = { 2219 .timings = &innolux_g101ice_l01_timing, 2220 .num_timings = 1, 2221 .bpc = 8, 2222 .size = { 2223 .width = 217, 2224 .height = 135, 2225 }, 2226 .delay = { 2227 .enable = 200, 2228 .disable = 200, 2229 }, 2230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2231 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2232 }; 2233 2234 static const struct display_timing innolux_g121i1_l01_timing = { 2235 .pixelclock = { 67450000, 71000000, 74550000 }, 2236 .hactive = { 1280, 1280, 1280 }, 2237 .hfront_porch = { 40, 80, 160 }, 2238 .hback_porch = { 39, 79, 159 }, 2239 .hsync_len = { 1, 1, 1 }, 2240 .vactive = { 800, 800, 800 }, 2241 .vfront_porch = { 5, 11, 100 }, 2242 .vback_porch = { 4, 11, 99 }, 2243 .vsync_len = { 1, 1, 1 }, 2244 }; 2245 2246 static const struct panel_desc innolux_g121i1_l01 = { 2247 .timings = &innolux_g121i1_l01_timing, 2248 .num_timings = 1, 2249 .bpc = 6, 2250 .size = { 2251 .width = 261, 2252 .height = 163, 2253 }, 2254 .delay = { 2255 .enable = 200, 2256 .disable = 20, 2257 }, 2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2259 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2260 }; 2261 2262 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2263 .clock = 65000, 2264 .hdisplay = 1024, 2265 .hsync_start = 1024 + 0, 2266 .hsync_end = 1024 + 1, 2267 .htotal = 1024 + 0 + 1 + 320, 2268 .vdisplay = 768, 2269 .vsync_start = 768 + 38, 2270 .vsync_end = 768 + 38 + 1, 2271 .vtotal = 768 + 38 + 1 + 0, 2272 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2273 }; 2274 2275 static const struct panel_desc innolux_g121x1_l03 = { 2276 .modes = &innolux_g121x1_l03_mode, 2277 .num_modes = 1, 2278 .bpc = 6, 2279 .size = { 2280 .width = 246, 2281 .height = 185, 2282 }, 2283 .delay = { 2284 .enable = 200, 2285 .unprepare = 200, 2286 .disable = 400, 2287 }, 2288 }; 2289 2290 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2291 .clock = 69300, 2292 .hdisplay = 1366, 2293 .hsync_start = 1366 + 16, 2294 .hsync_end = 1366 + 16 + 34, 2295 .htotal = 1366 + 16 + 34 + 50, 2296 .vdisplay = 768, 2297 .vsync_start = 768 + 2, 2298 .vsync_end = 768 + 2 + 6, 2299 .vtotal = 768 + 2 + 6 + 12, 2300 }; 2301 2302 static const struct panel_desc innolux_n156bge_l21 = { 2303 .modes = &innolux_n156bge_l21_mode, 2304 .num_modes = 1, 2305 .bpc = 6, 2306 .size = { 2307 .width = 344, 2308 .height = 193, 2309 }, 2310 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2311 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2312 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2313 }; 2314 2315 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2316 .clock = 51501, 2317 .hdisplay = 1024, 2318 .hsync_start = 1024 + 128, 2319 .hsync_end = 1024 + 128 + 64, 2320 .htotal = 1024 + 128 + 64 + 128, 2321 .vdisplay = 600, 2322 .vsync_start = 600 + 16, 2323 .vsync_end = 600 + 16 + 4, 2324 .vtotal = 600 + 16 + 4 + 16, 2325 }; 2326 2327 static const struct panel_desc innolux_zj070na_01p = { 2328 .modes = &innolux_zj070na_01p_mode, 2329 .num_modes = 1, 2330 .bpc = 6, 2331 .size = { 2332 .width = 154, 2333 .height = 90, 2334 }, 2335 }; 2336 2337 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2338 .pixelclock = { 5580000, 5850000, 6200000 }, 2339 .hactive = { 320, 320, 320 }, 2340 .hfront_porch = { 30, 30, 30 }, 2341 .hback_porch = { 30, 30, 30 }, 2342 .hsync_len = { 1, 5, 17 }, 2343 .vactive = { 240, 240, 240 }, 2344 .vfront_porch = { 6, 6, 6 }, 2345 .vback_porch = { 5, 5, 5 }, 2346 .vsync_len = { 1, 2, 11 }, 2347 .flags = DISPLAY_FLAGS_DE_HIGH, 2348 }; 2349 2350 static const struct panel_desc koe_tx14d24vm1bpa = { 2351 .timings = &koe_tx14d24vm1bpa_timing, 2352 .num_timings = 1, 2353 .bpc = 6, 2354 .size = { 2355 .width = 115, 2356 .height = 86, 2357 }, 2358 }; 2359 2360 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2361 .pixelclock = { 151820000, 156720000, 159780000 }, 2362 .hactive = { 1920, 1920, 1920 }, 2363 .hfront_porch = { 105, 130, 142 }, 2364 .hback_porch = { 45, 70, 82 }, 2365 .hsync_len = { 30, 30, 30 }, 2366 .vactive = { 1200, 1200, 1200}, 2367 .vfront_porch = { 3, 5, 10 }, 2368 .vback_porch = { 2, 5, 10 }, 2369 .vsync_len = { 5, 5, 5 }, 2370 }; 2371 2372 static const struct panel_desc koe_tx26d202vm0bwa = { 2373 .timings = &koe_tx26d202vm0bwa_timing, 2374 .num_timings = 1, 2375 .bpc = 8, 2376 .size = { 2377 .width = 217, 2378 .height = 136, 2379 }, 2380 .delay = { 2381 .prepare = 1000, 2382 .enable = 1000, 2383 .unprepare = 1000, 2384 .disable = 1000, 2385 }, 2386 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2387 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2388 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2389 }; 2390 2391 static const struct display_timing koe_tx31d200vm0baa_timing = { 2392 .pixelclock = { 39600000, 43200000, 48000000 }, 2393 .hactive = { 1280, 1280, 1280 }, 2394 .hfront_porch = { 16, 36, 56 }, 2395 .hback_porch = { 16, 36, 56 }, 2396 .hsync_len = { 8, 8, 8 }, 2397 .vactive = { 480, 480, 480 }, 2398 .vfront_porch = { 6, 21, 33 }, 2399 .vback_porch = { 6, 21, 33 }, 2400 .vsync_len = { 8, 8, 8 }, 2401 .flags = DISPLAY_FLAGS_DE_HIGH, 2402 }; 2403 2404 static const struct panel_desc koe_tx31d200vm0baa = { 2405 .timings = &koe_tx31d200vm0baa_timing, 2406 .num_timings = 1, 2407 .bpc = 6, 2408 .size = { 2409 .width = 292, 2410 .height = 109, 2411 }, 2412 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2413 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2414 }; 2415 2416 static const struct display_timing kyo_tcg121xglp_timing = { 2417 .pixelclock = { 52000000, 65000000, 71000000 }, 2418 .hactive = { 1024, 1024, 1024 }, 2419 .hfront_porch = { 2, 2, 2 }, 2420 .hback_porch = { 2, 2, 2 }, 2421 .hsync_len = { 86, 124, 244 }, 2422 .vactive = { 768, 768, 768 }, 2423 .vfront_porch = { 2, 2, 2 }, 2424 .vback_porch = { 2, 2, 2 }, 2425 .vsync_len = { 6, 34, 73 }, 2426 .flags = DISPLAY_FLAGS_DE_HIGH, 2427 }; 2428 2429 static const struct panel_desc kyo_tcg121xglp = { 2430 .timings = &kyo_tcg121xglp_timing, 2431 .num_timings = 1, 2432 .bpc = 8, 2433 .size = { 2434 .width = 246, 2435 .height = 184, 2436 }, 2437 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2438 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2439 }; 2440 2441 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2442 .clock = 7000, 2443 .hdisplay = 320, 2444 .hsync_start = 320 + 20, 2445 .hsync_end = 320 + 20 + 30, 2446 .htotal = 320 + 20 + 30 + 38, 2447 .vdisplay = 240, 2448 .vsync_start = 240 + 4, 2449 .vsync_end = 240 + 4 + 3, 2450 .vtotal = 240 + 4 + 3 + 15, 2451 }; 2452 2453 static const struct panel_desc lemaker_bl035_rgb_002 = { 2454 .modes = &lemaker_bl035_rgb_002_mode, 2455 .num_modes = 1, 2456 .size = { 2457 .width = 70, 2458 .height = 52, 2459 }, 2460 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2461 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2462 }; 2463 2464 static const struct drm_display_mode lg_lb070wv8_mode = { 2465 .clock = 33246, 2466 .hdisplay = 800, 2467 .hsync_start = 800 + 88, 2468 .hsync_end = 800 + 88 + 80, 2469 .htotal = 800 + 88 + 80 + 88, 2470 .vdisplay = 480, 2471 .vsync_start = 480 + 10, 2472 .vsync_end = 480 + 10 + 25, 2473 .vtotal = 480 + 10 + 25 + 10, 2474 }; 2475 2476 static const struct panel_desc lg_lb070wv8 = { 2477 .modes = &lg_lb070wv8_mode, 2478 .num_modes = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 151, 2482 .height = 91, 2483 }, 2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2485 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2486 }; 2487 2488 static const struct display_timing logictechno_lt161010_2nh_timing = { 2489 .pixelclock = { 26400000, 33300000, 46800000 }, 2490 .hactive = { 800, 800, 800 }, 2491 .hfront_porch = { 16, 210, 354 }, 2492 .hback_porch = { 46, 46, 46 }, 2493 .hsync_len = { 1, 20, 40 }, 2494 .vactive = { 480, 480, 480 }, 2495 .vfront_porch = { 7, 22, 147 }, 2496 .vback_porch = { 23, 23, 23 }, 2497 .vsync_len = { 1, 10, 20 }, 2498 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2499 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2500 DISPLAY_FLAGS_SYNC_POSEDGE, 2501 }; 2502 2503 static const struct panel_desc logictechno_lt161010_2nh = { 2504 .timings = &logictechno_lt161010_2nh_timing, 2505 .num_timings = 1, 2506 .size = { 2507 .width = 154, 2508 .height = 86, 2509 }, 2510 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2511 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2512 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2513 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2514 .connector_type = DRM_MODE_CONNECTOR_DPI, 2515 }; 2516 2517 static const struct display_timing logictechno_lt170410_2whc_timing = { 2518 .pixelclock = { 68900000, 71100000, 73400000 }, 2519 .hactive = { 1280, 1280, 1280 }, 2520 .hfront_porch = { 23, 60, 71 }, 2521 .hback_porch = { 23, 60, 71 }, 2522 .hsync_len = { 15, 40, 47 }, 2523 .vactive = { 800, 800, 800 }, 2524 .vfront_porch = { 5, 7, 10 }, 2525 .vback_porch = { 5, 7, 10 }, 2526 .vsync_len = { 6, 9, 12 }, 2527 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2528 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2529 DISPLAY_FLAGS_SYNC_POSEDGE, 2530 }; 2531 2532 static const struct panel_desc logictechno_lt170410_2whc = { 2533 .timings = &logictechno_lt170410_2whc_timing, 2534 .num_timings = 1, 2535 .size = { 2536 .width = 217, 2537 .height = 136, 2538 }, 2539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2540 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2541 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2542 }; 2543 2544 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2545 .clock = 33000, 2546 .hdisplay = 800, 2547 .hsync_start = 800 + 112, 2548 .hsync_end = 800 + 112 + 3, 2549 .htotal = 800 + 112 + 3 + 85, 2550 .vdisplay = 480, 2551 .vsync_start = 480 + 38, 2552 .vsync_end = 480 + 38 + 3, 2553 .vtotal = 480 + 38 + 3 + 29, 2554 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2555 }; 2556 2557 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2558 .modes = &logictechno_lttd800480070_l2rt_mode, 2559 .num_modes = 1, 2560 .bpc = 8, 2561 .size = { 2562 .width = 154, 2563 .height = 86, 2564 }, 2565 .delay = { 2566 .prepare = 45, 2567 .enable = 100, 2568 .disable = 100, 2569 .unprepare = 45 2570 }, 2571 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2572 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2573 .connector_type = DRM_MODE_CONNECTOR_DPI, 2574 }; 2575 2576 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2577 .clock = 33000, 2578 .hdisplay = 800, 2579 .hsync_start = 800 + 154, 2580 .hsync_end = 800 + 154 + 3, 2581 .htotal = 800 + 154 + 3 + 43, 2582 .vdisplay = 480, 2583 .vsync_start = 480 + 47, 2584 .vsync_end = 480 + 47 + 3, 2585 .vtotal = 480 + 47 + 3 + 20, 2586 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2587 }; 2588 2589 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2590 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2591 .num_modes = 1, 2592 .bpc = 8, 2593 .size = { 2594 .width = 154, 2595 .height = 86, 2596 }, 2597 .delay = { 2598 .prepare = 45, 2599 .enable = 100, 2600 .disable = 100, 2601 .unprepare = 45 2602 }, 2603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2604 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2605 .connector_type = DRM_MODE_CONNECTOR_DPI, 2606 }; 2607 2608 static const struct drm_display_mode logicpd_type_28_mode = { 2609 .clock = 9107, 2610 .hdisplay = 480, 2611 .hsync_start = 480 + 3, 2612 .hsync_end = 480 + 3 + 42, 2613 .htotal = 480 + 3 + 42 + 2, 2614 2615 .vdisplay = 272, 2616 .vsync_start = 272 + 2, 2617 .vsync_end = 272 + 2 + 11, 2618 .vtotal = 272 + 2 + 11 + 3, 2619 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2620 }; 2621 2622 static const struct panel_desc logicpd_type_28 = { 2623 .modes = &logicpd_type_28_mode, 2624 .num_modes = 1, 2625 .bpc = 8, 2626 .size = { 2627 .width = 105, 2628 .height = 67, 2629 }, 2630 .delay = { 2631 .prepare = 200, 2632 .enable = 200, 2633 .unprepare = 200, 2634 .disable = 200, 2635 }, 2636 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2637 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2638 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2639 .connector_type = DRM_MODE_CONNECTOR_DPI, 2640 }; 2641 2642 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2643 .clock = 30400, 2644 .hdisplay = 800, 2645 .hsync_start = 800 + 0, 2646 .hsync_end = 800 + 1, 2647 .htotal = 800 + 0 + 1 + 160, 2648 .vdisplay = 480, 2649 .vsync_start = 480 + 0, 2650 .vsync_end = 480 + 48 + 1, 2651 .vtotal = 480 + 48 + 1 + 0, 2652 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2653 }; 2654 2655 static const struct panel_desc mitsubishi_aa070mc01 = { 2656 .modes = &mitsubishi_aa070mc01_mode, 2657 .num_modes = 1, 2658 .bpc = 8, 2659 .size = { 2660 .width = 152, 2661 .height = 91, 2662 }, 2663 2664 .delay = { 2665 .enable = 200, 2666 .unprepare = 200, 2667 .disable = 400, 2668 }, 2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2670 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 }; 2673 2674 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2675 .pixelclock = { 29000000, 33000000, 38000000 }, 2676 .hactive = { 800, 800, 800 }, 2677 .hfront_porch = { 180, 210, 240 }, 2678 .hback_porch = { 16, 16, 16 }, 2679 .hsync_len = { 30, 30, 30 }, 2680 .vactive = { 480, 480, 480 }, 2681 .vfront_porch = { 12, 22, 32 }, 2682 .vback_porch = { 10, 10, 10 }, 2683 .vsync_len = { 13, 13, 13 }, 2684 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2685 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2686 DISPLAY_FLAGS_SYNC_POSEDGE, 2687 }; 2688 2689 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2690 .timings = &multi_inno_mi0700s4t_6_timing, 2691 .num_timings = 1, 2692 .bpc = 8, 2693 .size = { 2694 .width = 154, 2695 .height = 86, 2696 }, 2697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2699 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2700 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2701 .connector_type = DRM_MODE_CONNECTOR_DPI, 2702 }; 2703 2704 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2705 .pixelclock = { 68900000, 70000000, 73400000 }, 2706 .hactive = { 1280, 1280, 1280 }, 2707 .hfront_porch = { 30, 60, 71 }, 2708 .hback_porch = { 30, 60, 71 }, 2709 .hsync_len = { 10, 10, 48 }, 2710 .vactive = { 800, 800, 800 }, 2711 .vfront_porch = { 5, 10, 10 }, 2712 .vback_porch = { 5, 10, 10 }, 2713 .vsync_len = { 5, 6, 13 }, 2714 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2715 DISPLAY_FLAGS_DE_HIGH, 2716 }; 2717 2718 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2719 .timings = &multi_inno_mi1010ait_1cp_timing, 2720 .num_timings = 1, 2721 .bpc = 8, 2722 .size = { 2723 .width = 217, 2724 .height = 136, 2725 }, 2726 .delay = { 2727 .enable = 50, 2728 .disable = 50, 2729 }, 2730 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2731 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2733 }; 2734 2735 static const struct display_timing nec_nl12880bc20_05_timing = { 2736 .pixelclock = { 67000000, 71000000, 75000000 }, 2737 .hactive = { 1280, 1280, 1280 }, 2738 .hfront_porch = { 2, 30, 30 }, 2739 .hback_porch = { 6, 100, 100 }, 2740 .hsync_len = { 2, 30, 30 }, 2741 .vactive = { 800, 800, 800 }, 2742 .vfront_porch = { 5, 5, 5 }, 2743 .vback_porch = { 11, 11, 11 }, 2744 .vsync_len = { 7, 7, 7 }, 2745 }; 2746 2747 static const struct panel_desc nec_nl12880bc20_05 = { 2748 .timings = &nec_nl12880bc20_05_timing, 2749 .num_timings = 1, 2750 .bpc = 8, 2751 .size = { 2752 .width = 261, 2753 .height = 163, 2754 }, 2755 .delay = { 2756 .enable = 50, 2757 .disable = 50, 2758 }, 2759 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2760 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2761 }; 2762 2763 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2764 .clock = 10870, 2765 .hdisplay = 480, 2766 .hsync_start = 480 + 2, 2767 .hsync_end = 480 + 2 + 41, 2768 .htotal = 480 + 2 + 41 + 2, 2769 .vdisplay = 272, 2770 .vsync_start = 272 + 2, 2771 .vsync_end = 272 + 2 + 4, 2772 .vtotal = 272 + 2 + 4 + 2, 2773 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2774 }; 2775 2776 static const struct panel_desc nec_nl4827hc19_05b = { 2777 .modes = &nec_nl4827hc19_05b_mode, 2778 .num_modes = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 95, 2782 .height = 54, 2783 }, 2784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2785 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2786 }; 2787 2788 static const struct drm_display_mode netron_dy_e231732_mode = { 2789 .clock = 66000, 2790 .hdisplay = 1024, 2791 .hsync_start = 1024 + 160, 2792 .hsync_end = 1024 + 160 + 70, 2793 .htotal = 1024 + 160 + 70 + 90, 2794 .vdisplay = 600, 2795 .vsync_start = 600 + 127, 2796 .vsync_end = 600 + 127 + 20, 2797 .vtotal = 600 + 127 + 20 + 3, 2798 }; 2799 2800 static const struct panel_desc netron_dy_e231732 = { 2801 .modes = &netron_dy_e231732_mode, 2802 .num_modes = 1, 2803 .size = { 2804 .width = 154, 2805 .height = 87, 2806 }, 2807 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2808 }; 2809 2810 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2811 .clock = 9000, 2812 .hdisplay = 480, 2813 .hsync_start = 480 + 2, 2814 .hsync_end = 480 + 2 + 41, 2815 .htotal = 480 + 2 + 41 + 2, 2816 .vdisplay = 272, 2817 .vsync_start = 272 + 2, 2818 .vsync_end = 272 + 2 + 10, 2819 .vtotal = 272 + 2 + 10 + 2, 2820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2821 }; 2822 2823 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2824 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2825 .num_modes = 1, 2826 .bpc = 8, 2827 .size = { 2828 .width = 95, 2829 .height = 54, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2833 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2834 .connector_type = DRM_MODE_CONNECTOR_DPI, 2835 }; 2836 2837 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2838 .pixelclock = { 130000000, 148350000, 163000000 }, 2839 .hactive = { 1920, 1920, 1920 }, 2840 .hfront_porch = { 80, 100, 100 }, 2841 .hback_porch = { 100, 120, 120 }, 2842 .hsync_len = { 50, 60, 60 }, 2843 .vactive = { 1080, 1080, 1080 }, 2844 .vfront_porch = { 12, 30, 30 }, 2845 .vback_porch = { 4, 10, 10 }, 2846 .vsync_len = { 4, 5, 5 }, 2847 }; 2848 2849 static const struct panel_desc nlt_nl192108ac18_02d = { 2850 .timings = &nlt_nl192108ac18_02d_timing, 2851 .num_timings = 1, 2852 .bpc = 8, 2853 .size = { 2854 .width = 344, 2855 .height = 194, 2856 }, 2857 .delay = { 2858 .unprepare = 500, 2859 }, 2860 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2861 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2862 }; 2863 2864 static const struct drm_display_mode nvd_9128_mode = { 2865 .clock = 29500, 2866 .hdisplay = 800, 2867 .hsync_start = 800 + 130, 2868 .hsync_end = 800 + 130 + 98, 2869 .htotal = 800 + 0 + 130 + 98, 2870 .vdisplay = 480, 2871 .vsync_start = 480 + 10, 2872 .vsync_end = 480 + 10 + 50, 2873 .vtotal = 480 + 0 + 10 + 50, 2874 }; 2875 2876 static const struct panel_desc nvd_9128 = { 2877 .modes = &nvd_9128_mode, 2878 .num_modes = 1, 2879 .bpc = 8, 2880 .size = { 2881 .width = 156, 2882 .height = 88, 2883 }, 2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2886 }; 2887 2888 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2889 .pixelclock = { 30000000, 30000000, 40000000 }, 2890 .hactive = { 800, 800, 800 }, 2891 .hfront_porch = { 40, 40, 40 }, 2892 .hback_porch = { 40, 40, 40 }, 2893 .hsync_len = { 1, 48, 48 }, 2894 .vactive = { 480, 480, 480 }, 2895 .vfront_porch = { 13, 13, 13 }, 2896 .vback_porch = { 29, 29, 29 }, 2897 .vsync_len = { 3, 3, 3 }, 2898 .flags = DISPLAY_FLAGS_DE_HIGH, 2899 }; 2900 2901 static const struct panel_desc okaya_rs800480t_7x0gp = { 2902 .timings = &okaya_rs800480t_7x0gp_timing, 2903 .num_timings = 1, 2904 .bpc = 6, 2905 .size = { 2906 .width = 154, 2907 .height = 87, 2908 }, 2909 .delay = { 2910 .prepare = 41, 2911 .enable = 50, 2912 .unprepare = 41, 2913 .disable = 50, 2914 }, 2915 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2916 }; 2917 2918 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2919 .clock = 9000, 2920 .hdisplay = 480, 2921 .hsync_start = 480 + 5, 2922 .hsync_end = 480 + 5 + 30, 2923 .htotal = 480 + 5 + 30 + 10, 2924 .vdisplay = 272, 2925 .vsync_start = 272 + 8, 2926 .vsync_end = 272 + 8 + 5, 2927 .vtotal = 272 + 8 + 5 + 3, 2928 }; 2929 2930 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2931 .modes = &olimex_lcd_olinuxino_43ts_mode, 2932 .num_modes = 1, 2933 .size = { 2934 .width = 95, 2935 .height = 54, 2936 }, 2937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2938 }; 2939 2940 /* 2941 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2942 * pixel clocks, but this is the timing that was being used in the Adafruit 2943 * installation instructions. 2944 */ 2945 static const struct drm_display_mode ontat_yx700wv03_mode = { 2946 .clock = 29500, 2947 .hdisplay = 800, 2948 .hsync_start = 824, 2949 .hsync_end = 896, 2950 .htotal = 992, 2951 .vdisplay = 480, 2952 .vsync_start = 483, 2953 .vsync_end = 493, 2954 .vtotal = 500, 2955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2956 }; 2957 2958 /* 2959 * Specification at: 2960 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2961 */ 2962 static const struct panel_desc ontat_yx700wv03 = { 2963 .modes = &ontat_yx700wv03_mode, 2964 .num_modes = 1, 2965 .bpc = 8, 2966 .size = { 2967 .width = 154, 2968 .height = 83, 2969 }, 2970 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2971 }; 2972 2973 static const struct drm_display_mode ortustech_com37h3m_mode = { 2974 .clock = 22230, 2975 .hdisplay = 480, 2976 .hsync_start = 480 + 40, 2977 .hsync_end = 480 + 40 + 10, 2978 .htotal = 480 + 40 + 10 + 40, 2979 .vdisplay = 640, 2980 .vsync_start = 640 + 4, 2981 .vsync_end = 640 + 4 + 2, 2982 .vtotal = 640 + 4 + 2 + 4, 2983 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2984 }; 2985 2986 static const struct panel_desc ortustech_com37h3m = { 2987 .modes = &ortustech_com37h3m_mode, 2988 .num_modes = 1, 2989 .bpc = 8, 2990 .size = { 2991 .width = 56, /* 56.16mm */ 2992 .height = 75, /* 74.88mm */ 2993 }, 2994 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2995 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2996 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2997 }; 2998 2999 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3000 .clock = 25000, 3001 .hdisplay = 480, 3002 .hsync_start = 480 + 10, 3003 .hsync_end = 480 + 10 + 10, 3004 .htotal = 480 + 10 + 10 + 15, 3005 .vdisplay = 800, 3006 .vsync_start = 800 + 3, 3007 .vsync_end = 800 + 3 + 3, 3008 .vtotal = 800 + 3 + 3 + 3, 3009 }; 3010 3011 static const struct panel_desc ortustech_com43h4m85ulc = { 3012 .modes = &ortustech_com43h4m85ulc_mode, 3013 .num_modes = 1, 3014 .bpc = 6, 3015 .size = { 3016 .width = 56, 3017 .height = 93, 3018 }, 3019 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3021 .connector_type = DRM_MODE_CONNECTOR_DPI, 3022 }; 3023 3024 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3025 .clock = 33000, 3026 .hdisplay = 800, 3027 .hsync_start = 800 + 210, 3028 .hsync_end = 800 + 210 + 30, 3029 .htotal = 800 + 210 + 30 + 16, 3030 .vdisplay = 480, 3031 .vsync_start = 480 + 22, 3032 .vsync_end = 480 + 22 + 13, 3033 .vtotal = 480 + 22 + 13 + 10, 3034 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3035 }; 3036 3037 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3038 .modes = &osddisplays_osd070t1718_19ts_mode, 3039 .num_modes = 1, 3040 .bpc = 8, 3041 .size = { 3042 .width = 152, 3043 .height = 91, 3044 }, 3045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3047 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3048 .connector_type = DRM_MODE_CONNECTOR_DPI, 3049 }; 3050 3051 static const struct drm_display_mode pda_91_00156_a0_mode = { 3052 .clock = 33300, 3053 .hdisplay = 800, 3054 .hsync_start = 800 + 1, 3055 .hsync_end = 800 + 1 + 64, 3056 .htotal = 800 + 1 + 64 + 64, 3057 .vdisplay = 480, 3058 .vsync_start = 480 + 1, 3059 .vsync_end = 480 + 1 + 23, 3060 .vtotal = 480 + 1 + 23 + 22, 3061 }; 3062 3063 static const struct panel_desc pda_91_00156_a0 = { 3064 .modes = &pda_91_00156_a0_mode, 3065 .num_modes = 1, 3066 .size = { 3067 .width = 152, 3068 .height = 91, 3069 }, 3070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3071 }; 3072 3073 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3074 .clock = 24750, 3075 .hdisplay = 800, 3076 .hsync_start = 800 + 54, 3077 .hsync_end = 800 + 54 + 2, 3078 .htotal = 800 + 54 + 2 + 44, 3079 .vdisplay = 480, 3080 .vsync_start = 480 + 49, 3081 .vsync_end = 480 + 49 + 2, 3082 .vtotal = 480 + 49 + 2 + 22, 3083 }; 3084 3085 static const struct panel_desc powertip_ph800480t013_idf02 = { 3086 .modes = &powertip_ph800480t013_idf02_mode, 3087 .num_modes = 1, 3088 .size = { 3089 .width = 152, 3090 .height = 91, 3091 }, 3092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3093 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3094 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3096 .connector_type = DRM_MODE_CONNECTOR_DPI, 3097 }; 3098 3099 static const struct drm_display_mode qd43003c0_40_mode = { 3100 .clock = 9000, 3101 .hdisplay = 480, 3102 .hsync_start = 480 + 8, 3103 .hsync_end = 480 + 8 + 4, 3104 .htotal = 480 + 8 + 4 + 39, 3105 .vdisplay = 272, 3106 .vsync_start = 272 + 4, 3107 .vsync_end = 272 + 4 + 10, 3108 .vtotal = 272 + 4 + 10 + 2, 3109 }; 3110 3111 static const struct panel_desc qd43003c0_40 = { 3112 .modes = &qd43003c0_40_mode, 3113 .num_modes = 1, 3114 .bpc = 8, 3115 .size = { 3116 .width = 95, 3117 .height = 53, 3118 }, 3119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3120 }; 3121 3122 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3123 { /* 60 Hz */ 3124 .clock = 10800, 3125 .hdisplay = 480, 3126 .hsync_start = 480 + 77, 3127 .hsync_end = 480 + 77 + 41, 3128 .htotal = 480 + 77 + 41 + 2, 3129 .vdisplay = 272, 3130 .vsync_start = 272 + 16, 3131 .vsync_end = 272 + 16 + 10, 3132 .vtotal = 272 + 16 + 10 + 2, 3133 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3134 }, 3135 { /* 50 Hz */ 3136 .clock = 10800, 3137 .hdisplay = 480, 3138 .hsync_start = 480 + 17, 3139 .hsync_end = 480 + 17 + 41, 3140 .htotal = 480 + 17 + 41 + 2, 3141 .vdisplay = 272, 3142 .vsync_start = 272 + 116, 3143 .vsync_end = 272 + 116 + 10, 3144 .vtotal = 272 + 116 + 10 + 2, 3145 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3146 }, 3147 }; 3148 3149 static const struct panel_desc qishenglong_gopher2b_lcd = { 3150 .modes = qishenglong_gopher2b_lcd_modes, 3151 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3152 .bpc = 8, 3153 .size = { 3154 .width = 95, 3155 .height = 54, 3156 }, 3157 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3158 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3159 .connector_type = DRM_MODE_CONNECTOR_DPI, 3160 }; 3161 3162 static const struct display_timing rocktech_rk070er9427_timing = { 3163 .pixelclock = { 26400000, 33300000, 46800000 }, 3164 .hactive = { 800, 800, 800 }, 3165 .hfront_porch = { 16, 210, 354 }, 3166 .hback_porch = { 46, 46, 46 }, 3167 .hsync_len = { 1, 1, 1 }, 3168 .vactive = { 480, 480, 480 }, 3169 .vfront_porch = { 7, 22, 147 }, 3170 .vback_porch = { 23, 23, 23 }, 3171 .vsync_len = { 1, 1, 1 }, 3172 .flags = DISPLAY_FLAGS_DE_HIGH, 3173 }; 3174 3175 static const struct panel_desc rocktech_rk070er9427 = { 3176 .timings = &rocktech_rk070er9427_timing, 3177 .num_timings = 1, 3178 .bpc = 6, 3179 .size = { 3180 .width = 154, 3181 .height = 86, 3182 }, 3183 .delay = { 3184 .prepare = 41, 3185 .enable = 50, 3186 .unprepare = 41, 3187 .disable = 50, 3188 }, 3189 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3190 }; 3191 3192 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3193 .clock = 71100, 3194 .hdisplay = 1280, 3195 .hsync_start = 1280 + 48, 3196 .hsync_end = 1280 + 48 + 32, 3197 .htotal = 1280 + 48 + 32 + 80, 3198 .vdisplay = 800, 3199 .vsync_start = 800 + 2, 3200 .vsync_end = 800 + 2 + 5, 3201 .vtotal = 800 + 2 + 5 + 16, 3202 }; 3203 3204 static const struct panel_desc rocktech_rk101ii01d_ct = { 3205 .modes = &rocktech_rk101ii01d_ct_mode, 3206 .bpc = 8, 3207 .num_modes = 1, 3208 .size = { 3209 .width = 217, 3210 .height = 136, 3211 }, 3212 .delay = { 3213 .prepare = 50, 3214 .disable = 50, 3215 }, 3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3219 }; 3220 3221 static const struct display_timing samsung_ltl101al01_timing = { 3222 .pixelclock = { 66663000, 66663000, 66663000 }, 3223 .hactive = { 1280, 1280, 1280 }, 3224 .hfront_porch = { 18, 18, 18 }, 3225 .hback_porch = { 36, 36, 36 }, 3226 .hsync_len = { 16, 16, 16 }, 3227 .vactive = { 800, 800, 800 }, 3228 .vfront_porch = { 4, 4, 4 }, 3229 .vback_porch = { 16, 16, 16 }, 3230 .vsync_len = { 3, 3, 3 }, 3231 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3232 }; 3233 3234 static const struct panel_desc samsung_ltl101al01 = { 3235 .timings = &samsung_ltl101al01_timing, 3236 .num_timings = 1, 3237 .bpc = 8, 3238 .size = { 3239 .width = 217, 3240 .height = 135, 3241 }, 3242 .delay = { 3243 .prepare = 40, 3244 .enable = 300, 3245 .disable = 200, 3246 .unprepare = 600, 3247 }, 3248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3249 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3250 }; 3251 3252 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3253 .clock = 54030, 3254 .hdisplay = 1024, 3255 .hsync_start = 1024 + 24, 3256 .hsync_end = 1024 + 24 + 136, 3257 .htotal = 1024 + 24 + 136 + 160, 3258 .vdisplay = 600, 3259 .vsync_start = 600 + 3, 3260 .vsync_end = 600 + 3 + 6, 3261 .vtotal = 600 + 3 + 6 + 61, 3262 }; 3263 3264 static const struct panel_desc samsung_ltn101nt05 = { 3265 .modes = &samsung_ltn101nt05_mode, 3266 .num_modes = 1, 3267 .bpc = 6, 3268 .size = { 3269 .width = 223, 3270 .height = 125, 3271 }, 3272 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3273 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3275 }; 3276 3277 static const struct display_timing satoz_sat050at40h12r2_timing = { 3278 .pixelclock = {33300000, 33300000, 50000000}, 3279 .hactive = {800, 800, 800}, 3280 .hfront_porch = {16, 210, 354}, 3281 .hback_porch = {46, 46, 46}, 3282 .hsync_len = {1, 1, 40}, 3283 .vactive = {480, 480, 480}, 3284 .vfront_porch = {7, 22, 147}, 3285 .vback_porch = {23, 23, 23}, 3286 .vsync_len = {1, 1, 20}, 3287 }; 3288 3289 static const struct panel_desc satoz_sat050at40h12r2 = { 3290 .timings = &satoz_sat050at40h12r2_timing, 3291 .num_timings = 1, 3292 .bpc = 8, 3293 .size = { 3294 .width = 108, 3295 .height = 65, 3296 }, 3297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3299 }; 3300 3301 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3302 .clock = 33260, 3303 .hdisplay = 800, 3304 .hsync_start = 800 + 64, 3305 .hsync_end = 800 + 64 + 128, 3306 .htotal = 800 + 64 + 128 + 64, 3307 .vdisplay = 480, 3308 .vsync_start = 480 + 8, 3309 .vsync_end = 480 + 8 + 2, 3310 .vtotal = 480 + 8 + 2 + 35, 3311 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3312 }; 3313 3314 static const struct panel_desc sharp_lq070y3dg3b = { 3315 .modes = &sharp_lq070y3dg3b_mode, 3316 .num_modes = 1, 3317 .bpc = 8, 3318 .size = { 3319 .width = 152, /* 152.4mm */ 3320 .height = 91, /* 91.4mm */ 3321 }, 3322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3323 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3324 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3325 }; 3326 3327 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3328 .clock = 5500, 3329 .hdisplay = 240, 3330 .hsync_start = 240 + 16, 3331 .hsync_end = 240 + 16 + 7, 3332 .htotal = 240 + 16 + 7 + 5, 3333 .vdisplay = 320, 3334 .vsync_start = 320 + 9, 3335 .vsync_end = 320 + 9 + 1, 3336 .vtotal = 320 + 9 + 1 + 7, 3337 }; 3338 3339 static const struct panel_desc sharp_lq035q7db03 = { 3340 .modes = &sharp_lq035q7db03_mode, 3341 .num_modes = 1, 3342 .bpc = 6, 3343 .size = { 3344 .width = 54, 3345 .height = 72, 3346 }, 3347 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3348 }; 3349 3350 static const struct display_timing sharp_lq101k1ly04_timing = { 3351 .pixelclock = { 60000000, 65000000, 80000000 }, 3352 .hactive = { 1280, 1280, 1280 }, 3353 .hfront_porch = { 20, 20, 20 }, 3354 .hback_porch = { 20, 20, 20 }, 3355 .hsync_len = { 10, 10, 10 }, 3356 .vactive = { 800, 800, 800 }, 3357 .vfront_porch = { 4, 4, 4 }, 3358 .vback_porch = { 4, 4, 4 }, 3359 .vsync_len = { 4, 4, 4 }, 3360 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3361 }; 3362 3363 static const struct panel_desc sharp_lq101k1ly04 = { 3364 .timings = &sharp_lq101k1ly04_timing, 3365 .num_timings = 1, 3366 .bpc = 8, 3367 .size = { 3368 .width = 217, 3369 .height = 136, 3370 }, 3371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3372 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3373 }; 3374 3375 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3376 { /* 50 Hz */ 3377 .clock = 3000, 3378 .hdisplay = 240, 3379 .hsync_start = 240 + 58, 3380 .hsync_end = 240 + 58 + 1, 3381 .htotal = 240 + 58 + 1 + 1, 3382 .vdisplay = 160, 3383 .vsync_start = 160 + 24, 3384 .vsync_end = 160 + 24 + 10, 3385 .vtotal = 160 + 24 + 10 + 6, 3386 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3387 }, 3388 { /* 60 Hz */ 3389 .clock = 3000, 3390 .hdisplay = 240, 3391 .hsync_start = 240 + 8, 3392 .hsync_end = 240 + 8 + 1, 3393 .htotal = 240 + 8 + 1 + 1, 3394 .vdisplay = 160, 3395 .vsync_start = 160 + 24, 3396 .vsync_end = 160 + 24 + 10, 3397 .vtotal = 160 + 24 + 10 + 6, 3398 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3399 }, 3400 }; 3401 3402 static const struct panel_desc sharp_ls020b1dd01d = { 3403 .modes = sharp_ls020b1dd01d_modes, 3404 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3405 .bpc = 6, 3406 .size = { 3407 .width = 42, 3408 .height = 28, 3409 }, 3410 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3411 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3412 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3413 | DRM_BUS_FLAG_SHARP_SIGNALS, 3414 }; 3415 3416 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3417 .clock = 33300, 3418 .hdisplay = 800, 3419 .hsync_start = 800 + 1, 3420 .hsync_end = 800 + 1 + 64, 3421 .htotal = 800 + 1 + 64 + 64, 3422 .vdisplay = 480, 3423 .vsync_start = 480 + 1, 3424 .vsync_end = 480 + 1 + 23, 3425 .vtotal = 480 + 1 + 23 + 22, 3426 }; 3427 3428 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3429 .modes = &shelly_sca07010_bfn_lnn_mode, 3430 .num_modes = 1, 3431 .size = { 3432 .width = 152, 3433 .height = 91, 3434 }, 3435 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3436 }; 3437 3438 static const struct drm_display_mode starry_kr070pe2t_mode = { 3439 .clock = 33000, 3440 .hdisplay = 800, 3441 .hsync_start = 800 + 209, 3442 .hsync_end = 800 + 209 + 1, 3443 .htotal = 800 + 209 + 1 + 45, 3444 .vdisplay = 480, 3445 .vsync_start = 480 + 22, 3446 .vsync_end = 480 + 22 + 1, 3447 .vtotal = 480 + 22 + 1 + 22, 3448 }; 3449 3450 static const struct panel_desc starry_kr070pe2t = { 3451 .modes = &starry_kr070pe2t_mode, 3452 .num_modes = 1, 3453 .bpc = 8, 3454 .size = { 3455 .width = 152, 3456 .height = 86, 3457 }, 3458 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3459 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3460 .connector_type = DRM_MODE_CONNECTOR_DPI, 3461 }; 3462 3463 static const struct display_timing startek_kd070wvfpa_mode = { 3464 .pixelclock = { 25200000, 27200000, 30500000 }, 3465 .hactive = { 800, 800, 800 }, 3466 .hfront_porch = { 19, 44, 115 }, 3467 .hback_porch = { 5, 16, 101 }, 3468 .hsync_len = { 1, 2, 100 }, 3469 .vactive = { 480, 480, 480 }, 3470 .vfront_porch = { 5, 43, 67 }, 3471 .vback_porch = { 5, 5, 67 }, 3472 .vsync_len = { 1, 2, 66 }, 3473 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3474 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3475 DISPLAY_FLAGS_SYNC_POSEDGE, 3476 }; 3477 3478 static const struct panel_desc startek_kd070wvfpa = { 3479 .timings = &startek_kd070wvfpa_mode, 3480 .num_timings = 1, 3481 .bpc = 8, 3482 .size = { 3483 .width = 152, 3484 .height = 91, 3485 }, 3486 .delay = { 3487 .prepare = 20, 3488 .enable = 200, 3489 .disable = 200, 3490 }, 3491 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3492 .connector_type = DRM_MODE_CONNECTOR_DPI, 3493 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3494 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3495 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3496 }; 3497 3498 static const struct display_timing tsd_tst043015cmhx_timing = { 3499 .pixelclock = { 5000000, 9000000, 12000000 }, 3500 .hactive = { 480, 480, 480 }, 3501 .hfront_porch = { 4, 5, 65 }, 3502 .hback_porch = { 36, 40, 255 }, 3503 .hsync_len = { 1, 1, 1 }, 3504 .vactive = { 272, 272, 272 }, 3505 .vfront_porch = { 2, 8, 97 }, 3506 .vback_porch = { 3, 8, 31 }, 3507 .vsync_len = { 1, 1, 1 }, 3508 3509 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3510 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3511 }; 3512 3513 static const struct panel_desc tsd_tst043015cmhx = { 3514 .timings = &tsd_tst043015cmhx_timing, 3515 .num_timings = 1, 3516 .bpc = 8, 3517 .size = { 3518 .width = 105, 3519 .height = 67, 3520 }, 3521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3522 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3523 }; 3524 3525 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3526 .clock = 30000, 3527 .hdisplay = 800, 3528 .hsync_start = 800 + 39, 3529 .hsync_end = 800 + 39 + 47, 3530 .htotal = 800 + 39 + 47 + 39, 3531 .vdisplay = 480, 3532 .vsync_start = 480 + 13, 3533 .vsync_end = 480 + 13 + 2, 3534 .vtotal = 480 + 13 + 2 + 29, 3535 }; 3536 3537 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3538 .modes = &tfc_s9700rtwv43tr_01b_mode, 3539 .num_modes = 1, 3540 .bpc = 8, 3541 .size = { 3542 .width = 155, 3543 .height = 90, 3544 }, 3545 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3546 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3547 }; 3548 3549 static const struct display_timing tianma_tm070jdhg30_timing = { 3550 .pixelclock = { 62600000, 68200000, 78100000 }, 3551 .hactive = { 1280, 1280, 1280 }, 3552 .hfront_porch = { 15, 64, 159 }, 3553 .hback_porch = { 5, 5, 5 }, 3554 .hsync_len = { 1, 1, 256 }, 3555 .vactive = { 800, 800, 800 }, 3556 .vfront_porch = { 3, 40, 99 }, 3557 .vback_porch = { 2, 2, 2 }, 3558 .vsync_len = { 1, 1, 128 }, 3559 .flags = DISPLAY_FLAGS_DE_HIGH, 3560 }; 3561 3562 static const struct panel_desc tianma_tm070jdhg30 = { 3563 .timings = &tianma_tm070jdhg30_timing, 3564 .num_timings = 1, 3565 .bpc = 8, 3566 .size = { 3567 .width = 151, 3568 .height = 95, 3569 }, 3570 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3571 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3572 }; 3573 3574 static const struct panel_desc tianma_tm070jvhg33 = { 3575 .timings = &tianma_tm070jdhg30_timing, 3576 .num_timings = 1, 3577 .bpc = 8, 3578 .size = { 3579 .width = 150, 3580 .height = 94, 3581 }, 3582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3583 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3584 }; 3585 3586 static const struct display_timing tianma_tm070rvhg71_timing = { 3587 .pixelclock = { 27700000, 29200000, 39600000 }, 3588 .hactive = { 800, 800, 800 }, 3589 .hfront_porch = { 12, 40, 212 }, 3590 .hback_porch = { 88, 88, 88 }, 3591 .hsync_len = { 1, 1, 40 }, 3592 .vactive = { 480, 480, 480 }, 3593 .vfront_porch = { 1, 13, 88 }, 3594 .vback_porch = { 32, 32, 32 }, 3595 .vsync_len = { 1, 1, 3 }, 3596 .flags = DISPLAY_FLAGS_DE_HIGH, 3597 }; 3598 3599 static const struct panel_desc tianma_tm070rvhg71 = { 3600 .timings = &tianma_tm070rvhg71_timing, 3601 .num_timings = 1, 3602 .bpc = 8, 3603 .size = { 3604 .width = 154, 3605 .height = 86, 3606 }, 3607 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3608 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3609 }; 3610 3611 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3612 { 3613 .clock = 10000, 3614 .hdisplay = 320, 3615 .hsync_start = 320 + 50, 3616 .hsync_end = 320 + 50 + 6, 3617 .htotal = 320 + 50 + 6 + 38, 3618 .vdisplay = 240, 3619 .vsync_start = 240 + 3, 3620 .vsync_end = 240 + 3 + 1, 3621 .vtotal = 240 + 3 + 1 + 17, 3622 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3623 }, 3624 }; 3625 3626 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3627 .modes = ti_nspire_cx_lcd_mode, 3628 .num_modes = 1, 3629 .bpc = 8, 3630 .size = { 3631 .width = 65, 3632 .height = 49, 3633 }, 3634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3635 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3636 }; 3637 3638 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3639 { 3640 .clock = 10000, 3641 .hdisplay = 320, 3642 .hsync_start = 320 + 6, 3643 .hsync_end = 320 + 6 + 6, 3644 .htotal = 320 + 6 + 6 + 6, 3645 .vdisplay = 240, 3646 .vsync_start = 240 + 0, 3647 .vsync_end = 240 + 0 + 1, 3648 .vtotal = 240 + 0 + 1 + 0, 3649 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3650 }, 3651 }; 3652 3653 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3654 .modes = ti_nspire_classic_lcd_mode, 3655 .num_modes = 1, 3656 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3657 .bpc = 8, 3658 .size = { 3659 .width = 71, 3660 .height = 53, 3661 }, 3662 /* This is the grayscale bus format */ 3663 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3664 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3665 }; 3666 3667 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3668 .clock = 79500, 3669 .hdisplay = 1280, 3670 .hsync_start = 1280 + 192, 3671 .hsync_end = 1280 + 192 + 128, 3672 .htotal = 1280 + 192 + 128 + 64, 3673 .vdisplay = 768, 3674 .vsync_start = 768 + 20, 3675 .vsync_end = 768 + 20 + 7, 3676 .vtotal = 768 + 20 + 7 + 3, 3677 }; 3678 3679 static const struct panel_desc toshiba_lt089ac29000 = { 3680 .modes = &toshiba_lt089ac29000_mode, 3681 .num_modes = 1, 3682 .size = { 3683 .width = 194, 3684 .height = 116, 3685 }, 3686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3687 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3688 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3689 }; 3690 3691 static const struct drm_display_mode tpk_f07a_0102_mode = { 3692 .clock = 33260, 3693 .hdisplay = 800, 3694 .hsync_start = 800 + 40, 3695 .hsync_end = 800 + 40 + 128, 3696 .htotal = 800 + 40 + 128 + 88, 3697 .vdisplay = 480, 3698 .vsync_start = 480 + 10, 3699 .vsync_end = 480 + 10 + 2, 3700 .vtotal = 480 + 10 + 2 + 33, 3701 }; 3702 3703 static const struct panel_desc tpk_f07a_0102 = { 3704 .modes = &tpk_f07a_0102_mode, 3705 .num_modes = 1, 3706 .size = { 3707 .width = 152, 3708 .height = 91, 3709 }, 3710 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3711 }; 3712 3713 static const struct drm_display_mode tpk_f10a_0102_mode = { 3714 .clock = 45000, 3715 .hdisplay = 1024, 3716 .hsync_start = 1024 + 176, 3717 .hsync_end = 1024 + 176 + 5, 3718 .htotal = 1024 + 176 + 5 + 88, 3719 .vdisplay = 600, 3720 .vsync_start = 600 + 20, 3721 .vsync_end = 600 + 20 + 5, 3722 .vtotal = 600 + 20 + 5 + 25, 3723 }; 3724 3725 static const struct panel_desc tpk_f10a_0102 = { 3726 .modes = &tpk_f10a_0102_mode, 3727 .num_modes = 1, 3728 .size = { 3729 .width = 223, 3730 .height = 125, 3731 }, 3732 }; 3733 3734 static const struct display_timing urt_umsh_8596md_timing = { 3735 .pixelclock = { 33260000, 33260000, 33260000 }, 3736 .hactive = { 800, 800, 800 }, 3737 .hfront_porch = { 41, 41, 41 }, 3738 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3739 .hsync_len = { 71, 128, 128 }, 3740 .vactive = { 480, 480, 480 }, 3741 .vfront_porch = { 10, 10, 10 }, 3742 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3743 .vsync_len = { 2, 2, 2 }, 3744 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3745 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3746 }; 3747 3748 static const struct panel_desc urt_umsh_8596md_lvds = { 3749 .timings = &urt_umsh_8596md_timing, 3750 .num_timings = 1, 3751 .bpc = 6, 3752 .size = { 3753 .width = 152, 3754 .height = 91, 3755 }, 3756 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3757 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3758 }; 3759 3760 static const struct panel_desc urt_umsh_8596md_parallel = { 3761 .timings = &urt_umsh_8596md_timing, 3762 .num_timings = 1, 3763 .bpc = 6, 3764 .size = { 3765 .width = 152, 3766 .height = 91, 3767 }, 3768 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3769 }; 3770 3771 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3772 .clock = 60000, 3773 .hdisplay = 1024, 3774 .hsync_start = 1024 + 160, 3775 .hsync_end = 1024 + 160 + 100, 3776 .htotal = 1024 + 160 + 100 + 60, 3777 .vdisplay = 600, 3778 .vsync_start = 600 + 12, 3779 .vsync_end = 600 + 12 + 10, 3780 .vtotal = 600 + 12 + 10 + 13, 3781 }; 3782 3783 static const struct panel_desc vivax_tpc9150_panel = { 3784 .modes = &vivax_tpc9150_panel_mode, 3785 .num_modes = 1, 3786 .bpc = 6, 3787 .size = { 3788 .width = 200, 3789 .height = 115, 3790 }, 3791 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3792 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3794 }; 3795 3796 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3797 .clock = 33333, 3798 .hdisplay = 800, 3799 .hsync_start = 800 + 210, 3800 .hsync_end = 800 + 210 + 20, 3801 .htotal = 800 + 210 + 20 + 46, 3802 .vdisplay = 480, 3803 .vsync_start = 480 + 22, 3804 .vsync_end = 480 + 22 + 10, 3805 .vtotal = 480 + 22 + 10 + 23, 3806 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3807 }; 3808 3809 static const struct panel_desc vl050_8048nt_c01 = { 3810 .modes = &vl050_8048nt_c01_mode, 3811 .num_modes = 1, 3812 .bpc = 8, 3813 .size = { 3814 .width = 120, 3815 .height = 76, 3816 }, 3817 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3818 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3819 }; 3820 3821 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3822 .clock = 6410, 3823 .hdisplay = 320, 3824 .hsync_start = 320 + 20, 3825 .hsync_end = 320 + 20 + 30, 3826 .htotal = 320 + 20 + 30 + 38, 3827 .vdisplay = 240, 3828 .vsync_start = 240 + 4, 3829 .vsync_end = 240 + 4 + 3, 3830 .vtotal = 240 + 4 + 3 + 15, 3831 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3832 }; 3833 3834 static const struct panel_desc winstar_wf35ltiacd = { 3835 .modes = &winstar_wf35ltiacd_mode, 3836 .num_modes = 1, 3837 .bpc = 8, 3838 .size = { 3839 .width = 70, 3840 .height = 53, 3841 }, 3842 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3843 }; 3844 3845 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3846 .clock = 51200, 3847 .hdisplay = 1024, 3848 .hsync_start = 1024 + 100, 3849 .hsync_end = 1024 + 100 + 100, 3850 .htotal = 1024 + 100 + 100 + 120, 3851 .vdisplay = 600, 3852 .vsync_start = 600 + 10, 3853 .vsync_end = 600 + 10 + 10, 3854 .vtotal = 600 + 10 + 10 + 15, 3855 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3856 }; 3857 3858 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3859 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3860 .num_modes = 1, 3861 .bpc = 8, 3862 .size = { 3863 .width = 154, 3864 .height = 90, 3865 }, 3866 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3867 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3868 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3869 }; 3870 3871 static const struct drm_display_mode arm_rtsm_mode[] = { 3872 { 3873 .clock = 65000, 3874 .hdisplay = 1024, 3875 .hsync_start = 1024 + 24, 3876 .hsync_end = 1024 + 24 + 136, 3877 .htotal = 1024 + 24 + 136 + 160, 3878 .vdisplay = 768, 3879 .vsync_start = 768 + 3, 3880 .vsync_end = 768 + 3 + 6, 3881 .vtotal = 768 + 3 + 6 + 29, 3882 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3883 }, 3884 }; 3885 3886 static const struct panel_desc arm_rtsm = { 3887 .modes = arm_rtsm_mode, 3888 .num_modes = 1, 3889 .bpc = 8, 3890 .size = { 3891 .width = 400, 3892 .height = 300, 3893 }, 3894 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3895 }; 3896 3897 static const struct of_device_id platform_of_match[] = { 3898 { 3899 .compatible = "ampire,am-1280800n3tzqw-t00h", 3900 .data = &ire_am_1280800n3tzqw_t00h, 3901 }, { 3902 .compatible = "ampire,am-480272h3tmqw-t01h", 3903 .data = &ire_am_480272h3tmqw_t01h, 3904 }, { 3905 .compatible = "ampire,am800480r3tmqwa1h", 3906 .data = &ire_am800480r3tmqwa1h, 3907 }, { 3908 .compatible = "ampire,am800600p5tmqw-tb8h", 3909 .data = &ire_am800600p5tmqwtb8h, 3910 }, { 3911 .compatible = "arm,rtsm-display", 3912 .data = &arm_rtsm, 3913 }, { 3914 .compatible = "armadeus,st0700-adapt", 3915 .data = &armadeus_st0700_adapt, 3916 }, { 3917 .compatible = "auo,b101aw03", 3918 .data = &auo_b101aw03, 3919 }, { 3920 .compatible = "auo,b101xtn01", 3921 .data = &auo_b101xtn01, 3922 }, { 3923 .compatible = "auo,g070vvn01", 3924 .data = &auo_g070vvn01, 3925 }, { 3926 .compatible = "auo,g101evn010", 3927 .data = &auo_g101evn010, 3928 }, { 3929 .compatible = "auo,g104sn02", 3930 .data = &auo_g104sn02, 3931 }, { 3932 .compatible = "auo,g121ean01", 3933 .data = &auo_g121ean01, 3934 }, { 3935 .compatible = "auo,g133han01", 3936 .data = &auo_g133han01, 3937 }, { 3938 .compatible = "auo,g156xtn01", 3939 .data = &auo_g156xtn01, 3940 }, { 3941 .compatible = "auo,g185han01", 3942 .data = &auo_g185han01, 3943 }, { 3944 .compatible = "auo,g190ean01", 3945 .data = &auo_g190ean01, 3946 }, { 3947 .compatible = "auo,p320hvn03", 3948 .data = &auo_p320hvn03, 3949 }, { 3950 .compatible = "auo,t215hvn01", 3951 .data = &auo_t215hvn01, 3952 }, { 3953 .compatible = "avic,tm070ddh03", 3954 .data = &avic_tm070ddh03, 3955 }, { 3956 .compatible = "bananapi,s070wv20-ct16", 3957 .data = &bananapi_s070wv20_ct16, 3958 }, { 3959 .compatible = "boe,hv070wsa-100", 3960 .data = &boe_hv070wsa 3961 }, { 3962 .compatible = "cdtech,s043wq26h-ct7", 3963 .data = &cdtech_s043wq26h_ct7, 3964 }, { 3965 .compatible = "cdtech,s070pws19hp-fc21", 3966 .data = &cdtech_s070pws19hp_fc21, 3967 }, { 3968 .compatible = "cdtech,s070swv29hg-dc44", 3969 .data = &cdtech_s070swv29hg_dc44, 3970 }, { 3971 .compatible = "cdtech,s070wv95-ct16", 3972 .data = &cdtech_s070wv95_ct16, 3973 }, { 3974 .compatible = "chefree,ch101olhlwh-002", 3975 .data = &chefree_ch101olhlwh_002, 3976 }, { 3977 .compatible = "chunghwa,claa070wp03xg", 3978 .data = &chunghwa_claa070wp03xg, 3979 }, { 3980 .compatible = "chunghwa,claa101wa01a", 3981 .data = &chunghwa_claa101wa01a 3982 }, { 3983 .compatible = "chunghwa,claa101wb01", 3984 .data = &chunghwa_claa101wb01 3985 }, { 3986 .compatible = "dataimage,fg040346dsswbg04", 3987 .data = &dataimage_fg040346dsswbg04, 3988 }, { 3989 .compatible = "dataimage,fg1001l0dsswmg01", 3990 .data = &dataimage_fg1001l0dsswmg01, 3991 }, { 3992 .compatible = "dataimage,scf0700c48ggu18", 3993 .data = &dataimage_scf0700c48ggu18, 3994 }, { 3995 .compatible = "dlc,dlc0700yzg-1", 3996 .data = &dlc_dlc0700yzg_1, 3997 }, { 3998 .compatible = "dlc,dlc1010gig", 3999 .data = &dlc_dlc1010gig, 4000 }, { 4001 .compatible = "edt,et035012dm6", 4002 .data = &edt_et035012dm6, 4003 }, { 4004 .compatible = "edt,etm0350g0dh6", 4005 .data = &edt_etm0350g0dh6, 4006 }, { 4007 .compatible = "edt,etm043080dh6gp", 4008 .data = &edt_etm043080dh6gp, 4009 }, { 4010 .compatible = "edt,etm0430g0dh6", 4011 .data = &edt_etm0430g0dh6, 4012 }, { 4013 .compatible = "edt,et057090dhu", 4014 .data = &edt_et057090dhu, 4015 }, { 4016 .compatible = "edt,et070080dh6", 4017 .data = &edt_etm0700g0dh6, 4018 }, { 4019 .compatible = "edt,etm0700g0dh6", 4020 .data = &edt_etm0700g0dh6, 4021 }, { 4022 .compatible = "edt,etm0700g0bdh6", 4023 .data = &edt_etm0700g0bdh6, 4024 }, { 4025 .compatible = "edt,etm0700g0edh6", 4026 .data = &edt_etm0700g0bdh6, 4027 }, { 4028 .compatible = "edt,etml0700y5dha", 4029 .data = &edt_etml0700y5dha, 4030 }, { 4031 .compatible = "edt,etmv570g2dhu", 4032 .data = &edt_etmv570g2dhu, 4033 }, { 4034 .compatible = "eink,vb3300-kca", 4035 .data = &eink_vb3300_kca, 4036 }, { 4037 .compatible = "evervision,vgg804821", 4038 .data = &evervision_vgg804821, 4039 }, { 4040 .compatible = "foxlink,fl500wvr00-a0t", 4041 .data = &foxlink_fl500wvr00_a0t, 4042 }, { 4043 .compatible = "frida,frd350h54004", 4044 .data = &frida_frd350h54004, 4045 }, { 4046 .compatible = "friendlyarm,hd702e", 4047 .data = &friendlyarm_hd702e, 4048 }, { 4049 .compatible = "giantplus,gpg482739qs5", 4050 .data = &giantplus_gpg482739qs5 4051 }, { 4052 .compatible = "giantplus,gpm940b0", 4053 .data = &giantplus_gpm940b0, 4054 }, { 4055 .compatible = "hannstar,hsd070pww1", 4056 .data = &hannstar_hsd070pww1, 4057 }, { 4058 .compatible = "hannstar,hsd100pxn1", 4059 .data = &hannstar_hsd100pxn1, 4060 }, { 4061 .compatible = "hannstar,hsd101pww2", 4062 .data = &hannstar_hsd101pww2, 4063 }, { 4064 .compatible = "hit,tx23d38vm0caa", 4065 .data = &hitachi_tx23d38vm0caa 4066 }, { 4067 .compatible = "innolux,at043tn24", 4068 .data = &innolux_at043tn24, 4069 }, { 4070 .compatible = "innolux,at070tn92", 4071 .data = &innolux_at070tn92, 4072 }, { 4073 .compatible = "innolux,g070y2-l01", 4074 .data = &innolux_g070y2_l01, 4075 }, { 4076 .compatible = "innolux,g070y2-t02", 4077 .data = &innolux_g070y2_t02, 4078 }, { 4079 .compatible = "innolux,g101ice-l01", 4080 .data = &innolux_g101ice_l01 4081 }, { 4082 .compatible = "innolux,g121i1-l01", 4083 .data = &innolux_g121i1_l01 4084 }, { 4085 .compatible = "innolux,g121x1-l03", 4086 .data = &innolux_g121x1_l03, 4087 }, { 4088 .compatible = "innolux,n156bge-l21", 4089 .data = &innolux_n156bge_l21, 4090 }, { 4091 .compatible = "innolux,zj070na-01p", 4092 .data = &innolux_zj070na_01p, 4093 }, { 4094 .compatible = "koe,tx14d24vm1bpa", 4095 .data = &koe_tx14d24vm1bpa, 4096 }, { 4097 .compatible = "koe,tx26d202vm0bwa", 4098 .data = &koe_tx26d202vm0bwa, 4099 }, { 4100 .compatible = "koe,tx31d200vm0baa", 4101 .data = &koe_tx31d200vm0baa, 4102 }, { 4103 .compatible = "kyo,tcg121xglp", 4104 .data = &kyo_tcg121xglp, 4105 }, { 4106 .compatible = "lemaker,bl035-rgb-002", 4107 .data = &lemaker_bl035_rgb_002, 4108 }, { 4109 .compatible = "lg,lb070wv8", 4110 .data = &lg_lb070wv8, 4111 }, { 4112 .compatible = "logicpd,type28", 4113 .data = &logicpd_type_28, 4114 }, { 4115 .compatible = "logictechno,lt161010-2nhc", 4116 .data = &logictechno_lt161010_2nh, 4117 }, { 4118 .compatible = "logictechno,lt161010-2nhr", 4119 .data = &logictechno_lt161010_2nh, 4120 }, { 4121 .compatible = "logictechno,lt170410-2whc", 4122 .data = &logictechno_lt170410_2whc, 4123 }, { 4124 .compatible = "logictechno,lttd800480070-l2rt", 4125 .data = &logictechno_lttd800480070_l2rt, 4126 }, { 4127 .compatible = "logictechno,lttd800480070-l6wh-rt", 4128 .data = &logictechno_lttd800480070_l6wh_rt, 4129 }, { 4130 .compatible = "mitsubishi,aa070mc01-ca1", 4131 .data = &mitsubishi_aa070mc01, 4132 }, { 4133 .compatible = "multi-inno,mi0700s4t-6", 4134 .data = &multi_inno_mi0700s4t_6, 4135 }, { 4136 .compatible = "multi-inno,mi1010ait-1cp", 4137 .data = &multi_inno_mi1010ait_1cp, 4138 }, { 4139 .compatible = "nec,nl12880bc20-05", 4140 .data = &nec_nl12880bc20_05, 4141 }, { 4142 .compatible = "nec,nl4827hc19-05b", 4143 .data = &nec_nl4827hc19_05b, 4144 }, { 4145 .compatible = "netron-dy,e231732", 4146 .data = &netron_dy_e231732, 4147 }, { 4148 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4149 .data = &newhaven_nhd_43_480272ef_atxl, 4150 }, { 4151 .compatible = "nlt,nl192108ac18-02d", 4152 .data = &nlt_nl192108ac18_02d, 4153 }, { 4154 .compatible = "nvd,9128", 4155 .data = &nvd_9128, 4156 }, { 4157 .compatible = "okaya,rs800480t-7x0gp", 4158 .data = &okaya_rs800480t_7x0gp, 4159 }, { 4160 .compatible = "olimex,lcd-olinuxino-43-ts", 4161 .data = &olimex_lcd_olinuxino_43ts, 4162 }, { 4163 .compatible = "ontat,yx700wv03", 4164 .data = &ontat_yx700wv03, 4165 }, { 4166 .compatible = "ortustech,com37h3m05dtc", 4167 .data = &ortustech_com37h3m, 4168 }, { 4169 .compatible = "ortustech,com37h3m99dtc", 4170 .data = &ortustech_com37h3m, 4171 }, { 4172 .compatible = "ortustech,com43h4m85ulc", 4173 .data = &ortustech_com43h4m85ulc, 4174 }, { 4175 .compatible = "osddisplays,osd070t1718-19ts", 4176 .data = &osddisplays_osd070t1718_19ts, 4177 }, { 4178 .compatible = "pda,91-00156-a0", 4179 .data = &pda_91_00156_a0, 4180 }, { 4181 .compatible = "powertip,ph800480t013-idf02", 4182 .data = &powertip_ph800480t013_idf02, 4183 }, { 4184 .compatible = "qiaodian,qd43003c0-40", 4185 .data = &qd43003c0_40, 4186 }, { 4187 .compatible = "qishenglong,gopher2b-lcd", 4188 .data = &qishenglong_gopher2b_lcd, 4189 }, { 4190 .compatible = "rocktech,rk070er9427", 4191 .data = &rocktech_rk070er9427, 4192 }, { 4193 .compatible = "rocktech,rk101ii01d-ct", 4194 .data = &rocktech_rk101ii01d_ct, 4195 }, { 4196 .compatible = "samsung,ltl101al01", 4197 .data = &samsung_ltl101al01, 4198 }, { 4199 .compatible = "samsung,ltn101nt05", 4200 .data = &samsung_ltn101nt05, 4201 }, { 4202 .compatible = "satoz,sat050at40h12r2", 4203 .data = &satoz_sat050at40h12r2, 4204 }, { 4205 .compatible = "sharp,lq035q7db03", 4206 .data = &sharp_lq035q7db03, 4207 }, { 4208 .compatible = "sharp,lq070y3dg3b", 4209 .data = &sharp_lq070y3dg3b, 4210 }, { 4211 .compatible = "sharp,lq101k1ly04", 4212 .data = &sharp_lq101k1ly04, 4213 }, { 4214 .compatible = "sharp,ls020b1dd01d", 4215 .data = &sharp_ls020b1dd01d, 4216 }, { 4217 .compatible = "shelly,sca07010-bfn-lnn", 4218 .data = &shelly_sca07010_bfn_lnn, 4219 }, { 4220 .compatible = "starry,kr070pe2t", 4221 .data = &starry_kr070pe2t, 4222 }, { 4223 .compatible = "startek,kd070wvfpa", 4224 .data = &startek_kd070wvfpa, 4225 }, { 4226 .compatible = "team-source-display,tst043015cmhx", 4227 .data = &tsd_tst043015cmhx, 4228 }, { 4229 .compatible = "tfc,s9700rtwv43tr-01b", 4230 .data = &tfc_s9700rtwv43tr_01b, 4231 }, { 4232 .compatible = "tianma,tm070jdhg30", 4233 .data = &tianma_tm070jdhg30, 4234 }, { 4235 .compatible = "tianma,tm070jvhg33", 4236 .data = &tianma_tm070jvhg33, 4237 }, { 4238 .compatible = "tianma,tm070rvhg71", 4239 .data = &tianma_tm070rvhg71, 4240 }, { 4241 .compatible = "ti,nspire-cx-lcd-panel", 4242 .data = &ti_nspire_cx_lcd_panel, 4243 }, { 4244 .compatible = "ti,nspire-classic-lcd-panel", 4245 .data = &ti_nspire_classic_lcd_panel, 4246 }, { 4247 .compatible = "toshiba,lt089ac29000", 4248 .data = &toshiba_lt089ac29000, 4249 }, { 4250 .compatible = "tpk,f07a-0102", 4251 .data = &tpk_f07a_0102, 4252 }, { 4253 .compatible = "tpk,f10a-0102", 4254 .data = &tpk_f10a_0102, 4255 }, { 4256 .compatible = "urt,umsh-8596md-t", 4257 .data = &urt_umsh_8596md_parallel, 4258 }, { 4259 .compatible = "urt,umsh-8596md-1t", 4260 .data = &urt_umsh_8596md_parallel, 4261 }, { 4262 .compatible = "urt,umsh-8596md-7t", 4263 .data = &urt_umsh_8596md_parallel, 4264 }, { 4265 .compatible = "urt,umsh-8596md-11t", 4266 .data = &urt_umsh_8596md_lvds, 4267 }, { 4268 .compatible = "urt,umsh-8596md-19t", 4269 .data = &urt_umsh_8596md_lvds, 4270 }, { 4271 .compatible = "urt,umsh-8596md-20t", 4272 .data = &urt_umsh_8596md_parallel, 4273 }, { 4274 .compatible = "vivax,tpc9150-panel", 4275 .data = &vivax_tpc9150_panel, 4276 }, { 4277 .compatible = "vxt,vl050-8048nt-c01", 4278 .data = &vl050_8048nt_c01, 4279 }, { 4280 .compatible = "winstar,wf35ltiacd", 4281 .data = &winstar_wf35ltiacd, 4282 }, { 4283 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4284 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4285 }, { 4286 /* Must be the last entry */ 4287 .compatible = "panel-dpi", 4288 .data = &panel_dpi, 4289 }, { 4290 /* sentinel */ 4291 } 4292 }; 4293 MODULE_DEVICE_TABLE(of, platform_of_match); 4294 4295 static int panel_simple_platform_probe(struct platform_device *pdev) 4296 { 4297 const struct of_device_id *id; 4298 4299 id = of_match_node(platform_of_match, pdev->dev.of_node); 4300 if (!id) 4301 return -ENODEV; 4302 4303 return panel_simple_probe(&pdev->dev, id->data); 4304 } 4305 4306 static int panel_simple_platform_remove(struct platform_device *pdev) 4307 { 4308 panel_simple_remove(&pdev->dev); 4309 4310 return 0; 4311 } 4312 4313 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4314 { 4315 panel_simple_shutdown(&pdev->dev); 4316 } 4317 4318 static const struct dev_pm_ops panel_simple_pm_ops = { 4319 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4320 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4321 pm_runtime_force_resume) 4322 }; 4323 4324 static struct platform_driver panel_simple_platform_driver = { 4325 .driver = { 4326 .name = "panel-simple", 4327 .of_match_table = platform_of_match, 4328 .pm = &panel_simple_pm_ops, 4329 }, 4330 .probe = panel_simple_platform_probe, 4331 .remove = panel_simple_platform_remove, 4332 .shutdown = panel_simple_platform_shutdown, 4333 }; 4334 4335 struct panel_desc_dsi { 4336 struct panel_desc desc; 4337 4338 unsigned long flags; 4339 enum mipi_dsi_pixel_format format; 4340 unsigned int lanes; 4341 }; 4342 4343 static const struct drm_display_mode auo_b080uan01_mode = { 4344 .clock = 154500, 4345 .hdisplay = 1200, 4346 .hsync_start = 1200 + 62, 4347 .hsync_end = 1200 + 62 + 4, 4348 .htotal = 1200 + 62 + 4 + 62, 4349 .vdisplay = 1920, 4350 .vsync_start = 1920 + 9, 4351 .vsync_end = 1920 + 9 + 2, 4352 .vtotal = 1920 + 9 + 2 + 8, 4353 }; 4354 4355 static const struct panel_desc_dsi auo_b080uan01 = { 4356 .desc = { 4357 .modes = &auo_b080uan01_mode, 4358 .num_modes = 1, 4359 .bpc = 8, 4360 .size = { 4361 .width = 108, 4362 .height = 272, 4363 }, 4364 .connector_type = DRM_MODE_CONNECTOR_DSI, 4365 }, 4366 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4367 .format = MIPI_DSI_FMT_RGB888, 4368 .lanes = 4, 4369 }; 4370 4371 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4372 .clock = 160000, 4373 .hdisplay = 1200, 4374 .hsync_start = 1200 + 120, 4375 .hsync_end = 1200 + 120 + 20, 4376 .htotal = 1200 + 120 + 20 + 21, 4377 .vdisplay = 1920, 4378 .vsync_start = 1920 + 21, 4379 .vsync_end = 1920 + 21 + 3, 4380 .vtotal = 1920 + 21 + 3 + 18, 4381 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4382 }; 4383 4384 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4385 .desc = { 4386 .modes = &boe_tv080wum_nl0_mode, 4387 .num_modes = 1, 4388 .size = { 4389 .width = 107, 4390 .height = 172, 4391 }, 4392 .connector_type = DRM_MODE_CONNECTOR_DSI, 4393 }, 4394 .flags = MIPI_DSI_MODE_VIDEO | 4395 MIPI_DSI_MODE_VIDEO_BURST | 4396 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4397 .format = MIPI_DSI_FMT_RGB888, 4398 .lanes = 4, 4399 }; 4400 4401 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4402 .clock = 71000, 4403 .hdisplay = 800, 4404 .hsync_start = 800 + 32, 4405 .hsync_end = 800 + 32 + 1, 4406 .htotal = 800 + 32 + 1 + 57, 4407 .vdisplay = 1280, 4408 .vsync_start = 1280 + 28, 4409 .vsync_end = 1280 + 28 + 1, 4410 .vtotal = 1280 + 28 + 1 + 14, 4411 }; 4412 4413 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4414 .desc = { 4415 .modes = &lg_ld070wx3_sl01_mode, 4416 .num_modes = 1, 4417 .bpc = 8, 4418 .size = { 4419 .width = 94, 4420 .height = 151, 4421 }, 4422 .connector_type = DRM_MODE_CONNECTOR_DSI, 4423 }, 4424 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4425 .format = MIPI_DSI_FMT_RGB888, 4426 .lanes = 4, 4427 }; 4428 4429 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4430 .clock = 67000, 4431 .hdisplay = 720, 4432 .hsync_start = 720 + 12, 4433 .hsync_end = 720 + 12 + 4, 4434 .htotal = 720 + 12 + 4 + 112, 4435 .vdisplay = 1280, 4436 .vsync_start = 1280 + 8, 4437 .vsync_end = 1280 + 8 + 4, 4438 .vtotal = 1280 + 8 + 4 + 12, 4439 }; 4440 4441 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4442 .desc = { 4443 .modes = &lg_lh500wx1_sd03_mode, 4444 .num_modes = 1, 4445 .bpc = 8, 4446 .size = { 4447 .width = 62, 4448 .height = 110, 4449 }, 4450 .connector_type = DRM_MODE_CONNECTOR_DSI, 4451 }, 4452 .flags = MIPI_DSI_MODE_VIDEO, 4453 .format = MIPI_DSI_FMT_RGB888, 4454 .lanes = 4, 4455 }; 4456 4457 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4458 .clock = 157200, 4459 .hdisplay = 1920, 4460 .hsync_start = 1920 + 154, 4461 .hsync_end = 1920 + 154 + 16, 4462 .htotal = 1920 + 154 + 16 + 32, 4463 .vdisplay = 1200, 4464 .vsync_start = 1200 + 17, 4465 .vsync_end = 1200 + 17 + 2, 4466 .vtotal = 1200 + 17 + 2 + 16, 4467 }; 4468 4469 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4470 .desc = { 4471 .modes = &panasonic_vvx10f004b00_mode, 4472 .num_modes = 1, 4473 .bpc = 8, 4474 .size = { 4475 .width = 217, 4476 .height = 136, 4477 }, 4478 .connector_type = DRM_MODE_CONNECTOR_DSI, 4479 }, 4480 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4481 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4482 .format = MIPI_DSI_FMT_RGB888, 4483 .lanes = 4, 4484 }; 4485 4486 static const struct drm_display_mode lg_acx467akm_7_mode = { 4487 .clock = 150000, 4488 .hdisplay = 1080, 4489 .hsync_start = 1080 + 2, 4490 .hsync_end = 1080 + 2 + 2, 4491 .htotal = 1080 + 2 + 2 + 2, 4492 .vdisplay = 1920, 4493 .vsync_start = 1920 + 2, 4494 .vsync_end = 1920 + 2 + 2, 4495 .vtotal = 1920 + 2 + 2 + 2, 4496 }; 4497 4498 static const struct panel_desc_dsi lg_acx467akm_7 = { 4499 .desc = { 4500 .modes = &lg_acx467akm_7_mode, 4501 .num_modes = 1, 4502 .bpc = 8, 4503 .size = { 4504 .width = 62, 4505 .height = 110, 4506 }, 4507 .connector_type = DRM_MODE_CONNECTOR_DSI, 4508 }, 4509 .flags = 0, 4510 .format = MIPI_DSI_FMT_RGB888, 4511 .lanes = 4, 4512 }; 4513 4514 static const struct drm_display_mode osd101t2045_53ts_mode = { 4515 .clock = 154500, 4516 .hdisplay = 1920, 4517 .hsync_start = 1920 + 112, 4518 .hsync_end = 1920 + 112 + 16, 4519 .htotal = 1920 + 112 + 16 + 32, 4520 .vdisplay = 1200, 4521 .vsync_start = 1200 + 16, 4522 .vsync_end = 1200 + 16 + 2, 4523 .vtotal = 1200 + 16 + 2 + 16, 4524 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4525 }; 4526 4527 static const struct panel_desc_dsi osd101t2045_53ts = { 4528 .desc = { 4529 .modes = &osd101t2045_53ts_mode, 4530 .num_modes = 1, 4531 .bpc = 8, 4532 .size = { 4533 .width = 217, 4534 .height = 136, 4535 }, 4536 .connector_type = DRM_MODE_CONNECTOR_DSI, 4537 }, 4538 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4539 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4540 MIPI_DSI_MODE_NO_EOT_PACKET, 4541 .format = MIPI_DSI_FMT_RGB888, 4542 .lanes = 4, 4543 }; 4544 4545 static const struct of_device_id dsi_of_match[] = { 4546 { 4547 .compatible = "auo,b080uan01", 4548 .data = &auo_b080uan01 4549 }, { 4550 .compatible = "boe,tv080wum-nl0", 4551 .data = &boe_tv080wum_nl0 4552 }, { 4553 .compatible = "lg,ld070wx3-sl01", 4554 .data = &lg_ld070wx3_sl01 4555 }, { 4556 .compatible = "lg,lh500wx1-sd03", 4557 .data = &lg_lh500wx1_sd03 4558 }, { 4559 .compatible = "panasonic,vvx10f004b00", 4560 .data = &panasonic_vvx10f004b00 4561 }, { 4562 .compatible = "lg,acx467akm-7", 4563 .data = &lg_acx467akm_7 4564 }, { 4565 .compatible = "osddisplays,osd101t2045-53ts", 4566 .data = &osd101t2045_53ts 4567 }, { 4568 /* sentinel */ 4569 } 4570 }; 4571 MODULE_DEVICE_TABLE(of, dsi_of_match); 4572 4573 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4574 { 4575 const struct panel_desc_dsi *desc; 4576 const struct of_device_id *id; 4577 int err; 4578 4579 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4580 if (!id) 4581 return -ENODEV; 4582 4583 desc = id->data; 4584 4585 err = panel_simple_probe(&dsi->dev, &desc->desc); 4586 if (err < 0) 4587 return err; 4588 4589 dsi->mode_flags = desc->flags; 4590 dsi->format = desc->format; 4591 dsi->lanes = desc->lanes; 4592 4593 err = mipi_dsi_attach(dsi); 4594 if (err) { 4595 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4596 4597 drm_panel_remove(&panel->base); 4598 } 4599 4600 return err; 4601 } 4602 4603 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4604 { 4605 int err; 4606 4607 err = mipi_dsi_detach(dsi); 4608 if (err < 0) 4609 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4610 4611 panel_simple_remove(&dsi->dev); 4612 } 4613 4614 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4615 { 4616 panel_simple_shutdown(&dsi->dev); 4617 } 4618 4619 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4620 .driver = { 4621 .name = "panel-simple-dsi", 4622 .of_match_table = dsi_of_match, 4623 .pm = &panel_simple_pm_ops, 4624 }, 4625 .probe = panel_simple_dsi_probe, 4626 .remove = panel_simple_dsi_remove, 4627 .shutdown = panel_simple_dsi_shutdown, 4628 }; 4629 4630 static int __init panel_simple_init(void) 4631 { 4632 int err; 4633 4634 err = platform_driver_register(&panel_simple_platform_driver); 4635 if (err < 0) 4636 return err; 4637 4638 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4639 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4640 if (err < 0) 4641 goto err_did_platform_register; 4642 } 4643 4644 return 0; 4645 4646 err_did_platform_register: 4647 platform_driver_unregister(&panel_simple_platform_driver); 4648 4649 return err; 4650 } 4651 module_init(panel_simple_init); 4652 4653 static void __exit panel_simple_exit(void) 4654 { 4655 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4656 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4657 4658 platform_driver_unregister(&panel_simple_platform_driver); 4659 } 4660 module_exit(panel_simple_exit); 4661 4662 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4663 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4664 MODULE_LICENSE("GPL and additional rights"); 4665