1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_timings == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 if (p->enable_gpio) 191 gpiod_set_value_cansleep(p->enable_gpio, 0); 192 193 regulator_disable(p->supply); 194 195 if (p->desc->delay.unprepare) 196 msleep(p->desc->delay.unprepare); 197 198 p->prepared = false; 199 200 return 0; 201 } 202 203 static int panel_simple_prepare(struct drm_panel *panel) 204 { 205 struct panel_simple *p = to_panel_simple(panel); 206 int err; 207 208 if (p->prepared) 209 return 0; 210 211 err = regulator_enable(p->supply); 212 if (err < 0) { 213 dev_err(panel->dev, "failed to enable supply: %d\n", err); 214 return err; 215 } 216 217 if (p->enable_gpio) 218 gpiod_set_value_cansleep(p->enable_gpio, 1); 219 220 if (p->desc->delay.prepare) 221 msleep(p->desc->delay.prepare); 222 223 p->prepared = true; 224 225 return 0; 226 } 227 228 static int panel_simple_enable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (p->enabled) 233 return 0; 234 235 if (p->desc->delay.enable) 236 msleep(p->desc->delay.enable); 237 238 if (p->backlight) { 239 p->backlight->props.state &= ~BL_CORE_FBBLANK; 240 p->backlight->props.power = FB_BLANK_UNBLANK; 241 backlight_update_status(p->backlight); 242 } 243 244 p->enabled = true; 245 246 return 0; 247 } 248 249 static int panel_simple_get_modes(struct drm_panel *panel) 250 { 251 struct panel_simple *p = to_panel_simple(panel); 252 int num = 0; 253 254 /* probe EDID if a DDC bus is available */ 255 if (p->ddc) { 256 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 257 drm_mode_connector_update_edid_property(panel->connector, edid); 258 if (edid) { 259 num += drm_add_edid_modes(panel->connector, edid); 260 kfree(edid); 261 } 262 } 263 264 /* add hard-coded panel modes */ 265 num += panel_simple_get_fixed_modes(p); 266 267 return num; 268 } 269 270 static int panel_simple_get_timings(struct drm_panel *panel, 271 unsigned int num_timings, 272 struct display_timing *timings) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int i; 276 277 if (p->desc->num_timings < num_timings) 278 num_timings = p->desc->num_timings; 279 280 if (timings) 281 for (i = 0; i < num_timings; i++) 282 timings[i] = p->desc->timings[i]; 283 284 return p->desc->num_timings; 285 } 286 287 static const struct drm_panel_funcs panel_simple_funcs = { 288 .disable = panel_simple_disable, 289 .unprepare = panel_simple_unprepare, 290 .prepare = panel_simple_prepare, 291 .enable = panel_simple_enable, 292 .get_modes = panel_simple_get_modes, 293 .get_timings = panel_simple_get_timings, 294 }; 295 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 297 { 298 struct device_node *backlight, *ddc; 299 struct panel_simple *panel; 300 int err; 301 302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 303 if (!panel) 304 return -ENOMEM; 305 306 panel->enabled = false; 307 panel->prepared = false; 308 panel->desc = desc; 309 310 panel->supply = devm_regulator_get(dev, "power"); 311 if (IS_ERR(panel->supply)) 312 return PTR_ERR(panel->supply); 313 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 315 GPIOD_OUT_LOW); 316 if (IS_ERR(panel->enable_gpio)) { 317 err = PTR_ERR(panel->enable_gpio); 318 dev_err(dev, "failed to request GPIO: %d\n", err); 319 return err; 320 } 321 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 323 if (backlight) { 324 panel->backlight = of_find_backlight_by_node(backlight); 325 of_node_put(backlight); 326 327 if (!panel->backlight) 328 return -EPROBE_DEFER; 329 } 330 331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 332 if (ddc) { 333 panel->ddc = of_find_i2c_adapter_by_node(ddc); 334 of_node_put(ddc); 335 336 if (!panel->ddc) { 337 err = -EPROBE_DEFER; 338 goto free_backlight; 339 } 340 } 341 342 drm_panel_init(&panel->base); 343 panel->base.dev = dev; 344 panel->base.funcs = &panel_simple_funcs; 345 346 err = drm_panel_add(&panel->base); 347 if (err < 0) 348 goto free_ddc; 349 350 dev_set_drvdata(dev, panel); 351 352 return 0; 353 354 free_ddc: 355 if (panel->ddc) 356 put_device(&panel->ddc->dev); 357 free_backlight: 358 if (panel->backlight) 359 put_device(&panel->backlight->dev); 360 361 return err; 362 } 363 364 static int panel_simple_remove(struct device *dev) 365 { 366 struct panel_simple *panel = dev_get_drvdata(dev); 367 368 drm_panel_detach(&panel->base); 369 drm_panel_remove(&panel->base); 370 371 panel_simple_disable(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 390 .clock = 33333, 391 .hdisplay = 800, 392 .hsync_start = 800 + 0, 393 .hsync_end = 800 + 0 + 255, 394 .htotal = 800 + 0 + 255 + 0, 395 .vdisplay = 480, 396 .vsync_start = 480 + 2, 397 .vsync_end = 480 + 2 + 45, 398 .vtotal = 480 + 2 + 45 + 0, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am800480r3tmqwa1h = { 404 .modes = &ire_am800480r3tmqwa1h_mode, 405 .num_modes = 1, 406 .bpc = 6, 407 .size = { 408 .width = 152, 409 .height = 91, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 412 }; 413 414 static const struct drm_display_mode auo_b101aw03_mode = { 415 .clock = 51450, 416 .hdisplay = 1024, 417 .hsync_start = 1024 + 156, 418 .hsync_end = 1024 + 156 + 8, 419 .htotal = 1024 + 156 + 8 + 156, 420 .vdisplay = 600, 421 .vsync_start = 600 + 16, 422 .vsync_end = 600 + 16 + 6, 423 .vtotal = 600 + 16 + 6 + 16, 424 .vrefresh = 60, 425 }; 426 427 static const struct panel_desc auo_b101aw03 = { 428 .modes = &auo_b101aw03_mode, 429 .num_modes = 1, 430 .bpc = 6, 431 .size = { 432 .width = 223, 433 .height = 125, 434 }, 435 }; 436 437 static const struct drm_display_mode auo_b101ean01_mode = { 438 .clock = 72500, 439 .hdisplay = 1280, 440 .hsync_start = 1280 + 119, 441 .hsync_end = 1280 + 119 + 32, 442 .htotal = 1280 + 119 + 32 + 21, 443 .vdisplay = 800, 444 .vsync_start = 800 + 4, 445 .vsync_end = 800 + 4 + 20, 446 .vtotal = 800 + 4 + 20 + 8, 447 .vrefresh = 60, 448 }; 449 450 static const struct panel_desc auo_b101ean01 = { 451 .modes = &auo_b101ean01_mode, 452 .num_modes = 1, 453 .bpc = 6, 454 .size = { 455 .width = 217, 456 .height = 136, 457 }, 458 }; 459 460 static const struct drm_display_mode auo_b101xtn01_mode = { 461 .clock = 72000, 462 .hdisplay = 1366, 463 .hsync_start = 1366 + 20, 464 .hsync_end = 1366 + 20 + 70, 465 .htotal = 1366 + 20 + 70, 466 .vdisplay = 768, 467 .vsync_start = 768 + 14, 468 .vsync_end = 768 + 14 + 42, 469 .vtotal = 768 + 14 + 42, 470 .vrefresh = 60, 471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 472 }; 473 474 static const struct panel_desc auo_b101xtn01 = { 475 .modes = &auo_b101xtn01_mode, 476 .num_modes = 1, 477 .bpc = 6, 478 .size = { 479 .width = 223, 480 .height = 125, 481 }, 482 }; 483 484 static const struct drm_display_mode auo_b116xw03_mode = { 485 .clock = 70589, 486 .hdisplay = 1366, 487 .hsync_start = 1366 + 40, 488 .hsync_end = 1366 + 40 + 40, 489 .htotal = 1366 + 40 + 40 + 32, 490 .vdisplay = 768, 491 .vsync_start = 768 + 10, 492 .vsync_end = 768 + 10 + 12, 493 .vtotal = 768 + 10 + 12 + 6, 494 .vrefresh = 60, 495 }; 496 497 static const struct panel_desc auo_b116xw03 = { 498 .modes = &auo_b116xw03_mode, 499 .num_modes = 1, 500 .bpc = 6, 501 .size = { 502 .width = 256, 503 .height = 144, 504 }, 505 }; 506 507 static const struct drm_display_mode auo_b133xtn01_mode = { 508 .clock = 69500, 509 .hdisplay = 1366, 510 .hsync_start = 1366 + 48, 511 .hsync_end = 1366 + 48 + 32, 512 .htotal = 1366 + 48 + 32 + 20, 513 .vdisplay = 768, 514 .vsync_start = 768 + 3, 515 .vsync_end = 768 + 3 + 6, 516 .vtotal = 768 + 3 + 6 + 13, 517 .vrefresh = 60, 518 }; 519 520 static const struct panel_desc auo_b133xtn01 = { 521 .modes = &auo_b133xtn01_mode, 522 .num_modes = 1, 523 .bpc = 6, 524 .size = { 525 .width = 293, 526 .height = 165, 527 }, 528 }; 529 530 static const struct drm_display_mode auo_b133htn01_mode = { 531 .clock = 150660, 532 .hdisplay = 1920, 533 .hsync_start = 1920 + 172, 534 .hsync_end = 1920 + 172 + 80, 535 .htotal = 1920 + 172 + 80 + 60, 536 .vdisplay = 1080, 537 .vsync_start = 1080 + 25, 538 .vsync_end = 1080 + 25 + 10, 539 .vtotal = 1080 + 25 + 10 + 10, 540 .vrefresh = 60, 541 }; 542 543 static const struct panel_desc auo_b133htn01 = { 544 .modes = &auo_b133htn01_mode, 545 .num_modes = 1, 546 .bpc = 6, 547 .size = { 548 .width = 293, 549 .height = 165, 550 }, 551 .delay = { 552 .prepare = 105, 553 .enable = 20, 554 .unprepare = 50, 555 }, 556 }; 557 558 static const struct display_timing auo_g133han01_timings = { 559 .pixelclock = { 134000000, 141200000, 149000000 }, 560 .hactive = { 1920, 1920, 1920 }, 561 .hfront_porch = { 39, 58, 77 }, 562 .hback_porch = { 59, 88, 117 }, 563 .hsync_len = { 28, 42, 56 }, 564 .vactive = { 1080, 1080, 1080 }, 565 .vfront_porch = { 3, 8, 11 }, 566 .vback_porch = { 5, 14, 19 }, 567 .vsync_len = { 4, 14, 19 }, 568 }; 569 570 static const struct panel_desc auo_g133han01 = { 571 .timings = &auo_g133han01_timings, 572 .num_timings = 1, 573 .bpc = 8, 574 .size = { 575 .width = 293, 576 .height = 165, 577 }, 578 .delay = { 579 .prepare = 200, 580 .enable = 50, 581 .disable = 50, 582 .unprepare = 1000, 583 }, 584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 585 }; 586 587 static const struct display_timing auo_g185han01_timings = { 588 .pixelclock = { 120000000, 144000000, 175000000 }, 589 .hactive = { 1920, 1920, 1920 }, 590 .hfront_porch = { 18, 60, 74 }, 591 .hback_porch = { 12, 44, 54 }, 592 .hsync_len = { 10, 24, 32 }, 593 .vactive = { 1080, 1080, 1080 }, 594 .vfront_porch = { 6, 10, 40 }, 595 .vback_porch = { 2, 5, 20 }, 596 .vsync_len = { 2, 5, 20 }, 597 }; 598 599 static const struct panel_desc auo_g185han01 = { 600 .timings = &auo_g185han01_timings, 601 .num_timings = 1, 602 .bpc = 8, 603 .size = { 604 .width = 409, 605 .height = 230, 606 }, 607 .delay = { 608 .prepare = 50, 609 .enable = 200, 610 .disable = 110, 611 .unprepare = 1000, 612 }, 613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 614 }; 615 616 static const struct drm_display_mode auo_t215hvn01_mode = { 617 .clock = 148800, 618 .hdisplay = 1920, 619 .hsync_start = 1920 + 88, 620 .hsync_end = 1920 + 88 + 44, 621 .htotal = 1920 + 88 + 44 + 148, 622 .vdisplay = 1080, 623 .vsync_start = 1080 + 4, 624 .vsync_end = 1080 + 4 + 5, 625 .vtotal = 1080 + 4 + 5 + 36, 626 .vrefresh = 60, 627 }; 628 629 static const struct panel_desc auo_t215hvn01 = { 630 .modes = &auo_t215hvn01_mode, 631 .num_modes = 1, 632 .bpc = 8, 633 .size = { 634 .width = 430, 635 .height = 270, 636 }, 637 .delay = { 638 .disable = 5, 639 .unprepare = 1000, 640 } 641 }; 642 643 static const struct drm_display_mode avic_tm070ddh03_mode = { 644 .clock = 51200, 645 .hdisplay = 1024, 646 .hsync_start = 1024 + 160, 647 .hsync_end = 1024 + 160 + 4, 648 .htotal = 1024 + 160 + 4 + 156, 649 .vdisplay = 600, 650 .vsync_start = 600 + 17, 651 .vsync_end = 600 + 17 + 1, 652 .vtotal = 600 + 17 + 1 + 17, 653 .vrefresh = 60, 654 }; 655 656 static const struct panel_desc avic_tm070ddh03 = { 657 .modes = &avic_tm070ddh03_mode, 658 .num_modes = 1, 659 .bpc = 8, 660 .size = { 661 .width = 154, 662 .height = 90, 663 }, 664 .delay = { 665 .prepare = 20, 666 .enable = 200, 667 .disable = 200, 668 }, 669 }; 670 671 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 672 { 673 .clock = 71900, 674 .hdisplay = 1280, 675 .hsync_start = 1280 + 48, 676 .hsync_end = 1280 + 48 + 32, 677 .htotal = 1280 + 48 + 32 + 80, 678 .vdisplay = 800, 679 .vsync_start = 800 + 3, 680 .vsync_end = 800 + 3 + 5, 681 .vtotal = 800 + 3 + 5 + 24, 682 .vrefresh = 60, 683 }, 684 { 685 .clock = 57500, 686 .hdisplay = 1280, 687 .hsync_start = 1280 + 48, 688 .hsync_end = 1280 + 48 + 32, 689 .htotal = 1280 + 48 + 32 + 80, 690 .vdisplay = 800, 691 .vsync_start = 800 + 3, 692 .vsync_end = 800 + 3 + 5, 693 .vtotal = 800 + 3 + 5 + 24, 694 .vrefresh = 48, 695 }, 696 }; 697 698 static const struct panel_desc boe_nv101wxmn51 = { 699 .modes = boe_nv101wxmn51_modes, 700 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 701 .bpc = 8, 702 .size = { 703 .width = 217, 704 .height = 136, 705 }, 706 .delay = { 707 .prepare = 210, 708 .enable = 50, 709 .unprepare = 160, 710 }, 711 }; 712 713 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 714 .clock = 66770, 715 .hdisplay = 800, 716 .hsync_start = 800 + 49, 717 .hsync_end = 800 + 49 + 33, 718 .htotal = 800 + 49 + 33 + 17, 719 .vdisplay = 1280, 720 .vsync_start = 1280 + 1, 721 .vsync_end = 1280 + 1 + 7, 722 .vtotal = 1280 + 1 + 7 + 15, 723 .vrefresh = 60, 724 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 725 }; 726 727 static const struct panel_desc chunghwa_claa070wp03xg = { 728 .modes = &chunghwa_claa070wp03xg_mode, 729 .num_modes = 1, 730 .bpc = 6, 731 .size = { 732 .width = 94, 733 .height = 150, 734 }, 735 }; 736 737 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 738 .clock = 72070, 739 .hdisplay = 1366, 740 .hsync_start = 1366 + 58, 741 .hsync_end = 1366 + 58 + 58, 742 .htotal = 1366 + 58 + 58 + 58, 743 .vdisplay = 768, 744 .vsync_start = 768 + 4, 745 .vsync_end = 768 + 4 + 4, 746 .vtotal = 768 + 4 + 4 + 4, 747 .vrefresh = 60, 748 }; 749 750 static const struct panel_desc chunghwa_claa101wa01a = { 751 .modes = &chunghwa_claa101wa01a_mode, 752 .num_modes = 1, 753 .bpc = 6, 754 .size = { 755 .width = 220, 756 .height = 120, 757 }, 758 }; 759 760 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 761 .clock = 69300, 762 .hdisplay = 1366, 763 .hsync_start = 1366 + 48, 764 .hsync_end = 1366 + 48 + 32, 765 .htotal = 1366 + 48 + 32 + 20, 766 .vdisplay = 768, 767 .vsync_start = 768 + 16, 768 .vsync_end = 768 + 16 + 8, 769 .vtotal = 768 + 16 + 8 + 16, 770 .vrefresh = 60, 771 }; 772 773 static const struct panel_desc chunghwa_claa101wb01 = { 774 .modes = &chunghwa_claa101wb01_mode, 775 .num_modes = 1, 776 .bpc = 6, 777 .size = { 778 .width = 223, 779 .height = 125, 780 }, 781 }; 782 783 static const struct drm_display_mode edt_et057090dhu_mode = { 784 .clock = 25175, 785 .hdisplay = 640, 786 .hsync_start = 640 + 16, 787 .hsync_end = 640 + 16 + 30, 788 .htotal = 640 + 16 + 30 + 114, 789 .vdisplay = 480, 790 .vsync_start = 480 + 10, 791 .vsync_end = 480 + 10 + 3, 792 .vtotal = 480 + 10 + 3 + 32, 793 .vrefresh = 60, 794 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 795 }; 796 797 static const struct panel_desc edt_et057090dhu = { 798 .modes = &edt_et057090dhu_mode, 799 .num_modes = 1, 800 .bpc = 6, 801 .size = { 802 .width = 115, 803 .height = 86, 804 }, 805 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 806 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 807 }; 808 809 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 810 .clock = 33260, 811 .hdisplay = 800, 812 .hsync_start = 800 + 40, 813 .hsync_end = 800 + 40 + 128, 814 .htotal = 800 + 40 + 128 + 88, 815 .vdisplay = 480, 816 .vsync_start = 480 + 10, 817 .vsync_end = 480 + 10 + 2, 818 .vtotal = 480 + 10 + 2 + 33, 819 .vrefresh = 60, 820 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 821 }; 822 823 static const struct panel_desc edt_etm0700g0dh6 = { 824 .modes = &edt_etm0700g0dh6_mode, 825 .num_modes = 1, 826 .bpc = 6, 827 .size = { 828 .width = 152, 829 .height = 91, 830 }, 831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 833 }; 834 835 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 836 .clock = 32260, 837 .hdisplay = 800, 838 .hsync_start = 800 + 168, 839 .hsync_end = 800 + 168 + 64, 840 .htotal = 800 + 168 + 64 + 88, 841 .vdisplay = 480, 842 .vsync_start = 480 + 37, 843 .vsync_end = 480 + 37 + 2, 844 .vtotal = 480 + 37 + 2 + 8, 845 .vrefresh = 60, 846 }; 847 848 static const struct panel_desc foxlink_fl500wvr00_a0t = { 849 .modes = &foxlink_fl500wvr00_a0t_mode, 850 .num_modes = 1, 851 .bpc = 8, 852 .size = { 853 .width = 108, 854 .height = 65, 855 }, 856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 857 }; 858 859 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 860 .clock = 9000, 861 .hdisplay = 480, 862 .hsync_start = 480 + 5, 863 .hsync_end = 480 + 5 + 1, 864 .htotal = 480 + 5 + 1 + 40, 865 .vdisplay = 272, 866 .vsync_start = 272 + 8, 867 .vsync_end = 272 + 8 + 1, 868 .vtotal = 272 + 8 + 1 + 8, 869 .vrefresh = 60, 870 }; 871 872 static const struct panel_desc giantplus_gpg482739qs5 = { 873 .modes = &giantplus_gpg482739qs5_mode, 874 .num_modes = 1, 875 .bpc = 8, 876 .size = { 877 .width = 95, 878 .height = 54, 879 }, 880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 881 }; 882 883 static const struct display_timing hannstar_hsd070pww1_timing = { 884 .pixelclock = { 64300000, 71100000, 82000000 }, 885 .hactive = { 1280, 1280, 1280 }, 886 .hfront_porch = { 1, 1, 10 }, 887 .hback_porch = { 1, 1, 10 }, 888 /* 889 * According to the data sheet, the minimum horizontal blanking interval 890 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 891 * minimum working horizontal blanking interval to be 60 clocks. 892 */ 893 .hsync_len = { 58, 158, 661 }, 894 .vactive = { 800, 800, 800 }, 895 .vfront_porch = { 1, 1, 10 }, 896 .vback_porch = { 1, 1, 10 }, 897 .vsync_len = { 1, 21, 203 }, 898 .flags = DISPLAY_FLAGS_DE_HIGH, 899 }; 900 901 static const struct panel_desc hannstar_hsd070pww1 = { 902 .timings = &hannstar_hsd070pww1_timing, 903 .num_timings = 1, 904 .bpc = 6, 905 .size = { 906 .width = 151, 907 .height = 94, 908 }, 909 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 910 }; 911 912 static const struct display_timing hannstar_hsd100pxn1_timing = { 913 .pixelclock = { 55000000, 65000000, 75000000 }, 914 .hactive = { 1024, 1024, 1024 }, 915 .hfront_porch = { 40, 40, 40 }, 916 .hback_porch = { 220, 220, 220 }, 917 .hsync_len = { 20, 60, 100 }, 918 .vactive = { 768, 768, 768 }, 919 .vfront_porch = { 7, 7, 7 }, 920 .vback_porch = { 21, 21, 21 }, 921 .vsync_len = { 10, 10, 10 }, 922 .flags = DISPLAY_FLAGS_DE_HIGH, 923 }; 924 925 static const struct panel_desc hannstar_hsd100pxn1 = { 926 .timings = &hannstar_hsd100pxn1_timing, 927 .num_timings = 1, 928 .bpc = 6, 929 .size = { 930 .width = 203, 931 .height = 152, 932 }, 933 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 934 }; 935 936 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 937 .clock = 33333, 938 .hdisplay = 800, 939 .hsync_start = 800 + 85, 940 .hsync_end = 800 + 85 + 86, 941 .htotal = 800 + 85 + 86 + 85, 942 .vdisplay = 480, 943 .vsync_start = 480 + 16, 944 .vsync_end = 480 + 16 + 13, 945 .vtotal = 480 + 16 + 13 + 16, 946 .vrefresh = 60, 947 }; 948 949 static const struct panel_desc hitachi_tx23d38vm0caa = { 950 .modes = &hitachi_tx23d38vm0caa_mode, 951 .num_modes = 1, 952 .bpc = 6, 953 .size = { 954 .width = 195, 955 .height = 117, 956 }, 957 }; 958 959 static const struct drm_display_mode innolux_at043tn24_mode = { 960 .clock = 9000, 961 .hdisplay = 480, 962 .hsync_start = 480 + 2, 963 .hsync_end = 480 + 2 + 41, 964 .htotal = 480 + 2 + 41 + 2, 965 .vdisplay = 272, 966 .vsync_start = 272 + 2, 967 .vsync_end = 272 + 2 + 11, 968 .vtotal = 272 + 2 + 11 + 2, 969 .vrefresh = 60, 970 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 971 }; 972 973 static const struct panel_desc innolux_at043tn24 = { 974 .modes = &innolux_at043tn24_mode, 975 .num_modes = 1, 976 .bpc = 8, 977 .size = { 978 .width = 95, 979 .height = 54, 980 }, 981 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 982 }; 983 984 static const struct drm_display_mode innolux_at070tn92_mode = { 985 .clock = 33333, 986 .hdisplay = 800, 987 .hsync_start = 800 + 210, 988 .hsync_end = 800 + 210 + 20, 989 .htotal = 800 + 210 + 20 + 46, 990 .vdisplay = 480, 991 .vsync_start = 480 + 22, 992 .vsync_end = 480 + 22 + 10, 993 .vtotal = 480 + 22 + 23 + 10, 994 .vrefresh = 60, 995 }; 996 997 static const struct panel_desc innolux_at070tn92 = { 998 .modes = &innolux_at070tn92_mode, 999 .num_modes = 1, 1000 .size = { 1001 .width = 154, 1002 .height = 86, 1003 }, 1004 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1005 }; 1006 1007 static const struct display_timing innolux_g101ice_l01_timing = { 1008 .pixelclock = { 60400000, 71100000, 74700000 }, 1009 .hactive = { 1280, 1280, 1280 }, 1010 .hfront_porch = { 41, 80, 100 }, 1011 .hback_porch = { 40, 79, 99 }, 1012 .hsync_len = { 1, 1, 1 }, 1013 .vactive = { 800, 800, 800 }, 1014 .vfront_porch = { 5, 11, 14 }, 1015 .vback_porch = { 4, 11, 14 }, 1016 .vsync_len = { 1, 1, 1 }, 1017 .flags = DISPLAY_FLAGS_DE_HIGH, 1018 }; 1019 1020 static const struct panel_desc innolux_g101ice_l01 = { 1021 .timings = &innolux_g101ice_l01_timing, 1022 .num_timings = 1, 1023 .bpc = 8, 1024 .size = { 1025 .width = 217, 1026 .height = 135, 1027 }, 1028 .delay = { 1029 .enable = 200, 1030 .disable = 200, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1033 }; 1034 1035 static const struct display_timing innolux_g121i1_l01_timing = { 1036 .pixelclock = { 67450000, 71000000, 74550000 }, 1037 .hactive = { 1280, 1280, 1280 }, 1038 .hfront_porch = { 40, 80, 160 }, 1039 .hback_porch = { 39, 79, 159 }, 1040 .hsync_len = { 1, 1, 1 }, 1041 .vactive = { 800, 800, 800 }, 1042 .vfront_porch = { 5, 11, 100 }, 1043 .vback_porch = { 4, 11, 99 }, 1044 .vsync_len = { 1, 1, 1 }, 1045 }; 1046 1047 static const struct panel_desc innolux_g121i1_l01 = { 1048 .timings = &innolux_g121i1_l01_timing, 1049 .num_timings = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 261, 1053 .height = 163, 1054 }, 1055 .delay = { 1056 .enable = 200, 1057 .disable = 20, 1058 }, 1059 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1060 }; 1061 1062 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1063 .clock = 65000, 1064 .hdisplay = 1024, 1065 .hsync_start = 1024 + 0, 1066 .hsync_end = 1024 + 1, 1067 .htotal = 1024 + 0 + 1 + 320, 1068 .vdisplay = 768, 1069 .vsync_start = 768 + 38, 1070 .vsync_end = 768 + 38 + 1, 1071 .vtotal = 768 + 38 + 1 + 0, 1072 .vrefresh = 60, 1073 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1074 }; 1075 1076 static const struct panel_desc innolux_g121x1_l03 = { 1077 .modes = &innolux_g121x1_l03_mode, 1078 .num_modes = 1, 1079 .bpc = 6, 1080 .size = { 1081 .width = 246, 1082 .height = 185, 1083 }, 1084 .delay = { 1085 .enable = 200, 1086 .unprepare = 200, 1087 .disable = 400, 1088 }, 1089 }; 1090 1091 static const struct drm_display_mode innolux_n116bge_mode = { 1092 .clock = 76420, 1093 .hdisplay = 1366, 1094 .hsync_start = 1366 + 136, 1095 .hsync_end = 1366 + 136 + 30, 1096 .htotal = 1366 + 136 + 30 + 60, 1097 .vdisplay = 768, 1098 .vsync_start = 768 + 8, 1099 .vsync_end = 768 + 8 + 12, 1100 .vtotal = 768 + 8 + 12 + 12, 1101 .vrefresh = 60, 1102 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1103 }; 1104 1105 static const struct panel_desc innolux_n116bge = { 1106 .modes = &innolux_n116bge_mode, 1107 .num_modes = 1, 1108 .bpc = 6, 1109 .size = { 1110 .width = 256, 1111 .height = 144, 1112 }, 1113 }; 1114 1115 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1116 .clock = 69300, 1117 .hdisplay = 1366, 1118 .hsync_start = 1366 + 16, 1119 .hsync_end = 1366 + 16 + 34, 1120 .htotal = 1366 + 16 + 34 + 50, 1121 .vdisplay = 768, 1122 .vsync_start = 768 + 2, 1123 .vsync_end = 768 + 2 + 6, 1124 .vtotal = 768 + 2 + 6 + 12, 1125 .vrefresh = 60, 1126 }; 1127 1128 static const struct panel_desc innolux_n156bge_l21 = { 1129 .modes = &innolux_n156bge_l21_mode, 1130 .num_modes = 1, 1131 .bpc = 6, 1132 .size = { 1133 .width = 344, 1134 .height = 193, 1135 }, 1136 }; 1137 1138 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1139 .clock = 51501, 1140 .hdisplay = 1024, 1141 .hsync_start = 1024 + 128, 1142 .hsync_end = 1024 + 128 + 64, 1143 .htotal = 1024 + 128 + 64 + 128, 1144 .vdisplay = 600, 1145 .vsync_start = 600 + 16, 1146 .vsync_end = 600 + 16 + 4, 1147 .vtotal = 600 + 16 + 4 + 16, 1148 .vrefresh = 60, 1149 }; 1150 1151 static const struct panel_desc innolux_zj070na_01p = { 1152 .modes = &innolux_zj070na_01p_mode, 1153 .num_modes = 1, 1154 .bpc = 6, 1155 .size = { 1156 .width = 154, 1157 .height = 90, 1158 }, 1159 }; 1160 1161 static const struct display_timing kyo_tcg121xglp_timing = { 1162 .pixelclock = { 52000000, 65000000, 71000000 }, 1163 .hactive = { 1024, 1024, 1024 }, 1164 .hfront_porch = { 2, 2, 2 }, 1165 .hback_porch = { 2, 2, 2 }, 1166 .hsync_len = { 86, 124, 244 }, 1167 .vactive = { 768, 768, 768 }, 1168 .vfront_porch = { 2, 2, 2 }, 1169 .vback_porch = { 2, 2, 2 }, 1170 .vsync_len = { 6, 34, 73 }, 1171 .flags = DISPLAY_FLAGS_DE_HIGH, 1172 }; 1173 1174 static const struct panel_desc kyo_tcg121xglp = { 1175 .timings = &kyo_tcg121xglp_timing, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 246, 1180 .height = 184, 1181 }, 1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1183 }; 1184 1185 static const struct drm_display_mode lg_lb070wv8_mode = { 1186 .clock = 33246, 1187 .hdisplay = 800, 1188 .hsync_start = 800 + 88, 1189 .hsync_end = 800 + 88 + 80, 1190 .htotal = 800 + 88 + 80 + 88, 1191 .vdisplay = 480, 1192 .vsync_start = 480 + 10, 1193 .vsync_end = 480 + 10 + 25, 1194 .vtotal = 480 + 10 + 25 + 10, 1195 .vrefresh = 60, 1196 }; 1197 1198 static const struct panel_desc lg_lb070wv8 = { 1199 .modes = &lg_lb070wv8_mode, 1200 .num_modes = 1, 1201 .bpc = 16, 1202 .size = { 1203 .width = 151, 1204 .height = 91, 1205 }, 1206 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1207 }; 1208 1209 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1210 .clock = 200000, 1211 .hdisplay = 1536, 1212 .hsync_start = 1536 + 12, 1213 .hsync_end = 1536 + 12 + 16, 1214 .htotal = 1536 + 12 + 16 + 48, 1215 .vdisplay = 2048, 1216 .vsync_start = 2048 + 8, 1217 .vsync_end = 2048 + 8 + 4, 1218 .vtotal = 2048 + 8 + 4 + 8, 1219 .vrefresh = 60, 1220 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1221 }; 1222 1223 static const struct panel_desc lg_lp079qx1_sp0v = { 1224 .modes = &lg_lp079qx1_sp0v_mode, 1225 .num_modes = 1, 1226 .size = { 1227 .width = 129, 1228 .height = 171, 1229 }, 1230 }; 1231 1232 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1233 .clock = 205210, 1234 .hdisplay = 2048, 1235 .hsync_start = 2048 + 150, 1236 .hsync_end = 2048 + 150 + 5, 1237 .htotal = 2048 + 150 + 5 + 5, 1238 .vdisplay = 1536, 1239 .vsync_start = 1536 + 3, 1240 .vsync_end = 1536 + 3 + 1, 1241 .vtotal = 1536 + 3 + 1 + 9, 1242 .vrefresh = 60, 1243 }; 1244 1245 static const struct panel_desc lg_lp097qx1_spa1 = { 1246 .modes = &lg_lp097qx1_spa1_mode, 1247 .num_modes = 1, 1248 .size = { 1249 .width = 208, 1250 .height = 147, 1251 }, 1252 }; 1253 1254 static const struct drm_display_mode lg_lp120up1_mode = { 1255 .clock = 162300, 1256 .hdisplay = 1920, 1257 .hsync_start = 1920 + 40, 1258 .hsync_end = 1920 + 40 + 40, 1259 .htotal = 1920 + 40 + 40+ 80, 1260 .vdisplay = 1280, 1261 .vsync_start = 1280 + 4, 1262 .vsync_end = 1280 + 4 + 4, 1263 .vtotal = 1280 + 4 + 4 + 12, 1264 .vrefresh = 60, 1265 }; 1266 1267 static const struct panel_desc lg_lp120up1 = { 1268 .modes = &lg_lp120up1_mode, 1269 .num_modes = 1, 1270 .bpc = 8, 1271 .size = { 1272 .width = 267, 1273 .height = 183, 1274 }, 1275 }; 1276 1277 static const struct drm_display_mode lg_lp129qe_mode = { 1278 .clock = 285250, 1279 .hdisplay = 2560, 1280 .hsync_start = 2560 + 48, 1281 .hsync_end = 2560 + 48 + 32, 1282 .htotal = 2560 + 48 + 32 + 80, 1283 .vdisplay = 1700, 1284 .vsync_start = 1700 + 3, 1285 .vsync_end = 1700 + 3 + 10, 1286 .vtotal = 1700 + 3 + 10 + 36, 1287 .vrefresh = 60, 1288 }; 1289 1290 static const struct panel_desc lg_lp129qe = { 1291 .modes = &lg_lp129qe_mode, 1292 .num_modes = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 272, 1296 .height = 181, 1297 }, 1298 }; 1299 1300 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1301 .clock = 10870, 1302 .hdisplay = 480, 1303 .hsync_start = 480 + 2, 1304 .hsync_end = 480 + 2 + 41, 1305 .htotal = 480 + 2 + 41 + 2, 1306 .vdisplay = 272, 1307 .vsync_start = 272 + 2, 1308 .vsync_end = 272 + 2 + 4, 1309 .vtotal = 272 + 2 + 4 + 2, 1310 .vrefresh = 74, 1311 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1312 }; 1313 1314 static const struct panel_desc nec_nl4827hc19_05b = { 1315 .modes = &nec_nl4827hc19_05b_mode, 1316 .num_modes = 1, 1317 .bpc = 8, 1318 .size = { 1319 .width = 95, 1320 .height = 54, 1321 }, 1322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1323 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1324 }; 1325 1326 static const struct drm_display_mode netron_dy_e231732_mode = { 1327 .clock = 66000, 1328 .hdisplay = 1024, 1329 .hsync_start = 1024 + 160, 1330 .hsync_end = 1024 + 160 + 70, 1331 .htotal = 1024 + 160 + 70 + 90, 1332 .vdisplay = 600, 1333 .vsync_start = 600 + 127, 1334 .vsync_end = 600 + 127 + 20, 1335 .vtotal = 600 + 127 + 20 + 3, 1336 .vrefresh = 60, 1337 }; 1338 1339 static const struct panel_desc netron_dy_e231732 = { 1340 .modes = &netron_dy_e231732_mode, 1341 .num_modes = 1, 1342 .size = { 1343 .width = 154, 1344 .height = 87, 1345 }, 1346 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1347 }; 1348 1349 static const struct drm_display_mode nvd_9128_mode = { 1350 .clock = 29500, 1351 .hdisplay = 800, 1352 .hsync_start = 800 + 130, 1353 .hsync_end = 800 + 130 + 98, 1354 .htotal = 800 + 0 + 130 + 98, 1355 .vdisplay = 480, 1356 .vsync_start = 480 + 10, 1357 .vsync_end = 480 + 10 + 50, 1358 .vtotal = 480 + 0 + 10 + 50, 1359 }; 1360 1361 static const struct panel_desc nvd_9128 = { 1362 .modes = &nvd_9128_mode, 1363 .num_modes = 1, 1364 .bpc = 8, 1365 .size = { 1366 .width = 156, 1367 .height = 88, 1368 }, 1369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1370 }; 1371 1372 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1373 .pixelclock = { 30000000, 30000000, 40000000 }, 1374 .hactive = { 800, 800, 800 }, 1375 .hfront_porch = { 40, 40, 40 }, 1376 .hback_porch = { 40, 40, 40 }, 1377 .hsync_len = { 1, 48, 48 }, 1378 .vactive = { 480, 480, 480 }, 1379 .vfront_porch = { 13, 13, 13 }, 1380 .vback_porch = { 29, 29, 29 }, 1381 .vsync_len = { 3, 3, 3 }, 1382 .flags = DISPLAY_FLAGS_DE_HIGH, 1383 }; 1384 1385 static const struct panel_desc okaya_rs800480t_7x0gp = { 1386 .timings = &okaya_rs800480t_7x0gp_timing, 1387 .num_timings = 1, 1388 .bpc = 6, 1389 .size = { 1390 .width = 154, 1391 .height = 87, 1392 }, 1393 .delay = { 1394 .prepare = 41, 1395 .enable = 50, 1396 .unprepare = 41, 1397 .disable = 50, 1398 }, 1399 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1400 }; 1401 1402 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1403 .clock = 9000, 1404 .hdisplay = 480, 1405 .hsync_start = 480 + 5, 1406 .hsync_end = 480 + 5 + 30, 1407 .htotal = 480 + 5 + 30 + 10, 1408 .vdisplay = 272, 1409 .vsync_start = 272 + 8, 1410 .vsync_end = 272 + 8 + 5, 1411 .vtotal = 272 + 8 + 5 + 3, 1412 .vrefresh = 60, 1413 }; 1414 1415 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1416 .modes = &olimex_lcd_olinuxino_43ts_mode, 1417 .num_modes = 1, 1418 .size = { 1419 .width = 105, 1420 .height = 67, 1421 }, 1422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1423 }; 1424 1425 /* 1426 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1427 * pixel clocks, but this is the timing that was being used in the Adafruit 1428 * installation instructions. 1429 */ 1430 static const struct drm_display_mode ontat_yx700wv03_mode = { 1431 .clock = 29500, 1432 .hdisplay = 800, 1433 .hsync_start = 824, 1434 .hsync_end = 896, 1435 .htotal = 992, 1436 .vdisplay = 480, 1437 .vsync_start = 483, 1438 .vsync_end = 493, 1439 .vtotal = 500, 1440 .vrefresh = 60, 1441 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1442 }; 1443 1444 /* 1445 * Specification at: 1446 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1447 */ 1448 static const struct panel_desc ontat_yx700wv03 = { 1449 .modes = &ontat_yx700wv03_mode, 1450 .num_modes = 1, 1451 .bpc = 8, 1452 .size = { 1453 .width = 154, 1454 .height = 83, 1455 }, 1456 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1457 }; 1458 1459 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1460 .clock = 25000, 1461 .hdisplay = 480, 1462 .hsync_start = 480 + 10, 1463 .hsync_end = 480 + 10 + 10, 1464 .htotal = 480 + 10 + 10 + 15, 1465 .vdisplay = 800, 1466 .vsync_start = 800 + 3, 1467 .vsync_end = 800 + 3 + 3, 1468 .vtotal = 800 + 3 + 3 + 3, 1469 .vrefresh = 60, 1470 }; 1471 1472 static const struct panel_desc ortustech_com43h4m85ulc = { 1473 .modes = &ortustech_com43h4m85ulc_mode, 1474 .num_modes = 1, 1475 .bpc = 8, 1476 .size = { 1477 .width = 56, 1478 .height = 93, 1479 }, 1480 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1481 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1482 }; 1483 1484 static const struct drm_display_mode qd43003c0_40_mode = { 1485 .clock = 9000, 1486 .hdisplay = 480, 1487 .hsync_start = 480 + 8, 1488 .hsync_end = 480 + 8 + 4, 1489 .htotal = 480 + 8 + 4 + 39, 1490 .vdisplay = 272, 1491 .vsync_start = 272 + 4, 1492 .vsync_end = 272 + 4 + 10, 1493 .vtotal = 272 + 4 + 10 + 2, 1494 .vrefresh = 60, 1495 }; 1496 1497 static const struct panel_desc qd43003c0_40 = { 1498 .modes = &qd43003c0_40_mode, 1499 .num_modes = 1, 1500 .bpc = 8, 1501 .size = { 1502 .width = 95, 1503 .height = 53, 1504 }, 1505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1506 }; 1507 1508 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1509 .clock = 271560, 1510 .hdisplay = 2560, 1511 .hsync_start = 2560 + 48, 1512 .hsync_end = 2560 + 48 + 32, 1513 .htotal = 2560 + 48 + 32 + 80, 1514 .vdisplay = 1600, 1515 .vsync_start = 1600 + 2, 1516 .vsync_end = 1600 + 2 + 5, 1517 .vtotal = 1600 + 2 + 5 + 57, 1518 .vrefresh = 60, 1519 }; 1520 1521 static const struct panel_desc samsung_lsn122dl01_c01 = { 1522 .modes = &samsung_lsn122dl01_c01_mode, 1523 .num_modes = 1, 1524 .size = { 1525 .width = 263, 1526 .height = 164, 1527 }, 1528 }; 1529 1530 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1531 .clock = 54030, 1532 .hdisplay = 1024, 1533 .hsync_start = 1024 + 24, 1534 .hsync_end = 1024 + 24 + 136, 1535 .htotal = 1024 + 24 + 136 + 160, 1536 .vdisplay = 600, 1537 .vsync_start = 600 + 3, 1538 .vsync_end = 600 + 3 + 6, 1539 .vtotal = 600 + 3 + 6 + 61, 1540 .vrefresh = 60, 1541 }; 1542 1543 static const struct panel_desc samsung_ltn101nt05 = { 1544 .modes = &samsung_ltn101nt05_mode, 1545 .num_modes = 1, 1546 .bpc = 6, 1547 .size = { 1548 .width = 223, 1549 .height = 125, 1550 }, 1551 }; 1552 1553 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1554 .clock = 76300, 1555 .hdisplay = 1366, 1556 .hsync_start = 1366 + 64, 1557 .hsync_end = 1366 + 64 + 48, 1558 .htotal = 1366 + 64 + 48 + 128, 1559 .vdisplay = 768, 1560 .vsync_start = 768 + 2, 1561 .vsync_end = 768 + 2 + 5, 1562 .vtotal = 768 + 2 + 5 + 17, 1563 .vrefresh = 60, 1564 }; 1565 1566 static const struct panel_desc samsung_ltn140at29_301 = { 1567 .modes = &samsung_ltn140at29_301_mode, 1568 .num_modes = 1, 1569 .bpc = 6, 1570 .size = { 1571 .width = 320, 1572 .height = 187, 1573 }, 1574 }; 1575 1576 static const struct display_timing sharp_lq101k1ly04_timing = { 1577 .pixelclock = { 60000000, 65000000, 80000000 }, 1578 .hactive = { 1280, 1280, 1280 }, 1579 .hfront_porch = { 20, 20, 20 }, 1580 .hback_porch = { 20, 20, 20 }, 1581 .hsync_len = { 10, 10, 10 }, 1582 .vactive = { 800, 800, 800 }, 1583 .vfront_porch = { 4, 4, 4 }, 1584 .vback_porch = { 4, 4, 4 }, 1585 .vsync_len = { 4, 4, 4 }, 1586 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1587 }; 1588 1589 static const struct panel_desc sharp_lq101k1ly04 = { 1590 .timings = &sharp_lq101k1ly04_timing, 1591 .num_timings = 1, 1592 .bpc = 8, 1593 .size = { 1594 .width = 217, 1595 .height = 136, 1596 }, 1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1598 }; 1599 1600 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1601 .clock = 252750, 1602 .hdisplay = 2400, 1603 .hsync_start = 2400 + 48, 1604 .hsync_end = 2400 + 48 + 32, 1605 .htotal = 2400 + 48 + 32 + 80, 1606 .vdisplay = 1600, 1607 .vsync_start = 1600 + 3, 1608 .vsync_end = 1600 + 3 + 10, 1609 .vtotal = 1600 + 3 + 10 + 33, 1610 .vrefresh = 60, 1611 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1612 }; 1613 1614 static const struct panel_desc sharp_lq123p1jx31 = { 1615 .modes = &sharp_lq123p1jx31_mode, 1616 .num_modes = 1, 1617 .bpc = 8, 1618 .size = { 1619 .width = 259, 1620 .height = 173, 1621 }, 1622 .delay = { 1623 .prepare = 110, 1624 .enable = 50, 1625 .unprepare = 550, 1626 }, 1627 }; 1628 1629 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 1630 .clock = 71100, 1631 .hdisplay = 1024, 1632 .hsync_start = 1024 + 168, 1633 .hsync_end = 1024 + 168 + 64, 1634 .htotal = 1024 + 168 + 64 + 88, 1635 .vdisplay = 768, 1636 .vsync_start = 768 + 37, 1637 .vsync_end = 768 + 37 + 2, 1638 .vtotal = 768 + 37 + 2 + 8, 1639 .vrefresh = 60, 1640 }; 1641 1642 static const struct panel_desc sharp_lq150x1lg11 = { 1643 .modes = &sharp_lq150x1lg11_mode, 1644 .num_modes = 1, 1645 .bpc = 6, 1646 .size = { 1647 .width = 304, 1648 .height = 228, 1649 }, 1650 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 1651 }; 1652 1653 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1654 .clock = 33300, 1655 .hdisplay = 800, 1656 .hsync_start = 800 + 1, 1657 .hsync_end = 800 + 1 + 64, 1658 .htotal = 800 + 1 + 64 + 64, 1659 .vdisplay = 480, 1660 .vsync_start = 480 + 1, 1661 .vsync_end = 480 + 1 + 23, 1662 .vtotal = 480 + 1 + 23 + 22, 1663 .vrefresh = 60, 1664 }; 1665 1666 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1667 .modes = &shelly_sca07010_bfn_lnn_mode, 1668 .num_modes = 1, 1669 .size = { 1670 .width = 152, 1671 .height = 91, 1672 }, 1673 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1674 }; 1675 1676 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1677 .clock = 147000, 1678 .hdisplay = 1920, 1679 .hsync_start = 1920 + 16, 1680 .hsync_end = 1920 + 16 + 16, 1681 .htotal = 1920 + 16 + 16 + 32, 1682 .vdisplay = 1200, 1683 .vsync_start = 1200 + 15, 1684 .vsync_end = 1200 + 15 + 2, 1685 .vtotal = 1200 + 15 + 2 + 18, 1686 .vrefresh = 60, 1687 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1688 }; 1689 1690 static const struct panel_desc starry_kr122ea0sra = { 1691 .modes = &starry_kr122ea0sra_mode, 1692 .num_modes = 1, 1693 .size = { 1694 .width = 263, 1695 .height = 164, 1696 }, 1697 .delay = { 1698 .prepare = 10 + 200, 1699 .enable = 50, 1700 .unprepare = 10 + 500, 1701 }, 1702 }; 1703 1704 static const struct display_timing tianma_tm070jdhg30_timing = { 1705 .pixelclock = { 62600000, 68200000, 78100000 }, 1706 .hactive = { 1280, 1280, 1280 }, 1707 .hfront_porch = { 15, 64, 159 }, 1708 .hback_porch = { 5, 5, 5 }, 1709 .hsync_len = { 1, 1, 256 }, 1710 .vactive = { 800, 800, 800 }, 1711 .vfront_porch = { 3, 40, 99 }, 1712 .vback_porch = { 2, 2, 2 }, 1713 .vsync_len = { 1, 1, 128 }, 1714 .flags = DISPLAY_FLAGS_DE_HIGH, 1715 }; 1716 1717 static const struct panel_desc tianma_tm070jdhg30 = { 1718 .timings = &tianma_tm070jdhg30_timing, 1719 .num_timings = 1, 1720 .bpc = 8, 1721 .size = { 1722 .width = 151, 1723 .height = 95, 1724 }, 1725 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1726 }; 1727 1728 static const struct drm_display_mode tpk_f07a_0102_mode = { 1729 .clock = 33260, 1730 .hdisplay = 800, 1731 .hsync_start = 800 + 40, 1732 .hsync_end = 800 + 40 + 128, 1733 .htotal = 800 + 40 + 128 + 88, 1734 .vdisplay = 480, 1735 .vsync_start = 480 + 10, 1736 .vsync_end = 480 + 10 + 2, 1737 .vtotal = 480 + 10 + 2 + 33, 1738 .vrefresh = 60, 1739 }; 1740 1741 static const struct panel_desc tpk_f07a_0102 = { 1742 .modes = &tpk_f07a_0102_mode, 1743 .num_modes = 1, 1744 .size = { 1745 .width = 152, 1746 .height = 91, 1747 }, 1748 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1749 }; 1750 1751 static const struct drm_display_mode tpk_f10a_0102_mode = { 1752 .clock = 45000, 1753 .hdisplay = 1024, 1754 .hsync_start = 1024 + 176, 1755 .hsync_end = 1024 + 176 + 5, 1756 .htotal = 1024 + 176 + 5 + 88, 1757 .vdisplay = 600, 1758 .vsync_start = 600 + 20, 1759 .vsync_end = 600 + 20 + 5, 1760 .vtotal = 600 + 20 + 5 + 25, 1761 .vrefresh = 60, 1762 }; 1763 1764 static const struct panel_desc tpk_f10a_0102 = { 1765 .modes = &tpk_f10a_0102_mode, 1766 .num_modes = 1, 1767 .size = { 1768 .width = 223, 1769 .height = 125, 1770 }, 1771 }; 1772 1773 static const struct display_timing urt_umsh_8596md_timing = { 1774 .pixelclock = { 33260000, 33260000, 33260000 }, 1775 .hactive = { 800, 800, 800 }, 1776 .hfront_porch = { 41, 41, 41 }, 1777 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1778 .hsync_len = { 71, 128, 128 }, 1779 .vactive = { 480, 480, 480 }, 1780 .vfront_porch = { 10, 10, 10 }, 1781 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1782 .vsync_len = { 2, 2, 2 }, 1783 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1784 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1785 }; 1786 1787 static const struct panel_desc urt_umsh_8596md_lvds = { 1788 .timings = &urt_umsh_8596md_timing, 1789 .num_timings = 1, 1790 .bpc = 6, 1791 .size = { 1792 .width = 152, 1793 .height = 91, 1794 }, 1795 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1796 }; 1797 1798 static const struct panel_desc urt_umsh_8596md_parallel = { 1799 .timings = &urt_umsh_8596md_timing, 1800 .num_timings = 1, 1801 .bpc = 6, 1802 .size = { 1803 .width = 152, 1804 .height = 91, 1805 }, 1806 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1807 }; 1808 1809 static const struct of_device_id platform_of_match[] = { 1810 { 1811 .compatible = "ampire,am800480r3tmqwa1h", 1812 .data = &ire_am800480r3tmqwa1h, 1813 }, { 1814 .compatible = "auo,b101aw03", 1815 .data = &auo_b101aw03, 1816 }, { 1817 .compatible = "auo,b101ean01", 1818 .data = &auo_b101ean01, 1819 }, { 1820 .compatible = "auo,b101xtn01", 1821 .data = &auo_b101xtn01, 1822 }, { 1823 .compatible = "auo,b116xw03", 1824 .data = &auo_b116xw03, 1825 }, { 1826 .compatible = "auo,b133htn01", 1827 .data = &auo_b133htn01, 1828 }, { 1829 .compatible = "auo,b133xtn01", 1830 .data = &auo_b133xtn01, 1831 }, { 1832 .compatible = "auo,g133han01", 1833 .data = &auo_g133han01, 1834 }, { 1835 .compatible = "auo,g185han01", 1836 .data = &auo_g185han01, 1837 }, { 1838 .compatible = "auo,t215hvn01", 1839 .data = &auo_t215hvn01, 1840 }, { 1841 .compatible = "avic,tm070ddh03", 1842 .data = &avic_tm070ddh03, 1843 }, { 1844 .compatible = "boe,nv101wxmn51", 1845 .data = &boe_nv101wxmn51, 1846 }, { 1847 .compatible = "chunghwa,claa070wp03xg", 1848 .data = &chunghwa_claa070wp03xg, 1849 }, { 1850 .compatible = "chunghwa,claa101wa01a", 1851 .data = &chunghwa_claa101wa01a 1852 }, { 1853 .compatible = "chunghwa,claa101wb01", 1854 .data = &chunghwa_claa101wb01 1855 }, { 1856 .compatible = "edt,et057090dhu", 1857 .data = &edt_et057090dhu, 1858 }, { 1859 .compatible = "edt,et070080dh6", 1860 .data = &edt_etm0700g0dh6, 1861 }, { 1862 .compatible = "edt,etm0700g0dh6", 1863 .data = &edt_etm0700g0dh6, 1864 }, { 1865 .compatible = "foxlink,fl500wvr00-a0t", 1866 .data = &foxlink_fl500wvr00_a0t, 1867 }, { 1868 .compatible = "giantplus,gpg482739qs5", 1869 .data = &giantplus_gpg482739qs5 1870 }, { 1871 .compatible = "hannstar,hsd070pww1", 1872 .data = &hannstar_hsd070pww1, 1873 }, { 1874 .compatible = "hannstar,hsd100pxn1", 1875 .data = &hannstar_hsd100pxn1, 1876 }, { 1877 .compatible = "hit,tx23d38vm0caa", 1878 .data = &hitachi_tx23d38vm0caa 1879 }, { 1880 .compatible = "innolux,at043tn24", 1881 .data = &innolux_at043tn24, 1882 }, { 1883 .compatible = "innolux,at070tn92", 1884 .data = &innolux_at070tn92, 1885 }, { 1886 .compatible ="innolux,g101ice-l01", 1887 .data = &innolux_g101ice_l01 1888 }, { 1889 .compatible ="innolux,g121i1-l01", 1890 .data = &innolux_g121i1_l01 1891 }, { 1892 .compatible = "innolux,g121x1-l03", 1893 .data = &innolux_g121x1_l03, 1894 }, { 1895 .compatible = "innolux,n116bge", 1896 .data = &innolux_n116bge, 1897 }, { 1898 .compatible = "innolux,n156bge-l21", 1899 .data = &innolux_n156bge_l21, 1900 }, { 1901 .compatible = "innolux,zj070na-01p", 1902 .data = &innolux_zj070na_01p, 1903 }, { 1904 .compatible = "kyo,tcg121xglp", 1905 .data = &kyo_tcg121xglp, 1906 }, { 1907 .compatible = "lg,lb070wv8", 1908 .data = &lg_lb070wv8, 1909 }, { 1910 .compatible = "lg,lp079qx1-sp0v", 1911 .data = &lg_lp079qx1_sp0v, 1912 }, { 1913 .compatible = "lg,lp097qx1-spa1", 1914 .data = &lg_lp097qx1_spa1, 1915 }, { 1916 .compatible = "lg,lp120up1", 1917 .data = &lg_lp120up1, 1918 }, { 1919 .compatible = "lg,lp129qe", 1920 .data = &lg_lp129qe, 1921 }, { 1922 .compatible = "nec,nl4827hc19-05b", 1923 .data = &nec_nl4827hc19_05b, 1924 }, { 1925 .compatible = "netron-dy,e231732", 1926 .data = &netron_dy_e231732, 1927 }, { 1928 .compatible = "nvd,9128", 1929 .data = &nvd_9128, 1930 }, { 1931 .compatible = "okaya,rs800480t-7x0gp", 1932 .data = &okaya_rs800480t_7x0gp, 1933 }, { 1934 .compatible = "olimex,lcd-olinuxino-43-ts", 1935 .data = &olimex_lcd_olinuxino_43ts, 1936 }, { 1937 .compatible = "ontat,yx700wv03", 1938 .data = &ontat_yx700wv03, 1939 }, { 1940 .compatible = "ortustech,com43h4m85ulc", 1941 .data = &ortustech_com43h4m85ulc, 1942 }, { 1943 .compatible = "qiaodian,qd43003c0-40", 1944 .data = &qd43003c0_40, 1945 }, { 1946 .compatible = "samsung,lsn122dl01-c01", 1947 .data = &samsung_lsn122dl01_c01, 1948 }, { 1949 .compatible = "samsung,ltn101nt05", 1950 .data = &samsung_ltn101nt05, 1951 }, { 1952 .compatible = "samsung,ltn140at29-301", 1953 .data = &samsung_ltn140at29_301, 1954 }, { 1955 .compatible = "sharp,lq101k1ly04", 1956 .data = &sharp_lq101k1ly04, 1957 }, { 1958 .compatible = "sharp,lq123p1jx31", 1959 .data = &sharp_lq123p1jx31, 1960 }, { 1961 .compatible = "sharp,lq150x1lg11", 1962 .data = &sharp_lq150x1lg11, 1963 }, { 1964 .compatible = "shelly,sca07010-bfn-lnn", 1965 .data = &shelly_sca07010_bfn_lnn, 1966 }, { 1967 .compatible = "starry,kr122ea0sra", 1968 .data = &starry_kr122ea0sra, 1969 }, { 1970 .compatible = "tianma,tm070jdhg30", 1971 .data = &tianma_tm070jdhg30, 1972 }, { 1973 .compatible = "tpk,f07a-0102", 1974 .data = &tpk_f07a_0102, 1975 }, { 1976 .compatible = "tpk,f10a-0102", 1977 .data = &tpk_f10a_0102, 1978 }, { 1979 .compatible = "urt,umsh-8596md-t", 1980 .data = &urt_umsh_8596md_parallel, 1981 }, { 1982 .compatible = "urt,umsh-8596md-1t", 1983 .data = &urt_umsh_8596md_parallel, 1984 }, { 1985 .compatible = "urt,umsh-8596md-7t", 1986 .data = &urt_umsh_8596md_parallel, 1987 }, { 1988 .compatible = "urt,umsh-8596md-11t", 1989 .data = &urt_umsh_8596md_lvds, 1990 }, { 1991 .compatible = "urt,umsh-8596md-19t", 1992 .data = &urt_umsh_8596md_lvds, 1993 }, { 1994 .compatible = "urt,umsh-8596md-20t", 1995 .data = &urt_umsh_8596md_parallel, 1996 }, { 1997 /* sentinel */ 1998 } 1999 }; 2000 MODULE_DEVICE_TABLE(of, platform_of_match); 2001 2002 static int panel_simple_platform_probe(struct platform_device *pdev) 2003 { 2004 const struct of_device_id *id; 2005 2006 id = of_match_node(platform_of_match, pdev->dev.of_node); 2007 if (!id) 2008 return -ENODEV; 2009 2010 return panel_simple_probe(&pdev->dev, id->data); 2011 } 2012 2013 static int panel_simple_platform_remove(struct platform_device *pdev) 2014 { 2015 return panel_simple_remove(&pdev->dev); 2016 } 2017 2018 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2019 { 2020 panel_simple_shutdown(&pdev->dev); 2021 } 2022 2023 static struct platform_driver panel_simple_platform_driver = { 2024 .driver = { 2025 .name = "panel-simple", 2026 .of_match_table = platform_of_match, 2027 }, 2028 .probe = panel_simple_platform_probe, 2029 .remove = panel_simple_platform_remove, 2030 .shutdown = panel_simple_platform_shutdown, 2031 }; 2032 2033 struct panel_desc_dsi { 2034 struct panel_desc desc; 2035 2036 unsigned long flags; 2037 enum mipi_dsi_pixel_format format; 2038 unsigned int lanes; 2039 }; 2040 2041 static const struct drm_display_mode auo_b080uan01_mode = { 2042 .clock = 154500, 2043 .hdisplay = 1200, 2044 .hsync_start = 1200 + 62, 2045 .hsync_end = 1200 + 62 + 4, 2046 .htotal = 1200 + 62 + 4 + 62, 2047 .vdisplay = 1920, 2048 .vsync_start = 1920 + 9, 2049 .vsync_end = 1920 + 9 + 2, 2050 .vtotal = 1920 + 9 + 2 + 8, 2051 .vrefresh = 60, 2052 }; 2053 2054 static const struct panel_desc_dsi auo_b080uan01 = { 2055 .desc = { 2056 .modes = &auo_b080uan01_mode, 2057 .num_modes = 1, 2058 .bpc = 8, 2059 .size = { 2060 .width = 108, 2061 .height = 272, 2062 }, 2063 }, 2064 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2065 .format = MIPI_DSI_FMT_RGB888, 2066 .lanes = 4, 2067 }; 2068 2069 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2070 .clock = 160000, 2071 .hdisplay = 1200, 2072 .hsync_start = 1200 + 120, 2073 .hsync_end = 1200 + 120 + 20, 2074 .htotal = 1200 + 120 + 20 + 21, 2075 .vdisplay = 1920, 2076 .vsync_start = 1920 + 21, 2077 .vsync_end = 1920 + 21 + 3, 2078 .vtotal = 1920 + 21 + 3 + 18, 2079 .vrefresh = 60, 2080 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2081 }; 2082 2083 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2084 .desc = { 2085 .modes = &boe_tv080wum_nl0_mode, 2086 .num_modes = 1, 2087 .size = { 2088 .width = 107, 2089 .height = 172, 2090 }, 2091 }, 2092 .flags = MIPI_DSI_MODE_VIDEO | 2093 MIPI_DSI_MODE_VIDEO_BURST | 2094 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2095 .format = MIPI_DSI_FMT_RGB888, 2096 .lanes = 4, 2097 }; 2098 2099 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2100 .clock = 71000, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 32, 2103 .hsync_end = 800 + 32 + 1, 2104 .htotal = 800 + 32 + 1 + 57, 2105 .vdisplay = 1280, 2106 .vsync_start = 1280 + 28, 2107 .vsync_end = 1280 + 28 + 1, 2108 .vtotal = 1280 + 28 + 1 + 14, 2109 .vrefresh = 60, 2110 }; 2111 2112 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2113 .desc = { 2114 .modes = &lg_ld070wx3_sl01_mode, 2115 .num_modes = 1, 2116 .bpc = 8, 2117 .size = { 2118 .width = 94, 2119 .height = 151, 2120 }, 2121 }, 2122 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2123 .format = MIPI_DSI_FMT_RGB888, 2124 .lanes = 4, 2125 }; 2126 2127 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2128 .clock = 67000, 2129 .hdisplay = 720, 2130 .hsync_start = 720 + 12, 2131 .hsync_end = 720 + 12 + 4, 2132 .htotal = 720 + 12 + 4 + 112, 2133 .vdisplay = 1280, 2134 .vsync_start = 1280 + 8, 2135 .vsync_end = 1280 + 8 + 4, 2136 .vtotal = 1280 + 8 + 4 + 12, 2137 .vrefresh = 60, 2138 }; 2139 2140 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2141 .desc = { 2142 .modes = &lg_lh500wx1_sd03_mode, 2143 .num_modes = 1, 2144 .bpc = 8, 2145 .size = { 2146 .width = 62, 2147 .height = 110, 2148 }, 2149 }, 2150 .flags = MIPI_DSI_MODE_VIDEO, 2151 .format = MIPI_DSI_FMT_RGB888, 2152 .lanes = 4, 2153 }; 2154 2155 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2156 .clock = 157200, 2157 .hdisplay = 1920, 2158 .hsync_start = 1920 + 154, 2159 .hsync_end = 1920 + 154 + 16, 2160 .htotal = 1920 + 154 + 16 + 32, 2161 .vdisplay = 1200, 2162 .vsync_start = 1200 + 17, 2163 .vsync_end = 1200 + 17 + 2, 2164 .vtotal = 1200 + 17 + 2 + 16, 2165 .vrefresh = 60, 2166 }; 2167 2168 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2169 .desc = { 2170 .modes = &panasonic_vvx10f004b00_mode, 2171 .num_modes = 1, 2172 .bpc = 8, 2173 .size = { 2174 .width = 217, 2175 .height = 136, 2176 }, 2177 }, 2178 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2179 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2180 .format = MIPI_DSI_FMT_RGB888, 2181 .lanes = 4, 2182 }; 2183 2184 static const struct of_device_id dsi_of_match[] = { 2185 { 2186 .compatible = "auo,b080uan01", 2187 .data = &auo_b080uan01 2188 }, { 2189 .compatible = "boe,tv080wum-nl0", 2190 .data = &boe_tv080wum_nl0 2191 }, { 2192 .compatible = "lg,ld070wx3-sl01", 2193 .data = &lg_ld070wx3_sl01 2194 }, { 2195 .compatible = "lg,lh500wx1-sd03", 2196 .data = &lg_lh500wx1_sd03 2197 }, { 2198 .compatible = "panasonic,vvx10f004b00", 2199 .data = &panasonic_vvx10f004b00 2200 }, { 2201 /* sentinel */ 2202 } 2203 }; 2204 MODULE_DEVICE_TABLE(of, dsi_of_match); 2205 2206 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2207 { 2208 const struct panel_desc_dsi *desc; 2209 const struct of_device_id *id; 2210 int err; 2211 2212 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2213 if (!id) 2214 return -ENODEV; 2215 2216 desc = id->data; 2217 2218 err = panel_simple_probe(&dsi->dev, &desc->desc); 2219 if (err < 0) 2220 return err; 2221 2222 dsi->mode_flags = desc->flags; 2223 dsi->format = desc->format; 2224 dsi->lanes = desc->lanes; 2225 2226 return mipi_dsi_attach(dsi); 2227 } 2228 2229 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2230 { 2231 int err; 2232 2233 err = mipi_dsi_detach(dsi); 2234 if (err < 0) 2235 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2236 2237 return panel_simple_remove(&dsi->dev); 2238 } 2239 2240 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2241 { 2242 panel_simple_shutdown(&dsi->dev); 2243 } 2244 2245 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2246 .driver = { 2247 .name = "panel-simple-dsi", 2248 .of_match_table = dsi_of_match, 2249 }, 2250 .probe = panel_simple_dsi_probe, 2251 .remove = panel_simple_dsi_remove, 2252 .shutdown = panel_simple_dsi_shutdown, 2253 }; 2254 2255 static int __init panel_simple_init(void) 2256 { 2257 int err; 2258 2259 err = platform_driver_register(&panel_simple_platform_driver); 2260 if (err < 0) 2261 return err; 2262 2263 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2264 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2265 if (err < 0) 2266 return err; 2267 } 2268 2269 return 0; 2270 } 2271 module_init(panel_simple_init); 2272 2273 static void __exit panel_simple_exit(void) 2274 { 2275 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2276 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2277 2278 platform_driver_unregister(&panel_simple_platform_driver); 2279 } 2280 module_exit(panel_simple_exit); 2281 2282 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2283 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2284 MODULE_LICENSE("GPL and additional rights"); 2285