1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 116 enum drm_panel_orientation orientation; 117 }; 118 119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 120 { 121 return container_of(panel, struct panel_simple, base); 122 } 123 124 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 125 struct drm_connector *connector) 126 { 127 struct drm_display_mode *mode; 128 unsigned int i, num = 0; 129 130 for (i = 0; i < panel->desc->num_timings; i++) { 131 const struct display_timing *dt = &panel->desc->timings[i]; 132 struct videomode vm; 133 134 videomode_from_timing(dt, &vm); 135 mode = drm_mode_create(connector->dev); 136 if (!mode) { 137 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 138 dt->hactive.typ, dt->vactive.typ); 139 continue; 140 } 141 142 drm_display_mode_from_videomode(&vm, mode); 143 144 mode->type |= DRM_MODE_TYPE_DRIVER; 145 146 if (panel->desc->num_timings == 1) 147 mode->type |= DRM_MODE_TYPE_PREFERRED; 148 149 drm_mode_probed_add(connector, mode); 150 num++; 151 } 152 153 return num; 154 } 155 156 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 157 struct drm_connector *connector) 158 { 159 struct drm_display_mode *mode; 160 unsigned int i, num = 0; 161 162 for (i = 0; i < panel->desc->num_modes; i++) { 163 const struct drm_display_mode *m = &panel->desc->modes[i]; 164 165 mode = drm_mode_duplicate(connector->dev, m); 166 if (!mode) { 167 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 168 m->hdisplay, m->vdisplay, 169 drm_mode_vrefresh(m)); 170 continue; 171 } 172 173 mode->type |= DRM_MODE_TYPE_DRIVER; 174 175 if (panel->desc->num_modes == 1) 176 mode->type |= DRM_MODE_TYPE_PREFERRED; 177 178 drm_mode_set_name(mode); 179 180 drm_mode_probed_add(connector, mode); 181 num++; 182 } 183 184 return num; 185 } 186 187 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 188 struct drm_connector *connector) 189 { 190 struct drm_display_mode *mode; 191 bool has_override = panel->override_mode.type; 192 unsigned int num = 0; 193 194 if (!panel->desc) 195 return 0; 196 197 if (has_override) { 198 mode = drm_mode_duplicate(connector->dev, 199 &panel->override_mode); 200 if (mode) { 201 drm_mode_probed_add(connector, mode); 202 num = 1; 203 } else { 204 dev_err(panel->base.dev, "failed to add override mode\n"); 205 } 206 } 207 208 /* Only add timings if override was not there or failed to validate */ 209 if (num == 0 && panel->desc->num_timings) 210 num = panel_simple_get_timings_modes(panel, connector); 211 212 /* 213 * Only add fixed modes if timings/override added no mode. 214 * 215 * We should only ever have either the display timings specified 216 * or a fixed mode. Anything else is rather bogus. 217 */ 218 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 219 if (num == 0) 220 num = panel_simple_get_display_modes(panel, connector); 221 222 connector->display_info.bpc = panel->desc->bpc; 223 connector->display_info.width_mm = panel->desc->size.width; 224 connector->display_info.height_mm = panel->desc->size.height; 225 if (panel->desc->bus_format) 226 drm_display_info_set_bus_formats(&connector->display_info, 227 &panel->desc->bus_format, 1); 228 connector->display_info.bus_flags = panel->desc->bus_flags; 229 230 return num; 231 } 232 233 static int panel_simple_disable(struct drm_panel *panel) 234 { 235 struct panel_simple *p = to_panel_simple(panel); 236 237 if (!p->enabled) 238 return 0; 239 240 if (p->desc->delay.disable) 241 msleep(p->desc->delay.disable); 242 243 p->enabled = false; 244 245 return 0; 246 } 247 248 static int panel_simple_unprepare(struct drm_panel *panel) 249 { 250 struct panel_simple *p = to_panel_simple(panel); 251 252 if (!p->prepared) 253 return 0; 254 255 gpiod_set_value_cansleep(p->enable_gpio, 0); 256 257 regulator_disable(p->supply); 258 259 if (p->desc->delay.unprepare) 260 msleep(p->desc->delay.unprepare); 261 262 p->prepared = false; 263 264 return 0; 265 } 266 267 static int panel_simple_get_hpd_gpio(struct device *dev, 268 struct panel_simple *p, bool from_probe) 269 { 270 int err; 271 272 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 273 if (IS_ERR(p->hpd_gpio)) { 274 err = PTR_ERR(p->hpd_gpio); 275 276 /* 277 * If we're called from probe we won't consider '-EPROBE_DEFER' 278 * to be an error--we'll leave the error code in "hpd_gpio". 279 * When we try to use it we'll try again. This allows for 280 * circular dependencies where the component providing the 281 * hpd gpio needs the panel to init before probing. 282 */ 283 if (err != -EPROBE_DEFER || !from_probe) { 284 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 285 return err; 286 } 287 } 288 289 return 0; 290 } 291 292 static int panel_simple_prepare(struct drm_panel *panel) 293 { 294 struct panel_simple *p = to_panel_simple(panel); 295 unsigned int delay; 296 int err; 297 int hpd_asserted; 298 299 if (p->prepared) 300 return 0; 301 302 err = regulator_enable(p->supply); 303 if (err < 0) { 304 dev_err(panel->dev, "failed to enable supply: %d\n", err); 305 return err; 306 } 307 308 gpiod_set_value_cansleep(p->enable_gpio, 1); 309 310 delay = p->desc->delay.prepare; 311 if (p->no_hpd) 312 delay += p->desc->delay.hpd_absent_delay; 313 if (delay) 314 msleep(delay); 315 316 if (p->hpd_gpio) { 317 if (IS_ERR(p->hpd_gpio)) { 318 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 319 if (err) 320 return err; 321 } 322 323 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 324 hpd_asserted, hpd_asserted, 325 1000, 2000000); 326 if (hpd_asserted < 0) 327 err = hpd_asserted; 328 329 if (err) { 330 dev_err(panel->dev, 331 "error waiting for hpd GPIO: %d\n", err); 332 return err; 333 } 334 } 335 336 p->prepared = true; 337 338 return 0; 339 } 340 341 static int panel_simple_enable(struct drm_panel *panel) 342 { 343 struct panel_simple *p = to_panel_simple(panel); 344 345 if (p->enabled) 346 return 0; 347 348 if (p->desc->delay.enable) 349 msleep(p->desc->delay.enable); 350 351 p->enabled = true; 352 353 return 0; 354 } 355 356 static int panel_simple_get_modes(struct drm_panel *panel, 357 struct drm_connector *connector) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int num = 0; 361 362 /* probe EDID if a DDC bus is available */ 363 if (p->ddc) { 364 struct edid *edid = drm_get_edid(connector, p->ddc); 365 366 drm_connector_update_edid_property(connector, edid); 367 if (edid) { 368 num += drm_add_edid_modes(connector, edid); 369 kfree(edid); 370 } 371 } 372 373 /* add hard-coded panel modes */ 374 num += panel_simple_get_non_edid_modes(p, connector); 375 376 /* set up connector's "panel orientation" property */ 377 drm_connector_set_panel_orientation(connector, p->orientation); 378 379 return num; 380 } 381 382 static int panel_simple_get_timings(struct drm_panel *panel, 383 unsigned int num_timings, 384 struct display_timing *timings) 385 { 386 struct panel_simple *p = to_panel_simple(panel); 387 unsigned int i; 388 389 if (p->desc->num_timings < num_timings) 390 num_timings = p->desc->num_timings; 391 392 if (timings) 393 for (i = 0; i < num_timings; i++) 394 timings[i] = p->desc->timings[i]; 395 396 return p->desc->num_timings; 397 } 398 399 static const struct drm_panel_funcs panel_simple_funcs = { 400 .disable = panel_simple_disable, 401 .unprepare = panel_simple_unprepare, 402 .prepare = panel_simple_prepare, 403 .enable = panel_simple_enable, 404 .get_modes = panel_simple_get_modes, 405 .get_timings = panel_simple_get_timings, 406 }; 407 408 static struct panel_desc panel_dpi; 409 410 static int panel_dpi_probe(struct device *dev, 411 struct panel_simple *panel) 412 { 413 struct display_timing *timing; 414 const struct device_node *np; 415 struct panel_desc *desc; 416 unsigned int bus_flags; 417 struct videomode vm; 418 int ret; 419 420 np = dev->of_node; 421 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 422 if (!desc) 423 return -ENOMEM; 424 425 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 426 if (!timing) 427 return -ENOMEM; 428 429 ret = of_get_display_timing(np, "panel-timing", timing); 430 if (ret < 0) { 431 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 432 np); 433 return ret; 434 } 435 436 desc->timings = timing; 437 desc->num_timings = 1; 438 439 of_property_read_u32(np, "width-mm", &desc->size.width); 440 of_property_read_u32(np, "height-mm", &desc->size.height); 441 442 /* Extract bus_flags from display_timing */ 443 bus_flags = 0; 444 vm.flags = timing->flags; 445 drm_bus_flags_from_videomode(&vm, &bus_flags); 446 desc->bus_flags = bus_flags; 447 448 /* We do not know the connector for the DT node, so guess it */ 449 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 450 451 panel->desc = desc; 452 453 return 0; 454 } 455 456 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 457 (to_check->field.typ >= bounds->field.min && \ 458 to_check->field.typ <= bounds->field.max) 459 static void panel_simple_parse_panel_timing_node(struct device *dev, 460 struct panel_simple *panel, 461 const struct display_timing *ot) 462 { 463 const struct panel_desc *desc = panel->desc; 464 struct videomode vm; 465 unsigned int i; 466 467 if (WARN_ON(desc->num_modes)) { 468 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 469 return; 470 } 471 if (WARN_ON(!desc->num_timings)) { 472 dev_err(dev, "Reject override mode: no timings specified\n"); 473 return; 474 } 475 476 for (i = 0; i < panel->desc->num_timings; i++) { 477 const struct display_timing *dt = &panel->desc->timings[i]; 478 479 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 487 continue; 488 489 if (ot->flags != dt->flags) 490 continue; 491 492 videomode_from_timing(ot, &vm); 493 drm_display_mode_from_videomode(&vm, &panel->override_mode); 494 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 495 DRM_MODE_TYPE_PREFERRED; 496 break; 497 } 498 499 if (WARN_ON(!panel->override_mode.type)) 500 dev_err(dev, "Reject override mode: No display_timing found\n"); 501 } 502 503 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 504 { 505 struct panel_simple *panel; 506 struct display_timing dt; 507 struct device_node *ddc; 508 int connector_type; 509 u32 bus_flags; 510 int err; 511 512 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 513 if (!panel) 514 return -ENOMEM; 515 516 panel->enabled = false; 517 panel->prepared = false; 518 panel->desc = desc; 519 520 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 521 if (!panel->no_hpd) { 522 err = panel_simple_get_hpd_gpio(dev, panel, true); 523 if (err) 524 return err; 525 } 526 527 panel->supply = devm_regulator_get(dev, "power"); 528 if (IS_ERR(panel->supply)) 529 return PTR_ERR(panel->supply); 530 531 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 532 GPIOD_OUT_LOW); 533 if (IS_ERR(panel->enable_gpio)) { 534 err = PTR_ERR(panel->enable_gpio); 535 if (err != -EPROBE_DEFER) 536 dev_err(dev, "failed to request GPIO: %d\n", err); 537 return err; 538 } 539 540 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 541 if (err) { 542 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 543 return err; 544 } 545 546 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 547 if (ddc) { 548 panel->ddc = of_find_i2c_adapter_by_node(ddc); 549 of_node_put(ddc); 550 551 if (!panel->ddc) 552 return -EPROBE_DEFER; 553 } 554 555 if (desc == &panel_dpi) { 556 /* Handle the generic panel-dpi binding */ 557 err = panel_dpi_probe(dev, panel); 558 if (err) 559 goto free_ddc; 560 } else { 561 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 562 panel_simple_parse_panel_timing_node(dev, panel, &dt); 563 } 564 565 connector_type = desc->connector_type; 566 /* Catch common mistakes for panels. */ 567 switch (connector_type) { 568 case 0: 569 dev_warn(dev, "Specify missing connector_type\n"); 570 connector_type = DRM_MODE_CONNECTOR_DPI; 571 break; 572 case DRM_MODE_CONNECTOR_LVDS: 573 WARN_ON(desc->bus_flags & 574 ~(DRM_BUS_FLAG_DE_LOW | 575 DRM_BUS_FLAG_DE_HIGH | 576 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 577 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 578 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 579 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 580 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 581 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 582 desc->bpc != 6); 583 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 584 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 585 desc->bpc != 8); 586 break; 587 case DRM_MODE_CONNECTOR_eDP: 588 if (desc->bus_format == 0) 589 dev_warn(dev, "Specify missing bus_format\n"); 590 if (desc->bpc != 6 && desc->bpc != 8) 591 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 592 break; 593 case DRM_MODE_CONNECTOR_DSI: 594 if (desc->bpc != 6 && desc->bpc != 8) 595 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 596 break; 597 case DRM_MODE_CONNECTOR_DPI: 598 bus_flags = DRM_BUS_FLAG_DE_LOW | 599 DRM_BUS_FLAG_DE_HIGH | 600 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 601 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 602 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 603 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 604 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 606 if (desc->bus_flags & ~bus_flags) 607 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 608 if (!(desc->bus_flags & bus_flags)) 609 dev_warn(dev, "Specify missing bus_flags\n"); 610 if (desc->bus_format == 0) 611 dev_warn(dev, "Specify missing bus_format\n"); 612 if (desc->bpc != 6 && desc->bpc != 8) 613 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 614 break; 615 default: 616 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 617 connector_type = DRM_MODE_CONNECTOR_DPI; 618 break; 619 } 620 621 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 622 623 err = drm_panel_of_backlight(&panel->base); 624 if (err) 625 goto free_ddc; 626 627 drm_panel_add(&panel->base); 628 629 dev_set_drvdata(dev, panel); 630 631 return 0; 632 633 free_ddc: 634 if (panel->ddc) 635 put_device(&panel->ddc->dev); 636 637 return err; 638 } 639 640 static int panel_simple_remove(struct device *dev) 641 { 642 struct panel_simple *panel = dev_get_drvdata(dev); 643 644 drm_panel_remove(&panel->base); 645 drm_panel_disable(&panel->base); 646 drm_panel_unprepare(&panel->base); 647 648 if (panel->ddc) 649 put_device(&panel->ddc->dev); 650 651 return 0; 652 } 653 654 static void panel_simple_shutdown(struct device *dev) 655 { 656 struct panel_simple *panel = dev_get_drvdata(dev); 657 658 drm_panel_disable(&panel->base); 659 drm_panel_unprepare(&panel->base); 660 } 661 662 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 663 .clock = 71100, 664 .hdisplay = 1280, 665 .hsync_start = 1280 + 40, 666 .hsync_end = 1280 + 40 + 80, 667 .htotal = 1280 + 40 + 80 + 40, 668 .vdisplay = 800, 669 .vsync_start = 800 + 3, 670 .vsync_end = 800 + 3 + 10, 671 .vtotal = 800 + 3 + 10 + 10, 672 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 673 }; 674 675 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 676 .modes = &ire_am_1280800n3tzqw_t00h_mode, 677 .num_modes = 1, 678 .bpc = 6, 679 .size = { 680 .width = 217, 681 .height = 136, 682 }, 683 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 685 .connector_type = DRM_MODE_CONNECTOR_LVDS, 686 }; 687 688 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 689 .clock = 9000, 690 .hdisplay = 480, 691 .hsync_start = 480 + 2, 692 .hsync_end = 480 + 2 + 41, 693 .htotal = 480 + 2 + 41 + 2, 694 .vdisplay = 272, 695 .vsync_start = 272 + 2, 696 .vsync_end = 272 + 2 + 10, 697 .vtotal = 272 + 2 + 10 + 2, 698 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 699 }; 700 701 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 702 .modes = &ire_am_480272h3tmqw_t01h_mode, 703 .num_modes = 1, 704 .bpc = 8, 705 .size = { 706 .width = 105, 707 .height = 67, 708 }, 709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 710 }; 711 712 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 713 .clock = 33333, 714 .hdisplay = 800, 715 .hsync_start = 800 + 0, 716 .hsync_end = 800 + 0 + 255, 717 .htotal = 800 + 0 + 255 + 0, 718 .vdisplay = 480, 719 .vsync_start = 480 + 2, 720 .vsync_end = 480 + 2 + 45, 721 .vtotal = 480 + 2 + 45 + 0, 722 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 723 }; 724 725 static const struct panel_desc ampire_am800480r3tmqwa1h = { 726 .modes = &ire_am800480r3tmqwa1h_mode, 727 .num_modes = 1, 728 .bpc = 6, 729 .size = { 730 .width = 152, 731 .height = 91, 732 }, 733 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 734 }; 735 736 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 737 .pixelclock = { 26400000, 33300000, 46800000 }, 738 .hactive = { 800, 800, 800 }, 739 .hfront_porch = { 16, 210, 354 }, 740 .hback_porch = { 45, 36, 6 }, 741 .hsync_len = { 1, 10, 40 }, 742 .vactive = { 480, 480, 480 }, 743 .vfront_porch = { 7, 22, 147 }, 744 .vback_porch = { 22, 13, 3 }, 745 .vsync_len = { 1, 10, 20 }, 746 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 747 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 748 }; 749 750 static const struct panel_desc armadeus_st0700_adapt = { 751 .timings = &santek_st0700i5y_rbslw_f_timing, 752 .num_timings = 1, 753 .bpc = 6, 754 .size = { 755 .width = 154, 756 .height = 86, 757 }, 758 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 759 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 760 }; 761 762 static const struct drm_display_mode auo_b101aw03_mode = { 763 .clock = 51450, 764 .hdisplay = 1024, 765 .hsync_start = 1024 + 156, 766 .hsync_end = 1024 + 156 + 8, 767 .htotal = 1024 + 156 + 8 + 156, 768 .vdisplay = 600, 769 .vsync_start = 600 + 16, 770 .vsync_end = 600 + 16 + 6, 771 .vtotal = 600 + 16 + 6 + 16, 772 }; 773 774 static const struct panel_desc auo_b101aw03 = { 775 .modes = &auo_b101aw03_mode, 776 .num_modes = 1, 777 .bpc = 6, 778 .size = { 779 .width = 223, 780 .height = 125, 781 }, 782 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 783 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 785 }; 786 787 static const struct display_timing auo_b101ean01_timing = { 788 .pixelclock = { 65300000, 72500000, 75000000 }, 789 .hactive = { 1280, 1280, 1280 }, 790 .hfront_porch = { 18, 119, 119 }, 791 .hback_porch = { 21, 21, 21 }, 792 .hsync_len = { 32, 32, 32 }, 793 .vactive = { 800, 800, 800 }, 794 .vfront_porch = { 4, 4, 4 }, 795 .vback_porch = { 8, 8, 8 }, 796 .vsync_len = { 18, 20, 20 }, 797 }; 798 799 static const struct panel_desc auo_b101ean01 = { 800 .timings = &auo_b101ean01_timing, 801 .num_timings = 1, 802 .bpc = 6, 803 .size = { 804 .width = 217, 805 .height = 136, 806 }, 807 }; 808 809 static const struct drm_display_mode auo_b101xtn01_mode = { 810 .clock = 72000, 811 .hdisplay = 1366, 812 .hsync_start = 1366 + 20, 813 .hsync_end = 1366 + 20 + 70, 814 .htotal = 1366 + 20 + 70, 815 .vdisplay = 768, 816 .vsync_start = 768 + 14, 817 .vsync_end = 768 + 14 + 42, 818 .vtotal = 768 + 14 + 42, 819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 820 }; 821 822 static const struct panel_desc auo_b101xtn01 = { 823 .modes = &auo_b101xtn01_mode, 824 .num_modes = 1, 825 .bpc = 6, 826 .size = { 827 .width = 223, 828 .height = 125, 829 }, 830 }; 831 832 static const struct drm_display_mode auo_b116xak01_mode = { 833 .clock = 69300, 834 .hdisplay = 1366, 835 .hsync_start = 1366 + 48, 836 .hsync_end = 1366 + 48 + 32, 837 .htotal = 1366 + 48 + 32 + 10, 838 .vdisplay = 768, 839 .vsync_start = 768 + 4, 840 .vsync_end = 768 + 4 + 6, 841 .vtotal = 768 + 4 + 6 + 15, 842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 843 }; 844 845 static const struct panel_desc auo_b116xak01 = { 846 .modes = &auo_b116xak01_mode, 847 .num_modes = 1, 848 .bpc = 6, 849 .size = { 850 .width = 256, 851 .height = 144, 852 }, 853 .delay = { 854 .hpd_absent_delay = 200, 855 }, 856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 857 .connector_type = DRM_MODE_CONNECTOR_eDP, 858 }; 859 860 static const struct drm_display_mode auo_b116xw03_mode = { 861 .clock = 70589, 862 .hdisplay = 1366, 863 .hsync_start = 1366 + 40, 864 .hsync_end = 1366 + 40 + 40, 865 .htotal = 1366 + 40 + 40 + 32, 866 .vdisplay = 768, 867 .vsync_start = 768 + 10, 868 .vsync_end = 768 + 10 + 12, 869 .vtotal = 768 + 10 + 12 + 6, 870 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 871 }; 872 873 static const struct panel_desc auo_b116xw03 = { 874 .modes = &auo_b116xw03_mode, 875 .num_modes = 1, 876 .bpc = 6, 877 .size = { 878 .width = 256, 879 .height = 144, 880 }, 881 .delay = { 882 .enable = 400, 883 }, 884 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 885 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 886 .connector_type = DRM_MODE_CONNECTOR_eDP, 887 }; 888 889 static const struct drm_display_mode auo_b133xtn01_mode = { 890 .clock = 69500, 891 .hdisplay = 1366, 892 .hsync_start = 1366 + 48, 893 .hsync_end = 1366 + 48 + 32, 894 .htotal = 1366 + 48 + 32 + 20, 895 .vdisplay = 768, 896 .vsync_start = 768 + 3, 897 .vsync_end = 768 + 3 + 6, 898 .vtotal = 768 + 3 + 6 + 13, 899 }; 900 901 static const struct panel_desc auo_b133xtn01 = { 902 .modes = &auo_b133xtn01_mode, 903 .num_modes = 1, 904 .bpc = 6, 905 .size = { 906 .width = 293, 907 .height = 165, 908 }, 909 }; 910 911 static const struct drm_display_mode auo_b133htn01_mode = { 912 .clock = 150660, 913 .hdisplay = 1920, 914 .hsync_start = 1920 + 172, 915 .hsync_end = 1920 + 172 + 80, 916 .htotal = 1920 + 172 + 80 + 60, 917 .vdisplay = 1080, 918 .vsync_start = 1080 + 25, 919 .vsync_end = 1080 + 25 + 10, 920 .vtotal = 1080 + 25 + 10 + 10, 921 }; 922 923 static const struct panel_desc auo_b133htn01 = { 924 .modes = &auo_b133htn01_mode, 925 .num_modes = 1, 926 .bpc = 6, 927 .size = { 928 .width = 293, 929 .height = 165, 930 }, 931 .delay = { 932 .prepare = 105, 933 .enable = 20, 934 .unprepare = 50, 935 }, 936 }; 937 938 static const struct display_timing auo_g070vvn01_timings = { 939 .pixelclock = { 33300000, 34209000, 45000000 }, 940 .hactive = { 800, 800, 800 }, 941 .hfront_porch = { 20, 40, 200 }, 942 .hback_porch = { 87, 40, 1 }, 943 .hsync_len = { 1, 48, 87 }, 944 .vactive = { 480, 480, 480 }, 945 .vfront_porch = { 5, 13, 200 }, 946 .vback_porch = { 31, 31, 29 }, 947 .vsync_len = { 1, 1, 3 }, 948 }; 949 950 static const struct panel_desc auo_g070vvn01 = { 951 .timings = &auo_g070vvn01_timings, 952 .num_timings = 1, 953 .bpc = 8, 954 .size = { 955 .width = 152, 956 .height = 91, 957 }, 958 .delay = { 959 .prepare = 200, 960 .enable = 50, 961 .disable = 50, 962 .unprepare = 1000, 963 }, 964 }; 965 966 static const struct drm_display_mode auo_g101evn010_mode = { 967 .clock = 68930, 968 .hdisplay = 1280, 969 .hsync_start = 1280 + 82, 970 .hsync_end = 1280 + 82 + 2, 971 .htotal = 1280 + 82 + 2 + 84, 972 .vdisplay = 800, 973 .vsync_start = 800 + 8, 974 .vsync_end = 800 + 8 + 2, 975 .vtotal = 800 + 8 + 2 + 6, 976 }; 977 978 static const struct panel_desc auo_g101evn010 = { 979 .modes = &auo_g101evn010_mode, 980 .num_modes = 1, 981 .bpc = 6, 982 .size = { 983 .width = 216, 984 .height = 135, 985 }, 986 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 987 .connector_type = DRM_MODE_CONNECTOR_LVDS, 988 }; 989 990 static const struct drm_display_mode auo_g104sn02_mode = { 991 .clock = 40000, 992 .hdisplay = 800, 993 .hsync_start = 800 + 40, 994 .hsync_end = 800 + 40 + 216, 995 .htotal = 800 + 40 + 216 + 128, 996 .vdisplay = 600, 997 .vsync_start = 600 + 10, 998 .vsync_end = 600 + 10 + 35, 999 .vtotal = 600 + 10 + 35 + 2, 1000 }; 1001 1002 static const struct panel_desc auo_g104sn02 = { 1003 .modes = &auo_g104sn02_mode, 1004 .num_modes = 1, 1005 .bpc = 8, 1006 .size = { 1007 .width = 211, 1008 .height = 158, 1009 }, 1010 }; 1011 1012 static const struct drm_display_mode auo_g121ean01_mode = { 1013 .clock = 66700, 1014 .hdisplay = 1280, 1015 .hsync_start = 1280 + 58, 1016 .hsync_end = 1280 + 58 + 8, 1017 .htotal = 1280 + 58 + 8 + 70, 1018 .vdisplay = 800, 1019 .vsync_start = 800 + 6, 1020 .vsync_end = 800 + 6 + 4, 1021 .vtotal = 800 + 6 + 4 + 10, 1022 }; 1023 1024 static const struct panel_desc auo_g121ean01 = { 1025 .modes = &auo_g121ean01_mode, 1026 .num_modes = 1, 1027 .bpc = 8, 1028 .size = { 1029 .width = 261, 1030 .height = 163, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1033 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1034 }; 1035 1036 static const struct display_timing auo_g133han01_timings = { 1037 .pixelclock = { 134000000, 141200000, 149000000 }, 1038 .hactive = { 1920, 1920, 1920 }, 1039 .hfront_porch = { 39, 58, 77 }, 1040 .hback_porch = { 59, 88, 117 }, 1041 .hsync_len = { 28, 42, 56 }, 1042 .vactive = { 1080, 1080, 1080 }, 1043 .vfront_porch = { 3, 8, 11 }, 1044 .vback_porch = { 5, 14, 19 }, 1045 .vsync_len = { 4, 14, 19 }, 1046 }; 1047 1048 static const struct panel_desc auo_g133han01 = { 1049 .timings = &auo_g133han01_timings, 1050 .num_timings = 1, 1051 .bpc = 8, 1052 .size = { 1053 .width = 293, 1054 .height = 165, 1055 }, 1056 .delay = { 1057 .prepare = 200, 1058 .enable = 50, 1059 .disable = 50, 1060 .unprepare = 1000, 1061 }, 1062 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1063 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1064 }; 1065 1066 static const struct drm_display_mode auo_g156xtn01_mode = { 1067 .clock = 76000, 1068 .hdisplay = 1366, 1069 .hsync_start = 1366 + 33, 1070 .hsync_end = 1366 + 33 + 67, 1071 .htotal = 1560, 1072 .vdisplay = 768, 1073 .vsync_start = 768 + 4, 1074 .vsync_end = 768 + 4 + 4, 1075 .vtotal = 806, 1076 }; 1077 1078 static const struct panel_desc auo_g156xtn01 = { 1079 .modes = &auo_g156xtn01_mode, 1080 .num_modes = 1, 1081 .bpc = 8, 1082 .size = { 1083 .width = 344, 1084 .height = 194, 1085 }, 1086 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088 }; 1089 1090 static const struct display_timing auo_g185han01_timings = { 1091 .pixelclock = { 120000000, 144000000, 175000000 }, 1092 .hactive = { 1920, 1920, 1920 }, 1093 .hfront_porch = { 36, 120, 148 }, 1094 .hback_porch = { 24, 88, 108 }, 1095 .hsync_len = { 20, 48, 64 }, 1096 .vactive = { 1080, 1080, 1080 }, 1097 .vfront_porch = { 6, 10, 40 }, 1098 .vback_porch = { 2, 5, 20 }, 1099 .vsync_len = { 2, 5, 20 }, 1100 }; 1101 1102 static const struct panel_desc auo_g185han01 = { 1103 .timings = &auo_g185han01_timings, 1104 .num_timings = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 409, 1108 .height = 230, 1109 }, 1110 .delay = { 1111 .prepare = 50, 1112 .enable = 200, 1113 .disable = 110, 1114 .unprepare = 1000, 1115 }, 1116 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1117 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1118 }; 1119 1120 static const struct display_timing auo_g190ean01_timings = { 1121 .pixelclock = { 90000000, 108000000, 135000000 }, 1122 .hactive = { 1280, 1280, 1280 }, 1123 .hfront_porch = { 126, 184, 1266 }, 1124 .hback_porch = { 84, 122, 844 }, 1125 .hsync_len = { 70, 102, 704 }, 1126 .vactive = { 1024, 1024, 1024 }, 1127 .vfront_porch = { 4, 26, 76 }, 1128 .vback_porch = { 2, 8, 25 }, 1129 .vsync_len = { 2, 8, 25 }, 1130 }; 1131 1132 static const struct panel_desc auo_g190ean01 = { 1133 .timings = &auo_g190ean01_timings, 1134 .num_timings = 1, 1135 .bpc = 8, 1136 .size = { 1137 .width = 376, 1138 .height = 301, 1139 }, 1140 .delay = { 1141 .prepare = 50, 1142 .enable = 200, 1143 .disable = 110, 1144 .unprepare = 1000, 1145 }, 1146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1147 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1148 }; 1149 1150 static const struct display_timing auo_p320hvn03_timings = { 1151 .pixelclock = { 106000000, 148500000, 164000000 }, 1152 .hactive = { 1920, 1920, 1920 }, 1153 .hfront_porch = { 25, 50, 130 }, 1154 .hback_porch = { 25, 50, 130 }, 1155 .hsync_len = { 20, 40, 105 }, 1156 .vactive = { 1080, 1080, 1080 }, 1157 .vfront_porch = { 8, 17, 150 }, 1158 .vback_porch = { 8, 17, 150 }, 1159 .vsync_len = { 4, 11, 100 }, 1160 }; 1161 1162 static const struct panel_desc auo_p320hvn03 = { 1163 .timings = &auo_p320hvn03_timings, 1164 .num_timings = 1, 1165 .bpc = 8, 1166 .size = { 1167 .width = 698, 1168 .height = 393, 1169 }, 1170 .delay = { 1171 .prepare = 1, 1172 .enable = 450, 1173 .unprepare = 500, 1174 }, 1175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1177 }; 1178 1179 static const struct drm_display_mode auo_t215hvn01_mode = { 1180 .clock = 148800, 1181 .hdisplay = 1920, 1182 .hsync_start = 1920 + 88, 1183 .hsync_end = 1920 + 88 + 44, 1184 .htotal = 1920 + 88 + 44 + 148, 1185 .vdisplay = 1080, 1186 .vsync_start = 1080 + 4, 1187 .vsync_end = 1080 + 4 + 5, 1188 .vtotal = 1080 + 4 + 5 + 36, 1189 }; 1190 1191 static const struct panel_desc auo_t215hvn01 = { 1192 .modes = &auo_t215hvn01_mode, 1193 .num_modes = 1, 1194 .bpc = 8, 1195 .size = { 1196 .width = 430, 1197 .height = 270, 1198 }, 1199 .delay = { 1200 .disable = 5, 1201 .unprepare = 1000, 1202 } 1203 }; 1204 1205 static const struct drm_display_mode avic_tm070ddh03_mode = { 1206 .clock = 51200, 1207 .hdisplay = 1024, 1208 .hsync_start = 1024 + 160, 1209 .hsync_end = 1024 + 160 + 4, 1210 .htotal = 1024 + 160 + 4 + 156, 1211 .vdisplay = 600, 1212 .vsync_start = 600 + 17, 1213 .vsync_end = 600 + 17 + 1, 1214 .vtotal = 600 + 17 + 1 + 17, 1215 }; 1216 1217 static const struct panel_desc avic_tm070ddh03 = { 1218 .modes = &avic_tm070ddh03_mode, 1219 .num_modes = 1, 1220 .bpc = 8, 1221 .size = { 1222 .width = 154, 1223 .height = 90, 1224 }, 1225 .delay = { 1226 .prepare = 20, 1227 .enable = 200, 1228 .disable = 200, 1229 }, 1230 }; 1231 1232 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1233 .clock = 30000, 1234 .hdisplay = 800, 1235 .hsync_start = 800 + 40, 1236 .hsync_end = 800 + 40 + 48, 1237 .htotal = 800 + 40 + 48 + 40, 1238 .vdisplay = 480, 1239 .vsync_start = 480 + 13, 1240 .vsync_end = 480 + 13 + 3, 1241 .vtotal = 480 + 13 + 3 + 29, 1242 }; 1243 1244 static const struct panel_desc bananapi_s070wv20_ct16 = { 1245 .modes = &bananapi_s070wv20_ct16_mode, 1246 .num_modes = 1, 1247 .bpc = 6, 1248 .size = { 1249 .width = 154, 1250 .height = 86, 1251 }, 1252 }; 1253 1254 static const struct drm_display_mode boe_hv070wsa_mode = { 1255 .clock = 42105, 1256 .hdisplay = 1024, 1257 .hsync_start = 1024 + 30, 1258 .hsync_end = 1024 + 30 + 30, 1259 .htotal = 1024 + 30 + 30 + 30, 1260 .vdisplay = 600, 1261 .vsync_start = 600 + 10, 1262 .vsync_end = 600 + 10 + 10, 1263 .vtotal = 600 + 10 + 10 + 10, 1264 }; 1265 1266 static const struct panel_desc boe_hv070wsa = { 1267 .modes = &boe_hv070wsa_mode, 1268 .num_modes = 1, 1269 .bpc = 8, 1270 .size = { 1271 .width = 154, 1272 .height = 90, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1276 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1277 }; 1278 1279 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1280 { 1281 .clock = 71900, 1282 .hdisplay = 1280, 1283 .hsync_start = 1280 + 48, 1284 .hsync_end = 1280 + 48 + 32, 1285 .htotal = 1280 + 48 + 32 + 80, 1286 .vdisplay = 800, 1287 .vsync_start = 800 + 3, 1288 .vsync_end = 800 + 3 + 5, 1289 .vtotal = 800 + 3 + 5 + 24, 1290 }, 1291 { 1292 .clock = 57500, 1293 .hdisplay = 1280, 1294 .hsync_start = 1280 + 48, 1295 .hsync_end = 1280 + 48 + 32, 1296 .htotal = 1280 + 48 + 32 + 80, 1297 .vdisplay = 800, 1298 .vsync_start = 800 + 3, 1299 .vsync_end = 800 + 3 + 5, 1300 .vtotal = 800 + 3 + 5 + 24, 1301 }, 1302 }; 1303 1304 static const struct panel_desc boe_nv101wxmn51 = { 1305 .modes = boe_nv101wxmn51_modes, 1306 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1307 .bpc = 8, 1308 .size = { 1309 .width = 217, 1310 .height = 136, 1311 }, 1312 .delay = { 1313 .prepare = 210, 1314 .enable = 50, 1315 .unprepare = 160, 1316 }, 1317 }; 1318 1319 /* Also used for boe_nv133fhm_n62 */ 1320 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1321 .clock = 147840, 1322 .hdisplay = 1920, 1323 .hsync_start = 1920 + 48, 1324 .hsync_end = 1920 + 48 + 32, 1325 .htotal = 1920 + 48 + 32 + 200, 1326 .vdisplay = 1080, 1327 .vsync_start = 1080 + 3, 1328 .vsync_end = 1080 + 3 + 6, 1329 .vtotal = 1080 + 3 + 6 + 31, 1330 }; 1331 1332 /* Also used for boe_nv133fhm_n62 */ 1333 static const struct panel_desc boe_nv133fhm_n61 = { 1334 .modes = &boe_nv133fhm_n61_modes, 1335 .num_modes = 1, 1336 .bpc = 6, 1337 .size = { 1338 .width = 294, 1339 .height = 165, 1340 }, 1341 .delay = { 1342 /* 1343 * When power is first given to the panel there's a short 1344 * spike on the HPD line. It was explained that this spike 1345 * was until the TCON data download was complete. On 1346 * one system this was measured at 8 ms. We'll put 15 ms 1347 * in the prepare delay just to be safe and take it away 1348 * from the hpd_absent_delay (which would otherwise be 200 ms) 1349 * to handle this. That means: 1350 * - If HPD isn't hooked up you still have 200 ms delay. 1351 * - If HPD is hooked up we won't try to look at it for the 1352 * first 15 ms. 1353 */ 1354 .prepare = 15, 1355 .hpd_absent_delay = 185, 1356 1357 .unprepare = 500, 1358 }, 1359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1360 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1361 .connector_type = DRM_MODE_CONNECTOR_eDP, 1362 }; 1363 1364 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1365 { 1366 .clock = 148500, 1367 .hdisplay = 1920, 1368 .hsync_start = 1920 + 48, 1369 .hsync_end = 1920 + 48 + 32, 1370 .htotal = 2200, 1371 .vdisplay = 1080, 1372 .vsync_start = 1080 + 3, 1373 .vsync_end = 1080 + 3 + 5, 1374 .vtotal = 1125, 1375 }, 1376 }; 1377 1378 static const struct panel_desc boe_nv140fhmn49 = { 1379 .modes = boe_nv140fhmn49_modes, 1380 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1381 .bpc = 6, 1382 .size = { 1383 .width = 309, 1384 .height = 174, 1385 }, 1386 .delay = { 1387 .prepare = 210, 1388 .enable = 50, 1389 .unprepare = 160, 1390 }, 1391 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1392 .connector_type = DRM_MODE_CONNECTOR_eDP, 1393 }; 1394 1395 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1396 .clock = 9000, 1397 .hdisplay = 480, 1398 .hsync_start = 480 + 5, 1399 .hsync_end = 480 + 5 + 5, 1400 .htotal = 480 + 5 + 5 + 40, 1401 .vdisplay = 272, 1402 .vsync_start = 272 + 8, 1403 .vsync_end = 272 + 8 + 8, 1404 .vtotal = 272 + 8 + 8 + 8, 1405 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1406 }; 1407 1408 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1409 .modes = &cdtech_s043wq26h_ct7_mode, 1410 .num_modes = 1, 1411 .bpc = 8, 1412 .size = { 1413 .width = 95, 1414 .height = 54, 1415 }, 1416 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1417 }; 1418 1419 /* S070PWS19HP-FC21 2017/04/22 */ 1420 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1421 .clock = 51200, 1422 .hdisplay = 1024, 1423 .hsync_start = 1024 + 160, 1424 .hsync_end = 1024 + 160 + 20, 1425 .htotal = 1024 + 160 + 20 + 140, 1426 .vdisplay = 600, 1427 .vsync_start = 600 + 12, 1428 .vsync_end = 600 + 12 + 3, 1429 .vtotal = 600 + 12 + 3 + 20, 1430 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1431 }; 1432 1433 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1434 .modes = &cdtech_s070pws19hp_fc21_mode, 1435 .num_modes = 1, 1436 .bpc = 6, 1437 .size = { 1438 .width = 154, 1439 .height = 86, 1440 }, 1441 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1443 .connector_type = DRM_MODE_CONNECTOR_DPI, 1444 }; 1445 1446 /* S070SWV29HG-DC44 2017/09/21 */ 1447 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1448 .clock = 33300, 1449 .hdisplay = 800, 1450 .hsync_start = 800 + 210, 1451 .hsync_end = 800 + 210 + 2, 1452 .htotal = 800 + 210 + 2 + 44, 1453 .vdisplay = 480, 1454 .vsync_start = 480 + 22, 1455 .vsync_end = 480 + 22 + 2, 1456 .vtotal = 480 + 22 + 2 + 21, 1457 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1458 }; 1459 1460 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1461 .modes = &cdtech_s070swv29hg_dc44_mode, 1462 .num_modes = 1, 1463 .bpc = 6, 1464 .size = { 1465 .width = 154, 1466 .height = 86, 1467 }, 1468 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1470 .connector_type = DRM_MODE_CONNECTOR_DPI, 1471 }; 1472 1473 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1474 .clock = 35000, 1475 .hdisplay = 800, 1476 .hsync_start = 800 + 40, 1477 .hsync_end = 800 + 40 + 40, 1478 .htotal = 800 + 40 + 40 + 48, 1479 .vdisplay = 480, 1480 .vsync_start = 480 + 29, 1481 .vsync_end = 480 + 29 + 13, 1482 .vtotal = 480 + 29 + 13 + 3, 1483 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1484 }; 1485 1486 static const struct panel_desc cdtech_s070wv95_ct16 = { 1487 .modes = &cdtech_s070wv95_ct16_mode, 1488 .num_modes = 1, 1489 .bpc = 8, 1490 .size = { 1491 .width = 154, 1492 .height = 85, 1493 }, 1494 }; 1495 1496 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1497 .pixelclock = { 68900000, 71100000, 73400000 }, 1498 .hactive = { 1280, 1280, 1280 }, 1499 .hfront_porch = { 65, 80, 95 }, 1500 .hback_porch = { 64, 79, 94 }, 1501 .hsync_len = { 1, 1, 1 }, 1502 .vactive = { 800, 800, 800 }, 1503 .vfront_porch = { 7, 11, 14 }, 1504 .vback_porch = { 7, 11, 14 }, 1505 .vsync_len = { 1, 1, 1 }, 1506 .flags = DISPLAY_FLAGS_DE_HIGH, 1507 }; 1508 1509 static const struct panel_desc chefree_ch101olhlwh_002 = { 1510 .timings = &chefree_ch101olhlwh_002_timing, 1511 .num_timings = 1, 1512 .bpc = 8, 1513 .size = { 1514 .width = 217, 1515 .height = 135, 1516 }, 1517 .delay = { 1518 .enable = 200, 1519 .disable = 200, 1520 }, 1521 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1522 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1523 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1524 }; 1525 1526 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1527 .clock = 66770, 1528 .hdisplay = 800, 1529 .hsync_start = 800 + 49, 1530 .hsync_end = 800 + 49 + 33, 1531 .htotal = 800 + 49 + 33 + 17, 1532 .vdisplay = 1280, 1533 .vsync_start = 1280 + 1, 1534 .vsync_end = 1280 + 1 + 7, 1535 .vtotal = 1280 + 1 + 7 + 15, 1536 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1537 }; 1538 1539 static const struct panel_desc chunghwa_claa070wp03xg = { 1540 .modes = &chunghwa_claa070wp03xg_mode, 1541 .num_modes = 1, 1542 .bpc = 6, 1543 .size = { 1544 .width = 94, 1545 .height = 150, 1546 }, 1547 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1548 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1549 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1550 }; 1551 1552 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1553 .clock = 72070, 1554 .hdisplay = 1366, 1555 .hsync_start = 1366 + 58, 1556 .hsync_end = 1366 + 58 + 58, 1557 .htotal = 1366 + 58 + 58 + 58, 1558 .vdisplay = 768, 1559 .vsync_start = 768 + 4, 1560 .vsync_end = 768 + 4 + 4, 1561 .vtotal = 768 + 4 + 4 + 4, 1562 }; 1563 1564 static const struct panel_desc chunghwa_claa101wa01a = { 1565 .modes = &chunghwa_claa101wa01a_mode, 1566 .num_modes = 1, 1567 .bpc = 6, 1568 .size = { 1569 .width = 220, 1570 .height = 120, 1571 }, 1572 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1573 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1575 }; 1576 1577 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1578 .clock = 69300, 1579 .hdisplay = 1366, 1580 .hsync_start = 1366 + 48, 1581 .hsync_end = 1366 + 48 + 32, 1582 .htotal = 1366 + 48 + 32 + 20, 1583 .vdisplay = 768, 1584 .vsync_start = 768 + 16, 1585 .vsync_end = 768 + 16 + 8, 1586 .vtotal = 768 + 16 + 8 + 16, 1587 }; 1588 1589 static const struct panel_desc chunghwa_claa101wb01 = { 1590 .modes = &chunghwa_claa101wb01_mode, 1591 .num_modes = 1, 1592 .bpc = 6, 1593 .size = { 1594 .width = 223, 1595 .height = 125, 1596 }, 1597 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1598 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1599 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1600 }; 1601 1602 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1603 .clock = 33260, 1604 .hdisplay = 800, 1605 .hsync_start = 800 + 40, 1606 .hsync_end = 800 + 40 + 128, 1607 .htotal = 800 + 40 + 128 + 88, 1608 .vdisplay = 480, 1609 .vsync_start = 480 + 10, 1610 .vsync_end = 480 + 10 + 2, 1611 .vtotal = 480 + 10 + 2 + 33, 1612 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1613 }; 1614 1615 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1616 .modes = &dataimage_scf0700c48ggu18_mode, 1617 .num_modes = 1, 1618 .bpc = 8, 1619 .size = { 1620 .width = 152, 1621 .height = 91, 1622 }, 1623 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1624 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1625 }; 1626 1627 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1628 .pixelclock = { 45000000, 51200000, 57000000 }, 1629 .hactive = { 1024, 1024, 1024 }, 1630 .hfront_porch = { 100, 106, 113 }, 1631 .hback_porch = { 100, 106, 113 }, 1632 .hsync_len = { 100, 108, 114 }, 1633 .vactive = { 600, 600, 600 }, 1634 .vfront_porch = { 8, 11, 15 }, 1635 .vback_porch = { 8, 11, 15 }, 1636 .vsync_len = { 9, 13, 15 }, 1637 .flags = DISPLAY_FLAGS_DE_HIGH, 1638 }; 1639 1640 static const struct panel_desc dlc_dlc0700yzg_1 = { 1641 .timings = &dlc_dlc0700yzg_1_timing, 1642 .num_timings = 1, 1643 .bpc = 6, 1644 .size = { 1645 .width = 154, 1646 .height = 86, 1647 }, 1648 .delay = { 1649 .prepare = 30, 1650 .enable = 200, 1651 .disable = 200, 1652 }, 1653 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1654 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1655 }; 1656 1657 static const struct display_timing dlc_dlc1010gig_timing = { 1658 .pixelclock = { 68900000, 71100000, 73400000 }, 1659 .hactive = { 1280, 1280, 1280 }, 1660 .hfront_porch = { 43, 53, 63 }, 1661 .hback_porch = { 43, 53, 63 }, 1662 .hsync_len = { 44, 54, 64 }, 1663 .vactive = { 800, 800, 800 }, 1664 .vfront_porch = { 5, 8, 11 }, 1665 .vback_porch = { 5, 8, 11 }, 1666 .vsync_len = { 5, 7, 11 }, 1667 .flags = DISPLAY_FLAGS_DE_HIGH, 1668 }; 1669 1670 static const struct panel_desc dlc_dlc1010gig = { 1671 .timings = &dlc_dlc1010gig_timing, 1672 .num_timings = 1, 1673 .bpc = 8, 1674 .size = { 1675 .width = 216, 1676 .height = 135, 1677 }, 1678 .delay = { 1679 .prepare = 60, 1680 .enable = 150, 1681 .disable = 100, 1682 .unprepare = 60, 1683 }, 1684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1685 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1686 }; 1687 1688 static const struct drm_display_mode edt_et035012dm6_mode = { 1689 .clock = 6500, 1690 .hdisplay = 320, 1691 .hsync_start = 320 + 20, 1692 .hsync_end = 320 + 20 + 30, 1693 .htotal = 320 + 20 + 68, 1694 .vdisplay = 240, 1695 .vsync_start = 240 + 4, 1696 .vsync_end = 240 + 4 + 4, 1697 .vtotal = 240 + 4 + 4 + 14, 1698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1699 }; 1700 1701 static const struct panel_desc edt_et035012dm6 = { 1702 .modes = &edt_et035012dm6_mode, 1703 .num_modes = 1, 1704 .bpc = 8, 1705 .size = { 1706 .width = 70, 1707 .height = 52, 1708 }, 1709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1710 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1711 }; 1712 1713 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1714 .clock = 10870, 1715 .hdisplay = 480, 1716 .hsync_start = 480 + 8, 1717 .hsync_end = 480 + 8 + 4, 1718 .htotal = 480 + 8 + 4 + 41, 1719 1720 /* 1721 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1722 * fb_align 1723 */ 1724 1725 .vdisplay = 288, 1726 .vsync_start = 288 + 2, 1727 .vsync_end = 288 + 2 + 4, 1728 .vtotal = 288 + 2 + 4 + 10, 1729 }; 1730 1731 static const struct panel_desc edt_etm043080dh6gp = { 1732 .modes = &edt_etm043080dh6gp_mode, 1733 .num_modes = 1, 1734 .bpc = 8, 1735 .size = { 1736 .width = 100, 1737 .height = 65, 1738 }, 1739 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1740 .connector_type = DRM_MODE_CONNECTOR_DPI, 1741 }; 1742 1743 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1744 .clock = 9000, 1745 .hdisplay = 480, 1746 .hsync_start = 480 + 2, 1747 .hsync_end = 480 + 2 + 41, 1748 .htotal = 480 + 2 + 41 + 2, 1749 .vdisplay = 272, 1750 .vsync_start = 272 + 2, 1751 .vsync_end = 272 + 2 + 10, 1752 .vtotal = 272 + 2 + 10 + 2, 1753 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1754 }; 1755 1756 static const struct panel_desc edt_etm0430g0dh6 = { 1757 .modes = &edt_etm0430g0dh6_mode, 1758 .num_modes = 1, 1759 .bpc = 6, 1760 .size = { 1761 .width = 95, 1762 .height = 54, 1763 }, 1764 }; 1765 1766 static const struct drm_display_mode edt_et057090dhu_mode = { 1767 .clock = 25175, 1768 .hdisplay = 640, 1769 .hsync_start = 640 + 16, 1770 .hsync_end = 640 + 16 + 30, 1771 .htotal = 640 + 16 + 30 + 114, 1772 .vdisplay = 480, 1773 .vsync_start = 480 + 10, 1774 .vsync_end = 480 + 10 + 3, 1775 .vtotal = 480 + 10 + 3 + 32, 1776 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1777 }; 1778 1779 static const struct panel_desc edt_et057090dhu = { 1780 .modes = &edt_et057090dhu_mode, 1781 .num_modes = 1, 1782 .bpc = 6, 1783 .size = { 1784 .width = 115, 1785 .height = 86, 1786 }, 1787 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1788 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1789 .connector_type = DRM_MODE_CONNECTOR_DPI, 1790 }; 1791 1792 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1793 .clock = 33260, 1794 .hdisplay = 800, 1795 .hsync_start = 800 + 40, 1796 .hsync_end = 800 + 40 + 128, 1797 .htotal = 800 + 40 + 128 + 88, 1798 .vdisplay = 480, 1799 .vsync_start = 480 + 10, 1800 .vsync_end = 480 + 10 + 2, 1801 .vtotal = 480 + 10 + 2 + 33, 1802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1803 }; 1804 1805 static const struct panel_desc edt_etm0700g0dh6 = { 1806 .modes = &edt_etm0700g0dh6_mode, 1807 .num_modes = 1, 1808 .bpc = 6, 1809 .size = { 1810 .width = 152, 1811 .height = 91, 1812 }, 1813 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1814 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1815 }; 1816 1817 static const struct panel_desc edt_etm0700g0bdh6 = { 1818 .modes = &edt_etm0700g0dh6_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 152, 1823 .height = 91, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1827 }; 1828 1829 static const struct display_timing evervision_vgg804821_timing = { 1830 .pixelclock = { 27600000, 33300000, 50000000 }, 1831 .hactive = { 800, 800, 800 }, 1832 .hfront_porch = { 40, 66, 70 }, 1833 .hback_porch = { 40, 67, 70 }, 1834 .hsync_len = { 40, 67, 70 }, 1835 .vactive = { 480, 480, 480 }, 1836 .vfront_porch = { 6, 10, 10 }, 1837 .vback_porch = { 7, 11, 11 }, 1838 .vsync_len = { 7, 11, 11 }, 1839 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1840 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1841 DISPLAY_FLAGS_SYNC_NEGEDGE, 1842 }; 1843 1844 static const struct panel_desc evervision_vgg804821 = { 1845 .timings = &evervision_vgg804821_timing, 1846 .num_timings = 1, 1847 .bpc = 8, 1848 .size = { 1849 .width = 108, 1850 .height = 64, 1851 }, 1852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1853 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1854 }; 1855 1856 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1857 .clock = 32260, 1858 .hdisplay = 800, 1859 .hsync_start = 800 + 168, 1860 .hsync_end = 800 + 168 + 64, 1861 .htotal = 800 + 168 + 64 + 88, 1862 .vdisplay = 480, 1863 .vsync_start = 480 + 37, 1864 .vsync_end = 480 + 37 + 2, 1865 .vtotal = 480 + 37 + 2 + 8, 1866 }; 1867 1868 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1869 .modes = &foxlink_fl500wvr00_a0t_mode, 1870 .num_modes = 1, 1871 .bpc = 8, 1872 .size = { 1873 .width = 108, 1874 .height = 65, 1875 }, 1876 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1877 }; 1878 1879 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1880 { /* 60 Hz */ 1881 .clock = 6000, 1882 .hdisplay = 320, 1883 .hsync_start = 320 + 44, 1884 .hsync_end = 320 + 44 + 16, 1885 .htotal = 320 + 44 + 16 + 20, 1886 .vdisplay = 240, 1887 .vsync_start = 240 + 2, 1888 .vsync_end = 240 + 2 + 6, 1889 .vtotal = 240 + 2 + 6 + 2, 1890 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1891 }, 1892 { /* 50 Hz */ 1893 .clock = 5400, 1894 .hdisplay = 320, 1895 .hsync_start = 320 + 56, 1896 .hsync_end = 320 + 56 + 16, 1897 .htotal = 320 + 56 + 16 + 40, 1898 .vdisplay = 240, 1899 .vsync_start = 240 + 2, 1900 .vsync_end = 240 + 2 + 6, 1901 .vtotal = 240 + 2 + 6 + 2, 1902 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1903 }, 1904 }; 1905 1906 static const struct panel_desc frida_frd350h54004 = { 1907 .modes = frida_frd350h54004_modes, 1908 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1909 .bpc = 8, 1910 .size = { 1911 .width = 77, 1912 .height = 64, 1913 }, 1914 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1915 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1916 .connector_type = DRM_MODE_CONNECTOR_DPI, 1917 }; 1918 1919 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1920 .clock = 67185, 1921 .hdisplay = 800, 1922 .hsync_start = 800 + 20, 1923 .hsync_end = 800 + 20 + 24, 1924 .htotal = 800 + 20 + 24 + 20, 1925 .vdisplay = 1280, 1926 .vsync_start = 1280 + 4, 1927 .vsync_end = 1280 + 4 + 8, 1928 .vtotal = 1280 + 4 + 8 + 4, 1929 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1930 }; 1931 1932 static const struct panel_desc friendlyarm_hd702e = { 1933 .modes = &friendlyarm_hd702e_mode, 1934 .num_modes = 1, 1935 .size = { 1936 .width = 94, 1937 .height = 151, 1938 }, 1939 }; 1940 1941 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1942 .clock = 9000, 1943 .hdisplay = 480, 1944 .hsync_start = 480 + 5, 1945 .hsync_end = 480 + 5 + 1, 1946 .htotal = 480 + 5 + 1 + 40, 1947 .vdisplay = 272, 1948 .vsync_start = 272 + 8, 1949 .vsync_end = 272 + 8 + 1, 1950 .vtotal = 272 + 8 + 1 + 8, 1951 }; 1952 1953 static const struct panel_desc giantplus_gpg482739qs5 = { 1954 .modes = &giantplus_gpg482739qs5_mode, 1955 .num_modes = 1, 1956 .bpc = 8, 1957 .size = { 1958 .width = 95, 1959 .height = 54, 1960 }, 1961 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1962 }; 1963 1964 static const struct display_timing giantplus_gpm940b0_timing = { 1965 .pixelclock = { 13500000, 27000000, 27500000 }, 1966 .hactive = { 320, 320, 320 }, 1967 .hfront_porch = { 14, 686, 718 }, 1968 .hback_porch = { 50, 70, 255 }, 1969 .hsync_len = { 1, 1, 1 }, 1970 .vactive = { 240, 240, 240 }, 1971 .vfront_porch = { 1, 1, 179 }, 1972 .vback_porch = { 1, 21, 31 }, 1973 .vsync_len = { 1, 1, 6 }, 1974 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1975 }; 1976 1977 static const struct panel_desc giantplus_gpm940b0 = { 1978 .timings = &giantplus_gpm940b0_timing, 1979 .num_timings = 1, 1980 .bpc = 8, 1981 .size = { 1982 .width = 60, 1983 .height = 45, 1984 }, 1985 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1986 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1987 }; 1988 1989 static const struct display_timing hannstar_hsd070pww1_timing = { 1990 .pixelclock = { 64300000, 71100000, 82000000 }, 1991 .hactive = { 1280, 1280, 1280 }, 1992 .hfront_porch = { 1, 1, 10 }, 1993 .hback_porch = { 1, 1, 10 }, 1994 /* 1995 * According to the data sheet, the minimum horizontal blanking interval 1996 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1997 * minimum working horizontal blanking interval to be 60 clocks. 1998 */ 1999 .hsync_len = { 58, 158, 661 }, 2000 .vactive = { 800, 800, 800 }, 2001 .vfront_porch = { 1, 1, 10 }, 2002 .vback_porch = { 1, 1, 10 }, 2003 .vsync_len = { 1, 21, 203 }, 2004 .flags = DISPLAY_FLAGS_DE_HIGH, 2005 }; 2006 2007 static const struct panel_desc hannstar_hsd070pww1 = { 2008 .timings = &hannstar_hsd070pww1_timing, 2009 .num_timings = 1, 2010 .bpc = 6, 2011 .size = { 2012 .width = 151, 2013 .height = 94, 2014 }, 2015 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2016 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2017 }; 2018 2019 static const struct display_timing hannstar_hsd100pxn1_timing = { 2020 .pixelclock = { 55000000, 65000000, 75000000 }, 2021 .hactive = { 1024, 1024, 1024 }, 2022 .hfront_porch = { 40, 40, 40 }, 2023 .hback_porch = { 220, 220, 220 }, 2024 .hsync_len = { 20, 60, 100 }, 2025 .vactive = { 768, 768, 768 }, 2026 .vfront_porch = { 7, 7, 7 }, 2027 .vback_porch = { 21, 21, 21 }, 2028 .vsync_len = { 10, 10, 10 }, 2029 .flags = DISPLAY_FLAGS_DE_HIGH, 2030 }; 2031 2032 static const struct panel_desc hannstar_hsd100pxn1 = { 2033 .timings = &hannstar_hsd100pxn1_timing, 2034 .num_timings = 1, 2035 .bpc = 6, 2036 .size = { 2037 .width = 203, 2038 .height = 152, 2039 }, 2040 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2041 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2042 }; 2043 2044 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2045 .clock = 33333, 2046 .hdisplay = 800, 2047 .hsync_start = 800 + 85, 2048 .hsync_end = 800 + 85 + 86, 2049 .htotal = 800 + 85 + 86 + 85, 2050 .vdisplay = 480, 2051 .vsync_start = 480 + 16, 2052 .vsync_end = 480 + 16 + 13, 2053 .vtotal = 480 + 16 + 13 + 16, 2054 }; 2055 2056 static const struct panel_desc hitachi_tx23d38vm0caa = { 2057 .modes = &hitachi_tx23d38vm0caa_mode, 2058 .num_modes = 1, 2059 .bpc = 6, 2060 .size = { 2061 .width = 195, 2062 .height = 117, 2063 }, 2064 .delay = { 2065 .enable = 160, 2066 .disable = 160, 2067 }, 2068 }; 2069 2070 static const struct drm_display_mode innolux_at043tn24_mode = { 2071 .clock = 9000, 2072 .hdisplay = 480, 2073 .hsync_start = 480 + 2, 2074 .hsync_end = 480 + 2 + 41, 2075 .htotal = 480 + 2 + 41 + 2, 2076 .vdisplay = 272, 2077 .vsync_start = 272 + 2, 2078 .vsync_end = 272 + 2 + 10, 2079 .vtotal = 272 + 2 + 10 + 2, 2080 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2081 }; 2082 2083 static const struct panel_desc innolux_at043tn24 = { 2084 .modes = &innolux_at043tn24_mode, 2085 .num_modes = 1, 2086 .bpc = 8, 2087 .size = { 2088 .width = 95, 2089 .height = 54, 2090 }, 2091 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2093 }; 2094 2095 static const struct drm_display_mode innolux_at070tn92_mode = { 2096 .clock = 33333, 2097 .hdisplay = 800, 2098 .hsync_start = 800 + 210, 2099 .hsync_end = 800 + 210 + 20, 2100 .htotal = 800 + 210 + 20 + 46, 2101 .vdisplay = 480, 2102 .vsync_start = 480 + 22, 2103 .vsync_end = 480 + 22 + 10, 2104 .vtotal = 480 + 22 + 23 + 10, 2105 }; 2106 2107 static const struct panel_desc innolux_at070tn92 = { 2108 .modes = &innolux_at070tn92_mode, 2109 .num_modes = 1, 2110 .size = { 2111 .width = 154, 2112 .height = 86, 2113 }, 2114 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2115 }; 2116 2117 static const struct display_timing innolux_g070y2_l01_timing = { 2118 .pixelclock = { 28000000, 29500000, 32000000 }, 2119 .hactive = { 800, 800, 800 }, 2120 .hfront_porch = { 61, 91, 141 }, 2121 .hback_porch = { 60, 90, 140 }, 2122 .hsync_len = { 12, 12, 12 }, 2123 .vactive = { 480, 480, 480 }, 2124 .vfront_porch = { 4, 9, 30 }, 2125 .vback_porch = { 4, 8, 28 }, 2126 .vsync_len = { 2, 2, 2 }, 2127 .flags = DISPLAY_FLAGS_DE_HIGH, 2128 }; 2129 2130 static const struct panel_desc innolux_g070y2_l01 = { 2131 .timings = &innolux_g070y2_l01_timing, 2132 .num_timings = 1, 2133 .bpc = 6, 2134 .size = { 2135 .width = 152, 2136 .height = 91, 2137 }, 2138 .delay = { 2139 .prepare = 10, 2140 .enable = 100, 2141 .disable = 100, 2142 .unprepare = 800, 2143 }, 2144 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2145 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2146 }; 2147 2148 static const struct display_timing innolux_g101ice_l01_timing = { 2149 .pixelclock = { 60400000, 71100000, 74700000 }, 2150 .hactive = { 1280, 1280, 1280 }, 2151 .hfront_porch = { 41, 80, 100 }, 2152 .hback_porch = { 40, 79, 99 }, 2153 .hsync_len = { 1, 1, 1 }, 2154 .vactive = { 800, 800, 800 }, 2155 .vfront_porch = { 5, 11, 14 }, 2156 .vback_porch = { 4, 11, 14 }, 2157 .vsync_len = { 1, 1, 1 }, 2158 .flags = DISPLAY_FLAGS_DE_HIGH, 2159 }; 2160 2161 static const struct panel_desc innolux_g101ice_l01 = { 2162 .timings = &innolux_g101ice_l01_timing, 2163 .num_timings = 1, 2164 .bpc = 8, 2165 .size = { 2166 .width = 217, 2167 .height = 135, 2168 }, 2169 .delay = { 2170 .enable = 200, 2171 .disable = 200, 2172 }, 2173 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2174 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2175 }; 2176 2177 static const struct display_timing innolux_g121i1_l01_timing = { 2178 .pixelclock = { 67450000, 71000000, 74550000 }, 2179 .hactive = { 1280, 1280, 1280 }, 2180 .hfront_porch = { 40, 80, 160 }, 2181 .hback_porch = { 39, 79, 159 }, 2182 .hsync_len = { 1, 1, 1 }, 2183 .vactive = { 800, 800, 800 }, 2184 .vfront_porch = { 5, 11, 100 }, 2185 .vback_porch = { 4, 11, 99 }, 2186 .vsync_len = { 1, 1, 1 }, 2187 }; 2188 2189 static const struct panel_desc innolux_g121i1_l01 = { 2190 .timings = &innolux_g121i1_l01_timing, 2191 .num_timings = 1, 2192 .bpc = 6, 2193 .size = { 2194 .width = 261, 2195 .height = 163, 2196 }, 2197 .delay = { 2198 .enable = 200, 2199 .disable = 20, 2200 }, 2201 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2202 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2203 }; 2204 2205 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2206 .clock = 65000, 2207 .hdisplay = 1024, 2208 .hsync_start = 1024 + 0, 2209 .hsync_end = 1024 + 1, 2210 .htotal = 1024 + 0 + 1 + 320, 2211 .vdisplay = 768, 2212 .vsync_start = 768 + 38, 2213 .vsync_end = 768 + 38 + 1, 2214 .vtotal = 768 + 38 + 1 + 0, 2215 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2216 }; 2217 2218 static const struct panel_desc innolux_g121x1_l03 = { 2219 .modes = &innolux_g121x1_l03_mode, 2220 .num_modes = 1, 2221 .bpc = 6, 2222 .size = { 2223 .width = 246, 2224 .height = 185, 2225 }, 2226 .delay = { 2227 .enable = 200, 2228 .unprepare = 200, 2229 .disable = 400, 2230 }, 2231 }; 2232 2233 /* 2234 * Datasheet specifies that at 60 Hz refresh rate: 2235 * - total horizontal time: { 1506, 1592, 1716 } 2236 * - total vertical time: { 788, 800, 868 } 2237 * 2238 * ...but doesn't go into exactly how that should be split into a front 2239 * porch, back porch, or sync length. For now we'll leave a single setting 2240 * here which allows a bit of tweaking of the pixel clock at the expense of 2241 * refresh rate. 2242 */ 2243 static const struct display_timing innolux_n116bge_timing = { 2244 .pixelclock = { 72600000, 76420000, 80240000 }, 2245 .hactive = { 1366, 1366, 1366 }, 2246 .hfront_porch = { 136, 136, 136 }, 2247 .hback_porch = { 60, 60, 60 }, 2248 .hsync_len = { 30, 30, 30 }, 2249 .vactive = { 768, 768, 768 }, 2250 .vfront_porch = { 8, 8, 8 }, 2251 .vback_porch = { 12, 12, 12 }, 2252 .vsync_len = { 12, 12, 12 }, 2253 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2254 }; 2255 2256 static const struct panel_desc innolux_n116bge = { 2257 .timings = &innolux_n116bge_timing, 2258 .num_timings = 1, 2259 .bpc = 6, 2260 .size = { 2261 .width = 256, 2262 .height = 144, 2263 }, 2264 }; 2265 2266 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2267 .clock = 69300, 2268 .hdisplay = 1366, 2269 .hsync_start = 1366 + 16, 2270 .hsync_end = 1366 + 16 + 34, 2271 .htotal = 1366 + 16 + 34 + 50, 2272 .vdisplay = 768, 2273 .vsync_start = 768 + 2, 2274 .vsync_end = 768 + 2 + 6, 2275 .vtotal = 768 + 2 + 6 + 12, 2276 }; 2277 2278 static const struct panel_desc innolux_n156bge_l21 = { 2279 .modes = &innolux_n156bge_l21_mode, 2280 .num_modes = 1, 2281 .bpc = 6, 2282 .size = { 2283 .width = 344, 2284 .height = 193, 2285 }, 2286 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2287 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2288 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2289 }; 2290 2291 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2292 .clock = 206016, 2293 .hdisplay = 2160, 2294 .hsync_start = 2160 + 48, 2295 .hsync_end = 2160 + 48 + 32, 2296 .htotal = 2160 + 48 + 32 + 80, 2297 .vdisplay = 1440, 2298 .vsync_start = 1440 + 3, 2299 .vsync_end = 1440 + 3 + 10, 2300 .vtotal = 1440 + 3 + 10 + 27, 2301 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2302 }; 2303 2304 static const struct panel_desc innolux_p120zdg_bf1 = { 2305 .modes = &innolux_p120zdg_bf1_mode, 2306 .num_modes = 1, 2307 .bpc = 8, 2308 .size = { 2309 .width = 254, 2310 .height = 169, 2311 }, 2312 .delay = { 2313 .hpd_absent_delay = 200, 2314 .unprepare = 500, 2315 }, 2316 }; 2317 2318 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2319 .clock = 51501, 2320 .hdisplay = 1024, 2321 .hsync_start = 1024 + 128, 2322 .hsync_end = 1024 + 128 + 64, 2323 .htotal = 1024 + 128 + 64 + 128, 2324 .vdisplay = 600, 2325 .vsync_start = 600 + 16, 2326 .vsync_end = 600 + 16 + 4, 2327 .vtotal = 600 + 16 + 4 + 16, 2328 }; 2329 2330 static const struct panel_desc innolux_zj070na_01p = { 2331 .modes = &innolux_zj070na_01p_mode, 2332 .num_modes = 1, 2333 .bpc = 6, 2334 .size = { 2335 .width = 154, 2336 .height = 90, 2337 }, 2338 }; 2339 2340 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2341 .clock = 138778, 2342 .hdisplay = 1920, 2343 .hsync_start = 1920 + 24, 2344 .hsync_end = 1920 + 24 + 48, 2345 .htotal = 1920 + 24 + 48 + 88, 2346 .vdisplay = 1080, 2347 .vsync_start = 1080 + 3, 2348 .vsync_end = 1080 + 3 + 12, 2349 .vtotal = 1080 + 3 + 12 + 17, 2350 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2351 }; 2352 2353 static const struct panel_desc ivo_m133nwf4_r0 = { 2354 .modes = &ivo_m133nwf4_r0_mode, 2355 .num_modes = 1, 2356 .bpc = 8, 2357 .size = { 2358 .width = 294, 2359 .height = 165, 2360 }, 2361 .delay = { 2362 .hpd_absent_delay = 200, 2363 .unprepare = 500, 2364 }, 2365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2366 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2367 .connector_type = DRM_MODE_CONNECTOR_eDP, 2368 }; 2369 2370 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2371 .clock = 81000, 2372 .hdisplay = 1366, 2373 .hsync_start = 1366 + 40, 2374 .hsync_end = 1366 + 40 + 32, 2375 .htotal = 1366 + 40 + 32 + 62, 2376 .vdisplay = 768, 2377 .vsync_start = 768 + 5, 2378 .vsync_end = 768 + 5 + 5, 2379 .vtotal = 768 + 5 + 5 + 122, 2380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2381 }; 2382 2383 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2384 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2385 .num_modes = 1, 2386 .bpc = 6, 2387 .size = { 2388 .width = 256, 2389 .height = 144, 2390 }, 2391 .delay = { 2392 .hpd_absent_delay = 200, 2393 }, 2394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2395 .connector_type = DRM_MODE_CONNECTOR_eDP, 2396 }; 2397 2398 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2399 .pixelclock = { 5580000, 5850000, 6200000 }, 2400 .hactive = { 320, 320, 320 }, 2401 .hfront_porch = { 30, 30, 30 }, 2402 .hback_porch = { 30, 30, 30 }, 2403 .hsync_len = { 1, 5, 17 }, 2404 .vactive = { 240, 240, 240 }, 2405 .vfront_porch = { 6, 6, 6 }, 2406 .vback_porch = { 5, 5, 5 }, 2407 .vsync_len = { 1, 2, 11 }, 2408 .flags = DISPLAY_FLAGS_DE_HIGH, 2409 }; 2410 2411 static const struct panel_desc koe_tx14d24vm1bpa = { 2412 .timings = &koe_tx14d24vm1bpa_timing, 2413 .num_timings = 1, 2414 .bpc = 6, 2415 .size = { 2416 .width = 115, 2417 .height = 86, 2418 }, 2419 }; 2420 2421 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2422 .pixelclock = { 151820000, 156720000, 159780000 }, 2423 .hactive = { 1920, 1920, 1920 }, 2424 .hfront_porch = { 105, 130, 142 }, 2425 .hback_porch = { 45, 70, 82 }, 2426 .hsync_len = { 30, 30, 30 }, 2427 .vactive = { 1200, 1200, 1200}, 2428 .vfront_porch = { 3, 5, 10 }, 2429 .vback_porch = { 2, 5, 10 }, 2430 .vsync_len = { 5, 5, 5 }, 2431 }; 2432 2433 static const struct panel_desc koe_tx26d202vm0bwa = { 2434 .timings = &koe_tx26d202vm0bwa_timing, 2435 .num_timings = 1, 2436 .bpc = 8, 2437 .size = { 2438 .width = 217, 2439 .height = 136, 2440 }, 2441 .delay = { 2442 .prepare = 1000, 2443 .enable = 1000, 2444 .unprepare = 1000, 2445 .disable = 1000, 2446 }, 2447 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2448 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2449 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2450 }; 2451 2452 static const struct display_timing koe_tx31d200vm0baa_timing = { 2453 .pixelclock = { 39600000, 43200000, 48000000 }, 2454 .hactive = { 1280, 1280, 1280 }, 2455 .hfront_porch = { 16, 36, 56 }, 2456 .hback_porch = { 16, 36, 56 }, 2457 .hsync_len = { 8, 8, 8 }, 2458 .vactive = { 480, 480, 480 }, 2459 .vfront_porch = { 6, 21, 33 }, 2460 .vback_porch = { 6, 21, 33 }, 2461 .vsync_len = { 8, 8, 8 }, 2462 .flags = DISPLAY_FLAGS_DE_HIGH, 2463 }; 2464 2465 static const struct panel_desc koe_tx31d200vm0baa = { 2466 .timings = &koe_tx31d200vm0baa_timing, 2467 .num_timings = 1, 2468 .bpc = 6, 2469 .size = { 2470 .width = 292, 2471 .height = 109, 2472 }, 2473 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2474 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2475 }; 2476 2477 static const struct display_timing kyo_tcg121xglp_timing = { 2478 .pixelclock = { 52000000, 65000000, 71000000 }, 2479 .hactive = { 1024, 1024, 1024 }, 2480 .hfront_porch = { 2, 2, 2 }, 2481 .hback_porch = { 2, 2, 2 }, 2482 .hsync_len = { 86, 124, 244 }, 2483 .vactive = { 768, 768, 768 }, 2484 .vfront_porch = { 2, 2, 2 }, 2485 .vback_porch = { 2, 2, 2 }, 2486 .vsync_len = { 6, 34, 73 }, 2487 .flags = DISPLAY_FLAGS_DE_HIGH, 2488 }; 2489 2490 static const struct panel_desc kyo_tcg121xglp = { 2491 .timings = &kyo_tcg121xglp_timing, 2492 .num_timings = 1, 2493 .bpc = 8, 2494 .size = { 2495 .width = 246, 2496 .height = 184, 2497 }, 2498 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2499 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2500 }; 2501 2502 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2503 .clock = 7000, 2504 .hdisplay = 320, 2505 .hsync_start = 320 + 20, 2506 .hsync_end = 320 + 20 + 30, 2507 .htotal = 320 + 20 + 30 + 38, 2508 .vdisplay = 240, 2509 .vsync_start = 240 + 4, 2510 .vsync_end = 240 + 4 + 3, 2511 .vtotal = 240 + 4 + 3 + 15, 2512 }; 2513 2514 static const struct panel_desc lemaker_bl035_rgb_002 = { 2515 .modes = &lemaker_bl035_rgb_002_mode, 2516 .num_modes = 1, 2517 .size = { 2518 .width = 70, 2519 .height = 52, 2520 }, 2521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2522 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2523 }; 2524 2525 static const struct drm_display_mode lg_lb070wv8_mode = { 2526 .clock = 33246, 2527 .hdisplay = 800, 2528 .hsync_start = 800 + 88, 2529 .hsync_end = 800 + 88 + 80, 2530 .htotal = 800 + 88 + 80 + 88, 2531 .vdisplay = 480, 2532 .vsync_start = 480 + 10, 2533 .vsync_end = 480 + 10 + 25, 2534 .vtotal = 480 + 10 + 25 + 10, 2535 }; 2536 2537 static const struct panel_desc lg_lb070wv8 = { 2538 .modes = &lg_lb070wv8_mode, 2539 .num_modes = 1, 2540 .bpc = 8, 2541 .size = { 2542 .width = 151, 2543 .height = 91, 2544 }, 2545 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2546 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2547 }; 2548 2549 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2550 .clock = 200000, 2551 .hdisplay = 1536, 2552 .hsync_start = 1536 + 12, 2553 .hsync_end = 1536 + 12 + 16, 2554 .htotal = 1536 + 12 + 16 + 48, 2555 .vdisplay = 2048, 2556 .vsync_start = 2048 + 8, 2557 .vsync_end = 2048 + 8 + 4, 2558 .vtotal = 2048 + 8 + 4 + 8, 2559 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2560 }; 2561 2562 static const struct panel_desc lg_lp079qx1_sp0v = { 2563 .modes = &lg_lp079qx1_sp0v_mode, 2564 .num_modes = 1, 2565 .size = { 2566 .width = 129, 2567 .height = 171, 2568 }, 2569 }; 2570 2571 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2572 .clock = 205210, 2573 .hdisplay = 2048, 2574 .hsync_start = 2048 + 150, 2575 .hsync_end = 2048 + 150 + 5, 2576 .htotal = 2048 + 150 + 5 + 5, 2577 .vdisplay = 1536, 2578 .vsync_start = 1536 + 3, 2579 .vsync_end = 1536 + 3 + 1, 2580 .vtotal = 1536 + 3 + 1 + 9, 2581 }; 2582 2583 static const struct panel_desc lg_lp097qx1_spa1 = { 2584 .modes = &lg_lp097qx1_spa1_mode, 2585 .num_modes = 1, 2586 .size = { 2587 .width = 208, 2588 .height = 147, 2589 }, 2590 }; 2591 2592 static const struct drm_display_mode lg_lp120up1_mode = { 2593 .clock = 162300, 2594 .hdisplay = 1920, 2595 .hsync_start = 1920 + 40, 2596 .hsync_end = 1920 + 40 + 40, 2597 .htotal = 1920 + 40 + 40+ 80, 2598 .vdisplay = 1280, 2599 .vsync_start = 1280 + 4, 2600 .vsync_end = 1280 + 4 + 4, 2601 .vtotal = 1280 + 4 + 4 + 12, 2602 }; 2603 2604 static const struct panel_desc lg_lp120up1 = { 2605 .modes = &lg_lp120up1_mode, 2606 .num_modes = 1, 2607 .bpc = 8, 2608 .size = { 2609 .width = 267, 2610 .height = 183, 2611 }, 2612 .connector_type = DRM_MODE_CONNECTOR_eDP, 2613 }; 2614 2615 static const struct drm_display_mode lg_lp129qe_mode = { 2616 .clock = 285250, 2617 .hdisplay = 2560, 2618 .hsync_start = 2560 + 48, 2619 .hsync_end = 2560 + 48 + 32, 2620 .htotal = 2560 + 48 + 32 + 80, 2621 .vdisplay = 1700, 2622 .vsync_start = 1700 + 3, 2623 .vsync_end = 1700 + 3 + 10, 2624 .vtotal = 1700 + 3 + 10 + 36, 2625 }; 2626 2627 static const struct panel_desc lg_lp129qe = { 2628 .modes = &lg_lp129qe_mode, 2629 .num_modes = 1, 2630 .bpc = 8, 2631 .size = { 2632 .width = 272, 2633 .height = 181, 2634 }, 2635 }; 2636 2637 static const struct display_timing logictechno_lt161010_2nh_timing = { 2638 .pixelclock = { 26400000, 33300000, 46800000 }, 2639 .hactive = { 800, 800, 800 }, 2640 .hfront_porch = { 16, 210, 354 }, 2641 .hback_porch = { 46, 46, 46 }, 2642 .hsync_len = { 1, 20, 40 }, 2643 .vactive = { 480, 480, 480 }, 2644 .vfront_porch = { 7, 22, 147 }, 2645 .vback_porch = { 23, 23, 23 }, 2646 .vsync_len = { 1, 10, 20 }, 2647 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2648 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2649 DISPLAY_FLAGS_SYNC_POSEDGE, 2650 }; 2651 2652 static const struct panel_desc logictechno_lt161010_2nh = { 2653 .timings = &logictechno_lt161010_2nh_timing, 2654 .num_timings = 1, 2655 .size = { 2656 .width = 154, 2657 .height = 86, 2658 }, 2659 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2660 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2661 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2662 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2663 .connector_type = DRM_MODE_CONNECTOR_DPI, 2664 }; 2665 2666 static const struct display_timing logictechno_lt170410_2whc_timing = { 2667 .pixelclock = { 68900000, 71100000, 73400000 }, 2668 .hactive = { 1280, 1280, 1280 }, 2669 .hfront_porch = { 23, 60, 71 }, 2670 .hback_porch = { 23, 60, 71 }, 2671 .hsync_len = { 15, 40, 47 }, 2672 .vactive = { 800, 800, 800 }, 2673 .vfront_porch = { 5, 7, 10 }, 2674 .vback_porch = { 5, 7, 10 }, 2675 .vsync_len = { 6, 9, 12 }, 2676 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2677 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2678 DISPLAY_FLAGS_SYNC_POSEDGE, 2679 }; 2680 2681 static const struct panel_desc logictechno_lt170410_2whc = { 2682 .timings = &logictechno_lt170410_2whc_timing, 2683 .num_timings = 1, 2684 .size = { 2685 .width = 217, 2686 .height = 136, 2687 }, 2688 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2689 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2691 }; 2692 2693 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2694 .clock = 30400, 2695 .hdisplay = 800, 2696 .hsync_start = 800 + 0, 2697 .hsync_end = 800 + 1, 2698 .htotal = 800 + 0 + 1 + 160, 2699 .vdisplay = 480, 2700 .vsync_start = 480 + 0, 2701 .vsync_end = 480 + 48 + 1, 2702 .vtotal = 480 + 48 + 1 + 0, 2703 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2704 }; 2705 2706 static const struct drm_display_mode logicpd_type_28_mode = { 2707 .clock = 9107, 2708 .hdisplay = 480, 2709 .hsync_start = 480 + 3, 2710 .hsync_end = 480 + 3 + 42, 2711 .htotal = 480 + 3 + 42 + 2, 2712 2713 .vdisplay = 272, 2714 .vsync_start = 272 + 2, 2715 .vsync_end = 272 + 2 + 11, 2716 .vtotal = 272 + 2 + 11 + 3, 2717 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2718 }; 2719 2720 static const struct panel_desc logicpd_type_28 = { 2721 .modes = &logicpd_type_28_mode, 2722 .num_modes = 1, 2723 .bpc = 8, 2724 .size = { 2725 .width = 105, 2726 .height = 67, 2727 }, 2728 .delay = { 2729 .prepare = 200, 2730 .enable = 200, 2731 .unprepare = 200, 2732 .disable = 200, 2733 }, 2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2735 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2736 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2737 .connector_type = DRM_MODE_CONNECTOR_DPI, 2738 }; 2739 2740 static const struct panel_desc mitsubishi_aa070mc01 = { 2741 .modes = &mitsubishi_aa070mc01_mode, 2742 .num_modes = 1, 2743 .bpc = 8, 2744 .size = { 2745 .width = 152, 2746 .height = 91, 2747 }, 2748 2749 .delay = { 2750 .enable = 200, 2751 .unprepare = 200, 2752 .disable = 400, 2753 }, 2754 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2755 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2756 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2757 }; 2758 2759 static const struct display_timing nec_nl12880bc20_05_timing = { 2760 .pixelclock = { 67000000, 71000000, 75000000 }, 2761 .hactive = { 1280, 1280, 1280 }, 2762 .hfront_porch = { 2, 30, 30 }, 2763 .hback_porch = { 6, 100, 100 }, 2764 .hsync_len = { 2, 30, 30 }, 2765 .vactive = { 800, 800, 800 }, 2766 .vfront_porch = { 5, 5, 5 }, 2767 .vback_porch = { 11, 11, 11 }, 2768 .vsync_len = { 7, 7, 7 }, 2769 }; 2770 2771 static const struct panel_desc nec_nl12880bc20_05 = { 2772 .timings = &nec_nl12880bc20_05_timing, 2773 .num_timings = 1, 2774 .bpc = 8, 2775 .size = { 2776 .width = 261, 2777 .height = 163, 2778 }, 2779 .delay = { 2780 .enable = 50, 2781 .disable = 50, 2782 }, 2783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2785 }; 2786 2787 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2788 .clock = 10870, 2789 .hdisplay = 480, 2790 .hsync_start = 480 + 2, 2791 .hsync_end = 480 + 2 + 41, 2792 .htotal = 480 + 2 + 41 + 2, 2793 .vdisplay = 272, 2794 .vsync_start = 272 + 2, 2795 .vsync_end = 272 + 2 + 4, 2796 .vtotal = 272 + 2 + 4 + 2, 2797 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2798 }; 2799 2800 static const struct panel_desc nec_nl4827hc19_05b = { 2801 .modes = &nec_nl4827hc19_05b_mode, 2802 .num_modes = 1, 2803 .bpc = 8, 2804 .size = { 2805 .width = 95, 2806 .height = 54, 2807 }, 2808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2809 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2810 }; 2811 2812 static const struct drm_display_mode netron_dy_e231732_mode = { 2813 .clock = 66000, 2814 .hdisplay = 1024, 2815 .hsync_start = 1024 + 160, 2816 .hsync_end = 1024 + 160 + 70, 2817 .htotal = 1024 + 160 + 70 + 90, 2818 .vdisplay = 600, 2819 .vsync_start = 600 + 127, 2820 .vsync_end = 600 + 127 + 20, 2821 .vtotal = 600 + 127 + 20 + 3, 2822 }; 2823 2824 static const struct panel_desc netron_dy_e231732 = { 2825 .modes = &netron_dy_e231732_mode, 2826 .num_modes = 1, 2827 .size = { 2828 .width = 154, 2829 .height = 87, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2832 }; 2833 2834 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2835 { 2836 .clock = 138500, 2837 .hdisplay = 1920, 2838 .hsync_start = 1920 + 48, 2839 .hsync_end = 1920 + 48 + 32, 2840 .htotal = 1920 + 48 + 32 + 80, 2841 .vdisplay = 1080, 2842 .vsync_start = 1080 + 3, 2843 .vsync_end = 1080 + 3 + 5, 2844 .vtotal = 1080 + 3 + 5 + 23, 2845 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2846 }, { 2847 .clock = 110920, 2848 .hdisplay = 1920, 2849 .hsync_start = 1920 + 48, 2850 .hsync_end = 1920 + 48 + 32, 2851 .htotal = 1920 + 48 + 32 + 80, 2852 .vdisplay = 1080, 2853 .vsync_start = 1080 + 3, 2854 .vsync_end = 1080 + 3 + 5, 2855 .vtotal = 1080 + 3 + 5 + 23, 2856 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2857 } 2858 }; 2859 2860 static const struct panel_desc neweast_wjfh116008a = { 2861 .modes = neweast_wjfh116008a_modes, 2862 .num_modes = 2, 2863 .bpc = 6, 2864 .size = { 2865 .width = 260, 2866 .height = 150, 2867 }, 2868 .delay = { 2869 .prepare = 110, 2870 .enable = 20, 2871 .unprepare = 500, 2872 }, 2873 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2874 .connector_type = DRM_MODE_CONNECTOR_eDP, 2875 }; 2876 2877 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2878 .clock = 9000, 2879 .hdisplay = 480, 2880 .hsync_start = 480 + 2, 2881 .hsync_end = 480 + 2 + 41, 2882 .htotal = 480 + 2 + 41 + 2, 2883 .vdisplay = 272, 2884 .vsync_start = 272 + 2, 2885 .vsync_end = 272 + 2 + 10, 2886 .vtotal = 272 + 2 + 10 + 2, 2887 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2888 }; 2889 2890 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2891 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2892 .num_modes = 1, 2893 .bpc = 8, 2894 .size = { 2895 .width = 95, 2896 .height = 54, 2897 }, 2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2900 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2901 .connector_type = DRM_MODE_CONNECTOR_DPI, 2902 }; 2903 2904 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2905 .pixelclock = { 130000000, 148350000, 163000000 }, 2906 .hactive = { 1920, 1920, 1920 }, 2907 .hfront_porch = { 80, 100, 100 }, 2908 .hback_porch = { 100, 120, 120 }, 2909 .hsync_len = { 50, 60, 60 }, 2910 .vactive = { 1080, 1080, 1080 }, 2911 .vfront_porch = { 12, 30, 30 }, 2912 .vback_porch = { 4, 10, 10 }, 2913 .vsync_len = { 4, 5, 5 }, 2914 }; 2915 2916 static const struct panel_desc nlt_nl192108ac18_02d = { 2917 .timings = &nlt_nl192108ac18_02d_timing, 2918 .num_timings = 1, 2919 .bpc = 8, 2920 .size = { 2921 .width = 344, 2922 .height = 194, 2923 }, 2924 .delay = { 2925 .unprepare = 500, 2926 }, 2927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2928 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2929 }; 2930 2931 static const struct drm_display_mode nvd_9128_mode = { 2932 .clock = 29500, 2933 .hdisplay = 800, 2934 .hsync_start = 800 + 130, 2935 .hsync_end = 800 + 130 + 98, 2936 .htotal = 800 + 0 + 130 + 98, 2937 .vdisplay = 480, 2938 .vsync_start = 480 + 10, 2939 .vsync_end = 480 + 10 + 50, 2940 .vtotal = 480 + 0 + 10 + 50, 2941 }; 2942 2943 static const struct panel_desc nvd_9128 = { 2944 .modes = &nvd_9128_mode, 2945 .num_modes = 1, 2946 .bpc = 8, 2947 .size = { 2948 .width = 156, 2949 .height = 88, 2950 }, 2951 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2952 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2953 }; 2954 2955 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2956 .pixelclock = { 30000000, 30000000, 40000000 }, 2957 .hactive = { 800, 800, 800 }, 2958 .hfront_porch = { 40, 40, 40 }, 2959 .hback_porch = { 40, 40, 40 }, 2960 .hsync_len = { 1, 48, 48 }, 2961 .vactive = { 480, 480, 480 }, 2962 .vfront_porch = { 13, 13, 13 }, 2963 .vback_porch = { 29, 29, 29 }, 2964 .vsync_len = { 3, 3, 3 }, 2965 .flags = DISPLAY_FLAGS_DE_HIGH, 2966 }; 2967 2968 static const struct panel_desc okaya_rs800480t_7x0gp = { 2969 .timings = &okaya_rs800480t_7x0gp_timing, 2970 .num_timings = 1, 2971 .bpc = 6, 2972 .size = { 2973 .width = 154, 2974 .height = 87, 2975 }, 2976 .delay = { 2977 .prepare = 41, 2978 .enable = 50, 2979 .unprepare = 41, 2980 .disable = 50, 2981 }, 2982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2983 }; 2984 2985 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2986 .clock = 9000, 2987 .hdisplay = 480, 2988 .hsync_start = 480 + 5, 2989 .hsync_end = 480 + 5 + 30, 2990 .htotal = 480 + 5 + 30 + 10, 2991 .vdisplay = 272, 2992 .vsync_start = 272 + 8, 2993 .vsync_end = 272 + 8 + 5, 2994 .vtotal = 272 + 8 + 5 + 3, 2995 }; 2996 2997 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2998 .modes = &olimex_lcd_olinuxino_43ts_mode, 2999 .num_modes = 1, 3000 .size = { 3001 .width = 95, 3002 .height = 54, 3003 }, 3004 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3005 }; 3006 3007 /* 3008 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3009 * pixel clocks, but this is the timing that was being used in the Adafruit 3010 * installation instructions. 3011 */ 3012 static const struct drm_display_mode ontat_yx700wv03_mode = { 3013 .clock = 29500, 3014 .hdisplay = 800, 3015 .hsync_start = 824, 3016 .hsync_end = 896, 3017 .htotal = 992, 3018 .vdisplay = 480, 3019 .vsync_start = 483, 3020 .vsync_end = 493, 3021 .vtotal = 500, 3022 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3023 }; 3024 3025 /* 3026 * Specification at: 3027 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3028 */ 3029 static const struct panel_desc ontat_yx700wv03 = { 3030 .modes = &ontat_yx700wv03_mode, 3031 .num_modes = 1, 3032 .bpc = 8, 3033 .size = { 3034 .width = 154, 3035 .height = 83, 3036 }, 3037 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3038 }; 3039 3040 static const struct drm_display_mode ortustech_com37h3m_mode = { 3041 .clock = 22230, 3042 .hdisplay = 480, 3043 .hsync_start = 480 + 40, 3044 .hsync_end = 480 + 40 + 10, 3045 .htotal = 480 + 40 + 10 + 40, 3046 .vdisplay = 640, 3047 .vsync_start = 640 + 4, 3048 .vsync_end = 640 + 4 + 2, 3049 .vtotal = 640 + 4 + 2 + 4, 3050 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3051 }; 3052 3053 static const struct panel_desc ortustech_com37h3m = { 3054 .modes = &ortustech_com37h3m_mode, 3055 .num_modes = 1, 3056 .bpc = 8, 3057 .size = { 3058 .width = 56, /* 56.16mm */ 3059 .height = 75, /* 74.88mm */ 3060 }, 3061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3062 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3063 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3064 }; 3065 3066 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3067 .clock = 25000, 3068 .hdisplay = 480, 3069 .hsync_start = 480 + 10, 3070 .hsync_end = 480 + 10 + 10, 3071 .htotal = 480 + 10 + 10 + 15, 3072 .vdisplay = 800, 3073 .vsync_start = 800 + 3, 3074 .vsync_end = 800 + 3 + 3, 3075 .vtotal = 800 + 3 + 3 + 3, 3076 }; 3077 3078 static const struct panel_desc ortustech_com43h4m85ulc = { 3079 .modes = &ortustech_com43h4m85ulc_mode, 3080 .num_modes = 1, 3081 .bpc = 6, 3082 .size = { 3083 .width = 56, 3084 .height = 93, 3085 }, 3086 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3088 .connector_type = DRM_MODE_CONNECTOR_DPI, 3089 }; 3090 3091 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3092 .clock = 33000, 3093 .hdisplay = 800, 3094 .hsync_start = 800 + 210, 3095 .hsync_end = 800 + 210 + 30, 3096 .htotal = 800 + 210 + 30 + 16, 3097 .vdisplay = 480, 3098 .vsync_start = 480 + 22, 3099 .vsync_end = 480 + 22 + 13, 3100 .vtotal = 480 + 22 + 13 + 10, 3101 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3102 }; 3103 3104 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3105 .modes = &osddisplays_osd070t1718_19ts_mode, 3106 .num_modes = 1, 3107 .bpc = 8, 3108 .size = { 3109 .width = 152, 3110 .height = 91, 3111 }, 3112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3114 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3115 .connector_type = DRM_MODE_CONNECTOR_DPI, 3116 }; 3117 3118 static const struct drm_display_mode pda_91_00156_a0_mode = { 3119 .clock = 33300, 3120 .hdisplay = 800, 3121 .hsync_start = 800 + 1, 3122 .hsync_end = 800 + 1 + 64, 3123 .htotal = 800 + 1 + 64 + 64, 3124 .vdisplay = 480, 3125 .vsync_start = 480 + 1, 3126 .vsync_end = 480 + 1 + 23, 3127 .vtotal = 480 + 1 + 23 + 22, 3128 }; 3129 3130 static const struct panel_desc pda_91_00156_a0 = { 3131 .modes = &pda_91_00156_a0_mode, 3132 .num_modes = 1, 3133 .size = { 3134 .width = 152, 3135 .height = 91, 3136 }, 3137 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3138 }; 3139 3140 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3141 .clock = 24750, 3142 .hdisplay = 800, 3143 .hsync_start = 800 + 54, 3144 .hsync_end = 800 + 54 + 2, 3145 .htotal = 800 + 54 + 2 + 44, 3146 .vdisplay = 480, 3147 .vsync_start = 480 + 49, 3148 .vsync_end = 480 + 49 + 2, 3149 .vtotal = 480 + 49 + 2 + 22, 3150 }; 3151 3152 static const struct panel_desc powertip_ph800480t013_idf02 = { 3153 .modes = &powertip_ph800480t013_idf02_mode, 3154 .num_modes = 1, 3155 .size = { 3156 .width = 152, 3157 .height = 91, 3158 }, 3159 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3160 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3161 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3163 .connector_type = DRM_MODE_CONNECTOR_DPI, 3164 }; 3165 3166 static const struct drm_display_mode qd43003c0_40_mode = { 3167 .clock = 9000, 3168 .hdisplay = 480, 3169 .hsync_start = 480 + 8, 3170 .hsync_end = 480 + 8 + 4, 3171 .htotal = 480 + 8 + 4 + 39, 3172 .vdisplay = 272, 3173 .vsync_start = 272 + 4, 3174 .vsync_end = 272 + 4 + 10, 3175 .vtotal = 272 + 4 + 10 + 2, 3176 }; 3177 3178 static const struct panel_desc qd43003c0_40 = { 3179 .modes = &qd43003c0_40_mode, 3180 .num_modes = 1, 3181 .bpc = 8, 3182 .size = { 3183 .width = 95, 3184 .height = 53, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3187 }; 3188 3189 static const struct display_timing rocktech_rk070er9427_timing = { 3190 .pixelclock = { 26400000, 33300000, 46800000 }, 3191 .hactive = { 800, 800, 800 }, 3192 .hfront_porch = { 16, 210, 354 }, 3193 .hback_porch = { 46, 46, 46 }, 3194 .hsync_len = { 1, 1, 1 }, 3195 .vactive = { 480, 480, 480 }, 3196 .vfront_porch = { 7, 22, 147 }, 3197 .vback_porch = { 23, 23, 23 }, 3198 .vsync_len = { 1, 1, 1 }, 3199 .flags = DISPLAY_FLAGS_DE_HIGH, 3200 }; 3201 3202 static const struct panel_desc rocktech_rk070er9427 = { 3203 .timings = &rocktech_rk070er9427_timing, 3204 .num_timings = 1, 3205 .bpc = 6, 3206 .size = { 3207 .width = 154, 3208 .height = 86, 3209 }, 3210 .delay = { 3211 .prepare = 41, 3212 .enable = 50, 3213 .unprepare = 41, 3214 .disable = 50, 3215 }, 3216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3217 }; 3218 3219 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3220 .clock = 71100, 3221 .hdisplay = 1280, 3222 .hsync_start = 1280 + 48, 3223 .hsync_end = 1280 + 48 + 32, 3224 .htotal = 1280 + 48 + 32 + 80, 3225 .vdisplay = 800, 3226 .vsync_start = 800 + 2, 3227 .vsync_end = 800 + 2 + 5, 3228 .vtotal = 800 + 2 + 5 + 16, 3229 }; 3230 3231 static const struct panel_desc rocktech_rk101ii01d_ct = { 3232 .modes = &rocktech_rk101ii01d_ct_mode, 3233 .num_modes = 1, 3234 .size = { 3235 .width = 217, 3236 .height = 136, 3237 }, 3238 .delay = { 3239 .prepare = 50, 3240 .disable = 50, 3241 }, 3242 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3245 }; 3246 3247 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3248 .clock = 271560, 3249 .hdisplay = 2560, 3250 .hsync_start = 2560 + 48, 3251 .hsync_end = 2560 + 48 + 32, 3252 .htotal = 2560 + 48 + 32 + 80, 3253 .vdisplay = 1600, 3254 .vsync_start = 1600 + 2, 3255 .vsync_end = 1600 + 2 + 5, 3256 .vtotal = 1600 + 2 + 5 + 57, 3257 }; 3258 3259 static const struct panel_desc samsung_lsn122dl01_c01 = { 3260 .modes = &samsung_lsn122dl01_c01_mode, 3261 .num_modes = 1, 3262 .size = { 3263 .width = 263, 3264 .height = 164, 3265 }, 3266 }; 3267 3268 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3269 .clock = 54030, 3270 .hdisplay = 1024, 3271 .hsync_start = 1024 + 24, 3272 .hsync_end = 1024 + 24 + 136, 3273 .htotal = 1024 + 24 + 136 + 160, 3274 .vdisplay = 600, 3275 .vsync_start = 600 + 3, 3276 .vsync_end = 600 + 3 + 6, 3277 .vtotal = 600 + 3 + 6 + 61, 3278 }; 3279 3280 static const struct panel_desc samsung_ltn101nt05 = { 3281 .modes = &samsung_ltn101nt05_mode, 3282 .num_modes = 1, 3283 .bpc = 6, 3284 .size = { 3285 .width = 223, 3286 .height = 125, 3287 }, 3288 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3289 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3290 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3291 }; 3292 3293 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3294 .clock = 76300, 3295 .hdisplay = 1366, 3296 .hsync_start = 1366 + 64, 3297 .hsync_end = 1366 + 64 + 48, 3298 .htotal = 1366 + 64 + 48 + 128, 3299 .vdisplay = 768, 3300 .vsync_start = 768 + 2, 3301 .vsync_end = 768 + 2 + 5, 3302 .vtotal = 768 + 2 + 5 + 17, 3303 }; 3304 3305 static const struct panel_desc samsung_ltn140at29_301 = { 3306 .modes = &samsung_ltn140at29_301_mode, 3307 .num_modes = 1, 3308 .bpc = 6, 3309 .size = { 3310 .width = 320, 3311 .height = 187, 3312 }, 3313 }; 3314 3315 static const struct display_timing satoz_sat050at40h12r2_timing = { 3316 .pixelclock = {33300000, 33300000, 50000000}, 3317 .hactive = {800, 800, 800}, 3318 .hfront_porch = {16, 210, 354}, 3319 .hback_porch = {46, 46, 46}, 3320 .hsync_len = {1, 1, 40}, 3321 .vactive = {480, 480, 480}, 3322 .vfront_porch = {7, 22, 147}, 3323 .vback_porch = {23, 23, 23}, 3324 .vsync_len = {1, 1, 20}, 3325 }; 3326 3327 static const struct panel_desc satoz_sat050at40h12r2 = { 3328 .timings = &satoz_sat050at40h12r2_timing, 3329 .num_timings = 1, 3330 .bpc = 8, 3331 .size = { 3332 .width = 108, 3333 .height = 65, 3334 }, 3335 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3336 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3337 }; 3338 3339 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3340 .clock = 168480, 3341 .hdisplay = 1920, 3342 .hsync_start = 1920 + 48, 3343 .hsync_end = 1920 + 48 + 32, 3344 .htotal = 1920 + 48 + 32 + 80, 3345 .vdisplay = 1280, 3346 .vsync_start = 1280 + 3, 3347 .vsync_end = 1280 + 3 + 10, 3348 .vtotal = 1280 + 3 + 10 + 57, 3349 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3350 }; 3351 3352 static const struct panel_desc sharp_ld_d5116z01b = { 3353 .modes = &sharp_ld_d5116z01b_mode, 3354 .num_modes = 1, 3355 .bpc = 8, 3356 .size = { 3357 .width = 260, 3358 .height = 120, 3359 }, 3360 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3361 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3362 }; 3363 3364 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3365 .clock = 33260, 3366 .hdisplay = 800, 3367 .hsync_start = 800 + 64, 3368 .hsync_end = 800 + 64 + 128, 3369 .htotal = 800 + 64 + 128 + 64, 3370 .vdisplay = 480, 3371 .vsync_start = 480 + 8, 3372 .vsync_end = 480 + 8 + 2, 3373 .vtotal = 480 + 8 + 2 + 35, 3374 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3375 }; 3376 3377 static const struct panel_desc sharp_lq070y3dg3b = { 3378 .modes = &sharp_lq070y3dg3b_mode, 3379 .num_modes = 1, 3380 .bpc = 8, 3381 .size = { 3382 .width = 152, /* 152.4mm */ 3383 .height = 91, /* 91.4mm */ 3384 }, 3385 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3386 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3387 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3388 }; 3389 3390 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3391 .clock = 5500, 3392 .hdisplay = 240, 3393 .hsync_start = 240 + 16, 3394 .hsync_end = 240 + 16 + 7, 3395 .htotal = 240 + 16 + 7 + 5, 3396 .vdisplay = 320, 3397 .vsync_start = 320 + 9, 3398 .vsync_end = 320 + 9 + 1, 3399 .vtotal = 320 + 9 + 1 + 7, 3400 }; 3401 3402 static const struct panel_desc sharp_lq035q7db03 = { 3403 .modes = &sharp_lq035q7db03_mode, 3404 .num_modes = 1, 3405 .bpc = 6, 3406 .size = { 3407 .width = 54, 3408 .height = 72, 3409 }, 3410 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3411 }; 3412 3413 static const struct display_timing sharp_lq101k1ly04_timing = { 3414 .pixelclock = { 60000000, 65000000, 80000000 }, 3415 .hactive = { 1280, 1280, 1280 }, 3416 .hfront_porch = { 20, 20, 20 }, 3417 .hback_porch = { 20, 20, 20 }, 3418 .hsync_len = { 10, 10, 10 }, 3419 .vactive = { 800, 800, 800 }, 3420 .vfront_porch = { 4, 4, 4 }, 3421 .vback_porch = { 4, 4, 4 }, 3422 .vsync_len = { 4, 4, 4 }, 3423 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3424 }; 3425 3426 static const struct panel_desc sharp_lq101k1ly04 = { 3427 .timings = &sharp_lq101k1ly04_timing, 3428 .num_timings = 1, 3429 .bpc = 8, 3430 .size = { 3431 .width = 217, 3432 .height = 136, 3433 }, 3434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3435 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3436 }; 3437 3438 static const struct display_timing sharp_lq123p1jx31_timing = { 3439 .pixelclock = { 252750000, 252750000, 266604720 }, 3440 .hactive = { 2400, 2400, 2400 }, 3441 .hfront_porch = { 48, 48, 48 }, 3442 .hback_porch = { 80, 80, 84 }, 3443 .hsync_len = { 32, 32, 32 }, 3444 .vactive = { 1600, 1600, 1600 }, 3445 .vfront_porch = { 3, 3, 3 }, 3446 .vback_porch = { 33, 33, 120 }, 3447 .vsync_len = { 10, 10, 10 }, 3448 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3449 }; 3450 3451 static const struct panel_desc sharp_lq123p1jx31 = { 3452 .timings = &sharp_lq123p1jx31_timing, 3453 .num_timings = 1, 3454 .bpc = 8, 3455 .size = { 3456 .width = 259, 3457 .height = 173, 3458 }, 3459 .delay = { 3460 .prepare = 110, 3461 .enable = 50, 3462 .unprepare = 550, 3463 }, 3464 }; 3465 3466 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3467 { /* 50 Hz */ 3468 .clock = 3000, 3469 .hdisplay = 240, 3470 .hsync_start = 240 + 58, 3471 .hsync_end = 240 + 58 + 1, 3472 .htotal = 240 + 58 + 1 + 1, 3473 .vdisplay = 160, 3474 .vsync_start = 160 + 24, 3475 .vsync_end = 160 + 24 + 10, 3476 .vtotal = 160 + 24 + 10 + 6, 3477 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3478 }, 3479 { /* 60 Hz */ 3480 .clock = 3000, 3481 .hdisplay = 240, 3482 .hsync_start = 240 + 8, 3483 .hsync_end = 240 + 8 + 1, 3484 .htotal = 240 + 8 + 1 + 1, 3485 .vdisplay = 160, 3486 .vsync_start = 160 + 24, 3487 .vsync_end = 160 + 24 + 10, 3488 .vtotal = 160 + 24 + 10 + 6, 3489 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3490 }, 3491 }; 3492 3493 static const struct panel_desc sharp_ls020b1dd01d = { 3494 .modes = sharp_ls020b1dd01d_modes, 3495 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3496 .bpc = 6, 3497 .size = { 3498 .width = 42, 3499 .height = 28, 3500 }, 3501 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3502 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3503 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3504 | DRM_BUS_FLAG_SHARP_SIGNALS, 3505 }; 3506 3507 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3508 .clock = 33300, 3509 .hdisplay = 800, 3510 .hsync_start = 800 + 1, 3511 .hsync_end = 800 + 1 + 64, 3512 .htotal = 800 + 1 + 64 + 64, 3513 .vdisplay = 480, 3514 .vsync_start = 480 + 1, 3515 .vsync_end = 480 + 1 + 23, 3516 .vtotal = 480 + 1 + 23 + 22, 3517 }; 3518 3519 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3520 .modes = &shelly_sca07010_bfn_lnn_mode, 3521 .num_modes = 1, 3522 .size = { 3523 .width = 152, 3524 .height = 91, 3525 }, 3526 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3527 }; 3528 3529 static const struct drm_display_mode starry_kr070pe2t_mode = { 3530 .clock = 33000, 3531 .hdisplay = 800, 3532 .hsync_start = 800 + 209, 3533 .hsync_end = 800 + 209 + 1, 3534 .htotal = 800 + 209 + 1 + 45, 3535 .vdisplay = 480, 3536 .vsync_start = 480 + 22, 3537 .vsync_end = 480 + 22 + 1, 3538 .vtotal = 480 + 22 + 1 + 22, 3539 }; 3540 3541 static const struct panel_desc starry_kr070pe2t = { 3542 .modes = &starry_kr070pe2t_mode, 3543 .num_modes = 1, 3544 .bpc = 8, 3545 .size = { 3546 .width = 152, 3547 .height = 86, 3548 }, 3549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3550 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3551 .connector_type = DRM_MODE_CONNECTOR_DPI, 3552 }; 3553 3554 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3555 .clock = 147000, 3556 .hdisplay = 1920, 3557 .hsync_start = 1920 + 16, 3558 .hsync_end = 1920 + 16 + 16, 3559 .htotal = 1920 + 16 + 16 + 32, 3560 .vdisplay = 1200, 3561 .vsync_start = 1200 + 15, 3562 .vsync_end = 1200 + 15 + 2, 3563 .vtotal = 1200 + 15 + 2 + 18, 3564 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3565 }; 3566 3567 static const struct panel_desc starry_kr122ea0sra = { 3568 .modes = &starry_kr122ea0sra_mode, 3569 .num_modes = 1, 3570 .size = { 3571 .width = 263, 3572 .height = 164, 3573 }, 3574 .delay = { 3575 .prepare = 10 + 200, 3576 .enable = 50, 3577 .unprepare = 10 + 500, 3578 }, 3579 }; 3580 3581 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3582 .clock = 30000, 3583 .hdisplay = 800, 3584 .hsync_start = 800 + 39, 3585 .hsync_end = 800 + 39 + 47, 3586 .htotal = 800 + 39 + 47 + 39, 3587 .vdisplay = 480, 3588 .vsync_start = 480 + 13, 3589 .vsync_end = 480 + 13 + 2, 3590 .vtotal = 480 + 13 + 2 + 29, 3591 }; 3592 3593 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3594 .modes = &tfc_s9700rtwv43tr_01b_mode, 3595 .num_modes = 1, 3596 .bpc = 8, 3597 .size = { 3598 .width = 155, 3599 .height = 90, 3600 }, 3601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3602 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3603 }; 3604 3605 static const struct display_timing tianma_tm070jdhg30_timing = { 3606 .pixelclock = { 62600000, 68200000, 78100000 }, 3607 .hactive = { 1280, 1280, 1280 }, 3608 .hfront_porch = { 15, 64, 159 }, 3609 .hback_porch = { 5, 5, 5 }, 3610 .hsync_len = { 1, 1, 256 }, 3611 .vactive = { 800, 800, 800 }, 3612 .vfront_porch = { 3, 40, 99 }, 3613 .vback_porch = { 2, 2, 2 }, 3614 .vsync_len = { 1, 1, 128 }, 3615 .flags = DISPLAY_FLAGS_DE_HIGH, 3616 }; 3617 3618 static const struct panel_desc tianma_tm070jdhg30 = { 3619 .timings = &tianma_tm070jdhg30_timing, 3620 .num_timings = 1, 3621 .bpc = 8, 3622 .size = { 3623 .width = 151, 3624 .height = 95, 3625 }, 3626 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3627 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3628 }; 3629 3630 static const struct panel_desc tianma_tm070jvhg33 = { 3631 .timings = &tianma_tm070jdhg30_timing, 3632 .num_timings = 1, 3633 .bpc = 8, 3634 .size = { 3635 .width = 150, 3636 .height = 94, 3637 }, 3638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3639 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3640 }; 3641 3642 static const struct display_timing tianma_tm070rvhg71_timing = { 3643 .pixelclock = { 27700000, 29200000, 39600000 }, 3644 .hactive = { 800, 800, 800 }, 3645 .hfront_porch = { 12, 40, 212 }, 3646 .hback_porch = { 88, 88, 88 }, 3647 .hsync_len = { 1, 1, 40 }, 3648 .vactive = { 480, 480, 480 }, 3649 .vfront_porch = { 1, 13, 88 }, 3650 .vback_porch = { 32, 32, 32 }, 3651 .vsync_len = { 1, 1, 3 }, 3652 .flags = DISPLAY_FLAGS_DE_HIGH, 3653 }; 3654 3655 static const struct panel_desc tianma_tm070rvhg71 = { 3656 .timings = &tianma_tm070rvhg71_timing, 3657 .num_timings = 1, 3658 .bpc = 8, 3659 .size = { 3660 .width = 154, 3661 .height = 86, 3662 }, 3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3664 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3665 }; 3666 3667 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3668 { 3669 .clock = 10000, 3670 .hdisplay = 320, 3671 .hsync_start = 320 + 50, 3672 .hsync_end = 320 + 50 + 6, 3673 .htotal = 320 + 50 + 6 + 38, 3674 .vdisplay = 240, 3675 .vsync_start = 240 + 3, 3676 .vsync_end = 240 + 3 + 1, 3677 .vtotal = 240 + 3 + 1 + 17, 3678 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3679 }, 3680 }; 3681 3682 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3683 .modes = ti_nspire_cx_lcd_mode, 3684 .num_modes = 1, 3685 .bpc = 8, 3686 .size = { 3687 .width = 65, 3688 .height = 49, 3689 }, 3690 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3691 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3692 }; 3693 3694 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3695 { 3696 .clock = 10000, 3697 .hdisplay = 320, 3698 .hsync_start = 320 + 6, 3699 .hsync_end = 320 + 6 + 6, 3700 .htotal = 320 + 6 + 6 + 6, 3701 .vdisplay = 240, 3702 .vsync_start = 240 + 0, 3703 .vsync_end = 240 + 0 + 1, 3704 .vtotal = 240 + 0 + 1 + 0, 3705 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3706 }, 3707 }; 3708 3709 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3710 .modes = ti_nspire_classic_lcd_mode, 3711 .num_modes = 1, 3712 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3713 .bpc = 8, 3714 .size = { 3715 .width = 71, 3716 .height = 53, 3717 }, 3718 /* This is the grayscale bus format */ 3719 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3720 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3721 }; 3722 3723 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3724 .clock = 79500, 3725 .hdisplay = 1280, 3726 .hsync_start = 1280 + 192, 3727 .hsync_end = 1280 + 192 + 128, 3728 .htotal = 1280 + 192 + 128 + 64, 3729 .vdisplay = 768, 3730 .vsync_start = 768 + 20, 3731 .vsync_end = 768 + 20 + 7, 3732 .vtotal = 768 + 20 + 7 + 3, 3733 }; 3734 3735 static const struct panel_desc toshiba_lt089ac29000 = { 3736 .modes = &toshiba_lt089ac29000_mode, 3737 .num_modes = 1, 3738 .size = { 3739 .width = 194, 3740 .height = 116, 3741 }, 3742 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3743 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3744 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3745 }; 3746 3747 static const struct drm_display_mode tpk_f07a_0102_mode = { 3748 .clock = 33260, 3749 .hdisplay = 800, 3750 .hsync_start = 800 + 40, 3751 .hsync_end = 800 + 40 + 128, 3752 .htotal = 800 + 40 + 128 + 88, 3753 .vdisplay = 480, 3754 .vsync_start = 480 + 10, 3755 .vsync_end = 480 + 10 + 2, 3756 .vtotal = 480 + 10 + 2 + 33, 3757 }; 3758 3759 static const struct panel_desc tpk_f07a_0102 = { 3760 .modes = &tpk_f07a_0102_mode, 3761 .num_modes = 1, 3762 .size = { 3763 .width = 152, 3764 .height = 91, 3765 }, 3766 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3767 }; 3768 3769 static const struct drm_display_mode tpk_f10a_0102_mode = { 3770 .clock = 45000, 3771 .hdisplay = 1024, 3772 .hsync_start = 1024 + 176, 3773 .hsync_end = 1024 + 176 + 5, 3774 .htotal = 1024 + 176 + 5 + 88, 3775 .vdisplay = 600, 3776 .vsync_start = 600 + 20, 3777 .vsync_end = 600 + 20 + 5, 3778 .vtotal = 600 + 20 + 5 + 25, 3779 }; 3780 3781 static const struct panel_desc tpk_f10a_0102 = { 3782 .modes = &tpk_f10a_0102_mode, 3783 .num_modes = 1, 3784 .size = { 3785 .width = 223, 3786 .height = 125, 3787 }, 3788 }; 3789 3790 static const struct display_timing urt_umsh_8596md_timing = { 3791 .pixelclock = { 33260000, 33260000, 33260000 }, 3792 .hactive = { 800, 800, 800 }, 3793 .hfront_porch = { 41, 41, 41 }, 3794 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3795 .hsync_len = { 71, 128, 128 }, 3796 .vactive = { 480, 480, 480 }, 3797 .vfront_porch = { 10, 10, 10 }, 3798 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3799 .vsync_len = { 2, 2, 2 }, 3800 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3801 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3802 }; 3803 3804 static const struct panel_desc urt_umsh_8596md_lvds = { 3805 .timings = &urt_umsh_8596md_timing, 3806 .num_timings = 1, 3807 .bpc = 6, 3808 .size = { 3809 .width = 152, 3810 .height = 91, 3811 }, 3812 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3813 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3814 }; 3815 3816 static const struct panel_desc urt_umsh_8596md_parallel = { 3817 .timings = &urt_umsh_8596md_timing, 3818 .num_timings = 1, 3819 .bpc = 6, 3820 .size = { 3821 .width = 152, 3822 .height = 91, 3823 }, 3824 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3825 }; 3826 3827 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3828 .clock = 33333, 3829 .hdisplay = 800, 3830 .hsync_start = 800 + 210, 3831 .hsync_end = 800 + 210 + 20, 3832 .htotal = 800 + 210 + 20 + 46, 3833 .vdisplay = 480, 3834 .vsync_start = 480 + 22, 3835 .vsync_end = 480 + 22 + 10, 3836 .vtotal = 480 + 22 + 10 + 23, 3837 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3838 }; 3839 3840 static const struct panel_desc vl050_8048nt_c01 = { 3841 .modes = &vl050_8048nt_c01_mode, 3842 .num_modes = 1, 3843 .bpc = 8, 3844 .size = { 3845 .width = 120, 3846 .height = 76, 3847 }, 3848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3850 }; 3851 3852 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3853 .clock = 6410, 3854 .hdisplay = 320, 3855 .hsync_start = 320 + 20, 3856 .hsync_end = 320 + 20 + 30, 3857 .htotal = 320 + 20 + 30 + 38, 3858 .vdisplay = 240, 3859 .vsync_start = 240 + 4, 3860 .vsync_end = 240 + 4 + 3, 3861 .vtotal = 240 + 4 + 3 + 15, 3862 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3863 }; 3864 3865 static const struct panel_desc winstar_wf35ltiacd = { 3866 .modes = &winstar_wf35ltiacd_mode, 3867 .num_modes = 1, 3868 .bpc = 8, 3869 .size = { 3870 .width = 70, 3871 .height = 53, 3872 }, 3873 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3874 }; 3875 3876 static const struct drm_display_mode arm_rtsm_mode[] = { 3877 { 3878 .clock = 65000, 3879 .hdisplay = 1024, 3880 .hsync_start = 1024 + 24, 3881 .hsync_end = 1024 + 24 + 136, 3882 .htotal = 1024 + 24 + 136 + 160, 3883 .vdisplay = 768, 3884 .vsync_start = 768 + 3, 3885 .vsync_end = 768 + 3 + 6, 3886 .vtotal = 768 + 3 + 6 + 29, 3887 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3888 }, 3889 }; 3890 3891 static const struct panel_desc arm_rtsm = { 3892 .modes = arm_rtsm_mode, 3893 .num_modes = 1, 3894 .bpc = 8, 3895 .size = { 3896 .width = 400, 3897 .height = 300, 3898 }, 3899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3900 }; 3901 3902 static const struct of_device_id platform_of_match[] = { 3903 { 3904 .compatible = "ampire,am-1280800n3tzqw-t00h", 3905 .data = &ire_am_1280800n3tzqw_t00h, 3906 }, { 3907 .compatible = "ampire,am-480272h3tmqw-t01h", 3908 .data = &ire_am_480272h3tmqw_t01h, 3909 }, { 3910 .compatible = "ampire,am800480r3tmqwa1h", 3911 .data = &ire_am800480r3tmqwa1h, 3912 }, { 3913 .compatible = "arm,rtsm-display", 3914 .data = &arm_rtsm, 3915 }, { 3916 .compatible = "armadeus,st0700-adapt", 3917 .data = &armadeus_st0700_adapt, 3918 }, { 3919 .compatible = "auo,b101aw03", 3920 .data = &auo_b101aw03, 3921 }, { 3922 .compatible = "auo,b101ean01", 3923 .data = &auo_b101ean01, 3924 }, { 3925 .compatible = "auo,b101xtn01", 3926 .data = &auo_b101xtn01, 3927 }, { 3928 .compatible = "auo,b116xa01", 3929 .data = &auo_b116xak01, 3930 }, { 3931 .compatible = "auo,b116xw03", 3932 .data = &auo_b116xw03, 3933 }, { 3934 .compatible = "auo,b133htn01", 3935 .data = &auo_b133htn01, 3936 }, { 3937 .compatible = "auo,b133xtn01", 3938 .data = &auo_b133xtn01, 3939 }, { 3940 .compatible = "auo,g070vvn01", 3941 .data = &auo_g070vvn01, 3942 }, { 3943 .compatible = "auo,g101evn010", 3944 .data = &auo_g101evn010, 3945 }, { 3946 .compatible = "auo,g104sn02", 3947 .data = &auo_g104sn02, 3948 }, { 3949 .compatible = "auo,g121ean01", 3950 .data = &auo_g121ean01, 3951 }, { 3952 .compatible = "auo,g133han01", 3953 .data = &auo_g133han01, 3954 }, { 3955 .compatible = "auo,g156xtn01", 3956 .data = &auo_g156xtn01, 3957 }, { 3958 .compatible = "auo,g185han01", 3959 .data = &auo_g185han01, 3960 }, { 3961 .compatible = "auo,g190ean01", 3962 .data = &auo_g190ean01, 3963 }, { 3964 .compatible = "auo,p320hvn03", 3965 .data = &auo_p320hvn03, 3966 }, { 3967 .compatible = "auo,t215hvn01", 3968 .data = &auo_t215hvn01, 3969 }, { 3970 .compatible = "avic,tm070ddh03", 3971 .data = &avic_tm070ddh03, 3972 }, { 3973 .compatible = "bananapi,s070wv20-ct16", 3974 .data = &bananapi_s070wv20_ct16, 3975 }, { 3976 .compatible = "boe,hv070wsa-100", 3977 .data = &boe_hv070wsa 3978 }, { 3979 .compatible = "boe,nv101wxmn51", 3980 .data = &boe_nv101wxmn51, 3981 }, { 3982 .compatible = "boe,nv133fhm-n61", 3983 .data = &boe_nv133fhm_n61, 3984 }, { 3985 .compatible = "boe,nv133fhm-n62", 3986 .data = &boe_nv133fhm_n61, 3987 }, { 3988 .compatible = "boe,nv140fhmn49", 3989 .data = &boe_nv140fhmn49, 3990 }, { 3991 .compatible = "cdtech,s043wq26h-ct7", 3992 .data = &cdtech_s043wq26h_ct7, 3993 }, { 3994 .compatible = "cdtech,s070pws19hp-fc21", 3995 .data = &cdtech_s070pws19hp_fc21, 3996 }, { 3997 .compatible = "cdtech,s070swv29hg-dc44", 3998 .data = &cdtech_s070swv29hg_dc44, 3999 }, { 4000 .compatible = "cdtech,s070wv95-ct16", 4001 .data = &cdtech_s070wv95_ct16, 4002 }, { 4003 .compatible = "chefree,ch101olhlwh-002", 4004 .data = &chefree_ch101olhlwh_002, 4005 }, { 4006 .compatible = "chunghwa,claa070wp03xg", 4007 .data = &chunghwa_claa070wp03xg, 4008 }, { 4009 .compatible = "chunghwa,claa101wa01a", 4010 .data = &chunghwa_claa101wa01a 4011 }, { 4012 .compatible = "chunghwa,claa101wb01", 4013 .data = &chunghwa_claa101wb01 4014 }, { 4015 .compatible = "dataimage,scf0700c48ggu18", 4016 .data = &dataimage_scf0700c48ggu18, 4017 }, { 4018 .compatible = "dlc,dlc0700yzg-1", 4019 .data = &dlc_dlc0700yzg_1, 4020 }, { 4021 .compatible = "dlc,dlc1010gig", 4022 .data = &dlc_dlc1010gig, 4023 }, { 4024 .compatible = "edt,et035012dm6", 4025 .data = &edt_et035012dm6, 4026 }, { 4027 .compatible = "edt,etm043080dh6gp", 4028 .data = &edt_etm043080dh6gp, 4029 }, { 4030 .compatible = "edt,etm0430g0dh6", 4031 .data = &edt_etm0430g0dh6, 4032 }, { 4033 .compatible = "edt,et057090dhu", 4034 .data = &edt_et057090dhu, 4035 }, { 4036 .compatible = "edt,et070080dh6", 4037 .data = &edt_etm0700g0dh6, 4038 }, { 4039 .compatible = "edt,etm0700g0dh6", 4040 .data = &edt_etm0700g0dh6, 4041 }, { 4042 .compatible = "edt,etm0700g0bdh6", 4043 .data = &edt_etm0700g0bdh6, 4044 }, { 4045 .compatible = "edt,etm0700g0edh6", 4046 .data = &edt_etm0700g0bdh6, 4047 }, { 4048 .compatible = "evervision,vgg804821", 4049 .data = &evervision_vgg804821, 4050 }, { 4051 .compatible = "foxlink,fl500wvr00-a0t", 4052 .data = &foxlink_fl500wvr00_a0t, 4053 }, { 4054 .compatible = "frida,frd350h54004", 4055 .data = &frida_frd350h54004, 4056 }, { 4057 .compatible = "friendlyarm,hd702e", 4058 .data = &friendlyarm_hd702e, 4059 }, { 4060 .compatible = "giantplus,gpg482739qs5", 4061 .data = &giantplus_gpg482739qs5 4062 }, { 4063 .compatible = "giantplus,gpm940b0", 4064 .data = &giantplus_gpm940b0, 4065 }, { 4066 .compatible = "hannstar,hsd070pww1", 4067 .data = &hannstar_hsd070pww1, 4068 }, { 4069 .compatible = "hannstar,hsd100pxn1", 4070 .data = &hannstar_hsd100pxn1, 4071 }, { 4072 .compatible = "hit,tx23d38vm0caa", 4073 .data = &hitachi_tx23d38vm0caa 4074 }, { 4075 .compatible = "innolux,at043tn24", 4076 .data = &innolux_at043tn24, 4077 }, { 4078 .compatible = "innolux,at070tn92", 4079 .data = &innolux_at070tn92, 4080 }, { 4081 .compatible = "innolux,g070y2-l01", 4082 .data = &innolux_g070y2_l01, 4083 }, { 4084 .compatible = "innolux,g101ice-l01", 4085 .data = &innolux_g101ice_l01 4086 }, { 4087 .compatible = "innolux,g121i1-l01", 4088 .data = &innolux_g121i1_l01 4089 }, { 4090 .compatible = "innolux,g121x1-l03", 4091 .data = &innolux_g121x1_l03, 4092 }, { 4093 .compatible = "innolux,n116bge", 4094 .data = &innolux_n116bge, 4095 }, { 4096 .compatible = "innolux,n156bge-l21", 4097 .data = &innolux_n156bge_l21, 4098 }, { 4099 .compatible = "innolux,p120zdg-bf1", 4100 .data = &innolux_p120zdg_bf1, 4101 }, { 4102 .compatible = "innolux,zj070na-01p", 4103 .data = &innolux_zj070na_01p, 4104 }, { 4105 .compatible = "ivo,m133nwf4-r0", 4106 .data = &ivo_m133nwf4_r0, 4107 }, { 4108 .compatible = "kingdisplay,kd116n21-30nv-a010", 4109 .data = &kingdisplay_kd116n21_30nv_a010, 4110 }, { 4111 .compatible = "koe,tx14d24vm1bpa", 4112 .data = &koe_tx14d24vm1bpa, 4113 }, { 4114 .compatible = "koe,tx26d202vm0bwa", 4115 .data = &koe_tx26d202vm0bwa, 4116 }, { 4117 .compatible = "koe,tx31d200vm0baa", 4118 .data = &koe_tx31d200vm0baa, 4119 }, { 4120 .compatible = "kyo,tcg121xglp", 4121 .data = &kyo_tcg121xglp, 4122 }, { 4123 .compatible = "lemaker,bl035-rgb-002", 4124 .data = &lemaker_bl035_rgb_002, 4125 }, { 4126 .compatible = "lg,lb070wv8", 4127 .data = &lg_lb070wv8, 4128 }, { 4129 .compatible = "lg,lp079qx1-sp0v", 4130 .data = &lg_lp079qx1_sp0v, 4131 }, { 4132 .compatible = "lg,lp097qx1-spa1", 4133 .data = &lg_lp097qx1_spa1, 4134 }, { 4135 .compatible = "lg,lp120up1", 4136 .data = &lg_lp120up1, 4137 }, { 4138 .compatible = "lg,lp129qe", 4139 .data = &lg_lp129qe, 4140 }, { 4141 .compatible = "logicpd,type28", 4142 .data = &logicpd_type_28, 4143 }, { 4144 .compatible = "logictechno,lt161010-2nhc", 4145 .data = &logictechno_lt161010_2nh, 4146 }, { 4147 .compatible = "logictechno,lt161010-2nhr", 4148 .data = &logictechno_lt161010_2nh, 4149 }, { 4150 .compatible = "logictechno,lt170410-2whc", 4151 .data = &logictechno_lt170410_2whc, 4152 }, { 4153 .compatible = "mitsubishi,aa070mc01-ca1", 4154 .data = &mitsubishi_aa070mc01, 4155 }, { 4156 .compatible = "nec,nl12880bc20-05", 4157 .data = &nec_nl12880bc20_05, 4158 }, { 4159 .compatible = "nec,nl4827hc19-05b", 4160 .data = &nec_nl4827hc19_05b, 4161 }, { 4162 .compatible = "netron-dy,e231732", 4163 .data = &netron_dy_e231732, 4164 }, { 4165 .compatible = "neweast,wjfh116008a", 4166 .data = &neweast_wjfh116008a, 4167 }, { 4168 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4169 .data = &newhaven_nhd_43_480272ef_atxl, 4170 }, { 4171 .compatible = "nlt,nl192108ac18-02d", 4172 .data = &nlt_nl192108ac18_02d, 4173 }, { 4174 .compatible = "nvd,9128", 4175 .data = &nvd_9128, 4176 }, { 4177 .compatible = "okaya,rs800480t-7x0gp", 4178 .data = &okaya_rs800480t_7x0gp, 4179 }, { 4180 .compatible = "olimex,lcd-olinuxino-43-ts", 4181 .data = &olimex_lcd_olinuxino_43ts, 4182 }, { 4183 .compatible = "ontat,yx700wv03", 4184 .data = &ontat_yx700wv03, 4185 }, { 4186 .compatible = "ortustech,com37h3m05dtc", 4187 .data = &ortustech_com37h3m, 4188 }, { 4189 .compatible = "ortustech,com37h3m99dtc", 4190 .data = &ortustech_com37h3m, 4191 }, { 4192 .compatible = "ortustech,com43h4m85ulc", 4193 .data = &ortustech_com43h4m85ulc, 4194 }, { 4195 .compatible = "osddisplays,osd070t1718-19ts", 4196 .data = &osddisplays_osd070t1718_19ts, 4197 }, { 4198 .compatible = "pda,91-00156-a0", 4199 .data = &pda_91_00156_a0, 4200 }, { 4201 .compatible = "powertip,ph800480t013-idf02", 4202 .data = &powertip_ph800480t013_idf02, 4203 }, { 4204 .compatible = "qiaodian,qd43003c0-40", 4205 .data = &qd43003c0_40, 4206 }, { 4207 .compatible = "rocktech,rk070er9427", 4208 .data = &rocktech_rk070er9427, 4209 }, { 4210 .compatible = "rocktech,rk101ii01d-ct", 4211 .data = &rocktech_rk101ii01d_ct, 4212 }, { 4213 .compatible = "samsung,lsn122dl01-c01", 4214 .data = &samsung_lsn122dl01_c01, 4215 }, { 4216 .compatible = "samsung,ltn101nt05", 4217 .data = &samsung_ltn101nt05, 4218 }, { 4219 .compatible = "samsung,ltn140at29-301", 4220 .data = &samsung_ltn140at29_301, 4221 }, { 4222 .compatible = "satoz,sat050at40h12r2", 4223 .data = &satoz_sat050at40h12r2, 4224 }, { 4225 .compatible = "sharp,ld-d5116z01b", 4226 .data = &sharp_ld_d5116z01b, 4227 }, { 4228 .compatible = "sharp,lq035q7db03", 4229 .data = &sharp_lq035q7db03, 4230 }, { 4231 .compatible = "sharp,lq070y3dg3b", 4232 .data = &sharp_lq070y3dg3b, 4233 }, { 4234 .compatible = "sharp,lq101k1ly04", 4235 .data = &sharp_lq101k1ly04, 4236 }, { 4237 .compatible = "sharp,lq123p1jx31", 4238 .data = &sharp_lq123p1jx31, 4239 }, { 4240 .compatible = "sharp,ls020b1dd01d", 4241 .data = &sharp_ls020b1dd01d, 4242 }, { 4243 .compatible = "shelly,sca07010-bfn-lnn", 4244 .data = &shelly_sca07010_bfn_lnn, 4245 }, { 4246 .compatible = "starry,kr070pe2t", 4247 .data = &starry_kr070pe2t, 4248 }, { 4249 .compatible = "starry,kr122ea0sra", 4250 .data = &starry_kr122ea0sra, 4251 }, { 4252 .compatible = "tfc,s9700rtwv43tr-01b", 4253 .data = &tfc_s9700rtwv43tr_01b, 4254 }, { 4255 .compatible = "tianma,tm070jdhg30", 4256 .data = &tianma_tm070jdhg30, 4257 }, { 4258 .compatible = "tianma,tm070jvhg33", 4259 .data = &tianma_tm070jvhg33, 4260 }, { 4261 .compatible = "tianma,tm070rvhg71", 4262 .data = &tianma_tm070rvhg71, 4263 }, { 4264 .compatible = "ti,nspire-cx-lcd-panel", 4265 .data = &ti_nspire_cx_lcd_panel, 4266 }, { 4267 .compatible = "ti,nspire-classic-lcd-panel", 4268 .data = &ti_nspire_classic_lcd_panel, 4269 }, { 4270 .compatible = "toshiba,lt089ac29000", 4271 .data = &toshiba_lt089ac29000, 4272 }, { 4273 .compatible = "tpk,f07a-0102", 4274 .data = &tpk_f07a_0102, 4275 }, { 4276 .compatible = "tpk,f10a-0102", 4277 .data = &tpk_f10a_0102, 4278 }, { 4279 .compatible = "urt,umsh-8596md-t", 4280 .data = &urt_umsh_8596md_parallel, 4281 }, { 4282 .compatible = "urt,umsh-8596md-1t", 4283 .data = &urt_umsh_8596md_parallel, 4284 }, { 4285 .compatible = "urt,umsh-8596md-7t", 4286 .data = &urt_umsh_8596md_parallel, 4287 }, { 4288 .compatible = "urt,umsh-8596md-11t", 4289 .data = &urt_umsh_8596md_lvds, 4290 }, { 4291 .compatible = "urt,umsh-8596md-19t", 4292 .data = &urt_umsh_8596md_lvds, 4293 }, { 4294 .compatible = "urt,umsh-8596md-20t", 4295 .data = &urt_umsh_8596md_parallel, 4296 }, { 4297 .compatible = "vxt,vl050-8048nt-c01", 4298 .data = &vl050_8048nt_c01, 4299 }, { 4300 .compatible = "winstar,wf35ltiacd", 4301 .data = &winstar_wf35ltiacd, 4302 }, { 4303 /* Must be the last entry */ 4304 .compatible = "panel-dpi", 4305 .data = &panel_dpi, 4306 }, { 4307 /* sentinel */ 4308 } 4309 }; 4310 MODULE_DEVICE_TABLE(of, platform_of_match); 4311 4312 static int panel_simple_platform_probe(struct platform_device *pdev) 4313 { 4314 const struct of_device_id *id; 4315 4316 id = of_match_node(platform_of_match, pdev->dev.of_node); 4317 if (!id) 4318 return -ENODEV; 4319 4320 return panel_simple_probe(&pdev->dev, id->data); 4321 } 4322 4323 static int panel_simple_platform_remove(struct platform_device *pdev) 4324 { 4325 return panel_simple_remove(&pdev->dev); 4326 } 4327 4328 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4329 { 4330 panel_simple_shutdown(&pdev->dev); 4331 } 4332 4333 static struct platform_driver panel_simple_platform_driver = { 4334 .driver = { 4335 .name = "panel-simple", 4336 .of_match_table = platform_of_match, 4337 }, 4338 .probe = panel_simple_platform_probe, 4339 .remove = panel_simple_platform_remove, 4340 .shutdown = panel_simple_platform_shutdown, 4341 }; 4342 4343 struct panel_desc_dsi { 4344 struct panel_desc desc; 4345 4346 unsigned long flags; 4347 enum mipi_dsi_pixel_format format; 4348 unsigned int lanes; 4349 }; 4350 4351 static const struct drm_display_mode auo_b080uan01_mode = { 4352 .clock = 154500, 4353 .hdisplay = 1200, 4354 .hsync_start = 1200 + 62, 4355 .hsync_end = 1200 + 62 + 4, 4356 .htotal = 1200 + 62 + 4 + 62, 4357 .vdisplay = 1920, 4358 .vsync_start = 1920 + 9, 4359 .vsync_end = 1920 + 9 + 2, 4360 .vtotal = 1920 + 9 + 2 + 8, 4361 }; 4362 4363 static const struct panel_desc_dsi auo_b080uan01 = { 4364 .desc = { 4365 .modes = &auo_b080uan01_mode, 4366 .num_modes = 1, 4367 .bpc = 8, 4368 .size = { 4369 .width = 108, 4370 .height = 272, 4371 }, 4372 .connector_type = DRM_MODE_CONNECTOR_DSI, 4373 }, 4374 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4375 .format = MIPI_DSI_FMT_RGB888, 4376 .lanes = 4, 4377 }; 4378 4379 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4380 .clock = 160000, 4381 .hdisplay = 1200, 4382 .hsync_start = 1200 + 120, 4383 .hsync_end = 1200 + 120 + 20, 4384 .htotal = 1200 + 120 + 20 + 21, 4385 .vdisplay = 1920, 4386 .vsync_start = 1920 + 21, 4387 .vsync_end = 1920 + 21 + 3, 4388 .vtotal = 1920 + 21 + 3 + 18, 4389 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4390 }; 4391 4392 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4393 .desc = { 4394 .modes = &boe_tv080wum_nl0_mode, 4395 .num_modes = 1, 4396 .size = { 4397 .width = 107, 4398 .height = 172, 4399 }, 4400 .connector_type = DRM_MODE_CONNECTOR_DSI, 4401 }, 4402 .flags = MIPI_DSI_MODE_VIDEO | 4403 MIPI_DSI_MODE_VIDEO_BURST | 4404 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4405 .format = MIPI_DSI_FMT_RGB888, 4406 .lanes = 4, 4407 }; 4408 4409 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4410 .clock = 71000, 4411 .hdisplay = 800, 4412 .hsync_start = 800 + 32, 4413 .hsync_end = 800 + 32 + 1, 4414 .htotal = 800 + 32 + 1 + 57, 4415 .vdisplay = 1280, 4416 .vsync_start = 1280 + 28, 4417 .vsync_end = 1280 + 28 + 1, 4418 .vtotal = 1280 + 28 + 1 + 14, 4419 }; 4420 4421 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4422 .desc = { 4423 .modes = &lg_ld070wx3_sl01_mode, 4424 .num_modes = 1, 4425 .bpc = 8, 4426 .size = { 4427 .width = 94, 4428 .height = 151, 4429 }, 4430 .connector_type = DRM_MODE_CONNECTOR_DSI, 4431 }, 4432 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4433 .format = MIPI_DSI_FMT_RGB888, 4434 .lanes = 4, 4435 }; 4436 4437 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4438 .clock = 67000, 4439 .hdisplay = 720, 4440 .hsync_start = 720 + 12, 4441 .hsync_end = 720 + 12 + 4, 4442 .htotal = 720 + 12 + 4 + 112, 4443 .vdisplay = 1280, 4444 .vsync_start = 1280 + 8, 4445 .vsync_end = 1280 + 8 + 4, 4446 .vtotal = 1280 + 8 + 4 + 12, 4447 }; 4448 4449 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4450 .desc = { 4451 .modes = &lg_lh500wx1_sd03_mode, 4452 .num_modes = 1, 4453 .bpc = 8, 4454 .size = { 4455 .width = 62, 4456 .height = 110, 4457 }, 4458 .connector_type = DRM_MODE_CONNECTOR_DSI, 4459 }, 4460 .flags = MIPI_DSI_MODE_VIDEO, 4461 .format = MIPI_DSI_FMT_RGB888, 4462 .lanes = 4, 4463 }; 4464 4465 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4466 .clock = 157200, 4467 .hdisplay = 1920, 4468 .hsync_start = 1920 + 154, 4469 .hsync_end = 1920 + 154 + 16, 4470 .htotal = 1920 + 154 + 16 + 32, 4471 .vdisplay = 1200, 4472 .vsync_start = 1200 + 17, 4473 .vsync_end = 1200 + 17 + 2, 4474 .vtotal = 1200 + 17 + 2 + 16, 4475 }; 4476 4477 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4478 .desc = { 4479 .modes = &panasonic_vvx10f004b00_mode, 4480 .num_modes = 1, 4481 .bpc = 8, 4482 .size = { 4483 .width = 217, 4484 .height = 136, 4485 }, 4486 .connector_type = DRM_MODE_CONNECTOR_DSI, 4487 }, 4488 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4489 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4490 .format = MIPI_DSI_FMT_RGB888, 4491 .lanes = 4, 4492 }; 4493 4494 static const struct drm_display_mode lg_acx467akm_7_mode = { 4495 .clock = 150000, 4496 .hdisplay = 1080, 4497 .hsync_start = 1080 + 2, 4498 .hsync_end = 1080 + 2 + 2, 4499 .htotal = 1080 + 2 + 2 + 2, 4500 .vdisplay = 1920, 4501 .vsync_start = 1920 + 2, 4502 .vsync_end = 1920 + 2 + 2, 4503 .vtotal = 1920 + 2 + 2 + 2, 4504 }; 4505 4506 static const struct panel_desc_dsi lg_acx467akm_7 = { 4507 .desc = { 4508 .modes = &lg_acx467akm_7_mode, 4509 .num_modes = 1, 4510 .bpc = 8, 4511 .size = { 4512 .width = 62, 4513 .height = 110, 4514 }, 4515 .connector_type = DRM_MODE_CONNECTOR_DSI, 4516 }, 4517 .flags = 0, 4518 .format = MIPI_DSI_FMT_RGB888, 4519 .lanes = 4, 4520 }; 4521 4522 static const struct drm_display_mode osd101t2045_53ts_mode = { 4523 .clock = 154500, 4524 .hdisplay = 1920, 4525 .hsync_start = 1920 + 112, 4526 .hsync_end = 1920 + 112 + 16, 4527 .htotal = 1920 + 112 + 16 + 32, 4528 .vdisplay = 1200, 4529 .vsync_start = 1200 + 16, 4530 .vsync_end = 1200 + 16 + 2, 4531 .vtotal = 1200 + 16 + 2 + 16, 4532 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4533 }; 4534 4535 static const struct panel_desc_dsi osd101t2045_53ts = { 4536 .desc = { 4537 .modes = &osd101t2045_53ts_mode, 4538 .num_modes = 1, 4539 .bpc = 8, 4540 .size = { 4541 .width = 217, 4542 .height = 136, 4543 }, 4544 .connector_type = DRM_MODE_CONNECTOR_DSI, 4545 }, 4546 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4547 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4548 MIPI_DSI_MODE_EOT_PACKET, 4549 .format = MIPI_DSI_FMT_RGB888, 4550 .lanes = 4, 4551 }; 4552 4553 static const struct of_device_id dsi_of_match[] = { 4554 { 4555 .compatible = "auo,b080uan01", 4556 .data = &auo_b080uan01 4557 }, { 4558 .compatible = "boe,tv080wum-nl0", 4559 .data = &boe_tv080wum_nl0 4560 }, { 4561 .compatible = "lg,ld070wx3-sl01", 4562 .data = &lg_ld070wx3_sl01 4563 }, { 4564 .compatible = "lg,lh500wx1-sd03", 4565 .data = &lg_lh500wx1_sd03 4566 }, { 4567 .compatible = "panasonic,vvx10f004b00", 4568 .data = &panasonic_vvx10f004b00 4569 }, { 4570 .compatible = "lg,acx467akm-7", 4571 .data = &lg_acx467akm_7 4572 }, { 4573 .compatible = "osddisplays,osd101t2045-53ts", 4574 .data = &osd101t2045_53ts 4575 }, { 4576 /* sentinel */ 4577 } 4578 }; 4579 MODULE_DEVICE_TABLE(of, dsi_of_match); 4580 4581 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4582 { 4583 const struct panel_desc_dsi *desc; 4584 const struct of_device_id *id; 4585 int err; 4586 4587 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4588 if (!id) 4589 return -ENODEV; 4590 4591 desc = id->data; 4592 4593 err = panel_simple_probe(&dsi->dev, &desc->desc); 4594 if (err < 0) 4595 return err; 4596 4597 dsi->mode_flags = desc->flags; 4598 dsi->format = desc->format; 4599 dsi->lanes = desc->lanes; 4600 4601 err = mipi_dsi_attach(dsi); 4602 if (err) { 4603 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4604 4605 drm_panel_remove(&panel->base); 4606 } 4607 4608 return err; 4609 } 4610 4611 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4612 { 4613 int err; 4614 4615 err = mipi_dsi_detach(dsi); 4616 if (err < 0) 4617 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4618 4619 return panel_simple_remove(&dsi->dev); 4620 } 4621 4622 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4623 { 4624 panel_simple_shutdown(&dsi->dev); 4625 } 4626 4627 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4628 .driver = { 4629 .name = "panel-simple-dsi", 4630 .of_match_table = dsi_of_match, 4631 }, 4632 .probe = panel_simple_dsi_probe, 4633 .remove = panel_simple_dsi_remove, 4634 .shutdown = panel_simple_dsi_shutdown, 4635 }; 4636 4637 static int __init panel_simple_init(void) 4638 { 4639 int err; 4640 4641 err = platform_driver_register(&panel_simple_platform_driver); 4642 if (err < 0) 4643 return err; 4644 4645 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4646 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4647 if (err < 0) 4648 return err; 4649 } 4650 4651 return 0; 4652 } 4653 module_init(panel_simple_init); 4654 4655 static void __exit panel_simple_exit(void) 4656 { 4657 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4658 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4659 4660 platform_driver_unregister(&panel_simple_platform_driver); 4661 } 4662 module_exit(panel_simple_exit); 4663 4664 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4665 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4666 MODULE_LICENSE("GPL and additional rights"); 4667