1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_timings == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 if (p->enable_gpio) 191 gpiod_set_value_cansleep(p->enable_gpio, 0); 192 193 regulator_disable(p->supply); 194 195 if (p->desc->delay.unprepare) 196 msleep(p->desc->delay.unprepare); 197 198 p->prepared = false; 199 200 return 0; 201 } 202 203 static int panel_simple_prepare(struct drm_panel *panel) 204 { 205 struct panel_simple *p = to_panel_simple(panel); 206 int err; 207 208 if (p->prepared) 209 return 0; 210 211 err = regulator_enable(p->supply); 212 if (err < 0) { 213 dev_err(panel->dev, "failed to enable supply: %d\n", err); 214 return err; 215 } 216 217 if (p->enable_gpio) 218 gpiod_set_value_cansleep(p->enable_gpio, 1); 219 220 if (p->desc->delay.prepare) 221 msleep(p->desc->delay.prepare); 222 223 p->prepared = true; 224 225 return 0; 226 } 227 228 static int panel_simple_enable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (p->enabled) 233 return 0; 234 235 if (p->desc->delay.enable) 236 msleep(p->desc->delay.enable); 237 238 if (p->backlight) { 239 p->backlight->props.state &= ~BL_CORE_FBBLANK; 240 p->backlight->props.power = FB_BLANK_UNBLANK; 241 backlight_update_status(p->backlight); 242 } 243 244 p->enabled = true; 245 246 return 0; 247 } 248 249 static int panel_simple_get_modes(struct drm_panel *panel) 250 { 251 struct panel_simple *p = to_panel_simple(panel); 252 int num = 0; 253 254 /* probe EDID if a DDC bus is available */ 255 if (p->ddc) { 256 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 257 drm_mode_connector_update_edid_property(panel->connector, edid); 258 if (edid) { 259 num += drm_add_edid_modes(panel->connector, edid); 260 kfree(edid); 261 } 262 } 263 264 /* add hard-coded panel modes */ 265 num += panel_simple_get_fixed_modes(p); 266 267 return num; 268 } 269 270 static int panel_simple_get_timings(struct drm_panel *panel, 271 unsigned int num_timings, 272 struct display_timing *timings) 273 { 274 struct panel_simple *p = to_panel_simple(panel); 275 unsigned int i; 276 277 if (p->desc->num_timings < num_timings) 278 num_timings = p->desc->num_timings; 279 280 if (timings) 281 for (i = 0; i < num_timings; i++) 282 timings[i] = p->desc->timings[i]; 283 284 return p->desc->num_timings; 285 } 286 287 static const struct drm_panel_funcs panel_simple_funcs = { 288 .disable = panel_simple_disable, 289 .unprepare = panel_simple_unprepare, 290 .prepare = panel_simple_prepare, 291 .enable = panel_simple_enable, 292 .get_modes = panel_simple_get_modes, 293 .get_timings = panel_simple_get_timings, 294 }; 295 296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 297 { 298 struct device_node *backlight, *ddc; 299 struct panel_simple *panel; 300 int err; 301 302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 303 if (!panel) 304 return -ENOMEM; 305 306 panel->enabled = false; 307 panel->prepared = false; 308 panel->desc = desc; 309 310 panel->supply = devm_regulator_get(dev, "power"); 311 if (IS_ERR(panel->supply)) 312 return PTR_ERR(panel->supply); 313 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 315 GPIOD_OUT_LOW); 316 if (IS_ERR(panel->enable_gpio)) { 317 err = PTR_ERR(panel->enable_gpio); 318 dev_err(dev, "failed to request GPIO: %d\n", err); 319 return err; 320 } 321 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 323 if (backlight) { 324 panel->backlight = of_find_backlight_by_node(backlight); 325 of_node_put(backlight); 326 327 if (!panel->backlight) 328 return -EPROBE_DEFER; 329 } 330 331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 332 if (ddc) { 333 panel->ddc = of_find_i2c_adapter_by_node(ddc); 334 of_node_put(ddc); 335 336 if (!panel->ddc) { 337 err = -EPROBE_DEFER; 338 goto free_backlight; 339 } 340 } 341 342 drm_panel_init(&panel->base); 343 panel->base.dev = dev; 344 panel->base.funcs = &panel_simple_funcs; 345 346 err = drm_panel_add(&panel->base); 347 if (err < 0) 348 goto free_ddc; 349 350 dev_set_drvdata(dev, panel); 351 352 return 0; 353 354 free_ddc: 355 if (panel->ddc) 356 put_device(&panel->ddc->dev); 357 free_backlight: 358 if (panel->backlight) 359 put_device(&panel->backlight->dev); 360 361 return err; 362 } 363 364 static int panel_simple_remove(struct device *dev) 365 { 366 struct panel_simple *panel = dev_get_drvdata(dev); 367 368 drm_panel_detach(&panel->base); 369 drm_panel_remove(&panel->base); 370 371 panel_simple_disable(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 390 .clock = 9000, 391 .hdisplay = 480, 392 .hsync_start = 480 + 2, 393 .hsync_end = 480 + 2 + 41, 394 .htotal = 480 + 2 + 41 + 2, 395 .vdisplay = 272, 396 .vsync_start = 272 + 2, 397 .vsync_end = 272 + 2 + 10, 398 .vtotal = 272 + 2 + 10 + 2, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 404 .modes = &ire_am_480272h3tmqw_t01h_mode, 405 .num_modes = 1, 406 .bpc = 8, 407 .size = { 408 .width = 105, 409 .height = 67, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 412 }; 413 414 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 415 .clock = 33333, 416 .hdisplay = 800, 417 .hsync_start = 800 + 0, 418 .hsync_end = 800 + 0 + 255, 419 .htotal = 800 + 0 + 255 + 0, 420 .vdisplay = 480, 421 .vsync_start = 480 + 2, 422 .vsync_end = 480 + 2 + 45, 423 .vtotal = 480 + 2 + 45 + 0, 424 .vrefresh = 60, 425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 426 }; 427 428 static const struct panel_desc ampire_am800480r3tmqwa1h = { 429 .modes = &ire_am800480r3tmqwa1h_mode, 430 .num_modes = 1, 431 .bpc = 6, 432 .size = { 433 .width = 152, 434 .height = 91, 435 }, 436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 437 }; 438 439 static const struct drm_display_mode auo_b101aw03_mode = { 440 .clock = 51450, 441 .hdisplay = 1024, 442 .hsync_start = 1024 + 156, 443 .hsync_end = 1024 + 156 + 8, 444 .htotal = 1024 + 156 + 8 + 156, 445 .vdisplay = 600, 446 .vsync_start = 600 + 16, 447 .vsync_end = 600 + 16 + 6, 448 .vtotal = 600 + 16 + 6 + 16, 449 .vrefresh = 60, 450 }; 451 452 static const struct panel_desc auo_b101aw03 = { 453 .modes = &auo_b101aw03_mode, 454 .num_modes = 1, 455 .bpc = 6, 456 .size = { 457 .width = 223, 458 .height = 125, 459 }, 460 }; 461 462 static const struct drm_display_mode auo_b101ean01_mode = { 463 .clock = 72500, 464 .hdisplay = 1280, 465 .hsync_start = 1280 + 119, 466 .hsync_end = 1280 + 119 + 32, 467 .htotal = 1280 + 119 + 32 + 21, 468 .vdisplay = 800, 469 .vsync_start = 800 + 4, 470 .vsync_end = 800 + 4 + 20, 471 .vtotal = 800 + 4 + 20 + 8, 472 .vrefresh = 60, 473 }; 474 475 static const struct panel_desc auo_b101ean01 = { 476 .modes = &auo_b101ean01_mode, 477 .num_modes = 1, 478 .bpc = 6, 479 .size = { 480 .width = 217, 481 .height = 136, 482 }, 483 }; 484 485 static const struct drm_display_mode auo_b101xtn01_mode = { 486 .clock = 72000, 487 .hdisplay = 1366, 488 .hsync_start = 1366 + 20, 489 .hsync_end = 1366 + 20 + 70, 490 .htotal = 1366 + 20 + 70, 491 .vdisplay = 768, 492 .vsync_start = 768 + 14, 493 .vsync_end = 768 + 14 + 42, 494 .vtotal = 768 + 14 + 42, 495 .vrefresh = 60, 496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 497 }; 498 499 static const struct panel_desc auo_b101xtn01 = { 500 .modes = &auo_b101xtn01_mode, 501 .num_modes = 1, 502 .bpc = 6, 503 .size = { 504 .width = 223, 505 .height = 125, 506 }, 507 }; 508 509 static const struct drm_display_mode auo_b116xw03_mode = { 510 .clock = 70589, 511 .hdisplay = 1366, 512 .hsync_start = 1366 + 40, 513 .hsync_end = 1366 + 40 + 40, 514 .htotal = 1366 + 40 + 40 + 32, 515 .vdisplay = 768, 516 .vsync_start = 768 + 10, 517 .vsync_end = 768 + 10 + 12, 518 .vtotal = 768 + 10 + 12 + 6, 519 .vrefresh = 60, 520 }; 521 522 static const struct panel_desc auo_b116xw03 = { 523 .modes = &auo_b116xw03_mode, 524 .num_modes = 1, 525 .bpc = 6, 526 .size = { 527 .width = 256, 528 .height = 144, 529 }, 530 }; 531 532 static const struct drm_display_mode auo_b133xtn01_mode = { 533 .clock = 69500, 534 .hdisplay = 1366, 535 .hsync_start = 1366 + 48, 536 .hsync_end = 1366 + 48 + 32, 537 .htotal = 1366 + 48 + 32 + 20, 538 .vdisplay = 768, 539 .vsync_start = 768 + 3, 540 .vsync_end = 768 + 3 + 6, 541 .vtotal = 768 + 3 + 6 + 13, 542 .vrefresh = 60, 543 }; 544 545 static const struct panel_desc auo_b133xtn01 = { 546 .modes = &auo_b133xtn01_mode, 547 .num_modes = 1, 548 .bpc = 6, 549 .size = { 550 .width = 293, 551 .height = 165, 552 }, 553 }; 554 555 static const struct drm_display_mode auo_b133htn01_mode = { 556 .clock = 150660, 557 .hdisplay = 1920, 558 .hsync_start = 1920 + 172, 559 .hsync_end = 1920 + 172 + 80, 560 .htotal = 1920 + 172 + 80 + 60, 561 .vdisplay = 1080, 562 .vsync_start = 1080 + 25, 563 .vsync_end = 1080 + 25 + 10, 564 .vtotal = 1080 + 25 + 10 + 10, 565 .vrefresh = 60, 566 }; 567 568 static const struct panel_desc auo_b133htn01 = { 569 .modes = &auo_b133htn01_mode, 570 .num_modes = 1, 571 .bpc = 6, 572 .size = { 573 .width = 293, 574 .height = 165, 575 }, 576 .delay = { 577 .prepare = 105, 578 .enable = 20, 579 .unprepare = 50, 580 }, 581 }; 582 583 static const struct display_timing auo_g133han01_timings = { 584 .pixelclock = { 134000000, 141200000, 149000000 }, 585 .hactive = { 1920, 1920, 1920 }, 586 .hfront_porch = { 39, 58, 77 }, 587 .hback_porch = { 59, 88, 117 }, 588 .hsync_len = { 28, 42, 56 }, 589 .vactive = { 1080, 1080, 1080 }, 590 .vfront_porch = { 3, 8, 11 }, 591 .vback_porch = { 5, 14, 19 }, 592 .vsync_len = { 4, 14, 19 }, 593 }; 594 595 static const struct panel_desc auo_g133han01 = { 596 .timings = &auo_g133han01_timings, 597 .num_timings = 1, 598 .bpc = 8, 599 .size = { 600 .width = 293, 601 .height = 165, 602 }, 603 .delay = { 604 .prepare = 200, 605 .enable = 50, 606 .disable = 50, 607 .unprepare = 1000, 608 }, 609 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 610 }; 611 612 static const struct display_timing auo_g185han01_timings = { 613 .pixelclock = { 120000000, 144000000, 175000000 }, 614 .hactive = { 1920, 1920, 1920 }, 615 .hfront_porch = { 18, 60, 74 }, 616 .hback_porch = { 12, 44, 54 }, 617 .hsync_len = { 10, 24, 32 }, 618 .vactive = { 1080, 1080, 1080 }, 619 .vfront_porch = { 6, 10, 40 }, 620 .vback_porch = { 2, 5, 20 }, 621 .vsync_len = { 2, 5, 20 }, 622 }; 623 624 static const struct panel_desc auo_g185han01 = { 625 .timings = &auo_g185han01_timings, 626 .num_timings = 1, 627 .bpc = 8, 628 .size = { 629 .width = 409, 630 .height = 230, 631 }, 632 .delay = { 633 .prepare = 50, 634 .enable = 200, 635 .disable = 110, 636 .unprepare = 1000, 637 }, 638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 639 }; 640 641 static const struct display_timing auo_p320hvn03_timings = { 642 .pixelclock = { 106000000, 148500000, 164000000 }, 643 .hactive = { 1920, 1920, 1920 }, 644 .hfront_porch = { 25, 50, 130 }, 645 .hback_porch = { 25, 50, 130 }, 646 .hsync_len = { 20, 40, 105 }, 647 .vactive = { 1080, 1080, 1080 }, 648 .vfront_porch = { 8, 17, 150 }, 649 .vback_porch = { 8, 17, 150 }, 650 .vsync_len = { 4, 11, 100 }, 651 }; 652 653 static const struct panel_desc auo_p320hvn03 = { 654 .timings = &auo_p320hvn03_timings, 655 .num_timings = 1, 656 .bpc = 8, 657 .size = { 658 .width = 698, 659 .height = 393, 660 }, 661 .delay = { 662 .prepare = 1, 663 .enable = 450, 664 .unprepare = 500, 665 }, 666 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 667 }; 668 669 static const struct drm_display_mode auo_t215hvn01_mode = { 670 .clock = 148800, 671 .hdisplay = 1920, 672 .hsync_start = 1920 + 88, 673 .hsync_end = 1920 + 88 + 44, 674 .htotal = 1920 + 88 + 44 + 148, 675 .vdisplay = 1080, 676 .vsync_start = 1080 + 4, 677 .vsync_end = 1080 + 4 + 5, 678 .vtotal = 1080 + 4 + 5 + 36, 679 .vrefresh = 60, 680 }; 681 682 static const struct panel_desc auo_t215hvn01 = { 683 .modes = &auo_t215hvn01_mode, 684 .num_modes = 1, 685 .bpc = 8, 686 .size = { 687 .width = 430, 688 .height = 270, 689 }, 690 .delay = { 691 .disable = 5, 692 .unprepare = 1000, 693 } 694 }; 695 696 static const struct drm_display_mode avic_tm070ddh03_mode = { 697 .clock = 51200, 698 .hdisplay = 1024, 699 .hsync_start = 1024 + 160, 700 .hsync_end = 1024 + 160 + 4, 701 .htotal = 1024 + 160 + 4 + 156, 702 .vdisplay = 600, 703 .vsync_start = 600 + 17, 704 .vsync_end = 600 + 17 + 1, 705 .vtotal = 600 + 17 + 1 + 17, 706 .vrefresh = 60, 707 }; 708 709 static const struct panel_desc avic_tm070ddh03 = { 710 .modes = &avic_tm070ddh03_mode, 711 .num_modes = 1, 712 .bpc = 8, 713 .size = { 714 .width = 154, 715 .height = 90, 716 }, 717 .delay = { 718 .prepare = 20, 719 .enable = 200, 720 .disable = 200, 721 }, 722 }; 723 724 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 725 { 726 .clock = 71900, 727 .hdisplay = 1280, 728 .hsync_start = 1280 + 48, 729 .hsync_end = 1280 + 48 + 32, 730 .htotal = 1280 + 48 + 32 + 80, 731 .vdisplay = 800, 732 .vsync_start = 800 + 3, 733 .vsync_end = 800 + 3 + 5, 734 .vtotal = 800 + 3 + 5 + 24, 735 .vrefresh = 60, 736 }, 737 { 738 .clock = 57500, 739 .hdisplay = 1280, 740 .hsync_start = 1280 + 48, 741 .hsync_end = 1280 + 48 + 32, 742 .htotal = 1280 + 48 + 32 + 80, 743 .vdisplay = 800, 744 .vsync_start = 800 + 3, 745 .vsync_end = 800 + 3 + 5, 746 .vtotal = 800 + 3 + 5 + 24, 747 .vrefresh = 48, 748 }, 749 }; 750 751 static const struct panel_desc boe_nv101wxmn51 = { 752 .modes = boe_nv101wxmn51_modes, 753 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 754 .bpc = 8, 755 .size = { 756 .width = 217, 757 .height = 136, 758 }, 759 .delay = { 760 .prepare = 210, 761 .enable = 50, 762 .unprepare = 160, 763 }, 764 }; 765 766 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 767 .clock = 66770, 768 .hdisplay = 800, 769 .hsync_start = 800 + 49, 770 .hsync_end = 800 + 49 + 33, 771 .htotal = 800 + 49 + 33 + 17, 772 .vdisplay = 1280, 773 .vsync_start = 1280 + 1, 774 .vsync_end = 1280 + 1 + 7, 775 .vtotal = 1280 + 1 + 7 + 15, 776 .vrefresh = 60, 777 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 778 }; 779 780 static const struct panel_desc chunghwa_claa070wp03xg = { 781 .modes = &chunghwa_claa070wp03xg_mode, 782 .num_modes = 1, 783 .bpc = 6, 784 .size = { 785 .width = 94, 786 .height = 150, 787 }, 788 }; 789 790 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 791 .clock = 72070, 792 .hdisplay = 1366, 793 .hsync_start = 1366 + 58, 794 .hsync_end = 1366 + 58 + 58, 795 .htotal = 1366 + 58 + 58 + 58, 796 .vdisplay = 768, 797 .vsync_start = 768 + 4, 798 .vsync_end = 768 + 4 + 4, 799 .vtotal = 768 + 4 + 4 + 4, 800 .vrefresh = 60, 801 }; 802 803 static const struct panel_desc chunghwa_claa101wa01a = { 804 .modes = &chunghwa_claa101wa01a_mode, 805 .num_modes = 1, 806 .bpc = 6, 807 .size = { 808 .width = 220, 809 .height = 120, 810 }, 811 }; 812 813 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 814 .clock = 69300, 815 .hdisplay = 1366, 816 .hsync_start = 1366 + 48, 817 .hsync_end = 1366 + 48 + 32, 818 .htotal = 1366 + 48 + 32 + 20, 819 .vdisplay = 768, 820 .vsync_start = 768 + 16, 821 .vsync_end = 768 + 16 + 8, 822 .vtotal = 768 + 16 + 8 + 16, 823 .vrefresh = 60, 824 }; 825 826 static const struct panel_desc chunghwa_claa101wb01 = { 827 .modes = &chunghwa_claa101wb01_mode, 828 .num_modes = 1, 829 .bpc = 6, 830 .size = { 831 .width = 223, 832 .height = 125, 833 }, 834 }; 835 836 static const struct drm_display_mode edt_et057090dhu_mode = { 837 .clock = 25175, 838 .hdisplay = 640, 839 .hsync_start = 640 + 16, 840 .hsync_end = 640 + 16 + 30, 841 .htotal = 640 + 16 + 30 + 114, 842 .vdisplay = 480, 843 .vsync_start = 480 + 10, 844 .vsync_end = 480 + 10 + 3, 845 .vtotal = 480 + 10 + 3 + 32, 846 .vrefresh = 60, 847 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 848 }; 849 850 static const struct panel_desc edt_et057090dhu = { 851 .modes = &edt_et057090dhu_mode, 852 .num_modes = 1, 853 .bpc = 6, 854 .size = { 855 .width = 115, 856 .height = 86, 857 }, 858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 860 }; 861 862 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 863 .clock = 33260, 864 .hdisplay = 800, 865 .hsync_start = 800 + 40, 866 .hsync_end = 800 + 40 + 128, 867 .htotal = 800 + 40 + 128 + 88, 868 .vdisplay = 480, 869 .vsync_start = 480 + 10, 870 .vsync_end = 480 + 10 + 2, 871 .vtotal = 480 + 10 + 2 + 33, 872 .vrefresh = 60, 873 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 874 }; 875 876 static const struct panel_desc edt_etm0700g0dh6 = { 877 .modes = &edt_etm0700g0dh6_mode, 878 .num_modes = 1, 879 .bpc = 6, 880 .size = { 881 .width = 152, 882 .height = 91, 883 }, 884 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 886 }; 887 888 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 889 .clock = 32260, 890 .hdisplay = 800, 891 .hsync_start = 800 + 168, 892 .hsync_end = 800 + 168 + 64, 893 .htotal = 800 + 168 + 64 + 88, 894 .vdisplay = 480, 895 .vsync_start = 480 + 37, 896 .vsync_end = 480 + 37 + 2, 897 .vtotal = 480 + 37 + 2 + 8, 898 .vrefresh = 60, 899 }; 900 901 static const struct panel_desc foxlink_fl500wvr00_a0t = { 902 .modes = &foxlink_fl500wvr00_a0t_mode, 903 .num_modes = 1, 904 .bpc = 8, 905 .size = { 906 .width = 108, 907 .height = 65, 908 }, 909 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 910 }; 911 912 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 913 .clock = 9000, 914 .hdisplay = 480, 915 .hsync_start = 480 + 5, 916 .hsync_end = 480 + 5 + 1, 917 .htotal = 480 + 5 + 1 + 40, 918 .vdisplay = 272, 919 .vsync_start = 272 + 8, 920 .vsync_end = 272 + 8 + 1, 921 .vtotal = 272 + 8 + 1 + 8, 922 .vrefresh = 60, 923 }; 924 925 static const struct panel_desc giantplus_gpg482739qs5 = { 926 .modes = &giantplus_gpg482739qs5_mode, 927 .num_modes = 1, 928 .bpc = 8, 929 .size = { 930 .width = 95, 931 .height = 54, 932 }, 933 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 934 }; 935 936 static const struct display_timing hannstar_hsd070pww1_timing = { 937 .pixelclock = { 64300000, 71100000, 82000000 }, 938 .hactive = { 1280, 1280, 1280 }, 939 .hfront_porch = { 1, 1, 10 }, 940 .hback_porch = { 1, 1, 10 }, 941 /* 942 * According to the data sheet, the minimum horizontal blanking interval 943 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 944 * minimum working horizontal blanking interval to be 60 clocks. 945 */ 946 .hsync_len = { 58, 158, 661 }, 947 .vactive = { 800, 800, 800 }, 948 .vfront_porch = { 1, 1, 10 }, 949 .vback_porch = { 1, 1, 10 }, 950 .vsync_len = { 1, 21, 203 }, 951 .flags = DISPLAY_FLAGS_DE_HIGH, 952 }; 953 954 static const struct panel_desc hannstar_hsd070pww1 = { 955 .timings = &hannstar_hsd070pww1_timing, 956 .num_timings = 1, 957 .bpc = 6, 958 .size = { 959 .width = 151, 960 .height = 94, 961 }, 962 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 963 }; 964 965 static const struct display_timing hannstar_hsd100pxn1_timing = { 966 .pixelclock = { 55000000, 65000000, 75000000 }, 967 .hactive = { 1024, 1024, 1024 }, 968 .hfront_porch = { 40, 40, 40 }, 969 .hback_porch = { 220, 220, 220 }, 970 .hsync_len = { 20, 60, 100 }, 971 .vactive = { 768, 768, 768 }, 972 .vfront_porch = { 7, 7, 7 }, 973 .vback_porch = { 21, 21, 21 }, 974 .vsync_len = { 10, 10, 10 }, 975 .flags = DISPLAY_FLAGS_DE_HIGH, 976 }; 977 978 static const struct panel_desc hannstar_hsd100pxn1 = { 979 .timings = &hannstar_hsd100pxn1_timing, 980 .num_timings = 1, 981 .bpc = 6, 982 .size = { 983 .width = 203, 984 .height = 152, 985 }, 986 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 987 }; 988 989 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 990 .clock = 33333, 991 .hdisplay = 800, 992 .hsync_start = 800 + 85, 993 .hsync_end = 800 + 85 + 86, 994 .htotal = 800 + 85 + 86 + 85, 995 .vdisplay = 480, 996 .vsync_start = 480 + 16, 997 .vsync_end = 480 + 16 + 13, 998 .vtotal = 480 + 16 + 13 + 16, 999 .vrefresh = 60, 1000 }; 1001 1002 static const struct panel_desc hitachi_tx23d38vm0caa = { 1003 .modes = &hitachi_tx23d38vm0caa_mode, 1004 .num_modes = 1, 1005 .bpc = 6, 1006 .size = { 1007 .width = 195, 1008 .height = 117, 1009 }, 1010 }; 1011 1012 static const struct drm_display_mode innolux_at043tn24_mode = { 1013 .clock = 9000, 1014 .hdisplay = 480, 1015 .hsync_start = 480 + 2, 1016 .hsync_end = 480 + 2 + 41, 1017 .htotal = 480 + 2 + 41 + 2, 1018 .vdisplay = 272, 1019 .vsync_start = 272 + 2, 1020 .vsync_end = 272 + 2 + 11, 1021 .vtotal = 272 + 2 + 11 + 2, 1022 .vrefresh = 60, 1023 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1024 }; 1025 1026 static const struct panel_desc innolux_at043tn24 = { 1027 .modes = &innolux_at043tn24_mode, 1028 .num_modes = 1, 1029 .bpc = 8, 1030 .size = { 1031 .width = 95, 1032 .height = 54, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1035 }; 1036 1037 static const struct drm_display_mode innolux_at070tn92_mode = { 1038 .clock = 33333, 1039 .hdisplay = 800, 1040 .hsync_start = 800 + 210, 1041 .hsync_end = 800 + 210 + 20, 1042 .htotal = 800 + 210 + 20 + 46, 1043 .vdisplay = 480, 1044 .vsync_start = 480 + 22, 1045 .vsync_end = 480 + 22 + 10, 1046 .vtotal = 480 + 22 + 23 + 10, 1047 .vrefresh = 60, 1048 }; 1049 1050 static const struct panel_desc innolux_at070tn92 = { 1051 .modes = &innolux_at070tn92_mode, 1052 .num_modes = 1, 1053 .size = { 1054 .width = 154, 1055 .height = 86, 1056 }, 1057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1058 }; 1059 1060 static const struct display_timing innolux_g101ice_l01_timing = { 1061 .pixelclock = { 60400000, 71100000, 74700000 }, 1062 .hactive = { 1280, 1280, 1280 }, 1063 .hfront_porch = { 41, 80, 100 }, 1064 .hback_porch = { 40, 79, 99 }, 1065 .hsync_len = { 1, 1, 1 }, 1066 .vactive = { 800, 800, 800 }, 1067 .vfront_porch = { 5, 11, 14 }, 1068 .vback_porch = { 4, 11, 14 }, 1069 .vsync_len = { 1, 1, 1 }, 1070 .flags = DISPLAY_FLAGS_DE_HIGH, 1071 }; 1072 1073 static const struct panel_desc innolux_g101ice_l01 = { 1074 .timings = &innolux_g101ice_l01_timing, 1075 .num_timings = 1, 1076 .bpc = 8, 1077 .size = { 1078 .width = 217, 1079 .height = 135, 1080 }, 1081 .delay = { 1082 .enable = 200, 1083 .disable = 200, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1086 }; 1087 1088 static const struct display_timing innolux_g121i1_l01_timing = { 1089 .pixelclock = { 67450000, 71000000, 74550000 }, 1090 .hactive = { 1280, 1280, 1280 }, 1091 .hfront_porch = { 40, 80, 160 }, 1092 .hback_porch = { 39, 79, 159 }, 1093 .hsync_len = { 1, 1, 1 }, 1094 .vactive = { 800, 800, 800 }, 1095 .vfront_porch = { 5, 11, 100 }, 1096 .vback_porch = { 4, 11, 99 }, 1097 .vsync_len = { 1, 1, 1 }, 1098 }; 1099 1100 static const struct panel_desc innolux_g121i1_l01 = { 1101 .timings = &innolux_g121i1_l01_timing, 1102 .num_timings = 1, 1103 .bpc = 6, 1104 .size = { 1105 .width = 261, 1106 .height = 163, 1107 }, 1108 .delay = { 1109 .enable = 200, 1110 .disable = 20, 1111 }, 1112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1113 }; 1114 1115 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1116 .clock = 65000, 1117 .hdisplay = 1024, 1118 .hsync_start = 1024 + 0, 1119 .hsync_end = 1024 + 1, 1120 .htotal = 1024 + 0 + 1 + 320, 1121 .vdisplay = 768, 1122 .vsync_start = 768 + 38, 1123 .vsync_end = 768 + 38 + 1, 1124 .vtotal = 768 + 38 + 1 + 0, 1125 .vrefresh = 60, 1126 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1127 }; 1128 1129 static const struct panel_desc innolux_g121x1_l03 = { 1130 .modes = &innolux_g121x1_l03_mode, 1131 .num_modes = 1, 1132 .bpc = 6, 1133 .size = { 1134 .width = 246, 1135 .height = 185, 1136 }, 1137 .delay = { 1138 .enable = 200, 1139 .unprepare = 200, 1140 .disable = 400, 1141 }, 1142 }; 1143 1144 static const struct drm_display_mode innolux_n116bge_mode = { 1145 .clock = 76420, 1146 .hdisplay = 1366, 1147 .hsync_start = 1366 + 136, 1148 .hsync_end = 1366 + 136 + 30, 1149 .htotal = 1366 + 136 + 30 + 60, 1150 .vdisplay = 768, 1151 .vsync_start = 768 + 8, 1152 .vsync_end = 768 + 8 + 12, 1153 .vtotal = 768 + 8 + 12 + 12, 1154 .vrefresh = 60, 1155 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1156 }; 1157 1158 static const struct panel_desc innolux_n116bge = { 1159 .modes = &innolux_n116bge_mode, 1160 .num_modes = 1, 1161 .bpc = 6, 1162 .size = { 1163 .width = 256, 1164 .height = 144, 1165 }, 1166 }; 1167 1168 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1169 .clock = 69300, 1170 .hdisplay = 1366, 1171 .hsync_start = 1366 + 16, 1172 .hsync_end = 1366 + 16 + 34, 1173 .htotal = 1366 + 16 + 34 + 50, 1174 .vdisplay = 768, 1175 .vsync_start = 768 + 2, 1176 .vsync_end = 768 + 2 + 6, 1177 .vtotal = 768 + 2 + 6 + 12, 1178 .vrefresh = 60, 1179 }; 1180 1181 static const struct panel_desc innolux_n156bge_l21 = { 1182 .modes = &innolux_n156bge_l21_mode, 1183 .num_modes = 1, 1184 .bpc = 6, 1185 .size = { 1186 .width = 344, 1187 .height = 193, 1188 }, 1189 }; 1190 1191 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1192 .clock = 51501, 1193 .hdisplay = 1024, 1194 .hsync_start = 1024 + 128, 1195 .hsync_end = 1024 + 128 + 64, 1196 .htotal = 1024 + 128 + 64 + 128, 1197 .vdisplay = 600, 1198 .vsync_start = 600 + 16, 1199 .vsync_end = 600 + 16 + 4, 1200 .vtotal = 600 + 16 + 4 + 16, 1201 .vrefresh = 60, 1202 }; 1203 1204 static const struct panel_desc innolux_zj070na_01p = { 1205 .modes = &innolux_zj070na_01p_mode, 1206 .num_modes = 1, 1207 .bpc = 6, 1208 .size = { 1209 .width = 154, 1210 .height = 90, 1211 }, 1212 }; 1213 1214 static const struct display_timing kyo_tcg121xglp_timing = { 1215 .pixelclock = { 52000000, 65000000, 71000000 }, 1216 .hactive = { 1024, 1024, 1024 }, 1217 .hfront_porch = { 2, 2, 2 }, 1218 .hback_porch = { 2, 2, 2 }, 1219 .hsync_len = { 86, 124, 244 }, 1220 .vactive = { 768, 768, 768 }, 1221 .vfront_porch = { 2, 2, 2 }, 1222 .vback_porch = { 2, 2, 2 }, 1223 .vsync_len = { 6, 34, 73 }, 1224 .flags = DISPLAY_FLAGS_DE_HIGH, 1225 }; 1226 1227 static const struct panel_desc kyo_tcg121xglp = { 1228 .timings = &kyo_tcg121xglp_timing, 1229 .num_timings = 1, 1230 .bpc = 8, 1231 .size = { 1232 .width = 246, 1233 .height = 184, 1234 }, 1235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1236 }; 1237 1238 static const struct drm_display_mode lg_lb070wv8_mode = { 1239 .clock = 33246, 1240 .hdisplay = 800, 1241 .hsync_start = 800 + 88, 1242 .hsync_end = 800 + 88 + 80, 1243 .htotal = 800 + 88 + 80 + 88, 1244 .vdisplay = 480, 1245 .vsync_start = 480 + 10, 1246 .vsync_end = 480 + 10 + 25, 1247 .vtotal = 480 + 10 + 25 + 10, 1248 .vrefresh = 60, 1249 }; 1250 1251 static const struct panel_desc lg_lb070wv8 = { 1252 .modes = &lg_lb070wv8_mode, 1253 .num_modes = 1, 1254 .bpc = 16, 1255 .size = { 1256 .width = 151, 1257 .height = 91, 1258 }, 1259 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1260 }; 1261 1262 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1263 .clock = 200000, 1264 .hdisplay = 1536, 1265 .hsync_start = 1536 + 12, 1266 .hsync_end = 1536 + 12 + 16, 1267 .htotal = 1536 + 12 + 16 + 48, 1268 .vdisplay = 2048, 1269 .vsync_start = 2048 + 8, 1270 .vsync_end = 2048 + 8 + 4, 1271 .vtotal = 2048 + 8 + 4 + 8, 1272 .vrefresh = 60, 1273 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1274 }; 1275 1276 static const struct panel_desc lg_lp079qx1_sp0v = { 1277 .modes = &lg_lp079qx1_sp0v_mode, 1278 .num_modes = 1, 1279 .size = { 1280 .width = 129, 1281 .height = 171, 1282 }, 1283 }; 1284 1285 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1286 .clock = 205210, 1287 .hdisplay = 2048, 1288 .hsync_start = 2048 + 150, 1289 .hsync_end = 2048 + 150 + 5, 1290 .htotal = 2048 + 150 + 5 + 5, 1291 .vdisplay = 1536, 1292 .vsync_start = 1536 + 3, 1293 .vsync_end = 1536 + 3 + 1, 1294 .vtotal = 1536 + 3 + 1 + 9, 1295 .vrefresh = 60, 1296 }; 1297 1298 static const struct panel_desc lg_lp097qx1_spa1 = { 1299 .modes = &lg_lp097qx1_spa1_mode, 1300 .num_modes = 1, 1301 .size = { 1302 .width = 208, 1303 .height = 147, 1304 }, 1305 }; 1306 1307 static const struct drm_display_mode lg_lp120up1_mode = { 1308 .clock = 162300, 1309 .hdisplay = 1920, 1310 .hsync_start = 1920 + 40, 1311 .hsync_end = 1920 + 40 + 40, 1312 .htotal = 1920 + 40 + 40+ 80, 1313 .vdisplay = 1280, 1314 .vsync_start = 1280 + 4, 1315 .vsync_end = 1280 + 4 + 4, 1316 .vtotal = 1280 + 4 + 4 + 12, 1317 .vrefresh = 60, 1318 }; 1319 1320 static const struct panel_desc lg_lp120up1 = { 1321 .modes = &lg_lp120up1_mode, 1322 .num_modes = 1, 1323 .bpc = 8, 1324 .size = { 1325 .width = 267, 1326 .height = 183, 1327 }, 1328 }; 1329 1330 static const struct drm_display_mode lg_lp129qe_mode = { 1331 .clock = 285250, 1332 .hdisplay = 2560, 1333 .hsync_start = 2560 + 48, 1334 .hsync_end = 2560 + 48 + 32, 1335 .htotal = 2560 + 48 + 32 + 80, 1336 .vdisplay = 1700, 1337 .vsync_start = 1700 + 3, 1338 .vsync_end = 1700 + 3 + 10, 1339 .vtotal = 1700 + 3 + 10 + 36, 1340 .vrefresh = 60, 1341 }; 1342 1343 static const struct panel_desc lg_lp129qe = { 1344 .modes = &lg_lp129qe_mode, 1345 .num_modes = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 272, 1349 .height = 181, 1350 }, 1351 }; 1352 1353 static const struct display_timing nec_nl12880bc20_05_timing = { 1354 .pixelclock = { 67000000, 71000000, 75000000 }, 1355 .hactive = { 1280, 1280, 1280 }, 1356 .hfront_porch = { 2, 30, 30 }, 1357 .hback_porch = { 6, 100, 100 }, 1358 .hsync_len = { 2, 30, 30 }, 1359 .vactive = { 800, 800, 800 }, 1360 .vfront_porch = { 5, 5, 5 }, 1361 .vback_porch = { 11, 11, 11 }, 1362 .vsync_len = { 7, 7, 7 }, 1363 }; 1364 1365 static const struct panel_desc nec_nl12880bc20_05 = { 1366 .timings = &nec_nl12880bc20_05_timing, 1367 .num_timings = 1, 1368 .bpc = 8, 1369 .size = { 1370 .width = 261, 1371 .height = 163, 1372 }, 1373 .delay = { 1374 .enable = 50, 1375 .disable = 50, 1376 }, 1377 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1378 }; 1379 1380 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1381 .clock = 10870, 1382 .hdisplay = 480, 1383 .hsync_start = 480 + 2, 1384 .hsync_end = 480 + 2 + 41, 1385 .htotal = 480 + 2 + 41 + 2, 1386 .vdisplay = 272, 1387 .vsync_start = 272 + 2, 1388 .vsync_end = 272 + 2 + 4, 1389 .vtotal = 272 + 2 + 4 + 2, 1390 .vrefresh = 74, 1391 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1392 }; 1393 1394 static const struct panel_desc nec_nl4827hc19_05b = { 1395 .modes = &nec_nl4827hc19_05b_mode, 1396 .num_modes = 1, 1397 .bpc = 8, 1398 .size = { 1399 .width = 95, 1400 .height = 54, 1401 }, 1402 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1403 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1404 }; 1405 1406 static const struct drm_display_mode netron_dy_e231732_mode = { 1407 .clock = 66000, 1408 .hdisplay = 1024, 1409 .hsync_start = 1024 + 160, 1410 .hsync_end = 1024 + 160 + 70, 1411 .htotal = 1024 + 160 + 70 + 90, 1412 .vdisplay = 600, 1413 .vsync_start = 600 + 127, 1414 .vsync_end = 600 + 127 + 20, 1415 .vtotal = 600 + 127 + 20 + 3, 1416 .vrefresh = 60, 1417 }; 1418 1419 static const struct panel_desc netron_dy_e231732 = { 1420 .modes = &netron_dy_e231732_mode, 1421 .num_modes = 1, 1422 .size = { 1423 .width = 154, 1424 .height = 87, 1425 }, 1426 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1427 }; 1428 1429 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1430 .pixelclock = { 130000000, 148350000, 163000000 }, 1431 .hactive = { 1920, 1920, 1920 }, 1432 .hfront_porch = { 80, 100, 100 }, 1433 .hback_porch = { 100, 120, 120 }, 1434 .hsync_len = { 50, 60, 60 }, 1435 .vactive = { 1080, 1080, 1080 }, 1436 .vfront_porch = { 12, 30, 30 }, 1437 .vback_porch = { 4, 10, 10 }, 1438 .vsync_len = { 4, 5, 5 }, 1439 }; 1440 1441 static const struct panel_desc nlt_nl192108ac18_02d = { 1442 .timings = &nlt_nl192108ac18_02d_timing, 1443 .num_timings = 1, 1444 .bpc = 8, 1445 .size = { 1446 .width = 344, 1447 .height = 194, 1448 }, 1449 .delay = { 1450 .unprepare = 500, 1451 }, 1452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1453 }; 1454 1455 static const struct drm_display_mode nvd_9128_mode = { 1456 .clock = 29500, 1457 .hdisplay = 800, 1458 .hsync_start = 800 + 130, 1459 .hsync_end = 800 + 130 + 98, 1460 .htotal = 800 + 0 + 130 + 98, 1461 .vdisplay = 480, 1462 .vsync_start = 480 + 10, 1463 .vsync_end = 480 + 10 + 50, 1464 .vtotal = 480 + 0 + 10 + 50, 1465 }; 1466 1467 static const struct panel_desc nvd_9128 = { 1468 .modes = &nvd_9128_mode, 1469 .num_modes = 1, 1470 .bpc = 8, 1471 .size = { 1472 .width = 156, 1473 .height = 88, 1474 }, 1475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1476 }; 1477 1478 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1479 .pixelclock = { 30000000, 30000000, 40000000 }, 1480 .hactive = { 800, 800, 800 }, 1481 .hfront_porch = { 40, 40, 40 }, 1482 .hback_porch = { 40, 40, 40 }, 1483 .hsync_len = { 1, 48, 48 }, 1484 .vactive = { 480, 480, 480 }, 1485 .vfront_porch = { 13, 13, 13 }, 1486 .vback_porch = { 29, 29, 29 }, 1487 .vsync_len = { 3, 3, 3 }, 1488 .flags = DISPLAY_FLAGS_DE_HIGH, 1489 }; 1490 1491 static const struct panel_desc okaya_rs800480t_7x0gp = { 1492 .timings = &okaya_rs800480t_7x0gp_timing, 1493 .num_timings = 1, 1494 .bpc = 6, 1495 .size = { 1496 .width = 154, 1497 .height = 87, 1498 }, 1499 .delay = { 1500 .prepare = 41, 1501 .enable = 50, 1502 .unprepare = 41, 1503 .disable = 50, 1504 }, 1505 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1506 }; 1507 1508 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1509 .clock = 9000, 1510 .hdisplay = 480, 1511 .hsync_start = 480 + 5, 1512 .hsync_end = 480 + 5 + 30, 1513 .htotal = 480 + 5 + 30 + 10, 1514 .vdisplay = 272, 1515 .vsync_start = 272 + 8, 1516 .vsync_end = 272 + 8 + 5, 1517 .vtotal = 272 + 8 + 5 + 3, 1518 .vrefresh = 60, 1519 }; 1520 1521 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1522 .modes = &olimex_lcd_olinuxino_43ts_mode, 1523 .num_modes = 1, 1524 .size = { 1525 .width = 105, 1526 .height = 67, 1527 }, 1528 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1529 }; 1530 1531 /* 1532 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1533 * pixel clocks, but this is the timing that was being used in the Adafruit 1534 * installation instructions. 1535 */ 1536 static const struct drm_display_mode ontat_yx700wv03_mode = { 1537 .clock = 29500, 1538 .hdisplay = 800, 1539 .hsync_start = 824, 1540 .hsync_end = 896, 1541 .htotal = 992, 1542 .vdisplay = 480, 1543 .vsync_start = 483, 1544 .vsync_end = 493, 1545 .vtotal = 500, 1546 .vrefresh = 60, 1547 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1548 }; 1549 1550 /* 1551 * Specification at: 1552 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1553 */ 1554 static const struct panel_desc ontat_yx700wv03 = { 1555 .modes = &ontat_yx700wv03_mode, 1556 .num_modes = 1, 1557 .bpc = 8, 1558 .size = { 1559 .width = 154, 1560 .height = 83, 1561 }, 1562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1563 }; 1564 1565 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1566 .clock = 25000, 1567 .hdisplay = 480, 1568 .hsync_start = 480 + 10, 1569 .hsync_end = 480 + 10 + 10, 1570 .htotal = 480 + 10 + 10 + 15, 1571 .vdisplay = 800, 1572 .vsync_start = 800 + 3, 1573 .vsync_end = 800 + 3 + 3, 1574 .vtotal = 800 + 3 + 3 + 3, 1575 .vrefresh = 60, 1576 }; 1577 1578 static const struct panel_desc ortustech_com43h4m85ulc = { 1579 .modes = &ortustech_com43h4m85ulc_mode, 1580 .num_modes = 1, 1581 .bpc = 8, 1582 .size = { 1583 .width = 56, 1584 .height = 93, 1585 }, 1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1588 }; 1589 1590 static const struct drm_display_mode qd43003c0_40_mode = { 1591 .clock = 9000, 1592 .hdisplay = 480, 1593 .hsync_start = 480 + 8, 1594 .hsync_end = 480 + 8 + 4, 1595 .htotal = 480 + 8 + 4 + 39, 1596 .vdisplay = 272, 1597 .vsync_start = 272 + 4, 1598 .vsync_end = 272 + 4 + 10, 1599 .vtotal = 272 + 4 + 10 + 2, 1600 .vrefresh = 60, 1601 }; 1602 1603 static const struct panel_desc qd43003c0_40 = { 1604 .modes = &qd43003c0_40_mode, 1605 .num_modes = 1, 1606 .bpc = 8, 1607 .size = { 1608 .width = 95, 1609 .height = 53, 1610 }, 1611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1612 }; 1613 1614 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1615 .clock = 271560, 1616 .hdisplay = 2560, 1617 .hsync_start = 2560 + 48, 1618 .hsync_end = 2560 + 48 + 32, 1619 .htotal = 2560 + 48 + 32 + 80, 1620 .vdisplay = 1600, 1621 .vsync_start = 1600 + 2, 1622 .vsync_end = 1600 + 2 + 5, 1623 .vtotal = 1600 + 2 + 5 + 57, 1624 .vrefresh = 60, 1625 }; 1626 1627 static const struct panel_desc samsung_lsn122dl01_c01 = { 1628 .modes = &samsung_lsn122dl01_c01_mode, 1629 .num_modes = 1, 1630 .size = { 1631 .width = 263, 1632 .height = 164, 1633 }, 1634 }; 1635 1636 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1637 .clock = 54030, 1638 .hdisplay = 1024, 1639 .hsync_start = 1024 + 24, 1640 .hsync_end = 1024 + 24 + 136, 1641 .htotal = 1024 + 24 + 136 + 160, 1642 .vdisplay = 600, 1643 .vsync_start = 600 + 3, 1644 .vsync_end = 600 + 3 + 6, 1645 .vtotal = 600 + 3 + 6 + 61, 1646 .vrefresh = 60, 1647 }; 1648 1649 static const struct panel_desc samsung_ltn101nt05 = { 1650 .modes = &samsung_ltn101nt05_mode, 1651 .num_modes = 1, 1652 .bpc = 6, 1653 .size = { 1654 .width = 223, 1655 .height = 125, 1656 }, 1657 }; 1658 1659 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1660 .clock = 76300, 1661 .hdisplay = 1366, 1662 .hsync_start = 1366 + 64, 1663 .hsync_end = 1366 + 64 + 48, 1664 .htotal = 1366 + 64 + 48 + 128, 1665 .vdisplay = 768, 1666 .vsync_start = 768 + 2, 1667 .vsync_end = 768 + 2 + 5, 1668 .vtotal = 768 + 2 + 5 + 17, 1669 .vrefresh = 60, 1670 }; 1671 1672 static const struct panel_desc samsung_ltn140at29_301 = { 1673 .modes = &samsung_ltn140at29_301_mode, 1674 .num_modes = 1, 1675 .bpc = 6, 1676 .size = { 1677 .width = 320, 1678 .height = 187, 1679 }, 1680 }; 1681 1682 static const struct display_timing sharp_lq101k1ly04_timing = { 1683 .pixelclock = { 60000000, 65000000, 80000000 }, 1684 .hactive = { 1280, 1280, 1280 }, 1685 .hfront_porch = { 20, 20, 20 }, 1686 .hback_porch = { 20, 20, 20 }, 1687 .hsync_len = { 10, 10, 10 }, 1688 .vactive = { 800, 800, 800 }, 1689 .vfront_porch = { 4, 4, 4 }, 1690 .vback_porch = { 4, 4, 4 }, 1691 .vsync_len = { 4, 4, 4 }, 1692 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1693 }; 1694 1695 static const struct panel_desc sharp_lq101k1ly04 = { 1696 .timings = &sharp_lq101k1ly04_timing, 1697 .num_timings = 1, 1698 .bpc = 8, 1699 .size = { 1700 .width = 217, 1701 .height = 136, 1702 }, 1703 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1704 }; 1705 1706 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1707 .clock = 252750, 1708 .hdisplay = 2400, 1709 .hsync_start = 2400 + 48, 1710 .hsync_end = 2400 + 48 + 32, 1711 .htotal = 2400 + 48 + 32 + 80, 1712 .vdisplay = 1600, 1713 .vsync_start = 1600 + 3, 1714 .vsync_end = 1600 + 3 + 10, 1715 .vtotal = 1600 + 3 + 10 + 33, 1716 .vrefresh = 60, 1717 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1718 }; 1719 1720 static const struct panel_desc sharp_lq123p1jx31 = { 1721 .modes = &sharp_lq123p1jx31_mode, 1722 .num_modes = 1, 1723 .bpc = 8, 1724 .size = { 1725 .width = 259, 1726 .height = 173, 1727 }, 1728 .delay = { 1729 .prepare = 110, 1730 .enable = 50, 1731 .unprepare = 550, 1732 }, 1733 }; 1734 1735 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 1736 .clock = 71100, 1737 .hdisplay = 1024, 1738 .hsync_start = 1024 + 168, 1739 .hsync_end = 1024 + 168 + 64, 1740 .htotal = 1024 + 168 + 64 + 88, 1741 .vdisplay = 768, 1742 .vsync_start = 768 + 37, 1743 .vsync_end = 768 + 37 + 2, 1744 .vtotal = 768 + 37 + 2 + 8, 1745 .vrefresh = 60, 1746 }; 1747 1748 static const struct panel_desc sharp_lq150x1lg11 = { 1749 .modes = &sharp_lq150x1lg11_mode, 1750 .num_modes = 1, 1751 .bpc = 6, 1752 .size = { 1753 .width = 304, 1754 .height = 228, 1755 }, 1756 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 1757 }; 1758 1759 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1760 .clock = 33300, 1761 .hdisplay = 800, 1762 .hsync_start = 800 + 1, 1763 .hsync_end = 800 + 1 + 64, 1764 .htotal = 800 + 1 + 64 + 64, 1765 .vdisplay = 480, 1766 .vsync_start = 480 + 1, 1767 .vsync_end = 480 + 1 + 23, 1768 .vtotal = 480 + 1 + 23 + 22, 1769 .vrefresh = 60, 1770 }; 1771 1772 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1773 .modes = &shelly_sca07010_bfn_lnn_mode, 1774 .num_modes = 1, 1775 .size = { 1776 .width = 152, 1777 .height = 91, 1778 }, 1779 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1780 }; 1781 1782 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1783 .clock = 147000, 1784 .hdisplay = 1920, 1785 .hsync_start = 1920 + 16, 1786 .hsync_end = 1920 + 16 + 16, 1787 .htotal = 1920 + 16 + 16 + 32, 1788 .vdisplay = 1200, 1789 .vsync_start = 1200 + 15, 1790 .vsync_end = 1200 + 15 + 2, 1791 .vtotal = 1200 + 15 + 2 + 18, 1792 .vrefresh = 60, 1793 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1794 }; 1795 1796 static const struct panel_desc starry_kr122ea0sra = { 1797 .modes = &starry_kr122ea0sra_mode, 1798 .num_modes = 1, 1799 .size = { 1800 .width = 263, 1801 .height = 164, 1802 }, 1803 .delay = { 1804 .prepare = 10 + 200, 1805 .enable = 50, 1806 .unprepare = 10 + 500, 1807 }, 1808 }; 1809 1810 static const struct display_timing tianma_tm070jdhg30_timing = { 1811 .pixelclock = { 62600000, 68200000, 78100000 }, 1812 .hactive = { 1280, 1280, 1280 }, 1813 .hfront_porch = { 15, 64, 159 }, 1814 .hback_porch = { 5, 5, 5 }, 1815 .hsync_len = { 1, 1, 256 }, 1816 .vactive = { 800, 800, 800 }, 1817 .vfront_porch = { 3, 40, 99 }, 1818 .vback_porch = { 2, 2, 2 }, 1819 .vsync_len = { 1, 1, 128 }, 1820 .flags = DISPLAY_FLAGS_DE_HIGH, 1821 }; 1822 1823 static const struct panel_desc tianma_tm070jdhg30 = { 1824 .timings = &tianma_tm070jdhg30_timing, 1825 .num_timings = 1, 1826 .bpc = 8, 1827 .size = { 1828 .width = 151, 1829 .height = 95, 1830 }, 1831 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1832 }; 1833 1834 static const struct drm_display_mode tpk_f07a_0102_mode = { 1835 .clock = 33260, 1836 .hdisplay = 800, 1837 .hsync_start = 800 + 40, 1838 .hsync_end = 800 + 40 + 128, 1839 .htotal = 800 + 40 + 128 + 88, 1840 .vdisplay = 480, 1841 .vsync_start = 480 + 10, 1842 .vsync_end = 480 + 10 + 2, 1843 .vtotal = 480 + 10 + 2 + 33, 1844 .vrefresh = 60, 1845 }; 1846 1847 static const struct panel_desc tpk_f07a_0102 = { 1848 .modes = &tpk_f07a_0102_mode, 1849 .num_modes = 1, 1850 .size = { 1851 .width = 152, 1852 .height = 91, 1853 }, 1854 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1855 }; 1856 1857 static const struct drm_display_mode tpk_f10a_0102_mode = { 1858 .clock = 45000, 1859 .hdisplay = 1024, 1860 .hsync_start = 1024 + 176, 1861 .hsync_end = 1024 + 176 + 5, 1862 .htotal = 1024 + 176 + 5 + 88, 1863 .vdisplay = 600, 1864 .vsync_start = 600 + 20, 1865 .vsync_end = 600 + 20 + 5, 1866 .vtotal = 600 + 20 + 5 + 25, 1867 .vrefresh = 60, 1868 }; 1869 1870 static const struct panel_desc tpk_f10a_0102 = { 1871 .modes = &tpk_f10a_0102_mode, 1872 .num_modes = 1, 1873 .size = { 1874 .width = 223, 1875 .height = 125, 1876 }, 1877 }; 1878 1879 static const struct display_timing urt_umsh_8596md_timing = { 1880 .pixelclock = { 33260000, 33260000, 33260000 }, 1881 .hactive = { 800, 800, 800 }, 1882 .hfront_porch = { 41, 41, 41 }, 1883 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1884 .hsync_len = { 71, 128, 128 }, 1885 .vactive = { 480, 480, 480 }, 1886 .vfront_porch = { 10, 10, 10 }, 1887 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1888 .vsync_len = { 2, 2, 2 }, 1889 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1890 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1891 }; 1892 1893 static const struct panel_desc urt_umsh_8596md_lvds = { 1894 .timings = &urt_umsh_8596md_timing, 1895 .num_timings = 1, 1896 .bpc = 6, 1897 .size = { 1898 .width = 152, 1899 .height = 91, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1902 }; 1903 1904 static const struct panel_desc urt_umsh_8596md_parallel = { 1905 .timings = &urt_umsh_8596md_timing, 1906 .num_timings = 1, 1907 .bpc = 6, 1908 .size = { 1909 .width = 152, 1910 .height = 91, 1911 }, 1912 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1913 }; 1914 1915 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 1916 .clock = 6410, 1917 .hdisplay = 320, 1918 .hsync_start = 320 + 20, 1919 .hsync_end = 320 + 20 + 30, 1920 .htotal = 320 + 20 + 30 + 38, 1921 .vdisplay = 240, 1922 .vsync_start = 240 + 4, 1923 .vsync_end = 240 + 4 + 3, 1924 .vtotal = 240 + 4 + 3 + 15, 1925 .vrefresh = 60, 1926 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1927 }; 1928 1929 static const struct panel_desc winstar_wf35ltiacd = { 1930 .modes = &winstar_wf35ltiacd_mode, 1931 .num_modes = 1, 1932 .bpc = 8, 1933 .size = { 1934 .width = 70, 1935 .height = 53, 1936 }, 1937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1938 }; 1939 1940 static const struct of_device_id platform_of_match[] = { 1941 { 1942 .compatible = "ampire,am-480272h3tmqw-t01h", 1943 .data = &ire_am_480272h3tmqw_t01h, 1944 }, { 1945 .compatible = "ampire,am800480r3tmqwa1h", 1946 .data = &ire_am800480r3tmqwa1h, 1947 }, { 1948 .compatible = "auo,b101aw03", 1949 .data = &auo_b101aw03, 1950 }, { 1951 .compatible = "auo,b101ean01", 1952 .data = &auo_b101ean01, 1953 }, { 1954 .compatible = "auo,b101xtn01", 1955 .data = &auo_b101xtn01, 1956 }, { 1957 .compatible = "auo,b116xw03", 1958 .data = &auo_b116xw03, 1959 }, { 1960 .compatible = "auo,b133htn01", 1961 .data = &auo_b133htn01, 1962 }, { 1963 .compatible = "auo,b133xtn01", 1964 .data = &auo_b133xtn01, 1965 }, { 1966 .compatible = "auo,g133han01", 1967 .data = &auo_g133han01, 1968 }, { 1969 .compatible = "auo,g185han01", 1970 .data = &auo_g185han01, 1971 }, { 1972 .compatible = "auo,p320hvn03", 1973 .data = &auo_p320hvn03, 1974 }, { 1975 .compatible = "auo,t215hvn01", 1976 .data = &auo_t215hvn01, 1977 }, { 1978 .compatible = "avic,tm070ddh03", 1979 .data = &avic_tm070ddh03, 1980 }, { 1981 .compatible = "boe,nv101wxmn51", 1982 .data = &boe_nv101wxmn51, 1983 }, { 1984 .compatible = "chunghwa,claa070wp03xg", 1985 .data = &chunghwa_claa070wp03xg, 1986 }, { 1987 .compatible = "chunghwa,claa101wa01a", 1988 .data = &chunghwa_claa101wa01a 1989 }, { 1990 .compatible = "chunghwa,claa101wb01", 1991 .data = &chunghwa_claa101wb01 1992 }, { 1993 .compatible = "edt,et057090dhu", 1994 .data = &edt_et057090dhu, 1995 }, { 1996 .compatible = "edt,et070080dh6", 1997 .data = &edt_etm0700g0dh6, 1998 }, { 1999 .compatible = "edt,etm0700g0dh6", 2000 .data = &edt_etm0700g0dh6, 2001 }, { 2002 .compatible = "foxlink,fl500wvr00-a0t", 2003 .data = &foxlink_fl500wvr00_a0t, 2004 }, { 2005 .compatible = "giantplus,gpg482739qs5", 2006 .data = &giantplus_gpg482739qs5 2007 }, { 2008 .compatible = "hannstar,hsd070pww1", 2009 .data = &hannstar_hsd070pww1, 2010 }, { 2011 .compatible = "hannstar,hsd100pxn1", 2012 .data = &hannstar_hsd100pxn1, 2013 }, { 2014 .compatible = "hit,tx23d38vm0caa", 2015 .data = &hitachi_tx23d38vm0caa 2016 }, { 2017 .compatible = "innolux,at043tn24", 2018 .data = &innolux_at043tn24, 2019 }, { 2020 .compatible = "innolux,at070tn92", 2021 .data = &innolux_at070tn92, 2022 }, { 2023 .compatible ="innolux,g101ice-l01", 2024 .data = &innolux_g101ice_l01 2025 }, { 2026 .compatible ="innolux,g121i1-l01", 2027 .data = &innolux_g121i1_l01 2028 }, { 2029 .compatible = "innolux,g121x1-l03", 2030 .data = &innolux_g121x1_l03, 2031 }, { 2032 .compatible = "innolux,n116bge", 2033 .data = &innolux_n116bge, 2034 }, { 2035 .compatible = "innolux,n156bge-l21", 2036 .data = &innolux_n156bge_l21, 2037 }, { 2038 .compatible = "innolux,zj070na-01p", 2039 .data = &innolux_zj070na_01p, 2040 }, { 2041 .compatible = "kyo,tcg121xglp", 2042 .data = &kyo_tcg121xglp, 2043 }, { 2044 .compatible = "lg,lb070wv8", 2045 .data = &lg_lb070wv8, 2046 }, { 2047 .compatible = "lg,lp079qx1-sp0v", 2048 .data = &lg_lp079qx1_sp0v, 2049 }, { 2050 .compatible = "lg,lp097qx1-spa1", 2051 .data = &lg_lp097qx1_spa1, 2052 }, { 2053 .compatible = "lg,lp120up1", 2054 .data = &lg_lp120up1, 2055 }, { 2056 .compatible = "lg,lp129qe", 2057 .data = &lg_lp129qe, 2058 }, { 2059 .compatible = "nec,nl12880bc20-05", 2060 .data = &nec_nl12880bc20_05, 2061 }, { 2062 .compatible = "nec,nl4827hc19-05b", 2063 .data = &nec_nl4827hc19_05b, 2064 }, { 2065 .compatible = "netron-dy,e231732", 2066 .data = &netron_dy_e231732, 2067 }, { 2068 .compatible = "nlt,nl192108ac18-02d", 2069 .data = &nlt_nl192108ac18_02d, 2070 }, { 2071 .compatible = "nvd,9128", 2072 .data = &nvd_9128, 2073 }, { 2074 .compatible = "okaya,rs800480t-7x0gp", 2075 .data = &okaya_rs800480t_7x0gp, 2076 }, { 2077 .compatible = "olimex,lcd-olinuxino-43-ts", 2078 .data = &olimex_lcd_olinuxino_43ts, 2079 }, { 2080 .compatible = "ontat,yx700wv03", 2081 .data = &ontat_yx700wv03, 2082 }, { 2083 .compatible = "ortustech,com43h4m85ulc", 2084 .data = &ortustech_com43h4m85ulc, 2085 }, { 2086 .compatible = "qiaodian,qd43003c0-40", 2087 .data = &qd43003c0_40, 2088 }, { 2089 .compatible = "samsung,lsn122dl01-c01", 2090 .data = &samsung_lsn122dl01_c01, 2091 }, { 2092 .compatible = "samsung,ltn101nt05", 2093 .data = &samsung_ltn101nt05, 2094 }, { 2095 .compatible = "samsung,ltn140at29-301", 2096 .data = &samsung_ltn140at29_301, 2097 }, { 2098 .compatible = "sharp,lq101k1ly04", 2099 .data = &sharp_lq101k1ly04, 2100 }, { 2101 .compatible = "sharp,lq123p1jx31", 2102 .data = &sharp_lq123p1jx31, 2103 }, { 2104 .compatible = "sharp,lq150x1lg11", 2105 .data = &sharp_lq150x1lg11, 2106 }, { 2107 .compatible = "shelly,sca07010-bfn-lnn", 2108 .data = &shelly_sca07010_bfn_lnn, 2109 }, { 2110 .compatible = "starry,kr122ea0sra", 2111 .data = &starry_kr122ea0sra, 2112 }, { 2113 .compatible = "tianma,tm070jdhg30", 2114 .data = &tianma_tm070jdhg30, 2115 }, { 2116 .compatible = "tpk,f07a-0102", 2117 .data = &tpk_f07a_0102, 2118 }, { 2119 .compatible = "tpk,f10a-0102", 2120 .data = &tpk_f10a_0102, 2121 }, { 2122 .compatible = "urt,umsh-8596md-t", 2123 .data = &urt_umsh_8596md_parallel, 2124 }, { 2125 .compatible = "urt,umsh-8596md-1t", 2126 .data = &urt_umsh_8596md_parallel, 2127 }, { 2128 .compatible = "urt,umsh-8596md-7t", 2129 .data = &urt_umsh_8596md_parallel, 2130 }, { 2131 .compatible = "urt,umsh-8596md-11t", 2132 .data = &urt_umsh_8596md_lvds, 2133 }, { 2134 .compatible = "urt,umsh-8596md-19t", 2135 .data = &urt_umsh_8596md_lvds, 2136 }, { 2137 .compatible = "urt,umsh-8596md-20t", 2138 .data = &urt_umsh_8596md_parallel, 2139 }, { 2140 .compatible = "winstar,wf35ltiacd", 2141 .data = &winstar_wf35ltiacd, 2142 }, { 2143 /* sentinel */ 2144 } 2145 }; 2146 MODULE_DEVICE_TABLE(of, platform_of_match); 2147 2148 static int panel_simple_platform_probe(struct platform_device *pdev) 2149 { 2150 const struct of_device_id *id; 2151 2152 id = of_match_node(platform_of_match, pdev->dev.of_node); 2153 if (!id) 2154 return -ENODEV; 2155 2156 return panel_simple_probe(&pdev->dev, id->data); 2157 } 2158 2159 static int panel_simple_platform_remove(struct platform_device *pdev) 2160 { 2161 return panel_simple_remove(&pdev->dev); 2162 } 2163 2164 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2165 { 2166 panel_simple_shutdown(&pdev->dev); 2167 } 2168 2169 static struct platform_driver panel_simple_platform_driver = { 2170 .driver = { 2171 .name = "panel-simple", 2172 .of_match_table = platform_of_match, 2173 }, 2174 .probe = panel_simple_platform_probe, 2175 .remove = panel_simple_platform_remove, 2176 .shutdown = panel_simple_platform_shutdown, 2177 }; 2178 2179 struct panel_desc_dsi { 2180 struct panel_desc desc; 2181 2182 unsigned long flags; 2183 enum mipi_dsi_pixel_format format; 2184 unsigned int lanes; 2185 }; 2186 2187 static const struct drm_display_mode auo_b080uan01_mode = { 2188 .clock = 154500, 2189 .hdisplay = 1200, 2190 .hsync_start = 1200 + 62, 2191 .hsync_end = 1200 + 62 + 4, 2192 .htotal = 1200 + 62 + 4 + 62, 2193 .vdisplay = 1920, 2194 .vsync_start = 1920 + 9, 2195 .vsync_end = 1920 + 9 + 2, 2196 .vtotal = 1920 + 9 + 2 + 8, 2197 .vrefresh = 60, 2198 }; 2199 2200 static const struct panel_desc_dsi auo_b080uan01 = { 2201 .desc = { 2202 .modes = &auo_b080uan01_mode, 2203 .num_modes = 1, 2204 .bpc = 8, 2205 .size = { 2206 .width = 108, 2207 .height = 272, 2208 }, 2209 }, 2210 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2211 .format = MIPI_DSI_FMT_RGB888, 2212 .lanes = 4, 2213 }; 2214 2215 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2216 .clock = 160000, 2217 .hdisplay = 1200, 2218 .hsync_start = 1200 + 120, 2219 .hsync_end = 1200 + 120 + 20, 2220 .htotal = 1200 + 120 + 20 + 21, 2221 .vdisplay = 1920, 2222 .vsync_start = 1920 + 21, 2223 .vsync_end = 1920 + 21 + 3, 2224 .vtotal = 1920 + 21 + 3 + 18, 2225 .vrefresh = 60, 2226 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2227 }; 2228 2229 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2230 .desc = { 2231 .modes = &boe_tv080wum_nl0_mode, 2232 .num_modes = 1, 2233 .size = { 2234 .width = 107, 2235 .height = 172, 2236 }, 2237 }, 2238 .flags = MIPI_DSI_MODE_VIDEO | 2239 MIPI_DSI_MODE_VIDEO_BURST | 2240 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2241 .format = MIPI_DSI_FMT_RGB888, 2242 .lanes = 4, 2243 }; 2244 2245 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2246 .clock = 71000, 2247 .hdisplay = 800, 2248 .hsync_start = 800 + 32, 2249 .hsync_end = 800 + 32 + 1, 2250 .htotal = 800 + 32 + 1 + 57, 2251 .vdisplay = 1280, 2252 .vsync_start = 1280 + 28, 2253 .vsync_end = 1280 + 28 + 1, 2254 .vtotal = 1280 + 28 + 1 + 14, 2255 .vrefresh = 60, 2256 }; 2257 2258 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2259 .desc = { 2260 .modes = &lg_ld070wx3_sl01_mode, 2261 .num_modes = 1, 2262 .bpc = 8, 2263 .size = { 2264 .width = 94, 2265 .height = 151, 2266 }, 2267 }, 2268 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2269 .format = MIPI_DSI_FMT_RGB888, 2270 .lanes = 4, 2271 }; 2272 2273 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2274 .clock = 67000, 2275 .hdisplay = 720, 2276 .hsync_start = 720 + 12, 2277 .hsync_end = 720 + 12 + 4, 2278 .htotal = 720 + 12 + 4 + 112, 2279 .vdisplay = 1280, 2280 .vsync_start = 1280 + 8, 2281 .vsync_end = 1280 + 8 + 4, 2282 .vtotal = 1280 + 8 + 4 + 12, 2283 .vrefresh = 60, 2284 }; 2285 2286 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2287 .desc = { 2288 .modes = &lg_lh500wx1_sd03_mode, 2289 .num_modes = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 62, 2293 .height = 110, 2294 }, 2295 }, 2296 .flags = MIPI_DSI_MODE_VIDEO, 2297 .format = MIPI_DSI_FMT_RGB888, 2298 .lanes = 4, 2299 }; 2300 2301 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2302 .clock = 157200, 2303 .hdisplay = 1920, 2304 .hsync_start = 1920 + 154, 2305 .hsync_end = 1920 + 154 + 16, 2306 .htotal = 1920 + 154 + 16 + 32, 2307 .vdisplay = 1200, 2308 .vsync_start = 1200 + 17, 2309 .vsync_end = 1200 + 17 + 2, 2310 .vtotal = 1200 + 17 + 2 + 16, 2311 .vrefresh = 60, 2312 }; 2313 2314 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2315 .desc = { 2316 .modes = &panasonic_vvx10f004b00_mode, 2317 .num_modes = 1, 2318 .bpc = 8, 2319 .size = { 2320 .width = 217, 2321 .height = 136, 2322 }, 2323 }, 2324 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2325 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2326 .format = MIPI_DSI_FMT_RGB888, 2327 .lanes = 4, 2328 }; 2329 2330 static const struct of_device_id dsi_of_match[] = { 2331 { 2332 .compatible = "auo,b080uan01", 2333 .data = &auo_b080uan01 2334 }, { 2335 .compatible = "boe,tv080wum-nl0", 2336 .data = &boe_tv080wum_nl0 2337 }, { 2338 .compatible = "lg,ld070wx3-sl01", 2339 .data = &lg_ld070wx3_sl01 2340 }, { 2341 .compatible = "lg,lh500wx1-sd03", 2342 .data = &lg_lh500wx1_sd03 2343 }, { 2344 .compatible = "panasonic,vvx10f004b00", 2345 .data = &panasonic_vvx10f004b00 2346 }, { 2347 /* sentinel */ 2348 } 2349 }; 2350 MODULE_DEVICE_TABLE(of, dsi_of_match); 2351 2352 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2353 { 2354 const struct panel_desc_dsi *desc; 2355 const struct of_device_id *id; 2356 int err; 2357 2358 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2359 if (!id) 2360 return -ENODEV; 2361 2362 desc = id->data; 2363 2364 err = panel_simple_probe(&dsi->dev, &desc->desc); 2365 if (err < 0) 2366 return err; 2367 2368 dsi->mode_flags = desc->flags; 2369 dsi->format = desc->format; 2370 dsi->lanes = desc->lanes; 2371 2372 return mipi_dsi_attach(dsi); 2373 } 2374 2375 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2376 { 2377 int err; 2378 2379 err = mipi_dsi_detach(dsi); 2380 if (err < 0) 2381 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2382 2383 return panel_simple_remove(&dsi->dev); 2384 } 2385 2386 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2387 { 2388 panel_simple_shutdown(&dsi->dev); 2389 } 2390 2391 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2392 .driver = { 2393 .name = "panel-simple-dsi", 2394 .of_match_table = dsi_of_match, 2395 }, 2396 .probe = panel_simple_dsi_probe, 2397 .remove = panel_simple_dsi_remove, 2398 .shutdown = panel_simple_dsi_shutdown, 2399 }; 2400 2401 static int __init panel_simple_init(void) 2402 { 2403 int err; 2404 2405 err = platform_driver_register(&panel_simple_platform_driver); 2406 if (err < 0) 2407 return err; 2408 2409 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2410 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2411 if (err < 0) 2412 return err; 2413 } 2414 2415 return 0; 2416 } 2417 module_init(panel_simple_init); 2418 2419 static void __exit panel_simple_exit(void) 2420 { 2421 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2422 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2423 2424 platform_driver_unregister(&panel_simple_platform_driver); 2425 } 2426 module_exit(panel_simple_exit); 2427 2428 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2429 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2430 MODULE_LICENSE("GPL and additional rights"); 2431