1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t unprepared_time; 145 146 const struct panel_desc *desc; 147 148 struct regulator *supply; 149 struct i2c_adapter *ddc; 150 151 struct gpio_desc *enable_gpio; 152 153 struct edid *edid; 154 155 struct drm_display_mode override_mode; 156 157 enum drm_panel_orientation orientation; 158 }; 159 160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 161 { 162 return container_of(panel, struct panel_simple, base); 163 } 164 165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 166 struct drm_connector *connector) 167 { 168 struct drm_display_mode *mode; 169 unsigned int i, num = 0; 170 171 for (i = 0; i < panel->desc->num_timings; i++) { 172 const struct display_timing *dt = &panel->desc->timings[i]; 173 struct videomode vm; 174 175 videomode_from_timing(dt, &vm); 176 mode = drm_mode_create(connector->dev); 177 if (!mode) { 178 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 179 dt->hactive.typ, dt->vactive.typ); 180 continue; 181 } 182 183 drm_display_mode_from_videomode(&vm, mode); 184 185 mode->type |= DRM_MODE_TYPE_DRIVER; 186 187 if (panel->desc->num_timings == 1) 188 mode->type |= DRM_MODE_TYPE_PREFERRED; 189 190 drm_mode_probed_add(connector, mode); 191 num++; 192 } 193 194 return num; 195 } 196 197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 198 struct drm_connector *connector) 199 { 200 struct drm_display_mode *mode; 201 unsigned int i, num = 0; 202 203 for (i = 0; i < panel->desc->num_modes; i++) { 204 const struct drm_display_mode *m = &panel->desc->modes[i]; 205 206 mode = drm_mode_duplicate(connector->dev, m); 207 if (!mode) { 208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 209 m->hdisplay, m->vdisplay, 210 drm_mode_vrefresh(m)); 211 continue; 212 } 213 214 mode->type |= DRM_MODE_TYPE_DRIVER; 215 216 if (panel->desc->num_modes == 1) 217 mode->type |= DRM_MODE_TYPE_PREFERRED; 218 219 drm_mode_set_name(mode); 220 221 drm_mode_probed_add(connector, mode); 222 num++; 223 } 224 225 return num; 226 } 227 228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 229 struct drm_connector *connector) 230 { 231 struct drm_display_mode *mode; 232 bool has_override = panel->override_mode.type; 233 unsigned int num = 0; 234 235 if (!panel->desc) 236 return 0; 237 238 if (has_override) { 239 mode = drm_mode_duplicate(connector->dev, 240 &panel->override_mode); 241 if (mode) { 242 drm_mode_probed_add(connector, mode); 243 num = 1; 244 } else { 245 dev_err(panel->base.dev, "failed to add override mode\n"); 246 } 247 } 248 249 /* Only add timings if override was not there or failed to validate */ 250 if (num == 0 && panel->desc->num_timings) 251 num = panel_simple_get_timings_modes(panel, connector); 252 253 /* 254 * Only add fixed modes if timings/override added no mode. 255 * 256 * We should only ever have either the display timings specified 257 * or a fixed mode. Anything else is rather bogus. 258 */ 259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 260 if (num == 0) 261 num = panel_simple_get_display_modes(panel, connector); 262 263 connector->display_info.bpc = panel->desc->bpc; 264 connector->display_info.width_mm = panel->desc->size.width; 265 connector->display_info.height_mm = panel->desc->size.height; 266 if (panel->desc->bus_format) 267 drm_display_info_set_bus_formats(&connector->display_info, 268 &panel->desc->bus_format, 1); 269 connector->display_info.bus_flags = panel->desc->bus_flags; 270 271 return num; 272 } 273 274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 275 { 276 ktime_t now_ktime, min_ktime; 277 278 if (!min_ms) 279 return; 280 281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 282 now_ktime = ktime_get_boottime(); 283 284 if (ktime_before(now_ktime, min_ktime)) 285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 286 } 287 288 static int panel_simple_disable(struct drm_panel *panel) 289 { 290 struct panel_simple *p = to_panel_simple(panel); 291 292 if (!p->enabled) 293 return 0; 294 295 if (p->desc->delay.disable) 296 msleep(p->desc->delay.disable); 297 298 p->enabled = false; 299 300 return 0; 301 } 302 303 static int panel_simple_suspend(struct device *dev) 304 { 305 struct panel_simple *p = dev_get_drvdata(dev); 306 307 gpiod_set_value_cansleep(p->enable_gpio, 0); 308 regulator_disable(p->supply); 309 p->unprepared_time = ktime_get_boottime(); 310 311 kfree(p->edid); 312 p->edid = NULL; 313 314 return 0; 315 } 316 317 static int panel_simple_unprepare(struct drm_panel *panel) 318 { 319 struct panel_simple *p = to_panel_simple(panel); 320 int ret; 321 322 /* Unpreparing when already unprepared is a no-op */ 323 if (!p->prepared) 324 return 0; 325 326 pm_runtime_mark_last_busy(panel->dev); 327 ret = pm_runtime_put_autosuspend(panel->dev); 328 if (ret < 0) 329 return ret; 330 p->prepared = false; 331 332 return 0; 333 } 334 335 static int panel_simple_resume(struct device *dev) 336 { 337 struct panel_simple *p = dev_get_drvdata(dev); 338 int err; 339 340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 341 342 err = regulator_enable(p->supply); 343 if (err < 0) { 344 dev_err(dev, "failed to enable supply: %d\n", err); 345 return err; 346 } 347 348 gpiod_set_value_cansleep(p->enable_gpio, 1); 349 350 if (p->desc->delay.prepare) 351 msleep(p->desc->delay.prepare); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* 415 * TODO: Remove once all drm drivers call 416 * drm_connector_set_orientation_from_panel() 417 */ 418 drm_connector_set_panel_orientation(connector, p->orientation); 419 420 return num; 421 } 422 423 static int panel_simple_get_timings(struct drm_panel *panel, 424 unsigned int num_timings, 425 struct display_timing *timings) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 unsigned int i; 429 430 if (p->desc->num_timings < num_timings) 431 num_timings = p->desc->num_timings; 432 433 if (timings) 434 for (i = 0; i < num_timings; i++) 435 timings[i] = p->desc->timings[i]; 436 437 return p->desc->num_timings; 438 } 439 440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 441 { 442 struct panel_simple *p = to_panel_simple(panel); 443 444 return p->orientation; 445 } 446 447 static const struct drm_panel_funcs panel_simple_funcs = { 448 .disable = panel_simple_disable, 449 .unprepare = panel_simple_unprepare, 450 .prepare = panel_simple_prepare, 451 .enable = panel_simple_enable, 452 .get_modes = panel_simple_get_modes, 453 .get_orientation = panel_simple_get_orientation, 454 .get_timings = panel_simple_get_timings, 455 }; 456 457 static struct panel_desc panel_dpi; 458 459 static int panel_dpi_probe(struct device *dev, 460 struct panel_simple *panel) 461 { 462 struct display_timing *timing; 463 const struct device_node *np; 464 struct panel_desc *desc; 465 unsigned int bus_flags; 466 struct videomode vm; 467 int ret; 468 469 np = dev->of_node; 470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 471 if (!desc) 472 return -ENOMEM; 473 474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 475 if (!timing) 476 return -ENOMEM; 477 478 ret = of_get_display_timing(np, "panel-timing", timing); 479 if (ret < 0) { 480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 481 np); 482 return ret; 483 } 484 485 desc->timings = timing; 486 desc->num_timings = 1; 487 488 of_property_read_u32(np, "width-mm", &desc->size.width); 489 of_property_read_u32(np, "height-mm", &desc->size.height); 490 491 /* Extract bus_flags from display_timing */ 492 bus_flags = 0; 493 vm.flags = timing->flags; 494 drm_bus_flags_from_videomode(&vm, &bus_flags); 495 desc->bus_flags = bus_flags; 496 497 /* We do not know the connector for the DT node, so guess it */ 498 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 499 500 panel->desc = desc; 501 502 return 0; 503 } 504 505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 506 (to_check->field.typ >= bounds->field.min && \ 507 to_check->field.typ <= bounds->field.max) 508 static void panel_simple_parse_panel_timing_node(struct device *dev, 509 struct panel_simple *panel, 510 const struct display_timing *ot) 511 { 512 const struct panel_desc *desc = panel->desc; 513 struct videomode vm; 514 unsigned int i; 515 516 if (WARN_ON(desc->num_modes)) { 517 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 518 return; 519 } 520 if (WARN_ON(!desc->num_timings)) { 521 dev_err(dev, "Reject override mode: no timings specified\n"); 522 return; 523 } 524 525 for (i = 0; i < panel->desc->num_timings; i++) { 526 const struct display_timing *dt = &panel->desc->timings[i]; 527 528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 536 continue; 537 538 if (ot->flags != dt->flags) 539 continue; 540 541 videomode_from_timing(ot, &vm); 542 drm_display_mode_from_videomode(&vm, &panel->override_mode); 543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 544 DRM_MODE_TYPE_PREFERRED; 545 break; 546 } 547 548 if (WARN_ON(!panel->override_mode.type)) 549 dev_err(dev, "Reject override mode: No display_timing found\n"); 550 } 551 552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 553 { 554 struct panel_simple *panel; 555 struct display_timing dt; 556 struct device_node *ddc; 557 int connector_type; 558 u32 bus_flags; 559 int err; 560 561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 562 if (!panel) 563 return -ENOMEM; 564 565 panel->enabled = false; 566 panel->desc = desc; 567 568 panel->supply = devm_regulator_get(dev, "power"); 569 if (IS_ERR(panel->supply)) 570 return PTR_ERR(panel->supply); 571 572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 573 GPIOD_OUT_LOW); 574 if (IS_ERR(panel->enable_gpio)) 575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 576 "failed to request GPIO\n"); 577 578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 579 if (err) { 580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 581 return err; 582 } 583 584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 585 if (ddc) { 586 panel->ddc = of_find_i2c_adapter_by_node(ddc); 587 of_node_put(ddc); 588 589 if (!panel->ddc) 590 return -EPROBE_DEFER; 591 } 592 593 if (desc == &panel_dpi) { 594 /* Handle the generic panel-dpi binding */ 595 err = panel_dpi_probe(dev, panel); 596 if (err) 597 goto free_ddc; 598 desc = panel->desc; 599 } else { 600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 601 panel_simple_parse_panel_timing_node(dev, panel, &dt); 602 } 603 604 connector_type = desc->connector_type; 605 /* Catch common mistakes for panels. */ 606 switch (connector_type) { 607 case 0: 608 dev_warn(dev, "Specify missing connector_type\n"); 609 connector_type = DRM_MODE_CONNECTOR_DPI; 610 break; 611 case DRM_MODE_CONNECTOR_LVDS: 612 WARN_ON(desc->bus_flags & 613 ~(DRM_BUS_FLAG_DE_LOW | 614 DRM_BUS_FLAG_DE_HIGH | 615 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 616 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 621 desc->bpc != 6); 622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 624 desc->bpc != 8); 625 break; 626 case DRM_MODE_CONNECTOR_eDP: 627 dev_warn(dev, "eDP panels moved to panel-edp\n"); 628 err = -EINVAL; 629 goto free_ddc; 630 case DRM_MODE_CONNECTOR_DSI: 631 if (desc->bpc != 6 && desc->bpc != 8) 632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 633 break; 634 case DRM_MODE_CONNECTOR_DPI: 635 bus_flags = DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 639 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 640 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 643 if (desc->bus_flags & ~bus_flags) 644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 645 if (!(desc->bus_flags & bus_flags)) 646 dev_warn(dev, "Specify missing bus_flags\n"); 647 if (desc->bus_format == 0) 648 dev_warn(dev, "Specify missing bus_format\n"); 649 if (desc->bpc != 6 && desc->bpc != 8) 650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 651 break; 652 default: 653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 654 connector_type = DRM_MODE_CONNECTOR_DPI; 655 break; 656 } 657 658 dev_set_drvdata(dev, panel); 659 660 /* 661 * We use runtime PM for prepare / unprepare since those power the panel 662 * on and off and those can be very slow operations. This is important 663 * to optimize powering the panel on briefly to read the EDID before 664 * fully enabling the panel. 665 */ 666 pm_runtime_enable(dev); 667 pm_runtime_set_autosuspend_delay(dev, 1000); 668 pm_runtime_use_autosuspend(dev); 669 670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 671 672 err = drm_panel_of_backlight(&panel->base); 673 if (err) { 674 dev_err_probe(dev, err, "Could not find backlight\n"); 675 goto disable_pm_runtime; 676 } 677 678 drm_panel_add(&panel->base); 679 680 return 0; 681 682 disable_pm_runtime: 683 pm_runtime_dont_use_autosuspend(dev); 684 pm_runtime_disable(dev); 685 free_ddc: 686 if (panel->ddc) 687 put_device(&panel->ddc->dev); 688 689 return err; 690 } 691 692 static void panel_simple_remove(struct device *dev) 693 { 694 struct panel_simple *panel = dev_get_drvdata(dev); 695 696 drm_panel_remove(&panel->base); 697 drm_panel_disable(&panel->base); 698 drm_panel_unprepare(&panel->base); 699 700 pm_runtime_dont_use_autosuspend(dev); 701 pm_runtime_disable(dev); 702 if (panel->ddc) 703 put_device(&panel->ddc->dev); 704 } 705 706 static void panel_simple_shutdown(struct device *dev) 707 { 708 struct panel_simple *panel = dev_get_drvdata(dev); 709 710 drm_panel_disable(&panel->base); 711 drm_panel_unprepare(&panel->base); 712 } 713 714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 715 .clock = 71100, 716 .hdisplay = 1280, 717 .hsync_start = 1280 + 40, 718 .hsync_end = 1280 + 40 + 80, 719 .htotal = 1280 + 40 + 80 + 40, 720 .vdisplay = 800, 721 .vsync_start = 800 + 3, 722 .vsync_end = 800 + 3 + 10, 723 .vtotal = 800 + 3 + 10 + 10, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 728 .modes = &ire_am_1280800n3tzqw_t00h_mode, 729 .num_modes = 1, 730 .bpc = 8, 731 .size = { 732 .width = 217, 733 .height = 136, 734 }, 735 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 738 }; 739 740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 741 .clock = 9000, 742 .hdisplay = 480, 743 .hsync_start = 480 + 2, 744 .hsync_end = 480 + 2 + 41, 745 .htotal = 480 + 2 + 41 + 2, 746 .vdisplay = 272, 747 .vsync_start = 272 + 2, 748 .vsync_end = 272 + 2 + 10, 749 .vtotal = 272 + 2 + 10 + 2, 750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 751 }; 752 753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 754 .modes = &ire_am_480272h3tmqw_t01h_mode, 755 .num_modes = 1, 756 .bpc = 8, 757 .size = { 758 .width = 99, 759 .height = 58, 760 }, 761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 762 }; 763 764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 765 .clock = 33333, 766 .hdisplay = 800, 767 .hsync_start = 800 + 0, 768 .hsync_end = 800 + 0 + 255, 769 .htotal = 800 + 0 + 255 + 0, 770 .vdisplay = 480, 771 .vsync_start = 480 + 2, 772 .vsync_end = 480 + 2 + 45, 773 .vtotal = 480 + 2 + 45 + 0, 774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 775 }; 776 777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 778 .pixelclock = { 29930000, 33260000, 36590000 }, 779 .hactive = { 800, 800, 800 }, 780 .hfront_porch = { 1, 40, 168 }, 781 .hback_porch = { 88, 88, 88 }, 782 .hsync_len = { 1, 128, 128 }, 783 .vactive = { 480, 480, 480 }, 784 .vfront_porch = { 1, 35, 37 }, 785 .vback_porch = { 8, 8, 8 }, 786 .vsync_len = { 1, 2, 2 }, 787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 789 DISPLAY_FLAGS_SYNC_POSEDGE, 790 }; 791 792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 793 .timings = &ire_am_800480l1tmqw_t00h_timing, 794 .num_timings = 1, 795 .bpc = 8, 796 .size = { 797 .width = 111, 798 .height = 67, 799 }, 800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 804 .connector_type = DRM_MODE_CONNECTOR_DPI, 805 }; 806 807 static const struct panel_desc ampire_am800480r3tmqwa1h = { 808 .modes = &ire_am800480r3tmqwa1h_mode, 809 .num_modes = 1, 810 .bpc = 6, 811 .size = { 812 .width = 152, 813 .height = 91, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 }; 817 818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 819 .pixelclock = { 34500000, 39600000, 50400000 }, 820 .hactive = { 800, 800, 800 }, 821 .hfront_porch = { 12, 112, 312 }, 822 .hback_porch = { 87, 87, 48 }, 823 .hsync_len = { 1, 1, 40 }, 824 .vactive = { 600, 600, 600 }, 825 .vfront_porch = { 1, 21, 61 }, 826 .vback_porch = { 38, 38, 19 }, 827 .vsync_len = { 1, 1, 20 }, 828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 830 DISPLAY_FLAGS_SYNC_POSEDGE, 831 }; 832 833 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 834 .timings = &ire_am800600p5tmqw_tb8h_timing, 835 .num_timings = 1, 836 .bpc = 6, 837 .size = { 838 .width = 162, 839 .height = 122, 840 }, 841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 845 .connector_type = DRM_MODE_CONNECTOR_DPI, 846 }; 847 848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 849 .pixelclock = { 26400000, 33300000, 46800000 }, 850 .hactive = { 800, 800, 800 }, 851 .hfront_porch = { 16, 210, 354 }, 852 .hback_porch = { 45, 36, 6 }, 853 .hsync_len = { 1, 10, 40 }, 854 .vactive = { 480, 480, 480 }, 855 .vfront_porch = { 7, 22, 147 }, 856 .vback_porch = { 22, 13, 3 }, 857 .vsync_len = { 1, 10, 20 }, 858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 860 }; 861 862 static const struct panel_desc armadeus_st0700_adapt = { 863 .timings = &santek_st0700i5y_rbslw_f_timing, 864 .num_timings = 1, 865 .bpc = 6, 866 .size = { 867 .width = 154, 868 .height = 86, 869 }, 870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 872 }; 873 874 static const struct drm_display_mode auo_b101aw03_mode = { 875 .clock = 51450, 876 .hdisplay = 1024, 877 .hsync_start = 1024 + 156, 878 .hsync_end = 1024 + 156 + 8, 879 .htotal = 1024 + 156 + 8 + 156, 880 .vdisplay = 600, 881 .vsync_start = 600 + 16, 882 .vsync_end = 600 + 16 + 6, 883 .vtotal = 600 + 16 + 6 + 16, 884 }; 885 886 static const struct panel_desc auo_b101aw03 = { 887 .modes = &auo_b101aw03_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897 }; 898 899 static const struct drm_display_mode auo_b101xtn01_mode = { 900 .clock = 72000, 901 .hdisplay = 1366, 902 .hsync_start = 1366 + 20, 903 .hsync_end = 1366 + 20 + 70, 904 .htotal = 1366 + 20 + 70, 905 .vdisplay = 768, 906 .vsync_start = 768 + 14, 907 .vsync_end = 768 + 14 + 42, 908 .vtotal = 768 + 14 + 42, 909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 910 }; 911 912 static const struct panel_desc auo_b101xtn01 = { 913 .modes = &auo_b101xtn01_mode, 914 .num_modes = 1, 915 .bpc = 6, 916 .size = { 917 .width = 223, 918 .height = 125, 919 }, 920 }; 921 922 static const struct drm_display_mode auo_b116xw03_mode = { 923 .clock = 70589, 924 .hdisplay = 1366, 925 .hsync_start = 1366 + 40, 926 .hsync_end = 1366 + 40 + 40, 927 .htotal = 1366 + 40 + 40 + 32, 928 .vdisplay = 768, 929 .vsync_start = 768 + 10, 930 .vsync_end = 768 + 10 + 12, 931 .vtotal = 768 + 10 + 12 + 6, 932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 933 }; 934 935 static const struct panel_desc auo_b116xw03 = { 936 .modes = &auo_b116xw03_mode, 937 .num_modes = 1, 938 .bpc = 6, 939 .size = { 940 .width = 256, 941 .height = 144, 942 }, 943 .delay = { 944 .prepare = 1, 945 .enable = 200, 946 .disable = 200, 947 .unprepare = 500, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 950 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952 }; 953 954 static const struct display_timing auo_g070vvn01_timings = { 955 .pixelclock = { 33300000, 34209000, 45000000 }, 956 .hactive = { 800, 800, 800 }, 957 .hfront_porch = { 20, 40, 200 }, 958 .hback_porch = { 87, 40, 1 }, 959 .hsync_len = { 1, 48, 87 }, 960 .vactive = { 480, 480, 480 }, 961 .vfront_porch = { 5, 13, 200 }, 962 .vback_porch = { 31, 31, 29 }, 963 .vsync_len = { 1, 1, 3 }, 964 }; 965 966 static const struct panel_desc auo_g070vvn01 = { 967 .timings = &auo_g070vvn01_timings, 968 .num_timings = 1, 969 .bpc = 8, 970 .size = { 971 .width = 152, 972 .height = 91, 973 }, 974 .delay = { 975 .prepare = 200, 976 .enable = 50, 977 .disable = 50, 978 .unprepare = 1000, 979 }, 980 }; 981 982 static const struct drm_display_mode auo_g101evn010_mode = { 983 .clock = 68930, 984 .hdisplay = 1280, 985 .hsync_start = 1280 + 82, 986 .hsync_end = 1280 + 82 + 2, 987 .htotal = 1280 + 82 + 2 + 84, 988 .vdisplay = 800, 989 .vsync_start = 800 + 8, 990 .vsync_end = 800 + 8 + 2, 991 .vtotal = 800 + 8 + 2 + 6, 992 }; 993 994 static const struct panel_desc auo_g101evn010 = { 995 .modes = &auo_g101evn010_mode, 996 .num_modes = 1, 997 .bpc = 6, 998 .size = { 999 .width = 216, 1000 .height = 135, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1004 }; 1005 1006 static const struct drm_display_mode auo_g104sn02_mode = { 1007 .clock = 40000, 1008 .hdisplay = 800, 1009 .hsync_start = 800 + 40, 1010 .hsync_end = 800 + 40 + 216, 1011 .htotal = 800 + 40 + 216 + 128, 1012 .vdisplay = 600, 1013 .vsync_start = 600 + 10, 1014 .vsync_end = 600 + 10 + 35, 1015 .vtotal = 600 + 10 + 35 + 2, 1016 }; 1017 1018 static const struct panel_desc auo_g104sn02 = { 1019 .modes = &auo_g104sn02_mode, 1020 .num_modes = 1, 1021 .bpc = 8, 1022 .size = { 1023 .width = 211, 1024 .height = 158, 1025 }, 1026 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1027 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1028 }; 1029 1030 static const struct display_timing auo_g121ean01_timing = { 1031 .pixelclock = { 60000000, 74400000, 90000000 }, 1032 .hactive = { 1280, 1280, 1280 }, 1033 .hfront_porch = { 20, 50, 100 }, 1034 .hback_porch = { 20, 50, 100 }, 1035 .hsync_len = { 30, 100, 200 }, 1036 .vactive = { 800, 800, 800 }, 1037 .vfront_porch = { 2, 10, 25 }, 1038 .vback_porch = { 2, 10, 25 }, 1039 .vsync_len = { 4, 18, 50 }, 1040 }; 1041 1042 static const struct panel_desc auo_g121ean01 = { 1043 .timings = &auo_g121ean01_timing, 1044 .num_timings = 1, 1045 .bpc = 8, 1046 .size = { 1047 .width = 261, 1048 .height = 163, 1049 }, 1050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct display_timing auo_g133han01_timings = { 1055 .pixelclock = { 134000000, 141200000, 149000000 }, 1056 .hactive = { 1920, 1920, 1920 }, 1057 .hfront_porch = { 39, 58, 77 }, 1058 .hback_porch = { 59, 88, 117 }, 1059 .hsync_len = { 28, 42, 56 }, 1060 .vactive = { 1080, 1080, 1080 }, 1061 .vfront_porch = { 3, 8, 11 }, 1062 .vback_porch = { 5, 14, 19 }, 1063 .vsync_len = { 4, 14, 19 }, 1064 }; 1065 1066 static const struct panel_desc auo_g133han01 = { 1067 .timings = &auo_g133han01_timings, 1068 .num_timings = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 293, 1072 .height = 165, 1073 }, 1074 .delay = { 1075 .prepare = 200, 1076 .enable = 50, 1077 .disable = 50, 1078 .unprepare = 1000, 1079 }, 1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1082 }; 1083 1084 static const struct drm_display_mode auo_g156xtn01_mode = { 1085 .clock = 76000, 1086 .hdisplay = 1366, 1087 .hsync_start = 1366 + 33, 1088 .hsync_end = 1366 + 33 + 67, 1089 .htotal = 1560, 1090 .vdisplay = 768, 1091 .vsync_start = 768 + 4, 1092 .vsync_end = 768 + 4 + 4, 1093 .vtotal = 806, 1094 }; 1095 1096 static const struct panel_desc auo_g156xtn01 = { 1097 .modes = &auo_g156xtn01_mode, 1098 .num_modes = 1, 1099 .bpc = 8, 1100 .size = { 1101 .width = 344, 1102 .height = 194, 1103 }, 1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1106 }; 1107 1108 static const struct display_timing auo_g185han01_timings = { 1109 .pixelclock = { 120000000, 144000000, 175000000 }, 1110 .hactive = { 1920, 1920, 1920 }, 1111 .hfront_porch = { 36, 120, 148 }, 1112 .hback_porch = { 24, 88, 108 }, 1113 .hsync_len = { 20, 48, 64 }, 1114 .vactive = { 1080, 1080, 1080 }, 1115 .vfront_porch = { 6, 10, 40 }, 1116 .vback_porch = { 2, 5, 20 }, 1117 .vsync_len = { 2, 5, 20 }, 1118 }; 1119 1120 static const struct panel_desc auo_g185han01 = { 1121 .timings = &auo_g185han01_timings, 1122 .num_timings = 1, 1123 .bpc = 8, 1124 .size = { 1125 .width = 409, 1126 .height = 230, 1127 }, 1128 .delay = { 1129 .prepare = 50, 1130 .enable = 200, 1131 .disable = 110, 1132 .unprepare = 1000, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g190ean01_timings = { 1139 .pixelclock = { 90000000, 108000000, 135000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 126, 184, 1266 }, 1142 .hback_porch = { 84, 122, 844 }, 1143 .hsync_len = { 70, 102, 704 }, 1144 .vactive = { 1024, 1024, 1024 }, 1145 .vfront_porch = { 4, 26, 76 }, 1146 .vback_porch = { 2, 8, 25 }, 1147 .vsync_len = { 2, 8, 25 }, 1148 }; 1149 1150 static const struct panel_desc auo_g190ean01 = { 1151 .timings = &auo_g190ean01_timings, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 376, 1156 .height = 301, 1157 }, 1158 .delay = { 1159 .prepare = 50, 1160 .enable = 200, 1161 .disable = 110, 1162 .unprepare = 1000, 1163 }, 1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166 }; 1167 1168 static const struct display_timing auo_p320hvn03_timings = { 1169 .pixelclock = { 106000000, 148500000, 164000000 }, 1170 .hactive = { 1920, 1920, 1920 }, 1171 .hfront_porch = { 25, 50, 130 }, 1172 .hback_porch = { 25, 50, 130 }, 1173 .hsync_len = { 20, 40, 105 }, 1174 .vactive = { 1080, 1080, 1080 }, 1175 .vfront_porch = { 8, 17, 150 }, 1176 .vback_porch = { 8, 17, 150 }, 1177 .vsync_len = { 4, 11, 100 }, 1178 }; 1179 1180 static const struct panel_desc auo_p320hvn03 = { 1181 .timings = &auo_p320hvn03_timings, 1182 .num_timings = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 698, 1186 .height = 393, 1187 }, 1188 .delay = { 1189 .prepare = 1, 1190 .enable = 450, 1191 .unprepare = 500, 1192 }, 1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1195 }; 1196 1197 static const struct drm_display_mode auo_t215hvn01_mode = { 1198 .clock = 148800, 1199 .hdisplay = 1920, 1200 .hsync_start = 1920 + 88, 1201 .hsync_end = 1920 + 88 + 44, 1202 .htotal = 1920 + 88 + 44 + 148, 1203 .vdisplay = 1080, 1204 .vsync_start = 1080 + 4, 1205 .vsync_end = 1080 + 4 + 5, 1206 .vtotal = 1080 + 4 + 5 + 36, 1207 }; 1208 1209 static const struct panel_desc auo_t215hvn01 = { 1210 .modes = &auo_t215hvn01_mode, 1211 .num_modes = 1, 1212 .bpc = 8, 1213 .size = { 1214 .width = 430, 1215 .height = 270, 1216 }, 1217 .delay = { 1218 .disable = 5, 1219 .unprepare = 1000, 1220 }, 1221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1223 }; 1224 1225 static const struct drm_display_mode avic_tm070ddh03_mode = { 1226 .clock = 51200, 1227 .hdisplay = 1024, 1228 .hsync_start = 1024 + 160, 1229 .hsync_end = 1024 + 160 + 4, 1230 .htotal = 1024 + 160 + 4 + 156, 1231 .vdisplay = 600, 1232 .vsync_start = 600 + 17, 1233 .vsync_end = 600 + 17 + 1, 1234 .vtotal = 600 + 17 + 1 + 17, 1235 }; 1236 1237 static const struct panel_desc avic_tm070ddh03 = { 1238 .modes = &avic_tm070ddh03_mode, 1239 .num_modes = 1, 1240 .bpc = 8, 1241 .size = { 1242 .width = 154, 1243 .height = 90, 1244 }, 1245 .delay = { 1246 .prepare = 20, 1247 .enable = 200, 1248 .disable = 200, 1249 }, 1250 }; 1251 1252 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1253 .clock = 30000, 1254 .hdisplay = 800, 1255 .hsync_start = 800 + 40, 1256 .hsync_end = 800 + 40 + 48, 1257 .htotal = 800 + 40 + 48 + 40, 1258 .vdisplay = 480, 1259 .vsync_start = 480 + 13, 1260 .vsync_end = 480 + 13 + 3, 1261 .vtotal = 480 + 13 + 3 + 29, 1262 }; 1263 1264 static const struct panel_desc bananapi_s070wv20_ct16 = { 1265 .modes = &bananapi_s070wv20_ct16_mode, 1266 .num_modes = 1, 1267 .bpc = 6, 1268 .size = { 1269 .width = 154, 1270 .height = 86, 1271 }, 1272 }; 1273 1274 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1275 .pixelclock = { 69922000, 71000000, 72293000 }, 1276 .hactive = { 1280, 1280, 1280 }, 1277 .hfront_porch = { 48, 48, 48 }, 1278 .hback_porch = { 80, 80, 80 }, 1279 .hsync_len = { 32, 32, 32 }, 1280 .vactive = { 800, 800, 800 }, 1281 .vfront_porch = { 3, 3, 3 }, 1282 .vback_porch = { 14, 14, 14 }, 1283 .vsync_len = { 6, 6, 6 }, 1284 }; 1285 1286 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1287 .timings = &boe_ev121wxm_n10_1850_timing, 1288 .num_timings = 1, 1289 .bpc = 8, 1290 .size = { 1291 .width = 261, 1292 .height = 163, 1293 }, 1294 .delay = { 1295 .prepare = 9, 1296 .enable = 300, 1297 .unprepare = 300, 1298 .disable = 560, 1299 }, 1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1301 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1302 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1303 }; 1304 1305 static const struct drm_display_mode boe_hv070wsa_mode = { 1306 .clock = 42105, 1307 .hdisplay = 1024, 1308 .hsync_start = 1024 + 30, 1309 .hsync_end = 1024 + 30 + 30, 1310 .htotal = 1024 + 30 + 30 + 30, 1311 .vdisplay = 600, 1312 .vsync_start = 600 + 10, 1313 .vsync_end = 600 + 10 + 10, 1314 .vtotal = 600 + 10 + 10 + 10, 1315 }; 1316 1317 static const struct panel_desc boe_hv070wsa = { 1318 .modes = &boe_hv070wsa_mode, 1319 .num_modes = 1, 1320 .bpc = 8, 1321 .size = { 1322 .width = 154, 1323 .height = 90, 1324 }, 1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1326 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1328 }; 1329 1330 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1331 .clock = 9000, 1332 .hdisplay = 480, 1333 .hsync_start = 480 + 5, 1334 .hsync_end = 480 + 5 + 5, 1335 .htotal = 480 + 5 + 5 + 40, 1336 .vdisplay = 272, 1337 .vsync_start = 272 + 8, 1338 .vsync_end = 272 + 8 + 8, 1339 .vtotal = 272 + 8 + 8 + 8, 1340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1341 }; 1342 1343 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1344 .modes = &cdtech_s043wq26h_ct7_mode, 1345 .num_modes = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 95, 1349 .height = 54, 1350 }, 1351 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1352 }; 1353 1354 /* S070PWS19HP-FC21 2017/04/22 */ 1355 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1356 .clock = 51200, 1357 .hdisplay = 1024, 1358 .hsync_start = 1024 + 160, 1359 .hsync_end = 1024 + 160 + 20, 1360 .htotal = 1024 + 160 + 20 + 140, 1361 .vdisplay = 600, 1362 .vsync_start = 600 + 12, 1363 .vsync_end = 600 + 12 + 3, 1364 .vtotal = 600 + 12 + 3 + 20, 1365 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1366 }; 1367 1368 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1369 .modes = &cdtech_s070pws19hp_fc21_mode, 1370 .num_modes = 1, 1371 .bpc = 6, 1372 .size = { 1373 .width = 154, 1374 .height = 86, 1375 }, 1376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1378 .connector_type = DRM_MODE_CONNECTOR_DPI, 1379 }; 1380 1381 /* S070SWV29HG-DC44 2017/09/21 */ 1382 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1383 .clock = 33300, 1384 .hdisplay = 800, 1385 .hsync_start = 800 + 210, 1386 .hsync_end = 800 + 210 + 2, 1387 .htotal = 800 + 210 + 2 + 44, 1388 .vdisplay = 480, 1389 .vsync_start = 480 + 22, 1390 .vsync_end = 480 + 22 + 2, 1391 .vtotal = 480 + 22 + 2 + 21, 1392 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1393 }; 1394 1395 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1396 .modes = &cdtech_s070swv29hg_dc44_mode, 1397 .num_modes = 1, 1398 .bpc = 6, 1399 .size = { 1400 .width = 154, 1401 .height = 86, 1402 }, 1403 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1404 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1405 .connector_type = DRM_MODE_CONNECTOR_DPI, 1406 }; 1407 1408 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1409 .clock = 35000, 1410 .hdisplay = 800, 1411 .hsync_start = 800 + 40, 1412 .hsync_end = 800 + 40 + 40, 1413 .htotal = 800 + 40 + 40 + 48, 1414 .vdisplay = 480, 1415 .vsync_start = 480 + 29, 1416 .vsync_end = 480 + 29 + 13, 1417 .vtotal = 480 + 29 + 13 + 3, 1418 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1419 }; 1420 1421 static const struct panel_desc cdtech_s070wv95_ct16 = { 1422 .modes = &cdtech_s070wv95_ct16_mode, 1423 .num_modes = 1, 1424 .bpc = 8, 1425 .size = { 1426 .width = 154, 1427 .height = 85, 1428 }, 1429 }; 1430 1431 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1432 .pixelclock = { 68900000, 71100000, 73400000 }, 1433 .hactive = { 1280, 1280, 1280 }, 1434 .hfront_porch = { 65, 80, 95 }, 1435 .hback_porch = { 64, 79, 94 }, 1436 .hsync_len = { 1, 1, 1 }, 1437 .vactive = { 800, 800, 800 }, 1438 .vfront_porch = { 7, 11, 14 }, 1439 .vback_porch = { 7, 11, 14 }, 1440 .vsync_len = { 1, 1, 1 }, 1441 .flags = DISPLAY_FLAGS_DE_HIGH, 1442 }; 1443 1444 static const struct panel_desc chefree_ch101olhlwh_002 = { 1445 .timings = &chefree_ch101olhlwh_002_timing, 1446 .num_timings = 1, 1447 .bpc = 8, 1448 .size = { 1449 .width = 217, 1450 .height = 135, 1451 }, 1452 .delay = { 1453 .enable = 200, 1454 .disable = 200, 1455 }, 1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1457 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1458 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1459 }; 1460 1461 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1462 .clock = 66770, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 49, 1465 .hsync_end = 800 + 49 + 33, 1466 .htotal = 800 + 49 + 33 + 17, 1467 .vdisplay = 1280, 1468 .vsync_start = 1280 + 1, 1469 .vsync_end = 1280 + 1 + 7, 1470 .vtotal = 1280 + 1 + 7 + 15, 1471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1472 }; 1473 1474 static const struct panel_desc chunghwa_claa070wp03xg = { 1475 .modes = &chunghwa_claa070wp03xg_mode, 1476 .num_modes = 1, 1477 .bpc = 6, 1478 .size = { 1479 .width = 94, 1480 .height = 150, 1481 }, 1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1485 }; 1486 1487 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1488 .clock = 72070, 1489 .hdisplay = 1366, 1490 .hsync_start = 1366 + 58, 1491 .hsync_end = 1366 + 58 + 58, 1492 .htotal = 1366 + 58 + 58 + 58, 1493 .vdisplay = 768, 1494 .vsync_start = 768 + 4, 1495 .vsync_end = 768 + 4 + 4, 1496 .vtotal = 768 + 4 + 4 + 4, 1497 }; 1498 1499 static const struct panel_desc chunghwa_claa101wa01a = { 1500 .modes = &chunghwa_claa101wa01a_mode, 1501 .num_modes = 1, 1502 .bpc = 6, 1503 .size = { 1504 .width = 220, 1505 .height = 120, 1506 }, 1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510 }; 1511 1512 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1513 .clock = 69300, 1514 .hdisplay = 1366, 1515 .hsync_start = 1366 + 48, 1516 .hsync_end = 1366 + 48 + 32, 1517 .htotal = 1366 + 48 + 32 + 20, 1518 .vdisplay = 768, 1519 .vsync_start = 768 + 16, 1520 .vsync_end = 768 + 16 + 8, 1521 .vtotal = 768 + 16 + 8 + 16, 1522 }; 1523 1524 static const struct panel_desc chunghwa_claa101wb01 = { 1525 .modes = &chunghwa_claa101wb01_mode, 1526 .num_modes = 1, 1527 .bpc = 6, 1528 .size = { 1529 .width = 223, 1530 .height = 125, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535 }; 1536 1537 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1538 .pixelclock = { 5000000, 9000000, 12000000 }, 1539 .hactive = { 480, 480, 480 }, 1540 .hfront_porch = { 12, 12, 12 }, 1541 .hback_porch = { 12, 12, 12 }, 1542 .hsync_len = { 21, 21, 21 }, 1543 .vactive = { 272, 272, 272 }, 1544 .vfront_porch = { 4, 4, 4 }, 1545 .vback_porch = { 4, 4, 4 }, 1546 .vsync_len = { 8, 8, 8 }, 1547 }; 1548 1549 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1550 .timings = &dataimage_fg040346dsswbg04_timing, 1551 .num_timings = 1, 1552 .bpc = 8, 1553 .size = { 1554 .width = 95, 1555 .height = 54, 1556 }, 1557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1559 .connector_type = DRM_MODE_CONNECTOR_DPI, 1560 }; 1561 1562 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1563 .pixelclock = { 68900000, 71110000, 73400000 }, 1564 .hactive = { 1280, 1280, 1280 }, 1565 .vactive = { 800, 800, 800 }, 1566 .hback_porch = { 100, 100, 100 }, 1567 .hfront_porch = { 100, 100, 100 }, 1568 .vback_porch = { 5, 5, 5 }, 1569 .vfront_porch = { 5, 5, 5 }, 1570 .hsync_len = { 24, 24, 24 }, 1571 .vsync_len = { 3, 3, 3 }, 1572 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1573 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1574 }; 1575 1576 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1577 .timings = &dataimage_fg1001l0dsswmg01_timing, 1578 .num_timings = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 217, 1582 .height = 136, 1583 }, 1584 }; 1585 1586 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1587 .clock = 33260, 1588 .hdisplay = 800, 1589 .hsync_start = 800 + 40, 1590 .hsync_end = 800 + 40 + 128, 1591 .htotal = 800 + 40 + 128 + 88, 1592 .vdisplay = 480, 1593 .vsync_start = 480 + 10, 1594 .vsync_end = 480 + 10 + 2, 1595 .vtotal = 480 + 10 + 2 + 33, 1596 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1597 }; 1598 1599 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1600 .modes = &dataimage_scf0700c48ggu18_mode, 1601 .num_modes = 1, 1602 .bpc = 8, 1603 .size = { 1604 .width = 152, 1605 .height = 91, 1606 }, 1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1609 }; 1610 1611 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1612 .pixelclock = { 45000000, 51200000, 57000000 }, 1613 .hactive = { 1024, 1024, 1024 }, 1614 .hfront_porch = { 100, 106, 113 }, 1615 .hback_porch = { 100, 106, 113 }, 1616 .hsync_len = { 100, 108, 114 }, 1617 .vactive = { 600, 600, 600 }, 1618 .vfront_porch = { 8, 11, 15 }, 1619 .vback_porch = { 8, 11, 15 }, 1620 .vsync_len = { 9, 13, 15 }, 1621 .flags = DISPLAY_FLAGS_DE_HIGH, 1622 }; 1623 1624 static const struct panel_desc dlc_dlc0700yzg_1 = { 1625 .timings = &dlc_dlc0700yzg_1_timing, 1626 .num_timings = 1, 1627 .bpc = 6, 1628 .size = { 1629 .width = 154, 1630 .height = 86, 1631 }, 1632 .delay = { 1633 .prepare = 30, 1634 .enable = 200, 1635 .disable = 200, 1636 }, 1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1638 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1639 }; 1640 1641 static const struct display_timing dlc_dlc1010gig_timing = { 1642 .pixelclock = { 68900000, 71100000, 73400000 }, 1643 .hactive = { 1280, 1280, 1280 }, 1644 .hfront_porch = { 43, 53, 63 }, 1645 .hback_porch = { 43, 53, 63 }, 1646 .hsync_len = { 44, 54, 64 }, 1647 .vactive = { 800, 800, 800 }, 1648 .vfront_porch = { 5, 8, 11 }, 1649 .vback_porch = { 5, 8, 11 }, 1650 .vsync_len = { 5, 7, 11 }, 1651 .flags = DISPLAY_FLAGS_DE_HIGH, 1652 }; 1653 1654 static const struct panel_desc dlc_dlc1010gig = { 1655 .timings = &dlc_dlc1010gig_timing, 1656 .num_timings = 1, 1657 .bpc = 8, 1658 .size = { 1659 .width = 216, 1660 .height = 135, 1661 }, 1662 .delay = { 1663 .prepare = 60, 1664 .enable = 150, 1665 .disable = 100, 1666 .unprepare = 60, 1667 }, 1668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1669 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1670 }; 1671 1672 static const struct drm_display_mode edt_et035012dm6_mode = { 1673 .clock = 6500, 1674 .hdisplay = 320, 1675 .hsync_start = 320 + 20, 1676 .hsync_end = 320 + 20 + 30, 1677 .htotal = 320 + 20 + 68, 1678 .vdisplay = 240, 1679 .vsync_start = 240 + 4, 1680 .vsync_end = 240 + 4 + 4, 1681 .vtotal = 240 + 4 + 4 + 14, 1682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1683 }; 1684 1685 static const struct panel_desc edt_et035012dm6 = { 1686 .modes = &edt_et035012dm6_mode, 1687 .num_modes = 1, 1688 .bpc = 8, 1689 .size = { 1690 .width = 70, 1691 .height = 52, 1692 }, 1693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1694 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1695 }; 1696 1697 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1698 .clock = 6520, 1699 .hdisplay = 320, 1700 .hsync_start = 320 + 20, 1701 .hsync_end = 320 + 20 + 68, 1702 .htotal = 320 + 20 + 68, 1703 .vdisplay = 240, 1704 .vsync_start = 240 + 4, 1705 .vsync_end = 240 + 4 + 18, 1706 .vtotal = 240 + 4 + 18, 1707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1708 }; 1709 1710 static const struct panel_desc edt_etm0350g0dh6 = { 1711 .modes = &edt_etm0350g0dh6_mode, 1712 .num_modes = 1, 1713 .bpc = 6, 1714 .size = { 1715 .width = 70, 1716 .height = 53, 1717 }, 1718 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1719 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1720 .connector_type = DRM_MODE_CONNECTOR_DPI, 1721 }; 1722 1723 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1724 .clock = 10870, 1725 .hdisplay = 480, 1726 .hsync_start = 480 + 8, 1727 .hsync_end = 480 + 8 + 4, 1728 .htotal = 480 + 8 + 4 + 41, 1729 1730 /* 1731 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1732 * fb_align 1733 */ 1734 1735 .vdisplay = 288, 1736 .vsync_start = 288 + 2, 1737 .vsync_end = 288 + 2 + 4, 1738 .vtotal = 288 + 2 + 4 + 10, 1739 }; 1740 1741 static const struct panel_desc edt_etm043080dh6gp = { 1742 .modes = &edt_etm043080dh6gp_mode, 1743 .num_modes = 1, 1744 .bpc = 8, 1745 .size = { 1746 .width = 100, 1747 .height = 65, 1748 }, 1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1750 .connector_type = DRM_MODE_CONNECTOR_DPI, 1751 }; 1752 1753 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1754 .clock = 9000, 1755 .hdisplay = 480, 1756 .hsync_start = 480 + 2, 1757 .hsync_end = 480 + 2 + 41, 1758 .htotal = 480 + 2 + 41 + 2, 1759 .vdisplay = 272, 1760 .vsync_start = 272 + 2, 1761 .vsync_end = 272 + 2 + 10, 1762 .vtotal = 272 + 2 + 10 + 2, 1763 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1764 }; 1765 1766 static const struct panel_desc edt_etm0430g0dh6 = { 1767 .modes = &edt_etm0430g0dh6_mode, 1768 .num_modes = 1, 1769 .bpc = 6, 1770 .size = { 1771 .width = 95, 1772 .height = 54, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1776 .connector_type = DRM_MODE_CONNECTOR_DPI, 1777 }; 1778 1779 static const struct drm_display_mode edt_et057090dhu_mode = { 1780 .clock = 25175, 1781 .hdisplay = 640, 1782 .hsync_start = 640 + 16, 1783 .hsync_end = 640 + 16 + 30, 1784 .htotal = 640 + 16 + 30 + 114, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 3, 1788 .vtotal = 480 + 10 + 3 + 32, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790 }; 1791 1792 static const struct panel_desc edt_et057090dhu = { 1793 .modes = &edt_et057090dhu_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 115, 1798 .height = 86, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1806 .clock = 33260, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 40, 1809 .hsync_end = 800 + 40 + 128, 1810 .htotal = 800 + 40 + 128 + 88, 1811 .vdisplay = 480, 1812 .vsync_start = 480 + 10, 1813 .vsync_end = 480 + 10 + 2, 1814 .vtotal = 480 + 10 + 2 + 33, 1815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1816 }; 1817 1818 static const struct panel_desc edt_etm0700g0dh6 = { 1819 .modes = &edt_etm0700g0dh6_mode, 1820 .num_modes = 1, 1821 .bpc = 6, 1822 .size = { 1823 .width = 152, 1824 .height = 91, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1828 .connector_type = DRM_MODE_CONNECTOR_DPI, 1829 }; 1830 1831 static const struct panel_desc edt_etm0700g0bdh6 = { 1832 .modes = &edt_etm0700g0dh6_mode, 1833 .num_modes = 1, 1834 .bpc = 6, 1835 .size = { 1836 .width = 152, 1837 .height = 91, 1838 }, 1839 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1840 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1841 .connector_type = DRM_MODE_CONNECTOR_DPI, 1842 }; 1843 1844 static const struct display_timing edt_etml0700y5dha_timing = { 1845 .pixelclock = { 40800000, 51200000, 67200000 }, 1846 .hactive = { 1024, 1024, 1024 }, 1847 .hfront_porch = { 30, 106, 125 }, 1848 .hback_porch = { 30, 106, 125 }, 1849 .hsync_len = { 30, 108, 126 }, 1850 .vactive = { 600, 600, 600 }, 1851 .vfront_porch = { 3, 12, 67}, 1852 .vback_porch = { 3, 12, 67 }, 1853 .vsync_len = { 4, 11, 66 }, 1854 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1855 DISPLAY_FLAGS_DE_HIGH, 1856 }; 1857 1858 static const struct panel_desc edt_etml0700y5dha = { 1859 .timings = &edt_etml0700y5dha_timing, 1860 .num_timings = 1, 1861 .bpc = 8, 1862 .size = { 1863 .width = 155, 1864 .height = 86, 1865 }, 1866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1868 }; 1869 1870 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1871 .clock = 25175, 1872 .hdisplay = 640, 1873 .hsync_start = 640, 1874 .hsync_end = 640 + 16, 1875 .htotal = 640 + 16 + 30 + 114, 1876 .vdisplay = 480, 1877 .vsync_start = 480 + 10, 1878 .vsync_end = 480 + 10 + 3, 1879 .vtotal = 480 + 10 + 3 + 35, 1880 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1881 }; 1882 1883 static const struct panel_desc edt_etmv570g2dhu = { 1884 .modes = &edt_etmv570g2dhu_mode, 1885 .num_modes = 1, 1886 .bpc = 6, 1887 .size = { 1888 .width = 115, 1889 .height = 86, 1890 }, 1891 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1892 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1893 .connector_type = DRM_MODE_CONNECTOR_DPI, 1894 }; 1895 1896 static const struct display_timing eink_vb3300_kca_timing = { 1897 .pixelclock = { 40000000, 40000000, 40000000 }, 1898 .hactive = { 334, 334, 334 }, 1899 .hfront_porch = { 1, 1, 1 }, 1900 .hback_porch = { 1, 1, 1 }, 1901 .hsync_len = { 1, 1, 1 }, 1902 .vactive = { 1405, 1405, 1405 }, 1903 .vfront_porch = { 1, 1, 1 }, 1904 .vback_porch = { 1, 1, 1 }, 1905 .vsync_len = { 1, 1, 1 }, 1906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1908 }; 1909 1910 static const struct panel_desc eink_vb3300_kca = { 1911 .timings = &eink_vb3300_kca_timing, 1912 .num_timings = 1, 1913 .bpc = 6, 1914 .size = { 1915 .width = 157, 1916 .height = 209, 1917 }, 1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1920 .connector_type = DRM_MODE_CONNECTOR_DPI, 1921 }; 1922 1923 static const struct display_timing evervision_vgg804821_timing = { 1924 .pixelclock = { 27600000, 33300000, 50000000 }, 1925 .hactive = { 800, 800, 800 }, 1926 .hfront_porch = { 40, 66, 70 }, 1927 .hback_porch = { 40, 67, 70 }, 1928 .hsync_len = { 40, 67, 70 }, 1929 .vactive = { 480, 480, 480 }, 1930 .vfront_porch = { 6, 10, 10 }, 1931 .vback_porch = { 7, 11, 11 }, 1932 .vsync_len = { 7, 11, 11 }, 1933 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1935 DISPLAY_FLAGS_SYNC_NEGEDGE, 1936 }; 1937 1938 static const struct panel_desc evervision_vgg804821 = { 1939 .timings = &evervision_vgg804821_timing, 1940 .num_timings = 1, 1941 .bpc = 8, 1942 .size = { 1943 .width = 108, 1944 .height = 64, 1945 }, 1946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1948 }; 1949 1950 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1951 .clock = 32260, 1952 .hdisplay = 800, 1953 .hsync_start = 800 + 168, 1954 .hsync_end = 800 + 168 + 64, 1955 .htotal = 800 + 168 + 64 + 88, 1956 .vdisplay = 480, 1957 .vsync_start = 480 + 37, 1958 .vsync_end = 480 + 37 + 2, 1959 .vtotal = 480 + 37 + 2 + 8, 1960 }; 1961 1962 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1963 .modes = &foxlink_fl500wvr00_a0t_mode, 1964 .num_modes = 1, 1965 .bpc = 8, 1966 .size = { 1967 .width = 108, 1968 .height = 65, 1969 }, 1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1971 }; 1972 1973 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1974 { /* 60 Hz */ 1975 .clock = 6000, 1976 .hdisplay = 320, 1977 .hsync_start = 320 + 44, 1978 .hsync_end = 320 + 44 + 16, 1979 .htotal = 320 + 44 + 16 + 20, 1980 .vdisplay = 240, 1981 .vsync_start = 240 + 2, 1982 .vsync_end = 240 + 2 + 6, 1983 .vtotal = 240 + 2 + 6 + 2, 1984 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1985 }, 1986 { /* 50 Hz */ 1987 .clock = 5400, 1988 .hdisplay = 320, 1989 .hsync_start = 320 + 56, 1990 .hsync_end = 320 + 56 + 16, 1991 .htotal = 320 + 56 + 16 + 40, 1992 .vdisplay = 240, 1993 .vsync_start = 240 + 2, 1994 .vsync_end = 240 + 2 + 6, 1995 .vtotal = 240 + 2 + 6 + 2, 1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1997 }, 1998 }; 1999 2000 static const struct panel_desc frida_frd350h54004 = { 2001 .modes = frida_frd350h54004_modes, 2002 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2003 .bpc = 8, 2004 .size = { 2005 .width = 77, 2006 .height = 64, 2007 }, 2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2010 .connector_type = DRM_MODE_CONNECTOR_DPI, 2011 }; 2012 2013 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2014 .clock = 67185, 2015 .hdisplay = 800, 2016 .hsync_start = 800 + 20, 2017 .hsync_end = 800 + 20 + 24, 2018 .htotal = 800 + 20 + 24 + 20, 2019 .vdisplay = 1280, 2020 .vsync_start = 1280 + 4, 2021 .vsync_end = 1280 + 4 + 8, 2022 .vtotal = 1280 + 4 + 8 + 4, 2023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2024 }; 2025 2026 static const struct panel_desc friendlyarm_hd702e = { 2027 .modes = &friendlyarm_hd702e_mode, 2028 .num_modes = 1, 2029 .size = { 2030 .width = 94, 2031 .height = 151, 2032 }, 2033 }; 2034 2035 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2036 .clock = 9000, 2037 .hdisplay = 480, 2038 .hsync_start = 480 + 5, 2039 .hsync_end = 480 + 5 + 1, 2040 .htotal = 480 + 5 + 1 + 40, 2041 .vdisplay = 272, 2042 .vsync_start = 272 + 8, 2043 .vsync_end = 272 + 8 + 1, 2044 .vtotal = 272 + 8 + 1 + 8, 2045 }; 2046 2047 static const struct panel_desc giantplus_gpg482739qs5 = { 2048 .modes = &giantplus_gpg482739qs5_mode, 2049 .num_modes = 1, 2050 .bpc = 8, 2051 .size = { 2052 .width = 95, 2053 .height = 54, 2054 }, 2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2056 }; 2057 2058 static const struct display_timing giantplus_gpm940b0_timing = { 2059 .pixelclock = { 13500000, 27000000, 27500000 }, 2060 .hactive = { 320, 320, 320 }, 2061 .hfront_porch = { 14, 686, 718 }, 2062 .hback_porch = { 50, 70, 255 }, 2063 .hsync_len = { 1, 1, 1 }, 2064 .vactive = { 240, 240, 240 }, 2065 .vfront_porch = { 1, 1, 179 }, 2066 .vback_porch = { 1, 21, 31 }, 2067 .vsync_len = { 1, 1, 6 }, 2068 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2069 }; 2070 2071 static const struct panel_desc giantplus_gpm940b0 = { 2072 .timings = &giantplus_gpm940b0_timing, 2073 .num_timings = 1, 2074 .bpc = 8, 2075 .size = { 2076 .width = 60, 2077 .height = 45, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2081 }; 2082 2083 static const struct display_timing hannstar_hsd070pww1_timing = { 2084 .pixelclock = { 64300000, 71100000, 82000000 }, 2085 .hactive = { 1280, 1280, 1280 }, 2086 .hfront_porch = { 1, 1, 10 }, 2087 .hback_porch = { 1, 1, 10 }, 2088 /* 2089 * According to the data sheet, the minimum horizontal blanking interval 2090 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2091 * minimum working horizontal blanking interval to be 60 clocks. 2092 */ 2093 .hsync_len = { 58, 158, 661 }, 2094 .vactive = { 800, 800, 800 }, 2095 .vfront_porch = { 1, 1, 10 }, 2096 .vback_porch = { 1, 1, 10 }, 2097 .vsync_len = { 1, 21, 203 }, 2098 .flags = DISPLAY_FLAGS_DE_HIGH, 2099 }; 2100 2101 static const struct panel_desc hannstar_hsd070pww1 = { 2102 .timings = &hannstar_hsd070pww1_timing, 2103 .num_timings = 1, 2104 .bpc = 6, 2105 .size = { 2106 .width = 151, 2107 .height = 94, 2108 }, 2109 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2111 }; 2112 2113 static const struct display_timing hannstar_hsd100pxn1_timing = { 2114 .pixelclock = { 55000000, 65000000, 75000000 }, 2115 .hactive = { 1024, 1024, 1024 }, 2116 .hfront_porch = { 40, 40, 40 }, 2117 .hback_porch = { 220, 220, 220 }, 2118 .hsync_len = { 20, 60, 100 }, 2119 .vactive = { 768, 768, 768 }, 2120 .vfront_porch = { 7, 7, 7 }, 2121 .vback_porch = { 21, 21, 21 }, 2122 .vsync_len = { 10, 10, 10 }, 2123 .flags = DISPLAY_FLAGS_DE_HIGH, 2124 }; 2125 2126 static const struct panel_desc hannstar_hsd100pxn1 = { 2127 .timings = &hannstar_hsd100pxn1_timing, 2128 .num_timings = 1, 2129 .bpc = 6, 2130 .size = { 2131 .width = 203, 2132 .height = 152, 2133 }, 2134 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2136 }; 2137 2138 static const struct display_timing hannstar_hsd101pww2_timing = { 2139 .pixelclock = { 64300000, 71100000, 82000000 }, 2140 .hactive = { 1280, 1280, 1280 }, 2141 .hfront_porch = { 1, 1, 10 }, 2142 .hback_porch = { 1, 1, 10 }, 2143 .hsync_len = { 58, 158, 661 }, 2144 .vactive = { 800, 800, 800 }, 2145 .vfront_porch = { 1, 1, 10 }, 2146 .vback_porch = { 1, 1, 10 }, 2147 .vsync_len = { 1, 21, 203 }, 2148 .flags = DISPLAY_FLAGS_DE_HIGH, 2149 }; 2150 2151 static const struct panel_desc hannstar_hsd101pww2 = { 2152 .timings = &hannstar_hsd101pww2_timing, 2153 .num_timings = 1, 2154 .bpc = 8, 2155 .size = { 2156 .width = 217, 2157 .height = 136, 2158 }, 2159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2161 }; 2162 2163 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2164 .clock = 33333, 2165 .hdisplay = 800, 2166 .hsync_start = 800 + 85, 2167 .hsync_end = 800 + 85 + 86, 2168 .htotal = 800 + 85 + 86 + 85, 2169 .vdisplay = 480, 2170 .vsync_start = 480 + 16, 2171 .vsync_end = 480 + 16 + 13, 2172 .vtotal = 480 + 16 + 13 + 16, 2173 }; 2174 2175 static const struct panel_desc hitachi_tx23d38vm0caa = { 2176 .modes = &hitachi_tx23d38vm0caa_mode, 2177 .num_modes = 1, 2178 .bpc = 6, 2179 .size = { 2180 .width = 195, 2181 .height = 117, 2182 }, 2183 .delay = { 2184 .enable = 160, 2185 .disable = 160, 2186 }, 2187 }; 2188 2189 static const struct drm_display_mode innolux_at043tn24_mode = { 2190 .clock = 9000, 2191 .hdisplay = 480, 2192 .hsync_start = 480 + 2, 2193 .hsync_end = 480 + 2 + 41, 2194 .htotal = 480 + 2 + 41 + 2, 2195 .vdisplay = 272, 2196 .vsync_start = 272 + 2, 2197 .vsync_end = 272 + 2 + 10, 2198 .vtotal = 272 + 2 + 10 + 2, 2199 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2200 }; 2201 2202 static const struct panel_desc innolux_at043tn24 = { 2203 .modes = &innolux_at043tn24_mode, 2204 .num_modes = 1, 2205 .bpc = 8, 2206 .size = { 2207 .width = 95, 2208 .height = 54, 2209 }, 2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2211 .connector_type = DRM_MODE_CONNECTOR_DPI, 2212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2213 }; 2214 2215 static const struct drm_display_mode innolux_at070tn92_mode = { 2216 .clock = 33333, 2217 .hdisplay = 800, 2218 .hsync_start = 800 + 210, 2219 .hsync_end = 800 + 210 + 20, 2220 .htotal = 800 + 210 + 20 + 46, 2221 .vdisplay = 480, 2222 .vsync_start = 480 + 22, 2223 .vsync_end = 480 + 22 + 10, 2224 .vtotal = 480 + 22 + 23 + 10, 2225 }; 2226 2227 static const struct panel_desc innolux_at070tn92 = { 2228 .modes = &innolux_at070tn92_mode, 2229 .num_modes = 1, 2230 .size = { 2231 .width = 154, 2232 .height = 86, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2235 }; 2236 2237 static const struct display_timing innolux_g070ace_l01_timing = { 2238 .pixelclock = { 25200000, 35000000, 35700000 }, 2239 .hactive = { 800, 800, 800 }, 2240 .hfront_porch = { 30, 32, 87 }, 2241 .hback_porch = { 30, 32, 87 }, 2242 .hsync_len = { 1, 1, 1 }, 2243 .vactive = { 480, 480, 480 }, 2244 .vfront_porch = { 3, 3, 3 }, 2245 .vback_porch = { 13, 13, 13 }, 2246 .vsync_len = { 1, 1, 4 }, 2247 .flags = DISPLAY_FLAGS_DE_HIGH, 2248 }; 2249 2250 static const struct panel_desc innolux_g070ace_l01 = { 2251 .timings = &innolux_g070ace_l01_timing, 2252 .num_timings = 1, 2253 .bpc = 8, 2254 .size = { 2255 .width = 152, 2256 .height = 91, 2257 }, 2258 .delay = { 2259 .prepare = 10, 2260 .enable = 50, 2261 .disable = 50, 2262 .unprepare = 500, 2263 }, 2264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2266 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2267 }; 2268 2269 static const struct display_timing innolux_g070y2_l01_timing = { 2270 .pixelclock = { 28000000, 29500000, 32000000 }, 2271 .hactive = { 800, 800, 800 }, 2272 .hfront_porch = { 61, 91, 141 }, 2273 .hback_porch = { 60, 90, 140 }, 2274 .hsync_len = { 12, 12, 12 }, 2275 .vactive = { 480, 480, 480 }, 2276 .vfront_porch = { 4, 9, 30 }, 2277 .vback_porch = { 4, 8, 28 }, 2278 .vsync_len = { 2, 2, 2 }, 2279 .flags = DISPLAY_FLAGS_DE_HIGH, 2280 }; 2281 2282 static const struct panel_desc innolux_g070y2_l01 = { 2283 .timings = &innolux_g070y2_l01_timing, 2284 .num_timings = 1, 2285 .bpc = 8, 2286 .size = { 2287 .width = 152, 2288 .height = 91, 2289 }, 2290 .delay = { 2291 .prepare = 10, 2292 .enable = 100, 2293 .disable = 100, 2294 .unprepare = 800, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299 }; 2300 2301 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2302 .clock = 33333, 2303 .hdisplay = 800, 2304 .hsync_start = 800 + 210, 2305 .hsync_end = 800 + 210 + 20, 2306 .htotal = 800 + 210 + 20 + 46, 2307 .vdisplay = 480, 2308 .vsync_start = 480 + 22, 2309 .vsync_end = 480 + 22 + 10, 2310 .vtotal = 480 + 22 + 23 + 10, 2311 }; 2312 2313 static const struct panel_desc innolux_g070y2_t02 = { 2314 .modes = &innolux_g070y2_t02_mode, 2315 .num_modes = 1, 2316 .bpc = 8, 2317 .size = { 2318 .width = 152, 2319 .height = 92, 2320 }, 2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2322 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2323 .connector_type = DRM_MODE_CONNECTOR_DPI, 2324 }; 2325 2326 static const struct display_timing innolux_g101ice_l01_timing = { 2327 .pixelclock = { 60400000, 71100000, 74700000 }, 2328 .hactive = { 1280, 1280, 1280 }, 2329 .hfront_porch = { 41, 80, 100 }, 2330 .hback_porch = { 40, 79, 99 }, 2331 .hsync_len = { 1, 1, 1 }, 2332 .vactive = { 800, 800, 800 }, 2333 .vfront_porch = { 5, 11, 14 }, 2334 .vback_porch = { 4, 11, 14 }, 2335 .vsync_len = { 1, 1, 1 }, 2336 .flags = DISPLAY_FLAGS_DE_HIGH, 2337 }; 2338 2339 static const struct panel_desc innolux_g101ice_l01 = { 2340 .timings = &innolux_g101ice_l01_timing, 2341 .num_timings = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 217, 2345 .height = 135, 2346 }, 2347 .delay = { 2348 .enable = 200, 2349 .disable = 200, 2350 }, 2351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2352 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2353 }; 2354 2355 static const struct display_timing innolux_g121i1_l01_timing = { 2356 .pixelclock = { 67450000, 71000000, 74550000 }, 2357 .hactive = { 1280, 1280, 1280 }, 2358 .hfront_porch = { 40, 80, 160 }, 2359 .hback_porch = { 39, 79, 159 }, 2360 .hsync_len = { 1, 1, 1 }, 2361 .vactive = { 800, 800, 800 }, 2362 .vfront_porch = { 5, 11, 100 }, 2363 .vback_porch = { 4, 11, 99 }, 2364 .vsync_len = { 1, 1, 1 }, 2365 }; 2366 2367 static const struct panel_desc innolux_g121i1_l01 = { 2368 .timings = &innolux_g121i1_l01_timing, 2369 .num_timings = 1, 2370 .bpc = 6, 2371 .size = { 2372 .width = 261, 2373 .height = 163, 2374 }, 2375 .delay = { 2376 .enable = 200, 2377 .disable = 20, 2378 }, 2379 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2380 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2381 }; 2382 2383 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2384 .clock = 65000, 2385 .hdisplay = 1024, 2386 .hsync_start = 1024 + 0, 2387 .hsync_end = 1024 + 1, 2388 .htotal = 1024 + 0 + 1 + 320, 2389 .vdisplay = 768, 2390 .vsync_start = 768 + 38, 2391 .vsync_end = 768 + 38 + 1, 2392 .vtotal = 768 + 38 + 1 + 0, 2393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2394 }; 2395 2396 static const struct panel_desc innolux_g121x1_l03 = { 2397 .modes = &innolux_g121x1_l03_mode, 2398 .num_modes = 1, 2399 .bpc = 6, 2400 .size = { 2401 .width = 246, 2402 .height = 185, 2403 }, 2404 .delay = { 2405 .enable = 200, 2406 .unprepare = 200, 2407 .disable = 400, 2408 }, 2409 }; 2410 2411 static const struct display_timing innolux_g156hce_l01_timings = { 2412 .pixelclock = { 120000000, 141860000, 150000000 }, 2413 .hactive = { 1920, 1920, 1920 }, 2414 .hfront_porch = { 80, 90, 100 }, 2415 .hback_porch = { 80, 90, 100 }, 2416 .hsync_len = { 20, 30, 30 }, 2417 .vactive = { 1080, 1080, 1080 }, 2418 .vfront_porch = { 3, 10, 20 }, 2419 .vback_porch = { 3, 10, 20 }, 2420 .vsync_len = { 4, 10, 10 }, 2421 }; 2422 2423 static const struct panel_desc innolux_g156hce_l01 = { 2424 .timings = &innolux_g156hce_l01_timings, 2425 .num_timings = 1, 2426 .bpc = 8, 2427 .size = { 2428 .width = 344, 2429 .height = 194, 2430 }, 2431 .delay = { 2432 .prepare = 1, /* T1+T2 */ 2433 .enable = 450, /* T5 */ 2434 .disable = 200, /* T6 */ 2435 .unprepare = 10, /* T3+T7 */ 2436 }, 2437 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2438 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2439 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2440 }; 2441 2442 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2443 .clock = 69300, 2444 .hdisplay = 1366, 2445 .hsync_start = 1366 + 16, 2446 .hsync_end = 1366 + 16 + 34, 2447 .htotal = 1366 + 16 + 34 + 50, 2448 .vdisplay = 768, 2449 .vsync_start = 768 + 2, 2450 .vsync_end = 768 + 2 + 6, 2451 .vtotal = 768 + 2 + 6 + 12, 2452 }; 2453 2454 static const struct panel_desc innolux_n156bge_l21 = { 2455 .modes = &innolux_n156bge_l21_mode, 2456 .num_modes = 1, 2457 .bpc = 6, 2458 .size = { 2459 .width = 344, 2460 .height = 193, 2461 }, 2462 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2463 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2464 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2465 }; 2466 2467 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2468 .clock = 51501, 2469 .hdisplay = 1024, 2470 .hsync_start = 1024 + 128, 2471 .hsync_end = 1024 + 128 + 64, 2472 .htotal = 1024 + 128 + 64 + 128, 2473 .vdisplay = 600, 2474 .vsync_start = 600 + 16, 2475 .vsync_end = 600 + 16 + 4, 2476 .vtotal = 600 + 16 + 4 + 16, 2477 }; 2478 2479 static const struct panel_desc innolux_zj070na_01p = { 2480 .modes = &innolux_zj070na_01p_mode, 2481 .num_modes = 1, 2482 .bpc = 6, 2483 .size = { 2484 .width = 154, 2485 .height = 90, 2486 }, 2487 }; 2488 2489 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2490 .pixelclock = { 5580000, 5850000, 6200000 }, 2491 .hactive = { 320, 320, 320 }, 2492 .hfront_porch = { 30, 30, 30 }, 2493 .hback_porch = { 30, 30, 30 }, 2494 .hsync_len = { 1, 5, 17 }, 2495 .vactive = { 240, 240, 240 }, 2496 .vfront_porch = { 6, 6, 6 }, 2497 .vback_porch = { 5, 5, 5 }, 2498 .vsync_len = { 1, 2, 11 }, 2499 .flags = DISPLAY_FLAGS_DE_HIGH, 2500 }; 2501 2502 static const struct panel_desc koe_tx14d24vm1bpa = { 2503 .timings = &koe_tx14d24vm1bpa_timing, 2504 .num_timings = 1, 2505 .bpc = 6, 2506 .size = { 2507 .width = 115, 2508 .height = 86, 2509 }, 2510 }; 2511 2512 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2513 .pixelclock = { 151820000, 156720000, 159780000 }, 2514 .hactive = { 1920, 1920, 1920 }, 2515 .hfront_porch = { 105, 130, 142 }, 2516 .hback_porch = { 45, 70, 82 }, 2517 .hsync_len = { 30, 30, 30 }, 2518 .vactive = { 1200, 1200, 1200}, 2519 .vfront_porch = { 3, 5, 10 }, 2520 .vback_porch = { 2, 5, 10 }, 2521 .vsync_len = { 5, 5, 5 }, 2522 }; 2523 2524 static const struct panel_desc koe_tx26d202vm0bwa = { 2525 .timings = &koe_tx26d202vm0bwa_timing, 2526 .num_timings = 1, 2527 .bpc = 8, 2528 .size = { 2529 .width = 217, 2530 .height = 136, 2531 }, 2532 .delay = { 2533 .prepare = 1000, 2534 .enable = 1000, 2535 .unprepare = 1000, 2536 .disable = 1000, 2537 }, 2538 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2539 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2540 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2541 }; 2542 2543 static const struct display_timing koe_tx31d200vm0baa_timing = { 2544 .pixelclock = { 39600000, 43200000, 48000000 }, 2545 .hactive = { 1280, 1280, 1280 }, 2546 .hfront_porch = { 16, 36, 56 }, 2547 .hback_porch = { 16, 36, 56 }, 2548 .hsync_len = { 8, 8, 8 }, 2549 .vactive = { 480, 480, 480 }, 2550 .vfront_porch = { 6, 21, 33 }, 2551 .vback_porch = { 6, 21, 33 }, 2552 .vsync_len = { 8, 8, 8 }, 2553 .flags = DISPLAY_FLAGS_DE_HIGH, 2554 }; 2555 2556 static const struct panel_desc koe_tx31d200vm0baa = { 2557 .timings = &koe_tx31d200vm0baa_timing, 2558 .num_timings = 1, 2559 .bpc = 6, 2560 .size = { 2561 .width = 292, 2562 .height = 109, 2563 }, 2564 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2565 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2566 }; 2567 2568 static const struct display_timing kyo_tcg121xglp_timing = { 2569 .pixelclock = { 52000000, 65000000, 71000000 }, 2570 .hactive = { 1024, 1024, 1024 }, 2571 .hfront_porch = { 2, 2, 2 }, 2572 .hback_porch = { 2, 2, 2 }, 2573 .hsync_len = { 86, 124, 244 }, 2574 .vactive = { 768, 768, 768 }, 2575 .vfront_porch = { 2, 2, 2 }, 2576 .vback_porch = { 2, 2, 2 }, 2577 .vsync_len = { 6, 34, 73 }, 2578 .flags = DISPLAY_FLAGS_DE_HIGH, 2579 }; 2580 2581 static const struct panel_desc kyo_tcg121xglp = { 2582 .timings = &kyo_tcg121xglp_timing, 2583 .num_timings = 1, 2584 .bpc = 8, 2585 .size = { 2586 .width = 246, 2587 .height = 184, 2588 }, 2589 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2590 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2591 }; 2592 2593 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2594 .clock = 7000, 2595 .hdisplay = 320, 2596 .hsync_start = 320 + 20, 2597 .hsync_end = 320 + 20 + 30, 2598 .htotal = 320 + 20 + 30 + 38, 2599 .vdisplay = 240, 2600 .vsync_start = 240 + 4, 2601 .vsync_end = 240 + 4 + 3, 2602 .vtotal = 240 + 4 + 3 + 15, 2603 }; 2604 2605 static const struct panel_desc lemaker_bl035_rgb_002 = { 2606 .modes = &lemaker_bl035_rgb_002_mode, 2607 .num_modes = 1, 2608 .size = { 2609 .width = 70, 2610 .height = 52, 2611 }, 2612 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2613 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2614 }; 2615 2616 static const struct drm_display_mode lg_lb070wv8_mode = { 2617 .clock = 33246, 2618 .hdisplay = 800, 2619 .hsync_start = 800 + 88, 2620 .hsync_end = 800 + 88 + 80, 2621 .htotal = 800 + 88 + 80 + 88, 2622 .vdisplay = 480, 2623 .vsync_start = 480 + 10, 2624 .vsync_end = 480 + 10 + 25, 2625 .vtotal = 480 + 10 + 25 + 10, 2626 }; 2627 2628 static const struct panel_desc lg_lb070wv8 = { 2629 .modes = &lg_lb070wv8_mode, 2630 .num_modes = 1, 2631 .bpc = 8, 2632 .size = { 2633 .width = 151, 2634 .height = 91, 2635 }, 2636 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2637 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2638 }; 2639 2640 static const struct display_timing logictechno_lt161010_2nh_timing = { 2641 .pixelclock = { 26400000, 33300000, 46800000 }, 2642 .hactive = { 800, 800, 800 }, 2643 .hfront_porch = { 16, 210, 354 }, 2644 .hback_porch = { 46, 46, 46 }, 2645 .hsync_len = { 1, 20, 40 }, 2646 .vactive = { 480, 480, 480 }, 2647 .vfront_porch = { 7, 22, 147 }, 2648 .vback_porch = { 23, 23, 23 }, 2649 .vsync_len = { 1, 10, 20 }, 2650 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2651 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2652 DISPLAY_FLAGS_SYNC_POSEDGE, 2653 }; 2654 2655 static const struct panel_desc logictechno_lt161010_2nh = { 2656 .timings = &logictechno_lt161010_2nh_timing, 2657 .num_timings = 1, 2658 .bpc = 6, 2659 .size = { 2660 .width = 154, 2661 .height = 86, 2662 }, 2663 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2664 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2666 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2667 .connector_type = DRM_MODE_CONNECTOR_DPI, 2668 }; 2669 2670 static const struct display_timing logictechno_lt170410_2whc_timing = { 2671 .pixelclock = { 68900000, 71100000, 73400000 }, 2672 .hactive = { 1280, 1280, 1280 }, 2673 .hfront_porch = { 23, 60, 71 }, 2674 .hback_porch = { 23, 60, 71 }, 2675 .hsync_len = { 15, 40, 47 }, 2676 .vactive = { 800, 800, 800 }, 2677 .vfront_porch = { 5, 7, 10 }, 2678 .vback_porch = { 5, 7, 10 }, 2679 .vsync_len = { 6, 9, 12 }, 2680 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2681 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2682 DISPLAY_FLAGS_SYNC_POSEDGE, 2683 }; 2684 2685 static const struct panel_desc logictechno_lt170410_2whc = { 2686 .timings = &logictechno_lt170410_2whc_timing, 2687 .num_timings = 1, 2688 .bpc = 8, 2689 .size = { 2690 .width = 217, 2691 .height = 136, 2692 }, 2693 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2694 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2695 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2696 }; 2697 2698 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2699 .clock = 33000, 2700 .hdisplay = 800, 2701 .hsync_start = 800 + 112, 2702 .hsync_end = 800 + 112 + 3, 2703 .htotal = 800 + 112 + 3 + 85, 2704 .vdisplay = 480, 2705 .vsync_start = 480 + 38, 2706 .vsync_end = 480 + 38 + 3, 2707 .vtotal = 480 + 38 + 3 + 29, 2708 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2709 }; 2710 2711 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2712 .modes = &logictechno_lttd800480070_l2rt_mode, 2713 .num_modes = 1, 2714 .bpc = 8, 2715 .size = { 2716 .width = 154, 2717 .height = 86, 2718 }, 2719 .delay = { 2720 .prepare = 45, 2721 .enable = 100, 2722 .disable = 100, 2723 .unprepare = 45 2724 }, 2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2726 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2727 .connector_type = DRM_MODE_CONNECTOR_DPI, 2728 }; 2729 2730 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2731 .clock = 33000, 2732 .hdisplay = 800, 2733 .hsync_start = 800 + 154, 2734 .hsync_end = 800 + 154 + 3, 2735 .htotal = 800 + 154 + 3 + 43, 2736 .vdisplay = 480, 2737 .vsync_start = 480 + 47, 2738 .vsync_end = 480 + 47 + 3, 2739 .vtotal = 480 + 47 + 3 + 20, 2740 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2741 }; 2742 2743 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2744 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2745 .num_modes = 1, 2746 .bpc = 8, 2747 .size = { 2748 .width = 154, 2749 .height = 86, 2750 }, 2751 .delay = { 2752 .prepare = 45, 2753 .enable = 100, 2754 .disable = 100, 2755 .unprepare = 45 2756 }, 2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2758 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2759 .connector_type = DRM_MODE_CONNECTOR_DPI, 2760 }; 2761 2762 static const struct drm_display_mode logicpd_type_28_mode = { 2763 .clock = 9107, 2764 .hdisplay = 480, 2765 .hsync_start = 480 + 3, 2766 .hsync_end = 480 + 3 + 42, 2767 .htotal = 480 + 3 + 42 + 2, 2768 2769 .vdisplay = 272, 2770 .vsync_start = 272 + 2, 2771 .vsync_end = 272 + 2 + 11, 2772 .vtotal = 272 + 2 + 11 + 3, 2773 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2774 }; 2775 2776 static const struct panel_desc logicpd_type_28 = { 2777 .modes = &logicpd_type_28_mode, 2778 .num_modes = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 105, 2782 .height = 67, 2783 }, 2784 .delay = { 2785 .prepare = 200, 2786 .enable = 200, 2787 .unprepare = 200, 2788 .disable = 200, 2789 }, 2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2792 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2793 .connector_type = DRM_MODE_CONNECTOR_DPI, 2794 }; 2795 2796 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2797 .clock = 30400, 2798 .hdisplay = 800, 2799 .hsync_start = 800 + 0, 2800 .hsync_end = 800 + 1, 2801 .htotal = 800 + 0 + 1 + 160, 2802 .vdisplay = 480, 2803 .vsync_start = 480 + 0, 2804 .vsync_end = 480 + 48 + 1, 2805 .vtotal = 480 + 48 + 1 + 0, 2806 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2807 }; 2808 2809 static const struct panel_desc mitsubishi_aa070mc01 = { 2810 .modes = &mitsubishi_aa070mc01_mode, 2811 .num_modes = 1, 2812 .bpc = 8, 2813 .size = { 2814 .width = 152, 2815 .height = 91, 2816 }, 2817 2818 .delay = { 2819 .enable = 200, 2820 .unprepare = 200, 2821 .disable = 400, 2822 }, 2823 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2824 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2825 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2826 }; 2827 2828 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2829 .pixelclock = { 29000000, 33000000, 38000000 }, 2830 .hactive = { 800, 800, 800 }, 2831 .hfront_porch = { 180, 210, 240 }, 2832 .hback_porch = { 16, 16, 16 }, 2833 .hsync_len = { 30, 30, 30 }, 2834 .vactive = { 480, 480, 480 }, 2835 .vfront_porch = { 12, 22, 32 }, 2836 .vback_porch = { 10, 10, 10 }, 2837 .vsync_len = { 13, 13, 13 }, 2838 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2839 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2840 DISPLAY_FLAGS_SYNC_POSEDGE, 2841 }; 2842 2843 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2844 .timings = &multi_inno_mi0700s4t_6_timing, 2845 .num_timings = 1, 2846 .bpc = 8, 2847 .size = { 2848 .width = 154, 2849 .height = 86, 2850 }, 2851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2852 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2853 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2854 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2855 .connector_type = DRM_MODE_CONNECTOR_DPI, 2856 }; 2857 2858 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2859 .pixelclock = { 32000000, 40000000, 50000000 }, 2860 .hactive = { 800, 800, 800 }, 2861 .hfront_porch = { 16, 210, 354 }, 2862 .hback_porch = { 6, 26, 45 }, 2863 .hsync_len = { 1, 20, 40 }, 2864 .vactive = { 600, 600, 600 }, 2865 .vfront_porch = { 1, 12, 77 }, 2866 .vback_porch = { 3, 13, 22 }, 2867 .vsync_len = { 1, 10, 20 }, 2868 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2869 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2870 DISPLAY_FLAGS_SYNC_POSEDGE, 2871 }; 2872 2873 static const struct panel_desc multi_inno_mi0800ft_9 = { 2874 .timings = &multi_inno_mi0800ft_9_timing, 2875 .num_timings = 1, 2876 .bpc = 8, 2877 .size = { 2878 .width = 162, 2879 .height = 122, 2880 }, 2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2882 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2883 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2884 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2885 .connector_type = DRM_MODE_CONNECTOR_DPI, 2886 }; 2887 2888 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2889 .pixelclock = { 68900000, 70000000, 73400000 }, 2890 .hactive = { 1280, 1280, 1280 }, 2891 .hfront_porch = { 30, 60, 71 }, 2892 .hback_porch = { 30, 60, 71 }, 2893 .hsync_len = { 10, 10, 48 }, 2894 .vactive = { 800, 800, 800 }, 2895 .vfront_porch = { 5, 10, 10 }, 2896 .vback_porch = { 5, 10, 10 }, 2897 .vsync_len = { 5, 6, 13 }, 2898 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2899 DISPLAY_FLAGS_DE_HIGH, 2900 }; 2901 2902 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2903 .timings = &multi_inno_mi1010ait_1cp_timing, 2904 .num_timings = 1, 2905 .bpc = 8, 2906 .size = { 2907 .width = 217, 2908 .height = 136, 2909 }, 2910 .delay = { 2911 .enable = 50, 2912 .disable = 50, 2913 }, 2914 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2915 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2916 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2917 }; 2918 2919 static const struct display_timing nec_nl12880bc20_05_timing = { 2920 .pixelclock = { 67000000, 71000000, 75000000 }, 2921 .hactive = { 1280, 1280, 1280 }, 2922 .hfront_porch = { 2, 30, 30 }, 2923 .hback_porch = { 6, 100, 100 }, 2924 .hsync_len = { 2, 30, 30 }, 2925 .vactive = { 800, 800, 800 }, 2926 .vfront_porch = { 5, 5, 5 }, 2927 .vback_porch = { 11, 11, 11 }, 2928 .vsync_len = { 7, 7, 7 }, 2929 }; 2930 2931 static const struct panel_desc nec_nl12880bc20_05 = { 2932 .timings = &nec_nl12880bc20_05_timing, 2933 .num_timings = 1, 2934 .bpc = 8, 2935 .size = { 2936 .width = 261, 2937 .height = 163, 2938 }, 2939 .delay = { 2940 .enable = 50, 2941 .disable = 50, 2942 }, 2943 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2944 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2945 }; 2946 2947 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2948 .clock = 10870, 2949 .hdisplay = 480, 2950 .hsync_start = 480 + 2, 2951 .hsync_end = 480 + 2 + 41, 2952 .htotal = 480 + 2 + 41 + 2, 2953 .vdisplay = 272, 2954 .vsync_start = 272 + 2, 2955 .vsync_end = 272 + 2 + 4, 2956 .vtotal = 272 + 2 + 4 + 2, 2957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2958 }; 2959 2960 static const struct panel_desc nec_nl4827hc19_05b = { 2961 .modes = &nec_nl4827hc19_05b_mode, 2962 .num_modes = 1, 2963 .bpc = 8, 2964 .size = { 2965 .width = 95, 2966 .height = 54, 2967 }, 2968 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2969 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2970 }; 2971 2972 static const struct drm_display_mode netron_dy_e231732_mode = { 2973 .clock = 66000, 2974 .hdisplay = 1024, 2975 .hsync_start = 1024 + 160, 2976 .hsync_end = 1024 + 160 + 70, 2977 .htotal = 1024 + 160 + 70 + 90, 2978 .vdisplay = 600, 2979 .vsync_start = 600 + 127, 2980 .vsync_end = 600 + 127 + 20, 2981 .vtotal = 600 + 127 + 20 + 3, 2982 }; 2983 2984 static const struct panel_desc netron_dy_e231732 = { 2985 .modes = &netron_dy_e231732_mode, 2986 .num_modes = 1, 2987 .size = { 2988 .width = 154, 2989 .height = 87, 2990 }, 2991 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2992 }; 2993 2994 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2995 .clock = 9000, 2996 .hdisplay = 480, 2997 .hsync_start = 480 + 2, 2998 .hsync_end = 480 + 2 + 41, 2999 .htotal = 480 + 2 + 41 + 2, 3000 .vdisplay = 272, 3001 .vsync_start = 272 + 2, 3002 .vsync_end = 272 + 2 + 10, 3003 .vtotal = 272 + 2 + 10 + 2, 3004 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3005 }; 3006 3007 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3008 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3009 .num_modes = 1, 3010 .bpc = 8, 3011 .size = { 3012 .width = 95, 3013 .height = 54, 3014 }, 3015 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3016 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3017 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3018 .connector_type = DRM_MODE_CONNECTOR_DPI, 3019 }; 3020 3021 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3022 .pixelclock = { 130000000, 148350000, 163000000 }, 3023 .hactive = { 1920, 1920, 1920 }, 3024 .hfront_porch = { 80, 100, 100 }, 3025 .hback_porch = { 100, 120, 120 }, 3026 .hsync_len = { 50, 60, 60 }, 3027 .vactive = { 1080, 1080, 1080 }, 3028 .vfront_porch = { 12, 30, 30 }, 3029 .vback_porch = { 4, 10, 10 }, 3030 .vsync_len = { 4, 5, 5 }, 3031 }; 3032 3033 static const struct panel_desc nlt_nl192108ac18_02d = { 3034 .timings = &nlt_nl192108ac18_02d_timing, 3035 .num_timings = 1, 3036 .bpc = 8, 3037 .size = { 3038 .width = 344, 3039 .height = 194, 3040 }, 3041 .delay = { 3042 .unprepare = 500, 3043 }, 3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3045 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3046 }; 3047 3048 static const struct drm_display_mode nvd_9128_mode = { 3049 .clock = 29500, 3050 .hdisplay = 800, 3051 .hsync_start = 800 + 130, 3052 .hsync_end = 800 + 130 + 98, 3053 .htotal = 800 + 0 + 130 + 98, 3054 .vdisplay = 480, 3055 .vsync_start = 480 + 10, 3056 .vsync_end = 480 + 10 + 50, 3057 .vtotal = 480 + 0 + 10 + 50, 3058 }; 3059 3060 static const struct panel_desc nvd_9128 = { 3061 .modes = &nvd_9128_mode, 3062 .num_modes = 1, 3063 .bpc = 8, 3064 .size = { 3065 .width = 156, 3066 .height = 88, 3067 }, 3068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3069 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3070 }; 3071 3072 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3073 .pixelclock = { 30000000, 30000000, 40000000 }, 3074 .hactive = { 800, 800, 800 }, 3075 .hfront_porch = { 40, 40, 40 }, 3076 .hback_porch = { 40, 40, 40 }, 3077 .hsync_len = { 1, 48, 48 }, 3078 .vactive = { 480, 480, 480 }, 3079 .vfront_porch = { 13, 13, 13 }, 3080 .vback_porch = { 29, 29, 29 }, 3081 .vsync_len = { 3, 3, 3 }, 3082 .flags = DISPLAY_FLAGS_DE_HIGH, 3083 }; 3084 3085 static const struct panel_desc okaya_rs800480t_7x0gp = { 3086 .timings = &okaya_rs800480t_7x0gp_timing, 3087 .num_timings = 1, 3088 .bpc = 6, 3089 .size = { 3090 .width = 154, 3091 .height = 87, 3092 }, 3093 .delay = { 3094 .prepare = 41, 3095 .enable = 50, 3096 .unprepare = 41, 3097 .disable = 50, 3098 }, 3099 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3100 }; 3101 3102 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3103 .clock = 9000, 3104 .hdisplay = 480, 3105 .hsync_start = 480 + 5, 3106 .hsync_end = 480 + 5 + 30, 3107 .htotal = 480 + 5 + 30 + 10, 3108 .vdisplay = 272, 3109 .vsync_start = 272 + 8, 3110 .vsync_end = 272 + 8 + 5, 3111 .vtotal = 272 + 8 + 5 + 3, 3112 }; 3113 3114 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3115 .modes = &olimex_lcd_olinuxino_43ts_mode, 3116 .num_modes = 1, 3117 .size = { 3118 .width = 95, 3119 .height = 54, 3120 }, 3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3122 }; 3123 3124 /* 3125 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3126 * pixel clocks, but this is the timing that was being used in the Adafruit 3127 * installation instructions. 3128 */ 3129 static const struct drm_display_mode ontat_yx700wv03_mode = { 3130 .clock = 29500, 3131 .hdisplay = 800, 3132 .hsync_start = 824, 3133 .hsync_end = 896, 3134 .htotal = 992, 3135 .vdisplay = 480, 3136 .vsync_start = 483, 3137 .vsync_end = 493, 3138 .vtotal = 500, 3139 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3140 }; 3141 3142 /* 3143 * Specification at: 3144 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3145 */ 3146 static const struct panel_desc ontat_yx700wv03 = { 3147 .modes = &ontat_yx700wv03_mode, 3148 .num_modes = 1, 3149 .bpc = 8, 3150 .size = { 3151 .width = 154, 3152 .height = 83, 3153 }, 3154 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3155 }; 3156 3157 static const struct drm_display_mode ortustech_com37h3m_mode = { 3158 .clock = 22230, 3159 .hdisplay = 480, 3160 .hsync_start = 480 + 40, 3161 .hsync_end = 480 + 40 + 10, 3162 .htotal = 480 + 40 + 10 + 40, 3163 .vdisplay = 640, 3164 .vsync_start = 640 + 4, 3165 .vsync_end = 640 + 4 + 2, 3166 .vtotal = 640 + 4 + 2 + 4, 3167 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3168 }; 3169 3170 static const struct panel_desc ortustech_com37h3m = { 3171 .modes = &ortustech_com37h3m_mode, 3172 .num_modes = 1, 3173 .bpc = 8, 3174 .size = { 3175 .width = 56, /* 56.16mm */ 3176 .height = 75, /* 74.88mm */ 3177 }, 3178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3180 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3181 }; 3182 3183 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3184 .clock = 25000, 3185 .hdisplay = 480, 3186 .hsync_start = 480 + 10, 3187 .hsync_end = 480 + 10 + 10, 3188 .htotal = 480 + 10 + 10 + 15, 3189 .vdisplay = 800, 3190 .vsync_start = 800 + 3, 3191 .vsync_end = 800 + 3 + 3, 3192 .vtotal = 800 + 3 + 3 + 3, 3193 }; 3194 3195 static const struct panel_desc ortustech_com43h4m85ulc = { 3196 .modes = &ortustech_com43h4m85ulc_mode, 3197 .num_modes = 1, 3198 .bpc = 6, 3199 .size = { 3200 .width = 56, 3201 .height = 93, 3202 }, 3203 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3204 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3205 .connector_type = DRM_MODE_CONNECTOR_DPI, 3206 }; 3207 3208 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3209 .clock = 33000, 3210 .hdisplay = 800, 3211 .hsync_start = 800 + 210, 3212 .hsync_end = 800 + 210 + 30, 3213 .htotal = 800 + 210 + 30 + 16, 3214 .vdisplay = 480, 3215 .vsync_start = 480 + 22, 3216 .vsync_end = 480 + 22 + 13, 3217 .vtotal = 480 + 22 + 13 + 10, 3218 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3219 }; 3220 3221 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3222 .modes = &osddisplays_osd070t1718_19ts_mode, 3223 .num_modes = 1, 3224 .bpc = 8, 3225 .size = { 3226 .width = 152, 3227 .height = 91, 3228 }, 3229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3231 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3232 .connector_type = DRM_MODE_CONNECTOR_DPI, 3233 }; 3234 3235 static const struct drm_display_mode pda_91_00156_a0_mode = { 3236 .clock = 33300, 3237 .hdisplay = 800, 3238 .hsync_start = 800 + 1, 3239 .hsync_end = 800 + 1 + 64, 3240 .htotal = 800 + 1 + 64 + 64, 3241 .vdisplay = 480, 3242 .vsync_start = 480 + 1, 3243 .vsync_end = 480 + 1 + 23, 3244 .vtotal = 480 + 1 + 23 + 22, 3245 }; 3246 3247 static const struct panel_desc pda_91_00156_a0 = { 3248 .modes = &pda_91_00156_a0_mode, 3249 .num_modes = 1, 3250 .size = { 3251 .width = 152, 3252 .height = 91, 3253 }, 3254 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3255 }; 3256 3257 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3258 .clock = 24750, 3259 .hdisplay = 800, 3260 .hsync_start = 800 + 54, 3261 .hsync_end = 800 + 54 + 2, 3262 .htotal = 800 + 54 + 2 + 44, 3263 .vdisplay = 480, 3264 .vsync_start = 480 + 49, 3265 .vsync_end = 480 + 49 + 2, 3266 .vtotal = 480 + 49 + 2 + 22, 3267 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3268 }; 3269 3270 static const struct panel_desc powertip_ph800480t013_idf02 = { 3271 .modes = &powertip_ph800480t013_idf02_mode, 3272 .num_modes = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 152, 3276 .height = 91, 3277 }, 3278 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3279 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3280 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3282 .connector_type = DRM_MODE_CONNECTOR_DPI, 3283 }; 3284 3285 static const struct drm_display_mode qd43003c0_40_mode = { 3286 .clock = 9000, 3287 .hdisplay = 480, 3288 .hsync_start = 480 + 8, 3289 .hsync_end = 480 + 8 + 4, 3290 .htotal = 480 + 8 + 4 + 39, 3291 .vdisplay = 272, 3292 .vsync_start = 272 + 4, 3293 .vsync_end = 272 + 4 + 10, 3294 .vtotal = 272 + 4 + 10 + 2, 3295 }; 3296 3297 static const struct panel_desc qd43003c0_40 = { 3298 .modes = &qd43003c0_40_mode, 3299 .num_modes = 1, 3300 .bpc = 8, 3301 .size = { 3302 .width = 95, 3303 .height = 53, 3304 }, 3305 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3306 }; 3307 3308 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3309 { /* 60 Hz */ 3310 .clock = 10800, 3311 .hdisplay = 480, 3312 .hsync_start = 480 + 77, 3313 .hsync_end = 480 + 77 + 41, 3314 .htotal = 480 + 77 + 41 + 2, 3315 .vdisplay = 272, 3316 .vsync_start = 272 + 16, 3317 .vsync_end = 272 + 16 + 10, 3318 .vtotal = 272 + 16 + 10 + 2, 3319 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3320 }, 3321 { /* 50 Hz */ 3322 .clock = 10800, 3323 .hdisplay = 480, 3324 .hsync_start = 480 + 17, 3325 .hsync_end = 480 + 17 + 41, 3326 .htotal = 480 + 17 + 41 + 2, 3327 .vdisplay = 272, 3328 .vsync_start = 272 + 116, 3329 .vsync_end = 272 + 116 + 10, 3330 .vtotal = 272 + 116 + 10 + 2, 3331 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3332 }, 3333 }; 3334 3335 static const struct panel_desc qishenglong_gopher2b_lcd = { 3336 .modes = qishenglong_gopher2b_lcd_modes, 3337 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3338 .bpc = 8, 3339 .size = { 3340 .width = 95, 3341 .height = 54, 3342 }, 3343 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3344 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3345 .connector_type = DRM_MODE_CONNECTOR_DPI, 3346 }; 3347 3348 static const struct display_timing rocktech_rk043fn48h_timing = { 3349 .pixelclock = { 6000000, 9000000, 12000000 }, 3350 .hactive = { 480, 480, 480 }, 3351 .hback_porch = { 8, 43, 43 }, 3352 .hfront_porch = { 2, 8, 8 }, 3353 .hsync_len = { 1, 1, 1 }, 3354 .vactive = { 272, 272, 272 }, 3355 .vback_porch = { 2, 12, 12 }, 3356 .vfront_porch = { 1, 4, 4 }, 3357 .vsync_len = { 1, 10, 10 }, 3358 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3359 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3360 }; 3361 3362 static const struct panel_desc rocktech_rk043fn48h = { 3363 .timings = &rocktech_rk043fn48h_timing, 3364 .num_timings = 1, 3365 .bpc = 8, 3366 .size = { 3367 .width = 95, 3368 .height = 54, 3369 }, 3370 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3371 .connector_type = DRM_MODE_CONNECTOR_DPI, 3372 }; 3373 3374 static const struct display_timing rocktech_rk070er9427_timing = { 3375 .pixelclock = { 26400000, 33300000, 46800000 }, 3376 .hactive = { 800, 800, 800 }, 3377 .hfront_porch = { 16, 210, 354 }, 3378 .hback_porch = { 46, 46, 46 }, 3379 .hsync_len = { 1, 1, 1 }, 3380 .vactive = { 480, 480, 480 }, 3381 .vfront_porch = { 7, 22, 147 }, 3382 .vback_porch = { 23, 23, 23 }, 3383 .vsync_len = { 1, 1, 1 }, 3384 .flags = DISPLAY_FLAGS_DE_HIGH, 3385 }; 3386 3387 static const struct panel_desc rocktech_rk070er9427 = { 3388 .timings = &rocktech_rk070er9427_timing, 3389 .num_timings = 1, 3390 .bpc = 6, 3391 .size = { 3392 .width = 154, 3393 .height = 86, 3394 }, 3395 .delay = { 3396 .prepare = 41, 3397 .enable = 50, 3398 .unprepare = 41, 3399 .disable = 50, 3400 }, 3401 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3402 }; 3403 3404 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3405 .clock = 71100, 3406 .hdisplay = 1280, 3407 .hsync_start = 1280 + 48, 3408 .hsync_end = 1280 + 48 + 32, 3409 .htotal = 1280 + 48 + 32 + 80, 3410 .vdisplay = 800, 3411 .vsync_start = 800 + 2, 3412 .vsync_end = 800 + 2 + 5, 3413 .vtotal = 800 + 2 + 5 + 16, 3414 }; 3415 3416 static const struct panel_desc rocktech_rk101ii01d_ct = { 3417 .modes = &rocktech_rk101ii01d_ct_mode, 3418 .bpc = 8, 3419 .num_modes = 1, 3420 .size = { 3421 .width = 217, 3422 .height = 136, 3423 }, 3424 .delay = { 3425 .prepare = 50, 3426 .disable = 50, 3427 }, 3428 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3429 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3430 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3431 }; 3432 3433 static const struct display_timing samsung_ltl101al01_timing = { 3434 .pixelclock = { 66663000, 66663000, 66663000 }, 3435 .hactive = { 1280, 1280, 1280 }, 3436 .hfront_porch = { 18, 18, 18 }, 3437 .hback_porch = { 36, 36, 36 }, 3438 .hsync_len = { 16, 16, 16 }, 3439 .vactive = { 800, 800, 800 }, 3440 .vfront_porch = { 4, 4, 4 }, 3441 .vback_porch = { 16, 16, 16 }, 3442 .vsync_len = { 3, 3, 3 }, 3443 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3444 }; 3445 3446 static const struct panel_desc samsung_ltl101al01 = { 3447 .timings = &samsung_ltl101al01_timing, 3448 .num_timings = 1, 3449 .bpc = 8, 3450 .size = { 3451 .width = 217, 3452 .height = 135, 3453 }, 3454 .delay = { 3455 .prepare = 40, 3456 .enable = 300, 3457 .disable = 200, 3458 .unprepare = 600, 3459 }, 3460 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3461 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3462 }; 3463 3464 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3465 .clock = 54030, 3466 .hdisplay = 1024, 3467 .hsync_start = 1024 + 24, 3468 .hsync_end = 1024 + 24 + 136, 3469 .htotal = 1024 + 24 + 136 + 160, 3470 .vdisplay = 600, 3471 .vsync_start = 600 + 3, 3472 .vsync_end = 600 + 3 + 6, 3473 .vtotal = 600 + 3 + 6 + 61, 3474 }; 3475 3476 static const struct panel_desc samsung_ltn101nt05 = { 3477 .modes = &samsung_ltn101nt05_mode, 3478 .num_modes = 1, 3479 .bpc = 6, 3480 .size = { 3481 .width = 223, 3482 .height = 125, 3483 }, 3484 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3485 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3486 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3487 }; 3488 3489 static const struct display_timing satoz_sat050at40h12r2_timing = { 3490 .pixelclock = {33300000, 33300000, 50000000}, 3491 .hactive = {800, 800, 800}, 3492 .hfront_porch = {16, 210, 354}, 3493 .hback_porch = {46, 46, 46}, 3494 .hsync_len = {1, 1, 40}, 3495 .vactive = {480, 480, 480}, 3496 .vfront_porch = {7, 22, 147}, 3497 .vback_porch = {23, 23, 23}, 3498 .vsync_len = {1, 1, 20}, 3499 }; 3500 3501 static const struct panel_desc satoz_sat050at40h12r2 = { 3502 .timings = &satoz_sat050at40h12r2_timing, 3503 .num_timings = 1, 3504 .bpc = 8, 3505 .size = { 3506 .width = 108, 3507 .height = 65, 3508 }, 3509 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3510 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3511 }; 3512 3513 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3514 .clock = 33260, 3515 .hdisplay = 800, 3516 .hsync_start = 800 + 64, 3517 .hsync_end = 800 + 64 + 128, 3518 .htotal = 800 + 64 + 128 + 64, 3519 .vdisplay = 480, 3520 .vsync_start = 480 + 8, 3521 .vsync_end = 480 + 8 + 2, 3522 .vtotal = 480 + 8 + 2 + 35, 3523 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3524 }; 3525 3526 static const struct panel_desc sharp_lq070y3dg3b = { 3527 .modes = &sharp_lq070y3dg3b_mode, 3528 .num_modes = 1, 3529 .bpc = 8, 3530 .size = { 3531 .width = 152, /* 152.4mm */ 3532 .height = 91, /* 91.4mm */ 3533 }, 3534 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3535 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3536 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3537 }; 3538 3539 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3540 .clock = 5500, 3541 .hdisplay = 240, 3542 .hsync_start = 240 + 16, 3543 .hsync_end = 240 + 16 + 7, 3544 .htotal = 240 + 16 + 7 + 5, 3545 .vdisplay = 320, 3546 .vsync_start = 320 + 9, 3547 .vsync_end = 320 + 9 + 1, 3548 .vtotal = 320 + 9 + 1 + 7, 3549 }; 3550 3551 static const struct panel_desc sharp_lq035q7db03 = { 3552 .modes = &sharp_lq035q7db03_mode, 3553 .num_modes = 1, 3554 .bpc = 6, 3555 .size = { 3556 .width = 54, 3557 .height = 72, 3558 }, 3559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3560 }; 3561 3562 static const struct display_timing sharp_lq101k1ly04_timing = { 3563 .pixelclock = { 60000000, 65000000, 80000000 }, 3564 .hactive = { 1280, 1280, 1280 }, 3565 .hfront_porch = { 20, 20, 20 }, 3566 .hback_porch = { 20, 20, 20 }, 3567 .hsync_len = { 10, 10, 10 }, 3568 .vactive = { 800, 800, 800 }, 3569 .vfront_porch = { 4, 4, 4 }, 3570 .vback_porch = { 4, 4, 4 }, 3571 .vsync_len = { 4, 4, 4 }, 3572 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3573 }; 3574 3575 static const struct panel_desc sharp_lq101k1ly04 = { 3576 .timings = &sharp_lq101k1ly04_timing, 3577 .num_timings = 1, 3578 .bpc = 8, 3579 .size = { 3580 .width = 217, 3581 .height = 136, 3582 }, 3583 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3584 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3585 }; 3586 3587 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3588 { /* 50 Hz */ 3589 .clock = 3000, 3590 .hdisplay = 240, 3591 .hsync_start = 240 + 58, 3592 .hsync_end = 240 + 58 + 1, 3593 .htotal = 240 + 58 + 1 + 1, 3594 .vdisplay = 160, 3595 .vsync_start = 160 + 24, 3596 .vsync_end = 160 + 24 + 10, 3597 .vtotal = 160 + 24 + 10 + 6, 3598 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3599 }, 3600 { /* 60 Hz */ 3601 .clock = 3000, 3602 .hdisplay = 240, 3603 .hsync_start = 240 + 8, 3604 .hsync_end = 240 + 8 + 1, 3605 .htotal = 240 + 8 + 1 + 1, 3606 .vdisplay = 160, 3607 .vsync_start = 160 + 24, 3608 .vsync_end = 160 + 24 + 10, 3609 .vtotal = 160 + 24 + 10 + 6, 3610 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3611 }, 3612 }; 3613 3614 static const struct panel_desc sharp_ls020b1dd01d = { 3615 .modes = sharp_ls020b1dd01d_modes, 3616 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3617 .bpc = 6, 3618 .size = { 3619 .width = 42, 3620 .height = 28, 3621 }, 3622 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3623 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3624 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3625 | DRM_BUS_FLAG_SHARP_SIGNALS, 3626 }; 3627 3628 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3629 .clock = 33300, 3630 .hdisplay = 800, 3631 .hsync_start = 800 + 1, 3632 .hsync_end = 800 + 1 + 64, 3633 .htotal = 800 + 1 + 64 + 64, 3634 .vdisplay = 480, 3635 .vsync_start = 480 + 1, 3636 .vsync_end = 480 + 1 + 23, 3637 .vtotal = 480 + 1 + 23 + 22, 3638 }; 3639 3640 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3641 .modes = &shelly_sca07010_bfn_lnn_mode, 3642 .num_modes = 1, 3643 .size = { 3644 .width = 152, 3645 .height = 91, 3646 }, 3647 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3648 }; 3649 3650 static const struct drm_display_mode starry_kr070pe2t_mode = { 3651 .clock = 33000, 3652 .hdisplay = 800, 3653 .hsync_start = 800 + 209, 3654 .hsync_end = 800 + 209 + 1, 3655 .htotal = 800 + 209 + 1 + 45, 3656 .vdisplay = 480, 3657 .vsync_start = 480 + 22, 3658 .vsync_end = 480 + 22 + 1, 3659 .vtotal = 480 + 22 + 1 + 22, 3660 }; 3661 3662 static const struct panel_desc starry_kr070pe2t = { 3663 .modes = &starry_kr070pe2t_mode, 3664 .num_modes = 1, 3665 .bpc = 8, 3666 .size = { 3667 .width = 152, 3668 .height = 86, 3669 }, 3670 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3672 .connector_type = DRM_MODE_CONNECTOR_DPI, 3673 }; 3674 3675 static const struct display_timing startek_kd070wvfpa_mode = { 3676 .pixelclock = { 25200000, 27200000, 30500000 }, 3677 .hactive = { 800, 800, 800 }, 3678 .hfront_porch = { 19, 44, 115 }, 3679 .hback_porch = { 5, 16, 101 }, 3680 .hsync_len = { 1, 2, 100 }, 3681 .vactive = { 480, 480, 480 }, 3682 .vfront_porch = { 5, 43, 67 }, 3683 .vback_porch = { 5, 5, 67 }, 3684 .vsync_len = { 1, 2, 66 }, 3685 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3686 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3687 DISPLAY_FLAGS_SYNC_POSEDGE, 3688 }; 3689 3690 static const struct panel_desc startek_kd070wvfpa = { 3691 .timings = &startek_kd070wvfpa_mode, 3692 .num_timings = 1, 3693 .bpc = 8, 3694 .size = { 3695 .width = 152, 3696 .height = 91, 3697 }, 3698 .delay = { 3699 .prepare = 20, 3700 .enable = 200, 3701 .disable = 200, 3702 }, 3703 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3704 .connector_type = DRM_MODE_CONNECTOR_DPI, 3705 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3706 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3707 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3708 }; 3709 3710 static const struct display_timing tsd_tst043015cmhx_timing = { 3711 .pixelclock = { 5000000, 9000000, 12000000 }, 3712 .hactive = { 480, 480, 480 }, 3713 .hfront_porch = { 4, 5, 65 }, 3714 .hback_porch = { 36, 40, 255 }, 3715 .hsync_len = { 1, 1, 1 }, 3716 .vactive = { 272, 272, 272 }, 3717 .vfront_porch = { 2, 8, 97 }, 3718 .vback_porch = { 3, 8, 31 }, 3719 .vsync_len = { 1, 1, 1 }, 3720 3721 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3722 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3723 }; 3724 3725 static const struct panel_desc tsd_tst043015cmhx = { 3726 .timings = &tsd_tst043015cmhx_timing, 3727 .num_timings = 1, 3728 .bpc = 8, 3729 .size = { 3730 .width = 105, 3731 .height = 67, 3732 }, 3733 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3734 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3735 }; 3736 3737 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3738 .clock = 30000, 3739 .hdisplay = 800, 3740 .hsync_start = 800 + 39, 3741 .hsync_end = 800 + 39 + 47, 3742 .htotal = 800 + 39 + 47 + 39, 3743 .vdisplay = 480, 3744 .vsync_start = 480 + 13, 3745 .vsync_end = 480 + 13 + 2, 3746 .vtotal = 480 + 13 + 2 + 29, 3747 }; 3748 3749 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3750 .modes = &tfc_s9700rtwv43tr_01b_mode, 3751 .num_modes = 1, 3752 .bpc = 8, 3753 .size = { 3754 .width = 155, 3755 .height = 90, 3756 }, 3757 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3758 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3759 }; 3760 3761 static const struct display_timing tianma_tm070jdhg30_timing = { 3762 .pixelclock = { 62600000, 68200000, 78100000 }, 3763 .hactive = { 1280, 1280, 1280 }, 3764 .hfront_porch = { 15, 64, 159 }, 3765 .hback_porch = { 5, 5, 5 }, 3766 .hsync_len = { 1, 1, 256 }, 3767 .vactive = { 800, 800, 800 }, 3768 .vfront_porch = { 3, 40, 99 }, 3769 .vback_porch = { 2, 2, 2 }, 3770 .vsync_len = { 1, 1, 128 }, 3771 .flags = DISPLAY_FLAGS_DE_HIGH, 3772 }; 3773 3774 static const struct panel_desc tianma_tm070jdhg30 = { 3775 .timings = &tianma_tm070jdhg30_timing, 3776 .num_timings = 1, 3777 .bpc = 8, 3778 .size = { 3779 .width = 151, 3780 .height = 95, 3781 }, 3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3783 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3784 }; 3785 3786 static const struct panel_desc tianma_tm070jvhg33 = { 3787 .timings = &tianma_tm070jdhg30_timing, 3788 .num_timings = 1, 3789 .bpc = 8, 3790 .size = { 3791 .width = 150, 3792 .height = 94, 3793 }, 3794 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3795 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3796 }; 3797 3798 static const struct display_timing tianma_tm070rvhg71_timing = { 3799 .pixelclock = { 27700000, 29200000, 39600000 }, 3800 .hactive = { 800, 800, 800 }, 3801 .hfront_porch = { 12, 40, 212 }, 3802 .hback_porch = { 88, 88, 88 }, 3803 .hsync_len = { 1, 1, 40 }, 3804 .vactive = { 480, 480, 480 }, 3805 .vfront_porch = { 1, 13, 88 }, 3806 .vback_porch = { 32, 32, 32 }, 3807 .vsync_len = { 1, 1, 3 }, 3808 .flags = DISPLAY_FLAGS_DE_HIGH, 3809 }; 3810 3811 static const struct panel_desc tianma_tm070rvhg71 = { 3812 .timings = &tianma_tm070rvhg71_timing, 3813 .num_timings = 1, 3814 .bpc = 8, 3815 .size = { 3816 .width = 154, 3817 .height = 86, 3818 }, 3819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3821 }; 3822 3823 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3824 { 3825 .clock = 10000, 3826 .hdisplay = 320, 3827 .hsync_start = 320 + 50, 3828 .hsync_end = 320 + 50 + 6, 3829 .htotal = 320 + 50 + 6 + 38, 3830 .vdisplay = 240, 3831 .vsync_start = 240 + 3, 3832 .vsync_end = 240 + 3 + 1, 3833 .vtotal = 240 + 3 + 1 + 17, 3834 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3835 }, 3836 }; 3837 3838 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3839 .modes = ti_nspire_cx_lcd_mode, 3840 .num_modes = 1, 3841 .bpc = 8, 3842 .size = { 3843 .width = 65, 3844 .height = 49, 3845 }, 3846 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3847 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3848 }; 3849 3850 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3851 { 3852 .clock = 10000, 3853 .hdisplay = 320, 3854 .hsync_start = 320 + 6, 3855 .hsync_end = 320 + 6 + 6, 3856 .htotal = 320 + 6 + 6 + 6, 3857 .vdisplay = 240, 3858 .vsync_start = 240 + 0, 3859 .vsync_end = 240 + 0 + 1, 3860 .vtotal = 240 + 0 + 1 + 0, 3861 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3862 }, 3863 }; 3864 3865 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3866 .modes = ti_nspire_classic_lcd_mode, 3867 .num_modes = 1, 3868 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3869 .bpc = 8, 3870 .size = { 3871 .width = 71, 3872 .height = 53, 3873 }, 3874 /* This is the grayscale bus format */ 3875 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3876 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3877 }; 3878 3879 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3880 .clock = 79500, 3881 .hdisplay = 1280, 3882 .hsync_start = 1280 + 192, 3883 .hsync_end = 1280 + 192 + 128, 3884 .htotal = 1280 + 192 + 128 + 64, 3885 .vdisplay = 768, 3886 .vsync_start = 768 + 20, 3887 .vsync_end = 768 + 20 + 7, 3888 .vtotal = 768 + 20 + 7 + 3, 3889 }; 3890 3891 static const struct panel_desc toshiba_lt089ac29000 = { 3892 .modes = &toshiba_lt089ac29000_mode, 3893 .num_modes = 1, 3894 .size = { 3895 .width = 194, 3896 .height = 116, 3897 }, 3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3899 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3900 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3901 }; 3902 3903 static const struct drm_display_mode tpk_f07a_0102_mode = { 3904 .clock = 33260, 3905 .hdisplay = 800, 3906 .hsync_start = 800 + 40, 3907 .hsync_end = 800 + 40 + 128, 3908 .htotal = 800 + 40 + 128 + 88, 3909 .vdisplay = 480, 3910 .vsync_start = 480 + 10, 3911 .vsync_end = 480 + 10 + 2, 3912 .vtotal = 480 + 10 + 2 + 33, 3913 }; 3914 3915 static const struct panel_desc tpk_f07a_0102 = { 3916 .modes = &tpk_f07a_0102_mode, 3917 .num_modes = 1, 3918 .size = { 3919 .width = 152, 3920 .height = 91, 3921 }, 3922 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3923 }; 3924 3925 static const struct drm_display_mode tpk_f10a_0102_mode = { 3926 .clock = 45000, 3927 .hdisplay = 1024, 3928 .hsync_start = 1024 + 176, 3929 .hsync_end = 1024 + 176 + 5, 3930 .htotal = 1024 + 176 + 5 + 88, 3931 .vdisplay = 600, 3932 .vsync_start = 600 + 20, 3933 .vsync_end = 600 + 20 + 5, 3934 .vtotal = 600 + 20 + 5 + 25, 3935 }; 3936 3937 static const struct panel_desc tpk_f10a_0102 = { 3938 .modes = &tpk_f10a_0102_mode, 3939 .num_modes = 1, 3940 .size = { 3941 .width = 223, 3942 .height = 125, 3943 }, 3944 }; 3945 3946 static const struct display_timing urt_umsh_8596md_timing = { 3947 .pixelclock = { 33260000, 33260000, 33260000 }, 3948 .hactive = { 800, 800, 800 }, 3949 .hfront_porch = { 41, 41, 41 }, 3950 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3951 .hsync_len = { 71, 128, 128 }, 3952 .vactive = { 480, 480, 480 }, 3953 .vfront_porch = { 10, 10, 10 }, 3954 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3955 .vsync_len = { 2, 2, 2 }, 3956 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3957 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3958 }; 3959 3960 static const struct panel_desc urt_umsh_8596md_lvds = { 3961 .timings = &urt_umsh_8596md_timing, 3962 .num_timings = 1, 3963 .bpc = 6, 3964 .size = { 3965 .width = 152, 3966 .height = 91, 3967 }, 3968 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3970 }; 3971 3972 static const struct panel_desc urt_umsh_8596md_parallel = { 3973 .timings = &urt_umsh_8596md_timing, 3974 .num_timings = 1, 3975 .bpc = 6, 3976 .size = { 3977 .width = 152, 3978 .height = 91, 3979 }, 3980 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3981 }; 3982 3983 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3984 .clock = 60000, 3985 .hdisplay = 1024, 3986 .hsync_start = 1024 + 160, 3987 .hsync_end = 1024 + 160 + 100, 3988 .htotal = 1024 + 160 + 100 + 60, 3989 .vdisplay = 600, 3990 .vsync_start = 600 + 12, 3991 .vsync_end = 600 + 12 + 10, 3992 .vtotal = 600 + 12 + 10 + 13, 3993 }; 3994 3995 static const struct panel_desc vivax_tpc9150_panel = { 3996 .modes = &vivax_tpc9150_panel_mode, 3997 .num_modes = 1, 3998 .bpc = 6, 3999 .size = { 4000 .width = 200, 4001 .height = 115, 4002 }, 4003 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4004 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4006 }; 4007 4008 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4009 .clock = 33333, 4010 .hdisplay = 800, 4011 .hsync_start = 800 + 210, 4012 .hsync_end = 800 + 210 + 20, 4013 .htotal = 800 + 210 + 20 + 46, 4014 .vdisplay = 480, 4015 .vsync_start = 480 + 22, 4016 .vsync_end = 480 + 22 + 10, 4017 .vtotal = 480 + 22 + 10 + 23, 4018 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4019 }; 4020 4021 static const struct panel_desc vl050_8048nt_c01 = { 4022 .modes = &vl050_8048nt_c01_mode, 4023 .num_modes = 1, 4024 .bpc = 8, 4025 .size = { 4026 .width = 120, 4027 .height = 76, 4028 }, 4029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4030 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4031 }; 4032 4033 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4034 .clock = 6410, 4035 .hdisplay = 320, 4036 .hsync_start = 320 + 20, 4037 .hsync_end = 320 + 20 + 30, 4038 .htotal = 320 + 20 + 30 + 38, 4039 .vdisplay = 240, 4040 .vsync_start = 240 + 4, 4041 .vsync_end = 240 + 4 + 3, 4042 .vtotal = 240 + 4 + 3 + 15, 4043 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4044 }; 4045 4046 static const struct panel_desc winstar_wf35ltiacd = { 4047 .modes = &winstar_wf35ltiacd_mode, 4048 .num_modes = 1, 4049 .bpc = 8, 4050 .size = { 4051 .width = 70, 4052 .height = 53, 4053 }, 4054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4055 }; 4056 4057 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4058 .clock = 51200, 4059 .hdisplay = 1024, 4060 .hsync_start = 1024 + 100, 4061 .hsync_end = 1024 + 100 + 100, 4062 .htotal = 1024 + 100 + 100 + 120, 4063 .vdisplay = 600, 4064 .vsync_start = 600 + 10, 4065 .vsync_end = 600 + 10 + 10, 4066 .vtotal = 600 + 10 + 10 + 15, 4067 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4068 }; 4069 4070 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4071 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4072 .num_modes = 1, 4073 .bpc = 8, 4074 .size = { 4075 .width = 154, 4076 .height = 90, 4077 }, 4078 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4081 }; 4082 4083 static const struct drm_display_mode arm_rtsm_mode[] = { 4084 { 4085 .clock = 65000, 4086 .hdisplay = 1024, 4087 .hsync_start = 1024 + 24, 4088 .hsync_end = 1024 + 24 + 136, 4089 .htotal = 1024 + 24 + 136 + 160, 4090 .vdisplay = 768, 4091 .vsync_start = 768 + 3, 4092 .vsync_end = 768 + 3 + 6, 4093 .vtotal = 768 + 3 + 6 + 29, 4094 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4095 }, 4096 }; 4097 4098 static const struct panel_desc arm_rtsm = { 4099 .modes = arm_rtsm_mode, 4100 .num_modes = 1, 4101 .bpc = 8, 4102 .size = { 4103 .width = 400, 4104 .height = 300, 4105 }, 4106 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4107 }; 4108 4109 static const struct of_device_id platform_of_match[] = { 4110 { 4111 .compatible = "ampire,am-1280800n3tzqw-t00h", 4112 .data = &ire_am_1280800n3tzqw_t00h, 4113 }, { 4114 .compatible = "ampire,am-480272h3tmqw-t01h", 4115 .data = &ire_am_480272h3tmqw_t01h, 4116 }, { 4117 .compatible = "ampire,am-800480l1tmqw-t00h", 4118 .data = &ire_am_800480l1tmqw_t00h, 4119 }, { 4120 .compatible = "ampire,am800480r3tmqwa1h", 4121 .data = &ire_am800480r3tmqwa1h, 4122 }, { 4123 .compatible = "ampire,am800600p5tmqw-tb8h", 4124 .data = &ire_am800600p5tmqwtb8h, 4125 }, { 4126 .compatible = "arm,rtsm-display", 4127 .data = &arm_rtsm, 4128 }, { 4129 .compatible = "armadeus,st0700-adapt", 4130 .data = &armadeus_st0700_adapt, 4131 }, { 4132 .compatible = "auo,b101aw03", 4133 .data = &auo_b101aw03, 4134 }, { 4135 .compatible = "auo,b101xtn01", 4136 .data = &auo_b101xtn01, 4137 }, { 4138 .compatible = "auo,b116xw03", 4139 .data = &auo_b116xw03, 4140 }, { 4141 .compatible = "auo,g070vvn01", 4142 .data = &auo_g070vvn01, 4143 }, { 4144 .compatible = "auo,g101evn010", 4145 .data = &auo_g101evn010, 4146 }, { 4147 .compatible = "auo,g104sn02", 4148 .data = &auo_g104sn02, 4149 }, { 4150 .compatible = "auo,g121ean01", 4151 .data = &auo_g121ean01, 4152 }, { 4153 .compatible = "auo,g133han01", 4154 .data = &auo_g133han01, 4155 }, { 4156 .compatible = "auo,g156xtn01", 4157 .data = &auo_g156xtn01, 4158 }, { 4159 .compatible = "auo,g185han01", 4160 .data = &auo_g185han01, 4161 }, { 4162 .compatible = "auo,g190ean01", 4163 .data = &auo_g190ean01, 4164 }, { 4165 .compatible = "auo,p320hvn03", 4166 .data = &auo_p320hvn03, 4167 }, { 4168 .compatible = "auo,t215hvn01", 4169 .data = &auo_t215hvn01, 4170 }, { 4171 .compatible = "avic,tm070ddh03", 4172 .data = &avic_tm070ddh03, 4173 }, { 4174 .compatible = "bananapi,s070wv20-ct16", 4175 .data = &bananapi_s070wv20_ct16, 4176 }, { 4177 .compatible = "boe,ev121wxm-n10-1850", 4178 .data = &boe_ev121wxm_n10_1850, 4179 }, { 4180 .compatible = "boe,hv070wsa-100", 4181 .data = &boe_hv070wsa 4182 }, { 4183 .compatible = "cdtech,s043wq26h-ct7", 4184 .data = &cdtech_s043wq26h_ct7, 4185 }, { 4186 .compatible = "cdtech,s070pws19hp-fc21", 4187 .data = &cdtech_s070pws19hp_fc21, 4188 }, { 4189 .compatible = "cdtech,s070swv29hg-dc44", 4190 .data = &cdtech_s070swv29hg_dc44, 4191 }, { 4192 .compatible = "cdtech,s070wv95-ct16", 4193 .data = &cdtech_s070wv95_ct16, 4194 }, { 4195 .compatible = "chefree,ch101olhlwh-002", 4196 .data = &chefree_ch101olhlwh_002, 4197 }, { 4198 .compatible = "chunghwa,claa070wp03xg", 4199 .data = &chunghwa_claa070wp03xg, 4200 }, { 4201 .compatible = "chunghwa,claa101wa01a", 4202 .data = &chunghwa_claa101wa01a 4203 }, { 4204 .compatible = "chunghwa,claa101wb01", 4205 .data = &chunghwa_claa101wb01 4206 }, { 4207 .compatible = "dataimage,fg040346dsswbg04", 4208 .data = &dataimage_fg040346dsswbg04, 4209 }, { 4210 .compatible = "dataimage,fg1001l0dsswmg01", 4211 .data = &dataimage_fg1001l0dsswmg01, 4212 }, { 4213 .compatible = "dataimage,scf0700c48ggu18", 4214 .data = &dataimage_scf0700c48ggu18, 4215 }, { 4216 .compatible = "dlc,dlc0700yzg-1", 4217 .data = &dlc_dlc0700yzg_1, 4218 }, { 4219 .compatible = "dlc,dlc1010gig", 4220 .data = &dlc_dlc1010gig, 4221 }, { 4222 .compatible = "edt,et035012dm6", 4223 .data = &edt_et035012dm6, 4224 }, { 4225 .compatible = "edt,etm0350g0dh6", 4226 .data = &edt_etm0350g0dh6, 4227 }, { 4228 .compatible = "edt,etm043080dh6gp", 4229 .data = &edt_etm043080dh6gp, 4230 }, { 4231 .compatible = "edt,etm0430g0dh6", 4232 .data = &edt_etm0430g0dh6, 4233 }, { 4234 .compatible = "edt,et057090dhu", 4235 .data = &edt_et057090dhu, 4236 }, { 4237 .compatible = "edt,et070080dh6", 4238 .data = &edt_etm0700g0dh6, 4239 }, { 4240 .compatible = "edt,etm0700g0dh6", 4241 .data = &edt_etm0700g0dh6, 4242 }, { 4243 .compatible = "edt,etm0700g0bdh6", 4244 .data = &edt_etm0700g0bdh6, 4245 }, { 4246 .compatible = "edt,etm0700g0edh6", 4247 .data = &edt_etm0700g0bdh6, 4248 }, { 4249 .compatible = "edt,etml0700y5dha", 4250 .data = &edt_etml0700y5dha, 4251 }, { 4252 .compatible = "edt,etmv570g2dhu", 4253 .data = &edt_etmv570g2dhu, 4254 }, { 4255 .compatible = "eink,vb3300-kca", 4256 .data = &eink_vb3300_kca, 4257 }, { 4258 .compatible = "evervision,vgg804821", 4259 .data = &evervision_vgg804821, 4260 }, { 4261 .compatible = "foxlink,fl500wvr00-a0t", 4262 .data = &foxlink_fl500wvr00_a0t, 4263 }, { 4264 .compatible = "frida,frd350h54004", 4265 .data = &frida_frd350h54004, 4266 }, { 4267 .compatible = "friendlyarm,hd702e", 4268 .data = &friendlyarm_hd702e, 4269 }, { 4270 .compatible = "giantplus,gpg482739qs5", 4271 .data = &giantplus_gpg482739qs5 4272 }, { 4273 .compatible = "giantplus,gpm940b0", 4274 .data = &giantplus_gpm940b0, 4275 }, { 4276 .compatible = "hannstar,hsd070pww1", 4277 .data = &hannstar_hsd070pww1, 4278 }, { 4279 .compatible = "hannstar,hsd100pxn1", 4280 .data = &hannstar_hsd100pxn1, 4281 }, { 4282 .compatible = "hannstar,hsd101pww2", 4283 .data = &hannstar_hsd101pww2, 4284 }, { 4285 .compatible = "hit,tx23d38vm0caa", 4286 .data = &hitachi_tx23d38vm0caa 4287 }, { 4288 .compatible = "innolux,at043tn24", 4289 .data = &innolux_at043tn24, 4290 }, { 4291 .compatible = "innolux,at070tn92", 4292 .data = &innolux_at070tn92, 4293 }, { 4294 .compatible = "innolux,g070ace-l01", 4295 .data = &innolux_g070ace_l01, 4296 }, { 4297 .compatible = "innolux,g070y2-l01", 4298 .data = &innolux_g070y2_l01, 4299 }, { 4300 .compatible = "innolux,g070y2-t02", 4301 .data = &innolux_g070y2_t02, 4302 }, { 4303 .compatible = "innolux,g101ice-l01", 4304 .data = &innolux_g101ice_l01 4305 }, { 4306 .compatible = "innolux,g121i1-l01", 4307 .data = &innolux_g121i1_l01 4308 }, { 4309 .compatible = "innolux,g121x1-l03", 4310 .data = &innolux_g121x1_l03, 4311 }, { 4312 .compatible = "innolux,g156hce-l01", 4313 .data = &innolux_g156hce_l01, 4314 }, { 4315 .compatible = "innolux,n156bge-l21", 4316 .data = &innolux_n156bge_l21, 4317 }, { 4318 .compatible = "innolux,zj070na-01p", 4319 .data = &innolux_zj070na_01p, 4320 }, { 4321 .compatible = "koe,tx14d24vm1bpa", 4322 .data = &koe_tx14d24vm1bpa, 4323 }, { 4324 .compatible = "koe,tx26d202vm0bwa", 4325 .data = &koe_tx26d202vm0bwa, 4326 }, { 4327 .compatible = "koe,tx31d200vm0baa", 4328 .data = &koe_tx31d200vm0baa, 4329 }, { 4330 .compatible = "kyo,tcg121xglp", 4331 .data = &kyo_tcg121xglp, 4332 }, { 4333 .compatible = "lemaker,bl035-rgb-002", 4334 .data = &lemaker_bl035_rgb_002, 4335 }, { 4336 .compatible = "lg,lb070wv8", 4337 .data = &lg_lb070wv8, 4338 }, { 4339 .compatible = "logicpd,type28", 4340 .data = &logicpd_type_28, 4341 }, { 4342 .compatible = "logictechno,lt161010-2nhc", 4343 .data = &logictechno_lt161010_2nh, 4344 }, { 4345 .compatible = "logictechno,lt161010-2nhr", 4346 .data = &logictechno_lt161010_2nh, 4347 }, { 4348 .compatible = "logictechno,lt170410-2whc", 4349 .data = &logictechno_lt170410_2whc, 4350 }, { 4351 .compatible = "logictechno,lttd800480070-l2rt", 4352 .data = &logictechno_lttd800480070_l2rt, 4353 }, { 4354 .compatible = "logictechno,lttd800480070-l6wh-rt", 4355 .data = &logictechno_lttd800480070_l6wh_rt, 4356 }, { 4357 .compatible = "mitsubishi,aa070mc01-ca1", 4358 .data = &mitsubishi_aa070mc01, 4359 }, { 4360 .compatible = "multi-inno,mi0700s4t-6", 4361 .data = &multi_inno_mi0700s4t_6, 4362 }, { 4363 .compatible = "multi-inno,mi0800ft-9", 4364 .data = &multi_inno_mi0800ft_9, 4365 }, { 4366 .compatible = "multi-inno,mi1010ait-1cp", 4367 .data = &multi_inno_mi1010ait_1cp, 4368 }, { 4369 .compatible = "nec,nl12880bc20-05", 4370 .data = &nec_nl12880bc20_05, 4371 }, { 4372 .compatible = "nec,nl4827hc19-05b", 4373 .data = &nec_nl4827hc19_05b, 4374 }, { 4375 .compatible = "netron-dy,e231732", 4376 .data = &netron_dy_e231732, 4377 }, { 4378 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4379 .data = &newhaven_nhd_43_480272ef_atxl, 4380 }, { 4381 .compatible = "nlt,nl192108ac18-02d", 4382 .data = &nlt_nl192108ac18_02d, 4383 }, { 4384 .compatible = "nvd,9128", 4385 .data = &nvd_9128, 4386 }, { 4387 .compatible = "okaya,rs800480t-7x0gp", 4388 .data = &okaya_rs800480t_7x0gp, 4389 }, { 4390 .compatible = "olimex,lcd-olinuxino-43-ts", 4391 .data = &olimex_lcd_olinuxino_43ts, 4392 }, { 4393 .compatible = "ontat,yx700wv03", 4394 .data = &ontat_yx700wv03, 4395 }, { 4396 .compatible = "ortustech,com37h3m05dtc", 4397 .data = &ortustech_com37h3m, 4398 }, { 4399 .compatible = "ortustech,com37h3m99dtc", 4400 .data = &ortustech_com37h3m, 4401 }, { 4402 .compatible = "ortustech,com43h4m85ulc", 4403 .data = &ortustech_com43h4m85ulc, 4404 }, { 4405 .compatible = "osddisplays,osd070t1718-19ts", 4406 .data = &osddisplays_osd070t1718_19ts, 4407 }, { 4408 .compatible = "pda,91-00156-a0", 4409 .data = &pda_91_00156_a0, 4410 }, { 4411 .compatible = "powertip,ph800480t013-idf02", 4412 .data = &powertip_ph800480t013_idf02, 4413 }, { 4414 .compatible = "qiaodian,qd43003c0-40", 4415 .data = &qd43003c0_40, 4416 }, { 4417 .compatible = "qishenglong,gopher2b-lcd", 4418 .data = &qishenglong_gopher2b_lcd, 4419 }, { 4420 .compatible = "rocktech,rk043fn48h", 4421 .data = &rocktech_rk043fn48h, 4422 }, { 4423 .compatible = "rocktech,rk070er9427", 4424 .data = &rocktech_rk070er9427, 4425 }, { 4426 .compatible = "rocktech,rk101ii01d-ct", 4427 .data = &rocktech_rk101ii01d_ct, 4428 }, { 4429 .compatible = "samsung,ltl101al01", 4430 .data = &samsung_ltl101al01, 4431 }, { 4432 .compatible = "samsung,ltn101nt05", 4433 .data = &samsung_ltn101nt05, 4434 }, { 4435 .compatible = "satoz,sat050at40h12r2", 4436 .data = &satoz_sat050at40h12r2, 4437 }, { 4438 .compatible = "sharp,lq035q7db03", 4439 .data = &sharp_lq035q7db03, 4440 }, { 4441 .compatible = "sharp,lq070y3dg3b", 4442 .data = &sharp_lq070y3dg3b, 4443 }, { 4444 .compatible = "sharp,lq101k1ly04", 4445 .data = &sharp_lq101k1ly04, 4446 }, { 4447 .compatible = "sharp,ls020b1dd01d", 4448 .data = &sharp_ls020b1dd01d, 4449 }, { 4450 .compatible = "shelly,sca07010-bfn-lnn", 4451 .data = &shelly_sca07010_bfn_lnn, 4452 }, { 4453 .compatible = "starry,kr070pe2t", 4454 .data = &starry_kr070pe2t, 4455 }, { 4456 .compatible = "startek,kd070wvfpa", 4457 .data = &startek_kd070wvfpa, 4458 }, { 4459 .compatible = "team-source-display,tst043015cmhx", 4460 .data = &tsd_tst043015cmhx, 4461 }, { 4462 .compatible = "tfc,s9700rtwv43tr-01b", 4463 .data = &tfc_s9700rtwv43tr_01b, 4464 }, { 4465 .compatible = "tianma,tm070jdhg30", 4466 .data = &tianma_tm070jdhg30, 4467 }, { 4468 .compatible = "tianma,tm070jvhg33", 4469 .data = &tianma_tm070jvhg33, 4470 }, { 4471 .compatible = "tianma,tm070rvhg71", 4472 .data = &tianma_tm070rvhg71, 4473 }, { 4474 .compatible = "ti,nspire-cx-lcd-panel", 4475 .data = &ti_nspire_cx_lcd_panel, 4476 }, { 4477 .compatible = "ti,nspire-classic-lcd-panel", 4478 .data = &ti_nspire_classic_lcd_panel, 4479 }, { 4480 .compatible = "toshiba,lt089ac29000", 4481 .data = &toshiba_lt089ac29000, 4482 }, { 4483 .compatible = "tpk,f07a-0102", 4484 .data = &tpk_f07a_0102, 4485 }, { 4486 .compatible = "tpk,f10a-0102", 4487 .data = &tpk_f10a_0102, 4488 }, { 4489 .compatible = "urt,umsh-8596md-t", 4490 .data = &urt_umsh_8596md_parallel, 4491 }, { 4492 .compatible = "urt,umsh-8596md-1t", 4493 .data = &urt_umsh_8596md_parallel, 4494 }, { 4495 .compatible = "urt,umsh-8596md-7t", 4496 .data = &urt_umsh_8596md_parallel, 4497 }, { 4498 .compatible = "urt,umsh-8596md-11t", 4499 .data = &urt_umsh_8596md_lvds, 4500 }, { 4501 .compatible = "urt,umsh-8596md-19t", 4502 .data = &urt_umsh_8596md_lvds, 4503 }, { 4504 .compatible = "urt,umsh-8596md-20t", 4505 .data = &urt_umsh_8596md_parallel, 4506 }, { 4507 .compatible = "vivax,tpc9150-panel", 4508 .data = &vivax_tpc9150_panel, 4509 }, { 4510 .compatible = "vxt,vl050-8048nt-c01", 4511 .data = &vl050_8048nt_c01, 4512 }, { 4513 .compatible = "winstar,wf35ltiacd", 4514 .data = &winstar_wf35ltiacd, 4515 }, { 4516 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4517 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4518 }, { 4519 /* Must be the last entry */ 4520 .compatible = "panel-dpi", 4521 .data = &panel_dpi, 4522 }, { 4523 /* sentinel */ 4524 } 4525 }; 4526 MODULE_DEVICE_TABLE(of, platform_of_match); 4527 4528 static int panel_simple_platform_probe(struct platform_device *pdev) 4529 { 4530 const struct panel_desc *desc; 4531 4532 desc = of_device_get_match_data(&pdev->dev); 4533 if (!desc) 4534 return -ENODEV; 4535 4536 return panel_simple_probe(&pdev->dev, desc); 4537 } 4538 4539 static void panel_simple_platform_remove(struct platform_device *pdev) 4540 { 4541 panel_simple_remove(&pdev->dev); 4542 } 4543 4544 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4545 { 4546 panel_simple_shutdown(&pdev->dev); 4547 } 4548 4549 static const struct dev_pm_ops panel_simple_pm_ops = { 4550 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4551 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4552 pm_runtime_force_resume) 4553 }; 4554 4555 static struct platform_driver panel_simple_platform_driver = { 4556 .driver = { 4557 .name = "panel-simple", 4558 .of_match_table = platform_of_match, 4559 .pm = &panel_simple_pm_ops, 4560 }, 4561 .probe = panel_simple_platform_probe, 4562 .remove_new = panel_simple_platform_remove, 4563 .shutdown = panel_simple_platform_shutdown, 4564 }; 4565 4566 struct panel_desc_dsi { 4567 struct panel_desc desc; 4568 4569 unsigned long flags; 4570 enum mipi_dsi_pixel_format format; 4571 unsigned int lanes; 4572 }; 4573 4574 static const struct drm_display_mode auo_b080uan01_mode = { 4575 .clock = 154500, 4576 .hdisplay = 1200, 4577 .hsync_start = 1200 + 62, 4578 .hsync_end = 1200 + 62 + 4, 4579 .htotal = 1200 + 62 + 4 + 62, 4580 .vdisplay = 1920, 4581 .vsync_start = 1920 + 9, 4582 .vsync_end = 1920 + 9 + 2, 4583 .vtotal = 1920 + 9 + 2 + 8, 4584 }; 4585 4586 static const struct panel_desc_dsi auo_b080uan01 = { 4587 .desc = { 4588 .modes = &auo_b080uan01_mode, 4589 .num_modes = 1, 4590 .bpc = 8, 4591 .size = { 4592 .width = 108, 4593 .height = 272, 4594 }, 4595 .connector_type = DRM_MODE_CONNECTOR_DSI, 4596 }, 4597 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4598 .format = MIPI_DSI_FMT_RGB888, 4599 .lanes = 4, 4600 }; 4601 4602 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4603 .clock = 160000, 4604 .hdisplay = 1200, 4605 .hsync_start = 1200 + 120, 4606 .hsync_end = 1200 + 120 + 20, 4607 .htotal = 1200 + 120 + 20 + 21, 4608 .vdisplay = 1920, 4609 .vsync_start = 1920 + 21, 4610 .vsync_end = 1920 + 21 + 3, 4611 .vtotal = 1920 + 21 + 3 + 18, 4612 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4613 }; 4614 4615 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4616 .desc = { 4617 .modes = &boe_tv080wum_nl0_mode, 4618 .num_modes = 1, 4619 .size = { 4620 .width = 107, 4621 .height = 172, 4622 }, 4623 .connector_type = DRM_MODE_CONNECTOR_DSI, 4624 }, 4625 .flags = MIPI_DSI_MODE_VIDEO | 4626 MIPI_DSI_MODE_VIDEO_BURST | 4627 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4628 .format = MIPI_DSI_FMT_RGB888, 4629 .lanes = 4, 4630 }; 4631 4632 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4633 .clock = 71000, 4634 .hdisplay = 800, 4635 .hsync_start = 800 + 32, 4636 .hsync_end = 800 + 32 + 1, 4637 .htotal = 800 + 32 + 1 + 57, 4638 .vdisplay = 1280, 4639 .vsync_start = 1280 + 28, 4640 .vsync_end = 1280 + 28 + 1, 4641 .vtotal = 1280 + 28 + 1 + 14, 4642 }; 4643 4644 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4645 .desc = { 4646 .modes = &lg_ld070wx3_sl01_mode, 4647 .num_modes = 1, 4648 .bpc = 8, 4649 .size = { 4650 .width = 94, 4651 .height = 151, 4652 }, 4653 .connector_type = DRM_MODE_CONNECTOR_DSI, 4654 }, 4655 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4656 .format = MIPI_DSI_FMT_RGB888, 4657 .lanes = 4, 4658 }; 4659 4660 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4661 .clock = 67000, 4662 .hdisplay = 720, 4663 .hsync_start = 720 + 12, 4664 .hsync_end = 720 + 12 + 4, 4665 .htotal = 720 + 12 + 4 + 112, 4666 .vdisplay = 1280, 4667 .vsync_start = 1280 + 8, 4668 .vsync_end = 1280 + 8 + 4, 4669 .vtotal = 1280 + 8 + 4 + 12, 4670 }; 4671 4672 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4673 .desc = { 4674 .modes = &lg_lh500wx1_sd03_mode, 4675 .num_modes = 1, 4676 .bpc = 8, 4677 .size = { 4678 .width = 62, 4679 .height = 110, 4680 }, 4681 .connector_type = DRM_MODE_CONNECTOR_DSI, 4682 }, 4683 .flags = MIPI_DSI_MODE_VIDEO, 4684 .format = MIPI_DSI_FMT_RGB888, 4685 .lanes = 4, 4686 }; 4687 4688 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4689 .clock = 157200, 4690 .hdisplay = 1920, 4691 .hsync_start = 1920 + 154, 4692 .hsync_end = 1920 + 154 + 16, 4693 .htotal = 1920 + 154 + 16 + 32, 4694 .vdisplay = 1200, 4695 .vsync_start = 1200 + 17, 4696 .vsync_end = 1200 + 17 + 2, 4697 .vtotal = 1200 + 17 + 2 + 16, 4698 }; 4699 4700 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4701 .desc = { 4702 .modes = &panasonic_vvx10f004b00_mode, 4703 .num_modes = 1, 4704 .bpc = 8, 4705 .size = { 4706 .width = 217, 4707 .height = 136, 4708 }, 4709 .connector_type = DRM_MODE_CONNECTOR_DSI, 4710 }, 4711 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4712 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4713 .format = MIPI_DSI_FMT_RGB888, 4714 .lanes = 4, 4715 }; 4716 4717 static const struct drm_display_mode lg_acx467akm_7_mode = { 4718 .clock = 150000, 4719 .hdisplay = 1080, 4720 .hsync_start = 1080 + 2, 4721 .hsync_end = 1080 + 2 + 2, 4722 .htotal = 1080 + 2 + 2 + 2, 4723 .vdisplay = 1920, 4724 .vsync_start = 1920 + 2, 4725 .vsync_end = 1920 + 2 + 2, 4726 .vtotal = 1920 + 2 + 2 + 2, 4727 }; 4728 4729 static const struct panel_desc_dsi lg_acx467akm_7 = { 4730 .desc = { 4731 .modes = &lg_acx467akm_7_mode, 4732 .num_modes = 1, 4733 .bpc = 8, 4734 .size = { 4735 .width = 62, 4736 .height = 110, 4737 }, 4738 .connector_type = DRM_MODE_CONNECTOR_DSI, 4739 }, 4740 .flags = 0, 4741 .format = MIPI_DSI_FMT_RGB888, 4742 .lanes = 4, 4743 }; 4744 4745 static const struct drm_display_mode osd101t2045_53ts_mode = { 4746 .clock = 154500, 4747 .hdisplay = 1920, 4748 .hsync_start = 1920 + 112, 4749 .hsync_end = 1920 + 112 + 16, 4750 .htotal = 1920 + 112 + 16 + 32, 4751 .vdisplay = 1200, 4752 .vsync_start = 1200 + 16, 4753 .vsync_end = 1200 + 16 + 2, 4754 .vtotal = 1200 + 16 + 2 + 16, 4755 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4756 }; 4757 4758 static const struct panel_desc_dsi osd101t2045_53ts = { 4759 .desc = { 4760 .modes = &osd101t2045_53ts_mode, 4761 .num_modes = 1, 4762 .bpc = 8, 4763 .size = { 4764 .width = 217, 4765 .height = 136, 4766 }, 4767 .connector_type = DRM_MODE_CONNECTOR_DSI, 4768 }, 4769 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4770 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4771 MIPI_DSI_MODE_NO_EOT_PACKET, 4772 .format = MIPI_DSI_FMT_RGB888, 4773 .lanes = 4, 4774 }; 4775 4776 static const struct of_device_id dsi_of_match[] = { 4777 { 4778 .compatible = "auo,b080uan01", 4779 .data = &auo_b080uan01 4780 }, { 4781 .compatible = "boe,tv080wum-nl0", 4782 .data = &boe_tv080wum_nl0 4783 }, { 4784 .compatible = "lg,ld070wx3-sl01", 4785 .data = &lg_ld070wx3_sl01 4786 }, { 4787 .compatible = "lg,lh500wx1-sd03", 4788 .data = &lg_lh500wx1_sd03 4789 }, { 4790 .compatible = "panasonic,vvx10f004b00", 4791 .data = &panasonic_vvx10f004b00 4792 }, { 4793 .compatible = "lg,acx467akm-7", 4794 .data = &lg_acx467akm_7 4795 }, { 4796 .compatible = "osddisplays,osd101t2045-53ts", 4797 .data = &osd101t2045_53ts 4798 }, { 4799 /* sentinel */ 4800 } 4801 }; 4802 MODULE_DEVICE_TABLE(of, dsi_of_match); 4803 4804 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4805 { 4806 const struct panel_desc_dsi *desc; 4807 int err; 4808 4809 desc = of_device_get_match_data(&dsi->dev); 4810 if (!desc) 4811 return -ENODEV; 4812 4813 err = panel_simple_probe(&dsi->dev, &desc->desc); 4814 if (err < 0) 4815 return err; 4816 4817 dsi->mode_flags = desc->flags; 4818 dsi->format = desc->format; 4819 dsi->lanes = desc->lanes; 4820 4821 err = mipi_dsi_attach(dsi); 4822 if (err) { 4823 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4824 4825 drm_panel_remove(&panel->base); 4826 } 4827 4828 return err; 4829 } 4830 4831 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4832 { 4833 int err; 4834 4835 err = mipi_dsi_detach(dsi); 4836 if (err < 0) 4837 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4838 4839 panel_simple_remove(&dsi->dev); 4840 } 4841 4842 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4843 { 4844 panel_simple_shutdown(&dsi->dev); 4845 } 4846 4847 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4848 .driver = { 4849 .name = "panel-simple-dsi", 4850 .of_match_table = dsi_of_match, 4851 .pm = &panel_simple_pm_ops, 4852 }, 4853 .probe = panel_simple_dsi_probe, 4854 .remove = panel_simple_dsi_remove, 4855 .shutdown = panel_simple_dsi_shutdown, 4856 }; 4857 4858 static int __init panel_simple_init(void) 4859 { 4860 int err; 4861 4862 err = platform_driver_register(&panel_simple_platform_driver); 4863 if (err < 0) 4864 return err; 4865 4866 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4867 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4868 if (err < 0) 4869 goto err_did_platform_register; 4870 } 4871 4872 return 0; 4873 4874 err_did_platform_register: 4875 platform_driver_unregister(&panel_simple_platform_driver); 4876 4877 return err; 4878 } 4879 module_init(panel_simple_init); 4880 4881 static void __exit panel_simple_exit(void) 4882 { 4883 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4884 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4885 4886 platform_driver_unregister(&panel_simple_platform_driver); 4887 } 4888 module_exit(panel_simple_exit); 4889 4890 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4891 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4892 MODULE_LICENSE("GPL and additional rights"); 4893