1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_timings == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 gpiod_set_value_cansleep(p->enable_gpio, 0); 191 192 regulator_disable(p->supply); 193 194 if (p->desc->delay.unprepare) 195 msleep(p->desc->delay.unprepare); 196 197 p->prepared = false; 198 199 return 0; 200 } 201 202 static int panel_simple_prepare(struct drm_panel *panel) 203 { 204 struct panel_simple *p = to_panel_simple(panel); 205 int err; 206 207 if (p->prepared) 208 return 0; 209 210 err = regulator_enable(p->supply); 211 if (err < 0) { 212 dev_err(panel->dev, "failed to enable supply: %d\n", err); 213 return err; 214 } 215 216 gpiod_set_value_cansleep(p->enable_gpio, 1); 217 218 if (p->desc->delay.prepare) 219 msleep(p->desc->delay.prepare); 220 221 p->prepared = true; 222 223 return 0; 224 } 225 226 static int panel_simple_enable(struct drm_panel *panel) 227 { 228 struct panel_simple *p = to_panel_simple(panel); 229 230 if (p->enabled) 231 return 0; 232 233 if (p->desc->delay.enable) 234 msleep(p->desc->delay.enable); 235 236 if (p->backlight) { 237 p->backlight->props.state &= ~BL_CORE_FBBLANK; 238 p->backlight->props.power = FB_BLANK_UNBLANK; 239 backlight_update_status(p->backlight); 240 } 241 242 p->enabled = true; 243 244 return 0; 245 } 246 247 static int panel_simple_get_modes(struct drm_panel *panel) 248 { 249 struct panel_simple *p = to_panel_simple(panel); 250 int num = 0; 251 252 /* probe EDID if a DDC bus is available */ 253 if (p->ddc) { 254 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 255 drm_mode_connector_update_edid_property(panel->connector, edid); 256 if (edid) { 257 num += drm_add_edid_modes(panel->connector, edid); 258 kfree(edid); 259 } 260 } 261 262 /* add hard-coded panel modes */ 263 num += panel_simple_get_fixed_modes(p); 264 265 return num; 266 } 267 268 static int panel_simple_get_timings(struct drm_panel *panel, 269 unsigned int num_timings, 270 struct display_timing *timings) 271 { 272 struct panel_simple *p = to_panel_simple(panel); 273 unsigned int i; 274 275 if (p->desc->num_timings < num_timings) 276 num_timings = p->desc->num_timings; 277 278 if (timings) 279 for (i = 0; i < num_timings; i++) 280 timings[i] = p->desc->timings[i]; 281 282 return p->desc->num_timings; 283 } 284 285 static const struct drm_panel_funcs panel_simple_funcs = { 286 .disable = panel_simple_disable, 287 .unprepare = panel_simple_unprepare, 288 .prepare = panel_simple_prepare, 289 .enable = panel_simple_enable, 290 .get_modes = panel_simple_get_modes, 291 .get_timings = panel_simple_get_timings, 292 }; 293 294 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 295 { 296 struct device_node *backlight, *ddc; 297 struct panel_simple *panel; 298 int err; 299 300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 301 if (!panel) 302 return -ENOMEM; 303 304 panel->enabled = false; 305 panel->prepared = false; 306 panel->desc = desc; 307 308 panel->supply = devm_regulator_get(dev, "power"); 309 if (IS_ERR(panel->supply)) 310 return PTR_ERR(panel->supply); 311 312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 313 GPIOD_OUT_LOW); 314 if (IS_ERR(panel->enable_gpio)) { 315 err = PTR_ERR(panel->enable_gpio); 316 if (err != -EPROBE_DEFER) 317 dev_err(dev, "failed to request GPIO: %d\n", err); 318 return err; 319 } 320 321 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 322 if (backlight) { 323 panel->backlight = of_find_backlight_by_node(backlight); 324 of_node_put(backlight); 325 326 if (!panel->backlight) 327 return -EPROBE_DEFER; 328 } 329 330 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 331 if (ddc) { 332 panel->ddc = of_find_i2c_adapter_by_node(ddc); 333 of_node_put(ddc); 334 335 if (!panel->ddc) { 336 err = -EPROBE_DEFER; 337 goto free_backlight; 338 } 339 } 340 341 drm_panel_init(&panel->base); 342 panel->base.dev = dev; 343 panel->base.funcs = &panel_simple_funcs; 344 345 err = drm_panel_add(&panel->base); 346 if (err < 0) 347 goto free_ddc; 348 349 dev_set_drvdata(dev, panel); 350 351 return 0; 352 353 free_ddc: 354 if (panel->ddc) 355 put_device(&panel->ddc->dev); 356 free_backlight: 357 if (panel->backlight) 358 put_device(&panel->backlight->dev); 359 360 return err; 361 } 362 363 static int panel_simple_remove(struct device *dev) 364 { 365 struct panel_simple *panel = dev_get_drvdata(dev); 366 367 drm_panel_detach(&panel->base); 368 drm_panel_remove(&panel->base); 369 370 panel_simple_disable(&panel->base); 371 panel_simple_unprepare(&panel->base); 372 373 if (panel->ddc) 374 put_device(&panel->ddc->dev); 375 376 if (panel->backlight) 377 put_device(&panel->backlight->dev); 378 379 return 0; 380 } 381 382 static void panel_simple_shutdown(struct device *dev) 383 { 384 struct panel_simple *panel = dev_get_drvdata(dev); 385 386 panel_simple_disable(&panel->base); 387 panel_simple_unprepare(&panel->base); 388 } 389 390 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 391 .clock = 9000, 392 .hdisplay = 480, 393 .hsync_start = 480 + 2, 394 .hsync_end = 480 + 2 + 41, 395 .htotal = 480 + 2 + 41 + 2, 396 .vdisplay = 272, 397 .vsync_start = 272 + 2, 398 .vsync_end = 272 + 2 + 10, 399 .vtotal = 272 + 2 + 10 + 2, 400 .vrefresh = 60, 401 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 402 }; 403 404 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 405 .modes = &ire_am_480272h3tmqw_t01h_mode, 406 .num_modes = 1, 407 .bpc = 8, 408 .size = { 409 .width = 105, 410 .height = 67, 411 }, 412 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 413 }; 414 415 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 416 .clock = 33333, 417 .hdisplay = 800, 418 .hsync_start = 800 + 0, 419 .hsync_end = 800 + 0 + 255, 420 .htotal = 800 + 0 + 255 + 0, 421 .vdisplay = 480, 422 .vsync_start = 480 + 2, 423 .vsync_end = 480 + 2 + 45, 424 .vtotal = 480 + 2 + 45 + 0, 425 .vrefresh = 60, 426 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 427 }; 428 429 static const struct panel_desc ampire_am800480r3tmqwa1h = { 430 .modes = &ire_am800480r3tmqwa1h_mode, 431 .num_modes = 1, 432 .bpc = 6, 433 .size = { 434 .width = 152, 435 .height = 91, 436 }, 437 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 438 }; 439 440 static const struct drm_display_mode auo_b101aw03_mode = { 441 .clock = 51450, 442 .hdisplay = 1024, 443 .hsync_start = 1024 + 156, 444 .hsync_end = 1024 + 156 + 8, 445 .htotal = 1024 + 156 + 8 + 156, 446 .vdisplay = 600, 447 .vsync_start = 600 + 16, 448 .vsync_end = 600 + 16 + 6, 449 .vtotal = 600 + 16 + 6 + 16, 450 .vrefresh = 60, 451 }; 452 453 static const struct panel_desc auo_b101aw03 = { 454 .modes = &auo_b101aw03_mode, 455 .num_modes = 1, 456 .bpc = 6, 457 .size = { 458 .width = 223, 459 .height = 125, 460 }, 461 }; 462 463 static const struct drm_display_mode auo_b101ean01_mode = { 464 .clock = 72500, 465 .hdisplay = 1280, 466 .hsync_start = 1280 + 119, 467 .hsync_end = 1280 + 119 + 32, 468 .htotal = 1280 + 119 + 32 + 21, 469 .vdisplay = 800, 470 .vsync_start = 800 + 4, 471 .vsync_end = 800 + 4 + 20, 472 .vtotal = 800 + 4 + 20 + 8, 473 .vrefresh = 60, 474 }; 475 476 static const struct panel_desc auo_b101ean01 = { 477 .modes = &auo_b101ean01_mode, 478 .num_modes = 1, 479 .bpc = 6, 480 .size = { 481 .width = 217, 482 .height = 136, 483 }, 484 }; 485 486 static const struct drm_display_mode auo_b101xtn01_mode = { 487 .clock = 72000, 488 .hdisplay = 1366, 489 .hsync_start = 1366 + 20, 490 .hsync_end = 1366 + 20 + 70, 491 .htotal = 1366 + 20 + 70, 492 .vdisplay = 768, 493 .vsync_start = 768 + 14, 494 .vsync_end = 768 + 14 + 42, 495 .vtotal = 768 + 14 + 42, 496 .vrefresh = 60, 497 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 498 }; 499 500 static const struct panel_desc auo_b101xtn01 = { 501 .modes = &auo_b101xtn01_mode, 502 .num_modes = 1, 503 .bpc = 6, 504 .size = { 505 .width = 223, 506 .height = 125, 507 }, 508 }; 509 510 static const struct drm_display_mode auo_b116xw03_mode = { 511 .clock = 70589, 512 .hdisplay = 1366, 513 .hsync_start = 1366 + 40, 514 .hsync_end = 1366 + 40 + 40, 515 .htotal = 1366 + 40 + 40 + 32, 516 .vdisplay = 768, 517 .vsync_start = 768 + 10, 518 .vsync_end = 768 + 10 + 12, 519 .vtotal = 768 + 10 + 12 + 6, 520 .vrefresh = 60, 521 }; 522 523 static const struct panel_desc auo_b116xw03 = { 524 .modes = &auo_b116xw03_mode, 525 .num_modes = 1, 526 .bpc = 6, 527 .size = { 528 .width = 256, 529 .height = 144, 530 }, 531 }; 532 533 static const struct drm_display_mode auo_b133xtn01_mode = { 534 .clock = 69500, 535 .hdisplay = 1366, 536 .hsync_start = 1366 + 48, 537 .hsync_end = 1366 + 48 + 32, 538 .htotal = 1366 + 48 + 32 + 20, 539 .vdisplay = 768, 540 .vsync_start = 768 + 3, 541 .vsync_end = 768 + 3 + 6, 542 .vtotal = 768 + 3 + 6 + 13, 543 .vrefresh = 60, 544 }; 545 546 static const struct panel_desc auo_b133xtn01 = { 547 .modes = &auo_b133xtn01_mode, 548 .num_modes = 1, 549 .bpc = 6, 550 .size = { 551 .width = 293, 552 .height = 165, 553 }, 554 }; 555 556 static const struct drm_display_mode auo_b133htn01_mode = { 557 .clock = 150660, 558 .hdisplay = 1920, 559 .hsync_start = 1920 + 172, 560 .hsync_end = 1920 + 172 + 80, 561 .htotal = 1920 + 172 + 80 + 60, 562 .vdisplay = 1080, 563 .vsync_start = 1080 + 25, 564 .vsync_end = 1080 + 25 + 10, 565 .vtotal = 1080 + 25 + 10 + 10, 566 .vrefresh = 60, 567 }; 568 569 static const struct panel_desc auo_b133htn01 = { 570 .modes = &auo_b133htn01_mode, 571 .num_modes = 1, 572 .bpc = 6, 573 .size = { 574 .width = 293, 575 .height = 165, 576 }, 577 .delay = { 578 .prepare = 105, 579 .enable = 20, 580 .unprepare = 50, 581 }, 582 }; 583 584 static const struct display_timing auo_g133han01_timings = { 585 .pixelclock = { 134000000, 141200000, 149000000 }, 586 .hactive = { 1920, 1920, 1920 }, 587 .hfront_porch = { 39, 58, 77 }, 588 .hback_porch = { 59, 88, 117 }, 589 .hsync_len = { 28, 42, 56 }, 590 .vactive = { 1080, 1080, 1080 }, 591 .vfront_porch = { 3, 8, 11 }, 592 .vback_porch = { 5, 14, 19 }, 593 .vsync_len = { 4, 14, 19 }, 594 }; 595 596 static const struct panel_desc auo_g133han01 = { 597 .timings = &auo_g133han01_timings, 598 .num_timings = 1, 599 .bpc = 8, 600 .size = { 601 .width = 293, 602 .height = 165, 603 }, 604 .delay = { 605 .prepare = 200, 606 .enable = 50, 607 .disable = 50, 608 .unprepare = 1000, 609 }, 610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 611 }; 612 613 static const struct display_timing auo_g185han01_timings = { 614 .pixelclock = { 120000000, 144000000, 175000000 }, 615 .hactive = { 1920, 1920, 1920 }, 616 .hfront_porch = { 18, 60, 74 }, 617 .hback_porch = { 12, 44, 54 }, 618 .hsync_len = { 10, 24, 32 }, 619 .vactive = { 1080, 1080, 1080 }, 620 .vfront_porch = { 6, 10, 40 }, 621 .vback_porch = { 2, 5, 20 }, 622 .vsync_len = { 2, 5, 20 }, 623 }; 624 625 static const struct panel_desc auo_g185han01 = { 626 .timings = &auo_g185han01_timings, 627 .num_timings = 1, 628 .bpc = 8, 629 .size = { 630 .width = 409, 631 .height = 230, 632 }, 633 .delay = { 634 .prepare = 50, 635 .enable = 200, 636 .disable = 110, 637 .unprepare = 1000, 638 }, 639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 640 }; 641 642 static const struct display_timing auo_p320hvn03_timings = { 643 .pixelclock = { 106000000, 148500000, 164000000 }, 644 .hactive = { 1920, 1920, 1920 }, 645 .hfront_porch = { 25, 50, 130 }, 646 .hback_porch = { 25, 50, 130 }, 647 .hsync_len = { 20, 40, 105 }, 648 .vactive = { 1080, 1080, 1080 }, 649 .vfront_porch = { 8, 17, 150 }, 650 .vback_porch = { 8, 17, 150 }, 651 .vsync_len = { 4, 11, 100 }, 652 }; 653 654 static const struct panel_desc auo_p320hvn03 = { 655 .timings = &auo_p320hvn03_timings, 656 .num_timings = 1, 657 .bpc = 8, 658 .size = { 659 .width = 698, 660 .height = 393, 661 }, 662 .delay = { 663 .prepare = 1, 664 .enable = 450, 665 .unprepare = 500, 666 }, 667 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 668 }; 669 670 static const struct drm_display_mode auo_t215hvn01_mode = { 671 .clock = 148800, 672 .hdisplay = 1920, 673 .hsync_start = 1920 + 88, 674 .hsync_end = 1920 + 88 + 44, 675 .htotal = 1920 + 88 + 44 + 148, 676 .vdisplay = 1080, 677 .vsync_start = 1080 + 4, 678 .vsync_end = 1080 + 4 + 5, 679 .vtotal = 1080 + 4 + 5 + 36, 680 .vrefresh = 60, 681 }; 682 683 static const struct panel_desc auo_t215hvn01 = { 684 .modes = &auo_t215hvn01_mode, 685 .num_modes = 1, 686 .bpc = 8, 687 .size = { 688 .width = 430, 689 .height = 270, 690 }, 691 .delay = { 692 .disable = 5, 693 .unprepare = 1000, 694 } 695 }; 696 697 static const struct drm_display_mode avic_tm070ddh03_mode = { 698 .clock = 51200, 699 .hdisplay = 1024, 700 .hsync_start = 1024 + 160, 701 .hsync_end = 1024 + 160 + 4, 702 .htotal = 1024 + 160 + 4 + 156, 703 .vdisplay = 600, 704 .vsync_start = 600 + 17, 705 .vsync_end = 600 + 17 + 1, 706 .vtotal = 600 + 17 + 1 + 17, 707 .vrefresh = 60, 708 }; 709 710 static const struct panel_desc avic_tm070ddh03 = { 711 .modes = &avic_tm070ddh03_mode, 712 .num_modes = 1, 713 .bpc = 8, 714 .size = { 715 .width = 154, 716 .height = 90, 717 }, 718 .delay = { 719 .prepare = 20, 720 .enable = 200, 721 .disable = 200, 722 }, 723 }; 724 725 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 726 { 727 .clock = 71900, 728 .hdisplay = 1280, 729 .hsync_start = 1280 + 48, 730 .hsync_end = 1280 + 48 + 32, 731 .htotal = 1280 + 48 + 32 + 80, 732 .vdisplay = 800, 733 .vsync_start = 800 + 3, 734 .vsync_end = 800 + 3 + 5, 735 .vtotal = 800 + 3 + 5 + 24, 736 .vrefresh = 60, 737 }, 738 { 739 .clock = 57500, 740 .hdisplay = 1280, 741 .hsync_start = 1280 + 48, 742 .hsync_end = 1280 + 48 + 32, 743 .htotal = 1280 + 48 + 32 + 80, 744 .vdisplay = 800, 745 .vsync_start = 800 + 3, 746 .vsync_end = 800 + 3 + 5, 747 .vtotal = 800 + 3 + 5 + 24, 748 .vrefresh = 48, 749 }, 750 }; 751 752 static const struct panel_desc boe_nv101wxmn51 = { 753 .modes = boe_nv101wxmn51_modes, 754 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 755 .bpc = 8, 756 .size = { 757 .width = 217, 758 .height = 136, 759 }, 760 .delay = { 761 .prepare = 210, 762 .enable = 50, 763 .unprepare = 160, 764 }, 765 }; 766 767 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 768 .clock = 66770, 769 .hdisplay = 800, 770 .hsync_start = 800 + 49, 771 .hsync_end = 800 + 49 + 33, 772 .htotal = 800 + 49 + 33 + 17, 773 .vdisplay = 1280, 774 .vsync_start = 1280 + 1, 775 .vsync_end = 1280 + 1 + 7, 776 .vtotal = 1280 + 1 + 7 + 15, 777 .vrefresh = 60, 778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 779 }; 780 781 static const struct panel_desc chunghwa_claa070wp03xg = { 782 .modes = &chunghwa_claa070wp03xg_mode, 783 .num_modes = 1, 784 .bpc = 6, 785 .size = { 786 .width = 94, 787 .height = 150, 788 }, 789 }; 790 791 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 792 .clock = 72070, 793 .hdisplay = 1366, 794 .hsync_start = 1366 + 58, 795 .hsync_end = 1366 + 58 + 58, 796 .htotal = 1366 + 58 + 58 + 58, 797 .vdisplay = 768, 798 .vsync_start = 768 + 4, 799 .vsync_end = 768 + 4 + 4, 800 .vtotal = 768 + 4 + 4 + 4, 801 .vrefresh = 60, 802 }; 803 804 static const struct panel_desc chunghwa_claa101wa01a = { 805 .modes = &chunghwa_claa101wa01a_mode, 806 .num_modes = 1, 807 .bpc = 6, 808 .size = { 809 .width = 220, 810 .height = 120, 811 }, 812 }; 813 814 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 815 .clock = 69300, 816 .hdisplay = 1366, 817 .hsync_start = 1366 + 48, 818 .hsync_end = 1366 + 48 + 32, 819 .htotal = 1366 + 48 + 32 + 20, 820 .vdisplay = 768, 821 .vsync_start = 768 + 16, 822 .vsync_end = 768 + 16 + 8, 823 .vtotal = 768 + 16 + 8 + 16, 824 .vrefresh = 60, 825 }; 826 827 static const struct panel_desc chunghwa_claa101wb01 = { 828 .modes = &chunghwa_claa101wb01_mode, 829 .num_modes = 1, 830 .bpc = 6, 831 .size = { 832 .width = 223, 833 .height = 125, 834 }, 835 }; 836 837 static const struct drm_display_mode edt_et057090dhu_mode = { 838 .clock = 25175, 839 .hdisplay = 640, 840 .hsync_start = 640 + 16, 841 .hsync_end = 640 + 16 + 30, 842 .htotal = 640 + 16 + 30 + 114, 843 .vdisplay = 480, 844 .vsync_start = 480 + 10, 845 .vsync_end = 480 + 10 + 3, 846 .vtotal = 480 + 10 + 3 + 32, 847 .vrefresh = 60, 848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 849 }; 850 851 static const struct panel_desc edt_et057090dhu = { 852 .modes = &edt_et057090dhu_mode, 853 .num_modes = 1, 854 .bpc = 6, 855 .size = { 856 .width = 115, 857 .height = 86, 858 }, 859 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 860 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 861 }; 862 863 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 864 .clock = 33260, 865 .hdisplay = 800, 866 .hsync_start = 800 + 40, 867 .hsync_end = 800 + 40 + 128, 868 .htotal = 800 + 40 + 128 + 88, 869 .vdisplay = 480, 870 .vsync_start = 480 + 10, 871 .vsync_end = 480 + 10 + 2, 872 .vtotal = 480 + 10 + 2 + 33, 873 .vrefresh = 60, 874 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 875 }; 876 877 static const struct panel_desc edt_etm0700g0dh6 = { 878 .modes = &edt_etm0700g0dh6_mode, 879 .num_modes = 1, 880 .bpc = 6, 881 .size = { 882 .width = 152, 883 .height = 91, 884 }, 885 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 886 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 887 }; 888 889 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 890 .clock = 32260, 891 .hdisplay = 800, 892 .hsync_start = 800 + 168, 893 .hsync_end = 800 + 168 + 64, 894 .htotal = 800 + 168 + 64 + 88, 895 .vdisplay = 480, 896 .vsync_start = 480 + 37, 897 .vsync_end = 480 + 37 + 2, 898 .vtotal = 480 + 37 + 2 + 8, 899 .vrefresh = 60, 900 }; 901 902 static const struct panel_desc foxlink_fl500wvr00_a0t = { 903 .modes = &foxlink_fl500wvr00_a0t_mode, 904 .num_modes = 1, 905 .bpc = 8, 906 .size = { 907 .width = 108, 908 .height = 65, 909 }, 910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 911 }; 912 913 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 914 .clock = 9000, 915 .hdisplay = 480, 916 .hsync_start = 480 + 5, 917 .hsync_end = 480 + 5 + 1, 918 .htotal = 480 + 5 + 1 + 40, 919 .vdisplay = 272, 920 .vsync_start = 272 + 8, 921 .vsync_end = 272 + 8 + 1, 922 .vtotal = 272 + 8 + 1 + 8, 923 .vrefresh = 60, 924 }; 925 926 static const struct panel_desc giantplus_gpg482739qs5 = { 927 .modes = &giantplus_gpg482739qs5_mode, 928 .num_modes = 1, 929 .bpc = 8, 930 .size = { 931 .width = 95, 932 .height = 54, 933 }, 934 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 935 }; 936 937 static const struct display_timing hannstar_hsd070pww1_timing = { 938 .pixelclock = { 64300000, 71100000, 82000000 }, 939 .hactive = { 1280, 1280, 1280 }, 940 .hfront_porch = { 1, 1, 10 }, 941 .hback_porch = { 1, 1, 10 }, 942 /* 943 * According to the data sheet, the minimum horizontal blanking interval 944 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 945 * minimum working horizontal blanking interval to be 60 clocks. 946 */ 947 .hsync_len = { 58, 158, 661 }, 948 .vactive = { 800, 800, 800 }, 949 .vfront_porch = { 1, 1, 10 }, 950 .vback_porch = { 1, 1, 10 }, 951 .vsync_len = { 1, 21, 203 }, 952 .flags = DISPLAY_FLAGS_DE_HIGH, 953 }; 954 955 static const struct panel_desc hannstar_hsd070pww1 = { 956 .timings = &hannstar_hsd070pww1_timing, 957 .num_timings = 1, 958 .bpc = 6, 959 .size = { 960 .width = 151, 961 .height = 94, 962 }, 963 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 964 }; 965 966 static const struct display_timing hannstar_hsd100pxn1_timing = { 967 .pixelclock = { 55000000, 65000000, 75000000 }, 968 .hactive = { 1024, 1024, 1024 }, 969 .hfront_porch = { 40, 40, 40 }, 970 .hback_porch = { 220, 220, 220 }, 971 .hsync_len = { 20, 60, 100 }, 972 .vactive = { 768, 768, 768 }, 973 .vfront_porch = { 7, 7, 7 }, 974 .vback_porch = { 21, 21, 21 }, 975 .vsync_len = { 10, 10, 10 }, 976 .flags = DISPLAY_FLAGS_DE_HIGH, 977 }; 978 979 static const struct panel_desc hannstar_hsd100pxn1 = { 980 .timings = &hannstar_hsd100pxn1_timing, 981 .num_timings = 1, 982 .bpc = 6, 983 .size = { 984 .width = 203, 985 .height = 152, 986 }, 987 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 988 }; 989 990 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 991 .clock = 33333, 992 .hdisplay = 800, 993 .hsync_start = 800 + 85, 994 .hsync_end = 800 + 85 + 86, 995 .htotal = 800 + 85 + 86 + 85, 996 .vdisplay = 480, 997 .vsync_start = 480 + 16, 998 .vsync_end = 480 + 16 + 13, 999 .vtotal = 480 + 16 + 13 + 16, 1000 .vrefresh = 60, 1001 }; 1002 1003 static const struct panel_desc hitachi_tx23d38vm0caa = { 1004 .modes = &hitachi_tx23d38vm0caa_mode, 1005 .num_modes = 1, 1006 .bpc = 6, 1007 .size = { 1008 .width = 195, 1009 .height = 117, 1010 }, 1011 .delay = { 1012 .enable = 160, 1013 .disable = 160, 1014 }, 1015 }; 1016 1017 static const struct drm_display_mode innolux_at043tn24_mode = { 1018 .clock = 9000, 1019 .hdisplay = 480, 1020 .hsync_start = 480 + 2, 1021 .hsync_end = 480 + 2 + 41, 1022 .htotal = 480 + 2 + 41 + 2, 1023 .vdisplay = 272, 1024 .vsync_start = 272 + 2, 1025 .vsync_end = 272 + 2 + 10, 1026 .vtotal = 272 + 2 + 10 + 2, 1027 .vrefresh = 60, 1028 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1029 }; 1030 1031 static const struct panel_desc innolux_at043tn24 = { 1032 .modes = &innolux_at043tn24_mode, 1033 .num_modes = 1, 1034 .bpc = 8, 1035 .size = { 1036 .width = 95, 1037 .height = 54, 1038 }, 1039 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1040 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1041 }; 1042 1043 static const struct drm_display_mode innolux_at070tn92_mode = { 1044 .clock = 33333, 1045 .hdisplay = 800, 1046 .hsync_start = 800 + 210, 1047 .hsync_end = 800 + 210 + 20, 1048 .htotal = 800 + 210 + 20 + 46, 1049 .vdisplay = 480, 1050 .vsync_start = 480 + 22, 1051 .vsync_end = 480 + 22 + 10, 1052 .vtotal = 480 + 22 + 23 + 10, 1053 .vrefresh = 60, 1054 }; 1055 1056 static const struct panel_desc innolux_at070tn92 = { 1057 .modes = &innolux_at070tn92_mode, 1058 .num_modes = 1, 1059 .size = { 1060 .width = 154, 1061 .height = 86, 1062 }, 1063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1064 }; 1065 1066 static const struct display_timing innolux_g101ice_l01_timing = { 1067 .pixelclock = { 60400000, 71100000, 74700000 }, 1068 .hactive = { 1280, 1280, 1280 }, 1069 .hfront_porch = { 41, 80, 100 }, 1070 .hback_porch = { 40, 79, 99 }, 1071 .hsync_len = { 1, 1, 1 }, 1072 .vactive = { 800, 800, 800 }, 1073 .vfront_porch = { 5, 11, 14 }, 1074 .vback_porch = { 4, 11, 14 }, 1075 .vsync_len = { 1, 1, 1 }, 1076 .flags = DISPLAY_FLAGS_DE_HIGH, 1077 }; 1078 1079 static const struct panel_desc innolux_g101ice_l01 = { 1080 .timings = &innolux_g101ice_l01_timing, 1081 .num_timings = 1, 1082 .bpc = 8, 1083 .size = { 1084 .width = 217, 1085 .height = 135, 1086 }, 1087 .delay = { 1088 .enable = 200, 1089 .disable = 200, 1090 }, 1091 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1092 }; 1093 1094 static const struct display_timing innolux_g121i1_l01_timing = { 1095 .pixelclock = { 67450000, 71000000, 74550000 }, 1096 .hactive = { 1280, 1280, 1280 }, 1097 .hfront_porch = { 40, 80, 160 }, 1098 .hback_porch = { 39, 79, 159 }, 1099 .hsync_len = { 1, 1, 1 }, 1100 .vactive = { 800, 800, 800 }, 1101 .vfront_porch = { 5, 11, 100 }, 1102 .vback_porch = { 4, 11, 99 }, 1103 .vsync_len = { 1, 1, 1 }, 1104 }; 1105 1106 static const struct panel_desc innolux_g121i1_l01 = { 1107 .timings = &innolux_g121i1_l01_timing, 1108 .num_timings = 1, 1109 .bpc = 6, 1110 .size = { 1111 .width = 261, 1112 .height = 163, 1113 }, 1114 .delay = { 1115 .enable = 200, 1116 .disable = 20, 1117 }, 1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1119 }; 1120 1121 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1122 .clock = 65000, 1123 .hdisplay = 1024, 1124 .hsync_start = 1024 + 0, 1125 .hsync_end = 1024 + 1, 1126 .htotal = 1024 + 0 + 1 + 320, 1127 .vdisplay = 768, 1128 .vsync_start = 768 + 38, 1129 .vsync_end = 768 + 38 + 1, 1130 .vtotal = 768 + 38 + 1 + 0, 1131 .vrefresh = 60, 1132 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1133 }; 1134 1135 static const struct panel_desc innolux_g121x1_l03 = { 1136 .modes = &innolux_g121x1_l03_mode, 1137 .num_modes = 1, 1138 .bpc = 6, 1139 .size = { 1140 .width = 246, 1141 .height = 185, 1142 }, 1143 .delay = { 1144 .enable = 200, 1145 .unprepare = 200, 1146 .disable = 400, 1147 }, 1148 }; 1149 1150 static const struct drm_display_mode innolux_n116bge_mode = { 1151 .clock = 76420, 1152 .hdisplay = 1366, 1153 .hsync_start = 1366 + 136, 1154 .hsync_end = 1366 + 136 + 30, 1155 .htotal = 1366 + 136 + 30 + 60, 1156 .vdisplay = 768, 1157 .vsync_start = 768 + 8, 1158 .vsync_end = 768 + 8 + 12, 1159 .vtotal = 768 + 8 + 12 + 12, 1160 .vrefresh = 60, 1161 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1162 }; 1163 1164 static const struct panel_desc innolux_n116bge = { 1165 .modes = &innolux_n116bge_mode, 1166 .num_modes = 1, 1167 .bpc = 6, 1168 .size = { 1169 .width = 256, 1170 .height = 144, 1171 }, 1172 }; 1173 1174 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1175 .clock = 69300, 1176 .hdisplay = 1366, 1177 .hsync_start = 1366 + 16, 1178 .hsync_end = 1366 + 16 + 34, 1179 .htotal = 1366 + 16 + 34 + 50, 1180 .vdisplay = 768, 1181 .vsync_start = 768 + 2, 1182 .vsync_end = 768 + 2 + 6, 1183 .vtotal = 768 + 2 + 6 + 12, 1184 .vrefresh = 60, 1185 }; 1186 1187 static const struct panel_desc innolux_n156bge_l21 = { 1188 .modes = &innolux_n156bge_l21_mode, 1189 .num_modes = 1, 1190 .bpc = 6, 1191 .size = { 1192 .width = 344, 1193 .height = 193, 1194 }, 1195 }; 1196 1197 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1198 .clock = 51501, 1199 .hdisplay = 1024, 1200 .hsync_start = 1024 + 128, 1201 .hsync_end = 1024 + 128 + 64, 1202 .htotal = 1024 + 128 + 64 + 128, 1203 .vdisplay = 600, 1204 .vsync_start = 600 + 16, 1205 .vsync_end = 600 + 16 + 4, 1206 .vtotal = 600 + 16 + 4 + 16, 1207 .vrefresh = 60, 1208 }; 1209 1210 static const struct panel_desc innolux_zj070na_01p = { 1211 .modes = &innolux_zj070na_01p_mode, 1212 .num_modes = 1, 1213 .bpc = 6, 1214 .size = { 1215 .width = 154, 1216 .height = 90, 1217 }, 1218 }; 1219 1220 static const struct display_timing kyo_tcg121xglp_timing = { 1221 .pixelclock = { 52000000, 65000000, 71000000 }, 1222 .hactive = { 1024, 1024, 1024 }, 1223 .hfront_porch = { 2, 2, 2 }, 1224 .hback_porch = { 2, 2, 2 }, 1225 .hsync_len = { 86, 124, 244 }, 1226 .vactive = { 768, 768, 768 }, 1227 .vfront_porch = { 2, 2, 2 }, 1228 .vback_porch = { 2, 2, 2 }, 1229 .vsync_len = { 6, 34, 73 }, 1230 .flags = DISPLAY_FLAGS_DE_HIGH, 1231 }; 1232 1233 static const struct panel_desc kyo_tcg121xglp = { 1234 .timings = &kyo_tcg121xglp_timing, 1235 .num_timings = 1, 1236 .bpc = 8, 1237 .size = { 1238 .width = 246, 1239 .height = 184, 1240 }, 1241 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1242 }; 1243 1244 static const struct drm_display_mode lg_lb070wv8_mode = { 1245 .clock = 33246, 1246 .hdisplay = 800, 1247 .hsync_start = 800 + 88, 1248 .hsync_end = 800 + 88 + 80, 1249 .htotal = 800 + 88 + 80 + 88, 1250 .vdisplay = 480, 1251 .vsync_start = 480 + 10, 1252 .vsync_end = 480 + 10 + 25, 1253 .vtotal = 480 + 10 + 25 + 10, 1254 .vrefresh = 60, 1255 }; 1256 1257 static const struct panel_desc lg_lb070wv8 = { 1258 .modes = &lg_lb070wv8_mode, 1259 .num_modes = 1, 1260 .bpc = 16, 1261 .size = { 1262 .width = 151, 1263 .height = 91, 1264 }, 1265 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1266 }; 1267 1268 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1269 .clock = 200000, 1270 .hdisplay = 1536, 1271 .hsync_start = 1536 + 12, 1272 .hsync_end = 1536 + 12 + 16, 1273 .htotal = 1536 + 12 + 16 + 48, 1274 .vdisplay = 2048, 1275 .vsync_start = 2048 + 8, 1276 .vsync_end = 2048 + 8 + 4, 1277 .vtotal = 2048 + 8 + 4 + 8, 1278 .vrefresh = 60, 1279 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1280 }; 1281 1282 static const struct panel_desc lg_lp079qx1_sp0v = { 1283 .modes = &lg_lp079qx1_sp0v_mode, 1284 .num_modes = 1, 1285 .size = { 1286 .width = 129, 1287 .height = 171, 1288 }, 1289 }; 1290 1291 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1292 .clock = 205210, 1293 .hdisplay = 2048, 1294 .hsync_start = 2048 + 150, 1295 .hsync_end = 2048 + 150 + 5, 1296 .htotal = 2048 + 150 + 5 + 5, 1297 .vdisplay = 1536, 1298 .vsync_start = 1536 + 3, 1299 .vsync_end = 1536 + 3 + 1, 1300 .vtotal = 1536 + 3 + 1 + 9, 1301 .vrefresh = 60, 1302 }; 1303 1304 static const struct panel_desc lg_lp097qx1_spa1 = { 1305 .modes = &lg_lp097qx1_spa1_mode, 1306 .num_modes = 1, 1307 .size = { 1308 .width = 208, 1309 .height = 147, 1310 }, 1311 }; 1312 1313 static const struct drm_display_mode lg_lp120up1_mode = { 1314 .clock = 162300, 1315 .hdisplay = 1920, 1316 .hsync_start = 1920 + 40, 1317 .hsync_end = 1920 + 40 + 40, 1318 .htotal = 1920 + 40 + 40+ 80, 1319 .vdisplay = 1280, 1320 .vsync_start = 1280 + 4, 1321 .vsync_end = 1280 + 4 + 4, 1322 .vtotal = 1280 + 4 + 4 + 12, 1323 .vrefresh = 60, 1324 }; 1325 1326 static const struct panel_desc lg_lp120up1 = { 1327 .modes = &lg_lp120up1_mode, 1328 .num_modes = 1, 1329 .bpc = 8, 1330 .size = { 1331 .width = 267, 1332 .height = 183, 1333 }, 1334 }; 1335 1336 static const struct drm_display_mode lg_lp129qe_mode = { 1337 .clock = 285250, 1338 .hdisplay = 2560, 1339 .hsync_start = 2560 + 48, 1340 .hsync_end = 2560 + 48 + 32, 1341 .htotal = 2560 + 48 + 32 + 80, 1342 .vdisplay = 1700, 1343 .vsync_start = 1700 + 3, 1344 .vsync_end = 1700 + 3 + 10, 1345 .vtotal = 1700 + 3 + 10 + 36, 1346 .vrefresh = 60, 1347 }; 1348 1349 static const struct panel_desc lg_lp129qe = { 1350 .modes = &lg_lp129qe_mode, 1351 .num_modes = 1, 1352 .bpc = 8, 1353 .size = { 1354 .width = 272, 1355 .height = 181, 1356 }, 1357 }; 1358 1359 static const struct display_timing nec_nl12880bc20_05_timing = { 1360 .pixelclock = { 67000000, 71000000, 75000000 }, 1361 .hactive = { 1280, 1280, 1280 }, 1362 .hfront_porch = { 2, 30, 30 }, 1363 .hback_porch = { 6, 100, 100 }, 1364 .hsync_len = { 2, 30, 30 }, 1365 .vactive = { 800, 800, 800 }, 1366 .vfront_porch = { 5, 5, 5 }, 1367 .vback_porch = { 11, 11, 11 }, 1368 .vsync_len = { 7, 7, 7 }, 1369 }; 1370 1371 static const struct panel_desc nec_nl12880bc20_05 = { 1372 .timings = &nec_nl12880bc20_05_timing, 1373 .num_timings = 1, 1374 .bpc = 8, 1375 .size = { 1376 .width = 261, 1377 .height = 163, 1378 }, 1379 .delay = { 1380 .enable = 50, 1381 .disable = 50, 1382 }, 1383 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1384 }; 1385 1386 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1387 .clock = 10870, 1388 .hdisplay = 480, 1389 .hsync_start = 480 + 2, 1390 .hsync_end = 480 + 2 + 41, 1391 .htotal = 480 + 2 + 41 + 2, 1392 .vdisplay = 272, 1393 .vsync_start = 272 + 2, 1394 .vsync_end = 272 + 2 + 4, 1395 .vtotal = 272 + 2 + 4 + 2, 1396 .vrefresh = 74, 1397 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1398 }; 1399 1400 static const struct panel_desc nec_nl4827hc19_05b = { 1401 .modes = &nec_nl4827hc19_05b_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 95, 1406 .height = 54, 1407 }, 1408 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1409 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1410 }; 1411 1412 static const struct drm_display_mode netron_dy_e231732_mode = { 1413 .clock = 66000, 1414 .hdisplay = 1024, 1415 .hsync_start = 1024 + 160, 1416 .hsync_end = 1024 + 160 + 70, 1417 .htotal = 1024 + 160 + 70 + 90, 1418 .vdisplay = 600, 1419 .vsync_start = 600 + 127, 1420 .vsync_end = 600 + 127 + 20, 1421 .vtotal = 600 + 127 + 20 + 3, 1422 .vrefresh = 60, 1423 }; 1424 1425 static const struct panel_desc netron_dy_e231732 = { 1426 .modes = &netron_dy_e231732_mode, 1427 .num_modes = 1, 1428 .size = { 1429 .width = 154, 1430 .height = 87, 1431 }, 1432 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1433 }; 1434 1435 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1436 .pixelclock = { 130000000, 148350000, 163000000 }, 1437 .hactive = { 1920, 1920, 1920 }, 1438 .hfront_porch = { 80, 100, 100 }, 1439 .hback_porch = { 100, 120, 120 }, 1440 .hsync_len = { 50, 60, 60 }, 1441 .vactive = { 1080, 1080, 1080 }, 1442 .vfront_porch = { 12, 30, 30 }, 1443 .vback_porch = { 4, 10, 10 }, 1444 .vsync_len = { 4, 5, 5 }, 1445 }; 1446 1447 static const struct panel_desc nlt_nl192108ac18_02d = { 1448 .timings = &nlt_nl192108ac18_02d_timing, 1449 .num_timings = 1, 1450 .bpc = 8, 1451 .size = { 1452 .width = 344, 1453 .height = 194, 1454 }, 1455 .delay = { 1456 .unprepare = 500, 1457 }, 1458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1459 }; 1460 1461 static const struct drm_display_mode nvd_9128_mode = { 1462 .clock = 29500, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 130, 1465 .hsync_end = 800 + 130 + 98, 1466 .htotal = 800 + 0 + 130 + 98, 1467 .vdisplay = 480, 1468 .vsync_start = 480 + 10, 1469 .vsync_end = 480 + 10 + 50, 1470 .vtotal = 480 + 0 + 10 + 50, 1471 }; 1472 1473 static const struct panel_desc nvd_9128 = { 1474 .modes = &nvd_9128_mode, 1475 .num_modes = 1, 1476 .bpc = 8, 1477 .size = { 1478 .width = 156, 1479 .height = 88, 1480 }, 1481 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1482 }; 1483 1484 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1485 .pixelclock = { 30000000, 30000000, 40000000 }, 1486 .hactive = { 800, 800, 800 }, 1487 .hfront_porch = { 40, 40, 40 }, 1488 .hback_porch = { 40, 40, 40 }, 1489 .hsync_len = { 1, 48, 48 }, 1490 .vactive = { 480, 480, 480 }, 1491 .vfront_porch = { 13, 13, 13 }, 1492 .vback_porch = { 29, 29, 29 }, 1493 .vsync_len = { 3, 3, 3 }, 1494 .flags = DISPLAY_FLAGS_DE_HIGH, 1495 }; 1496 1497 static const struct panel_desc okaya_rs800480t_7x0gp = { 1498 .timings = &okaya_rs800480t_7x0gp_timing, 1499 .num_timings = 1, 1500 .bpc = 6, 1501 .size = { 1502 .width = 154, 1503 .height = 87, 1504 }, 1505 .delay = { 1506 .prepare = 41, 1507 .enable = 50, 1508 .unprepare = 41, 1509 .disable = 50, 1510 }, 1511 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1512 }; 1513 1514 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1515 .clock = 9000, 1516 .hdisplay = 480, 1517 .hsync_start = 480 + 5, 1518 .hsync_end = 480 + 5 + 30, 1519 .htotal = 480 + 5 + 30 + 10, 1520 .vdisplay = 272, 1521 .vsync_start = 272 + 8, 1522 .vsync_end = 272 + 8 + 5, 1523 .vtotal = 272 + 8 + 5 + 3, 1524 .vrefresh = 60, 1525 }; 1526 1527 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1528 .modes = &olimex_lcd_olinuxino_43ts_mode, 1529 .num_modes = 1, 1530 .size = { 1531 .width = 95, 1532 .height = 54, 1533 }, 1534 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1535 }; 1536 1537 /* 1538 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1539 * pixel clocks, but this is the timing that was being used in the Adafruit 1540 * installation instructions. 1541 */ 1542 static const struct drm_display_mode ontat_yx700wv03_mode = { 1543 .clock = 29500, 1544 .hdisplay = 800, 1545 .hsync_start = 824, 1546 .hsync_end = 896, 1547 .htotal = 992, 1548 .vdisplay = 480, 1549 .vsync_start = 483, 1550 .vsync_end = 493, 1551 .vtotal = 500, 1552 .vrefresh = 60, 1553 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1554 }; 1555 1556 /* 1557 * Specification at: 1558 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1559 */ 1560 static const struct panel_desc ontat_yx700wv03 = { 1561 .modes = &ontat_yx700wv03_mode, 1562 .num_modes = 1, 1563 .bpc = 8, 1564 .size = { 1565 .width = 154, 1566 .height = 83, 1567 }, 1568 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1569 }; 1570 1571 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1572 .clock = 25000, 1573 .hdisplay = 480, 1574 .hsync_start = 480 + 10, 1575 .hsync_end = 480 + 10 + 10, 1576 .htotal = 480 + 10 + 10 + 15, 1577 .vdisplay = 800, 1578 .vsync_start = 800 + 3, 1579 .vsync_end = 800 + 3 + 3, 1580 .vtotal = 800 + 3 + 3 + 3, 1581 .vrefresh = 60, 1582 }; 1583 1584 static const struct panel_desc ortustech_com43h4m85ulc = { 1585 .modes = &ortustech_com43h4m85ulc_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 56, 1590 .height = 93, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1594 }; 1595 1596 static const struct drm_display_mode qd43003c0_40_mode = { 1597 .clock = 9000, 1598 .hdisplay = 480, 1599 .hsync_start = 480 + 8, 1600 .hsync_end = 480 + 8 + 4, 1601 .htotal = 480 + 8 + 4 + 39, 1602 .vdisplay = 272, 1603 .vsync_start = 272 + 4, 1604 .vsync_end = 272 + 4 + 10, 1605 .vtotal = 272 + 4 + 10 + 2, 1606 .vrefresh = 60, 1607 }; 1608 1609 static const struct panel_desc qd43003c0_40 = { 1610 .modes = &qd43003c0_40_mode, 1611 .num_modes = 1, 1612 .bpc = 8, 1613 .size = { 1614 .width = 95, 1615 .height = 53, 1616 }, 1617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1618 }; 1619 1620 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1621 .clock = 271560, 1622 .hdisplay = 2560, 1623 .hsync_start = 2560 + 48, 1624 .hsync_end = 2560 + 48 + 32, 1625 .htotal = 2560 + 48 + 32 + 80, 1626 .vdisplay = 1600, 1627 .vsync_start = 1600 + 2, 1628 .vsync_end = 1600 + 2 + 5, 1629 .vtotal = 1600 + 2 + 5 + 57, 1630 .vrefresh = 60, 1631 }; 1632 1633 static const struct panel_desc samsung_lsn122dl01_c01 = { 1634 .modes = &samsung_lsn122dl01_c01_mode, 1635 .num_modes = 1, 1636 .size = { 1637 .width = 263, 1638 .height = 164, 1639 }, 1640 }; 1641 1642 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1643 .clock = 54030, 1644 .hdisplay = 1024, 1645 .hsync_start = 1024 + 24, 1646 .hsync_end = 1024 + 24 + 136, 1647 .htotal = 1024 + 24 + 136 + 160, 1648 .vdisplay = 600, 1649 .vsync_start = 600 + 3, 1650 .vsync_end = 600 + 3 + 6, 1651 .vtotal = 600 + 3 + 6 + 61, 1652 .vrefresh = 60, 1653 }; 1654 1655 static const struct panel_desc samsung_ltn101nt05 = { 1656 .modes = &samsung_ltn101nt05_mode, 1657 .num_modes = 1, 1658 .bpc = 6, 1659 .size = { 1660 .width = 223, 1661 .height = 125, 1662 }, 1663 }; 1664 1665 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1666 .clock = 76300, 1667 .hdisplay = 1366, 1668 .hsync_start = 1366 + 64, 1669 .hsync_end = 1366 + 64 + 48, 1670 .htotal = 1366 + 64 + 48 + 128, 1671 .vdisplay = 768, 1672 .vsync_start = 768 + 2, 1673 .vsync_end = 768 + 2 + 5, 1674 .vtotal = 768 + 2 + 5 + 17, 1675 .vrefresh = 60, 1676 }; 1677 1678 static const struct panel_desc samsung_ltn140at29_301 = { 1679 .modes = &samsung_ltn140at29_301_mode, 1680 .num_modes = 1, 1681 .bpc = 6, 1682 .size = { 1683 .width = 320, 1684 .height = 187, 1685 }, 1686 }; 1687 1688 static const struct display_timing sharp_lq101k1ly04_timing = { 1689 .pixelclock = { 60000000, 65000000, 80000000 }, 1690 .hactive = { 1280, 1280, 1280 }, 1691 .hfront_porch = { 20, 20, 20 }, 1692 .hback_porch = { 20, 20, 20 }, 1693 .hsync_len = { 10, 10, 10 }, 1694 .vactive = { 800, 800, 800 }, 1695 .vfront_porch = { 4, 4, 4 }, 1696 .vback_porch = { 4, 4, 4 }, 1697 .vsync_len = { 4, 4, 4 }, 1698 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 1699 }; 1700 1701 static const struct panel_desc sharp_lq101k1ly04 = { 1702 .timings = &sharp_lq101k1ly04_timing, 1703 .num_timings = 1, 1704 .bpc = 8, 1705 .size = { 1706 .width = 217, 1707 .height = 136, 1708 }, 1709 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1710 }; 1711 1712 static const struct drm_display_mode sharp_lq123p1jx31_mode = { 1713 .clock = 252750, 1714 .hdisplay = 2400, 1715 .hsync_start = 2400 + 48, 1716 .hsync_end = 2400 + 48 + 32, 1717 .htotal = 2400 + 48 + 32 + 80, 1718 .vdisplay = 1600, 1719 .vsync_start = 1600 + 3, 1720 .vsync_end = 1600 + 3 + 10, 1721 .vtotal = 1600 + 3 + 10 + 33, 1722 .vrefresh = 60, 1723 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1724 }; 1725 1726 static const struct panel_desc sharp_lq123p1jx31 = { 1727 .modes = &sharp_lq123p1jx31_mode, 1728 .num_modes = 1, 1729 .bpc = 8, 1730 .size = { 1731 .width = 259, 1732 .height = 173, 1733 }, 1734 .delay = { 1735 .prepare = 110, 1736 .enable = 50, 1737 .unprepare = 550, 1738 }, 1739 }; 1740 1741 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 1742 .clock = 71100, 1743 .hdisplay = 1024, 1744 .hsync_start = 1024 + 168, 1745 .hsync_end = 1024 + 168 + 64, 1746 .htotal = 1024 + 168 + 64 + 88, 1747 .vdisplay = 768, 1748 .vsync_start = 768 + 37, 1749 .vsync_end = 768 + 37 + 2, 1750 .vtotal = 768 + 37 + 2 + 8, 1751 .vrefresh = 60, 1752 }; 1753 1754 static const struct panel_desc sharp_lq150x1lg11 = { 1755 .modes = &sharp_lq150x1lg11_mode, 1756 .num_modes = 1, 1757 .bpc = 6, 1758 .size = { 1759 .width = 304, 1760 .height = 228, 1761 }, 1762 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 1763 }; 1764 1765 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 1766 .clock = 33300, 1767 .hdisplay = 800, 1768 .hsync_start = 800 + 1, 1769 .hsync_end = 800 + 1 + 64, 1770 .htotal = 800 + 1 + 64 + 64, 1771 .vdisplay = 480, 1772 .vsync_start = 480 + 1, 1773 .vsync_end = 480 + 1 + 23, 1774 .vtotal = 480 + 1 + 23 + 22, 1775 .vrefresh = 60, 1776 }; 1777 1778 static const struct panel_desc shelly_sca07010_bfn_lnn = { 1779 .modes = &shelly_sca07010_bfn_lnn_mode, 1780 .num_modes = 1, 1781 .size = { 1782 .width = 152, 1783 .height = 91, 1784 }, 1785 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1786 }; 1787 1788 static const struct drm_display_mode starry_kr122ea0sra_mode = { 1789 .clock = 147000, 1790 .hdisplay = 1920, 1791 .hsync_start = 1920 + 16, 1792 .hsync_end = 1920 + 16 + 16, 1793 .htotal = 1920 + 16 + 16 + 32, 1794 .vdisplay = 1200, 1795 .vsync_start = 1200 + 15, 1796 .vsync_end = 1200 + 15 + 2, 1797 .vtotal = 1200 + 15 + 2 + 18, 1798 .vrefresh = 60, 1799 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1800 }; 1801 1802 static const struct panel_desc starry_kr122ea0sra = { 1803 .modes = &starry_kr122ea0sra_mode, 1804 .num_modes = 1, 1805 .size = { 1806 .width = 263, 1807 .height = 164, 1808 }, 1809 .delay = { 1810 .prepare = 10 + 200, 1811 .enable = 50, 1812 .unprepare = 10 + 500, 1813 }, 1814 }; 1815 1816 static const struct display_timing tianma_tm070jdhg30_timing = { 1817 .pixelclock = { 62600000, 68200000, 78100000 }, 1818 .hactive = { 1280, 1280, 1280 }, 1819 .hfront_porch = { 15, 64, 159 }, 1820 .hback_porch = { 5, 5, 5 }, 1821 .hsync_len = { 1, 1, 256 }, 1822 .vactive = { 800, 800, 800 }, 1823 .vfront_porch = { 3, 40, 99 }, 1824 .vback_porch = { 2, 2, 2 }, 1825 .vsync_len = { 1, 1, 128 }, 1826 .flags = DISPLAY_FLAGS_DE_HIGH, 1827 }; 1828 1829 static const struct panel_desc tianma_tm070jdhg30 = { 1830 .timings = &tianma_tm070jdhg30_timing, 1831 .num_timings = 1, 1832 .bpc = 8, 1833 .size = { 1834 .width = 151, 1835 .height = 95, 1836 }, 1837 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1838 }; 1839 1840 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 1841 .clock = 79500, 1842 .hdisplay = 1280, 1843 .hsync_start = 1280 + 192, 1844 .hsync_end = 1280 + 192 + 128, 1845 .htotal = 1280 + 192 + 128 + 64, 1846 .vdisplay = 768, 1847 .vsync_start = 768 + 20, 1848 .vsync_end = 768 + 20 + 7, 1849 .vtotal = 768 + 20 + 7 + 3, 1850 .vrefresh = 60, 1851 }; 1852 1853 static const struct panel_desc toshiba_lt089ac29000 = { 1854 .modes = &toshiba_lt089ac29000_mode, 1855 .num_modes = 1, 1856 .size = { 1857 .width = 194, 1858 .height = 116, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1862 }; 1863 1864 static const struct drm_display_mode tpk_f07a_0102_mode = { 1865 .clock = 33260, 1866 .hdisplay = 800, 1867 .hsync_start = 800 + 40, 1868 .hsync_end = 800 + 40 + 128, 1869 .htotal = 800 + 40 + 128 + 88, 1870 .vdisplay = 480, 1871 .vsync_start = 480 + 10, 1872 .vsync_end = 480 + 10 + 2, 1873 .vtotal = 480 + 10 + 2 + 33, 1874 .vrefresh = 60, 1875 }; 1876 1877 static const struct panel_desc tpk_f07a_0102 = { 1878 .modes = &tpk_f07a_0102_mode, 1879 .num_modes = 1, 1880 .size = { 1881 .width = 152, 1882 .height = 91, 1883 }, 1884 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1885 }; 1886 1887 static const struct drm_display_mode tpk_f10a_0102_mode = { 1888 .clock = 45000, 1889 .hdisplay = 1024, 1890 .hsync_start = 1024 + 176, 1891 .hsync_end = 1024 + 176 + 5, 1892 .htotal = 1024 + 176 + 5 + 88, 1893 .vdisplay = 600, 1894 .vsync_start = 600 + 20, 1895 .vsync_end = 600 + 20 + 5, 1896 .vtotal = 600 + 20 + 5 + 25, 1897 .vrefresh = 60, 1898 }; 1899 1900 static const struct panel_desc tpk_f10a_0102 = { 1901 .modes = &tpk_f10a_0102_mode, 1902 .num_modes = 1, 1903 .size = { 1904 .width = 223, 1905 .height = 125, 1906 }, 1907 }; 1908 1909 static const struct display_timing urt_umsh_8596md_timing = { 1910 .pixelclock = { 33260000, 33260000, 33260000 }, 1911 .hactive = { 800, 800, 800 }, 1912 .hfront_porch = { 41, 41, 41 }, 1913 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 1914 .hsync_len = { 71, 128, 128 }, 1915 .vactive = { 480, 480, 480 }, 1916 .vfront_porch = { 10, 10, 10 }, 1917 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 1918 .vsync_len = { 2, 2, 2 }, 1919 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1920 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1921 }; 1922 1923 static const struct panel_desc urt_umsh_8596md_lvds = { 1924 .timings = &urt_umsh_8596md_timing, 1925 .num_timings = 1, 1926 .bpc = 6, 1927 .size = { 1928 .width = 152, 1929 .height = 91, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 }; 1933 1934 static const struct panel_desc urt_umsh_8596md_parallel = { 1935 .timings = &urt_umsh_8596md_timing, 1936 .num_timings = 1, 1937 .bpc = 6, 1938 .size = { 1939 .width = 152, 1940 .height = 91, 1941 }, 1942 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1943 }; 1944 1945 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 1946 .clock = 6410, 1947 .hdisplay = 320, 1948 .hsync_start = 320 + 20, 1949 .hsync_end = 320 + 20 + 30, 1950 .htotal = 320 + 20 + 30 + 38, 1951 .vdisplay = 240, 1952 .vsync_start = 240 + 4, 1953 .vsync_end = 240 + 4 + 3, 1954 .vtotal = 240 + 4 + 3 + 15, 1955 .vrefresh = 60, 1956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1957 }; 1958 1959 static const struct panel_desc winstar_wf35ltiacd = { 1960 .modes = &winstar_wf35ltiacd_mode, 1961 .num_modes = 1, 1962 .bpc = 8, 1963 .size = { 1964 .width = 70, 1965 .height = 53, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1968 }; 1969 1970 static const struct of_device_id platform_of_match[] = { 1971 { 1972 .compatible = "ampire,am-480272h3tmqw-t01h", 1973 .data = &ire_am_480272h3tmqw_t01h, 1974 }, { 1975 .compatible = "ampire,am800480r3tmqwa1h", 1976 .data = &ire_am800480r3tmqwa1h, 1977 }, { 1978 .compatible = "auo,b101aw03", 1979 .data = &auo_b101aw03, 1980 }, { 1981 .compatible = "auo,b101ean01", 1982 .data = &auo_b101ean01, 1983 }, { 1984 .compatible = "auo,b101xtn01", 1985 .data = &auo_b101xtn01, 1986 }, { 1987 .compatible = "auo,b116xw03", 1988 .data = &auo_b116xw03, 1989 }, { 1990 .compatible = "auo,b133htn01", 1991 .data = &auo_b133htn01, 1992 }, { 1993 .compatible = "auo,b133xtn01", 1994 .data = &auo_b133xtn01, 1995 }, { 1996 .compatible = "auo,g133han01", 1997 .data = &auo_g133han01, 1998 }, { 1999 .compatible = "auo,g185han01", 2000 .data = &auo_g185han01, 2001 }, { 2002 .compatible = "auo,p320hvn03", 2003 .data = &auo_p320hvn03, 2004 }, { 2005 .compatible = "auo,t215hvn01", 2006 .data = &auo_t215hvn01, 2007 }, { 2008 .compatible = "avic,tm070ddh03", 2009 .data = &avic_tm070ddh03, 2010 }, { 2011 .compatible = "boe,nv101wxmn51", 2012 .data = &boe_nv101wxmn51, 2013 }, { 2014 .compatible = "chunghwa,claa070wp03xg", 2015 .data = &chunghwa_claa070wp03xg, 2016 }, { 2017 .compatible = "chunghwa,claa101wa01a", 2018 .data = &chunghwa_claa101wa01a 2019 }, { 2020 .compatible = "chunghwa,claa101wb01", 2021 .data = &chunghwa_claa101wb01 2022 }, { 2023 .compatible = "edt,et057090dhu", 2024 .data = &edt_et057090dhu, 2025 }, { 2026 .compatible = "edt,et070080dh6", 2027 .data = &edt_etm0700g0dh6, 2028 }, { 2029 .compatible = "edt,etm0700g0dh6", 2030 .data = &edt_etm0700g0dh6, 2031 }, { 2032 .compatible = "foxlink,fl500wvr00-a0t", 2033 .data = &foxlink_fl500wvr00_a0t, 2034 }, { 2035 .compatible = "giantplus,gpg482739qs5", 2036 .data = &giantplus_gpg482739qs5 2037 }, { 2038 .compatible = "hannstar,hsd070pww1", 2039 .data = &hannstar_hsd070pww1, 2040 }, { 2041 .compatible = "hannstar,hsd100pxn1", 2042 .data = &hannstar_hsd100pxn1, 2043 }, { 2044 .compatible = "hit,tx23d38vm0caa", 2045 .data = &hitachi_tx23d38vm0caa 2046 }, { 2047 .compatible = "innolux,at043tn24", 2048 .data = &innolux_at043tn24, 2049 }, { 2050 .compatible = "innolux,at070tn92", 2051 .data = &innolux_at070tn92, 2052 }, { 2053 .compatible ="innolux,g101ice-l01", 2054 .data = &innolux_g101ice_l01 2055 }, { 2056 .compatible ="innolux,g121i1-l01", 2057 .data = &innolux_g121i1_l01 2058 }, { 2059 .compatible = "innolux,g121x1-l03", 2060 .data = &innolux_g121x1_l03, 2061 }, { 2062 .compatible = "innolux,n116bge", 2063 .data = &innolux_n116bge, 2064 }, { 2065 .compatible = "innolux,n156bge-l21", 2066 .data = &innolux_n156bge_l21, 2067 }, { 2068 .compatible = "innolux,zj070na-01p", 2069 .data = &innolux_zj070na_01p, 2070 }, { 2071 .compatible = "kyo,tcg121xglp", 2072 .data = &kyo_tcg121xglp, 2073 }, { 2074 .compatible = "lg,lb070wv8", 2075 .data = &lg_lb070wv8, 2076 }, { 2077 .compatible = "lg,lp079qx1-sp0v", 2078 .data = &lg_lp079qx1_sp0v, 2079 }, { 2080 .compatible = "lg,lp097qx1-spa1", 2081 .data = &lg_lp097qx1_spa1, 2082 }, { 2083 .compatible = "lg,lp120up1", 2084 .data = &lg_lp120up1, 2085 }, { 2086 .compatible = "lg,lp129qe", 2087 .data = &lg_lp129qe, 2088 }, { 2089 .compatible = "nec,nl12880bc20-05", 2090 .data = &nec_nl12880bc20_05, 2091 }, { 2092 .compatible = "nec,nl4827hc19-05b", 2093 .data = &nec_nl4827hc19_05b, 2094 }, { 2095 .compatible = "netron-dy,e231732", 2096 .data = &netron_dy_e231732, 2097 }, { 2098 .compatible = "nlt,nl192108ac18-02d", 2099 .data = &nlt_nl192108ac18_02d, 2100 }, { 2101 .compatible = "nvd,9128", 2102 .data = &nvd_9128, 2103 }, { 2104 .compatible = "okaya,rs800480t-7x0gp", 2105 .data = &okaya_rs800480t_7x0gp, 2106 }, { 2107 .compatible = "olimex,lcd-olinuxino-43-ts", 2108 .data = &olimex_lcd_olinuxino_43ts, 2109 }, { 2110 .compatible = "ontat,yx700wv03", 2111 .data = &ontat_yx700wv03, 2112 }, { 2113 .compatible = "ortustech,com43h4m85ulc", 2114 .data = &ortustech_com43h4m85ulc, 2115 }, { 2116 .compatible = "qiaodian,qd43003c0-40", 2117 .data = &qd43003c0_40, 2118 }, { 2119 .compatible = "samsung,lsn122dl01-c01", 2120 .data = &samsung_lsn122dl01_c01, 2121 }, { 2122 .compatible = "samsung,ltn101nt05", 2123 .data = &samsung_ltn101nt05, 2124 }, { 2125 .compatible = "samsung,ltn140at29-301", 2126 .data = &samsung_ltn140at29_301, 2127 }, { 2128 .compatible = "sharp,lq101k1ly04", 2129 .data = &sharp_lq101k1ly04, 2130 }, { 2131 .compatible = "sharp,lq123p1jx31", 2132 .data = &sharp_lq123p1jx31, 2133 }, { 2134 .compatible = "sharp,lq150x1lg11", 2135 .data = &sharp_lq150x1lg11, 2136 }, { 2137 .compatible = "shelly,sca07010-bfn-lnn", 2138 .data = &shelly_sca07010_bfn_lnn, 2139 }, { 2140 .compatible = "starry,kr122ea0sra", 2141 .data = &starry_kr122ea0sra, 2142 }, { 2143 .compatible = "tianma,tm070jdhg30", 2144 .data = &tianma_tm070jdhg30, 2145 }, { 2146 .compatible = "toshiba,lt089ac29000", 2147 .data = &toshiba_lt089ac29000, 2148 }, { 2149 .compatible = "tpk,f07a-0102", 2150 .data = &tpk_f07a_0102, 2151 }, { 2152 .compatible = "tpk,f10a-0102", 2153 .data = &tpk_f10a_0102, 2154 }, { 2155 .compatible = "urt,umsh-8596md-t", 2156 .data = &urt_umsh_8596md_parallel, 2157 }, { 2158 .compatible = "urt,umsh-8596md-1t", 2159 .data = &urt_umsh_8596md_parallel, 2160 }, { 2161 .compatible = "urt,umsh-8596md-7t", 2162 .data = &urt_umsh_8596md_parallel, 2163 }, { 2164 .compatible = "urt,umsh-8596md-11t", 2165 .data = &urt_umsh_8596md_lvds, 2166 }, { 2167 .compatible = "urt,umsh-8596md-19t", 2168 .data = &urt_umsh_8596md_lvds, 2169 }, { 2170 .compatible = "urt,umsh-8596md-20t", 2171 .data = &urt_umsh_8596md_parallel, 2172 }, { 2173 .compatible = "winstar,wf35ltiacd", 2174 .data = &winstar_wf35ltiacd, 2175 }, { 2176 /* sentinel */ 2177 } 2178 }; 2179 MODULE_DEVICE_TABLE(of, platform_of_match); 2180 2181 static int panel_simple_platform_probe(struct platform_device *pdev) 2182 { 2183 const struct of_device_id *id; 2184 2185 id = of_match_node(platform_of_match, pdev->dev.of_node); 2186 if (!id) 2187 return -ENODEV; 2188 2189 return panel_simple_probe(&pdev->dev, id->data); 2190 } 2191 2192 static int panel_simple_platform_remove(struct platform_device *pdev) 2193 { 2194 return panel_simple_remove(&pdev->dev); 2195 } 2196 2197 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2198 { 2199 panel_simple_shutdown(&pdev->dev); 2200 } 2201 2202 static struct platform_driver panel_simple_platform_driver = { 2203 .driver = { 2204 .name = "panel-simple", 2205 .of_match_table = platform_of_match, 2206 }, 2207 .probe = panel_simple_platform_probe, 2208 .remove = panel_simple_platform_remove, 2209 .shutdown = panel_simple_platform_shutdown, 2210 }; 2211 2212 struct panel_desc_dsi { 2213 struct panel_desc desc; 2214 2215 unsigned long flags; 2216 enum mipi_dsi_pixel_format format; 2217 unsigned int lanes; 2218 }; 2219 2220 static const struct drm_display_mode auo_b080uan01_mode = { 2221 .clock = 154500, 2222 .hdisplay = 1200, 2223 .hsync_start = 1200 + 62, 2224 .hsync_end = 1200 + 62 + 4, 2225 .htotal = 1200 + 62 + 4 + 62, 2226 .vdisplay = 1920, 2227 .vsync_start = 1920 + 9, 2228 .vsync_end = 1920 + 9 + 2, 2229 .vtotal = 1920 + 9 + 2 + 8, 2230 .vrefresh = 60, 2231 }; 2232 2233 static const struct panel_desc_dsi auo_b080uan01 = { 2234 .desc = { 2235 .modes = &auo_b080uan01_mode, 2236 .num_modes = 1, 2237 .bpc = 8, 2238 .size = { 2239 .width = 108, 2240 .height = 272, 2241 }, 2242 }, 2243 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2244 .format = MIPI_DSI_FMT_RGB888, 2245 .lanes = 4, 2246 }; 2247 2248 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2249 .clock = 160000, 2250 .hdisplay = 1200, 2251 .hsync_start = 1200 + 120, 2252 .hsync_end = 1200 + 120 + 20, 2253 .htotal = 1200 + 120 + 20 + 21, 2254 .vdisplay = 1920, 2255 .vsync_start = 1920 + 21, 2256 .vsync_end = 1920 + 21 + 3, 2257 .vtotal = 1920 + 21 + 3 + 18, 2258 .vrefresh = 60, 2259 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2260 }; 2261 2262 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2263 .desc = { 2264 .modes = &boe_tv080wum_nl0_mode, 2265 .num_modes = 1, 2266 .size = { 2267 .width = 107, 2268 .height = 172, 2269 }, 2270 }, 2271 .flags = MIPI_DSI_MODE_VIDEO | 2272 MIPI_DSI_MODE_VIDEO_BURST | 2273 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2274 .format = MIPI_DSI_FMT_RGB888, 2275 .lanes = 4, 2276 }; 2277 2278 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2279 .clock = 71000, 2280 .hdisplay = 800, 2281 .hsync_start = 800 + 32, 2282 .hsync_end = 800 + 32 + 1, 2283 .htotal = 800 + 32 + 1 + 57, 2284 .vdisplay = 1280, 2285 .vsync_start = 1280 + 28, 2286 .vsync_end = 1280 + 28 + 1, 2287 .vtotal = 1280 + 28 + 1 + 14, 2288 .vrefresh = 60, 2289 }; 2290 2291 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2292 .desc = { 2293 .modes = &lg_ld070wx3_sl01_mode, 2294 .num_modes = 1, 2295 .bpc = 8, 2296 .size = { 2297 .width = 94, 2298 .height = 151, 2299 }, 2300 }, 2301 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2302 .format = MIPI_DSI_FMT_RGB888, 2303 .lanes = 4, 2304 }; 2305 2306 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2307 .clock = 67000, 2308 .hdisplay = 720, 2309 .hsync_start = 720 + 12, 2310 .hsync_end = 720 + 12 + 4, 2311 .htotal = 720 + 12 + 4 + 112, 2312 .vdisplay = 1280, 2313 .vsync_start = 1280 + 8, 2314 .vsync_end = 1280 + 8 + 4, 2315 .vtotal = 1280 + 8 + 4 + 12, 2316 .vrefresh = 60, 2317 }; 2318 2319 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2320 .desc = { 2321 .modes = &lg_lh500wx1_sd03_mode, 2322 .num_modes = 1, 2323 .bpc = 8, 2324 .size = { 2325 .width = 62, 2326 .height = 110, 2327 }, 2328 }, 2329 .flags = MIPI_DSI_MODE_VIDEO, 2330 .format = MIPI_DSI_FMT_RGB888, 2331 .lanes = 4, 2332 }; 2333 2334 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2335 .clock = 157200, 2336 .hdisplay = 1920, 2337 .hsync_start = 1920 + 154, 2338 .hsync_end = 1920 + 154 + 16, 2339 .htotal = 1920 + 154 + 16 + 32, 2340 .vdisplay = 1200, 2341 .vsync_start = 1200 + 17, 2342 .vsync_end = 1200 + 17 + 2, 2343 .vtotal = 1200 + 17 + 2 + 16, 2344 .vrefresh = 60, 2345 }; 2346 2347 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2348 .desc = { 2349 .modes = &panasonic_vvx10f004b00_mode, 2350 .num_modes = 1, 2351 .bpc = 8, 2352 .size = { 2353 .width = 217, 2354 .height = 136, 2355 }, 2356 }, 2357 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2358 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2359 .format = MIPI_DSI_FMT_RGB888, 2360 .lanes = 4, 2361 }; 2362 2363 static const struct of_device_id dsi_of_match[] = { 2364 { 2365 .compatible = "auo,b080uan01", 2366 .data = &auo_b080uan01 2367 }, { 2368 .compatible = "boe,tv080wum-nl0", 2369 .data = &boe_tv080wum_nl0 2370 }, { 2371 .compatible = "lg,ld070wx3-sl01", 2372 .data = &lg_ld070wx3_sl01 2373 }, { 2374 .compatible = "lg,lh500wx1-sd03", 2375 .data = &lg_lh500wx1_sd03 2376 }, { 2377 .compatible = "panasonic,vvx10f004b00", 2378 .data = &panasonic_vvx10f004b00 2379 }, { 2380 /* sentinel */ 2381 } 2382 }; 2383 MODULE_DEVICE_TABLE(of, dsi_of_match); 2384 2385 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2386 { 2387 const struct panel_desc_dsi *desc; 2388 const struct of_device_id *id; 2389 int err; 2390 2391 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2392 if (!id) 2393 return -ENODEV; 2394 2395 desc = id->data; 2396 2397 err = panel_simple_probe(&dsi->dev, &desc->desc); 2398 if (err < 0) 2399 return err; 2400 2401 dsi->mode_flags = desc->flags; 2402 dsi->format = desc->format; 2403 dsi->lanes = desc->lanes; 2404 2405 return mipi_dsi_attach(dsi); 2406 } 2407 2408 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2409 { 2410 int err; 2411 2412 err = mipi_dsi_detach(dsi); 2413 if (err < 0) 2414 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2415 2416 return panel_simple_remove(&dsi->dev); 2417 } 2418 2419 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2420 { 2421 panel_simple_shutdown(&dsi->dev); 2422 } 2423 2424 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2425 .driver = { 2426 .name = "panel-simple-dsi", 2427 .of_match_table = dsi_of_match, 2428 }, 2429 .probe = panel_simple_dsi_probe, 2430 .remove = panel_simple_dsi_remove, 2431 .shutdown = panel_simple_dsi_shutdown, 2432 }; 2433 2434 static int __init panel_simple_init(void) 2435 { 2436 int err; 2437 2438 err = platform_driver_register(&panel_simple_platform_driver); 2439 if (err < 0) 2440 return err; 2441 2442 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2443 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2444 if (err < 0) 2445 return err; 2446 } 2447 2448 return 0; 2449 } 2450 module_init(panel_simple_init); 2451 2452 static void __exit panel_simple_exit(void) 2453 { 2454 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2455 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2456 2457 platform_driver_unregister(&panel_simple_platform_driver); 2458 } 2459 module_exit(panel_simple_exit); 2460 2461 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2462 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2463 MODULE_LICENSE("GPL and additional rights"); 2464