1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * struct panel_desc - Describes a simple panel. 43 */ 44 struct panel_desc { 45 /** 46 * @modes: Pointer to array of fixed modes appropriate for this panel. 47 * 48 * If only one mode then this can just be the address of the mode. 49 * NOTE: cannot be used with "timings" and also if this is specified 50 * then you cannot override the mode in the device tree. 51 */ 52 const struct drm_display_mode *modes; 53 54 /** @num_modes: Number of elements in modes array. */ 55 unsigned int num_modes; 56 57 /** 58 * @timings: Pointer to array of display timings 59 * 60 * NOTE: cannot be used with "modes" and also these will be used to 61 * validate a device tree override if one is present. 62 */ 63 const struct display_timing *timings; 64 65 /** @num_timings: Number of elements in timings array. */ 66 unsigned int num_timings; 67 68 /** @bpc: Bits per color. */ 69 unsigned int bpc; 70 71 /** @size: Structure containing the physical size of this panel. */ 72 struct { 73 /** 74 * @size.width: Width (in mm) of the active display area. 75 */ 76 unsigned int width; 77 78 /** 79 * @size.height: Height (in mm) of the active display area. 80 */ 81 unsigned int height; 82 } size; 83 84 /** @delay: Structure containing various delay values for this panel. */ 85 struct { 86 /** 87 * @delay.prepare: Time for the panel to become ready. 88 * 89 * The time (in milliseconds) that it takes for the panel to 90 * become ready and start receiving video data 91 */ 92 unsigned int prepare; 93 94 /** 95 * @delay.enable: Time for the panel to display a valid frame. 96 * 97 * The time (in milliseconds) that it takes for the panel to 98 * display the first valid frame after starting to receive 99 * video data. 100 */ 101 unsigned int enable; 102 103 /** 104 * @delay.disable: Time for the panel to turn the display off. 105 * 106 * The time (in milliseconds) that it takes for the panel to 107 * turn the display off (no content is visible). 108 */ 109 unsigned int disable; 110 111 /** 112 * @delay.unprepare: Time to power down completely. 113 * 114 * The time (in milliseconds) that it takes for the panel 115 * to power itself down completely. 116 * 117 * This time is used to prevent a future "prepare" from 118 * starting until at least this many milliseconds has passed. 119 * If at prepare time less time has passed since unprepare 120 * finished, the driver waits for the remaining time. 121 */ 122 unsigned int unprepare; 123 } delay; 124 125 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 126 u32 bus_format; 127 128 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 129 u32 bus_flags; 130 131 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 132 int connector_type; 133 }; 134 135 struct panel_simple { 136 struct drm_panel base; 137 bool enabled; 138 139 bool prepared; 140 141 ktime_t prepared_time; 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 struct edid *edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (!p->enabled) 291 return 0; 292 293 if (p->desc->delay.disable) 294 msleep(p->desc->delay.disable); 295 296 p->enabled = false; 297 298 return 0; 299 } 300 301 static int panel_simple_suspend(struct device *dev) 302 { 303 struct panel_simple *p = dev_get_drvdata(dev); 304 305 gpiod_set_value_cansleep(p->enable_gpio, 0); 306 regulator_disable(p->supply); 307 p->unprepared_time = ktime_get(); 308 309 kfree(p->edid); 310 p->edid = NULL; 311 312 return 0; 313 } 314 315 static int panel_simple_unprepare(struct drm_panel *panel) 316 { 317 struct panel_simple *p = to_panel_simple(panel); 318 int ret; 319 320 /* Unpreparing when already unprepared is a no-op */ 321 if (!p->prepared) 322 return 0; 323 324 pm_runtime_mark_last_busy(panel->dev); 325 ret = pm_runtime_put_autosuspend(panel->dev); 326 if (ret < 0) 327 return ret; 328 p->prepared = false; 329 330 return 0; 331 } 332 333 static int panel_simple_resume(struct device *dev) 334 { 335 struct panel_simple *p = dev_get_drvdata(dev); 336 int err; 337 338 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 339 340 err = regulator_enable(p->supply); 341 if (err < 0) { 342 dev_err(dev, "failed to enable supply: %d\n", err); 343 return err; 344 } 345 346 gpiod_set_value_cansleep(p->enable_gpio, 1); 347 348 if (p->desc->delay.prepare) 349 msleep(p->desc->delay.prepare); 350 351 p->prepared_time = ktime_get(); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* set up connector's "panel orientation" property */ 415 drm_connector_set_panel_orientation(connector, p->orientation); 416 417 return num; 418 } 419 420 static int panel_simple_get_timings(struct drm_panel *panel, 421 unsigned int num_timings, 422 struct display_timing *timings) 423 { 424 struct panel_simple *p = to_panel_simple(panel); 425 unsigned int i; 426 427 if (p->desc->num_timings < num_timings) 428 num_timings = p->desc->num_timings; 429 430 if (timings) 431 for (i = 0; i < num_timings; i++) 432 timings[i] = p->desc->timings[i]; 433 434 return p->desc->num_timings; 435 } 436 437 static const struct drm_panel_funcs panel_simple_funcs = { 438 .disable = panel_simple_disable, 439 .unprepare = panel_simple_unprepare, 440 .prepare = panel_simple_prepare, 441 .enable = panel_simple_enable, 442 .get_modes = panel_simple_get_modes, 443 .get_timings = panel_simple_get_timings, 444 }; 445 446 static struct panel_desc panel_dpi; 447 448 static int panel_dpi_probe(struct device *dev, 449 struct panel_simple *panel) 450 { 451 struct display_timing *timing; 452 const struct device_node *np; 453 struct panel_desc *desc; 454 unsigned int bus_flags; 455 struct videomode vm; 456 int ret; 457 458 np = dev->of_node; 459 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 460 if (!desc) 461 return -ENOMEM; 462 463 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 464 if (!timing) 465 return -ENOMEM; 466 467 ret = of_get_display_timing(np, "panel-timing", timing); 468 if (ret < 0) { 469 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 470 np); 471 return ret; 472 } 473 474 desc->timings = timing; 475 desc->num_timings = 1; 476 477 of_property_read_u32(np, "width-mm", &desc->size.width); 478 of_property_read_u32(np, "height-mm", &desc->size.height); 479 480 /* Extract bus_flags from display_timing */ 481 bus_flags = 0; 482 vm.flags = timing->flags; 483 drm_bus_flags_from_videomode(&vm, &bus_flags); 484 desc->bus_flags = bus_flags; 485 486 /* We do not know the connector for the DT node, so guess it */ 487 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 488 489 panel->desc = desc; 490 491 return 0; 492 } 493 494 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 495 (to_check->field.typ >= bounds->field.min && \ 496 to_check->field.typ <= bounds->field.max) 497 static void panel_simple_parse_panel_timing_node(struct device *dev, 498 struct panel_simple *panel, 499 const struct display_timing *ot) 500 { 501 const struct panel_desc *desc = panel->desc; 502 struct videomode vm; 503 unsigned int i; 504 505 if (WARN_ON(desc->num_modes)) { 506 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 507 return; 508 } 509 if (WARN_ON(!desc->num_timings)) { 510 dev_err(dev, "Reject override mode: no timings specified\n"); 511 return; 512 } 513 514 for (i = 0; i < panel->desc->num_timings; i++) { 515 const struct display_timing *dt = &panel->desc->timings[i]; 516 517 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 518 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 519 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 520 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 521 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 522 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 523 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 524 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 525 continue; 526 527 if (ot->flags != dt->flags) 528 continue; 529 530 videomode_from_timing(ot, &vm); 531 drm_display_mode_from_videomode(&vm, &panel->override_mode); 532 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 533 DRM_MODE_TYPE_PREFERRED; 534 break; 535 } 536 537 if (WARN_ON(!panel->override_mode.type)) 538 dev_err(dev, "Reject override mode: No display_timing found\n"); 539 } 540 541 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 542 { 543 struct panel_simple *panel; 544 struct display_timing dt; 545 struct device_node *ddc; 546 int connector_type; 547 u32 bus_flags; 548 int err; 549 550 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 551 if (!panel) 552 return -ENOMEM; 553 554 panel->enabled = false; 555 panel->prepared_time = 0; 556 panel->desc = desc; 557 558 panel->supply = devm_regulator_get(dev, "power"); 559 if (IS_ERR(panel->supply)) 560 return PTR_ERR(panel->supply); 561 562 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 563 GPIOD_OUT_LOW); 564 if (IS_ERR(panel->enable_gpio)) { 565 err = PTR_ERR(panel->enable_gpio); 566 if (err != -EPROBE_DEFER) 567 dev_err(dev, "failed to request GPIO: %d\n", err); 568 return err; 569 } 570 571 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 572 if (err) { 573 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 574 return err; 575 } 576 577 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 578 if (ddc) { 579 panel->ddc = of_find_i2c_adapter_by_node(ddc); 580 of_node_put(ddc); 581 582 if (!panel->ddc) 583 return -EPROBE_DEFER; 584 } 585 586 if (desc == &panel_dpi) { 587 /* Handle the generic panel-dpi binding */ 588 err = panel_dpi_probe(dev, panel); 589 if (err) 590 goto free_ddc; 591 } else { 592 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 593 panel_simple_parse_panel_timing_node(dev, panel, &dt); 594 } 595 596 connector_type = desc->connector_type; 597 /* Catch common mistakes for panels. */ 598 switch (connector_type) { 599 case 0: 600 dev_warn(dev, "Specify missing connector_type\n"); 601 connector_type = DRM_MODE_CONNECTOR_DPI; 602 break; 603 case DRM_MODE_CONNECTOR_LVDS: 604 WARN_ON(desc->bus_flags & 605 ~(DRM_BUS_FLAG_DE_LOW | 606 DRM_BUS_FLAG_DE_HIGH | 607 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 608 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 609 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 610 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 611 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 612 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 613 desc->bpc != 6); 614 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 615 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 616 desc->bpc != 8); 617 break; 618 case DRM_MODE_CONNECTOR_eDP: 619 dev_warn(dev, "eDP panels moved to panel-edp\n"); 620 err = -EINVAL; 621 goto free_ddc; 622 case DRM_MODE_CONNECTOR_DSI: 623 if (desc->bpc != 6 && desc->bpc != 8) 624 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 625 break; 626 case DRM_MODE_CONNECTOR_DPI: 627 bus_flags = DRM_BUS_FLAG_DE_LOW | 628 DRM_BUS_FLAG_DE_HIGH | 629 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 630 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 631 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 632 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 633 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 634 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 635 if (desc->bus_flags & ~bus_flags) 636 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 637 if (!(desc->bus_flags & bus_flags)) 638 dev_warn(dev, "Specify missing bus_flags\n"); 639 if (desc->bus_format == 0) 640 dev_warn(dev, "Specify missing bus_format\n"); 641 if (desc->bpc != 6 && desc->bpc != 8) 642 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 643 break; 644 default: 645 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 646 connector_type = DRM_MODE_CONNECTOR_DPI; 647 break; 648 } 649 650 dev_set_drvdata(dev, panel); 651 652 /* 653 * We use runtime PM for prepare / unprepare since those power the panel 654 * on and off and those can be very slow operations. This is important 655 * to optimize powering the panel on briefly to read the EDID before 656 * fully enabling the panel. 657 */ 658 pm_runtime_enable(dev); 659 pm_runtime_set_autosuspend_delay(dev, 1000); 660 pm_runtime_use_autosuspend(dev); 661 662 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 663 664 err = drm_panel_of_backlight(&panel->base); 665 if (err) 666 goto disable_pm_runtime; 667 668 drm_panel_add(&panel->base); 669 670 return 0; 671 672 disable_pm_runtime: 673 pm_runtime_dont_use_autosuspend(dev); 674 pm_runtime_disable(dev); 675 free_ddc: 676 if (panel->ddc) 677 put_device(&panel->ddc->dev); 678 679 return err; 680 } 681 682 static int panel_simple_remove(struct device *dev) 683 { 684 struct panel_simple *panel = dev_get_drvdata(dev); 685 686 drm_panel_remove(&panel->base); 687 drm_panel_disable(&panel->base); 688 drm_panel_unprepare(&panel->base); 689 690 pm_runtime_dont_use_autosuspend(dev); 691 pm_runtime_disable(dev); 692 if (panel->ddc) 693 put_device(&panel->ddc->dev); 694 695 return 0; 696 } 697 698 static void panel_simple_shutdown(struct device *dev) 699 { 700 struct panel_simple *panel = dev_get_drvdata(dev); 701 702 drm_panel_disable(&panel->base); 703 drm_panel_unprepare(&panel->base); 704 } 705 706 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 707 .clock = 71100, 708 .hdisplay = 1280, 709 .hsync_start = 1280 + 40, 710 .hsync_end = 1280 + 40 + 80, 711 .htotal = 1280 + 40 + 80 + 40, 712 .vdisplay = 800, 713 .vsync_start = 800 + 3, 714 .vsync_end = 800 + 3 + 10, 715 .vtotal = 800 + 3 + 10 + 10, 716 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 717 }; 718 719 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 720 .modes = &ire_am_1280800n3tzqw_t00h_mode, 721 .num_modes = 1, 722 .bpc = 6, 723 .size = { 724 .width = 217, 725 .height = 136, 726 }, 727 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 729 .connector_type = DRM_MODE_CONNECTOR_LVDS, 730 }; 731 732 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 733 .clock = 9000, 734 .hdisplay = 480, 735 .hsync_start = 480 + 2, 736 .hsync_end = 480 + 2 + 41, 737 .htotal = 480 + 2 + 41 + 2, 738 .vdisplay = 272, 739 .vsync_start = 272 + 2, 740 .vsync_end = 272 + 2 + 10, 741 .vtotal = 272 + 2 + 10 + 2, 742 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 743 }; 744 745 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 746 .modes = &ire_am_480272h3tmqw_t01h_mode, 747 .num_modes = 1, 748 .bpc = 8, 749 .size = { 750 .width = 105, 751 .height = 67, 752 }, 753 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 754 }; 755 756 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 757 .clock = 33333, 758 .hdisplay = 800, 759 .hsync_start = 800 + 0, 760 .hsync_end = 800 + 0 + 255, 761 .htotal = 800 + 0 + 255 + 0, 762 .vdisplay = 480, 763 .vsync_start = 480 + 2, 764 .vsync_end = 480 + 2 + 45, 765 .vtotal = 480 + 2 + 45 + 0, 766 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 767 }; 768 769 static const struct panel_desc ampire_am800480r3tmqwa1h = { 770 .modes = &ire_am800480r3tmqwa1h_mode, 771 .num_modes = 1, 772 .bpc = 6, 773 .size = { 774 .width = 152, 775 .height = 91, 776 }, 777 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 778 }; 779 780 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 781 .pixelclock = { 26400000, 33300000, 46800000 }, 782 .hactive = { 800, 800, 800 }, 783 .hfront_porch = { 16, 210, 354 }, 784 .hback_porch = { 45, 36, 6 }, 785 .hsync_len = { 1, 10, 40 }, 786 .vactive = { 480, 480, 480 }, 787 .vfront_porch = { 7, 22, 147 }, 788 .vback_porch = { 22, 13, 3 }, 789 .vsync_len = { 1, 10, 20 }, 790 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 791 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 792 }; 793 794 static const struct panel_desc armadeus_st0700_adapt = { 795 .timings = &santek_st0700i5y_rbslw_f_timing, 796 .num_timings = 1, 797 .bpc = 6, 798 .size = { 799 .width = 154, 800 .height = 86, 801 }, 802 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 803 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 804 }; 805 806 static const struct drm_display_mode auo_b101aw03_mode = { 807 .clock = 51450, 808 .hdisplay = 1024, 809 .hsync_start = 1024 + 156, 810 .hsync_end = 1024 + 156 + 8, 811 .htotal = 1024 + 156 + 8 + 156, 812 .vdisplay = 600, 813 .vsync_start = 600 + 16, 814 .vsync_end = 600 + 16 + 6, 815 .vtotal = 600 + 16 + 6 + 16, 816 }; 817 818 static const struct panel_desc auo_b101aw03 = { 819 .modes = &auo_b101aw03_mode, 820 .num_modes = 1, 821 .bpc = 6, 822 .size = { 823 .width = 223, 824 .height = 125, 825 }, 826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 827 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 828 .connector_type = DRM_MODE_CONNECTOR_LVDS, 829 }; 830 831 static const struct drm_display_mode auo_b101xtn01_mode = { 832 .clock = 72000, 833 .hdisplay = 1366, 834 .hsync_start = 1366 + 20, 835 .hsync_end = 1366 + 20 + 70, 836 .htotal = 1366 + 20 + 70, 837 .vdisplay = 768, 838 .vsync_start = 768 + 14, 839 .vsync_end = 768 + 14 + 42, 840 .vtotal = 768 + 14 + 42, 841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 842 }; 843 844 static const struct panel_desc auo_b101xtn01 = { 845 .modes = &auo_b101xtn01_mode, 846 .num_modes = 1, 847 .bpc = 6, 848 .size = { 849 .width = 223, 850 .height = 125, 851 }, 852 }; 853 854 static const struct display_timing auo_g070vvn01_timings = { 855 .pixelclock = { 33300000, 34209000, 45000000 }, 856 .hactive = { 800, 800, 800 }, 857 .hfront_porch = { 20, 40, 200 }, 858 .hback_porch = { 87, 40, 1 }, 859 .hsync_len = { 1, 48, 87 }, 860 .vactive = { 480, 480, 480 }, 861 .vfront_porch = { 5, 13, 200 }, 862 .vback_porch = { 31, 31, 29 }, 863 .vsync_len = { 1, 1, 3 }, 864 }; 865 866 static const struct panel_desc auo_g070vvn01 = { 867 .timings = &auo_g070vvn01_timings, 868 .num_timings = 1, 869 .bpc = 8, 870 .size = { 871 .width = 152, 872 .height = 91, 873 }, 874 .delay = { 875 .prepare = 200, 876 .enable = 50, 877 .disable = 50, 878 .unprepare = 1000, 879 }, 880 }; 881 882 static const struct drm_display_mode auo_g101evn010_mode = { 883 .clock = 68930, 884 .hdisplay = 1280, 885 .hsync_start = 1280 + 82, 886 .hsync_end = 1280 + 82 + 2, 887 .htotal = 1280 + 82 + 2 + 84, 888 .vdisplay = 800, 889 .vsync_start = 800 + 8, 890 .vsync_end = 800 + 8 + 2, 891 .vtotal = 800 + 8 + 2 + 6, 892 }; 893 894 static const struct panel_desc auo_g101evn010 = { 895 .modes = &auo_g101evn010_mode, 896 .num_modes = 1, 897 .bpc = 6, 898 .size = { 899 .width = 216, 900 .height = 135, 901 }, 902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 904 }; 905 906 static const struct drm_display_mode auo_g104sn02_mode = { 907 .clock = 40000, 908 .hdisplay = 800, 909 .hsync_start = 800 + 40, 910 .hsync_end = 800 + 40 + 216, 911 .htotal = 800 + 40 + 216 + 128, 912 .vdisplay = 600, 913 .vsync_start = 600 + 10, 914 .vsync_end = 600 + 10 + 35, 915 .vtotal = 600 + 10 + 35 + 2, 916 }; 917 918 static const struct panel_desc auo_g104sn02 = { 919 .modes = &auo_g104sn02_mode, 920 .num_modes = 1, 921 .bpc = 8, 922 .size = { 923 .width = 211, 924 .height = 158, 925 }, 926 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 928 }; 929 930 static const struct drm_display_mode auo_g121ean01_mode = { 931 .clock = 66700, 932 .hdisplay = 1280, 933 .hsync_start = 1280 + 58, 934 .hsync_end = 1280 + 58 + 8, 935 .htotal = 1280 + 58 + 8 + 70, 936 .vdisplay = 800, 937 .vsync_start = 800 + 6, 938 .vsync_end = 800 + 6 + 4, 939 .vtotal = 800 + 6 + 4 + 10, 940 }; 941 942 static const struct panel_desc auo_g121ean01 = { 943 .modes = &auo_g121ean01_mode, 944 .num_modes = 1, 945 .bpc = 8, 946 .size = { 947 .width = 261, 948 .height = 163, 949 }, 950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952 }; 953 954 static const struct display_timing auo_g133han01_timings = { 955 .pixelclock = { 134000000, 141200000, 149000000 }, 956 .hactive = { 1920, 1920, 1920 }, 957 .hfront_porch = { 39, 58, 77 }, 958 .hback_porch = { 59, 88, 117 }, 959 .hsync_len = { 28, 42, 56 }, 960 .vactive = { 1080, 1080, 1080 }, 961 .vfront_porch = { 3, 8, 11 }, 962 .vback_porch = { 5, 14, 19 }, 963 .vsync_len = { 4, 14, 19 }, 964 }; 965 966 static const struct panel_desc auo_g133han01 = { 967 .timings = &auo_g133han01_timings, 968 .num_timings = 1, 969 .bpc = 8, 970 .size = { 971 .width = 293, 972 .height = 165, 973 }, 974 .delay = { 975 .prepare = 200, 976 .enable = 50, 977 .disable = 50, 978 .unprepare = 1000, 979 }, 980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 981 .connector_type = DRM_MODE_CONNECTOR_LVDS, 982 }; 983 984 static const struct drm_display_mode auo_g156xtn01_mode = { 985 .clock = 76000, 986 .hdisplay = 1366, 987 .hsync_start = 1366 + 33, 988 .hsync_end = 1366 + 33 + 67, 989 .htotal = 1560, 990 .vdisplay = 768, 991 .vsync_start = 768 + 4, 992 .vsync_end = 768 + 4 + 4, 993 .vtotal = 806, 994 }; 995 996 static const struct panel_desc auo_g156xtn01 = { 997 .modes = &auo_g156xtn01_mode, 998 .num_modes = 1, 999 .bpc = 8, 1000 .size = { 1001 .width = 344, 1002 .height = 194, 1003 }, 1004 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1006 }; 1007 1008 static const struct display_timing auo_g185han01_timings = { 1009 .pixelclock = { 120000000, 144000000, 175000000 }, 1010 .hactive = { 1920, 1920, 1920 }, 1011 .hfront_porch = { 36, 120, 148 }, 1012 .hback_porch = { 24, 88, 108 }, 1013 .hsync_len = { 20, 48, 64 }, 1014 .vactive = { 1080, 1080, 1080 }, 1015 .vfront_porch = { 6, 10, 40 }, 1016 .vback_porch = { 2, 5, 20 }, 1017 .vsync_len = { 2, 5, 20 }, 1018 }; 1019 1020 static const struct panel_desc auo_g185han01 = { 1021 .timings = &auo_g185han01_timings, 1022 .num_timings = 1, 1023 .bpc = 8, 1024 .size = { 1025 .width = 409, 1026 .height = 230, 1027 }, 1028 .delay = { 1029 .prepare = 50, 1030 .enable = 200, 1031 .disable = 110, 1032 .unprepare = 1000, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g190ean01_timings = { 1039 .pixelclock = { 90000000, 108000000, 135000000 }, 1040 .hactive = { 1280, 1280, 1280 }, 1041 .hfront_porch = { 126, 184, 1266 }, 1042 .hback_porch = { 84, 122, 844 }, 1043 .hsync_len = { 70, 102, 704 }, 1044 .vactive = { 1024, 1024, 1024 }, 1045 .vfront_porch = { 4, 26, 76 }, 1046 .vback_porch = { 2, 8, 25 }, 1047 .vsync_len = { 2, 8, 25 }, 1048 }; 1049 1050 static const struct panel_desc auo_g190ean01 = { 1051 .timings = &auo_g190ean01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 376, 1056 .height = 301, 1057 }, 1058 .delay = { 1059 .prepare = 50, 1060 .enable = 200, 1061 .disable = 110, 1062 .unprepare = 1000, 1063 }, 1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1066 }; 1067 1068 static const struct display_timing auo_p320hvn03_timings = { 1069 .pixelclock = { 106000000, 148500000, 164000000 }, 1070 .hactive = { 1920, 1920, 1920 }, 1071 .hfront_porch = { 25, 50, 130 }, 1072 .hback_porch = { 25, 50, 130 }, 1073 .hsync_len = { 20, 40, 105 }, 1074 .vactive = { 1080, 1080, 1080 }, 1075 .vfront_porch = { 8, 17, 150 }, 1076 .vback_porch = { 8, 17, 150 }, 1077 .vsync_len = { 4, 11, 100 }, 1078 }; 1079 1080 static const struct panel_desc auo_p320hvn03 = { 1081 .timings = &auo_p320hvn03_timings, 1082 .num_timings = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 698, 1086 .height = 393, 1087 }, 1088 .delay = { 1089 .prepare = 1, 1090 .enable = 450, 1091 .unprepare = 500, 1092 }, 1093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1094 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1095 }; 1096 1097 static const struct drm_display_mode auo_t215hvn01_mode = { 1098 .clock = 148800, 1099 .hdisplay = 1920, 1100 .hsync_start = 1920 + 88, 1101 .hsync_end = 1920 + 88 + 44, 1102 .htotal = 1920 + 88 + 44 + 148, 1103 .vdisplay = 1080, 1104 .vsync_start = 1080 + 4, 1105 .vsync_end = 1080 + 4 + 5, 1106 .vtotal = 1080 + 4 + 5 + 36, 1107 }; 1108 1109 static const struct panel_desc auo_t215hvn01 = { 1110 .modes = &auo_t215hvn01_mode, 1111 .num_modes = 1, 1112 .bpc = 8, 1113 .size = { 1114 .width = 430, 1115 .height = 270, 1116 }, 1117 .delay = { 1118 .disable = 5, 1119 .unprepare = 1000, 1120 } 1121 }; 1122 1123 static const struct drm_display_mode avic_tm070ddh03_mode = { 1124 .clock = 51200, 1125 .hdisplay = 1024, 1126 .hsync_start = 1024 + 160, 1127 .hsync_end = 1024 + 160 + 4, 1128 .htotal = 1024 + 160 + 4 + 156, 1129 .vdisplay = 600, 1130 .vsync_start = 600 + 17, 1131 .vsync_end = 600 + 17 + 1, 1132 .vtotal = 600 + 17 + 1 + 17, 1133 }; 1134 1135 static const struct panel_desc avic_tm070ddh03 = { 1136 .modes = &avic_tm070ddh03_mode, 1137 .num_modes = 1, 1138 .bpc = 8, 1139 .size = { 1140 .width = 154, 1141 .height = 90, 1142 }, 1143 .delay = { 1144 .prepare = 20, 1145 .enable = 200, 1146 .disable = 200, 1147 }, 1148 }; 1149 1150 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1151 .clock = 30000, 1152 .hdisplay = 800, 1153 .hsync_start = 800 + 40, 1154 .hsync_end = 800 + 40 + 48, 1155 .htotal = 800 + 40 + 48 + 40, 1156 .vdisplay = 480, 1157 .vsync_start = 480 + 13, 1158 .vsync_end = 480 + 13 + 3, 1159 .vtotal = 480 + 13 + 3 + 29, 1160 }; 1161 1162 static const struct panel_desc bananapi_s070wv20_ct16 = { 1163 .modes = &bananapi_s070wv20_ct16_mode, 1164 .num_modes = 1, 1165 .bpc = 6, 1166 .size = { 1167 .width = 154, 1168 .height = 86, 1169 }, 1170 }; 1171 1172 static const struct drm_display_mode boe_hv070wsa_mode = { 1173 .clock = 42105, 1174 .hdisplay = 1024, 1175 .hsync_start = 1024 + 30, 1176 .hsync_end = 1024 + 30 + 30, 1177 .htotal = 1024 + 30 + 30 + 30, 1178 .vdisplay = 600, 1179 .vsync_start = 600 + 10, 1180 .vsync_end = 600 + 10 + 10, 1181 .vtotal = 600 + 10 + 10 + 10, 1182 }; 1183 1184 static const struct panel_desc boe_hv070wsa = { 1185 .modes = &boe_hv070wsa_mode, 1186 .num_modes = 1, 1187 .bpc = 8, 1188 .size = { 1189 .width = 154, 1190 .height = 90, 1191 }, 1192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1193 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1195 }; 1196 1197 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1198 .clock = 9000, 1199 .hdisplay = 480, 1200 .hsync_start = 480 + 5, 1201 .hsync_end = 480 + 5 + 5, 1202 .htotal = 480 + 5 + 5 + 40, 1203 .vdisplay = 272, 1204 .vsync_start = 272 + 8, 1205 .vsync_end = 272 + 8 + 8, 1206 .vtotal = 272 + 8 + 8 + 8, 1207 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1208 }; 1209 1210 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1211 .modes = &cdtech_s043wq26h_ct7_mode, 1212 .num_modes = 1, 1213 .bpc = 8, 1214 .size = { 1215 .width = 95, 1216 .height = 54, 1217 }, 1218 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1219 }; 1220 1221 /* S070PWS19HP-FC21 2017/04/22 */ 1222 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1223 .clock = 51200, 1224 .hdisplay = 1024, 1225 .hsync_start = 1024 + 160, 1226 .hsync_end = 1024 + 160 + 20, 1227 .htotal = 1024 + 160 + 20 + 140, 1228 .vdisplay = 600, 1229 .vsync_start = 600 + 12, 1230 .vsync_end = 600 + 12 + 3, 1231 .vtotal = 600 + 12 + 3 + 20, 1232 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1233 }; 1234 1235 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1236 .modes = &cdtech_s070pws19hp_fc21_mode, 1237 .num_modes = 1, 1238 .bpc = 6, 1239 .size = { 1240 .width = 154, 1241 .height = 86, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1244 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1245 .connector_type = DRM_MODE_CONNECTOR_DPI, 1246 }; 1247 1248 /* S070SWV29HG-DC44 2017/09/21 */ 1249 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1250 .clock = 33300, 1251 .hdisplay = 800, 1252 .hsync_start = 800 + 210, 1253 .hsync_end = 800 + 210 + 2, 1254 .htotal = 800 + 210 + 2 + 44, 1255 .vdisplay = 480, 1256 .vsync_start = 480 + 22, 1257 .vsync_end = 480 + 22 + 2, 1258 .vtotal = 480 + 22 + 2 + 21, 1259 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1260 }; 1261 1262 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1263 .modes = &cdtech_s070swv29hg_dc44_mode, 1264 .num_modes = 1, 1265 .bpc = 6, 1266 .size = { 1267 .width = 154, 1268 .height = 86, 1269 }, 1270 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1271 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1272 .connector_type = DRM_MODE_CONNECTOR_DPI, 1273 }; 1274 1275 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1276 .clock = 35000, 1277 .hdisplay = 800, 1278 .hsync_start = 800 + 40, 1279 .hsync_end = 800 + 40 + 40, 1280 .htotal = 800 + 40 + 40 + 48, 1281 .vdisplay = 480, 1282 .vsync_start = 480 + 29, 1283 .vsync_end = 480 + 29 + 13, 1284 .vtotal = 480 + 29 + 13 + 3, 1285 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1286 }; 1287 1288 static const struct panel_desc cdtech_s070wv95_ct16 = { 1289 .modes = &cdtech_s070wv95_ct16_mode, 1290 .num_modes = 1, 1291 .bpc = 8, 1292 .size = { 1293 .width = 154, 1294 .height = 85, 1295 }, 1296 }; 1297 1298 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1299 .pixelclock = { 68900000, 71100000, 73400000 }, 1300 .hactive = { 1280, 1280, 1280 }, 1301 .hfront_porch = { 65, 80, 95 }, 1302 .hback_porch = { 64, 79, 94 }, 1303 .hsync_len = { 1, 1, 1 }, 1304 .vactive = { 800, 800, 800 }, 1305 .vfront_porch = { 7, 11, 14 }, 1306 .vback_porch = { 7, 11, 14 }, 1307 .vsync_len = { 1, 1, 1 }, 1308 .flags = DISPLAY_FLAGS_DE_HIGH, 1309 }; 1310 1311 static const struct panel_desc chefree_ch101olhlwh_002 = { 1312 .timings = &chefree_ch101olhlwh_002_timing, 1313 .num_timings = 1, 1314 .bpc = 8, 1315 .size = { 1316 .width = 217, 1317 .height = 135, 1318 }, 1319 .delay = { 1320 .enable = 200, 1321 .disable = 200, 1322 }, 1323 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1326 }; 1327 1328 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1329 .clock = 66770, 1330 .hdisplay = 800, 1331 .hsync_start = 800 + 49, 1332 .hsync_end = 800 + 49 + 33, 1333 .htotal = 800 + 49 + 33 + 17, 1334 .vdisplay = 1280, 1335 .vsync_start = 1280 + 1, 1336 .vsync_end = 1280 + 1 + 7, 1337 .vtotal = 1280 + 1 + 7 + 15, 1338 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1339 }; 1340 1341 static const struct panel_desc chunghwa_claa070wp03xg = { 1342 .modes = &chunghwa_claa070wp03xg_mode, 1343 .num_modes = 1, 1344 .bpc = 6, 1345 .size = { 1346 .width = 94, 1347 .height = 150, 1348 }, 1349 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1350 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1351 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1352 }; 1353 1354 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1355 .clock = 72070, 1356 .hdisplay = 1366, 1357 .hsync_start = 1366 + 58, 1358 .hsync_end = 1366 + 58 + 58, 1359 .htotal = 1366 + 58 + 58 + 58, 1360 .vdisplay = 768, 1361 .vsync_start = 768 + 4, 1362 .vsync_end = 768 + 4 + 4, 1363 .vtotal = 768 + 4 + 4 + 4, 1364 }; 1365 1366 static const struct panel_desc chunghwa_claa101wa01a = { 1367 .modes = &chunghwa_claa101wa01a_mode, 1368 .num_modes = 1, 1369 .bpc = 6, 1370 .size = { 1371 .width = 220, 1372 .height = 120, 1373 }, 1374 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1375 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1376 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1377 }; 1378 1379 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1380 .clock = 69300, 1381 .hdisplay = 1366, 1382 .hsync_start = 1366 + 48, 1383 .hsync_end = 1366 + 48 + 32, 1384 .htotal = 1366 + 48 + 32 + 20, 1385 .vdisplay = 768, 1386 .vsync_start = 768 + 16, 1387 .vsync_end = 768 + 16 + 8, 1388 .vtotal = 768 + 16 + 8 + 16, 1389 }; 1390 1391 static const struct panel_desc chunghwa_claa101wb01 = { 1392 .modes = &chunghwa_claa101wb01_mode, 1393 .num_modes = 1, 1394 .bpc = 6, 1395 .size = { 1396 .width = 223, 1397 .height = 125, 1398 }, 1399 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1400 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1402 }; 1403 1404 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1405 .clock = 33260, 1406 .hdisplay = 800, 1407 .hsync_start = 800 + 40, 1408 .hsync_end = 800 + 40 + 128, 1409 .htotal = 800 + 40 + 128 + 88, 1410 .vdisplay = 480, 1411 .vsync_start = 480 + 10, 1412 .vsync_end = 480 + 10 + 2, 1413 .vtotal = 480 + 10 + 2 + 33, 1414 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1415 }; 1416 1417 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1418 .modes = &dataimage_scf0700c48ggu18_mode, 1419 .num_modes = 1, 1420 .bpc = 8, 1421 .size = { 1422 .width = 152, 1423 .height = 91, 1424 }, 1425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1427 }; 1428 1429 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1430 .pixelclock = { 45000000, 51200000, 57000000 }, 1431 .hactive = { 1024, 1024, 1024 }, 1432 .hfront_porch = { 100, 106, 113 }, 1433 .hback_porch = { 100, 106, 113 }, 1434 .hsync_len = { 100, 108, 114 }, 1435 .vactive = { 600, 600, 600 }, 1436 .vfront_porch = { 8, 11, 15 }, 1437 .vback_porch = { 8, 11, 15 }, 1438 .vsync_len = { 9, 13, 15 }, 1439 .flags = DISPLAY_FLAGS_DE_HIGH, 1440 }; 1441 1442 static const struct panel_desc dlc_dlc0700yzg_1 = { 1443 .timings = &dlc_dlc0700yzg_1_timing, 1444 .num_timings = 1, 1445 .bpc = 6, 1446 .size = { 1447 .width = 154, 1448 .height = 86, 1449 }, 1450 .delay = { 1451 .prepare = 30, 1452 .enable = 200, 1453 .disable = 200, 1454 }, 1455 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1456 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1457 }; 1458 1459 static const struct display_timing dlc_dlc1010gig_timing = { 1460 .pixelclock = { 68900000, 71100000, 73400000 }, 1461 .hactive = { 1280, 1280, 1280 }, 1462 .hfront_porch = { 43, 53, 63 }, 1463 .hback_porch = { 43, 53, 63 }, 1464 .hsync_len = { 44, 54, 64 }, 1465 .vactive = { 800, 800, 800 }, 1466 .vfront_porch = { 5, 8, 11 }, 1467 .vback_porch = { 5, 8, 11 }, 1468 .vsync_len = { 5, 7, 11 }, 1469 .flags = DISPLAY_FLAGS_DE_HIGH, 1470 }; 1471 1472 static const struct panel_desc dlc_dlc1010gig = { 1473 .timings = &dlc_dlc1010gig_timing, 1474 .num_timings = 1, 1475 .bpc = 8, 1476 .size = { 1477 .width = 216, 1478 .height = 135, 1479 }, 1480 .delay = { 1481 .prepare = 60, 1482 .enable = 150, 1483 .disable = 100, 1484 .unprepare = 60, 1485 }, 1486 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1488 }; 1489 1490 static const struct drm_display_mode edt_et035012dm6_mode = { 1491 .clock = 6500, 1492 .hdisplay = 320, 1493 .hsync_start = 320 + 20, 1494 .hsync_end = 320 + 20 + 30, 1495 .htotal = 320 + 20 + 68, 1496 .vdisplay = 240, 1497 .vsync_start = 240 + 4, 1498 .vsync_end = 240 + 4 + 4, 1499 .vtotal = 240 + 4 + 4 + 14, 1500 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1501 }; 1502 1503 static const struct panel_desc edt_et035012dm6 = { 1504 .modes = &edt_et035012dm6_mode, 1505 .num_modes = 1, 1506 .bpc = 8, 1507 .size = { 1508 .width = 70, 1509 .height = 52, 1510 }, 1511 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1512 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1513 }; 1514 1515 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1516 .clock = 6520, 1517 .hdisplay = 320, 1518 .hsync_start = 320 + 20, 1519 .hsync_end = 320 + 20 + 68, 1520 .htotal = 320 + 20 + 68, 1521 .vdisplay = 240, 1522 .vsync_start = 240 + 4, 1523 .vsync_end = 240 + 4 + 18, 1524 .vtotal = 240 + 4 + 18, 1525 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1526 }; 1527 1528 static const struct panel_desc edt_etm0350g0dh6 = { 1529 .modes = &edt_etm0350g0dh6_mode, 1530 .num_modes = 1, 1531 .bpc = 6, 1532 .size = { 1533 .width = 70, 1534 .height = 53, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1538 .connector_type = DRM_MODE_CONNECTOR_DPI, 1539 }; 1540 1541 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1542 .clock = 10870, 1543 .hdisplay = 480, 1544 .hsync_start = 480 + 8, 1545 .hsync_end = 480 + 8 + 4, 1546 .htotal = 480 + 8 + 4 + 41, 1547 1548 /* 1549 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1550 * fb_align 1551 */ 1552 1553 .vdisplay = 288, 1554 .vsync_start = 288 + 2, 1555 .vsync_end = 288 + 2 + 4, 1556 .vtotal = 288 + 2 + 4 + 10, 1557 }; 1558 1559 static const struct panel_desc edt_etm043080dh6gp = { 1560 .modes = &edt_etm043080dh6gp_mode, 1561 .num_modes = 1, 1562 .bpc = 8, 1563 .size = { 1564 .width = 100, 1565 .height = 65, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1568 .connector_type = DRM_MODE_CONNECTOR_DPI, 1569 }; 1570 1571 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1572 .clock = 9000, 1573 .hdisplay = 480, 1574 .hsync_start = 480 + 2, 1575 .hsync_end = 480 + 2 + 41, 1576 .htotal = 480 + 2 + 41 + 2, 1577 .vdisplay = 272, 1578 .vsync_start = 272 + 2, 1579 .vsync_end = 272 + 2 + 10, 1580 .vtotal = 272 + 2 + 10 + 2, 1581 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1582 }; 1583 1584 static const struct panel_desc edt_etm0430g0dh6 = { 1585 .modes = &edt_etm0430g0dh6_mode, 1586 .num_modes = 1, 1587 .bpc = 6, 1588 .size = { 1589 .width = 95, 1590 .height = 54, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1594 .connector_type = DRM_MODE_CONNECTOR_DPI, 1595 }; 1596 1597 static const struct drm_display_mode edt_et057090dhu_mode = { 1598 .clock = 25175, 1599 .hdisplay = 640, 1600 .hsync_start = 640 + 16, 1601 .hsync_end = 640 + 16 + 30, 1602 .htotal = 640 + 16 + 30 + 114, 1603 .vdisplay = 480, 1604 .vsync_start = 480 + 10, 1605 .vsync_end = 480 + 10 + 3, 1606 .vtotal = 480 + 10 + 3 + 32, 1607 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1608 }; 1609 1610 static const struct panel_desc edt_et057090dhu = { 1611 .modes = &edt_et057090dhu_mode, 1612 .num_modes = 1, 1613 .bpc = 6, 1614 .size = { 1615 .width = 115, 1616 .height = 86, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1624 .clock = 33260, 1625 .hdisplay = 800, 1626 .hsync_start = 800 + 40, 1627 .hsync_end = 800 + 40 + 128, 1628 .htotal = 800 + 40 + 128 + 88, 1629 .vdisplay = 480, 1630 .vsync_start = 480 + 10, 1631 .vsync_end = 480 + 10 + 2, 1632 .vtotal = 480 + 10 + 2 + 33, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc edt_etm0700g0dh6 = { 1637 .modes = &edt_etm0700g0dh6_mode, 1638 .num_modes = 1, 1639 .bpc = 6, 1640 .size = { 1641 .width = 152, 1642 .height = 91, 1643 }, 1644 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1645 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1646 .connector_type = DRM_MODE_CONNECTOR_DPI, 1647 }; 1648 1649 static const struct panel_desc edt_etm0700g0bdh6 = { 1650 .modes = &edt_etm0700g0dh6_mode, 1651 .num_modes = 1, 1652 .bpc = 6, 1653 .size = { 1654 .width = 152, 1655 .height = 91, 1656 }, 1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1659 .connector_type = DRM_MODE_CONNECTOR_DPI, 1660 }; 1661 1662 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1663 .clock = 25175, 1664 .hdisplay = 640, 1665 .hsync_start = 640, 1666 .hsync_end = 640 + 16, 1667 .htotal = 640 + 16 + 30 + 114, 1668 .vdisplay = 480, 1669 .vsync_start = 480 + 10, 1670 .vsync_end = 480 + 10 + 3, 1671 .vtotal = 480 + 10 + 3 + 35, 1672 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1673 }; 1674 1675 static const struct panel_desc edt_etmv570g2dhu = { 1676 .modes = &edt_etmv570g2dhu_mode, 1677 .num_modes = 1, 1678 .bpc = 6, 1679 .size = { 1680 .width = 115, 1681 .height = 86, 1682 }, 1683 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1685 .connector_type = DRM_MODE_CONNECTOR_DPI, 1686 }; 1687 1688 static const struct display_timing eink_vb3300_kca_timing = { 1689 .pixelclock = { 40000000, 40000000, 40000000 }, 1690 .hactive = { 334, 334, 334 }, 1691 .hfront_porch = { 1, 1, 1 }, 1692 .hback_porch = { 1, 1, 1 }, 1693 .hsync_len = { 1, 1, 1 }, 1694 .vactive = { 1405, 1405, 1405 }, 1695 .vfront_porch = { 1, 1, 1 }, 1696 .vback_porch = { 1, 1, 1 }, 1697 .vsync_len = { 1, 1, 1 }, 1698 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1699 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1700 }; 1701 1702 static const struct panel_desc eink_vb3300_kca = { 1703 .timings = &eink_vb3300_kca_timing, 1704 .num_timings = 1, 1705 .bpc = 6, 1706 .size = { 1707 .width = 157, 1708 .height = 209, 1709 }, 1710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1711 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1712 .connector_type = DRM_MODE_CONNECTOR_DPI, 1713 }; 1714 1715 static const struct display_timing evervision_vgg804821_timing = { 1716 .pixelclock = { 27600000, 33300000, 50000000 }, 1717 .hactive = { 800, 800, 800 }, 1718 .hfront_porch = { 40, 66, 70 }, 1719 .hback_porch = { 40, 67, 70 }, 1720 .hsync_len = { 40, 67, 70 }, 1721 .vactive = { 480, 480, 480 }, 1722 .vfront_porch = { 6, 10, 10 }, 1723 .vback_porch = { 7, 11, 11 }, 1724 .vsync_len = { 7, 11, 11 }, 1725 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1726 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1727 DISPLAY_FLAGS_SYNC_NEGEDGE, 1728 }; 1729 1730 static const struct panel_desc evervision_vgg804821 = { 1731 .timings = &evervision_vgg804821_timing, 1732 .num_timings = 1, 1733 .bpc = 8, 1734 .size = { 1735 .width = 108, 1736 .height = 64, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1740 }; 1741 1742 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1743 .clock = 32260, 1744 .hdisplay = 800, 1745 .hsync_start = 800 + 168, 1746 .hsync_end = 800 + 168 + 64, 1747 .htotal = 800 + 168 + 64 + 88, 1748 .vdisplay = 480, 1749 .vsync_start = 480 + 37, 1750 .vsync_end = 480 + 37 + 2, 1751 .vtotal = 480 + 37 + 2 + 8, 1752 }; 1753 1754 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1755 .modes = &foxlink_fl500wvr00_a0t_mode, 1756 .num_modes = 1, 1757 .bpc = 8, 1758 .size = { 1759 .width = 108, 1760 .height = 65, 1761 }, 1762 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1763 }; 1764 1765 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1766 { /* 60 Hz */ 1767 .clock = 6000, 1768 .hdisplay = 320, 1769 .hsync_start = 320 + 44, 1770 .hsync_end = 320 + 44 + 16, 1771 .htotal = 320 + 44 + 16 + 20, 1772 .vdisplay = 240, 1773 .vsync_start = 240 + 2, 1774 .vsync_end = 240 + 2 + 6, 1775 .vtotal = 240 + 2 + 6 + 2, 1776 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1777 }, 1778 { /* 50 Hz */ 1779 .clock = 5400, 1780 .hdisplay = 320, 1781 .hsync_start = 320 + 56, 1782 .hsync_end = 320 + 56 + 16, 1783 .htotal = 320 + 56 + 16 + 40, 1784 .vdisplay = 240, 1785 .vsync_start = 240 + 2, 1786 .vsync_end = 240 + 2 + 6, 1787 .vtotal = 240 + 2 + 6 + 2, 1788 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1789 }, 1790 }; 1791 1792 static const struct panel_desc frida_frd350h54004 = { 1793 .modes = frida_frd350h54004_modes, 1794 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1795 .bpc = 8, 1796 .size = { 1797 .width = 77, 1798 .height = 64, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1806 .clock = 67185, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 20, 1809 .hsync_end = 800 + 20 + 24, 1810 .htotal = 800 + 20 + 24 + 20, 1811 .vdisplay = 1280, 1812 .vsync_start = 1280 + 4, 1813 .vsync_end = 1280 + 4 + 8, 1814 .vtotal = 1280 + 4 + 8 + 4, 1815 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1816 }; 1817 1818 static const struct panel_desc friendlyarm_hd702e = { 1819 .modes = &friendlyarm_hd702e_mode, 1820 .num_modes = 1, 1821 .size = { 1822 .width = 94, 1823 .height = 151, 1824 }, 1825 }; 1826 1827 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1828 .clock = 9000, 1829 .hdisplay = 480, 1830 .hsync_start = 480 + 5, 1831 .hsync_end = 480 + 5 + 1, 1832 .htotal = 480 + 5 + 1 + 40, 1833 .vdisplay = 272, 1834 .vsync_start = 272 + 8, 1835 .vsync_end = 272 + 8 + 1, 1836 .vtotal = 272 + 8 + 1 + 8, 1837 }; 1838 1839 static const struct panel_desc giantplus_gpg482739qs5 = { 1840 .modes = &giantplus_gpg482739qs5_mode, 1841 .num_modes = 1, 1842 .bpc = 8, 1843 .size = { 1844 .width = 95, 1845 .height = 54, 1846 }, 1847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1848 }; 1849 1850 static const struct display_timing giantplus_gpm940b0_timing = { 1851 .pixelclock = { 13500000, 27000000, 27500000 }, 1852 .hactive = { 320, 320, 320 }, 1853 .hfront_porch = { 14, 686, 718 }, 1854 .hback_porch = { 50, 70, 255 }, 1855 .hsync_len = { 1, 1, 1 }, 1856 .vactive = { 240, 240, 240 }, 1857 .vfront_porch = { 1, 1, 179 }, 1858 .vback_porch = { 1, 21, 31 }, 1859 .vsync_len = { 1, 1, 6 }, 1860 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1861 }; 1862 1863 static const struct panel_desc giantplus_gpm940b0 = { 1864 .timings = &giantplus_gpm940b0_timing, 1865 .num_timings = 1, 1866 .bpc = 8, 1867 .size = { 1868 .width = 60, 1869 .height = 45, 1870 }, 1871 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1872 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1873 }; 1874 1875 static const struct display_timing hannstar_hsd070pww1_timing = { 1876 .pixelclock = { 64300000, 71100000, 82000000 }, 1877 .hactive = { 1280, 1280, 1280 }, 1878 .hfront_porch = { 1, 1, 10 }, 1879 .hback_porch = { 1, 1, 10 }, 1880 /* 1881 * According to the data sheet, the minimum horizontal blanking interval 1882 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1883 * minimum working horizontal blanking interval to be 60 clocks. 1884 */ 1885 .hsync_len = { 58, 158, 661 }, 1886 .vactive = { 800, 800, 800 }, 1887 .vfront_porch = { 1, 1, 10 }, 1888 .vback_porch = { 1, 1, 10 }, 1889 .vsync_len = { 1, 21, 203 }, 1890 .flags = DISPLAY_FLAGS_DE_HIGH, 1891 }; 1892 1893 static const struct panel_desc hannstar_hsd070pww1 = { 1894 .timings = &hannstar_hsd070pww1_timing, 1895 .num_timings = 1, 1896 .bpc = 6, 1897 .size = { 1898 .width = 151, 1899 .height = 94, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1903 }; 1904 1905 static const struct display_timing hannstar_hsd100pxn1_timing = { 1906 .pixelclock = { 55000000, 65000000, 75000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 40, 40, 40 }, 1909 .hback_porch = { 220, 220, 220 }, 1910 .hsync_len = { 20, 60, 100 }, 1911 .vactive = { 768, 768, 768 }, 1912 .vfront_porch = { 7, 7, 7 }, 1913 .vback_porch = { 21, 21, 21 }, 1914 .vsync_len = { 10, 10, 10 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc hannstar_hsd100pxn1 = { 1919 .timings = &hannstar_hsd100pxn1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 203, 1924 .height = 152, 1925 }, 1926 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1928 }; 1929 1930 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1931 .clock = 33333, 1932 .hdisplay = 800, 1933 .hsync_start = 800 + 85, 1934 .hsync_end = 800 + 85 + 86, 1935 .htotal = 800 + 85 + 86 + 85, 1936 .vdisplay = 480, 1937 .vsync_start = 480 + 16, 1938 .vsync_end = 480 + 16 + 13, 1939 .vtotal = 480 + 16 + 13 + 16, 1940 }; 1941 1942 static const struct panel_desc hitachi_tx23d38vm0caa = { 1943 .modes = &hitachi_tx23d38vm0caa_mode, 1944 .num_modes = 1, 1945 .bpc = 6, 1946 .size = { 1947 .width = 195, 1948 .height = 117, 1949 }, 1950 .delay = { 1951 .enable = 160, 1952 .disable = 160, 1953 }, 1954 }; 1955 1956 static const struct drm_display_mode innolux_at043tn24_mode = { 1957 .clock = 9000, 1958 .hdisplay = 480, 1959 .hsync_start = 480 + 2, 1960 .hsync_end = 480 + 2 + 41, 1961 .htotal = 480 + 2 + 41 + 2, 1962 .vdisplay = 272, 1963 .vsync_start = 272 + 2, 1964 .vsync_end = 272 + 2 + 10, 1965 .vtotal = 272 + 2 + 10 + 2, 1966 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1967 }; 1968 1969 static const struct panel_desc innolux_at043tn24 = { 1970 .modes = &innolux_at043tn24_mode, 1971 .num_modes = 1, 1972 .bpc = 8, 1973 .size = { 1974 .width = 95, 1975 .height = 54, 1976 }, 1977 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1978 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1979 }; 1980 1981 static const struct drm_display_mode innolux_at070tn92_mode = { 1982 .clock = 33333, 1983 .hdisplay = 800, 1984 .hsync_start = 800 + 210, 1985 .hsync_end = 800 + 210 + 20, 1986 .htotal = 800 + 210 + 20 + 46, 1987 .vdisplay = 480, 1988 .vsync_start = 480 + 22, 1989 .vsync_end = 480 + 22 + 10, 1990 .vtotal = 480 + 22 + 23 + 10, 1991 }; 1992 1993 static const struct panel_desc innolux_at070tn92 = { 1994 .modes = &innolux_at070tn92_mode, 1995 .num_modes = 1, 1996 .size = { 1997 .width = 154, 1998 .height = 86, 1999 }, 2000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2001 }; 2002 2003 static const struct display_timing innolux_g070y2_l01_timing = { 2004 .pixelclock = { 28000000, 29500000, 32000000 }, 2005 .hactive = { 800, 800, 800 }, 2006 .hfront_porch = { 61, 91, 141 }, 2007 .hback_porch = { 60, 90, 140 }, 2008 .hsync_len = { 12, 12, 12 }, 2009 .vactive = { 480, 480, 480 }, 2010 .vfront_porch = { 4, 9, 30 }, 2011 .vback_porch = { 4, 8, 28 }, 2012 .vsync_len = { 2, 2, 2 }, 2013 .flags = DISPLAY_FLAGS_DE_HIGH, 2014 }; 2015 2016 static const struct panel_desc innolux_g070y2_l01 = { 2017 .timings = &innolux_g070y2_l01_timing, 2018 .num_timings = 1, 2019 .bpc = 6, 2020 .size = { 2021 .width = 152, 2022 .height = 91, 2023 }, 2024 .delay = { 2025 .prepare = 10, 2026 .enable = 100, 2027 .disable = 100, 2028 .unprepare = 800, 2029 }, 2030 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2031 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2032 }; 2033 2034 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2035 .clock = 33333, 2036 .hdisplay = 800, 2037 .hsync_start = 800 + 210, 2038 .hsync_end = 800 + 210 + 20, 2039 .htotal = 800 + 210 + 20 + 46, 2040 .vdisplay = 480, 2041 .vsync_start = 480 + 22, 2042 .vsync_end = 480 + 22 + 10, 2043 .vtotal = 480 + 22 + 23 + 10, 2044 }; 2045 2046 static const struct panel_desc innolux_g070y2_t02 = { 2047 .modes = &innolux_g070y2_t02_mode, 2048 .num_modes = 1, 2049 .bpc = 8, 2050 .size = { 2051 .width = 152, 2052 .height = 92, 2053 }, 2054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2055 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2056 .connector_type = DRM_MODE_CONNECTOR_DPI, 2057 }; 2058 2059 static const struct display_timing innolux_g101ice_l01_timing = { 2060 .pixelclock = { 60400000, 71100000, 74700000 }, 2061 .hactive = { 1280, 1280, 1280 }, 2062 .hfront_porch = { 41, 80, 100 }, 2063 .hback_porch = { 40, 79, 99 }, 2064 .hsync_len = { 1, 1, 1 }, 2065 .vactive = { 800, 800, 800 }, 2066 .vfront_porch = { 5, 11, 14 }, 2067 .vback_porch = { 4, 11, 14 }, 2068 .vsync_len = { 1, 1, 1 }, 2069 .flags = DISPLAY_FLAGS_DE_HIGH, 2070 }; 2071 2072 static const struct panel_desc innolux_g101ice_l01 = { 2073 .timings = &innolux_g101ice_l01_timing, 2074 .num_timings = 1, 2075 .bpc = 8, 2076 .size = { 2077 .width = 217, 2078 .height = 135, 2079 }, 2080 .delay = { 2081 .enable = 200, 2082 .disable = 200, 2083 }, 2084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2085 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2086 }; 2087 2088 static const struct display_timing innolux_g121i1_l01_timing = { 2089 .pixelclock = { 67450000, 71000000, 74550000 }, 2090 .hactive = { 1280, 1280, 1280 }, 2091 .hfront_porch = { 40, 80, 160 }, 2092 .hback_porch = { 39, 79, 159 }, 2093 .hsync_len = { 1, 1, 1 }, 2094 .vactive = { 800, 800, 800 }, 2095 .vfront_porch = { 5, 11, 100 }, 2096 .vback_porch = { 4, 11, 99 }, 2097 .vsync_len = { 1, 1, 1 }, 2098 }; 2099 2100 static const struct panel_desc innolux_g121i1_l01 = { 2101 .timings = &innolux_g121i1_l01_timing, 2102 .num_timings = 1, 2103 .bpc = 6, 2104 .size = { 2105 .width = 261, 2106 .height = 163, 2107 }, 2108 .delay = { 2109 .enable = 200, 2110 .disable = 20, 2111 }, 2112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2113 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2114 }; 2115 2116 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2117 .clock = 65000, 2118 .hdisplay = 1024, 2119 .hsync_start = 1024 + 0, 2120 .hsync_end = 1024 + 1, 2121 .htotal = 1024 + 0 + 1 + 320, 2122 .vdisplay = 768, 2123 .vsync_start = 768 + 38, 2124 .vsync_end = 768 + 38 + 1, 2125 .vtotal = 768 + 38 + 1 + 0, 2126 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2127 }; 2128 2129 static const struct panel_desc innolux_g121x1_l03 = { 2130 .modes = &innolux_g121x1_l03_mode, 2131 .num_modes = 1, 2132 .bpc = 6, 2133 .size = { 2134 .width = 246, 2135 .height = 185, 2136 }, 2137 .delay = { 2138 .enable = 200, 2139 .unprepare = 200, 2140 .disable = 400, 2141 }, 2142 }; 2143 2144 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2145 .clock = 69300, 2146 .hdisplay = 1366, 2147 .hsync_start = 1366 + 16, 2148 .hsync_end = 1366 + 16 + 34, 2149 .htotal = 1366 + 16 + 34 + 50, 2150 .vdisplay = 768, 2151 .vsync_start = 768 + 2, 2152 .vsync_end = 768 + 2 + 6, 2153 .vtotal = 768 + 2 + 6 + 12, 2154 }; 2155 2156 static const struct panel_desc innolux_n156bge_l21 = { 2157 .modes = &innolux_n156bge_l21_mode, 2158 .num_modes = 1, 2159 .bpc = 6, 2160 .size = { 2161 .width = 344, 2162 .height = 193, 2163 }, 2164 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2165 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2167 }; 2168 2169 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2170 .clock = 51501, 2171 .hdisplay = 1024, 2172 .hsync_start = 1024 + 128, 2173 .hsync_end = 1024 + 128 + 64, 2174 .htotal = 1024 + 128 + 64 + 128, 2175 .vdisplay = 600, 2176 .vsync_start = 600 + 16, 2177 .vsync_end = 600 + 16 + 4, 2178 .vtotal = 600 + 16 + 4 + 16, 2179 }; 2180 2181 static const struct panel_desc innolux_zj070na_01p = { 2182 .modes = &innolux_zj070na_01p_mode, 2183 .num_modes = 1, 2184 .bpc = 6, 2185 .size = { 2186 .width = 154, 2187 .height = 90, 2188 }, 2189 }; 2190 2191 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2192 .pixelclock = { 5580000, 5850000, 6200000 }, 2193 .hactive = { 320, 320, 320 }, 2194 .hfront_porch = { 30, 30, 30 }, 2195 .hback_porch = { 30, 30, 30 }, 2196 .hsync_len = { 1, 5, 17 }, 2197 .vactive = { 240, 240, 240 }, 2198 .vfront_porch = { 6, 6, 6 }, 2199 .vback_porch = { 5, 5, 5 }, 2200 .vsync_len = { 1, 2, 11 }, 2201 .flags = DISPLAY_FLAGS_DE_HIGH, 2202 }; 2203 2204 static const struct panel_desc koe_tx14d24vm1bpa = { 2205 .timings = &koe_tx14d24vm1bpa_timing, 2206 .num_timings = 1, 2207 .bpc = 6, 2208 .size = { 2209 .width = 115, 2210 .height = 86, 2211 }, 2212 }; 2213 2214 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2215 .pixelclock = { 151820000, 156720000, 159780000 }, 2216 .hactive = { 1920, 1920, 1920 }, 2217 .hfront_porch = { 105, 130, 142 }, 2218 .hback_porch = { 45, 70, 82 }, 2219 .hsync_len = { 30, 30, 30 }, 2220 .vactive = { 1200, 1200, 1200}, 2221 .vfront_porch = { 3, 5, 10 }, 2222 .vback_porch = { 2, 5, 10 }, 2223 .vsync_len = { 5, 5, 5 }, 2224 }; 2225 2226 static const struct panel_desc koe_tx26d202vm0bwa = { 2227 .timings = &koe_tx26d202vm0bwa_timing, 2228 .num_timings = 1, 2229 .bpc = 8, 2230 .size = { 2231 .width = 217, 2232 .height = 136, 2233 }, 2234 .delay = { 2235 .prepare = 1000, 2236 .enable = 1000, 2237 .unprepare = 1000, 2238 .disable = 1000, 2239 }, 2240 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2241 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2242 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2243 }; 2244 2245 static const struct display_timing koe_tx31d200vm0baa_timing = { 2246 .pixelclock = { 39600000, 43200000, 48000000 }, 2247 .hactive = { 1280, 1280, 1280 }, 2248 .hfront_porch = { 16, 36, 56 }, 2249 .hback_porch = { 16, 36, 56 }, 2250 .hsync_len = { 8, 8, 8 }, 2251 .vactive = { 480, 480, 480 }, 2252 .vfront_porch = { 6, 21, 33 }, 2253 .vback_porch = { 6, 21, 33 }, 2254 .vsync_len = { 8, 8, 8 }, 2255 .flags = DISPLAY_FLAGS_DE_HIGH, 2256 }; 2257 2258 static const struct panel_desc koe_tx31d200vm0baa = { 2259 .timings = &koe_tx31d200vm0baa_timing, 2260 .num_timings = 1, 2261 .bpc = 6, 2262 .size = { 2263 .width = 292, 2264 .height = 109, 2265 }, 2266 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2268 }; 2269 2270 static const struct display_timing kyo_tcg121xglp_timing = { 2271 .pixelclock = { 52000000, 65000000, 71000000 }, 2272 .hactive = { 1024, 1024, 1024 }, 2273 .hfront_porch = { 2, 2, 2 }, 2274 .hback_porch = { 2, 2, 2 }, 2275 .hsync_len = { 86, 124, 244 }, 2276 .vactive = { 768, 768, 768 }, 2277 .vfront_porch = { 2, 2, 2 }, 2278 .vback_porch = { 2, 2, 2 }, 2279 .vsync_len = { 6, 34, 73 }, 2280 .flags = DISPLAY_FLAGS_DE_HIGH, 2281 }; 2282 2283 static const struct panel_desc kyo_tcg121xglp = { 2284 .timings = &kyo_tcg121xglp_timing, 2285 .num_timings = 1, 2286 .bpc = 8, 2287 .size = { 2288 .width = 246, 2289 .height = 184, 2290 }, 2291 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2292 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2293 }; 2294 2295 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2296 .clock = 7000, 2297 .hdisplay = 320, 2298 .hsync_start = 320 + 20, 2299 .hsync_end = 320 + 20 + 30, 2300 .htotal = 320 + 20 + 30 + 38, 2301 .vdisplay = 240, 2302 .vsync_start = 240 + 4, 2303 .vsync_end = 240 + 4 + 3, 2304 .vtotal = 240 + 4 + 3 + 15, 2305 }; 2306 2307 static const struct panel_desc lemaker_bl035_rgb_002 = { 2308 .modes = &lemaker_bl035_rgb_002_mode, 2309 .num_modes = 1, 2310 .size = { 2311 .width = 70, 2312 .height = 52, 2313 }, 2314 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2315 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2316 }; 2317 2318 static const struct drm_display_mode lg_lb070wv8_mode = { 2319 .clock = 33246, 2320 .hdisplay = 800, 2321 .hsync_start = 800 + 88, 2322 .hsync_end = 800 + 88 + 80, 2323 .htotal = 800 + 88 + 80 + 88, 2324 .vdisplay = 480, 2325 .vsync_start = 480 + 10, 2326 .vsync_end = 480 + 10 + 25, 2327 .vtotal = 480 + 10 + 25 + 10, 2328 }; 2329 2330 static const struct panel_desc lg_lb070wv8 = { 2331 .modes = &lg_lb070wv8_mode, 2332 .num_modes = 1, 2333 .bpc = 8, 2334 .size = { 2335 .width = 151, 2336 .height = 91, 2337 }, 2338 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2339 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2340 }; 2341 2342 static const struct display_timing logictechno_lt161010_2nh_timing = { 2343 .pixelclock = { 26400000, 33300000, 46800000 }, 2344 .hactive = { 800, 800, 800 }, 2345 .hfront_porch = { 16, 210, 354 }, 2346 .hback_porch = { 46, 46, 46 }, 2347 .hsync_len = { 1, 20, 40 }, 2348 .vactive = { 480, 480, 480 }, 2349 .vfront_porch = { 7, 22, 147 }, 2350 .vback_porch = { 23, 23, 23 }, 2351 .vsync_len = { 1, 10, 20 }, 2352 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2353 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2354 DISPLAY_FLAGS_SYNC_POSEDGE, 2355 }; 2356 2357 static const struct panel_desc logictechno_lt161010_2nh = { 2358 .timings = &logictechno_lt161010_2nh_timing, 2359 .num_timings = 1, 2360 .size = { 2361 .width = 154, 2362 .height = 86, 2363 }, 2364 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2365 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2366 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2367 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2368 .connector_type = DRM_MODE_CONNECTOR_DPI, 2369 }; 2370 2371 static const struct display_timing logictechno_lt170410_2whc_timing = { 2372 .pixelclock = { 68900000, 71100000, 73400000 }, 2373 .hactive = { 1280, 1280, 1280 }, 2374 .hfront_porch = { 23, 60, 71 }, 2375 .hback_porch = { 23, 60, 71 }, 2376 .hsync_len = { 15, 40, 47 }, 2377 .vactive = { 800, 800, 800 }, 2378 .vfront_porch = { 5, 7, 10 }, 2379 .vback_porch = { 5, 7, 10 }, 2380 .vsync_len = { 6, 9, 12 }, 2381 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2382 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2383 DISPLAY_FLAGS_SYNC_POSEDGE, 2384 }; 2385 2386 static const struct panel_desc logictechno_lt170410_2whc = { 2387 .timings = &logictechno_lt170410_2whc_timing, 2388 .num_timings = 1, 2389 .size = { 2390 .width = 217, 2391 .height = 136, 2392 }, 2393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2394 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2396 }; 2397 2398 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2399 .clock = 33000, 2400 .hdisplay = 800, 2401 .hsync_start = 800 + 112, 2402 .hsync_end = 800 + 112 + 3, 2403 .htotal = 800 + 112 + 3 + 85, 2404 .vdisplay = 480, 2405 .vsync_start = 480 + 38, 2406 .vsync_end = 480 + 38 + 3, 2407 .vtotal = 480 + 38 + 3 + 29, 2408 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2409 }; 2410 2411 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2412 .modes = &logictechno_lttd800480070_l2rt_mode, 2413 .num_modes = 1, 2414 .bpc = 8, 2415 .size = { 2416 .width = 154, 2417 .height = 86, 2418 }, 2419 .delay = { 2420 .prepare = 45, 2421 .enable = 100, 2422 .disable = 100, 2423 .unprepare = 45 2424 }, 2425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2426 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2427 .connector_type = DRM_MODE_CONNECTOR_DPI, 2428 }; 2429 2430 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2431 .clock = 33000, 2432 .hdisplay = 800, 2433 .hsync_start = 800 + 154, 2434 .hsync_end = 800 + 154 + 3, 2435 .htotal = 800 + 154 + 3 + 43, 2436 .vdisplay = 480, 2437 .vsync_start = 480 + 47, 2438 .vsync_end = 480 + 47 + 3, 2439 .vtotal = 480 + 47 + 3 + 20, 2440 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2441 }; 2442 2443 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2444 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2445 .num_modes = 1, 2446 .bpc = 8, 2447 .size = { 2448 .width = 154, 2449 .height = 86, 2450 }, 2451 .delay = { 2452 .prepare = 45, 2453 .enable = 100, 2454 .disable = 100, 2455 .unprepare = 45 2456 }, 2457 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2458 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2459 .connector_type = DRM_MODE_CONNECTOR_DPI, 2460 }; 2461 2462 static const struct drm_display_mode logicpd_type_28_mode = { 2463 .clock = 9107, 2464 .hdisplay = 480, 2465 .hsync_start = 480 + 3, 2466 .hsync_end = 480 + 3 + 42, 2467 .htotal = 480 + 3 + 42 + 2, 2468 2469 .vdisplay = 272, 2470 .vsync_start = 272 + 2, 2471 .vsync_end = 272 + 2 + 11, 2472 .vtotal = 272 + 2 + 11 + 3, 2473 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2474 }; 2475 2476 static const struct panel_desc logicpd_type_28 = { 2477 .modes = &logicpd_type_28_mode, 2478 .num_modes = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 105, 2482 .height = 67, 2483 }, 2484 .delay = { 2485 .prepare = 200, 2486 .enable = 200, 2487 .unprepare = 200, 2488 .disable = 200, 2489 }, 2490 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2491 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2492 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2493 .connector_type = DRM_MODE_CONNECTOR_DPI, 2494 }; 2495 2496 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2497 .clock = 30400, 2498 .hdisplay = 800, 2499 .hsync_start = 800 + 0, 2500 .hsync_end = 800 + 1, 2501 .htotal = 800 + 0 + 1 + 160, 2502 .vdisplay = 480, 2503 .vsync_start = 480 + 0, 2504 .vsync_end = 480 + 48 + 1, 2505 .vtotal = 480 + 48 + 1 + 0, 2506 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2507 }; 2508 2509 static const struct panel_desc mitsubishi_aa070mc01 = { 2510 .modes = &mitsubishi_aa070mc01_mode, 2511 .num_modes = 1, 2512 .bpc = 8, 2513 .size = { 2514 .width = 152, 2515 .height = 91, 2516 }, 2517 2518 .delay = { 2519 .enable = 200, 2520 .unprepare = 200, 2521 .disable = 400, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2524 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2525 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2526 }; 2527 2528 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2529 .pixelclock = { 68900000, 70000000, 73400000 }, 2530 .hactive = { 1280, 1280, 1280 }, 2531 .hfront_porch = { 30, 60, 71 }, 2532 .hback_porch = { 30, 60, 71 }, 2533 .hsync_len = { 10, 10, 48 }, 2534 .vactive = { 800, 800, 800 }, 2535 .vfront_porch = { 5, 10, 10 }, 2536 .vback_porch = { 5, 10, 10 }, 2537 .vsync_len = { 5, 6, 13 }, 2538 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2539 DISPLAY_FLAGS_DE_HIGH, 2540 }; 2541 2542 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2543 .timings = &multi_inno_mi1010ait_1cp_timing, 2544 .num_timings = 1, 2545 .bpc = 8, 2546 .size = { 2547 .width = 217, 2548 .height = 136, 2549 }, 2550 .delay = { 2551 .enable = 50, 2552 .disable = 50, 2553 }, 2554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2555 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2556 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2557 }; 2558 2559 static const struct display_timing nec_nl12880bc20_05_timing = { 2560 .pixelclock = { 67000000, 71000000, 75000000 }, 2561 .hactive = { 1280, 1280, 1280 }, 2562 .hfront_porch = { 2, 30, 30 }, 2563 .hback_porch = { 6, 100, 100 }, 2564 .hsync_len = { 2, 30, 30 }, 2565 .vactive = { 800, 800, 800 }, 2566 .vfront_porch = { 5, 5, 5 }, 2567 .vback_porch = { 11, 11, 11 }, 2568 .vsync_len = { 7, 7, 7 }, 2569 }; 2570 2571 static const struct panel_desc nec_nl12880bc20_05 = { 2572 .timings = &nec_nl12880bc20_05_timing, 2573 .num_timings = 1, 2574 .bpc = 8, 2575 .size = { 2576 .width = 261, 2577 .height = 163, 2578 }, 2579 .delay = { 2580 .enable = 50, 2581 .disable = 50, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2584 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2585 }; 2586 2587 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2588 .clock = 10870, 2589 .hdisplay = 480, 2590 .hsync_start = 480 + 2, 2591 .hsync_end = 480 + 2 + 41, 2592 .htotal = 480 + 2 + 41 + 2, 2593 .vdisplay = 272, 2594 .vsync_start = 272 + 2, 2595 .vsync_end = 272 + 2 + 4, 2596 .vtotal = 272 + 2 + 4 + 2, 2597 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2598 }; 2599 2600 static const struct panel_desc nec_nl4827hc19_05b = { 2601 .modes = &nec_nl4827hc19_05b_mode, 2602 .num_modes = 1, 2603 .bpc = 8, 2604 .size = { 2605 .width = 95, 2606 .height = 54, 2607 }, 2608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2609 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2610 }; 2611 2612 static const struct drm_display_mode netron_dy_e231732_mode = { 2613 .clock = 66000, 2614 .hdisplay = 1024, 2615 .hsync_start = 1024 + 160, 2616 .hsync_end = 1024 + 160 + 70, 2617 .htotal = 1024 + 160 + 70 + 90, 2618 .vdisplay = 600, 2619 .vsync_start = 600 + 127, 2620 .vsync_end = 600 + 127 + 20, 2621 .vtotal = 600 + 127 + 20 + 3, 2622 }; 2623 2624 static const struct panel_desc netron_dy_e231732 = { 2625 .modes = &netron_dy_e231732_mode, 2626 .num_modes = 1, 2627 .size = { 2628 .width = 154, 2629 .height = 87, 2630 }, 2631 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2632 }; 2633 2634 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2635 .clock = 9000, 2636 .hdisplay = 480, 2637 .hsync_start = 480 + 2, 2638 .hsync_end = 480 + 2 + 41, 2639 .htotal = 480 + 2 + 41 + 2, 2640 .vdisplay = 272, 2641 .vsync_start = 272 + 2, 2642 .vsync_end = 272 + 2 + 10, 2643 .vtotal = 272 + 2 + 10 + 2, 2644 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2645 }; 2646 2647 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2648 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2649 .num_modes = 1, 2650 .bpc = 8, 2651 .size = { 2652 .width = 95, 2653 .height = 54, 2654 }, 2655 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2656 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2657 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2658 .connector_type = DRM_MODE_CONNECTOR_DPI, 2659 }; 2660 2661 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2662 .pixelclock = { 130000000, 148350000, 163000000 }, 2663 .hactive = { 1920, 1920, 1920 }, 2664 .hfront_porch = { 80, 100, 100 }, 2665 .hback_porch = { 100, 120, 120 }, 2666 .hsync_len = { 50, 60, 60 }, 2667 .vactive = { 1080, 1080, 1080 }, 2668 .vfront_porch = { 12, 30, 30 }, 2669 .vback_porch = { 4, 10, 10 }, 2670 .vsync_len = { 4, 5, 5 }, 2671 }; 2672 2673 static const struct panel_desc nlt_nl192108ac18_02d = { 2674 .timings = &nlt_nl192108ac18_02d_timing, 2675 .num_timings = 1, 2676 .bpc = 8, 2677 .size = { 2678 .width = 344, 2679 .height = 194, 2680 }, 2681 .delay = { 2682 .unprepare = 500, 2683 }, 2684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2685 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2686 }; 2687 2688 static const struct drm_display_mode nvd_9128_mode = { 2689 .clock = 29500, 2690 .hdisplay = 800, 2691 .hsync_start = 800 + 130, 2692 .hsync_end = 800 + 130 + 98, 2693 .htotal = 800 + 0 + 130 + 98, 2694 .vdisplay = 480, 2695 .vsync_start = 480 + 10, 2696 .vsync_end = 480 + 10 + 50, 2697 .vtotal = 480 + 0 + 10 + 50, 2698 }; 2699 2700 static const struct panel_desc nvd_9128 = { 2701 .modes = &nvd_9128_mode, 2702 .num_modes = 1, 2703 .bpc = 8, 2704 .size = { 2705 .width = 156, 2706 .height = 88, 2707 }, 2708 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2709 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2710 }; 2711 2712 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2713 .pixelclock = { 30000000, 30000000, 40000000 }, 2714 .hactive = { 800, 800, 800 }, 2715 .hfront_porch = { 40, 40, 40 }, 2716 .hback_porch = { 40, 40, 40 }, 2717 .hsync_len = { 1, 48, 48 }, 2718 .vactive = { 480, 480, 480 }, 2719 .vfront_porch = { 13, 13, 13 }, 2720 .vback_porch = { 29, 29, 29 }, 2721 .vsync_len = { 3, 3, 3 }, 2722 .flags = DISPLAY_FLAGS_DE_HIGH, 2723 }; 2724 2725 static const struct panel_desc okaya_rs800480t_7x0gp = { 2726 .timings = &okaya_rs800480t_7x0gp_timing, 2727 .num_timings = 1, 2728 .bpc = 6, 2729 .size = { 2730 .width = 154, 2731 .height = 87, 2732 }, 2733 .delay = { 2734 .prepare = 41, 2735 .enable = 50, 2736 .unprepare = 41, 2737 .disable = 50, 2738 }, 2739 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2740 }; 2741 2742 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2743 .clock = 9000, 2744 .hdisplay = 480, 2745 .hsync_start = 480 + 5, 2746 .hsync_end = 480 + 5 + 30, 2747 .htotal = 480 + 5 + 30 + 10, 2748 .vdisplay = 272, 2749 .vsync_start = 272 + 8, 2750 .vsync_end = 272 + 8 + 5, 2751 .vtotal = 272 + 8 + 5 + 3, 2752 }; 2753 2754 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2755 .modes = &olimex_lcd_olinuxino_43ts_mode, 2756 .num_modes = 1, 2757 .size = { 2758 .width = 95, 2759 .height = 54, 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2762 }; 2763 2764 /* 2765 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2766 * pixel clocks, but this is the timing that was being used in the Adafruit 2767 * installation instructions. 2768 */ 2769 static const struct drm_display_mode ontat_yx700wv03_mode = { 2770 .clock = 29500, 2771 .hdisplay = 800, 2772 .hsync_start = 824, 2773 .hsync_end = 896, 2774 .htotal = 992, 2775 .vdisplay = 480, 2776 .vsync_start = 483, 2777 .vsync_end = 493, 2778 .vtotal = 500, 2779 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2780 }; 2781 2782 /* 2783 * Specification at: 2784 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2785 */ 2786 static const struct panel_desc ontat_yx700wv03 = { 2787 .modes = &ontat_yx700wv03_mode, 2788 .num_modes = 1, 2789 .bpc = 8, 2790 .size = { 2791 .width = 154, 2792 .height = 83, 2793 }, 2794 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2795 }; 2796 2797 static const struct drm_display_mode ortustech_com37h3m_mode = { 2798 .clock = 22230, 2799 .hdisplay = 480, 2800 .hsync_start = 480 + 40, 2801 .hsync_end = 480 + 40 + 10, 2802 .htotal = 480 + 40 + 10 + 40, 2803 .vdisplay = 640, 2804 .vsync_start = 640 + 4, 2805 .vsync_end = 640 + 4 + 2, 2806 .vtotal = 640 + 4 + 2 + 4, 2807 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2808 }; 2809 2810 static const struct panel_desc ortustech_com37h3m = { 2811 .modes = &ortustech_com37h3m_mode, 2812 .num_modes = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 56, /* 56.16mm */ 2816 .height = 75, /* 74.88mm */ 2817 }, 2818 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2819 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2820 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2821 }; 2822 2823 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2824 .clock = 25000, 2825 .hdisplay = 480, 2826 .hsync_start = 480 + 10, 2827 .hsync_end = 480 + 10 + 10, 2828 .htotal = 480 + 10 + 10 + 15, 2829 .vdisplay = 800, 2830 .vsync_start = 800 + 3, 2831 .vsync_end = 800 + 3 + 3, 2832 .vtotal = 800 + 3 + 3 + 3, 2833 }; 2834 2835 static const struct panel_desc ortustech_com43h4m85ulc = { 2836 .modes = &ortustech_com43h4m85ulc_mode, 2837 .num_modes = 1, 2838 .bpc = 6, 2839 .size = { 2840 .width = 56, 2841 .height = 93, 2842 }, 2843 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2844 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2845 .connector_type = DRM_MODE_CONNECTOR_DPI, 2846 }; 2847 2848 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2849 .clock = 33000, 2850 .hdisplay = 800, 2851 .hsync_start = 800 + 210, 2852 .hsync_end = 800 + 210 + 30, 2853 .htotal = 800 + 210 + 30 + 16, 2854 .vdisplay = 480, 2855 .vsync_start = 480 + 22, 2856 .vsync_end = 480 + 22 + 13, 2857 .vtotal = 480 + 22 + 13 + 10, 2858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2859 }; 2860 2861 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2862 .modes = &osddisplays_osd070t1718_19ts_mode, 2863 .num_modes = 1, 2864 .bpc = 8, 2865 .size = { 2866 .width = 152, 2867 .height = 91, 2868 }, 2869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2870 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2871 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2872 .connector_type = DRM_MODE_CONNECTOR_DPI, 2873 }; 2874 2875 static const struct drm_display_mode pda_91_00156_a0_mode = { 2876 .clock = 33300, 2877 .hdisplay = 800, 2878 .hsync_start = 800 + 1, 2879 .hsync_end = 800 + 1 + 64, 2880 .htotal = 800 + 1 + 64 + 64, 2881 .vdisplay = 480, 2882 .vsync_start = 480 + 1, 2883 .vsync_end = 480 + 1 + 23, 2884 .vtotal = 480 + 1 + 23 + 22, 2885 }; 2886 2887 static const struct panel_desc pda_91_00156_a0 = { 2888 .modes = &pda_91_00156_a0_mode, 2889 .num_modes = 1, 2890 .size = { 2891 .width = 152, 2892 .height = 91, 2893 }, 2894 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2895 }; 2896 2897 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 2898 .clock = 24750, 2899 .hdisplay = 800, 2900 .hsync_start = 800 + 54, 2901 .hsync_end = 800 + 54 + 2, 2902 .htotal = 800 + 54 + 2 + 44, 2903 .vdisplay = 480, 2904 .vsync_start = 480 + 49, 2905 .vsync_end = 480 + 49 + 2, 2906 .vtotal = 480 + 49 + 2 + 22, 2907 }; 2908 2909 static const struct panel_desc powertip_ph800480t013_idf02 = { 2910 .modes = &powertip_ph800480t013_idf02_mode, 2911 .num_modes = 1, 2912 .size = { 2913 .width = 152, 2914 .height = 91, 2915 }, 2916 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2917 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2918 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2920 .connector_type = DRM_MODE_CONNECTOR_DPI, 2921 }; 2922 2923 static const struct drm_display_mode qd43003c0_40_mode = { 2924 .clock = 9000, 2925 .hdisplay = 480, 2926 .hsync_start = 480 + 8, 2927 .hsync_end = 480 + 8 + 4, 2928 .htotal = 480 + 8 + 4 + 39, 2929 .vdisplay = 272, 2930 .vsync_start = 272 + 4, 2931 .vsync_end = 272 + 4 + 10, 2932 .vtotal = 272 + 4 + 10 + 2, 2933 }; 2934 2935 static const struct panel_desc qd43003c0_40 = { 2936 .modes = &qd43003c0_40_mode, 2937 .num_modes = 1, 2938 .bpc = 8, 2939 .size = { 2940 .width = 95, 2941 .height = 53, 2942 }, 2943 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2944 }; 2945 2946 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 2947 { /* 60 Hz */ 2948 .clock = 10800, 2949 .hdisplay = 480, 2950 .hsync_start = 480 + 77, 2951 .hsync_end = 480 + 77 + 41, 2952 .htotal = 480 + 77 + 41 + 2, 2953 .vdisplay = 272, 2954 .vsync_start = 272 + 16, 2955 .vsync_end = 272 + 16 + 10, 2956 .vtotal = 272 + 16 + 10 + 2, 2957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2958 }, 2959 { /* 50 Hz */ 2960 .clock = 10800, 2961 .hdisplay = 480, 2962 .hsync_start = 480 + 17, 2963 .hsync_end = 480 + 17 + 41, 2964 .htotal = 480 + 17 + 41 + 2, 2965 .vdisplay = 272, 2966 .vsync_start = 272 + 116, 2967 .vsync_end = 272 + 116 + 10, 2968 .vtotal = 272 + 116 + 10 + 2, 2969 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2970 }, 2971 }; 2972 2973 static const struct panel_desc qishenglong_gopher2b_lcd = { 2974 .modes = qishenglong_gopher2b_lcd_modes, 2975 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 2976 .bpc = 8, 2977 .size = { 2978 .width = 95, 2979 .height = 54, 2980 }, 2981 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2982 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2983 .connector_type = DRM_MODE_CONNECTOR_DPI, 2984 }; 2985 2986 static const struct display_timing rocktech_rk070er9427_timing = { 2987 .pixelclock = { 26400000, 33300000, 46800000 }, 2988 .hactive = { 800, 800, 800 }, 2989 .hfront_porch = { 16, 210, 354 }, 2990 .hback_porch = { 46, 46, 46 }, 2991 .hsync_len = { 1, 1, 1 }, 2992 .vactive = { 480, 480, 480 }, 2993 .vfront_porch = { 7, 22, 147 }, 2994 .vback_porch = { 23, 23, 23 }, 2995 .vsync_len = { 1, 1, 1 }, 2996 .flags = DISPLAY_FLAGS_DE_HIGH, 2997 }; 2998 2999 static const struct panel_desc rocktech_rk070er9427 = { 3000 .timings = &rocktech_rk070er9427_timing, 3001 .num_timings = 1, 3002 .bpc = 6, 3003 .size = { 3004 .width = 154, 3005 .height = 86, 3006 }, 3007 .delay = { 3008 .prepare = 41, 3009 .enable = 50, 3010 .unprepare = 41, 3011 .disable = 50, 3012 }, 3013 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3014 }; 3015 3016 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3017 .clock = 71100, 3018 .hdisplay = 1280, 3019 .hsync_start = 1280 + 48, 3020 .hsync_end = 1280 + 48 + 32, 3021 .htotal = 1280 + 48 + 32 + 80, 3022 .vdisplay = 800, 3023 .vsync_start = 800 + 2, 3024 .vsync_end = 800 + 2 + 5, 3025 .vtotal = 800 + 2 + 5 + 16, 3026 }; 3027 3028 static const struct panel_desc rocktech_rk101ii01d_ct = { 3029 .modes = &rocktech_rk101ii01d_ct_mode, 3030 .num_modes = 1, 3031 .size = { 3032 .width = 217, 3033 .height = 136, 3034 }, 3035 .delay = { 3036 .prepare = 50, 3037 .disable = 50, 3038 }, 3039 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3040 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3041 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3042 }; 3043 3044 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3045 .clock = 54030, 3046 .hdisplay = 1024, 3047 .hsync_start = 1024 + 24, 3048 .hsync_end = 1024 + 24 + 136, 3049 .htotal = 1024 + 24 + 136 + 160, 3050 .vdisplay = 600, 3051 .vsync_start = 600 + 3, 3052 .vsync_end = 600 + 3 + 6, 3053 .vtotal = 600 + 3 + 6 + 61, 3054 }; 3055 3056 static const struct panel_desc samsung_ltn101nt05 = { 3057 .modes = &samsung_ltn101nt05_mode, 3058 .num_modes = 1, 3059 .bpc = 6, 3060 .size = { 3061 .width = 223, 3062 .height = 125, 3063 }, 3064 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3065 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3066 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3067 }; 3068 3069 static const struct display_timing satoz_sat050at40h12r2_timing = { 3070 .pixelclock = {33300000, 33300000, 50000000}, 3071 .hactive = {800, 800, 800}, 3072 .hfront_porch = {16, 210, 354}, 3073 .hback_porch = {46, 46, 46}, 3074 .hsync_len = {1, 1, 40}, 3075 .vactive = {480, 480, 480}, 3076 .vfront_porch = {7, 22, 147}, 3077 .vback_porch = {23, 23, 23}, 3078 .vsync_len = {1, 1, 20}, 3079 }; 3080 3081 static const struct panel_desc satoz_sat050at40h12r2 = { 3082 .timings = &satoz_sat050at40h12r2_timing, 3083 .num_timings = 1, 3084 .bpc = 8, 3085 .size = { 3086 .width = 108, 3087 .height = 65, 3088 }, 3089 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3090 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3091 }; 3092 3093 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3094 .clock = 33260, 3095 .hdisplay = 800, 3096 .hsync_start = 800 + 64, 3097 .hsync_end = 800 + 64 + 128, 3098 .htotal = 800 + 64 + 128 + 64, 3099 .vdisplay = 480, 3100 .vsync_start = 480 + 8, 3101 .vsync_end = 480 + 8 + 2, 3102 .vtotal = 480 + 8 + 2 + 35, 3103 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3104 }; 3105 3106 static const struct panel_desc sharp_lq070y3dg3b = { 3107 .modes = &sharp_lq070y3dg3b_mode, 3108 .num_modes = 1, 3109 .bpc = 8, 3110 .size = { 3111 .width = 152, /* 152.4mm */ 3112 .height = 91, /* 91.4mm */ 3113 }, 3114 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3115 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3116 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3117 }; 3118 3119 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3120 .clock = 5500, 3121 .hdisplay = 240, 3122 .hsync_start = 240 + 16, 3123 .hsync_end = 240 + 16 + 7, 3124 .htotal = 240 + 16 + 7 + 5, 3125 .vdisplay = 320, 3126 .vsync_start = 320 + 9, 3127 .vsync_end = 320 + 9 + 1, 3128 .vtotal = 320 + 9 + 1 + 7, 3129 }; 3130 3131 static const struct panel_desc sharp_lq035q7db03 = { 3132 .modes = &sharp_lq035q7db03_mode, 3133 .num_modes = 1, 3134 .bpc = 6, 3135 .size = { 3136 .width = 54, 3137 .height = 72, 3138 }, 3139 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3140 }; 3141 3142 static const struct display_timing sharp_lq101k1ly04_timing = { 3143 .pixelclock = { 60000000, 65000000, 80000000 }, 3144 .hactive = { 1280, 1280, 1280 }, 3145 .hfront_porch = { 20, 20, 20 }, 3146 .hback_porch = { 20, 20, 20 }, 3147 .hsync_len = { 10, 10, 10 }, 3148 .vactive = { 800, 800, 800 }, 3149 .vfront_porch = { 4, 4, 4 }, 3150 .vback_porch = { 4, 4, 4 }, 3151 .vsync_len = { 4, 4, 4 }, 3152 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3153 }; 3154 3155 static const struct panel_desc sharp_lq101k1ly04 = { 3156 .timings = &sharp_lq101k1ly04_timing, 3157 .num_timings = 1, 3158 .bpc = 8, 3159 .size = { 3160 .width = 217, 3161 .height = 136, 3162 }, 3163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3164 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3165 }; 3166 3167 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3168 { /* 50 Hz */ 3169 .clock = 3000, 3170 .hdisplay = 240, 3171 .hsync_start = 240 + 58, 3172 .hsync_end = 240 + 58 + 1, 3173 .htotal = 240 + 58 + 1 + 1, 3174 .vdisplay = 160, 3175 .vsync_start = 160 + 24, 3176 .vsync_end = 160 + 24 + 10, 3177 .vtotal = 160 + 24 + 10 + 6, 3178 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3179 }, 3180 { /* 60 Hz */ 3181 .clock = 3000, 3182 .hdisplay = 240, 3183 .hsync_start = 240 + 8, 3184 .hsync_end = 240 + 8 + 1, 3185 .htotal = 240 + 8 + 1 + 1, 3186 .vdisplay = 160, 3187 .vsync_start = 160 + 24, 3188 .vsync_end = 160 + 24 + 10, 3189 .vtotal = 160 + 24 + 10 + 6, 3190 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3191 }, 3192 }; 3193 3194 static const struct panel_desc sharp_ls020b1dd01d = { 3195 .modes = sharp_ls020b1dd01d_modes, 3196 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3197 .bpc = 6, 3198 .size = { 3199 .width = 42, 3200 .height = 28, 3201 }, 3202 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3203 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3204 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3205 | DRM_BUS_FLAG_SHARP_SIGNALS, 3206 }; 3207 3208 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3209 .clock = 33300, 3210 .hdisplay = 800, 3211 .hsync_start = 800 + 1, 3212 .hsync_end = 800 + 1 + 64, 3213 .htotal = 800 + 1 + 64 + 64, 3214 .vdisplay = 480, 3215 .vsync_start = 480 + 1, 3216 .vsync_end = 480 + 1 + 23, 3217 .vtotal = 480 + 1 + 23 + 22, 3218 }; 3219 3220 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3221 .modes = &shelly_sca07010_bfn_lnn_mode, 3222 .num_modes = 1, 3223 .size = { 3224 .width = 152, 3225 .height = 91, 3226 }, 3227 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3228 }; 3229 3230 static const struct drm_display_mode starry_kr070pe2t_mode = { 3231 .clock = 33000, 3232 .hdisplay = 800, 3233 .hsync_start = 800 + 209, 3234 .hsync_end = 800 + 209 + 1, 3235 .htotal = 800 + 209 + 1 + 45, 3236 .vdisplay = 480, 3237 .vsync_start = 480 + 22, 3238 .vsync_end = 480 + 22 + 1, 3239 .vtotal = 480 + 22 + 1 + 22, 3240 }; 3241 3242 static const struct panel_desc starry_kr070pe2t = { 3243 .modes = &starry_kr070pe2t_mode, 3244 .num_modes = 1, 3245 .bpc = 8, 3246 .size = { 3247 .width = 152, 3248 .height = 86, 3249 }, 3250 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3251 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3252 .connector_type = DRM_MODE_CONNECTOR_DPI, 3253 }; 3254 3255 static const struct display_timing tsd_tst043015cmhx_timing = { 3256 .pixelclock = { 5000000, 9000000, 12000000 }, 3257 .hactive = { 480, 480, 480 }, 3258 .hfront_porch = { 4, 5, 65 }, 3259 .hback_porch = { 36, 40, 255 }, 3260 .hsync_len = { 1, 1, 1 }, 3261 .vactive = { 272, 272, 272 }, 3262 .vfront_porch = { 2, 8, 97 }, 3263 .vback_porch = { 3, 8, 31 }, 3264 .vsync_len = { 1, 1, 1 }, 3265 3266 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3267 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3268 }; 3269 3270 static const struct panel_desc tsd_tst043015cmhx = { 3271 .timings = &tsd_tst043015cmhx_timing, 3272 .num_timings = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 105, 3276 .height = 67, 3277 }, 3278 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3279 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3280 }; 3281 3282 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3283 .clock = 30000, 3284 .hdisplay = 800, 3285 .hsync_start = 800 + 39, 3286 .hsync_end = 800 + 39 + 47, 3287 .htotal = 800 + 39 + 47 + 39, 3288 .vdisplay = 480, 3289 .vsync_start = 480 + 13, 3290 .vsync_end = 480 + 13 + 2, 3291 .vtotal = 480 + 13 + 2 + 29, 3292 }; 3293 3294 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3295 .modes = &tfc_s9700rtwv43tr_01b_mode, 3296 .num_modes = 1, 3297 .bpc = 8, 3298 .size = { 3299 .width = 155, 3300 .height = 90, 3301 }, 3302 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3303 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3304 }; 3305 3306 static const struct display_timing tianma_tm070jdhg30_timing = { 3307 .pixelclock = { 62600000, 68200000, 78100000 }, 3308 .hactive = { 1280, 1280, 1280 }, 3309 .hfront_porch = { 15, 64, 159 }, 3310 .hback_porch = { 5, 5, 5 }, 3311 .hsync_len = { 1, 1, 256 }, 3312 .vactive = { 800, 800, 800 }, 3313 .vfront_porch = { 3, 40, 99 }, 3314 .vback_porch = { 2, 2, 2 }, 3315 .vsync_len = { 1, 1, 128 }, 3316 .flags = DISPLAY_FLAGS_DE_HIGH, 3317 }; 3318 3319 static const struct panel_desc tianma_tm070jdhg30 = { 3320 .timings = &tianma_tm070jdhg30_timing, 3321 .num_timings = 1, 3322 .bpc = 8, 3323 .size = { 3324 .width = 151, 3325 .height = 95, 3326 }, 3327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3329 }; 3330 3331 static const struct panel_desc tianma_tm070jvhg33 = { 3332 .timings = &tianma_tm070jdhg30_timing, 3333 .num_timings = 1, 3334 .bpc = 8, 3335 .size = { 3336 .width = 150, 3337 .height = 94, 3338 }, 3339 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3340 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3341 }; 3342 3343 static const struct display_timing tianma_tm070rvhg71_timing = { 3344 .pixelclock = { 27700000, 29200000, 39600000 }, 3345 .hactive = { 800, 800, 800 }, 3346 .hfront_porch = { 12, 40, 212 }, 3347 .hback_porch = { 88, 88, 88 }, 3348 .hsync_len = { 1, 1, 40 }, 3349 .vactive = { 480, 480, 480 }, 3350 .vfront_porch = { 1, 13, 88 }, 3351 .vback_porch = { 32, 32, 32 }, 3352 .vsync_len = { 1, 1, 3 }, 3353 .flags = DISPLAY_FLAGS_DE_HIGH, 3354 }; 3355 3356 static const struct panel_desc tianma_tm070rvhg71 = { 3357 .timings = &tianma_tm070rvhg71_timing, 3358 .num_timings = 1, 3359 .bpc = 8, 3360 .size = { 3361 .width = 154, 3362 .height = 86, 3363 }, 3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3365 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3366 }; 3367 3368 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3369 { 3370 .clock = 10000, 3371 .hdisplay = 320, 3372 .hsync_start = 320 + 50, 3373 .hsync_end = 320 + 50 + 6, 3374 .htotal = 320 + 50 + 6 + 38, 3375 .vdisplay = 240, 3376 .vsync_start = 240 + 3, 3377 .vsync_end = 240 + 3 + 1, 3378 .vtotal = 240 + 3 + 1 + 17, 3379 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3380 }, 3381 }; 3382 3383 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3384 .modes = ti_nspire_cx_lcd_mode, 3385 .num_modes = 1, 3386 .bpc = 8, 3387 .size = { 3388 .width = 65, 3389 .height = 49, 3390 }, 3391 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3392 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3393 }; 3394 3395 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3396 { 3397 .clock = 10000, 3398 .hdisplay = 320, 3399 .hsync_start = 320 + 6, 3400 .hsync_end = 320 + 6 + 6, 3401 .htotal = 320 + 6 + 6 + 6, 3402 .vdisplay = 240, 3403 .vsync_start = 240 + 0, 3404 .vsync_end = 240 + 0 + 1, 3405 .vtotal = 240 + 0 + 1 + 0, 3406 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3407 }, 3408 }; 3409 3410 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3411 .modes = ti_nspire_classic_lcd_mode, 3412 .num_modes = 1, 3413 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3414 .bpc = 8, 3415 .size = { 3416 .width = 71, 3417 .height = 53, 3418 }, 3419 /* This is the grayscale bus format */ 3420 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3421 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3422 }; 3423 3424 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3425 .clock = 79500, 3426 .hdisplay = 1280, 3427 .hsync_start = 1280 + 192, 3428 .hsync_end = 1280 + 192 + 128, 3429 .htotal = 1280 + 192 + 128 + 64, 3430 .vdisplay = 768, 3431 .vsync_start = 768 + 20, 3432 .vsync_end = 768 + 20 + 7, 3433 .vtotal = 768 + 20 + 7 + 3, 3434 }; 3435 3436 static const struct panel_desc toshiba_lt089ac29000 = { 3437 .modes = &toshiba_lt089ac29000_mode, 3438 .num_modes = 1, 3439 .size = { 3440 .width = 194, 3441 .height = 116, 3442 }, 3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3444 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3445 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3446 }; 3447 3448 static const struct drm_display_mode tpk_f07a_0102_mode = { 3449 .clock = 33260, 3450 .hdisplay = 800, 3451 .hsync_start = 800 + 40, 3452 .hsync_end = 800 + 40 + 128, 3453 .htotal = 800 + 40 + 128 + 88, 3454 .vdisplay = 480, 3455 .vsync_start = 480 + 10, 3456 .vsync_end = 480 + 10 + 2, 3457 .vtotal = 480 + 10 + 2 + 33, 3458 }; 3459 3460 static const struct panel_desc tpk_f07a_0102 = { 3461 .modes = &tpk_f07a_0102_mode, 3462 .num_modes = 1, 3463 .size = { 3464 .width = 152, 3465 .height = 91, 3466 }, 3467 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3468 }; 3469 3470 static const struct drm_display_mode tpk_f10a_0102_mode = { 3471 .clock = 45000, 3472 .hdisplay = 1024, 3473 .hsync_start = 1024 + 176, 3474 .hsync_end = 1024 + 176 + 5, 3475 .htotal = 1024 + 176 + 5 + 88, 3476 .vdisplay = 600, 3477 .vsync_start = 600 + 20, 3478 .vsync_end = 600 + 20 + 5, 3479 .vtotal = 600 + 20 + 5 + 25, 3480 }; 3481 3482 static const struct panel_desc tpk_f10a_0102 = { 3483 .modes = &tpk_f10a_0102_mode, 3484 .num_modes = 1, 3485 .size = { 3486 .width = 223, 3487 .height = 125, 3488 }, 3489 }; 3490 3491 static const struct display_timing urt_umsh_8596md_timing = { 3492 .pixelclock = { 33260000, 33260000, 33260000 }, 3493 .hactive = { 800, 800, 800 }, 3494 .hfront_porch = { 41, 41, 41 }, 3495 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3496 .hsync_len = { 71, 128, 128 }, 3497 .vactive = { 480, 480, 480 }, 3498 .vfront_porch = { 10, 10, 10 }, 3499 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3500 .vsync_len = { 2, 2, 2 }, 3501 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3502 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3503 }; 3504 3505 static const struct panel_desc urt_umsh_8596md_lvds = { 3506 .timings = &urt_umsh_8596md_timing, 3507 .num_timings = 1, 3508 .bpc = 6, 3509 .size = { 3510 .width = 152, 3511 .height = 91, 3512 }, 3513 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3514 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3515 }; 3516 3517 static const struct panel_desc urt_umsh_8596md_parallel = { 3518 .timings = &urt_umsh_8596md_timing, 3519 .num_timings = 1, 3520 .bpc = 6, 3521 .size = { 3522 .width = 152, 3523 .height = 91, 3524 }, 3525 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3526 }; 3527 3528 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3529 .clock = 60000, 3530 .hdisplay = 1024, 3531 .hsync_start = 1024 + 160, 3532 .hsync_end = 1024 + 160 + 100, 3533 .htotal = 1024 + 160 + 100 + 60, 3534 .vdisplay = 600, 3535 .vsync_start = 600 + 12, 3536 .vsync_end = 600 + 12 + 10, 3537 .vtotal = 600 + 12 + 10 + 13, 3538 }; 3539 3540 static const struct panel_desc vivax_tpc9150_panel = { 3541 .modes = &vivax_tpc9150_panel_mode, 3542 .num_modes = 1, 3543 .bpc = 6, 3544 .size = { 3545 .width = 200, 3546 .height = 115, 3547 }, 3548 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3549 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3551 }; 3552 3553 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3554 .clock = 33333, 3555 .hdisplay = 800, 3556 .hsync_start = 800 + 210, 3557 .hsync_end = 800 + 210 + 20, 3558 .htotal = 800 + 210 + 20 + 46, 3559 .vdisplay = 480, 3560 .vsync_start = 480 + 22, 3561 .vsync_end = 480 + 22 + 10, 3562 .vtotal = 480 + 22 + 10 + 23, 3563 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3564 }; 3565 3566 static const struct panel_desc vl050_8048nt_c01 = { 3567 .modes = &vl050_8048nt_c01_mode, 3568 .num_modes = 1, 3569 .bpc = 8, 3570 .size = { 3571 .width = 120, 3572 .height = 76, 3573 }, 3574 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3575 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3576 }; 3577 3578 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3579 .clock = 6410, 3580 .hdisplay = 320, 3581 .hsync_start = 320 + 20, 3582 .hsync_end = 320 + 20 + 30, 3583 .htotal = 320 + 20 + 30 + 38, 3584 .vdisplay = 240, 3585 .vsync_start = 240 + 4, 3586 .vsync_end = 240 + 4 + 3, 3587 .vtotal = 240 + 4 + 3 + 15, 3588 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3589 }; 3590 3591 static const struct panel_desc winstar_wf35ltiacd = { 3592 .modes = &winstar_wf35ltiacd_mode, 3593 .num_modes = 1, 3594 .bpc = 8, 3595 .size = { 3596 .width = 70, 3597 .height = 53, 3598 }, 3599 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3600 }; 3601 3602 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3603 .clock = 51200, 3604 .hdisplay = 1024, 3605 .hsync_start = 1024 + 100, 3606 .hsync_end = 1024 + 100 + 100, 3607 .htotal = 1024 + 100 + 100 + 120, 3608 .vdisplay = 600, 3609 .vsync_start = 600 + 10, 3610 .vsync_end = 600 + 10 + 10, 3611 .vtotal = 600 + 10 + 10 + 15, 3612 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3613 }; 3614 3615 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3616 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3617 .num_modes = 1, 3618 .bpc = 8, 3619 .size = { 3620 .width = 154, 3621 .height = 90, 3622 }, 3623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3624 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3625 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3626 }; 3627 3628 static const struct drm_display_mode arm_rtsm_mode[] = { 3629 { 3630 .clock = 65000, 3631 .hdisplay = 1024, 3632 .hsync_start = 1024 + 24, 3633 .hsync_end = 1024 + 24 + 136, 3634 .htotal = 1024 + 24 + 136 + 160, 3635 .vdisplay = 768, 3636 .vsync_start = 768 + 3, 3637 .vsync_end = 768 + 3 + 6, 3638 .vtotal = 768 + 3 + 6 + 29, 3639 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3640 }, 3641 }; 3642 3643 static const struct panel_desc arm_rtsm = { 3644 .modes = arm_rtsm_mode, 3645 .num_modes = 1, 3646 .bpc = 8, 3647 .size = { 3648 .width = 400, 3649 .height = 300, 3650 }, 3651 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3652 }; 3653 3654 static const struct of_device_id platform_of_match[] = { 3655 { 3656 .compatible = "ampire,am-1280800n3tzqw-t00h", 3657 .data = &ire_am_1280800n3tzqw_t00h, 3658 }, { 3659 .compatible = "ampire,am-480272h3tmqw-t01h", 3660 .data = &ire_am_480272h3tmqw_t01h, 3661 }, { 3662 .compatible = "ampire,am800480r3tmqwa1h", 3663 .data = &ire_am800480r3tmqwa1h, 3664 }, { 3665 .compatible = "arm,rtsm-display", 3666 .data = &arm_rtsm, 3667 }, { 3668 .compatible = "armadeus,st0700-adapt", 3669 .data = &armadeus_st0700_adapt, 3670 }, { 3671 .compatible = "auo,b101aw03", 3672 .data = &auo_b101aw03, 3673 }, { 3674 .compatible = "auo,b101xtn01", 3675 .data = &auo_b101xtn01, 3676 }, { 3677 .compatible = "auo,g070vvn01", 3678 .data = &auo_g070vvn01, 3679 }, { 3680 .compatible = "auo,g101evn010", 3681 .data = &auo_g101evn010, 3682 }, { 3683 .compatible = "auo,g104sn02", 3684 .data = &auo_g104sn02, 3685 }, { 3686 .compatible = "auo,g121ean01", 3687 .data = &auo_g121ean01, 3688 }, { 3689 .compatible = "auo,g133han01", 3690 .data = &auo_g133han01, 3691 }, { 3692 .compatible = "auo,g156xtn01", 3693 .data = &auo_g156xtn01, 3694 }, { 3695 .compatible = "auo,g185han01", 3696 .data = &auo_g185han01, 3697 }, { 3698 .compatible = "auo,g190ean01", 3699 .data = &auo_g190ean01, 3700 }, { 3701 .compatible = "auo,p320hvn03", 3702 .data = &auo_p320hvn03, 3703 }, { 3704 .compatible = "auo,t215hvn01", 3705 .data = &auo_t215hvn01, 3706 }, { 3707 .compatible = "avic,tm070ddh03", 3708 .data = &avic_tm070ddh03, 3709 }, { 3710 .compatible = "bananapi,s070wv20-ct16", 3711 .data = &bananapi_s070wv20_ct16, 3712 }, { 3713 .compatible = "boe,hv070wsa-100", 3714 .data = &boe_hv070wsa 3715 }, { 3716 .compatible = "cdtech,s043wq26h-ct7", 3717 .data = &cdtech_s043wq26h_ct7, 3718 }, { 3719 .compatible = "cdtech,s070pws19hp-fc21", 3720 .data = &cdtech_s070pws19hp_fc21, 3721 }, { 3722 .compatible = "cdtech,s070swv29hg-dc44", 3723 .data = &cdtech_s070swv29hg_dc44, 3724 }, { 3725 .compatible = "cdtech,s070wv95-ct16", 3726 .data = &cdtech_s070wv95_ct16, 3727 }, { 3728 .compatible = "chefree,ch101olhlwh-002", 3729 .data = &chefree_ch101olhlwh_002, 3730 }, { 3731 .compatible = "chunghwa,claa070wp03xg", 3732 .data = &chunghwa_claa070wp03xg, 3733 }, { 3734 .compatible = "chunghwa,claa101wa01a", 3735 .data = &chunghwa_claa101wa01a 3736 }, { 3737 .compatible = "chunghwa,claa101wb01", 3738 .data = &chunghwa_claa101wb01 3739 }, { 3740 .compatible = "dataimage,scf0700c48ggu18", 3741 .data = &dataimage_scf0700c48ggu18, 3742 }, { 3743 .compatible = "dlc,dlc0700yzg-1", 3744 .data = &dlc_dlc0700yzg_1, 3745 }, { 3746 .compatible = "dlc,dlc1010gig", 3747 .data = &dlc_dlc1010gig, 3748 }, { 3749 .compatible = "edt,et035012dm6", 3750 .data = &edt_et035012dm6, 3751 }, { 3752 .compatible = "edt,etm0350g0dh6", 3753 .data = &edt_etm0350g0dh6, 3754 }, { 3755 .compatible = "edt,etm043080dh6gp", 3756 .data = &edt_etm043080dh6gp, 3757 }, { 3758 .compatible = "edt,etm0430g0dh6", 3759 .data = &edt_etm0430g0dh6, 3760 }, { 3761 .compatible = "edt,et057090dhu", 3762 .data = &edt_et057090dhu, 3763 }, { 3764 .compatible = "edt,et070080dh6", 3765 .data = &edt_etm0700g0dh6, 3766 }, { 3767 .compatible = "edt,etm0700g0dh6", 3768 .data = &edt_etm0700g0dh6, 3769 }, { 3770 .compatible = "edt,etm0700g0bdh6", 3771 .data = &edt_etm0700g0bdh6, 3772 }, { 3773 .compatible = "edt,etm0700g0edh6", 3774 .data = &edt_etm0700g0bdh6, 3775 }, { 3776 .compatible = "edt,etmv570g2dhu", 3777 .data = &edt_etmv570g2dhu, 3778 }, { 3779 .compatible = "eink,vb3300-kca", 3780 .data = &eink_vb3300_kca, 3781 }, { 3782 .compatible = "evervision,vgg804821", 3783 .data = &evervision_vgg804821, 3784 }, { 3785 .compatible = "foxlink,fl500wvr00-a0t", 3786 .data = &foxlink_fl500wvr00_a0t, 3787 }, { 3788 .compatible = "frida,frd350h54004", 3789 .data = &frida_frd350h54004, 3790 }, { 3791 .compatible = "friendlyarm,hd702e", 3792 .data = &friendlyarm_hd702e, 3793 }, { 3794 .compatible = "giantplus,gpg482739qs5", 3795 .data = &giantplus_gpg482739qs5 3796 }, { 3797 .compatible = "giantplus,gpm940b0", 3798 .data = &giantplus_gpm940b0, 3799 }, { 3800 .compatible = "hannstar,hsd070pww1", 3801 .data = &hannstar_hsd070pww1, 3802 }, { 3803 .compatible = "hannstar,hsd100pxn1", 3804 .data = &hannstar_hsd100pxn1, 3805 }, { 3806 .compatible = "hit,tx23d38vm0caa", 3807 .data = &hitachi_tx23d38vm0caa 3808 }, { 3809 .compatible = "innolux,at043tn24", 3810 .data = &innolux_at043tn24, 3811 }, { 3812 .compatible = "innolux,at070tn92", 3813 .data = &innolux_at070tn92, 3814 }, { 3815 .compatible = "innolux,g070y2-l01", 3816 .data = &innolux_g070y2_l01, 3817 }, { 3818 .compatible = "innolux,g070y2-t02", 3819 .data = &innolux_g070y2_t02, 3820 }, { 3821 .compatible = "innolux,g101ice-l01", 3822 .data = &innolux_g101ice_l01 3823 }, { 3824 .compatible = "innolux,g121i1-l01", 3825 .data = &innolux_g121i1_l01 3826 }, { 3827 .compatible = "innolux,g121x1-l03", 3828 .data = &innolux_g121x1_l03, 3829 }, { 3830 .compatible = "innolux,n156bge-l21", 3831 .data = &innolux_n156bge_l21, 3832 }, { 3833 .compatible = "innolux,zj070na-01p", 3834 .data = &innolux_zj070na_01p, 3835 }, { 3836 .compatible = "koe,tx14d24vm1bpa", 3837 .data = &koe_tx14d24vm1bpa, 3838 }, { 3839 .compatible = "koe,tx26d202vm0bwa", 3840 .data = &koe_tx26d202vm0bwa, 3841 }, { 3842 .compatible = "koe,tx31d200vm0baa", 3843 .data = &koe_tx31d200vm0baa, 3844 }, { 3845 .compatible = "kyo,tcg121xglp", 3846 .data = &kyo_tcg121xglp, 3847 }, { 3848 .compatible = "lemaker,bl035-rgb-002", 3849 .data = &lemaker_bl035_rgb_002, 3850 }, { 3851 .compatible = "lg,lb070wv8", 3852 .data = &lg_lb070wv8, 3853 }, { 3854 .compatible = "logicpd,type28", 3855 .data = &logicpd_type_28, 3856 }, { 3857 .compatible = "logictechno,lt161010-2nhc", 3858 .data = &logictechno_lt161010_2nh, 3859 }, { 3860 .compatible = "logictechno,lt161010-2nhr", 3861 .data = &logictechno_lt161010_2nh, 3862 }, { 3863 .compatible = "logictechno,lt170410-2whc", 3864 .data = &logictechno_lt170410_2whc, 3865 }, { 3866 .compatible = "logictechno,lttd800480070-l2rt", 3867 .data = &logictechno_lttd800480070_l2rt, 3868 }, { 3869 .compatible = "logictechno,lttd800480070-l6wh-rt", 3870 .data = &logictechno_lttd800480070_l6wh_rt, 3871 }, { 3872 .compatible = "mitsubishi,aa070mc01-ca1", 3873 .data = &mitsubishi_aa070mc01, 3874 }, { 3875 .compatible = "multi-inno,mi1010ait-1cp", 3876 .data = &multi_inno_mi1010ait_1cp, 3877 }, { 3878 .compatible = "nec,nl12880bc20-05", 3879 .data = &nec_nl12880bc20_05, 3880 }, { 3881 .compatible = "nec,nl4827hc19-05b", 3882 .data = &nec_nl4827hc19_05b, 3883 }, { 3884 .compatible = "netron-dy,e231732", 3885 .data = &netron_dy_e231732, 3886 }, { 3887 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3888 .data = &newhaven_nhd_43_480272ef_atxl, 3889 }, { 3890 .compatible = "nlt,nl192108ac18-02d", 3891 .data = &nlt_nl192108ac18_02d, 3892 }, { 3893 .compatible = "nvd,9128", 3894 .data = &nvd_9128, 3895 }, { 3896 .compatible = "okaya,rs800480t-7x0gp", 3897 .data = &okaya_rs800480t_7x0gp, 3898 }, { 3899 .compatible = "olimex,lcd-olinuxino-43-ts", 3900 .data = &olimex_lcd_olinuxino_43ts, 3901 }, { 3902 .compatible = "ontat,yx700wv03", 3903 .data = &ontat_yx700wv03, 3904 }, { 3905 .compatible = "ortustech,com37h3m05dtc", 3906 .data = &ortustech_com37h3m, 3907 }, { 3908 .compatible = "ortustech,com37h3m99dtc", 3909 .data = &ortustech_com37h3m, 3910 }, { 3911 .compatible = "ortustech,com43h4m85ulc", 3912 .data = &ortustech_com43h4m85ulc, 3913 }, { 3914 .compatible = "osddisplays,osd070t1718-19ts", 3915 .data = &osddisplays_osd070t1718_19ts, 3916 }, { 3917 .compatible = "pda,91-00156-a0", 3918 .data = &pda_91_00156_a0, 3919 }, { 3920 .compatible = "powertip,ph800480t013-idf02", 3921 .data = &powertip_ph800480t013_idf02, 3922 }, { 3923 .compatible = "qiaodian,qd43003c0-40", 3924 .data = &qd43003c0_40, 3925 }, { 3926 .compatible = "qishenglong,gopher2b-lcd", 3927 .data = &qishenglong_gopher2b_lcd, 3928 }, { 3929 .compatible = "rocktech,rk070er9427", 3930 .data = &rocktech_rk070er9427, 3931 }, { 3932 .compatible = "rocktech,rk101ii01d-ct", 3933 .data = &rocktech_rk101ii01d_ct, 3934 }, { 3935 .compatible = "samsung,ltn101nt05", 3936 .data = &samsung_ltn101nt05, 3937 }, { 3938 .compatible = "satoz,sat050at40h12r2", 3939 .data = &satoz_sat050at40h12r2, 3940 }, { 3941 .compatible = "sharp,lq035q7db03", 3942 .data = &sharp_lq035q7db03, 3943 }, { 3944 .compatible = "sharp,lq070y3dg3b", 3945 .data = &sharp_lq070y3dg3b, 3946 }, { 3947 .compatible = "sharp,lq101k1ly04", 3948 .data = &sharp_lq101k1ly04, 3949 }, { 3950 .compatible = "sharp,ls020b1dd01d", 3951 .data = &sharp_ls020b1dd01d, 3952 }, { 3953 .compatible = "shelly,sca07010-bfn-lnn", 3954 .data = &shelly_sca07010_bfn_lnn, 3955 }, { 3956 .compatible = "starry,kr070pe2t", 3957 .data = &starry_kr070pe2t, 3958 }, { 3959 .compatible = "team-source-display,tst043015cmhx", 3960 .data = &tsd_tst043015cmhx, 3961 }, { 3962 .compatible = "tfc,s9700rtwv43tr-01b", 3963 .data = &tfc_s9700rtwv43tr_01b, 3964 }, { 3965 .compatible = "tianma,tm070jdhg30", 3966 .data = &tianma_tm070jdhg30, 3967 }, { 3968 .compatible = "tianma,tm070jvhg33", 3969 .data = &tianma_tm070jvhg33, 3970 }, { 3971 .compatible = "tianma,tm070rvhg71", 3972 .data = &tianma_tm070rvhg71, 3973 }, { 3974 .compatible = "ti,nspire-cx-lcd-panel", 3975 .data = &ti_nspire_cx_lcd_panel, 3976 }, { 3977 .compatible = "ti,nspire-classic-lcd-panel", 3978 .data = &ti_nspire_classic_lcd_panel, 3979 }, { 3980 .compatible = "toshiba,lt089ac29000", 3981 .data = &toshiba_lt089ac29000, 3982 }, { 3983 .compatible = "tpk,f07a-0102", 3984 .data = &tpk_f07a_0102, 3985 }, { 3986 .compatible = "tpk,f10a-0102", 3987 .data = &tpk_f10a_0102, 3988 }, { 3989 .compatible = "urt,umsh-8596md-t", 3990 .data = &urt_umsh_8596md_parallel, 3991 }, { 3992 .compatible = "urt,umsh-8596md-1t", 3993 .data = &urt_umsh_8596md_parallel, 3994 }, { 3995 .compatible = "urt,umsh-8596md-7t", 3996 .data = &urt_umsh_8596md_parallel, 3997 }, { 3998 .compatible = "urt,umsh-8596md-11t", 3999 .data = &urt_umsh_8596md_lvds, 4000 }, { 4001 .compatible = "urt,umsh-8596md-19t", 4002 .data = &urt_umsh_8596md_lvds, 4003 }, { 4004 .compatible = "urt,umsh-8596md-20t", 4005 .data = &urt_umsh_8596md_parallel, 4006 }, { 4007 .compatible = "vivax,tpc9150-panel", 4008 .data = &vivax_tpc9150_panel, 4009 }, { 4010 .compatible = "vxt,vl050-8048nt-c01", 4011 .data = &vl050_8048nt_c01, 4012 }, { 4013 .compatible = "winstar,wf35ltiacd", 4014 .data = &winstar_wf35ltiacd, 4015 }, { 4016 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4017 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4018 }, { 4019 /* Must be the last entry */ 4020 .compatible = "panel-dpi", 4021 .data = &panel_dpi, 4022 }, { 4023 /* sentinel */ 4024 } 4025 }; 4026 MODULE_DEVICE_TABLE(of, platform_of_match); 4027 4028 static int panel_simple_platform_probe(struct platform_device *pdev) 4029 { 4030 const struct of_device_id *id; 4031 4032 id = of_match_node(platform_of_match, pdev->dev.of_node); 4033 if (!id) 4034 return -ENODEV; 4035 4036 return panel_simple_probe(&pdev->dev, id->data); 4037 } 4038 4039 static int panel_simple_platform_remove(struct platform_device *pdev) 4040 { 4041 return panel_simple_remove(&pdev->dev); 4042 } 4043 4044 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4045 { 4046 panel_simple_shutdown(&pdev->dev); 4047 } 4048 4049 static const struct dev_pm_ops panel_simple_pm_ops = { 4050 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4051 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4052 pm_runtime_force_resume) 4053 }; 4054 4055 static struct platform_driver panel_simple_platform_driver = { 4056 .driver = { 4057 .name = "panel-simple", 4058 .of_match_table = platform_of_match, 4059 .pm = &panel_simple_pm_ops, 4060 }, 4061 .probe = panel_simple_platform_probe, 4062 .remove = panel_simple_platform_remove, 4063 .shutdown = panel_simple_platform_shutdown, 4064 }; 4065 4066 struct panel_desc_dsi { 4067 struct panel_desc desc; 4068 4069 unsigned long flags; 4070 enum mipi_dsi_pixel_format format; 4071 unsigned int lanes; 4072 }; 4073 4074 static const struct drm_display_mode auo_b080uan01_mode = { 4075 .clock = 154500, 4076 .hdisplay = 1200, 4077 .hsync_start = 1200 + 62, 4078 .hsync_end = 1200 + 62 + 4, 4079 .htotal = 1200 + 62 + 4 + 62, 4080 .vdisplay = 1920, 4081 .vsync_start = 1920 + 9, 4082 .vsync_end = 1920 + 9 + 2, 4083 .vtotal = 1920 + 9 + 2 + 8, 4084 }; 4085 4086 static const struct panel_desc_dsi auo_b080uan01 = { 4087 .desc = { 4088 .modes = &auo_b080uan01_mode, 4089 .num_modes = 1, 4090 .bpc = 8, 4091 .size = { 4092 .width = 108, 4093 .height = 272, 4094 }, 4095 .connector_type = DRM_MODE_CONNECTOR_DSI, 4096 }, 4097 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4098 .format = MIPI_DSI_FMT_RGB888, 4099 .lanes = 4, 4100 }; 4101 4102 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4103 .clock = 160000, 4104 .hdisplay = 1200, 4105 .hsync_start = 1200 + 120, 4106 .hsync_end = 1200 + 120 + 20, 4107 .htotal = 1200 + 120 + 20 + 21, 4108 .vdisplay = 1920, 4109 .vsync_start = 1920 + 21, 4110 .vsync_end = 1920 + 21 + 3, 4111 .vtotal = 1920 + 21 + 3 + 18, 4112 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4113 }; 4114 4115 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4116 .desc = { 4117 .modes = &boe_tv080wum_nl0_mode, 4118 .num_modes = 1, 4119 .size = { 4120 .width = 107, 4121 .height = 172, 4122 }, 4123 .connector_type = DRM_MODE_CONNECTOR_DSI, 4124 }, 4125 .flags = MIPI_DSI_MODE_VIDEO | 4126 MIPI_DSI_MODE_VIDEO_BURST | 4127 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4128 .format = MIPI_DSI_FMT_RGB888, 4129 .lanes = 4, 4130 }; 4131 4132 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4133 .clock = 71000, 4134 .hdisplay = 800, 4135 .hsync_start = 800 + 32, 4136 .hsync_end = 800 + 32 + 1, 4137 .htotal = 800 + 32 + 1 + 57, 4138 .vdisplay = 1280, 4139 .vsync_start = 1280 + 28, 4140 .vsync_end = 1280 + 28 + 1, 4141 .vtotal = 1280 + 28 + 1 + 14, 4142 }; 4143 4144 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4145 .desc = { 4146 .modes = &lg_ld070wx3_sl01_mode, 4147 .num_modes = 1, 4148 .bpc = 8, 4149 .size = { 4150 .width = 94, 4151 .height = 151, 4152 }, 4153 .connector_type = DRM_MODE_CONNECTOR_DSI, 4154 }, 4155 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4156 .format = MIPI_DSI_FMT_RGB888, 4157 .lanes = 4, 4158 }; 4159 4160 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4161 .clock = 67000, 4162 .hdisplay = 720, 4163 .hsync_start = 720 + 12, 4164 .hsync_end = 720 + 12 + 4, 4165 .htotal = 720 + 12 + 4 + 112, 4166 .vdisplay = 1280, 4167 .vsync_start = 1280 + 8, 4168 .vsync_end = 1280 + 8 + 4, 4169 .vtotal = 1280 + 8 + 4 + 12, 4170 }; 4171 4172 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4173 .desc = { 4174 .modes = &lg_lh500wx1_sd03_mode, 4175 .num_modes = 1, 4176 .bpc = 8, 4177 .size = { 4178 .width = 62, 4179 .height = 110, 4180 }, 4181 .connector_type = DRM_MODE_CONNECTOR_DSI, 4182 }, 4183 .flags = MIPI_DSI_MODE_VIDEO, 4184 .format = MIPI_DSI_FMT_RGB888, 4185 .lanes = 4, 4186 }; 4187 4188 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4189 .clock = 157200, 4190 .hdisplay = 1920, 4191 .hsync_start = 1920 + 154, 4192 .hsync_end = 1920 + 154 + 16, 4193 .htotal = 1920 + 154 + 16 + 32, 4194 .vdisplay = 1200, 4195 .vsync_start = 1200 + 17, 4196 .vsync_end = 1200 + 17 + 2, 4197 .vtotal = 1200 + 17 + 2 + 16, 4198 }; 4199 4200 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4201 .desc = { 4202 .modes = &panasonic_vvx10f004b00_mode, 4203 .num_modes = 1, 4204 .bpc = 8, 4205 .size = { 4206 .width = 217, 4207 .height = 136, 4208 }, 4209 .connector_type = DRM_MODE_CONNECTOR_DSI, 4210 }, 4211 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4212 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4213 .format = MIPI_DSI_FMT_RGB888, 4214 .lanes = 4, 4215 }; 4216 4217 static const struct drm_display_mode lg_acx467akm_7_mode = { 4218 .clock = 150000, 4219 .hdisplay = 1080, 4220 .hsync_start = 1080 + 2, 4221 .hsync_end = 1080 + 2 + 2, 4222 .htotal = 1080 + 2 + 2 + 2, 4223 .vdisplay = 1920, 4224 .vsync_start = 1920 + 2, 4225 .vsync_end = 1920 + 2 + 2, 4226 .vtotal = 1920 + 2 + 2 + 2, 4227 }; 4228 4229 static const struct panel_desc_dsi lg_acx467akm_7 = { 4230 .desc = { 4231 .modes = &lg_acx467akm_7_mode, 4232 .num_modes = 1, 4233 .bpc = 8, 4234 .size = { 4235 .width = 62, 4236 .height = 110, 4237 }, 4238 .connector_type = DRM_MODE_CONNECTOR_DSI, 4239 }, 4240 .flags = 0, 4241 .format = MIPI_DSI_FMT_RGB888, 4242 .lanes = 4, 4243 }; 4244 4245 static const struct drm_display_mode osd101t2045_53ts_mode = { 4246 .clock = 154500, 4247 .hdisplay = 1920, 4248 .hsync_start = 1920 + 112, 4249 .hsync_end = 1920 + 112 + 16, 4250 .htotal = 1920 + 112 + 16 + 32, 4251 .vdisplay = 1200, 4252 .vsync_start = 1200 + 16, 4253 .vsync_end = 1200 + 16 + 2, 4254 .vtotal = 1200 + 16 + 2 + 16, 4255 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4256 }; 4257 4258 static const struct panel_desc_dsi osd101t2045_53ts = { 4259 .desc = { 4260 .modes = &osd101t2045_53ts_mode, 4261 .num_modes = 1, 4262 .bpc = 8, 4263 .size = { 4264 .width = 217, 4265 .height = 136, 4266 }, 4267 .connector_type = DRM_MODE_CONNECTOR_DSI, 4268 }, 4269 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4270 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4271 MIPI_DSI_MODE_NO_EOT_PACKET, 4272 .format = MIPI_DSI_FMT_RGB888, 4273 .lanes = 4, 4274 }; 4275 4276 static const struct of_device_id dsi_of_match[] = { 4277 { 4278 .compatible = "auo,b080uan01", 4279 .data = &auo_b080uan01 4280 }, { 4281 .compatible = "boe,tv080wum-nl0", 4282 .data = &boe_tv080wum_nl0 4283 }, { 4284 .compatible = "lg,ld070wx3-sl01", 4285 .data = &lg_ld070wx3_sl01 4286 }, { 4287 .compatible = "lg,lh500wx1-sd03", 4288 .data = &lg_lh500wx1_sd03 4289 }, { 4290 .compatible = "panasonic,vvx10f004b00", 4291 .data = &panasonic_vvx10f004b00 4292 }, { 4293 .compatible = "lg,acx467akm-7", 4294 .data = &lg_acx467akm_7 4295 }, { 4296 .compatible = "osddisplays,osd101t2045-53ts", 4297 .data = &osd101t2045_53ts 4298 }, { 4299 /* sentinel */ 4300 } 4301 }; 4302 MODULE_DEVICE_TABLE(of, dsi_of_match); 4303 4304 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4305 { 4306 const struct panel_desc_dsi *desc; 4307 const struct of_device_id *id; 4308 int err; 4309 4310 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4311 if (!id) 4312 return -ENODEV; 4313 4314 desc = id->data; 4315 4316 err = panel_simple_probe(&dsi->dev, &desc->desc); 4317 if (err < 0) 4318 return err; 4319 4320 dsi->mode_flags = desc->flags; 4321 dsi->format = desc->format; 4322 dsi->lanes = desc->lanes; 4323 4324 err = mipi_dsi_attach(dsi); 4325 if (err) { 4326 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4327 4328 drm_panel_remove(&panel->base); 4329 } 4330 4331 return err; 4332 } 4333 4334 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4335 { 4336 int err; 4337 4338 err = mipi_dsi_detach(dsi); 4339 if (err < 0) 4340 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4341 4342 return panel_simple_remove(&dsi->dev); 4343 } 4344 4345 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4346 { 4347 panel_simple_shutdown(&dsi->dev); 4348 } 4349 4350 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4351 .driver = { 4352 .name = "panel-simple-dsi", 4353 .of_match_table = dsi_of_match, 4354 .pm = &panel_simple_pm_ops, 4355 }, 4356 .probe = panel_simple_dsi_probe, 4357 .remove = panel_simple_dsi_remove, 4358 .shutdown = panel_simple_dsi_shutdown, 4359 }; 4360 4361 static int __init panel_simple_init(void) 4362 { 4363 int err; 4364 4365 err = platform_driver_register(&panel_simple_platform_driver); 4366 if (err < 0) 4367 return err; 4368 4369 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4370 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4371 if (err < 0) 4372 goto err_did_platform_register; 4373 } 4374 4375 return 0; 4376 4377 err_did_platform_register: 4378 platform_driver_unregister(&panel_simple_platform_driver); 4379 4380 return err; 4381 } 4382 module_init(panel_simple_init); 4383 4384 static void __exit panel_simple_exit(void) 4385 { 4386 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4387 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4388 4389 platform_driver_unregister(&panel_simple_platform_driver); 4390 } 4391 module_exit(panel_simple_exit); 4392 4393 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4394 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4395 MODULE_LICENSE("GPL and additional rights"); 4396