1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, m->vrefresh); 167 continue; 168 } 169 170 mode->type |= DRM_MODE_TYPE_DRIVER; 171 172 if (panel->desc->num_modes == 1) 173 mode->type |= DRM_MODE_TYPE_PREFERRED; 174 175 drm_mode_set_name(mode); 176 177 drm_mode_probed_add(connector, mode); 178 num++; 179 } 180 181 return num; 182 } 183 184 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 185 struct drm_connector *connector) 186 { 187 struct drm_display_mode *mode; 188 bool has_override = panel->override_mode.type; 189 unsigned int num = 0; 190 191 if (!panel->desc) 192 return 0; 193 194 if (has_override) { 195 mode = drm_mode_duplicate(connector->dev, 196 &panel->override_mode); 197 if (mode) { 198 drm_mode_probed_add(connector, mode); 199 num = 1; 200 } else { 201 dev_err(panel->base.dev, "failed to add override mode\n"); 202 } 203 } 204 205 /* Only add timings if override was not there or failed to validate */ 206 if (num == 0 && panel->desc->num_timings) 207 num = panel_simple_get_timings_modes(panel, connector); 208 209 /* 210 * Only add fixed modes if timings/override added no mode. 211 * 212 * We should only ever have either the display timings specified 213 * or a fixed mode. Anything else is rather bogus. 214 */ 215 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 216 if (num == 0) 217 num = panel_simple_get_display_modes(panel, connector); 218 219 connector->display_info.bpc = panel->desc->bpc; 220 connector->display_info.width_mm = panel->desc->size.width; 221 connector->display_info.height_mm = panel->desc->size.height; 222 if (panel->desc->bus_format) 223 drm_display_info_set_bus_formats(&connector->display_info, 224 &panel->desc->bus_format, 1); 225 connector->display_info.bus_flags = panel->desc->bus_flags; 226 227 return num; 228 } 229 230 static int panel_simple_disable(struct drm_panel *panel) 231 { 232 struct panel_simple *p = to_panel_simple(panel); 233 234 if (!p->enabled) 235 return 0; 236 237 if (p->desc->delay.disable) 238 msleep(p->desc->delay.disable); 239 240 p->enabled = false; 241 242 return 0; 243 } 244 245 static int panel_simple_unprepare(struct drm_panel *panel) 246 { 247 struct panel_simple *p = to_panel_simple(panel); 248 249 if (!p->prepared) 250 return 0; 251 252 gpiod_set_value_cansleep(p->enable_gpio, 0); 253 254 regulator_disable(p->supply); 255 256 if (p->desc->delay.unprepare) 257 msleep(p->desc->delay.unprepare); 258 259 p->prepared = false; 260 261 return 0; 262 } 263 264 static int panel_simple_get_hpd_gpio(struct device *dev, 265 struct panel_simple *p, bool from_probe) 266 { 267 int err; 268 269 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 270 if (IS_ERR(p->hpd_gpio)) { 271 err = PTR_ERR(p->hpd_gpio); 272 273 /* 274 * If we're called from probe we won't consider '-EPROBE_DEFER' 275 * to be an error--we'll leave the error code in "hpd_gpio". 276 * When we try to use it we'll try again. This allows for 277 * circular dependencies where the component providing the 278 * hpd gpio needs the panel to init before probing. 279 */ 280 if (err != -EPROBE_DEFER || !from_probe) { 281 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 282 return err; 283 } 284 } 285 286 return 0; 287 } 288 289 static int panel_simple_prepare(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 unsigned int delay; 293 int err; 294 int hpd_asserted; 295 296 if (p->prepared) 297 return 0; 298 299 err = regulator_enable(p->supply); 300 if (err < 0) { 301 dev_err(panel->dev, "failed to enable supply: %d\n", err); 302 return err; 303 } 304 305 gpiod_set_value_cansleep(p->enable_gpio, 1); 306 307 delay = p->desc->delay.prepare; 308 if (p->no_hpd) 309 delay += p->desc->delay.hpd_absent_delay; 310 if (delay) 311 msleep(delay); 312 313 if (p->hpd_gpio) { 314 if (IS_ERR(p->hpd_gpio)) { 315 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 316 if (err) 317 return err; 318 } 319 320 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 321 hpd_asserted, hpd_asserted, 322 1000, 2000000); 323 if (hpd_asserted < 0) 324 err = hpd_asserted; 325 326 if (err) { 327 dev_err(panel->dev, 328 "error waiting for hpd GPIO: %d\n", err); 329 return err; 330 } 331 } 332 333 p->prepared = true; 334 335 return 0; 336 } 337 338 static int panel_simple_enable(struct drm_panel *panel) 339 { 340 struct panel_simple *p = to_panel_simple(panel); 341 342 if (p->enabled) 343 return 0; 344 345 if (p->desc->delay.enable) 346 msleep(p->desc->delay.enable); 347 348 p->enabled = true; 349 350 return 0; 351 } 352 353 static int panel_simple_get_modes(struct drm_panel *panel, 354 struct drm_connector *connector) 355 { 356 struct panel_simple *p = to_panel_simple(panel); 357 int num = 0; 358 359 /* probe EDID if a DDC bus is available */ 360 if (p->ddc) { 361 struct edid *edid = drm_get_edid(connector, p->ddc); 362 363 drm_connector_update_edid_property(connector, edid); 364 if (edid) { 365 num += drm_add_edid_modes(connector, edid); 366 kfree(edid); 367 } 368 } 369 370 /* add hard-coded panel modes */ 371 num += panel_simple_get_non_edid_modes(p, connector); 372 373 return num; 374 } 375 376 static int panel_simple_get_timings(struct drm_panel *panel, 377 unsigned int num_timings, 378 struct display_timing *timings) 379 { 380 struct panel_simple *p = to_panel_simple(panel); 381 unsigned int i; 382 383 if (p->desc->num_timings < num_timings) 384 num_timings = p->desc->num_timings; 385 386 if (timings) 387 for (i = 0; i < num_timings; i++) 388 timings[i] = p->desc->timings[i]; 389 390 return p->desc->num_timings; 391 } 392 393 static const struct drm_panel_funcs panel_simple_funcs = { 394 .disable = panel_simple_disable, 395 .unprepare = panel_simple_unprepare, 396 .prepare = panel_simple_prepare, 397 .enable = panel_simple_enable, 398 .get_modes = panel_simple_get_modes, 399 .get_timings = panel_simple_get_timings, 400 }; 401 402 static struct panel_desc panel_dpi; 403 404 static int panel_dpi_probe(struct device *dev, 405 struct panel_simple *panel) 406 { 407 struct display_timing *timing; 408 const struct device_node *np; 409 struct panel_desc *desc; 410 unsigned int bus_flags; 411 struct videomode vm; 412 int ret; 413 414 np = dev->of_node; 415 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 416 if (!desc) 417 return -ENOMEM; 418 419 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 420 if (!timing) 421 return -ENOMEM; 422 423 ret = of_get_display_timing(np, "panel-timing", timing); 424 if (ret < 0) { 425 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 426 np); 427 return ret; 428 } 429 430 desc->timings = timing; 431 desc->num_timings = 1; 432 433 of_property_read_u32(np, "width-mm", &desc->size.width); 434 of_property_read_u32(np, "height-mm", &desc->size.height); 435 436 /* Extract bus_flags from display_timing */ 437 bus_flags = 0; 438 vm.flags = timing->flags; 439 drm_bus_flags_from_videomode(&vm, &bus_flags); 440 desc->bus_flags = bus_flags; 441 442 /* We do not know the connector for the DT node, so guess it */ 443 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 444 445 panel->desc = desc; 446 447 return 0; 448 } 449 450 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 451 (to_check->field.typ >= bounds->field.min && \ 452 to_check->field.typ <= bounds->field.max) 453 static void panel_simple_parse_panel_timing_node(struct device *dev, 454 struct panel_simple *panel, 455 const struct display_timing *ot) 456 { 457 const struct panel_desc *desc = panel->desc; 458 struct videomode vm; 459 unsigned int i; 460 461 if (WARN_ON(desc->num_modes)) { 462 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 463 return; 464 } 465 if (WARN_ON(!desc->num_timings)) { 466 dev_err(dev, "Reject override mode: no timings specified\n"); 467 return; 468 } 469 470 for (i = 0; i < panel->desc->num_timings; i++) { 471 const struct display_timing *dt = &panel->desc->timings[i]; 472 473 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 474 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 481 continue; 482 483 if (ot->flags != dt->flags) 484 continue; 485 486 videomode_from_timing(ot, &vm); 487 drm_display_mode_from_videomode(&vm, &panel->override_mode); 488 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 489 DRM_MODE_TYPE_PREFERRED; 490 break; 491 } 492 493 if (WARN_ON(!panel->override_mode.type)) 494 dev_err(dev, "Reject override mode: No display_timing found\n"); 495 } 496 497 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 498 { 499 struct panel_simple *panel; 500 struct display_timing dt; 501 struct device_node *ddc; 502 int err; 503 504 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 505 if (!panel) 506 return -ENOMEM; 507 508 panel->enabled = false; 509 panel->prepared = false; 510 panel->desc = desc; 511 512 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 513 if (!panel->no_hpd) { 514 err = panel_simple_get_hpd_gpio(dev, panel, true); 515 if (err) 516 return err; 517 } 518 519 panel->supply = devm_regulator_get(dev, "power"); 520 if (IS_ERR(panel->supply)) 521 return PTR_ERR(panel->supply); 522 523 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 524 GPIOD_OUT_LOW); 525 if (IS_ERR(panel->enable_gpio)) { 526 err = PTR_ERR(panel->enable_gpio); 527 if (err != -EPROBE_DEFER) 528 dev_err(dev, "failed to request GPIO: %d\n", err); 529 return err; 530 } 531 532 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 533 if (ddc) { 534 panel->ddc = of_find_i2c_adapter_by_node(ddc); 535 of_node_put(ddc); 536 537 if (!panel->ddc) 538 return -EPROBE_DEFER; 539 } 540 541 if (desc == &panel_dpi) { 542 /* Handle the generic panel-dpi binding */ 543 err = panel_dpi_probe(dev, panel); 544 if (err) 545 goto free_ddc; 546 } else { 547 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 548 panel_simple_parse_panel_timing_node(dev, panel, &dt); 549 } 550 551 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 552 desc->connector_type); 553 554 err = drm_panel_of_backlight(&panel->base); 555 if (err) 556 goto free_ddc; 557 558 err = drm_panel_add(&panel->base); 559 if (err < 0) 560 goto free_ddc; 561 562 dev_set_drvdata(dev, panel); 563 564 return 0; 565 566 free_ddc: 567 if (panel->ddc) 568 put_device(&panel->ddc->dev); 569 570 return err; 571 } 572 573 static int panel_simple_remove(struct device *dev) 574 { 575 struct panel_simple *panel = dev_get_drvdata(dev); 576 577 drm_panel_remove(&panel->base); 578 drm_panel_disable(&panel->base); 579 drm_panel_unprepare(&panel->base); 580 581 if (panel->ddc) 582 put_device(&panel->ddc->dev); 583 584 return 0; 585 } 586 587 static void panel_simple_shutdown(struct device *dev) 588 { 589 struct panel_simple *panel = dev_get_drvdata(dev); 590 591 drm_panel_disable(&panel->base); 592 drm_panel_unprepare(&panel->base); 593 } 594 595 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 596 .clock = 9000, 597 .hdisplay = 480, 598 .hsync_start = 480 + 2, 599 .hsync_end = 480 + 2 + 41, 600 .htotal = 480 + 2 + 41 + 2, 601 .vdisplay = 272, 602 .vsync_start = 272 + 2, 603 .vsync_end = 272 + 2 + 10, 604 .vtotal = 272 + 2 + 10 + 2, 605 .vrefresh = 60, 606 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 607 }; 608 609 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 610 .modes = &ire_am_480272h3tmqw_t01h_mode, 611 .num_modes = 1, 612 .bpc = 8, 613 .size = { 614 .width = 105, 615 .height = 67, 616 }, 617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 618 }; 619 620 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 621 .clock = 33333, 622 .hdisplay = 800, 623 .hsync_start = 800 + 0, 624 .hsync_end = 800 + 0 + 255, 625 .htotal = 800 + 0 + 255 + 0, 626 .vdisplay = 480, 627 .vsync_start = 480 + 2, 628 .vsync_end = 480 + 2 + 45, 629 .vtotal = 480 + 2 + 45 + 0, 630 .vrefresh = 60, 631 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 632 }; 633 634 static const struct panel_desc ampire_am800480r3tmqwa1h = { 635 .modes = &ire_am800480r3tmqwa1h_mode, 636 .num_modes = 1, 637 .bpc = 6, 638 .size = { 639 .width = 152, 640 .height = 91, 641 }, 642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 643 }; 644 645 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 646 .pixelclock = { 26400000, 33300000, 46800000 }, 647 .hactive = { 800, 800, 800 }, 648 .hfront_porch = { 16, 210, 354 }, 649 .hback_porch = { 45, 36, 6 }, 650 .hsync_len = { 1, 10, 40 }, 651 .vactive = { 480, 480, 480 }, 652 .vfront_porch = { 7, 22, 147 }, 653 .vback_porch = { 22, 13, 3 }, 654 .vsync_len = { 1, 10, 20 }, 655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 656 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 657 }; 658 659 static const struct panel_desc armadeus_st0700_adapt = { 660 .timings = &santek_st0700i5y_rbslw_f_timing, 661 .num_timings = 1, 662 .bpc = 6, 663 .size = { 664 .width = 154, 665 .height = 86, 666 }, 667 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 669 }; 670 671 static const struct drm_display_mode auo_b101aw03_mode = { 672 .clock = 51450, 673 .hdisplay = 1024, 674 .hsync_start = 1024 + 156, 675 .hsync_end = 1024 + 156 + 8, 676 .htotal = 1024 + 156 + 8 + 156, 677 .vdisplay = 600, 678 .vsync_start = 600 + 16, 679 .vsync_end = 600 + 16 + 6, 680 .vtotal = 600 + 16 + 6 + 16, 681 .vrefresh = 60, 682 }; 683 684 static const struct panel_desc auo_b101aw03 = { 685 .modes = &auo_b101aw03_mode, 686 .num_modes = 1, 687 .bpc = 6, 688 .size = { 689 .width = 223, 690 .height = 125, 691 }, 692 }; 693 694 static const struct display_timing auo_b101ean01_timing = { 695 .pixelclock = { 65300000, 72500000, 75000000 }, 696 .hactive = { 1280, 1280, 1280 }, 697 .hfront_porch = { 18, 119, 119 }, 698 .hback_porch = { 21, 21, 21 }, 699 .hsync_len = { 32, 32, 32 }, 700 .vactive = { 800, 800, 800 }, 701 .vfront_porch = { 4, 4, 4 }, 702 .vback_porch = { 8, 8, 8 }, 703 .vsync_len = { 18, 20, 20 }, 704 }; 705 706 static const struct panel_desc auo_b101ean01 = { 707 .timings = &auo_b101ean01_timing, 708 .num_timings = 1, 709 .bpc = 6, 710 .size = { 711 .width = 217, 712 .height = 136, 713 }, 714 }; 715 716 static const struct drm_display_mode auo_b101xtn01_mode = { 717 .clock = 72000, 718 .hdisplay = 1366, 719 .hsync_start = 1366 + 20, 720 .hsync_end = 1366 + 20 + 70, 721 .htotal = 1366 + 20 + 70, 722 .vdisplay = 768, 723 .vsync_start = 768 + 14, 724 .vsync_end = 768 + 14 + 42, 725 .vtotal = 768 + 14 + 42, 726 .vrefresh = 60, 727 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 728 }; 729 730 static const struct panel_desc auo_b101xtn01 = { 731 .modes = &auo_b101xtn01_mode, 732 .num_modes = 1, 733 .bpc = 6, 734 .size = { 735 .width = 223, 736 .height = 125, 737 }, 738 }; 739 740 static const struct drm_display_mode auo_b116xak01_mode = { 741 .clock = 69300, 742 .hdisplay = 1366, 743 .hsync_start = 1366 + 48, 744 .hsync_end = 1366 + 48 + 32, 745 .htotal = 1366 + 48 + 32 + 10, 746 .vdisplay = 768, 747 .vsync_start = 768 + 4, 748 .vsync_end = 768 + 4 + 6, 749 .vtotal = 768 + 4 + 6 + 15, 750 .vrefresh = 60, 751 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 752 }; 753 754 static const struct panel_desc auo_b116xak01 = { 755 .modes = &auo_b116xak01_mode, 756 .num_modes = 1, 757 .bpc = 6, 758 .size = { 759 .width = 256, 760 .height = 144, 761 }, 762 .delay = { 763 .hpd_absent_delay = 200, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 766 .connector_type = DRM_MODE_CONNECTOR_eDP, 767 }; 768 769 static const struct drm_display_mode auo_b116xw03_mode = { 770 .clock = 70589, 771 .hdisplay = 1366, 772 .hsync_start = 1366 + 40, 773 .hsync_end = 1366 + 40 + 40, 774 .htotal = 1366 + 40 + 40 + 32, 775 .vdisplay = 768, 776 .vsync_start = 768 + 10, 777 .vsync_end = 768 + 10 + 12, 778 .vtotal = 768 + 10 + 12 + 6, 779 .vrefresh = 60, 780 }; 781 782 static const struct panel_desc auo_b116xw03 = { 783 .modes = &auo_b116xw03_mode, 784 .num_modes = 1, 785 .bpc = 6, 786 .size = { 787 .width = 256, 788 .height = 144, 789 }, 790 }; 791 792 static const struct drm_display_mode auo_b133xtn01_mode = { 793 .clock = 69500, 794 .hdisplay = 1366, 795 .hsync_start = 1366 + 48, 796 .hsync_end = 1366 + 48 + 32, 797 .htotal = 1366 + 48 + 32 + 20, 798 .vdisplay = 768, 799 .vsync_start = 768 + 3, 800 .vsync_end = 768 + 3 + 6, 801 .vtotal = 768 + 3 + 6 + 13, 802 .vrefresh = 60, 803 }; 804 805 static const struct panel_desc auo_b133xtn01 = { 806 .modes = &auo_b133xtn01_mode, 807 .num_modes = 1, 808 .bpc = 6, 809 .size = { 810 .width = 293, 811 .height = 165, 812 }, 813 }; 814 815 static const struct drm_display_mode auo_b133htn01_mode = { 816 .clock = 150660, 817 .hdisplay = 1920, 818 .hsync_start = 1920 + 172, 819 .hsync_end = 1920 + 172 + 80, 820 .htotal = 1920 + 172 + 80 + 60, 821 .vdisplay = 1080, 822 .vsync_start = 1080 + 25, 823 .vsync_end = 1080 + 25 + 10, 824 .vtotal = 1080 + 25 + 10 + 10, 825 .vrefresh = 60, 826 }; 827 828 static const struct panel_desc auo_b133htn01 = { 829 .modes = &auo_b133htn01_mode, 830 .num_modes = 1, 831 .bpc = 6, 832 .size = { 833 .width = 293, 834 .height = 165, 835 }, 836 .delay = { 837 .prepare = 105, 838 .enable = 20, 839 .unprepare = 50, 840 }, 841 }; 842 843 static const struct display_timing auo_g070vvn01_timings = { 844 .pixelclock = { 33300000, 34209000, 45000000 }, 845 .hactive = { 800, 800, 800 }, 846 .hfront_porch = { 20, 40, 200 }, 847 .hback_porch = { 87, 40, 1 }, 848 .hsync_len = { 1, 48, 87 }, 849 .vactive = { 480, 480, 480 }, 850 .vfront_porch = { 5, 13, 200 }, 851 .vback_porch = { 31, 31, 29 }, 852 .vsync_len = { 1, 1, 3 }, 853 }; 854 855 static const struct panel_desc auo_g070vvn01 = { 856 .timings = &auo_g070vvn01_timings, 857 .num_timings = 1, 858 .bpc = 8, 859 .size = { 860 .width = 152, 861 .height = 91, 862 }, 863 .delay = { 864 .prepare = 200, 865 .enable = 50, 866 .disable = 50, 867 .unprepare = 1000, 868 }, 869 }; 870 871 static const struct drm_display_mode auo_g101evn010_mode = { 872 .clock = 68930, 873 .hdisplay = 1280, 874 .hsync_start = 1280 + 82, 875 .hsync_end = 1280 + 82 + 2, 876 .htotal = 1280 + 82 + 2 + 84, 877 .vdisplay = 800, 878 .vsync_start = 800 + 8, 879 .vsync_end = 800 + 8 + 2, 880 .vtotal = 800 + 8 + 2 + 6, 881 .vrefresh = 60, 882 }; 883 884 static const struct panel_desc auo_g101evn010 = { 885 .modes = &auo_g101evn010_mode, 886 .num_modes = 1, 887 .bpc = 6, 888 .size = { 889 .width = 216, 890 .height = 135, 891 }, 892 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 893 .connector_type = DRM_MODE_CONNECTOR_LVDS, 894 }; 895 896 static const struct drm_display_mode auo_g104sn02_mode = { 897 .clock = 40000, 898 .hdisplay = 800, 899 .hsync_start = 800 + 40, 900 .hsync_end = 800 + 40 + 216, 901 .htotal = 800 + 40 + 216 + 128, 902 .vdisplay = 600, 903 .vsync_start = 600 + 10, 904 .vsync_end = 600 + 10 + 35, 905 .vtotal = 600 + 10 + 35 + 2, 906 .vrefresh = 60, 907 }; 908 909 static const struct panel_desc auo_g104sn02 = { 910 .modes = &auo_g104sn02_mode, 911 .num_modes = 1, 912 .bpc = 8, 913 .size = { 914 .width = 211, 915 .height = 158, 916 }, 917 }; 918 919 static const struct drm_display_mode auo_g121ean01_mode = { 920 .clock = 66700, 921 .hdisplay = 1280, 922 .hsync_start = 1280 + 58, 923 .hsync_end = 1280 + 58 + 8, 924 .htotal = 1280 + 58 + 8 + 70, 925 .vdisplay = 800, 926 .vsync_start = 800 + 6, 927 .vsync_end = 800 + 6 + 4, 928 .vtotal = 800 + 6 + 4 + 10, 929 .vrefresh = 60, 930 }; 931 932 static const struct panel_desc auo_g121ean01 = { 933 .modes = &auo_g121ean01_mode, 934 .num_modes = 1, 935 .bpc = 8, 936 .size = { 937 .width = 261, 938 .height = 163, 939 }, 940 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 941 .connector_type = DRM_MODE_CONNECTOR_LVDS, 942 }; 943 944 static const struct display_timing auo_g133han01_timings = { 945 .pixelclock = { 134000000, 141200000, 149000000 }, 946 .hactive = { 1920, 1920, 1920 }, 947 .hfront_porch = { 39, 58, 77 }, 948 .hback_porch = { 59, 88, 117 }, 949 .hsync_len = { 28, 42, 56 }, 950 .vactive = { 1080, 1080, 1080 }, 951 .vfront_porch = { 3, 8, 11 }, 952 .vback_porch = { 5, 14, 19 }, 953 .vsync_len = { 4, 14, 19 }, 954 }; 955 956 static const struct panel_desc auo_g133han01 = { 957 .timings = &auo_g133han01_timings, 958 .num_timings = 1, 959 .bpc = 8, 960 .size = { 961 .width = 293, 962 .height = 165, 963 }, 964 .delay = { 965 .prepare = 200, 966 .enable = 50, 967 .disable = 50, 968 .unprepare = 1000, 969 }, 970 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 972 }; 973 974 static const struct drm_display_mode auo_g156xtn01_mode = { 975 .clock = 76000, 976 .hdisplay = 1366, 977 .hsync_start = 1366 + 33, 978 .hsync_end = 1366 + 33 + 67, 979 .htotal = 1560, 980 .vdisplay = 768, 981 .vsync_start = 768 + 4, 982 .vsync_end = 768 + 4 + 4, 983 .vtotal = 806, 984 .vrefresh = 60, 985 }; 986 987 static const struct panel_desc auo_g156xtn01 = { 988 .modes = &auo_g156xtn01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 344, 993 .height = 194, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g185han01_timings = { 1000 .pixelclock = { 120000000, 144000000, 175000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 36, 120, 148 }, 1003 .hback_porch = { 24, 88, 108 }, 1004 .hsync_len = { 20, 48, 64 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 6, 10, 40 }, 1007 .vback_porch = { 2, 5, 20 }, 1008 .vsync_len = { 2, 5, 20 }, 1009 }; 1010 1011 static const struct panel_desc auo_g185han01 = { 1012 .timings = &auo_g185han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 409, 1017 .height = 230, 1018 }, 1019 .delay = { 1020 .prepare = 50, 1021 .enable = 200, 1022 .disable = 110, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct display_timing auo_g190ean01_timings = { 1030 .pixelclock = { 90000000, 108000000, 135000000 }, 1031 .hactive = { 1280, 1280, 1280 }, 1032 .hfront_porch = { 126, 184, 1266 }, 1033 .hback_porch = { 84, 122, 844 }, 1034 .hsync_len = { 70, 102, 704 }, 1035 .vactive = { 1024, 1024, 1024 }, 1036 .vfront_porch = { 4, 26, 76 }, 1037 .vback_porch = { 2, 8, 25 }, 1038 .vsync_len = { 2, 8, 25 }, 1039 }; 1040 1041 static const struct panel_desc auo_g190ean01 = { 1042 .timings = &auo_g190ean01_timings, 1043 .num_timings = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 376, 1047 .height = 301, 1048 }, 1049 .delay = { 1050 .prepare = 50, 1051 .enable = 200, 1052 .disable = 110, 1053 .unprepare = 1000, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct display_timing auo_p320hvn03_timings = { 1060 .pixelclock = { 106000000, 148500000, 164000000 }, 1061 .hactive = { 1920, 1920, 1920 }, 1062 .hfront_porch = { 25, 50, 130 }, 1063 .hback_porch = { 25, 50, 130 }, 1064 .hsync_len = { 20, 40, 105 }, 1065 .vactive = { 1080, 1080, 1080 }, 1066 .vfront_porch = { 8, 17, 150 }, 1067 .vback_porch = { 8, 17, 150 }, 1068 .vsync_len = { 4, 11, 100 }, 1069 }; 1070 1071 static const struct panel_desc auo_p320hvn03 = { 1072 .timings = &auo_p320hvn03_timings, 1073 .num_timings = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 698, 1077 .height = 393, 1078 }, 1079 .delay = { 1080 .prepare = 1, 1081 .enable = 450, 1082 .unprepare = 500, 1083 }, 1084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1085 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1086 }; 1087 1088 static const struct drm_display_mode auo_t215hvn01_mode = { 1089 .clock = 148800, 1090 .hdisplay = 1920, 1091 .hsync_start = 1920 + 88, 1092 .hsync_end = 1920 + 88 + 44, 1093 .htotal = 1920 + 88 + 44 + 148, 1094 .vdisplay = 1080, 1095 .vsync_start = 1080 + 4, 1096 .vsync_end = 1080 + 4 + 5, 1097 .vtotal = 1080 + 4 + 5 + 36, 1098 .vrefresh = 60, 1099 }; 1100 1101 static const struct panel_desc auo_t215hvn01 = { 1102 .modes = &auo_t215hvn01_mode, 1103 .num_modes = 1, 1104 .bpc = 8, 1105 .size = { 1106 .width = 430, 1107 .height = 270, 1108 }, 1109 .delay = { 1110 .disable = 5, 1111 .unprepare = 1000, 1112 } 1113 }; 1114 1115 static const struct drm_display_mode avic_tm070ddh03_mode = { 1116 .clock = 51200, 1117 .hdisplay = 1024, 1118 .hsync_start = 1024 + 160, 1119 .hsync_end = 1024 + 160 + 4, 1120 .htotal = 1024 + 160 + 4 + 156, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 17, 1123 .vsync_end = 600 + 17 + 1, 1124 .vtotal = 600 + 17 + 1 + 17, 1125 .vrefresh = 60, 1126 }; 1127 1128 static const struct panel_desc avic_tm070ddh03 = { 1129 .modes = &avic_tm070ddh03_mode, 1130 .num_modes = 1, 1131 .bpc = 8, 1132 .size = { 1133 .width = 154, 1134 .height = 90, 1135 }, 1136 .delay = { 1137 .prepare = 20, 1138 .enable = 200, 1139 .disable = 200, 1140 }, 1141 }; 1142 1143 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1144 .clock = 30000, 1145 .hdisplay = 800, 1146 .hsync_start = 800 + 40, 1147 .hsync_end = 800 + 40 + 48, 1148 .htotal = 800 + 40 + 48 + 40, 1149 .vdisplay = 480, 1150 .vsync_start = 480 + 13, 1151 .vsync_end = 480 + 13 + 3, 1152 .vtotal = 480 + 13 + 3 + 29, 1153 }; 1154 1155 static const struct panel_desc bananapi_s070wv20_ct16 = { 1156 .modes = &bananapi_s070wv20_ct16_mode, 1157 .num_modes = 1, 1158 .bpc = 6, 1159 .size = { 1160 .width = 154, 1161 .height = 86, 1162 }, 1163 }; 1164 1165 static const struct drm_display_mode boe_hv070wsa_mode = { 1166 .clock = 42105, 1167 .hdisplay = 1024, 1168 .hsync_start = 1024 + 30, 1169 .hsync_end = 1024 + 30 + 30, 1170 .htotal = 1024 + 30 + 30 + 30, 1171 .vdisplay = 600, 1172 .vsync_start = 600 + 10, 1173 .vsync_end = 600 + 10 + 10, 1174 .vtotal = 600 + 10 + 10 + 10, 1175 .vrefresh = 60, 1176 }; 1177 1178 static const struct panel_desc boe_hv070wsa = { 1179 .modes = &boe_hv070wsa_mode, 1180 .num_modes = 1, 1181 .size = { 1182 .width = 154, 1183 .height = 90, 1184 }, 1185 }; 1186 1187 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1188 { 1189 .clock = 71900, 1190 .hdisplay = 1280, 1191 .hsync_start = 1280 + 48, 1192 .hsync_end = 1280 + 48 + 32, 1193 .htotal = 1280 + 48 + 32 + 80, 1194 .vdisplay = 800, 1195 .vsync_start = 800 + 3, 1196 .vsync_end = 800 + 3 + 5, 1197 .vtotal = 800 + 3 + 5 + 24, 1198 .vrefresh = 60, 1199 }, 1200 { 1201 .clock = 57500, 1202 .hdisplay = 1280, 1203 .hsync_start = 1280 + 48, 1204 .hsync_end = 1280 + 48 + 32, 1205 .htotal = 1280 + 48 + 32 + 80, 1206 .vdisplay = 800, 1207 .vsync_start = 800 + 3, 1208 .vsync_end = 800 + 3 + 5, 1209 .vtotal = 800 + 3 + 5 + 24, 1210 .vrefresh = 48, 1211 }, 1212 }; 1213 1214 static const struct panel_desc boe_nv101wxmn51 = { 1215 .modes = boe_nv101wxmn51_modes, 1216 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1217 .bpc = 8, 1218 .size = { 1219 .width = 217, 1220 .height = 136, 1221 }, 1222 .delay = { 1223 .prepare = 210, 1224 .enable = 50, 1225 .unprepare = 160, 1226 }, 1227 }; 1228 1229 /* Also used for boe_nv133fhm_n62 */ 1230 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1231 .clock = 147840, 1232 .hdisplay = 1920, 1233 .hsync_start = 1920 + 48, 1234 .hsync_end = 1920 + 48 + 32, 1235 .htotal = 1920 + 48 + 32 + 200, 1236 .vdisplay = 1080, 1237 .vsync_start = 1080 + 3, 1238 .vsync_end = 1080 + 3 + 6, 1239 .vtotal = 1080 + 3 + 6 + 31, 1240 .vrefresh = 60, 1241 }; 1242 1243 /* Also used for boe_nv133fhm_n62 */ 1244 static const struct panel_desc boe_nv133fhm_n61 = { 1245 .modes = &boe_nv133fhm_n61_modes, 1246 .num_modes = 1, 1247 .bpc = 6, 1248 .size = { 1249 .width = 294, 1250 .height = 165, 1251 }, 1252 .delay = { 1253 .hpd_absent_delay = 200, 1254 .unprepare = 500, 1255 }, 1256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1257 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1258 .connector_type = DRM_MODE_CONNECTOR_eDP, 1259 }; 1260 1261 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1262 { 1263 .clock = 148500, 1264 .hdisplay = 1920, 1265 .hsync_start = 1920 + 48, 1266 .hsync_end = 1920 + 48 + 32, 1267 .htotal = 2200, 1268 .vdisplay = 1080, 1269 .vsync_start = 1080 + 3, 1270 .vsync_end = 1080 + 3 + 5, 1271 .vtotal = 1125, 1272 .vrefresh = 60, 1273 }, 1274 }; 1275 1276 static const struct panel_desc boe_nv140fhmn49 = { 1277 .modes = boe_nv140fhmn49_modes, 1278 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1279 .bpc = 6, 1280 .size = { 1281 .width = 309, 1282 .height = 174, 1283 }, 1284 .delay = { 1285 .prepare = 210, 1286 .enable = 50, 1287 .unprepare = 160, 1288 }, 1289 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1290 .connector_type = DRM_MODE_CONNECTOR_eDP, 1291 }; 1292 1293 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1294 .clock = 9000, 1295 .hdisplay = 480, 1296 .hsync_start = 480 + 5, 1297 .hsync_end = 480 + 5 + 5, 1298 .htotal = 480 + 5 + 5 + 40, 1299 .vdisplay = 272, 1300 .vsync_start = 272 + 8, 1301 .vsync_end = 272 + 8 + 8, 1302 .vtotal = 272 + 8 + 8 + 8, 1303 .vrefresh = 60, 1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1305 }; 1306 1307 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1308 .modes = &cdtech_s043wq26h_ct7_mode, 1309 .num_modes = 1, 1310 .bpc = 8, 1311 .size = { 1312 .width = 95, 1313 .height = 54, 1314 }, 1315 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1316 }; 1317 1318 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1319 .clock = 35000, 1320 .hdisplay = 800, 1321 .hsync_start = 800 + 40, 1322 .hsync_end = 800 + 40 + 40, 1323 .htotal = 800 + 40 + 40 + 48, 1324 .vdisplay = 480, 1325 .vsync_start = 480 + 29, 1326 .vsync_end = 480 + 29 + 13, 1327 .vtotal = 480 + 29 + 13 + 3, 1328 .vrefresh = 60, 1329 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1330 }; 1331 1332 static const struct panel_desc cdtech_s070wv95_ct16 = { 1333 .modes = &cdtech_s070wv95_ct16_mode, 1334 .num_modes = 1, 1335 .bpc = 8, 1336 .size = { 1337 .width = 154, 1338 .height = 85, 1339 }, 1340 }; 1341 1342 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1343 .clock = 66770, 1344 .hdisplay = 800, 1345 .hsync_start = 800 + 49, 1346 .hsync_end = 800 + 49 + 33, 1347 .htotal = 800 + 49 + 33 + 17, 1348 .vdisplay = 1280, 1349 .vsync_start = 1280 + 1, 1350 .vsync_end = 1280 + 1 + 7, 1351 .vtotal = 1280 + 1 + 7 + 15, 1352 .vrefresh = 60, 1353 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1354 }; 1355 1356 static const struct panel_desc chunghwa_claa070wp03xg = { 1357 .modes = &chunghwa_claa070wp03xg_mode, 1358 .num_modes = 1, 1359 .bpc = 6, 1360 .size = { 1361 .width = 94, 1362 .height = 150, 1363 }, 1364 }; 1365 1366 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1367 .clock = 72070, 1368 .hdisplay = 1366, 1369 .hsync_start = 1366 + 58, 1370 .hsync_end = 1366 + 58 + 58, 1371 .htotal = 1366 + 58 + 58 + 58, 1372 .vdisplay = 768, 1373 .vsync_start = 768 + 4, 1374 .vsync_end = 768 + 4 + 4, 1375 .vtotal = 768 + 4 + 4 + 4, 1376 .vrefresh = 60, 1377 }; 1378 1379 static const struct panel_desc chunghwa_claa101wa01a = { 1380 .modes = &chunghwa_claa101wa01a_mode, 1381 .num_modes = 1, 1382 .bpc = 6, 1383 .size = { 1384 .width = 220, 1385 .height = 120, 1386 }, 1387 }; 1388 1389 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1390 .clock = 69300, 1391 .hdisplay = 1366, 1392 .hsync_start = 1366 + 48, 1393 .hsync_end = 1366 + 48 + 32, 1394 .htotal = 1366 + 48 + 32 + 20, 1395 .vdisplay = 768, 1396 .vsync_start = 768 + 16, 1397 .vsync_end = 768 + 16 + 8, 1398 .vtotal = 768 + 16 + 8 + 16, 1399 .vrefresh = 60, 1400 }; 1401 1402 static const struct panel_desc chunghwa_claa101wb01 = { 1403 .modes = &chunghwa_claa101wb01_mode, 1404 .num_modes = 1, 1405 .bpc = 6, 1406 .size = { 1407 .width = 223, 1408 .height = 125, 1409 }, 1410 }; 1411 1412 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1413 .clock = 33260, 1414 .hdisplay = 800, 1415 .hsync_start = 800 + 40, 1416 .hsync_end = 800 + 40 + 128, 1417 .htotal = 800 + 40 + 128 + 88, 1418 .vdisplay = 480, 1419 .vsync_start = 480 + 10, 1420 .vsync_end = 480 + 10 + 2, 1421 .vtotal = 480 + 10 + 2 + 33, 1422 .vrefresh = 60, 1423 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1424 }; 1425 1426 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1427 .modes = &dataimage_scf0700c48ggu18_mode, 1428 .num_modes = 1, 1429 .bpc = 8, 1430 .size = { 1431 .width = 152, 1432 .height = 91, 1433 }, 1434 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1435 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1436 }; 1437 1438 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1439 .pixelclock = { 45000000, 51200000, 57000000 }, 1440 .hactive = { 1024, 1024, 1024 }, 1441 .hfront_porch = { 100, 106, 113 }, 1442 .hback_porch = { 100, 106, 113 }, 1443 .hsync_len = { 100, 108, 114 }, 1444 .vactive = { 600, 600, 600 }, 1445 .vfront_porch = { 8, 11, 15 }, 1446 .vback_porch = { 8, 11, 15 }, 1447 .vsync_len = { 9, 13, 15 }, 1448 .flags = DISPLAY_FLAGS_DE_HIGH, 1449 }; 1450 1451 static const struct panel_desc dlc_dlc0700yzg_1 = { 1452 .timings = &dlc_dlc0700yzg_1_timing, 1453 .num_timings = 1, 1454 .bpc = 6, 1455 .size = { 1456 .width = 154, 1457 .height = 86, 1458 }, 1459 .delay = { 1460 .prepare = 30, 1461 .enable = 200, 1462 .disable = 200, 1463 }, 1464 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1465 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1466 }; 1467 1468 static const struct display_timing dlc_dlc1010gig_timing = { 1469 .pixelclock = { 68900000, 71100000, 73400000 }, 1470 .hactive = { 1280, 1280, 1280 }, 1471 .hfront_porch = { 43, 53, 63 }, 1472 .hback_porch = { 43, 53, 63 }, 1473 .hsync_len = { 44, 54, 64 }, 1474 .vactive = { 800, 800, 800 }, 1475 .vfront_porch = { 5, 8, 11 }, 1476 .vback_porch = { 5, 8, 11 }, 1477 .vsync_len = { 5, 7, 11 }, 1478 .flags = DISPLAY_FLAGS_DE_HIGH, 1479 }; 1480 1481 static const struct panel_desc dlc_dlc1010gig = { 1482 .timings = &dlc_dlc1010gig_timing, 1483 .num_timings = 1, 1484 .bpc = 8, 1485 .size = { 1486 .width = 216, 1487 .height = 135, 1488 }, 1489 .delay = { 1490 .prepare = 60, 1491 .enable = 150, 1492 .disable = 100, 1493 .unprepare = 60, 1494 }, 1495 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1496 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1497 }; 1498 1499 static const struct drm_display_mode edt_et035012dm6_mode = { 1500 .clock = 6500, 1501 .hdisplay = 320, 1502 .hsync_start = 320 + 20, 1503 .hsync_end = 320 + 20 + 30, 1504 .htotal = 320 + 20 + 68, 1505 .vdisplay = 240, 1506 .vsync_start = 240 + 4, 1507 .vsync_end = 240 + 4 + 4, 1508 .vtotal = 240 + 4 + 4 + 14, 1509 .vrefresh = 60, 1510 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1511 }; 1512 1513 static const struct panel_desc edt_et035012dm6 = { 1514 .modes = &edt_et035012dm6_mode, 1515 .num_modes = 1, 1516 .bpc = 8, 1517 .size = { 1518 .width = 70, 1519 .height = 52, 1520 }, 1521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1522 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1523 }; 1524 1525 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1526 .clock = 10870, 1527 .hdisplay = 480, 1528 .hsync_start = 480 + 8, 1529 .hsync_end = 480 + 8 + 4, 1530 .htotal = 480 + 8 + 4 + 41, 1531 1532 /* 1533 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1534 * fb_align 1535 */ 1536 1537 .vdisplay = 288, 1538 .vsync_start = 288 + 2, 1539 .vsync_end = 288 + 2 + 4, 1540 .vtotal = 288 + 2 + 4 + 10, 1541 .vrefresh = 60, 1542 }; 1543 1544 static const struct panel_desc edt_etm043080dh6gp = { 1545 .modes = &edt_etm043080dh6gp_mode, 1546 .num_modes = 1, 1547 .bpc = 8, 1548 .size = { 1549 .width = 100, 1550 .height = 65, 1551 }, 1552 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1553 .connector_type = DRM_MODE_CONNECTOR_DPI, 1554 }; 1555 1556 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1557 .clock = 9000, 1558 .hdisplay = 480, 1559 .hsync_start = 480 + 2, 1560 .hsync_end = 480 + 2 + 41, 1561 .htotal = 480 + 2 + 41 + 2, 1562 .vdisplay = 272, 1563 .vsync_start = 272 + 2, 1564 .vsync_end = 272 + 2 + 10, 1565 .vtotal = 272 + 2 + 10 + 2, 1566 .vrefresh = 60, 1567 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1568 }; 1569 1570 static const struct panel_desc edt_etm0430g0dh6 = { 1571 .modes = &edt_etm0430g0dh6_mode, 1572 .num_modes = 1, 1573 .bpc = 6, 1574 .size = { 1575 .width = 95, 1576 .height = 54, 1577 }, 1578 }; 1579 1580 static const struct drm_display_mode edt_et057090dhu_mode = { 1581 .clock = 25175, 1582 .hdisplay = 640, 1583 .hsync_start = 640 + 16, 1584 .hsync_end = 640 + 16 + 30, 1585 .htotal = 640 + 16 + 30 + 114, 1586 .vdisplay = 480, 1587 .vsync_start = 480 + 10, 1588 .vsync_end = 480 + 10 + 3, 1589 .vtotal = 480 + 10 + 3 + 32, 1590 .vrefresh = 60, 1591 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1592 }; 1593 1594 static const struct panel_desc edt_et057090dhu = { 1595 .modes = &edt_et057090dhu_mode, 1596 .num_modes = 1, 1597 .bpc = 6, 1598 .size = { 1599 .width = 115, 1600 .height = 86, 1601 }, 1602 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1603 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1604 }; 1605 1606 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1607 .clock = 33260, 1608 .hdisplay = 800, 1609 .hsync_start = 800 + 40, 1610 .hsync_end = 800 + 40 + 128, 1611 .htotal = 800 + 40 + 128 + 88, 1612 .vdisplay = 480, 1613 .vsync_start = 480 + 10, 1614 .vsync_end = 480 + 10 + 2, 1615 .vtotal = 480 + 10 + 2 + 33, 1616 .vrefresh = 60, 1617 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1618 }; 1619 1620 static const struct panel_desc edt_etm0700g0dh6 = { 1621 .modes = &edt_etm0700g0dh6_mode, 1622 .num_modes = 1, 1623 .bpc = 6, 1624 .size = { 1625 .width = 152, 1626 .height = 91, 1627 }, 1628 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1629 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1630 }; 1631 1632 static const struct panel_desc edt_etm0700g0bdh6 = { 1633 .modes = &edt_etm0700g0dh6_mode, 1634 .num_modes = 1, 1635 .bpc = 6, 1636 .size = { 1637 .width = 152, 1638 .height = 91, 1639 }, 1640 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1641 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1642 }; 1643 1644 static const struct display_timing evervision_vgg804821_timing = { 1645 .pixelclock = { 27600000, 33300000, 50000000 }, 1646 .hactive = { 800, 800, 800 }, 1647 .hfront_porch = { 40, 66, 70 }, 1648 .hback_porch = { 40, 67, 70 }, 1649 .hsync_len = { 40, 67, 70 }, 1650 .vactive = { 480, 480, 480 }, 1651 .vfront_porch = { 6, 10, 10 }, 1652 .vback_porch = { 7, 11, 11 }, 1653 .vsync_len = { 7, 11, 11 }, 1654 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1655 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1656 DISPLAY_FLAGS_SYNC_NEGEDGE, 1657 }; 1658 1659 static const struct panel_desc evervision_vgg804821 = { 1660 .timings = &evervision_vgg804821_timing, 1661 .num_timings = 1, 1662 .bpc = 8, 1663 .size = { 1664 .width = 108, 1665 .height = 64, 1666 }, 1667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1669 }; 1670 1671 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1672 .clock = 32260, 1673 .hdisplay = 800, 1674 .hsync_start = 800 + 168, 1675 .hsync_end = 800 + 168 + 64, 1676 .htotal = 800 + 168 + 64 + 88, 1677 .vdisplay = 480, 1678 .vsync_start = 480 + 37, 1679 .vsync_end = 480 + 37 + 2, 1680 .vtotal = 480 + 37 + 2 + 8, 1681 .vrefresh = 60, 1682 }; 1683 1684 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1685 .modes = &foxlink_fl500wvr00_a0t_mode, 1686 .num_modes = 1, 1687 .bpc = 8, 1688 .size = { 1689 .width = 108, 1690 .height = 65, 1691 }, 1692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1693 }; 1694 1695 static const struct drm_display_mode frida_frd350h54004_mode = { 1696 .clock = 6000, 1697 .hdisplay = 320, 1698 .hsync_start = 320 + 44, 1699 .hsync_end = 320 + 44 + 16, 1700 .htotal = 320 + 44 + 16 + 20, 1701 .vdisplay = 240, 1702 .vsync_start = 240 + 2, 1703 .vsync_end = 240 + 2 + 6, 1704 .vtotal = 240 + 2 + 6 + 2, 1705 .vrefresh = 60, 1706 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1707 }; 1708 1709 static const struct panel_desc frida_frd350h54004 = { 1710 .modes = &frida_frd350h54004_mode, 1711 .num_modes = 1, 1712 .bpc = 8, 1713 .size = { 1714 .width = 77, 1715 .height = 64, 1716 }, 1717 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1718 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1719 .connector_type = DRM_MODE_CONNECTOR_DPI, 1720 }; 1721 1722 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1723 .clock = 67185, 1724 .hdisplay = 800, 1725 .hsync_start = 800 + 20, 1726 .hsync_end = 800 + 20 + 24, 1727 .htotal = 800 + 20 + 24 + 20, 1728 .vdisplay = 1280, 1729 .vsync_start = 1280 + 4, 1730 .vsync_end = 1280 + 4 + 8, 1731 .vtotal = 1280 + 4 + 8 + 4, 1732 .vrefresh = 60, 1733 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1734 }; 1735 1736 static const struct panel_desc friendlyarm_hd702e = { 1737 .modes = &friendlyarm_hd702e_mode, 1738 .num_modes = 1, 1739 .size = { 1740 .width = 94, 1741 .height = 151, 1742 }, 1743 }; 1744 1745 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1746 .clock = 9000, 1747 .hdisplay = 480, 1748 .hsync_start = 480 + 5, 1749 .hsync_end = 480 + 5 + 1, 1750 .htotal = 480 + 5 + 1 + 40, 1751 .vdisplay = 272, 1752 .vsync_start = 272 + 8, 1753 .vsync_end = 272 + 8 + 1, 1754 .vtotal = 272 + 8 + 1 + 8, 1755 .vrefresh = 60, 1756 }; 1757 1758 static const struct panel_desc giantplus_gpg482739qs5 = { 1759 .modes = &giantplus_gpg482739qs5_mode, 1760 .num_modes = 1, 1761 .bpc = 8, 1762 .size = { 1763 .width = 95, 1764 .height = 54, 1765 }, 1766 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1767 }; 1768 1769 static const struct display_timing giantplus_gpm940b0_timing = { 1770 .pixelclock = { 13500000, 27000000, 27500000 }, 1771 .hactive = { 320, 320, 320 }, 1772 .hfront_porch = { 14, 686, 718 }, 1773 .hback_porch = { 50, 70, 255 }, 1774 .hsync_len = { 1, 1, 1 }, 1775 .vactive = { 240, 240, 240 }, 1776 .vfront_porch = { 1, 1, 179 }, 1777 .vback_porch = { 1, 21, 31 }, 1778 .vsync_len = { 1, 1, 6 }, 1779 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1780 }; 1781 1782 static const struct panel_desc giantplus_gpm940b0 = { 1783 .timings = &giantplus_gpm940b0_timing, 1784 .num_timings = 1, 1785 .bpc = 8, 1786 .size = { 1787 .width = 60, 1788 .height = 45, 1789 }, 1790 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1792 }; 1793 1794 static const struct display_timing hannstar_hsd070pww1_timing = { 1795 .pixelclock = { 64300000, 71100000, 82000000 }, 1796 .hactive = { 1280, 1280, 1280 }, 1797 .hfront_porch = { 1, 1, 10 }, 1798 .hback_porch = { 1, 1, 10 }, 1799 /* 1800 * According to the data sheet, the minimum horizontal blanking interval 1801 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1802 * minimum working horizontal blanking interval to be 60 clocks. 1803 */ 1804 .hsync_len = { 58, 158, 661 }, 1805 .vactive = { 800, 800, 800 }, 1806 .vfront_porch = { 1, 1, 10 }, 1807 .vback_porch = { 1, 1, 10 }, 1808 .vsync_len = { 1, 21, 203 }, 1809 .flags = DISPLAY_FLAGS_DE_HIGH, 1810 }; 1811 1812 static const struct panel_desc hannstar_hsd070pww1 = { 1813 .timings = &hannstar_hsd070pww1_timing, 1814 .num_timings = 1, 1815 .bpc = 6, 1816 .size = { 1817 .width = 151, 1818 .height = 94, 1819 }, 1820 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1822 }; 1823 1824 static const struct display_timing hannstar_hsd100pxn1_timing = { 1825 .pixelclock = { 55000000, 65000000, 75000000 }, 1826 .hactive = { 1024, 1024, 1024 }, 1827 .hfront_porch = { 40, 40, 40 }, 1828 .hback_porch = { 220, 220, 220 }, 1829 .hsync_len = { 20, 60, 100 }, 1830 .vactive = { 768, 768, 768 }, 1831 .vfront_porch = { 7, 7, 7 }, 1832 .vback_porch = { 21, 21, 21 }, 1833 .vsync_len = { 10, 10, 10 }, 1834 .flags = DISPLAY_FLAGS_DE_HIGH, 1835 }; 1836 1837 static const struct panel_desc hannstar_hsd100pxn1 = { 1838 .timings = &hannstar_hsd100pxn1_timing, 1839 .num_timings = 1, 1840 .bpc = 6, 1841 .size = { 1842 .width = 203, 1843 .height = 152, 1844 }, 1845 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1846 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1847 }; 1848 1849 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1850 .clock = 33333, 1851 .hdisplay = 800, 1852 .hsync_start = 800 + 85, 1853 .hsync_end = 800 + 85 + 86, 1854 .htotal = 800 + 85 + 86 + 85, 1855 .vdisplay = 480, 1856 .vsync_start = 480 + 16, 1857 .vsync_end = 480 + 16 + 13, 1858 .vtotal = 480 + 16 + 13 + 16, 1859 .vrefresh = 60, 1860 }; 1861 1862 static const struct panel_desc hitachi_tx23d38vm0caa = { 1863 .modes = &hitachi_tx23d38vm0caa_mode, 1864 .num_modes = 1, 1865 .bpc = 6, 1866 .size = { 1867 .width = 195, 1868 .height = 117, 1869 }, 1870 .delay = { 1871 .enable = 160, 1872 .disable = 160, 1873 }, 1874 }; 1875 1876 static const struct drm_display_mode innolux_at043tn24_mode = { 1877 .clock = 9000, 1878 .hdisplay = 480, 1879 .hsync_start = 480 + 2, 1880 .hsync_end = 480 + 2 + 41, 1881 .htotal = 480 + 2 + 41 + 2, 1882 .vdisplay = 272, 1883 .vsync_start = 272 + 2, 1884 .vsync_end = 272 + 2 + 10, 1885 .vtotal = 272 + 2 + 10 + 2, 1886 .vrefresh = 60, 1887 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1888 }; 1889 1890 static const struct panel_desc innolux_at043tn24 = { 1891 .modes = &innolux_at043tn24_mode, 1892 .num_modes = 1, 1893 .bpc = 8, 1894 .size = { 1895 .width = 95, 1896 .height = 54, 1897 }, 1898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1899 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1900 }; 1901 1902 static const struct drm_display_mode innolux_at070tn92_mode = { 1903 .clock = 33333, 1904 .hdisplay = 800, 1905 .hsync_start = 800 + 210, 1906 .hsync_end = 800 + 210 + 20, 1907 .htotal = 800 + 210 + 20 + 46, 1908 .vdisplay = 480, 1909 .vsync_start = 480 + 22, 1910 .vsync_end = 480 + 22 + 10, 1911 .vtotal = 480 + 22 + 23 + 10, 1912 .vrefresh = 60, 1913 }; 1914 1915 static const struct panel_desc innolux_at070tn92 = { 1916 .modes = &innolux_at070tn92_mode, 1917 .num_modes = 1, 1918 .size = { 1919 .width = 154, 1920 .height = 86, 1921 }, 1922 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1923 }; 1924 1925 static const struct display_timing innolux_g070y2_l01_timing = { 1926 .pixelclock = { 28000000, 29500000, 32000000 }, 1927 .hactive = { 800, 800, 800 }, 1928 .hfront_porch = { 61, 91, 141 }, 1929 .hback_porch = { 60, 90, 140 }, 1930 .hsync_len = { 12, 12, 12 }, 1931 .vactive = { 480, 480, 480 }, 1932 .vfront_porch = { 4, 9, 30 }, 1933 .vback_porch = { 4, 8, 28 }, 1934 .vsync_len = { 2, 2, 2 }, 1935 .flags = DISPLAY_FLAGS_DE_HIGH, 1936 }; 1937 1938 static const struct panel_desc innolux_g070y2_l01 = { 1939 .timings = &innolux_g070y2_l01_timing, 1940 .num_timings = 1, 1941 .bpc = 6, 1942 .size = { 1943 .width = 152, 1944 .height = 91, 1945 }, 1946 .delay = { 1947 .prepare = 10, 1948 .enable = 100, 1949 .disable = 100, 1950 .unprepare = 800, 1951 }, 1952 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1953 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1954 }; 1955 1956 static const struct display_timing innolux_g101ice_l01_timing = { 1957 .pixelclock = { 60400000, 71100000, 74700000 }, 1958 .hactive = { 1280, 1280, 1280 }, 1959 .hfront_porch = { 41, 80, 100 }, 1960 .hback_porch = { 40, 79, 99 }, 1961 .hsync_len = { 1, 1, 1 }, 1962 .vactive = { 800, 800, 800 }, 1963 .vfront_porch = { 5, 11, 14 }, 1964 .vback_porch = { 4, 11, 14 }, 1965 .vsync_len = { 1, 1, 1 }, 1966 .flags = DISPLAY_FLAGS_DE_HIGH, 1967 }; 1968 1969 static const struct panel_desc innolux_g101ice_l01 = { 1970 .timings = &innolux_g101ice_l01_timing, 1971 .num_timings = 1, 1972 .bpc = 8, 1973 .size = { 1974 .width = 217, 1975 .height = 135, 1976 }, 1977 .delay = { 1978 .enable = 200, 1979 .disable = 200, 1980 }, 1981 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1982 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1983 }; 1984 1985 static const struct display_timing innolux_g121i1_l01_timing = { 1986 .pixelclock = { 67450000, 71000000, 74550000 }, 1987 .hactive = { 1280, 1280, 1280 }, 1988 .hfront_porch = { 40, 80, 160 }, 1989 .hback_porch = { 39, 79, 159 }, 1990 .hsync_len = { 1, 1, 1 }, 1991 .vactive = { 800, 800, 800 }, 1992 .vfront_porch = { 5, 11, 100 }, 1993 .vback_porch = { 4, 11, 99 }, 1994 .vsync_len = { 1, 1, 1 }, 1995 }; 1996 1997 static const struct panel_desc innolux_g121i1_l01 = { 1998 .timings = &innolux_g121i1_l01_timing, 1999 .num_timings = 1, 2000 .bpc = 6, 2001 .size = { 2002 .width = 261, 2003 .height = 163, 2004 }, 2005 .delay = { 2006 .enable = 200, 2007 .disable = 20, 2008 }, 2009 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2010 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2011 }; 2012 2013 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2014 .clock = 65000, 2015 .hdisplay = 1024, 2016 .hsync_start = 1024 + 0, 2017 .hsync_end = 1024 + 1, 2018 .htotal = 1024 + 0 + 1 + 320, 2019 .vdisplay = 768, 2020 .vsync_start = 768 + 38, 2021 .vsync_end = 768 + 38 + 1, 2022 .vtotal = 768 + 38 + 1 + 0, 2023 .vrefresh = 60, 2024 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2025 }; 2026 2027 static const struct panel_desc innolux_g121x1_l03 = { 2028 .modes = &innolux_g121x1_l03_mode, 2029 .num_modes = 1, 2030 .bpc = 6, 2031 .size = { 2032 .width = 246, 2033 .height = 185, 2034 }, 2035 .delay = { 2036 .enable = 200, 2037 .unprepare = 200, 2038 .disable = 400, 2039 }, 2040 }; 2041 2042 /* 2043 * Datasheet specifies that at 60 Hz refresh rate: 2044 * - total horizontal time: { 1506, 1592, 1716 } 2045 * - total vertical time: { 788, 800, 868 } 2046 * 2047 * ...but doesn't go into exactly how that should be split into a front 2048 * porch, back porch, or sync length. For now we'll leave a single setting 2049 * here which allows a bit of tweaking of the pixel clock at the expense of 2050 * refresh rate. 2051 */ 2052 static const struct display_timing innolux_n116bge_timing = { 2053 .pixelclock = { 72600000, 76420000, 80240000 }, 2054 .hactive = { 1366, 1366, 1366 }, 2055 .hfront_porch = { 136, 136, 136 }, 2056 .hback_porch = { 60, 60, 60 }, 2057 .hsync_len = { 30, 30, 30 }, 2058 .vactive = { 768, 768, 768 }, 2059 .vfront_porch = { 8, 8, 8 }, 2060 .vback_porch = { 12, 12, 12 }, 2061 .vsync_len = { 12, 12, 12 }, 2062 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2063 }; 2064 2065 static const struct panel_desc innolux_n116bge = { 2066 .timings = &innolux_n116bge_timing, 2067 .num_timings = 1, 2068 .bpc = 6, 2069 .size = { 2070 .width = 256, 2071 .height = 144, 2072 }, 2073 }; 2074 2075 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2076 .clock = 69300, 2077 .hdisplay = 1366, 2078 .hsync_start = 1366 + 16, 2079 .hsync_end = 1366 + 16 + 34, 2080 .htotal = 1366 + 16 + 34 + 50, 2081 .vdisplay = 768, 2082 .vsync_start = 768 + 2, 2083 .vsync_end = 768 + 2 + 6, 2084 .vtotal = 768 + 2 + 6 + 12, 2085 .vrefresh = 60, 2086 }; 2087 2088 static const struct panel_desc innolux_n156bge_l21 = { 2089 .modes = &innolux_n156bge_l21_mode, 2090 .num_modes = 1, 2091 .bpc = 6, 2092 .size = { 2093 .width = 344, 2094 .height = 193, 2095 }, 2096 }; 2097 2098 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2099 .clock = 206016, 2100 .hdisplay = 2160, 2101 .hsync_start = 2160 + 48, 2102 .hsync_end = 2160 + 48 + 32, 2103 .htotal = 2160 + 48 + 32 + 80, 2104 .vdisplay = 1440, 2105 .vsync_start = 1440 + 3, 2106 .vsync_end = 1440 + 3 + 10, 2107 .vtotal = 1440 + 3 + 10 + 27, 2108 .vrefresh = 60, 2109 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2110 }; 2111 2112 static const struct panel_desc innolux_p120zdg_bf1 = { 2113 .modes = &innolux_p120zdg_bf1_mode, 2114 .num_modes = 1, 2115 .bpc = 8, 2116 .size = { 2117 .width = 254, 2118 .height = 169, 2119 }, 2120 .delay = { 2121 .hpd_absent_delay = 200, 2122 .unprepare = 500, 2123 }, 2124 }; 2125 2126 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2127 .clock = 51501, 2128 .hdisplay = 1024, 2129 .hsync_start = 1024 + 128, 2130 .hsync_end = 1024 + 128 + 64, 2131 .htotal = 1024 + 128 + 64 + 128, 2132 .vdisplay = 600, 2133 .vsync_start = 600 + 16, 2134 .vsync_end = 600 + 16 + 4, 2135 .vtotal = 600 + 16 + 4 + 16, 2136 .vrefresh = 60, 2137 }; 2138 2139 static const struct panel_desc innolux_zj070na_01p = { 2140 .modes = &innolux_zj070na_01p_mode, 2141 .num_modes = 1, 2142 .bpc = 6, 2143 .size = { 2144 .width = 154, 2145 .height = 90, 2146 }, 2147 }; 2148 2149 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2150 .clock = 138778, 2151 .hdisplay = 1920, 2152 .hsync_start = 1920 + 24, 2153 .hsync_end = 1920 + 24 + 48, 2154 .htotal = 1920 + 24 + 48 + 88, 2155 .vdisplay = 1080, 2156 .vsync_start = 1080 + 3, 2157 .vsync_end = 1080 + 3 + 12, 2158 .vtotal = 1080 + 3 + 12 + 17, 2159 .vrefresh = 60, 2160 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2161 }; 2162 2163 static const struct panel_desc ivo_m133nwf4_r0 = { 2164 .modes = &ivo_m133nwf4_r0_mode, 2165 .num_modes = 1, 2166 .bpc = 8, 2167 .size = { 2168 .width = 294, 2169 .height = 165, 2170 }, 2171 .delay = { 2172 .hpd_absent_delay = 200, 2173 .unprepare = 500, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2176 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2177 .connector_type = DRM_MODE_CONNECTOR_eDP, 2178 }; 2179 2180 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2181 .pixelclock = { 5580000, 5850000, 6200000 }, 2182 .hactive = { 320, 320, 320 }, 2183 .hfront_porch = { 30, 30, 30 }, 2184 .hback_porch = { 30, 30, 30 }, 2185 .hsync_len = { 1, 5, 17 }, 2186 .vactive = { 240, 240, 240 }, 2187 .vfront_porch = { 6, 6, 6 }, 2188 .vback_porch = { 5, 5, 5 }, 2189 .vsync_len = { 1, 2, 11 }, 2190 .flags = DISPLAY_FLAGS_DE_HIGH, 2191 }; 2192 2193 static const struct panel_desc koe_tx14d24vm1bpa = { 2194 .timings = &koe_tx14d24vm1bpa_timing, 2195 .num_timings = 1, 2196 .bpc = 6, 2197 .size = { 2198 .width = 115, 2199 .height = 86, 2200 }, 2201 }; 2202 2203 static const struct display_timing koe_tx31d200vm0baa_timing = { 2204 .pixelclock = { 39600000, 43200000, 48000000 }, 2205 .hactive = { 1280, 1280, 1280 }, 2206 .hfront_porch = { 16, 36, 56 }, 2207 .hback_porch = { 16, 36, 56 }, 2208 .hsync_len = { 8, 8, 8 }, 2209 .vactive = { 480, 480, 480 }, 2210 .vfront_porch = { 6, 21, 33 }, 2211 .vback_porch = { 6, 21, 33 }, 2212 .vsync_len = { 8, 8, 8 }, 2213 .flags = DISPLAY_FLAGS_DE_HIGH, 2214 }; 2215 2216 static const struct panel_desc koe_tx31d200vm0baa = { 2217 .timings = &koe_tx31d200vm0baa_timing, 2218 .num_timings = 1, 2219 .bpc = 6, 2220 .size = { 2221 .width = 292, 2222 .height = 109, 2223 }, 2224 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2225 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2226 }; 2227 2228 static const struct display_timing kyo_tcg121xglp_timing = { 2229 .pixelclock = { 52000000, 65000000, 71000000 }, 2230 .hactive = { 1024, 1024, 1024 }, 2231 .hfront_porch = { 2, 2, 2 }, 2232 .hback_porch = { 2, 2, 2 }, 2233 .hsync_len = { 86, 124, 244 }, 2234 .vactive = { 768, 768, 768 }, 2235 .vfront_porch = { 2, 2, 2 }, 2236 .vback_porch = { 2, 2, 2 }, 2237 .vsync_len = { 6, 34, 73 }, 2238 .flags = DISPLAY_FLAGS_DE_HIGH, 2239 }; 2240 2241 static const struct panel_desc kyo_tcg121xglp = { 2242 .timings = &kyo_tcg121xglp_timing, 2243 .num_timings = 1, 2244 .bpc = 8, 2245 .size = { 2246 .width = 246, 2247 .height = 184, 2248 }, 2249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2250 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2251 }; 2252 2253 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2254 .clock = 7000, 2255 .hdisplay = 320, 2256 .hsync_start = 320 + 20, 2257 .hsync_end = 320 + 20 + 30, 2258 .htotal = 320 + 20 + 30 + 38, 2259 .vdisplay = 240, 2260 .vsync_start = 240 + 4, 2261 .vsync_end = 240 + 4 + 3, 2262 .vtotal = 240 + 4 + 3 + 15, 2263 .vrefresh = 60, 2264 }; 2265 2266 static const struct panel_desc lemaker_bl035_rgb_002 = { 2267 .modes = &lemaker_bl035_rgb_002_mode, 2268 .num_modes = 1, 2269 .size = { 2270 .width = 70, 2271 .height = 52, 2272 }, 2273 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2274 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2275 }; 2276 2277 static const struct drm_display_mode lg_lb070wv8_mode = { 2278 .clock = 33246, 2279 .hdisplay = 800, 2280 .hsync_start = 800 + 88, 2281 .hsync_end = 800 + 88 + 80, 2282 .htotal = 800 + 88 + 80 + 88, 2283 .vdisplay = 480, 2284 .vsync_start = 480 + 10, 2285 .vsync_end = 480 + 10 + 25, 2286 .vtotal = 480 + 10 + 25 + 10, 2287 .vrefresh = 60, 2288 }; 2289 2290 static const struct panel_desc lg_lb070wv8 = { 2291 .modes = &lg_lb070wv8_mode, 2292 .num_modes = 1, 2293 .bpc = 16, 2294 .size = { 2295 .width = 151, 2296 .height = 91, 2297 }, 2298 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2299 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2300 }; 2301 2302 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2303 .clock = 200000, 2304 .hdisplay = 1536, 2305 .hsync_start = 1536 + 12, 2306 .hsync_end = 1536 + 12 + 16, 2307 .htotal = 1536 + 12 + 16 + 48, 2308 .vdisplay = 2048, 2309 .vsync_start = 2048 + 8, 2310 .vsync_end = 2048 + 8 + 4, 2311 .vtotal = 2048 + 8 + 4 + 8, 2312 .vrefresh = 60, 2313 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2314 }; 2315 2316 static const struct panel_desc lg_lp079qx1_sp0v = { 2317 .modes = &lg_lp079qx1_sp0v_mode, 2318 .num_modes = 1, 2319 .size = { 2320 .width = 129, 2321 .height = 171, 2322 }, 2323 }; 2324 2325 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2326 .clock = 205210, 2327 .hdisplay = 2048, 2328 .hsync_start = 2048 + 150, 2329 .hsync_end = 2048 + 150 + 5, 2330 .htotal = 2048 + 150 + 5 + 5, 2331 .vdisplay = 1536, 2332 .vsync_start = 1536 + 3, 2333 .vsync_end = 1536 + 3 + 1, 2334 .vtotal = 1536 + 3 + 1 + 9, 2335 .vrefresh = 60, 2336 }; 2337 2338 static const struct panel_desc lg_lp097qx1_spa1 = { 2339 .modes = &lg_lp097qx1_spa1_mode, 2340 .num_modes = 1, 2341 .size = { 2342 .width = 208, 2343 .height = 147, 2344 }, 2345 }; 2346 2347 static const struct drm_display_mode lg_lp120up1_mode = { 2348 .clock = 162300, 2349 .hdisplay = 1920, 2350 .hsync_start = 1920 + 40, 2351 .hsync_end = 1920 + 40 + 40, 2352 .htotal = 1920 + 40 + 40+ 80, 2353 .vdisplay = 1280, 2354 .vsync_start = 1280 + 4, 2355 .vsync_end = 1280 + 4 + 4, 2356 .vtotal = 1280 + 4 + 4 + 12, 2357 .vrefresh = 60, 2358 }; 2359 2360 static const struct panel_desc lg_lp120up1 = { 2361 .modes = &lg_lp120up1_mode, 2362 .num_modes = 1, 2363 .bpc = 8, 2364 .size = { 2365 .width = 267, 2366 .height = 183, 2367 }, 2368 .connector_type = DRM_MODE_CONNECTOR_eDP, 2369 }; 2370 2371 static const struct drm_display_mode lg_lp129qe_mode = { 2372 .clock = 285250, 2373 .hdisplay = 2560, 2374 .hsync_start = 2560 + 48, 2375 .hsync_end = 2560 + 48 + 32, 2376 .htotal = 2560 + 48 + 32 + 80, 2377 .vdisplay = 1700, 2378 .vsync_start = 1700 + 3, 2379 .vsync_end = 1700 + 3 + 10, 2380 .vtotal = 1700 + 3 + 10 + 36, 2381 .vrefresh = 60, 2382 }; 2383 2384 static const struct panel_desc lg_lp129qe = { 2385 .modes = &lg_lp129qe_mode, 2386 .num_modes = 1, 2387 .bpc = 8, 2388 .size = { 2389 .width = 272, 2390 .height = 181, 2391 }, 2392 }; 2393 2394 static const struct display_timing logictechno_lt161010_2nh_timing = { 2395 .pixelclock = { 26400000, 33300000, 46800000 }, 2396 .hactive = { 800, 800, 800 }, 2397 .hfront_porch = { 16, 210, 354 }, 2398 .hback_porch = { 46, 46, 46 }, 2399 .hsync_len = { 1, 20, 40 }, 2400 .vactive = { 480, 480, 480 }, 2401 .vfront_porch = { 7, 22, 147 }, 2402 .vback_porch = { 23, 23, 23 }, 2403 .vsync_len = { 1, 10, 20 }, 2404 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2405 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2406 DISPLAY_FLAGS_SYNC_POSEDGE, 2407 }; 2408 2409 static const struct panel_desc logictechno_lt161010_2nh = { 2410 .timings = &logictechno_lt161010_2nh_timing, 2411 .num_timings = 1, 2412 .size = { 2413 .width = 154, 2414 .height = 86, 2415 }, 2416 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2417 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2418 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2419 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2420 .connector_type = DRM_MODE_CONNECTOR_DPI, 2421 }; 2422 2423 static const struct display_timing logictechno_lt170410_2whc_timing = { 2424 .pixelclock = { 68900000, 71100000, 73400000 }, 2425 .hactive = { 1280, 1280, 1280 }, 2426 .hfront_porch = { 23, 60, 71 }, 2427 .hback_porch = { 23, 60, 71 }, 2428 .hsync_len = { 15, 40, 47 }, 2429 .vactive = { 800, 800, 800 }, 2430 .vfront_porch = { 5, 7, 10 }, 2431 .vback_porch = { 5, 7, 10 }, 2432 .vsync_len = { 6, 9, 12 }, 2433 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2434 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2435 DISPLAY_FLAGS_SYNC_POSEDGE, 2436 }; 2437 2438 static const struct panel_desc logictechno_lt170410_2whc = { 2439 .timings = &logictechno_lt170410_2whc_timing, 2440 .num_timings = 1, 2441 .size = { 2442 .width = 217, 2443 .height = 136, 2444 }, 2445 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2446 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2447 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2448 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2449 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2450 }; 2451 2452 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2453 .clock = 30400, 2454 .hdisplay = 800, 2455 .hsync_start = 800 + 0, 2456 .hsync_end = 800 + 1, 2457 .htotal = 800 + 0 + 1 + 160, 2458 .vdisplay = 480, 2459 .vsync_start = 480 + 0, 2460 .vsync_end = 480 + 48 + 1, 2461 .vtotal = 480 + 48 + 1 + 0, 2462 .vrefresh = 60, 2463 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2464 }; 2465 2466 static const struct drm_display_mode logicpd_type_28_mode = { 2467 .clock = 9107, 2468 .hdisplay = 480, 2469 .hsync_start = 480 + 3, 2470 .hsync_end = 480 + 3 + 42, 2471 .htotal = 480 + 3 + 42 + 2, 2472 2473 .vdisplay = 272, 2474 .vsync_start = 272 + 2, 2475 .vsync_end = 272 + 2 + 11, 2476 .vtotal = 272 + 2 + 11 + 3, 2477 .vrefresh = 60, 2478 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2479 }; 2480 2481 static const struct panel_desc logicpd_type_28 = { 2482 .modes = &logicpd_type_28_mode, 2483 .num_modes = 1, 2484 .bpc = 8, 2485 .size = { 2486 .width = 105, 2487 .height = 67, 2488 }, 2489 .delay = { 2490 .prepare = 200, 2491 .enable = 200, 2492 .unprepare = 200, 2493 .disable = 200, 2494 }, 2495 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2496 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2497 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2498 .connector_type = DRM_MODE_CONNECTOR_DPI, 2499 }; 2500 2501 static const struct panel_desc mitsubishi_aa070mc01 = { 2502 .modes = &mitsubishi_aa070mc01_mode, 2503 .num_modes = 1, 2504 .bpc = 8, 2505 .size = { 2506 .width = 152, 2507 .height = 91, 2508 }, 2509 2510 .delay = { 2511 .enable = 200, 2512 .unprepare = 200, 2513 .disable = 400, 2514 }, 2515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2517 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2518 }; 2519 2520 static const struct display_timing nec_nl12880bc20_05_timing = { 2521 .pixelclock = { 67000000, 71000000, 75000000 }, 2522 .hactive = { 1280, 1280, 1280 }, 2523 .hfront_porch = { 2, 30, 30 }, 2524 .hback_porch = { 6, 100, 100 }, 2525 .hsync_len = { 2, 30, 30 }, 2526 .vactive = { 800, 800, 800 }, 2527 .vfront_porch = { 5, 5, 5 }, 2528 .vback_porch = { 11, 11, 11 }, 2529 .vsync_len = { 7, 7, 7 }, 2530 }; 2531 2532 static const struct panel_desc nec_nl12880bc20_05 = { 2533 .timings = &nec_nl12880bc20_05_timing, 2534 .num_timings = 1, 2535 .bpc = 8, 2536 .size = { 2537 .width = 261, 2538 .height = 163, 2539 }, 2540 .delay = { 2541 .enable = 50, 2542 .disable = 50, 2543 }, 2544 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2545 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2546 }; 2547 2548 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2549 .clock = 10870, 2550 .hdisplay = 480, 2551 .hsync_start = 480 + 2, 2552 .hsync_end = 480 + 2 + 41, 2553 .htotal = 480 + 2 + 41 + 2, 2554 .vdisplay = 272, 2555 .vsync_start = 272 + 2, 2556 .vsync_end = 272 + 2 + 4, 2557 .vtotal = 272 + 2 + 4 + 2, 2558 .vrefresh = 74, 2559 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2560 }; 2561 2562 static const struct panel_desc nec_nl4827hc19_05b = { 2563 .modes = &nec_nl4827hc19_05b_mode, 2564 .num_modes = 1, 2565 .bpc = 8, 2566 .size = { 2567 .width = 95, 2568 .height = 54, 2569 }, 2570 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2571 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2572 }; 2573 2574 static const struct drm_display_mode netron_dy_e231732_mode = { 2575 .clock = 66000, 2576 .hdisplay = 1024, 2577 .hsync_start = 1024 + 160, 2578 .hsync_end = 1024 + 160 + 70, 2579 .htotal = 1024 + 160 + 70 + 90, 2580 .vdisplay = 600, 2581 .vsync_start = 600 + 127, 2582 .vsync_end = 600 + 127 + 20, 2583 .vtotal = 600 + 127 + 20 + 3, 2584 .vrefresh = 60, 2585 }; 2586 2587 static const struct panel_desc netron_dy_e231732 = { 2588 .modes = &netron_dy_e231732_mode, 2589 .num_modes = 1, 2590 .size = { 2591 .width = 154, 2592 .height = 87, 2593 }, 2594 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2595 }; 2596 2597 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2598 { 2599 .clock = 138500, 2600 .hdisplay = 1920, 2601 .hsync_start = 1920 + 48, 2602 .hsync_end = 1920 + 48 + 32, 2603 .htotal = 1920 + 48 + 32 + 80, 2604 .vdisplay = 1080, 2605 .vsync_start = 1080 + 3, 2606 .vsync_end = 1080 + 3 + 5, 2607 .vtotal = 1080 + 3 + 5 + 23, 2608 .vrefresh = 60, 2609 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2610 }, { 2611 .clock = 110920, 2612 .hdisplay = 1920, 2613 .hsync_start = 1920 + 48, 2614 .hsync_end = 1920 + 48 + 32, 2615 .htotal = 1920 + 48 + 32 + 80, 2616 .vdisplay = 1080, 2617 .vsync_start = 1080 + 3, 2618 .vsync_end = 1080 + 3 + 5, 2619 .vtotal = 1080 + 3 + 5 + 23, 2620 .vrefresh = 48, 2621 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2622 } 2623 }; 2624 2625 static const struct panel_desc neweast_wjfh116008a = { 2626 .modes = neweast_wjfh116008a_modes, 2627 .num_modes = 2, 2628 .bpc = 6, 2629 .size = { 2630 .width = 260, 2631 .height = 150, 2632 }, 2633 .delay = { 2634 .prepare = 110, 2635 .enable = 20, 2636 .unprepare = 500, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2639 .connector_type = DRM_MODE_CONNECTOR_eDP, 2640 }; 2641 2642 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2643 .clock = 9000, 2644 .hdisplay = 480, 2645 .hsync_start = 480 + 2, 2646 .hsync_end = 480 + 2 + 41, 2647 .htotal = 480 + 2 + 41 + 2, 2648 .vdisplay = 272, 2649 .vsync_start = 272 + 2, 2650 .vsync_end = 272 + 2 + 10, 2651 .vtotal = 272 + 2 + 10 + 2, 2652 .vrefresh = 60, 2653 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2654 }; 2655 2656 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2657 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2658 .num_modes = 1, 2659 .bpc = 8, 2660 .size = { 2661 .width = 95, 2662 .height = 54, 2663 }, 2664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2665 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2666 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2667 .connector_type = DRM_MODE_CONNECTOR_DPI, 2668 }; 2669 2670 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2671 .pixelclock = { 130000000, 148350000, 163000000 }, 2672 .hactive = { 1920, 1920, 1920 }, 2673 .hfront_porch = { 80, 100, 100 }, 2674 .hback_porch = { 100, 120, 120 }, 2675 .hsync_len = { 50, 60, 60 }, 2676 .vactive = { 1080, 1080, 1080 }, 2677 .vfront_porch = { 12, 30, 30 }, 2678 .vback_porch = { 4, 10, 10 }, 2679 .vsync_len = { 4, 5, 5 }, 2680 }; 2681 2682 static const struct panel_desc nlt_nl192108ac18_02d = { 2683 .timings = &nlt_nl192108ac18_02d_timing, 2684 .num_timings = 1, 2685 .bpc = 8, 2686 .size = { 2687 .width = 344, 2688 .height = 194, 2689 }, 2690 .delay = { 2691 .unprepare = 500, 2692 }, 2693 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2694 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2695 }; 2696 2697 static const struct drm_display_mode nvd_9128_mode = { 2698 .clock = 29500, 2699 .hdisplay = 800, 2700 .hsync_start = 800 + 130, 2701 .hsync_end = 800 + 130 + 98, 2702 .htotal = 800 + 0 + 130 + 98, 2703 .vdisplay = 480, 2704 .vsync_start = 480 + 10, 2705 .vsync_end = 480 + 10 + 50, 2706 .vtotal = 480 + 0 + 10 + 50, 2707 }; 2708 2709 static const struct panel_desc nvd_9128 = { 2710 .modes = &nvd_9128_mode, 2711 .num_modes = 1, 2712 .bpc = 8, 2713 .size = { 2714 .width = 156, 2715 .height = 88, 2716 }, 2717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2718 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2719 }; 2720 2721 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2722 .pixelclock = { 30000000, 30000000, 40000000 }, 2723 .hactive = { 800, 800, 800 }, 2724 .hfront_porch = { 40, 40, 40 }, 2725 .hback_porch = { 40, 40, 40 }, 2726 .hsync_len = { 1, 48, 48 }, 2727 .vactive = { 480, 480, 480 }, 2728 .vfront_porch = { 13, 13, 13 }, 2729 .vback_porch = { 29, 29, 29 }, 2730 .vsync_len = { 3, 3, 3 }, 2731 .flags = DISPLAY_FLAGS_DE_HIGH, 2732 }; 2733 2734 static const struct panel_desc okaya_rs800480t_7x0gp = { 2735 .timings = &okaya_rs800480t_7x0gp_timing, 2736 .num_timings = 1, 2737 .bpc = 6, 2738 .size = { 2739 .width = 154, 2740 .height = 87, 2741 }, 2742 .delay = { 2743 .prepare = 41, 2744 .enable = 50, 2745 .unprepare = 41, 2746 .disable = 50, 2747 }, 2748 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2749 }; 2750 2751 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2752 .clock = 9000, 2753 .hdisplay = 480, 2754 .hsync_start = 480 + 5, 2755 .hsync_end = 480 + 5 + 30, 2756 .htotal = 480 + 5 + 30 + 10, 2757 .vdisplay = 272, 2758 .vsync_start = 272 + 8, 2759 .vsync_end = 272 + 8 + 5, 2760 .vtotal = 272 + 8 + 5 + 3, 2761 .vrefresh = 60, 2762 }; 2763 2764 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2765 .modes = &olimex_lcd_olinuxino_43ts_mode, 2766 .num_modes = 1, 2767 .size = { 2768 .width = 95, 2769 .height = 54, 2770 }, 2771 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2772 }; 2773 2774 /* 2775 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2776 * pixel clocks, but this is the timing that was being used in the Adafruit 2777 * installation instructions. 2778 */ 2779 static const struct drm_display_mode ontat_yx700wv03_mode = { 2780 .clock = 29500, 2781 .hdisplay = 800, 2782 .hsync_start = 824, 2783 .hsync_end = 896, 2784 .htotal = 992, 2785 .vdisplay = 480, 2786 .vsync_start = 483, 2787 .vsync_end = 493, 2788 .vtotal = 500, 2789 .vrefresh = 60, 2790 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2791 }; 2792 2793 /* 2794 * Specification at: 2795 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2796 */ 2797 static const struct panel_desc ontat_yx700wv03 = { 2798 .modes = &ontat_yx700wv03_mode, 2799 .num_modes = 1, 2800 .bpc = 8, 2801 .size = { 2802 .width = 154, 2803 .height = 83, 2804 }, 2805 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2806 }; 2807 2808 static const struct drm_display_mode ortustech_com37h3m_mode = { 2809 .clock = 22230, 2810 .hdisplay = 480, 2811 .hsync_start = 480 + 40, 2812 .hsync_end = 480 + 40 + 10, 2813 .htotal = 480 + 40 + 10 + 40, 2814 .vdisplay = 640, 2815 .vsync_start = 640 + 4, 2816 .vsync_end = 640 + 4 + 2, 2817 .vtotal = 640 + 4 + 2 + 4, 2818 .vrefresh = 60, 2819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2820 }; 2821 2822 static const struct panel_desc ortustech_com37h3m = { 2823 .modes = &ortustech_com37h3m_mode, 2824 .num_modes = 1, 2825 .bpc = 8, 2826 .size = { 2827 .width = 56, /* 56.16mm */ 2828 .height = 75, /* 74.88mm */ 2829 }, 2830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2832 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2833 }; 2834 2835 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2836 .clock = 25000, 2837 .hdisplay = 480, 2838 .hsync_start = 480 + 10, 2839 .hsync_end = 480 + 10 + 10, 2840 .htotal = 480 + 10 + 10 + 15, 2841 .vdisplay = 800, 2842 .vsync_start = 800 + 3, 2843 .vsync_end = 800 + 3 + 3, 2844 .vtotal = 800 + 3 + 3 + 3, 2845 .vrefresh = 60, 2846 }; 2847 2848 static const struct panel_desc ortustech_com43h4m85ulc = { 2849 .modes = &ortustech_com43h4m85ulc_mode, 2850 .num_modes = 1, 2851 .bpc = 8, 2852 .size = { 2853 .width = 56, 2854 .height = 93, 2855 }, 2856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2858 .connector_type = DRM_MODE_CONNECTOR_DPI, 2859 }; 2860 2861 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2862 .clock = 33000, 2863 .hdisplay = 800, 2864 .hsync_start = 800 + 210, 2865 .hsync_end = 800 + 210 + 30, 2866 .htotal = 800 + 210 + 30 + 16, 2867 .vdisplay = 480, 2868 .vsync_start = 480 + 22, 2869 .vsync_end = 480 + 22 + 13, 2870 .vtotal = 480 + 22 + 13 + 10, 2871 .vrefresh = 60, 2872 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2873 }; 2874 2875 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2876 .modes = &osddisplays_osd070t1718_19ts_mode, 2877 .num_modes = 1, 2878 .bpc = 8, 2879 .size = { 2880 .width = 152, 2881 .height = 91, 2882 }, 2883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2885 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2886 .connector_type = DRM_MODE_CONNECTOR_DPI, 2887 }; 2888 2889 static const struct drm_display_mode pda_91_00156_a0_mode = { 2890 .clock = 33300, 2891 .hdisplay = 800, 2892 .hsync_start = 800 + 1, 2893 .hsync_end = 800 + 1 + 64, 2894 .htotal = 800 + 1 + 64 + 64, 2895 .vdisplay = 480, 2896 .vsync_start = 480 + 1, 2897 .vsync_end = 480 + 1 + 23, 2898 .vtotal = 480 + 1 + 23 + 22, 2899 .vrefresh = 60, 2900 }; 2901 2902 static const struct panel_desc pda_91_00156_a0 = { 2903 .modes = &pda_91_00156_a0_mode, 2904 .num_modes = 1, 2905 .size = { 2906 .width = 152, 2907 .height = 91, 2908 }, 2909 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2910 }; 2911 2912 2913 static const struct drm_display_mode qd43003c0_40_mode = { 2914 .clock = 9000, 2915 .hdisplay = 480, 2916 .hsync_start = 480 + 8, 2917 .hsync_end = 480 + 8 + 4, 2918 .htotal = 480 + 8 + 4 + 39, 2919 .vdisplay = 272, 2920 .vsync_start = 272 + 4, 2921 .vsync_end = 272 + 4 + 10, 2922 .vtotal = 272 + 4 + 10 + 2, 2923 .vrefresh = 60, 2924 }; 2925 2926 static const struct panel_desc qd43003c0_40 = { 2927 .modes = &qd43003c0_40_mode, 2928 .num_modes = 1, 2929 .bpc = 8, 2930 .size = { 2931 .width = 95, 2932 .height = 53, 2933 }, 2934 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2935 }; 2936 2937 static const struct display_timing rocktech_rk070er9427_timing = { 2938 .pixelclock = { 26400000, 33300000, 46800000 }, 2939 .hactive = { 800, 800, 800 }, 2940 .hfront_porch = { 16, 210, 354 }, 2941 .hback_porch = { 46, 46, 46 }, 2942 .hsync_len = { 1, 1, 1 }, 2943 .vactive = { 480, 480, 480 }, 2944 .vfront_porch = { 7, 22, 147 }, 2945 .vback_porch = { 23, 23, 23 }, 2946 .vsync_len = { 1, 1, 1 }, 2947 .flags = DISPLAY_FLAGS_DE_HIGH, 2948 }; 2949 2950 static const struct panel_desc rocktech_rk070er9427 = { 2951 .timings = &rocktech_rk070er9427_timing, 2952 .num_timings = 1, 2953 .bpc = 6, 2954 .size = { 2955 .width = 154, 2956 .height = 86, 2957 }, 2958 .delay = { 2959 .prepare = 41, 2960 .enable = 50, 2961 .unprepare = 41, 2962 .disable = 50, 2963 }, 2964 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2965 }; 2966 2967 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2968 .clock = 71100, 2969 .hdisplay = 1280, 2970 .hsync_start = 1280 + 48, 2971 .hsync_end = 1280 + 48 + 32, 2972 .htotal = 1280 + 48 + 32 + 80, 2973 .vdisplay = 800, 2974 .vsync_start = 800 + 2, 2975 .vsync_end = 800 + 2 + 5, 2976 .vtotal = 800 + 2 + 5 + 16, 2977 .vrefresh = 60, 2978 }; 2979 2980 static const struct panel_desc rocktech_rk101ii01d_ct = { 2981 .modes = &rocktech_rk101ii01d_ct_mode, 2982 .num_modes = 1, 2983 .size = { 2984 .width = 217, 2985 .height = 136, 2986 }, 2987 .delay = { 2988 .prepare = 50, 2989 .disable = 50, 2990 }, 2991 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2992 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2993 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2994 }; 2995 2996 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2997 .clock = 271560, 2998 .hdisplay = 2560, 2999 .hsync_start = 2560 + 48, 3000 .hsync_end = 2560 + 48 + 32, 3001 .htotal = 2560 + 48 + 32 + 80, 3002 .vdisplay = 1600, 3003 .vsync_start = 1600 + 2, 3004 .vsync_end = 1600 + 2 + 5, 3005 .vtotal = 1600 + 2 + 5 + 57, 3006 .vrefresh = 60, 3007 }; 3008 3009 static const struct panel_desc samsung_lsn122dl01_c01 = { 3010 .modes = &samsung_lsn122dl01_c01_mode, 3011 .num_modes = 1, 3012 .size = { 3013 .width = 263, 3014 .height = 164, 3015 }, 3016 }; 3017 3018 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3019 .clock = 54030, 3020 .hdisplay = 1024, 3021 .hsync_start = 1024 + 24, 3022 .hsync_end = 1024 + 24 + 136, 3023 .htotal = 1024 + 24 + 136 + 160, 3024 .vdisplay = 600, 3025 .vsync_start = 600 + 3, 3026 .vsync_end = 600 + 3 + 6, 3027 .vtotal = 600 + 3 + 6 + 61, 3028 .vrefresh = 60, 3029 }; 3030 3031 static const struct panel_desc samsung_ltn101nt05 = { 3032 .modes = &samsung_ltn101nt05_mode, 3033 .num_modes = 1, 3034 .bpc = 6, 3035 .size = { 3036 .width = 223, 3037 .height = 125, 3038 }, 3039 }; 3040 3041 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3042 .clock = 76300, 3043 .hdisplay = 1366, 3044 .hsync_start = 1366 + 64, 3045 .hsync_end = 1366 + 64 + 48, 3046 .htotal = 1366 + 64 + 48 + 128, 3047 .vdisplay = 768, 3048 .vsync_start = 768 + 2, 3049 .vsync_end = 768 + 2 + 5, 3050 .vtotal = 768 + 2 + 5 + 17, 3051 .vrefresh = 60, 3052 }; 3053 3054 static const struct panel_desc samsung_ltn140at29_301 = { 3055 .modes = &samsung_ltn140at29_301_mode, 3056 .num_modes = 1, 3057 .bpc = 6, 3058 .size = { 3059 .width = 320, 3060 .height = 187, 3061 }, 3062 }; 3063 3064 static const struct display_timing satoz_sat050at40h12r2_timing = { 3065 .pixelclock = {33300000, 33300000, 50000000}, 3066 .hactive = {800, 800, 800}, 3067 .hfront_porch = {16, 210, 354}, 3068 .hback_porch = {46, 46, 46}, 3069 .hsync_len = {1, 1, 40}, 3070 .vactive = {480, 480, 480}, 3071 .vfront_porch = {7, 22, 147}, 3072 .vback_porch = {23, 23, 23}, 3073 .vsync_len = {1, 1, 20}, 3074 }; 3075 3076 static const struct panel_desc satoz_sat050at40h12r2 = { 3077 .timings = &satoz_sat050at40h12r2_timing, 3078 .num_timings = 1, 3079 .bpc = 8, 3080 .size = { 3081 .width = 108, 3082 .height = 65, 3083 }, 3084 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3085 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3086 }; 3087 3088 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3089 .clock = 168480, 3090 .hdisplay = 1920, 3091 .hsync_start = 1920 + 48, 3092 .hsync_end = 1920 + 48 + 32, 3093 .htotal = 1920 + 48 + 32 + 80, 3094 .vdisplay = 1280, 3095 .vsync_start = 1280 + 3, 3096 .vsync_end = 1280 + 3 + 10, 3097 .vtotal = 1280 + 3 + 10 + 57, 3098 .vrefresh = 60, 3099 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3100 }; 3101 3102 static const struct panel_desc sharp_ld_d5116z01b = { 3103 .modes = &sharp_ld_d5116z01b_mode, 3104 .num_modes = 1, 3105 .bpc = 8, 3106 .size = { 3107 .width = 260, 3108 .height = 120, 3109 }, 3110 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3111 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3112 }; 3113 3114 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3115 .clock = 33260, 3116 .hdisplay = 800, 3117 .hsync_start = 800 + 64, 3118 .hsync_end = 800 + 64 + 128, 3119 .htotal = 800 + 64 + 128 + 64, 3120 .vdisplay = 480, 3121 .vsync_start = 480 + 8, 3122 .vsync_end = 480 + 8 + 2, 3123 .vtotal = 480 + 8 + 2 + 35, 3124 .vrefresh = 60, 3125 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3126 }; 3127 3128 static const struct panel_desc sharp_lq070y3dg3b = { 3129 .modes = &sharp_lq070y3dg3b_mode, 3130 .num_modes = 1, 3131 .bpc = 8, 3132 .size = { 3133 .width = 152, /* 152.4mm */ 3134 .height = 91, /* 91.4mm */ 3135 }, 3136 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3137 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 3138 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3139 }; 3140 3141 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3142 .clock = 5500, 3143 .hdisplay = 240, 3144 .hsync_start = 240 + 16, 3145 .hsync_end = 240 + 16 + 7, 3146 .htotal = 240 + 16 + 7 + 5, 3147 .vdisplay = 320, 3148 .vsync_start = 320 + 9, 3149 .vsync_end = 320 + 9 + 1, 3150 .vtotal = 320 + 9 + 1 + 7, 3151 .vrefresh = 60, 3152 }; 3153 3154 static const struct panel_desc sharp_lq035q7db03 = { 3155 .modes = &sharp_lq035q7db03_mode, 3156 .num_modes = 1, 3157 .bpc = 6, 3158 .size = { 3159 .width = 54, 3160 .height = 72, 3161 }, 3162 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3163 }; 3164 3165 static const struct display_timing sharp_lq101k1ly04_timing = { 3166 .pixelclock = { 60000000, 65000000, 80000000 }, 3167 .hactive = { 1280, 1280, 1280 }, 3168 .hfront_porch = { 20, 20, 20 }, 3169 .hback_porch = { 20, 20, 20 }, 3170 .hsync_len = { 10, 10, 10 }, 3171 .vactive = { 800, 800, 800 }, 3172 .vfront_porch = { 4, 4, 4 }, 3173 .vback_porch = { 4, 4, 4 }, 3174 .vsync_len = { 4, 4, 4 }, 3175 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3176 }; 3177 3178 static const struct panel_desc sharp_lq101k1ly04 = { 3179 .timings = &sharp_lq101k1ly04_timing, 3180 .num_timings = 1, 3181 .bpc = 8, 3182 .size = { 3183 .width = 217, 3184 .height = 136, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3187 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3188 }; 3189 3190 static const struct display_timing sharp_lq123p1jx31_timing = { 3191 .pixelclock = { 252750000, 252750000, 266604720 }, 3192 .hactive = { 2400, 2400, 2400 }, 3193 .hfront_porch = { 48, 48, 48 }, 3194 .hback_porch = { 80, 80, 84 }, 3195 .hsync_len = { 32, 32, 32 }, 3196 .vactive = { 1600, 1600, 1600 }, 3197 .vfront_porch = { 3, 3, 3 }, 3198 .vback_porch = { 33, 33, 120 }, 3199 .vsync_len = { 10, 10, 10 }, 3200 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3201 }; 3202 3203 static const struct panel_desc sharp_lq123p1jx31 = { 3204 .timings = &sharp_lq123p1jx31_timing, 3205 .num_timings = 1, 3206 .bpc = 8, 3207 .size = { 3208 .width = 259, 3209 .height = 173, 3210 }, 3211 .delay = { 3212 .prepare = 110, 3213 .enable = 50, 3214 .unprepare = 550, 3215 }, 3216 }; 3217 3218 static const struct display_timing sharp_ls020b1dd01d_timing = { 3219 .pixelclock = { 2000000, 4200000, 5000000 }, 3220 .hactive = { 240, 240, 240 }, 3221 .hfront_porch = { 66, 66, 66 }, 3222 .hback_porch = { 1, 1, 1 }, 3223 .hsync_len = { 1, 1, 1 }, 3224 .vactive = { 160, 160, 160 }, 3225 .vfront_porch = { 52, 52, 52 }, 3226 .vback_porch = { 6, 6, 6 }, 3227 .vsync_len = { 10, 10, 10 }, 3228 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3229 }; 3230 3231 static const struct panel_desc sharp_ls020b1dd01d = { 3232 .timings = &sharp_ls020b1dd01d_timing, 3233 .num_timings = 1, 3234 .bpc = 6, 3235 .size = { 3236 .width = 42, 3237 .height = 28, 3238 }, 3239 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3240 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3241 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3242 | DRM_BUS_FLAG_SHARP_SIGNALS, 3243 }; 3244 3245 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3246 .clock = 33300, 3247 .hdisplay = 800, 3248 .hsync_start = 800 + 1, 3249 .hsync_end = 800 + 1 + 64, 3250 .htotal = 800 + 1 + 64 + 64, 3251 .vdisplay = 480, 3252 .vsync_start = 480 + 1, 3253 .vsync_end = 480 + 1 + 23, 3254 .vtotal = 480 + 1 + 23 + 22, 3255 .vrefresh = 60, 3256 }; 3257 3258 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3259 .modes = &shelly_sca07010_bfn_lnn_mode, 3260 .num_modes = 1, 3261 .size = { 3262 .width = 152, 3263 .height = 91, 3264 }, 3265 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3266 }; 3267 3268 static const struct drm_display_mode starry_kr070pe2t_mode = { 3269 .clock = 33000, 3270 .hdisplay = 800, 3271 .hsync_start = 800 + 209, 3272 .hsync_end = 800 + 209 + 1, 3273 .htotal = 800 + 209 + 1 + 45, 3274 .vdisplay = 480, 3275 .vsync_start = 480 + 22, 3276 .vsync_end = 480 + 22 + 1, 3277 .vtotal = 480 + 22 + 1 + 22, 3278 .vrefresh = 60, 3279 }; 3280 3281 static const struct panel_desc starry_kr070pe2t = { 3282 .modes = &starry_kr070pe2t_mode, 3283 .num_modes = 1, 3284 .bpc = 8, 3285 .size = { 3286 .width = 152, 3287 .height = 86, 3288 }, 3289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3291 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3292 }; 3293 3294 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3295 .clock = 147000, 3296 .hdisplay = 1920, 3297 .hsync_start = 1920 + 16, 3298 .hsync_end = 1920 + 16 + 16, 3299 .htotal = 1920 + 16 + 16 + 32, 3300 .vdisplay = 1200, 3301 .vsync_start = 1200 + 15, 3302 .vsync_end = 1200 + 15 + 2, 3303 .vtotal = 1200 + 15 + 2 + 18, 3304 .vrefresh = 60, 3305 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3306 }; 3307 3308 static const struct panel_desc starry_kr122ea0sra = { 3309 .modes = &starry_kr122ea0sra_mode, 3310 .num_modes = 1, 3311 .size = { 3312 .width = 263, 3313 .height = 164, 3314 }, 3315 .delay = { 3316 .prepare = 10 + 200, 3317 .enable = 50, 3318 .unprepare = 10 + 500, 3319 }, 3320 }; 3321 3322 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3323 .clock = 30000, 3324 .hdisplay = 800, 3325 .hsync_start = 800 + 39, 3326 .hsync_end = 800 + 39 + 47, 3327 .htotal = 800 + 39 + 47 + 39, 3328 .vdisplay = 480, 3329 .vsync_start = 480 + 13, 3330 .vsync_end = 480 + 13 + 2, 3331 .vtotal = 480 + 13 + 2 + 29, 3332 .vrefresh = 62, 3333 }; 3334 3335 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3336 .modes = &tfc_s9700rtwv43tr_01b_mode, 3337 .num_modes = 1, 3338 .bpc = 8, 3339 .size = { 3340 .width = 155, 3341 .height = 90, 3342 }, 3343 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3344 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3345 }; 3346 3347 static const struct display_timing tianma_tm070jdhg30_timing = { 3348 .pixelclock = { 62600000, 68200000, 78100000 }, 3349 .hactive = { 1280, 1280, 1280 }, 3350 .hfront_porch = { 15, 64, 159 }, 3351 .hback_porch = { 5, 5, 5 }, 3352 .hsync_len = { 1, 1, 256 }, 3353 .vactive = { 800, 800, 800 }, 3354 .vfront_porch = { 3, 40, 99 }, 3355 .vback_porch = { 2, 2, 2 }, 3356 .vsync_len = { 1, 1, 128 }, 3357 .flags = DISPLAY_FLAGS_DE_HIGH, 3358 }; 3359 3360 static const struct panel_desc tianma_tm070jdhg30 = { 3361 .timings = &tianma_tm070jdhg30_timing, 3362 .num_timings = 1, 3363 .bpc = 8, 3364 .size = { 3365 .width = 151, 3366 .height = 95, 3367 }, 3368 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3369 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3370 }; 3371 3372 static const struct display_timing tianma_tm070rvhg71_timing = { 3373 .pixelclock = { 27700000, 29200000, 39600000 }, 3374 .hactive = { 800, 800, 800 }, 3375 .hfront_porch = { 12, 40, 212 }, 3376 .hback_porch = { 88, 88, 88 }, 3377 .hsync_len = { 1, 1, 40 }, 3378 .vactive = { 480, 480, 480 }, 3379 .vfront_porch = { 1, 13, 88 }, 3380 .vback_porch = { 32, 32, 32 }, 3381 .vsync_len = { 1, 1, 3 }, 3382 .flags = DISPLAY_FLAGS_DE_HIGH, 3383 }; 3384 3385 static const struct panel_desc tianma_tm070rvhg71 = { 3386 .timings = &tianma_tm070rvhg71_timing, 3387 .num_timings = 1, 3388 .bpc = 8, 3389 .size = { 3390 .width = 154, 3391 .height = 86, 3392 }, 3393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3394 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3395 }; 3396 3397 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3398 { 3399 .clock = 10000, 3400 .hdisplay = 320, 3401 .hsync_start = 320 + 50, 3402 .hsync_end = 320 + 50 + 6, 3403 .htotal = 320 + 50 + 6 + 38, 3404 .vdisplay = 240, 3405 .vsync_start = 240 + 3, 3406 .vsync_end = 240 + 3 + 1, 3407 .vtotal = 240 + 3 + 1 + 17, 3408 .vrefresh = 60, 3409 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3410 }, 3411 }; 3412 3413 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3414 .modes = ti_nspire_cx_lcd_mode, 3415 .num_modes = 1, 3416 .bpc = 8, 3417 .size = { 3418 .width = 65, 3419 .height = 49, 3420 }, 3421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3422 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3423 }; 3424 3425 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3426 { 3427 .clock = 10000, 3428 .hdisplay = 320, 3429 .hsync_start = 320 + 6, 3430 .hsync_end = 320 + 6 + 6, 3431 .htotal = 320 + 6 + 6 + 6, 3432 .vdisplay = 240, 3433 .vsync_start = 240 + 0, 3434 .vsync_end = 240 + 0 + 1, 3435 .vtotal = 240 + 0 + 1 + 0, 3436 .vrefresh = 60, 3437 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3438 }, 3439 }; 3440 3441 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3442 .modes = ti_nspire_classic_lcd_mode, 3443 .num_modes = 1, 3444 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3445 .bpc = 8, 3446 .size = { 3447 .width = 71, 3448 .height = 53, 3449 }, 3450 /* This is the grayscale bus format */ 3451 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3452 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3453 }; 3454 3455 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3456 .clock = 79500, 3457 .hdisplay = 1280, 3458 .hsync_start = 1280 + 192, 3459 .hsync_end = 1280 + 192 + 128, 3460 .htotal = 1280 + 192 + 128 + 64, 3461 .vdisplay = 768, 3462 .vsync_start = 768 + 20, 3463 .vsync_end = 768 + 20 + 7, 3464 .vtotal = 768 + 20 + 7 + 3, 3465 .vrefresh = 60, 3466 }; 3467 3468 static const struct panel_desc toshiba_lt089ac29000 = { 3469 .modes = &toshiba_lt089ac29000_mode, 3470 .num_modes = 1, 3471 .size = { 3472 .width = 194, 3473 .height = 116, 3474 }, 3475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3476 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3478 }; 3479 3480 static const struct drm_display_mode tpk_f07a_0102_mode = { 3481 .clock = 33260, 3482 .hdisplay = 800, 3483 .hsync_start = 800 + 40, 3484 .hsync_end = 800 + 40 + 128, 3485 .htotal = 800 + 40 + 128 + 88, 3486 .vdisplay = 480, 3487 .vsync_start = 480 + 10, 3488 .vsync_end = 480 + 10 + 2, 3489 .vtotal = 480 + 10 + 2 + 33, 3490 .vrefresh = 60, 3491 }; 3492 3493 static const struct panel_desc tpk_f07a_0102 = { 3494 .modes = &tpk_f07a_0102_mode, 3495 .num_modes = 1, 3496 .size = { 3497 .width = 152, 3498 .height = 91, 3499 }, 3500 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3501 }; 3502 3503 static const struct drm_display_mode tpk_f10a_0102_mode = { 3504 .clock = 45000, 3505 .hdisplay = 1024, 3506 .hsync_start = 1024 + 176, 3507 .hsync_end = 1024 + 176 + 5, 3508 .htotal = 1024 + 176 + 5 + 88, 3509 .vdisplay = 600, 3510 .vsync_start = 600 + 20, 3511 .vsync_end = 600 + 20 + 5, 3512 .vtotal = 600 + 20 + 5 + 25, 3513 .vrefresh = 60, 3514 }; 3515 3516 static const struct panel_desc tpk_f10a_0102 = { 3517 .modes = &tpk_f10a_0102_mode, 3518 .num_modes = 1, 3519 .size = { 3520 .width = 223, 3521 .height = 125, 3522 }, 3523 }; 3524 3525 static const struct display_timing urt_umsh_8596md_timing = { 3526 .pixelclock = { 33260000, 33260000, 33260000 }, 3527 .hactive = { 800, 800, 800 }, 3528 .hfront_porch = { 41, 41, 41 }, 3529 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3530 .hsync_len = { 71, 128, 128 }, 3531 .vactive = { 480, 480, 480 }, 3532 .vfront_porch = { 10, 10, 10 }, 3533 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3534 .vsync_len = { 2, 2, 2 }, 3535 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3536 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3537 }; 3538 3539 static const struct panel_desc urt_umsh_8596md_lvds = { 3540 .timings = &urt_umsh_8596md_timing, 3541 .num_timings = 1, 3542 .bpc = 6, 3543 .size = { 3544 .width = 152, 3545 .height = 91, 3546 }, 3547 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3549 }; 3550 3551 static const struct panel_desc urt_umsh_8596md_parallel = { 3552 .timings = &urt_umsh_8596md_timing, 3553 .num_timings = 1, 3554 .bpc = 6, 3555 .size = { 3556 .width = 152, 3557 .height = 91, 3558 }, 3559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3560 }; 3561 3562 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3563 .clock = 33333, 3564 .hdisplay = 800, 3565 .hsync_start = 800 + 210, 3566 .hsync_end = 800 + 210 + 20, 3567 .htotal = 800 + 210 + 20 + 46, 3568 .vdisplay = 480, 3569 .vsync_start = 480 + 22, 3570 .vsync_end = 480 + 22 + 10, 3571 .vtotal = 480 + 22 + 10 + 23, 3572 .vrefresh = 60, 3573 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3574 }; 3575 3576 static const struct panel_desc vl050_8048nt_c01 = { 3577 .modes = &vl050_8048nt_c01_mode, 3578 .num_modes = 1, 3579 .bpc = 8, 3580 .size = { 3581 .width = 120, 3582 .height = 76, 3583 }, 3584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3585 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3586 }; 3587 3588 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3589 .clock = 6410, 3590 .hdisplay = 320, 3591 .hsync_start = 320 + 20, 3592 .hsync_end = 320 + 20 + 30, 3593 .htotal = 320 + 20 + 30 + 38, 3594 .vdisplay = 240, 3595 .vsync_start = 240 + 4, 3596 .vsync_end = 240 + 4 + 3, 3597 .vtotal = 240 + 4 + 3 + 15, 3598 .vrefresh = 60, 3599 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3600 }; 3601 3602 static const struct panel_desc winstar_wf35ltiacd = { 3603 .modes = &winstar_wf35ltiacd_mode, 3604 .num_modes = 1, 3605 .bpc = 8, 3606 .size = { 3607 .width = 70, 3608 .height = 53, 3609 }, 3610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3611 }; 3612 3613 static const struct drm_display_mode arm_rtsm_mode[] = { 3614 { 3615 .clock = 65000, 3616 .hdisplay = 1024, 3617 .hsync_start = 1024 + 24, 3618 .hsync_end = 1024 + 24 + 136, 3619 .htotal = 1024 + 24 + 136 + 160, 3620 .vdisplay = 768, 3621 .vsync_start = 768 + 3, 3622 .vsync_end = 768 + 3 + 6, 3623 .vtotal = 768 + 3 + 6 + 29, 3624 .vrefresh = 60, 3625 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3626 }, 3627 }; 3628 3629 static const struct panel_desc arm_rtsm = { 3630 .modes = arm_rtsm_mode, 3631 .num_modes = 1, 3632 .bpc = 8, 3633 .size = { 3634 .width = 400, 3635 .height = 300, 3636 }, 3637 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3638 }; 3639 3640 static const struct of_device_id platform_of_match[] = { 3641 { 3642 .compatible = "ampire,am-480272h3tmqw-t01h", 3643 .data = &ire_am_480272h3tmqw_t01h, 3644 }, { 3645 .compatible = "ampire,am800480r3tmqwa1h", 3646 .data = &ire_am800480r3tmqwa1h, 3647 }, { 3648 .compatible = "arm,rtsm-display", 3649 .data = &arm_rtsm, 3650 }, { 3651 .compatible = "armadeus,st0700-adapt", 3652 .data = &armadeus_st0700_adapt, 3653 }, { 3654 .compatible = "auo,b101aw03", 3655 .data = &auo_b101aw03, 3656 }, { 3657 .compatible = "auo,b101ean01", 3658 .data = &auo_b101ean01, 3659 }, { 3660 .compatible = "auo,b101xtn01", 3661 .data = &auo_b101xtn01, 3662 }, { 3663 .compatible = "auo,b116xa01", 3664 .data = &auo_b116xak01, 3665 }, { 3666 .compatible = "auo,b116xw03", 3667 .data = &auo_b116xw03, 3668 }, { 3669 .compatible = "auo,b133htn01", 3670 .data = &auo_b133htn01, 3671 }, { 3672 .compatible = "auo,b133xtn01", 3673 .data = &auo_b133xtn01, 3674 }, { 3675 .compatible = "auo,g070vvn01", 3676 .data = &auo_g070vvn01, 3677 }, { 3678 .compatible = "auo,g101evn010", 3679 .data = &auo_g101evn010, 3680 }, { 3681 .compatible = "auo,g104sn02", 3682 .data = &auo_g104sn02, 3683 }, { 3684 .compatible = "auo,g121ean01", 3685 .data = &auo_g121ean01, 3686 }, { 3687 .compatible = "auo,g133han01", 3688 .data = &auo_g133han01, 3689 }, { 3690 .compatible = "auo,g156xtn01", 3691 .data = &auo_g156xtn01, 3692 }, { 3693 .compatible = "auo,g185han01", 3694 .data = &auo_g185han01, 3695 }, { 3696 .compatible = "auo,g190ean01", 3697 .data = &auo_g190ean01, 3698 }, { 3699 .compatible = "auo,p320hvn03", 3700 .data = &auo_p320hvn03, 3701 }, { 3702 .compatible = "auo,t215hvn01", 3703 .data = &auo_t215hvn01, 3704 }, { 3705 .compatible = "avic,tm070ddh03", 3706 .data = &avic_tm070ddh03, 3707 }, { 3708 .compatible = "bananapi,s070wv20-ct16", 3709 .data = &bananapi_s070wv20_ct16, 3710 }, { 3711 .compatible = "boe,hv070wsa-100", 3712 .data = &boe_hv070wsa 3713 }, { 3714 .compatible = "boe,nv101wxmn51", 3715 .data = &boe_nv101wxmn51, 3716 }, { 3717 .compatible = "boe,nv133fhm-n61", 3718 .data = &boe_nv133fhm_n61, 3719 }, { 3720 .compatible = "boe,nv133fhm-n62", 3721 .data = &boe_nv133fhm_n61, 3722 }, { 3723 .compatible = "boe,nv140fhmn49", 3724 .data = &boe_nv140fhmn49, 3725 }, { 3726 .compatible = "cdtech,s043wq26h-ct7", 3727 .data = &cdtech_s043wq26h_ct7, 3728 }, { 3729 .compatible = "cdtech,s070wv95-ct16", 3730 .data = &cdtech_s070wv95_ct16, 3731 }, { 3732 .compatible = "chunghwa,claa070wp03xg", 3733 .data = &chunghwa_claa070wp03xg, 3734 }, { 3735 .compatible = "chunghwa,claa101wa01a", 3736 .data = &chunghwa_claa101wa01a 3737 }, { 3738 .compatible = "chunghwa,claa101wb01", 3739 .data = &chunghwa_claa101wb01 3740 }, { 3741 .compatible = "dataimage,scf0700c48ggu18", 3742 .data = &dataimage_scf0700c48ggu18, 3743 }, { 3744 .compatible = "dlc,dlc0700yzg-1", 3745 .data = &dlc_dlc0700yzg_1, 3746 }, { 3747 .compatible = "dlc,dlc1010gig", 3748 .data = &dlc_dlc1010gig, 3749 }, { 3750 .compatible = "edt,et035012dm6", 3751 .data = &edt_et035012dm6, 3752 }, { 3753 .compatible = "edt,etm043080dh6gp", 3754 .data = &edt_etm043080dh6gp, 3755 }, { 3756 .compatible = "edt,etm0430g0dh6", 3757 .data = &edt_etm0430g0dh6, 3758 }, { 3759 .compatible = "edt,et057090dhu", 3760 .data = &edt_et057090dhu, 3761 }, { 3762 .compatible = "edt,et070080dh6", 3763 .data = &edt_etm0700g0dh6, 3764 }, { 3765 .compatible = "edt,etm0700g0dh6", 3766 .data = &edt_etm0700g0dh6, 3767 }, { 3768 .compatible = "edt,etm0700g0bdh6", 3769 .data = &edt_etm0700g0bdh6, 3770 }, { 3771 .compatible = "edt,etm0700g0edh6", 3772 .data = &edt_etm0700g0bdh6, 3773 }, { 3774 .compatible = "evervision,vgg804821", 3775 .data = &evervision_vgg804821, 3776 }, { 3777 .compatible = "foxlink,fl500wvr00-a0t", 3778 .data = &foxlink_fl500wvr00_a0t, 3779 }, { 3780 .compatible = "frida,frd350h54004", 3781 .data = &frida_frd350h54004, 3782 }, { 3783 .compatible = "friendlyarm,hd702e", 3784 .data = &friendlyarm_hd702e, 3785 }, { 3786 .compatible = "giantplus,gpg482739qs5", 3787 .data = &giantplus_gpg482739qs5 3788 }, { 3789 .compatible = "giantplus,gpm940b0", 3790 .data = &giantplus_gpm940b0, 3791 }, { 3792 .compatible = "hannstar,hsd070pww1", 3793 .data = &hannstar_hsd070pww1, 3794 }, { 3795 .compatible = "hannstar,hsd100pxn1", 3796 .data = &hannstar_hsd100pxn1, 3797 }, { 3798 .compatible = "hit,tx23d38vm0caa", 3799 .data = &hitachi_tx23d38vm0caa 3800 }, { 3801 .compatible = "innolux,at043tn24", 3802 .data = &innolux_at043tn24, 3803 }, { 3804 .compatible = "innolux,at070tn92", 3805 .data = &innolux_at070tn92, 3806 }, { 3807 .compatible = "innolux,g070y2-l01", 3808 .data = &innolux_g070y2_l01, 3809 }, { 3810 .compatible = "innolux,g101ice-l01", 3811 .data = &innolux_g101ice_l01 3812 }, { 3813 .compatible = "innolux,g121i1-l01", 3814 .data = &innolux_g121i1_l01 3815 }, { 3816 .compatible = "innolux,g121x1-l03", 3817 .data = &innolux_g121x1_l03, 3818 }, { 3819 .compatible = "innolux,n116bge", 3820 .data = &innolux_n116bge, 3821 }, { 3822 .compatible = "innolux,n156bge-l21", 3823 .data = &innolux_n156bge_l21, 3824 }, { 3825 .compatible = "innolux,p120zdg-bf1", 3826 .data = &innolux_p120zdg_bf1, 3827 }, { 3828 .compatible = "innolux,zj070na-01p", 3829 .data = &innolux_zj070na_01p, 3830 }, { 3831 .compatible = "ivo,m133nwf4-r0", 3832 .data = &ivo_m133nwf4_r0, 3833 }, { 3834 .compatible = "koe,tx14d24vm1bpa", 3835 .data = &koe_tx14d24vm1bpa, 3836 }, { 3837 .compatible = "koe,tx31d200vm0baa", 3838 .data = &koe_tx31d200vm0baa, 3839 }, { 3840 .compatible = "kyo,tcg121xglp", 3841 .data = &kyo_tcg121xglp, 3842 }, { 3843 .compatible = "lemaker,bl035-rgb-002", 3844 .data = &lemaker_bl035_rgb_002, 3845 }, { 3846 .compatible = "lg,lb070wv8", 3847 .data = &lg_lb070wv8, 3848 }, { 3849 .compatible = "lg,lp079qx1-sp0v", 3850 .data = &lg_lp079qx1_sp0v, 3851 }, { 3852 .compatible = "lg,lp097qx1-spa1", 3853 .data = &lg_lp097qx1_spa1, 3854 }, { 3855 .compatible = "lg,lp120up1", 3856 .data = &lg_lp120up1, 3857 }, { 3858 .compatible = "lg,lp129qe", 3859 .data = &lg_lp129qe, 3860 }, { 3861 .compatible = "logicpd,type28", 3862 .data = &logicpd_type_28, 3863 }, { 3864 .compatible = "logictechno,lt161010-2nhc", 3865 .data = &logictechno_lt161010_2nh, 3866 }, { 3867 .compatible = "logictechno,lt161010-2nhr", 3868 .data = &logictechno_lt161010_2nh, 3869 }, { 3870 .compatible = "logictechno,lt170410-2whc", 3871 .data = &logictechno_lt170410_2whc, 3872 }, { 3873 .compatible = "mitsubishi,aa070mc01-ca1", 3874 .data = &mitsubishi_aa070mc01, 3875 }, { 3876 .compatible = "nec,nl12880bc20-05", 3877 .data = &nec_nl12880bc20_05, 3878 }, { 3879 .compatible = "nec,nl4827hc19-05b", 3880 .data = &nec_nl4827hc19_05b, 3881 }, { 3882 .compatible = "netron-dy,e231732", 3883 .data = &netron_dy_e231732, 3884 }, { 3885 .compatible = "neweast,wjfh116008a", 3886 .data = &neweast_wjfh116008a, 3887 }, { 3888 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3889 .data = &newhaven_nhd_43_480272ef_atxl, 3890 }, { 3891 .compatible = "nlt,nl192108ac18-02d", 3892 .data = &nlt_nl192108ac18_02d, 3893 }, { 3894 .compatible = "nvd,9128", 3895 .data = &nvd_9128, 3896 }, { 3897 .compatible = "okaya,rs800480t-7x0gp", 3898 .data = &okaya_rs800480t_7x0gp, 3899 }, { 3900 .compatible = "olimex,lcd-olinuxino-43-ts", 3901 .data = &olimex_lcd_olinuxino_43ts, 3902 }, { 3903 .compatible = "ontat,yx700wv03", 3904 .data = &ontat_yx700wv03, 3905 }, { 3906 .compatible = "ortustech,com37h3m05dtc", 3907 .data = &ortustech_com37h3m, 3908 }, { 3909 .compatible = "ortustech,com37h3m99dtc", 3910 .data = &ortustech_com37h3m, 3911 }, { 3912 .compatible = "ortustech,com43h4m85ulc", 3913 .data = &ortustech_com43h4m85ulc, 3914 }, { 3915 .compatible = "osddisplays,osd070t1718-19ts", 3916 .data = &osddisplays_osd070t1718_19ts, 3917 }, { 3918 .compatible = "pda,91-00156-a0", 3919 .data = &pda_91_00156_a0, 3920 }, { 3921 .compatible = "qiaodian,qd43003c0-40", 3922 .data = &qd43003c0_40, 3923 }, { 3924 .compatible = "rocktech,rk070er9427", 3925 .data = &rocktech_rk070er9427, 3926 }, { 3927 .compatible = "rocktech,rk101ii01d-ct", 3928 .data = &rocktech_rk101ii01d_ct, 3929 }, { 3930 .compatible = "samsung,lsn122dl01-c01", 3931 .data = &samsung_lsn122dl01_c01, 3932 }, { 3933 .compatible = "samsung,ltn101nt05", 3934 .data = &samsung_ltn101nt05, 3935 }, { 3936 .compatible = "samsung,ltn140at29-301", 3937 .data = &samsung_ltn140at29_301, 3938 }, { 3939 .compatible = "satoz,sat050at40h12r2", 3940 .data = &satoz_sat050at40h12r2, 3941 }, { 3942 .compatible = "sharp,ld-d5116z01b", 3943 .data = &sharp_ld_d5116z01b, 3944 }, { 3945 .compatible = "sharp,lq035q7db03", 3946 .data = &sharp_lq035q7db03, 3947 }, { 3948 .compatible = "sharp,lq070y3dg3b", 3949 .data = &sharp_lq070y3dg3b, 3950 }, { 3951 .compatible = "sharp,lq101k1ly04", 3952 .data = &sharp_lq101k1ly04, 3953 }, { 3954 .compatible = "sharp,lq123p1jx31", 3955 .data = &sharp_lq123p1jx31, 3956 }, { 3957 .compatible = "sharp,ls020b1dd01d", 3958 .data = &sharp_ls020b1dd01d, 3959 }, { 3960 .compatible = "shelly,sca07010-bfn-lnn", 3961 .data = &shelly_sca07010_bfn_lnn, 3962 }, { 3963 .compatible = "starry,kr070pe2t", 3964 .data = &starry_kr070pe2t, 3965 }, { 3966 .compatible = "starry,kr122ea0sra", 3967 .data = &starry_kr122ea0sra, 3968 }, { 3969 .compatible = "tfc,s9700rtwv43tr-01b", 3970 .data = &tfc_s9700rtwv43tr_01b, 3971 }, { 3972 .compatible = "tianma,tm070jdhg30", 3973 .data = &tianma_tm070jdhg30, 3974 }, { 3975 .compatible = "tianma,tm070rvhg71", 3976 .data = &tianma_tm070rvhg71, 3977 }, { 3978 .compatible = "ti,nspire-cx-lcd-panel", 3979 .data = &ti_nspire_cx_lcd_panel, 3980 }, { 3981 .compatible = "ti,nspire-classic-lcd-panel", 3982 .data = &ti_nspire_classic_lcd_panel, 3983 }, { 3984 .compatible = "toshiba,lt089ac29000", 3985 .data = &toshiba_lt089ac29000, 3986 }, { 3987 .compatible = "tpk,f07a-0102", 3988 .data = &tpk_f07a_0102, 3989 }, { 3990 .compatible = "tpk,f10a-0102", 3991 .data = &tpk_f10a_0102, 3992 }, { 3993 .compatible = "urt,umsh-8596md-t", 3994 .data = &urt_umsh_8596md_parallel, 3995 }, { 3996 .compatible = "urt,umsh-8596md-1t", 3997 .data = &urt_umsh_8596md_parallel, 3998 }, { 3999 .compatible = "urt,umsh-8596md-7t", 4000 .data = &urt_umsh_8596md_parallel, 4001 }, { 4002 .compatible = "urt,umsh-8596md-11t", 4003 .data = &urt_umsh_8596md_lvds, 4004 }, { 4005 .compatible = "urt,umsh-8596md-19t", 4006 .data = &urt_umsh_8596md_lvds, 4007 }, { 4008 .compatible = "urt,umsh-8596md-20t", 4009 .data = &urt_umsh_8596md_parallel, 4010 }, { 4011 .compatible = "vxt,vl050-8048nt-c01", 4012 .data = &vl050_8048nt_c01, 4013 }, { 4014 .compatible = "winstar,wf35ltiacd", 4015 .data = &winstar_wf35ltiacd, 4016 }, { 4017 /* Must be the last entry */ 4018 .compatible = "panel-dpi", 4019 .data = &panel_dpi, 4020 }, { 4021 /* sentinel */ 4022 } 4023 }; 4024 MODULE_DEVICE_TABLE(of, platform_of_match); 4025 4026 static int panel_simple_platform_probe(struct platform_device *pdev) 4027 { 4028 const struct of_device_id *id; 4029 4030 id = of_match_node(platform_of_match, pdev->dev.of_node); 4031 if (!id) 4032 return -ENODEV; 4033 4034 return panel_simple_probe(&pdev->dev, id->data); 4035 } 4036 4037 static int panel_simple_platform_remove(struct platform_device *pdev) 4038 { 4039 return panel_simple_remove(&pdev->dev); 4040 } 4041 4042 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4043 { 4044 panel_simple_shutdown(&pdev->dev); 4045 } 4046 4047 static struct platform_driver panel_simple_platform_driver = { 4048 .driver = { 4049 .name = "panel-simple", 4050 .of_match_table = platform_of_match, 4051 }, 4052 .probe = panel_simple_platform_probe, 4053 .remove = panel_simple_platform_remove, 4054 .shutdown = panel_simple_platform_shutdown, 4055 }; 4056 4057 struct panel_desc_dsi { 4058 struct panel_desc desc; 4059 4060 unsigned long flags; 4061 enum mipi_dsi_pixel_format format; 4062 unsigned int lanes; 4063 }; 4064 4065 static const struct drm_display_mode auo_b080uan01_mode = { 4066 .clock = 154500, 4067 .hdisplay = 1200, 4068 .hsync_start = 1200 + 62, 4069 .hsync_end = 1200 + 62 + 4, 4070 .htotal = 1200 + 62 + 4 + 62, 4071 .vdisplay = 1920, 4072 .vsync_start = 1920 + 9, 4073 .vsync_end = 1920 + 9 + 2, 4074 .vtotal = 1920 + 9 + 2 + 8, 4075 .vrefresh = 60, 4076 }; 4077 4078 static const struct panel_desc_dsi auo_b080uan01 = { 4079 .desc = { 4080 .modes = &auo_b080uan01_mode, 4081 .num_modes = 1, 4082 .bpc = 8, 4083 .size = { 4084 .width = 108, 4085 .height = 272, 4086 }, 4087 }, 4088 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4089 .format = MIPI_DSI_FMT_RGB888, 4090 .lanes = 4, 4091 }; 4092 4093 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4094 .clock = 160000, 4095 .hdisplay = 1200, 4096 .hsync_start = 1200 + 120, 4097 .hsync_end = 1200 + 120 + 20, 4098 .htotal = 1200 + 120 + 20 + 21, 4099 .vdisplay = 1920, 4100 .vsync_start = 1920 + 21, 4101 .vsync_end = 1920 + 21 + 3, 4102 .vtotal = 1920 + 21 + 3 + 18, 4103 .vrefresh = 60, 4104 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4105 }; 4106 4107 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4108 .desc = { 4109 .modes = &boe_tv080wum_nl0_mode, 4110 .num_modes = 1, 4111 .size = { 4112 .width = 107, 4113 .height = 172, 4114 }, 4115 }, 4116 .flags = MIPI_DSI_MODE_VIDEO | 4117 MIPI_DSI_MODE_VIDEO_BURST | 4118 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4119 .format = MIPI_DSI_FMT_RGB888, 4120 .lanes = 4, 4121 }; 4122 4123 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4124 .clock = 71000, 4125 .hdisplay = 800, 4126 .hsync_start = 800 + 32, 4127 .hsync_end = 800 + 32 + 1, 4128 .htotal = 800 + 32 + 1 + 57, 4129 .vdisplay = 1280, 4130 .vsync_start = 1280 + 28, 4131 .vsync_end = 1280 + 28 + 1, 4132 .vtotal = 1280 + 28 + 1 + 14, 4133 .vrefresh = 60, 4134 }; 4135 4136 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4137 .desc = { 4138 .modes = &lg_ld070wx3_sl01_mode, 4139 .num_modes = 1, 4140 .bpc = 8, 4141 .size = { 4142 .width = 94, 4143 .height = 151, 4144 }, 4145 }, 4146 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4147 .format = MIPI_DSI_FMT_RGB888, 4148 .lanes = 4, 4149 }; 4150 4151 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4152 .clock = 67000, 4153 .hdisplay = 720, 4154 .hsync_start = 720 + 12, 4155 .hsync_end = 720 + 12 + 4, 4156 .htotal = 720 + 12 + 4 + 112, 4157 .vdisplay = 1280, 4158 .vsync_start = 1280 + 8, 4159 .vsync_end = 1280 + 8 + 4, 4160 .vtotal = 1280 + 8 + 4 + 12, 4161 .vrefresh = 60, 4162 }; 4163 4164 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4165 .desc = { 4166 .modes = &lg_lh500wx1_sd03_mode, 4167 .num_modes = 1, 4168 .bpc = 8, 4169 .size = { 4170 .width = 62, 4171 .height = 110, 4172 }, 4173 }, 4174 .flags = MIPI_DSI_MODE_VIDEO, 4175 .format = MIPI_DSI_FMT_RGB888, 4176 .lanes = 4, 4177 }; 4178 4179 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4180 .clock = 157200, 4181 .hdisplay = 1920, 4182 .hsync_start = 1920 + 154, 4183 .hsync_end = 1920 + 154 + 16, 4184 .htotal = 1920 + 154 + 16 + 32, 4185 .vdisplay = 1200, 4186 .vsync_start = 1200 + 17, 4187 .vsync_end = 1200 + 17 + 2, 4188 .vtotal = 1200 + 17 + 2 + 16, 4189 .vrefresh = 60, 4190 }; 4191 4192 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4193 .desc = { 4194 .modes = &panasonic_vvx10f004b00_mode, 4195 .num_modes = 1, 4196 .bpc = 8, 4197 .size = { 4198 .width = 217, 4199 .height = 136, 4200 }, 4201 }, 4202 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4203 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4204 .format = MIPI_DSI_FMT_RGB888, 4205 .lanes = 4, 4206 }; 4207 4208 static const struct drm_display_mode lg_acx467akm_7_mode = { 4209 .clock = 150000, 4210 .hdisplay = 1080, 4211 .hsync_start = 1080 + 2, 4212 .hsync_end = 1080 + 2 + 2, 4213 .htotal = 1080 + 2 + 2 + 2, 4214 .vdisplay = 1920, 4215 .vsync_start = 1920 + 2, 4216 .vsync_end = 1920 + 2 + 2, 4217 .vtotal = 1920 + 2 + 2 + 2, 4218 .vrefresh = 60, 4219 }; 4220 4221 static const struct panel_desc_dsi lg_acx467akm_7 = { 4222 .desc = { 4223 .modes = &lg_acx467akm_7_mode, 4224 .num_modes = 1, 4225 .bpc = 8, 4226 .size = { 4227 .width = 62, 4228 .height = 110, 4229 }, 4230 }, 4231 .flags = 0, 4232 .format = MIPI_DSI_FMT_RGB888, 4233 .lanes = 4, 4234 }; 4235 4236 static const struct drm_display_mode osd101t2045_53ts_mode = { 4237 .clock = 154500, 4238 .hdisplay = 1920, 4239 .hsync_start = 1920 + 112, 4240 .hsync_end = 1920 + 112 + 16, 4241 .htotal = 1920 + 112 + 16 + 32, 4242 .vdisplay = 1200, 4243 .vsync_start = 1200 + 16, 4244 .vsync_end = 1200 + 16 + 2, 4245 .vtotal = 1200 + 16 + 2 + 16, 4246 .vrefresh = 60, 4247 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4248 }; 4249 4250 static const struct panel_desc_dsi osd101t2045_53ts = { 4251 .desc = { 4252 .modes = &osd101t2045_53ts_mode, 4253 .num_modes = 1, 4254 .bpc = 8, 4255 .size = { 4256 .width = 217, 4257 .height = 136, 4258 }, 4259 }, 4260 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4261 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4262 MIPI_DSI_MODE_EOT_PACKET, 4263 .format = MIPI_DSI_FMT_RGB888, 4264 .lanes = 4, 4265 }; 4266 4267 static const struct of_device_id dsi_of_match[] = { 4268 { 4269 .compatible = "auo,b080uan01", 4270 .data = &auo_b080uan01 4271 }, { 4272 .compatible = "boe,tv080wum-nl0", 4273 .data = &boe_tv080wum_nl0 4274 }, { 4275 .compatible = "lg,ld070wx3-sl01", 4276 .data = &lg_ld070wx3_sl01 4277 }, { 4278 .compatible = "lg,lh500wx1-sd03", 4279 .data = &lg_lh500wx1_sd03 4280 }, { 4281 .compatible = "panasonic,vvx10f004b00", 4282 .data = &panasonic_vvx10f004b00 4283 }, { 4284 .compatible = "lg,acx467akm-7", 4285 .data = &lg_acx467akm_7 4286 }, { 4287 .compatible = "osddisplays,osd101t2045-53ts", 4288 .data = &osd101t2045_53ts 4289 }, { 4290 /* sentinel */ 4291 } 4292 }; 4293 MODULE_DEVICE_TABLE(of, dsi_of_match); 4294 4295 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4296 { 4297 const struct panel_desc_dsi *desc; 4298 const struct of_device_id *id; 4299 int err; 4300 4301 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4302 if (!id) 4303 return -ENODEV; 4304 4305 desc = id->data; 4306 4307 err = panel_simple_probe(&dsi->dev, &desc->desc); 4308 if (err < 0) 4309 return err; 4310 4311 dsi->mode_flags = desc->flags; 4312 dsi->format = desc->format; 4313 dsi->lanes = desc->lanes; 4314 4315 err = mipi_dsi_attach(dsi); 4316 if (err) { 4317 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4318 4319 drm_panel_remove(&panel->base); 4320 } 4321 4322 return err; 4323 } 4324 4325 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4326 { 4327 int err; 4328 4329 err = mipi_dsi_detach(dsi); 4330 if (err < 0) 4331 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4332 4333 return panel_simple_remove(&dsi->dev); 4334 } 4335 4336 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4337 { 4338 panel_simple_shutdown(&dsi->dev); 4339 } 4340 4341 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4342 .driver = { 4343 .name = "panel-simple-dsi", 4344 .of_match_table = dsi_of_match, 4345 }, 4346 .probe = panel_simple_dsi_probe, 4347 .remove = panel_simple_dsi_remove, 4348 .shutdown = panel_simple_dsi_shutdown, 4349 }; 4350 4351 static int __init panel_simple_init(void) 4352 { 4353 int err; 4354 4355 err = platform_driver_register(&panel_simple_platform_driver); 4356 if (err < 0) 4357 return err; 4358 4359 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4360 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4361 if (err < 0) 4362 return err; 4363 } 4364 4365 return 0; 4366 } 4367 module_init(panel_simple_init); 4368 4369 static void __exit panel_simple_exit(void) 4370 { 4371 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4372 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4373 4374 platform_driver_unregister(&panel_simple_platform_driver); 4375 } 4376 module_exit(panel_simple_exit); 4377 4378 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4379 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4380 MODULE_LICENSE("GPL and additional rights"); 4381