1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, m->vrefresh); 167 continue; 168 } 169 170 mode->type |= DRM_MODE_TYPE_DRIVER; 171 172 if (panel->desc->num_modes == 1) 173 mode->type |= DRM_MODE_TYPE_PREFERRED; 174 175 drm_mode_set_name(mode); 176 177 drm_mode_probed_add(connector, mode); 178 num++; 179 } 180 181 return num; 182 } 183 184 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 185 struct drm_connector *connector) 186 { 187 struct drm_display_mode *mode; 188 bool has_override = panel->override_mode.type; 189 unsigned int num = 0; 190 191 if (!panel->desc) 192 return 0; 193 194 if (has_override) { 195 mode = drm_mode_duplicate(connector->dev, 196 &panel->override_mode); 197 if (mode) { 198 drm_mode_probed_add(connector, mode); 199 num = 1; 200 } else { 201 dev_err(panel->base.dev, "failed to add override mode\n"); 202 } 203 } 204 205 /* Only add timings if override was not there or failed to validate */ 206 if (num == 0 && panel->desc->num_timings) 207 num = panel_simple_get_timings_modes(panel, connector); 208 209 /* 210 * Only add fixed modes if timings/override added no mode. 211 * 212 * We should only ever have either the display timings specified 213 * or a fixed mode. Anything else is rather bogus. 214 */ 215 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 216 if (num == 0) 217 num = panel_simple_get_display_modes(panel, connector); 218 219 connector->display_info.bpc = panel->desc->bpc; 220 connector->display_info.width_mm = panel->desc->size.width; 221 connector->display_info.height_mm = panel->desc->size.height; 222 if (panel->desc->bus_format) 223 drm_display_info_set_bus_formats(&connector->display_info, 224 &panel->desc->bus_format, 1); 225 connector->display_info.bus_flags = panel->desc->bus_flags; 226 227 return num; 228 } 229 230 static int panel_simple_disable(struct drm_panel *panel) 231 { 232 struct panel_simple *p = to_panel_simple(panel); 233 234 if (!p->enabled) 235 return 0; 236 237 if (p->desc->delay.disable) 238 msleep(p->desc->delay.disable); 239 240 p->enabled = false; 241 242 return 0; 243 } 244 245 static int panel_simple_unprepare(struct drm_panel *panel) 246 { 247 struct panel_simple *p = to_panel_simple(panel); 248 249 if (!p->prepared) 250 return 0; 251 252 gpiod_set_value_cansleep(p->enable_gpio, 0); 253 254 regulator_disable(p->supply); 255 256 if (p->desc->delay.unprepare) 257 msleep(p->desc->delay.unprepare); 258 259 p->prepared = false; 260 261 return 0; 262 } 263 264 static int panel_simple_get_hpd_gpio(struct device *dev, 265 struct panel_simple *p, bool from_probe) 266 { 267 int err; 268 269 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 270 if (IS_ERR(p->hpd_gpio)) { 271 err = PTR_ERR(p->hpd_gpio); 272 273 /* 274 * If we're called from probe we won't consider '-EPROBE_DEFER' 275 * to be an error--we'll leave the error code in "hpd_gpio". 276 * When we try to use it we'll try again. This allows for 277 * circular dependencies where the component providing the 278 * hpd gpio needs the panel to init before probing. 279 */ 280 if (err != -EPROBE_DEFER || !from_probe) { 281 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 282 return err; 283 } 284 } 285 286 return 0; 287 } 288 289 static int panel_simple_prepare(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 unsigned int delay; 293 int err; 294 int hpd_asserted; 295 296 if (p->prepared) 297 return 0; 298 299 err = regulator_enable(p->supply); 300 if (err < 0) { 301 dev_err(panel->dev, "failed to enable supply: %d\n", err); 302 return err; 303 } 304 305 gpiod_set_value_cansleep(p->enable_gpio, 1); 306 307 delay = p->desc->delay.prepare; 308 if (p->no_hpd) 309 delay += p->desc->delay.hpd_absent_delay; 310 if (delay) 311 msleep(delay); 312 313 if (p->hpd_gpio) { 314 if (IS_ERR(p->hpd_gpio)) { 315 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 316 if (err) 317 return err; 318 } 319 320 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 321 hpd_asserted, hpd_asserted, 322 1000, 2000000); 323 if (hpd_asserted < 0) 324 err = hpd_asserted; 325 326 if (err) { 327 dev_err(panel->dev, 328 "error waiting for hpd GPIO: %d\n", err); 329 return err; 330 } 331 } 332 333 p->prepared = true; 334 335 return 0; 336 } 337 338 static int panel_simple_enable(struct drm_panel *panel) 339 { 340 struct panel_simple *p = to_panel_simple(panel); 341 342 if (p->enabled) 343 return 0; 344 345 if (p->desc->delay.enable) 346 msleep(p->desc->delay.enable); 347 348 p->enabled = true; 349 350 return 0; 351 } 352 353 static int panel_simple_get_modes(struct drm_panel *panel, 354 struct drm_connector *connector) 355 { 356 struct panel_simple *p = to_panel_simple(panel); 357 int num = 0; 358 359 /* probe EDID if a DDC bus is available */ 360 if (p->ddc) { 361 struct edid *edid = drm_get_edid(connector, p->ddc); 362 363 drm_connector_update_edid_property(connector, edid); 364 if (edid) { 365 num += drm_add_edid_modes(connector, edid); 366 kfree(edid); 367 } 368 } 369 370 /* add hard-coded panel modes */ 371 num += panel_simple_get_non_edid_modes(p, connector); 372 373 return num; 374 } 375 376 static int panel_simple_get_timings(struct drm_panel *panel, 377 unsigned int num_timings, 378 struct display_timing *timings) 379 { 380 struct panel_simple *p = to_panel_simple(panel); 381 unsigned int i; 382 383 if (p->desc->num_timings < num_timings) 384 num_timings = p->desc->num_timings; 385 386 if (timings) 387 for (i = 0; i < num_timings; i++) 388 timings[i] = p->desc->timings[i]; 389 390 return p->desc->num_timings; 391 } 392 393 static const struct drm_panel_funcs panel_simple_funcs = { 394 .disable = panel_simple_disable, 395 .unprepare = panel_simple_unprepare, 396 .prepare = panel_simple_prepare, 397 .enable = panel_simple_enable, 398 .get_modes = panel_simple_get_modes, 399 .get_timings = panel_simple_get_timings, 400 }; 401 402 static struct panel_desc panel_dpi; 403 404 static int panel_dpi_probe(struct device *dev, 405 struct panel_simple *panel) 406 { 407 struct display_timing *timing; 408 const struct device_node *np; 409 struct panel_desc *desc; 410 unsigned int bus_flags; 411 struct videomode vm; 412 int ret; 413 414 np = dev->of_node; 415 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 416 if (!desc) 417 return -ENOMEM; 418 419 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 420 if (!timing) 421 return -ENOMEM; 422 423 ret = of_get_display_timing(np, "panel-timing", timing); 424 if (ret < 0) { 425 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 426 np); 427 return ret; 428 } 429 430 desc->timings = timing; 431 desc->num_timings = 1; 432 433 of_property_read_u32(np, "width-mm", &desc->size.width); 434 of_property_read_u32(np, "height-mm", &desc->size.height); 435 436 /* Extract bus_flags from display_timing */ 437 bus_flags = 0; 438 vm.flags = timing->flags; 439 drm_bus_flags_from_videomode(&vm, &bus_flags); 440 desc->bus_flags = bus_flags; 441 442 /* We do not know the connector for the DT node, so guess it */ 443 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 444 445 panel->desc = desc; 446 447 return 0; 448 } 449 450 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 451 (to_check->field.typ >= bounds->field.min && \ 452 to_check->field.typ <= bounds->field.max) 453 static void panel_simple_parse_panel_timing_node(struct device *dev, 454 struct panel_simple *panel, 455 const struct display_timing *ot) 456 { 457 const struct panel_desc *desc = panel->desc; 458 struct videomode vm; 459 unsigned int i; 460 461 if (WARN_ON(desc->num_modes)) { 462 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 463 return; 464 } 465 if (WARN_ON(!desc->num_timings)) { 466 dev_err(dev, "Reject override mode: no timings specified\n"); 467 return; 468 } 469 470 for (i = 0; i < panel->desc->num_timings; i++) { 471 const struct display_timing *dt = &panel->desc->timings[i]; 472 473 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 474 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 481 continue; 482 483 if (ot->flags != dt->flags) 484 continue; 485 486 videomode_from_timing(ot, &vm); 487 drm_display_mode_from_videomode(&vm, &panel->override_mode); 488 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 489 DRM_MODE_TYPE_PREFERRED; 490 break; 491 } 492 493 if (WARN_ON(!panel->override_mode.type)) 494 dev_err(dev, "Reject override mode: No display_timing found\n"); 495 } 496 497 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 498 { 499 struct panel_simple *panel; 500 struct display_timing dt; 501 struct device_node *ddc; 502 int err; 503 504 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 505 if (!panel) 506 return -ENOMEM; 507 508 panel->enabled = false; 509 panel->prepared = false; 510 panel->desc = desc; 511 512 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 513 if (!panel->no_hpd) { 514 err = panel_simple_get_hpd_gpio(dev, panel, true); 515 if (err) 516 return err; 517 } 518 519 panel->supply = devm_regulator_get(dev, "power"); 520 if (IS_ERR(panel->supply)) 521 return PTR_ERR(panel->supply); 522 523 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 524 GPIOD_OUT_LOW); 525 if (IS_ERR(panel->enable_gpio)) { 526 err = PTR_ERR(panel->enable_gpio); 527 if (err != -EPROBE_DEFER) 528 dev_err(dev, "failed to request GPIO: %d\n", err); 529 return err; 530 } 531 532 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 533 if (ddc) { 534 panel->ddc = of_find_i2c_adapter_by_node(ddc); 535 of_node_put(ddc); 536 537 if (!panel->ddc) 538 return -EPROBE_DEFER; 539 } 540 541 if (desc == &panel_dpi) { 542 /* Handle the generic panel-dpi binding */ 543 err = panel_dpi_probe(dev, panel); 544 if (err) 545 goto free_ddc; 546 } else { 547 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 548 panel_simple_parse_panel_timing_node(dev, panel, &dt); 549 } 550 551 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 552 desc->connector_type); 553 554 err = drm_panel_of_backlight(&panel->base); 555 if (err) 556 goto free_ddc; 557 558 err = drm_panel_add(&panel->base); 559 if (err < 0) 560 goto free_ddc; 561 562 dev_set_drvdata(dev, panel); 563 564 return 0; 565 566 free_ddc: 567 if (panel->ddc) 568 put_device(&panel->ddc->dev); 569 570 return err; 571 } 572 573 static int panel_simple_remove(struct device *dev) 574 { 575 struct panel_simple *panel = dev_get_drvdata(dev); 576 577 drm_panel_remove(&panel->base); 578 drm_panel_disable(&panel->base); 579 drm_panel_unprepare(&panel->base); 580 581 if (panel->ddc) 582 put_device(&panel->ddc->dev); 583 584 return 0; 585 } 586 587 static void panel_simple_shutdown(struct device *dev) 588 { 589 struct panel_simple *panel = dev_get_drvdata(dev); 590 591 drm_panel_disable(&panel->base); 592 drm_panel_unprepare(&panel->base); 593 } 594 595 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 596 .clock = 9000, 597 .hdisplay = 480, 598 .hsync_start = 480 + 2, 599 .hsync_end = 480 + 2 + 41, 600 .htotal = 480 + 2 + 41 + 2, 601 .vdisplay = 272, 602 .vsync_start = 272 + 2, 603 .vsync_end = 272 + 2 + 10, 604 .vtotal = 272 + 2 + 10 + 2, 605 .vrefresh = 60, 606 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 607 }; 608 609 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 610 .modes = &ire_am_480272h3tmqw_t01h_mode, 611 .num_modes = 1, 612 .bpc = 8, 613 .size = { 614 .width = 105, 615 .height = 67, 616 }, 617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 618 }; 619 620 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 621 .clock = 33333, 622 .hdisplay = 800, 623 .hsync_start = 800 + 0, 624 .hsync_end = 800 + 0 + 255, 625 .htotal = 800 + 0 + 255 + 0, 626 .vdisplay = 480, 627 .vsync_start = 480 + 2, 628 .vsync_end = 480 + 2 + 45, 629 .vtotal = 480 + 2 + 45 + 0, 630 .vrefresh = 60, 631 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 632 }; 633 634 static const struct panel_desc ampire_am800480r3tmqwa1h = { 635 .modes = &ire_am800480r3tmqwa1h_mode, 636 .num_modes = 1, 637 .bpc = 6, 638 .size = { 639 .width = 152, 640 .height = 91, 641 }, 642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 643 }; 644 645 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 646 .pixelclock = { 26400000, 33300000, 46800000 }, 647 .hactive = { 800, 800, 800 }, 648 .hfront_porch = { 16, 210, 354 }, 649 .hback_porch = { 45, 36, 6 }, 650 .hsync_len = { 1, 10, 40 }, 651 .vactive = { 480, 480, 480 }, 652 .vfront_porch = { 7, 22, 147 }, 653 .vback_porch = { 22, 13, 3 }, 654 .vsync_len = { 1, 10, 20 }, 655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 656 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 657 }; 658 659 static const struct panel_desc armadeus_st0700_adapt = { 660 .timings = &santek_st0700i5y_rbslw_f_timing, 661 .num_timings = 1, 662 .bpc = 6, 663 .size = { 664 .width = 154, 665 .height = 86, 666 }, 667 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 669 }; 670 671 static const struct drm_display_mode auo_b101aw03_mode = { 672 .clock = 51450, 673 .hdisplay = 1024, 674 .hsync_start = 1024 + 156, 675 .hsync_end = 1024 + 156 + 8, 676 .htotal = 1024 + 156 + 8 + 156, 677 .vdisplay = 600, 678 .vsync_start = 600 + 16, 679 .vsync_end = 600 + 16 + 6, 680 .vtotal = 600 + 16 + 6 + 16, 681 .vrefresh = 60, 682 }; 683 684 static const struct panel_desc auo_b101aw03 = { 685 .modes = &auo_b101aw03_mode, 686 .num_modes = 1, 687 .bpc = 6, 688 .size = { 689 .width = 223, 690 .height = 125, 691 }, 692 }; 693 694 static const struct display_timing auo_b101ean01_timing = { 695 .pixelclock = { 65300000, 72500000, 75000000 }, 696 .hactive = { 1280, 1280, 1280 }, 697 .hfront_porch = { 18, 119, 119 }, 698 .hback_porch = { 21, 21, 21 }, 699 .hsync_len = { 32, 32, 32 }, 700 .vactive = { 800, 800, 800 }, 701 .vfront_porch = { 4, 4, 4 }, 702 .vback_porch = { 8, 8, 8 }, 703 .vsync_len = { 18, 20, 20 }, 704 }; 705 706 static const struct panel_desc auo_b101ean01 = { 707 .timings = &auo_b101ean01_timing, 708 .num_timings = 1, 709 .bpc = 6, 710 .size = { 711 .width = 217, 712 .height = 136, 713 }, 714 }; 715 716 static const struct drm_display_mode auo_b101xtn01_mode = { 717 .clock = 72000, 718 .hdisplay = 1366, 719 .hsync_start = 1366 + 20, 720 .hsync_end = 1366 + 20 + 70, 721 .htotal = 1366 + 20 + 70, 722 .vdisplay = 768, 723 .vsync_start = 768 + 14, 724 .vsync_end = 768 + 14 + 42, 725 .vtotal = 768 + 14 + 42, 726 .vrefresh = 60, 727 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 728 }; 729 730 static const struct panel_desc auo_b101xtn01 = { 731 .modes = &auo_b101xtn01_mode, 732 .num_modes = 1, 733 .bpc = 6, 734 .size = { 735 .width = 223, 736 .height = 125, 737 }, 738 }; 739 740 static const struct drm_display_mode auo_b116xak01_mode = { 741 .clock = 69300, 742 .hdisplay = 1366, 743 .hsync_start = 1366 + 48, 744 .hsync_end = 1366 + 48 + 32, 745 .htotal = 1366 + 48 + 32 + 10, 746 .vdisplay = 768, 747 .vsync_start = 768 + 4, 748 .vsync_end = 768 + 4 + 6, 749 .vtotal = 768 + 4 + 6 + 15, 750 .vrefresh = 60, 751 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 752 }; 753 754 static const struct panel_desc auo_b116xak01 = { 755 .modes = &auo_b116xak01_mode, 756 .num_modes = 1, 757 .bpc = 6, 758 .size = { 759 .width = 256, 760 .height = 144, 761 }, 762 .delay = { 763 .hpd_absent_delay = 200, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 766 .connector_type = DRM_MODE_CONNECTOR_eDP, 767 }; 768 769 static const struct drm_display_mode auo_b116xw03_mode = { 770 .clock = 70589, 771 .hdisplay = 1366, 772 .hsync_start = 1366 + 40, 773 .hsync_end = 1366 + 40 + 40, 774 .htotal = 1366 + 40 + 40 + 32, 775 .vdisplay = 768, 776 .vsync_start = 768 + 10, 777 .vsync_end = 768 + 10 + 12, 778 .vtotal = 768 + 10 + 12 + 6, 779 .vrefresh = 60, 780 }; 781 782 static const struct panel_desc auo_b116xw03 = { 783 .modes = &auo_b116xw03_mode, 784 .num_modes = 1, 785 .bpc = 6, 786 .size = { 787 .width = 256, 788 .height = 144, 789 }, 790 }; 791 792 static const struct drm_display_mode auo_b133xtn01_mode = { 793 .clock = 69500, 794 .hdisplay = 1366, 795 .hsync_start = 1366 + 48, 796 .hsync_end = 1366 + 48 + 32, 797 .htotal = 1366 + 48 + 32 + 20, 798 .vdisplay = 768, 799 .vsync_start = 768 + 3, 800 .vsync_end = 768 + 3 + 6, 801 .vtotal = 768 + 3 + 6 + 13, 802 .vrefresh = 60, 803 }; 804 805 static const struct panel_desc auo_b133xtn01 = { 806 .modes = &auo_b133xtn01_mode, 807 .num_modes = 1, 808 .bpc = 6, 809 .size = { 810 .width = 293, 811 .height = 165, 812 }, 813 }; 814 815 static const struct drm_display_mode auo_b133htn01_mode = { 816 .clock = 150660, 817 .hdisplay = 1920, 818 .hsync_start = 1920 + 172, 819 .hsync_end = 1920 + 172 + 80, 820 .htotal = 1920 + 172 + 80 + 60, 821 .vdisplay = 1080, 822 .vsync_start = 1080 + 25, 823 .vsync_end = 1080 + 25 + 10, 824 .vtotal = 1080 + 25 + 10 + 10, 825 .vrefresh = 60, 826 }; 827 828 static const struct panel_desc auo_b133htn01 = { 829 .modes = &auo_b133htn01_mode, 830 .num_modes = 1, 831 .bpc = 6, 832 .size = { 833 .width = 293, 834 .height = 165, 835 }, 836 .delay = { 837 .prepare = 105, 838 .enable = 20, 839 .unprepare = 50, 840 }, 841 }; 842 843 static const struct display_timing auo_g070vvn01_timings = { 844 .pixelclock = { 33300000, 34209000, 45000000 }, 845 .hactive = { 800, 800, 800 }, 846 .hfront_porch = { 20, 40, 200 }, 847 .hback_porch = { 87, 40, 1 }, 848 .hsync_len = { 1, 48, 87 }, 849 .vactive = { 480, 480, 480 }, 850 .vfront_porch = { 5, 13, 200 }, 851 .vback_porch = { 31, 31, 29 }, 852 .vsync_len = { 1, 1, 3 }, 853 }; 854 855 static const struct panel_desc auo_g070vvn01 = { 856 .timings = &auo_g070vvn01_timings, 857 .num_timings = 1, 858 .bpc = 8, 859 .size = { 860 .width = 152, 861 .height = 91, 862 }, 863 .delay = { 864 .prepare = 200, 865 .enable = 50, 866 .disable = 50, 867 .unprepare = 1000, 868 }, 869 }; 870 871 static const struct drm_display_mode auo_g101evn010_mode = { 872 .clock = 68930, 873 .hdisplay = 1280, 874 .hsync_start = 1280 + 82, 875 .hsync_end = 1280 + 82 + 2, 876 .htotal = 1280 + 82 + 2 + 84, 877 .vdisplay = 800, 878 .vsync_start = 800 + 8, 879 .vsync_end = 800 + 8 + 2, 880 .vtotal = 800 + 8 + 2 + 6, 881 .vrefresh = 60, 882 }; 883 884 static const struct panel_desc auo_g101evn010 = { 885 .modes = &auo_g101evn010_mode, 886 .num_modes = 1, 887 .bpc = 6, 888 .size = { 889 .width = 216, 890 .height = 135, 891 }, 892 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 893 .connector_type = DRM_MODE_CONNECTOR_LVDS, 894 }; 895 896 static const struct drm_display_mode auo_g104sn02_mode = { 897 .clock = 40000, 898 .hdisplay = 800, 899 .hsync_start = 800 + 40, 900 .hsync_end = 800 + 40 + 216, 901 .htotal = 800 + 40 + 216 + 128, 902 .vdisplay = 600, 903 .vsync_start = 600 + 10, 904 .vsync_end = 600 + 10 + 35, 905 .vtotal = 600 + 10 + 35 + 2, 906 .vrefresh = 60, 907 }; 908 909 static const struct panel_desc auo_g104sn02 = { 910 .modes = &auo_g104sn02_mode, 911 .num_modes = 1, 912 .bpc = 8, 913 .size = { 914 .width = 211, 915 .height = 158, 916 }, 917 }; 918 919 static const struct drm_display_mode auo_g121ean01_mode = { 920 .clock = 66700, 921 .hdisplay = 1280, 922 .hsync_start = 1280 + 58, 923 .hsync_end = 1280 + 58 + 8, 924 .htotal = 1280 + 58 + 8 + 70, 925 .vdisplay = 800, 926 .vsync_start = 800 + 6, 927 .vsync_end = 800 + 6 + 4, 928 .vtotal = 800 + 6 + 4 + 10, 929 .vrefresh = 60, 930 }; 931 932 static const struct panel_desc auo_g121ean01 = { 933 .modes = &auo_g121ean01_mode, 934 .num_modes = 1, 935 .bpc = 8, 936 .size = { 937 .width = 261, 938 .height = 163, 939 }, 940 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 941 .connector_type = DRM_MODE_CONNECTOR_LVDS, 942 }; 943 944 static const struct display_timing auo_g133han01_timings = { 945 .pixelclock = { 134000000, 141200000, 149000000 }, 946 .hactive = { 1920, 1920, 1920 }, 947 .hfront_porch = { 39, 58, 77 }, 948 .hback_porch = { 59, 88, 117 }, 949 .hsync_len = { 28, 42, 56 }, 950 .vactive = { 1080, 1080, 1080 }, 951 .vfront_porch = { 3, 8, 11 }, 952 .vback_porch = { 5, 14, 19 }, 953 .vsync_len = { 4, 14, 19 }, 954 }; 955 956 static const struct panel_desc auo_g133han01 = { 957 .timings = &auo_g133han01_timings, 958 .num_timings = 1, 959 .bpc = 8, 960 .size = { 961 .width = 293, 962 .height = 165, 963 }, 964 .delay = { 965 .prepare = 200, 966 .enable = 50, 967 .disable = 50, 968 .unprepare = 1000, 969 }, 970 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 972 }; 973 974 static const struct drm_display_mode auo_g156xtn01_mode = { 975 .clock = 76000, 976 .hdisplay = 1366, 977 .hsync_start = 1366 + 33, 978 .hsync_end = 1366 + 33 + 67, 979 .htotal = 1560, 980 .vdisplay = 768, 981 .vsync_start = 768 + 4, 982 .vsync_end = 768 + 4 + 4, 983 .vtotal = 806, 984 .vrefresh = 60, 985 }; 986 987 static const struct panel_desc auo_g156xtn01 = { 988 .modes = &auo_g156xtn01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 344, 993 .height = 194, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g185han01_timings = { 1000 .pixelclock = { 120000000, 144000000, 175000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 36, 120, 148 }, 1003 .hback_porch = { 24, 88, 108 }, 1004 .hsync_len = { 20, 48, 64 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 6, 10, 40 }, 1007 .vback_porch = { 2, 5, 20 }, 1008 .vsync_len = { 2, 5, 20 }, 1009 }; 1010 1011 static const struct panel_desc auo_g185han01 = { 1012 .timings = &auo_g185han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 409, 1017 .height = 230, 1018 }, 1019 .delay = { 1020 .prepare = 50, 1021 .enable = 200, 1022 .disable = 110, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct display_timing auo_g190ean01_timings = { 1030 .pixelclock = { 90000000, 108000000, 135000000 }, 1031 .hactive = { 1280, 1280, 1280 }, 1032 .hfront_porch = { 126, 184, 1266 }, 1033 .hback_porch = { 84, 122, 844 }, 1034 .hsync_len = { 70, 102, 704 }, 1035 .vactive = { 1024, 1024, 1024 }, 1036 .vfront_porch = { 4, 26, 76 }, 1037 .vback_porch = { 2, 8, 25 }, 1038 .vsync_len = { 2, 8, 25 }, 1039 }; 1040 1041 static const struct panel_desc auo_g190ean01 = { 1042 .timings = &auo_g190ean01_timings, 1043 .num_timings = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 376, 1047 .height = 301, 1048 }, 1049 .delay = { 1050 .prepare = 50, 1051 .enable = 200, 1052 .disable = 110, 1053 .unprepare = 1000, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct display_timing auo_p320hvn03_timings = { 1060 .pixelclock = { 106000000, 148500000, 164000000 }, 1061 .hactive = { 1920, 1920, 1920 }, 1062 .hfront_porch = { 25, 50, 130 }, 1063 .hback_porch = { 25, 50, 130 }, 1064 .hsync_len = { 20, 40, 105 }, 1065 .vactive = { 1080, 1080, 1080 }, 1066 .vfront_porch = { 8, 17, 150 }, 1067 .vback_porch = { 8, 17, 150 }, 1068 .vsync_len = { 4, 11, 100 }, 1069 }; 1070 1071 static const struct panel_desc auo_p320hvn03 = { 1072 .timings = &auo_p320hvn03_timings, 1073 .num_timings = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 698, 1077 .height = 393, 1078 }, 1079 .delay = { 1080 .prepare = 1, 1081 .enable = 450, 1082 .unprepare = 500, 1083 }, 1084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1085 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1086 }; 1087 1088 static const struct drm_display_mode auo_t215hvn01_mode = { 1089 .clock = 148800, 1090 .hdisplay = 1920, 1091 .hsync_start = 1920 + 88, 1092 .hsync_end = 1920 + 88 + 44, 1093 .htotal = 1920 + 88 + 44 + 148, 1094 .vdisplay = 1080, 1095 .vsync_start = 1080 + 4, 1096 .vsync_end = 1080 + 4 + 5, 1097 .vtotal = 1080 + 4 + 5 + 36, 1098 .vrefresh = 60, 1099 }; 1100 1101 static const struct panel_desc auo_t215hvn01 = { 1102 .modes = &auo_t215hvn01_mode, 1103 .num_modes = 1, 1104 .bpc = 8, 1105 .size = { 1106 .width = 430, 1107 .height = 270, 1108 }, 1109 .delay = { 1110 .disable = 5, 1111 .unprepare = 1000, 1112 } 1113 }; 1114 1115 static const struct drm_display_mode avic_tm070ddh03_mode = { 1116 .clock = 51200, 1117 .hdisplay = 1024, 1118 .hsync_start = 1024 + 160, 1119 .hsync_end = 1024 + 160 + 4, 1120 .htotal = 1024 + 160 + 4 + 156, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 17, 1123 .vsync_end = 600 + 17 + 1, 1124 .vtotal = 600 + 17 + 1 + 17, 1125 .vrefresh = 60, 1126 }; 1127 1128 static const struct panel_desc avic_tm070ddh03 = { 1129 .modes = &avic_tm070ddh03_mode, 1130 .num_modes = 1, 1131 .bpc = 8, 1132 .size = { 1133 .width = 154, 1134 .height = 90, 1135 }, 1136 .delay = { 1137 .prepare = 20, 1138 .enable = 200, 1139 .disable = 200, 1140 }, 1141 }; 1142 1143 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1144 .clock = 30000, 1145 .hdisplay = 800, 1146 .hsync_start = 800 + 40, 1147 .hsync_end = 800 + 40 + 48, 1148 .htotal = 800 + 40 + 48 + 40, 1149 .vdisplay = 480, 1150 .vsync_start = 480 + 13, 1151 .vsync_end = 480 + 13 + 3, 1152 .vtotal = 480 + 13 + 3 + 29, 1153 }; 1154 1155 static const struct panel_desc bananapi_s070wv20_ct16 = { 1156 .modes = &bananapi_s070wv20_ct16_mode, 1157 .num_modes = 1, 1158 .bpc = 6, 1159 .size = { 1160 .width = 154, 1161 .height = 86, 1162 }, 1163 }; 1164 1165 static const struct drm_display_mode boe_hv070wsa_mode = { 1166 .clock = 42105, 1167 .hdisplay = 1024, 1168 .hsync_start = 1024 + 30, 1169 .hsync_end = 1024 + 30 + 30, 1170 .htotal = 1024 + 30 + 30 + 30, 1171 .vdisplay = 600, 1172 .vsync_start = 600 + 10, 1173 .vsync_end = 600 + 10 + 10, 1174 .vtotal = 600 + 10 + 10 + 10, 1175 .vrefresh = 60, 1176 }; 1177 1178 static const struct panel_desc boe_hv070wsa = { 1179 .modes = &boe_hv070wsa_mode, 1180 .num_modes = 1, 1181 .size = { 1182 .width = 154, 1183 .height = 90, 1184 }, 1185 }; 1186 1187 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1188 { 1189 .clock = 71900, 1190 .hdisplay = 1280, 1191 .hsync_start = 1280 + 48, 1192 .hsync_end = 1280 + 48 + 32, 1193 .htotal = 1280 + 48 + 32 + 80, 1194 .vdisplay = 800, 1195 .vsync_start = 800 + 3, 1196 .vsync_end = 800 + 3 + 5, 1197 .vtotal = 800 + 3 + 5 + 24, 1198 .vrefresh = 60, 1199 }, 1200 { 1201 .clock = 57500, 1202 .hdisplay = 1280, 1203 .hsync_start = 1280 + 48, 1204 .hsync_end = 1280 + 48 + 32, 1205 .htotal = 1280 + 48 + 32 + 80, 1206 .vdisplay = 800, 1207 .vsync_start = 800 + 3, 1208 .vsync_end = 800 + 3 + 5, 1209 .vtotal = 800 + 3 + 5 + 24, 1210 .vrefresh = 48, 1211 }, 1212 }; 1213 1214 static const struct panel_desc boe_nv101wxmn51 = { 1215 .modes = boe_nv101wxmn51_modes, 1216 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1217 .bpc = 8, 1218 .size = { 1219 .width = 217, 1220 .height = 136, 1221 }, 1222 .delay = { 1223 .prepare = 210, 1224 .enable = 50, 1225 .unprepare = 160, 1226 }, 1227 }; 1228 1229 /* Also used for boe_nv133fhm_n62 */ 1230 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1231 .clock = 147840, 1232 .hdisplay = 1920, 1233 .hsync_start = 1920 + 48, 1234 .hsync_end = 1920 + 48 + 32, 1235 .htotal = 1920 + 48 + 32 + 200, 1236 .vdisplay = 1080, 1237 .vsync_start = 1080 + 3, 1238 .vsync_end = 1080 + 3 + 6, 1239 .vtotal = 1080 + 3 + 6 + 31, 1240 .vrefresh = 60, 1241 }; 1242 1243 /* Also used for boe_nv133fhm_n62 */ 1244 static const struct panel_desc boe_nv133fhm_n61 = { 1245 .modes = &boe_nv133fhm_n61_modes, 1246 .num_modes = 1, 1247 .bpc = 6, 1248 .size = { 1249 .width = 294, 1250 .height = 165, 1251 }, 1252 .delay = { 1253 /* 1254 * When power is first given to the panel there's a short 1255 * spike on the HPD line. It was explained that this spike 1256 * was until the TCON data download was complete. On 1257 * one system this was measured at 8 ms. We'll put 15 ms 1258 * in the prepare delay just to be safe and take it away 1259 * from the hpd_absent_delay (which would otherwise be 200 ms) 1260 * to handle this. That means: 1261 * - If HPD isn't hooked up you still have 200 ms delay. 1262 * - If HPD is hooked up we won't try to look at it for the 1263 * first 15 ms. 1264 */ 1265 .prepare = 15, 1266 .hpd_absent_delay = 185, 1267 1268 .unprepare = 500, 1269 }, 1270 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1271 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1272 .connector_type = DRM_MODE_CONNECTOR_eDP, 1273 }; 1274 1275 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1276 { 1277 .clock = 148500, 1278 .hdisplay = 1920, 1279 .hsync_start = 1920 + 48, 1280 .hsync_end = 1920 + 48 + 32, 1281 .htotal = 2200, 1282 .vdisplay = 1080, 1283 .vsync_start = 1080 + 3, 1284 .vsync_end = 1080 + 3 + 5, 1285 .vtotal = 1125, 1286 .vrefresh = 60, 1287 }, 1288 }; 1289 1290 static const struct panel_desc boe_nv140fhmn49 = { 1291 .modes = boe_nv140fhmn49_modes, 1292 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1293 .bpc = 6, 1294 .size = { 1295 .width = 309, 1296 .height = 174, 1297 }, 1298 .delay = { 1299 .prepare = 210, 1300 .enable = 50, 1301 .unprepare = 160, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1304 .connector_type = DRM_MODE_CONNECTOR_eDP, 1305 }; 1306 1307 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1308 .clock = 9000, 1309 .hdisplay = 480, 1310 .hsync_start = 480 + 5, 1311 .hsync_end = 480 + 5 + 5, 1312 .htotal = 480 + 5 + 5 + 40, 1313 .vdisplay = 272, 1314 .vsync_start = 272 + 8, 1315 .vsync_end = 272 + 8 + 8, 1316 .vtotal = 272 + 8 + 8 + 8, 1317 .vrefresh = 60, 1318 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1319 }; 1320 1321 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1322 .modes = &cdtech_s043wq26h_ct7_mode, 1323 .num_modes = 1, 1324 .bpc = 8, 1325 .size = { 1326 .width = 95, 1327 .height = 54, 1328 }, 1329 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1330 }; 1331 1332 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1333 .clock = 35000, 1334 .hdisplay = 800, 1335 .hsync_start = 800 + 40, 1336 .hsync_end = 800 + 40 + 40, 1337 .htotal = 800 + 40 + 40 + 48, 1338 .vdisplay = 480, 1339 .vsync_start = 480 + 29, 1340 .vsync_end = 480 + 29 + 13, 1341 .vtotal = 480 + 29 + 13 + 3, 1342 .vrefresh = 60, 1343 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1344 }; 1345 1346 static const struct panel_desc cdtech_s070wv95_ct16 = { 1347 .modes = &cdtech_s070wv95_ct16_mode, 1348 .num_modes = 1, 1349 .bpc = 8, 1350 .size = { 1351 .width = 154, 1352 .height = 85, 1353 }, 1354 }; 1355 1356 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1357 .clock = 66770, 1358 .hdisplay = 800, 1359 .hsync_start = 800 + 49, 1360 .hsync_end = 800 + 49 + 33, 1361 .htotal = 800 + 49 + 33 + 17, 1362 .vdisplay = 1280, 1363 .vsync_start = 1280 + 1, 1364 .vsync_end = 1280 + 1 + 7, 1365 .vtotal = 1280 + 1 + 7 + 15, 1366 .vrefresh = 60, 1367 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1368 }; 1369 1370 static const struct panel_desc chunghwa_claa070wp03xg = { 1371 .modes = &chunghwa_claa070wp03xg_mode, 1372 .num_modes = 1, 1373 .bpc = 6, 1374 .size = { 1375 .width = 94, 1376 .height = 150, 1377 }, 1378 }; 1379 1380 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1381 .clock = 72070, 1382 .hdisplay = 1366, 1383 .hsync_start = 1366 + 58, 1384 .hsync_end = 1366 + 58 + 58, 1385 .htotal = 1366 + 58 + 58 + 58, 1386 .vdisplay = 768, 1387 .vsync_start = 768 + 4, 1388 .vsync_end = 768 + 4 + 4, 1389 .vtotal = 768 + 4 + 4 + 4, 1390 .vrefresh = 60, 1391 }; 1392 1393 static const struct panel_desc chunghwa_claa101wa01a = { 1394 .modes = &chunghwa_claa101wa01a_mode, 1395 .num_modes = 1, 1396 .bpc = 6, 1397 .size = { 1398 .width = 220, 1399 .height = 120, 1400 }, 1401 }; 1402 1403 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1404 .clock = 69300, 1405 .hdisplay = 1366, 1406 .hsync_start = 1366 + 48, 1407 .hsync_end = 1366 + 48 + 32, 1408 .htotal = 1366 + 48 + 32 + 20, 1409 .vdisplay = 768, 1410 .vsync_start = 768 + 16, 1411 .vsync_end = 768 + 16 + 8, 1412 .vtotal = 768 + 16 + 8 + 16, 1413 .vrefresh = 60, 1414 }; 1415 1416 static const struct panel_desc chunghwa_claa101wb01 = { 1417 .modes = &chunghwa_claa101wb01_mode, 1418 .num_modes = 1, 1419 .bpc = 6, 1420 .size = { 1421 .width = 223, 1422 .height = 125, 1423 }, 1424 }; 1425 1426 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1427 .clock = 33260, 1428 .hdisplay = 800, 1429 .hsync_start = 800 + 40, 1430 .hsync_end = 800 + 40 + 128, 1431 .htotal = 800 + 40 + 128 + 88, 1432 .vdisplay = 480, 1433 .vsync_start = 480 + 10, 1434 .vsync_end = 480 + 10 + 2, 1435 .vtotal = 480 + 10 + 2 + 33, 1436 .vrefresh = 60, 1437 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1438 }; 1439 1440 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1441 .modes = &dataimage_scf0700c48ggu18_mode, 1442 .num_modes = 1, 1443 .bpc = 8, 1444 .size = { 1445 .width = 152, 1446 .height = 91, 1447 }, 1448 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1449 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1450 }; 1451 1452 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1453 .pixelclock = { 45000000, 51200000, 57000000 }, 1454 .hactive = { 1024, 1024, 1024 }, 1455 .hfront_porch = { 100, 106, 113 }, 1456 .hback_porch = { 100, 106, 113 }, 1457 .hsync_len = { 100, 108, 114 }, 1458 .vactive = { 600, 600, 600 }, 1459 .vfront_porch = { 8, 11, 15 }, 1460 .vback_porch = { 8, 11, 15 }, 1461 .vsync_len = { 9, 13, 15 }, 1462 .flags = DISPLAY_FLAGS_DE_HIGH, 1463 }; 1464 1465 static const struct panel_desc dlc_dlc0700yzg_1 = { 1466 .timings = &dlc_dlc0700yzg_1_timing, 1467 .num_timings = 1, 1468 .bpc = 6, 1469 .size = { 1470 .width = 154, 1471 .height = 86, 1472 }, 1473 .delay = { 1474 .prepare = 30, 1475 .enable = 200, 1476 .disable = 200, 1477 }, 1478 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1480 }; 1481 1482 static const struct display_timing dlc_dlc1010gig_timing = { 1483 .pixelclock = { 68900000, 71100000, 73400000 }, 1484 .hactive = { 1280, 1280, 1280 }, 1485 .hfront_porch = { 43, 53, 63 }, 1486 .hback_porch = { 43, 53, 63 }, 1487 .hsync_len = { 44, 54, 64 }, 1488 .vactive = { 800, 800, 800 }, 1489 .vfront_porch = { 5, 8, 11 }, 1490 .vback_porch = { 5, 8, 11 }, 1491 .vsync_len = { 5, 7, 11 }, 1492 .flags = DISPLAY_FLAGS_DE_HIGH, 1493 }; 1494 1495 static const struct panel_desc dlc_dlc1010gig = { 1496 .timings = &dlc_dlc1010gig_timing, 1497 .num_timings = 1, 1498 .bpc = 8, 1499 .size = { 1500 .width = 216, 1501 .height = 135, 1502 }, 1503 .delay = { 1504 .prepare = 60, 1505 .enable = 150, 1506 .disable = 100, 1507 .unprepare = 60, 1508 }, 1509 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1510 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1511 }; 1512 1513 static const struct drm_display_mode edt_et035012dm6_mode = { 1514 .clock = 6500, 1515 .hdisplay = 320, 1516 .hsync_start = 320 + 20, 1517 .hsync_end = 320 + 20 + 30, 1518 .htotal = 320 + 20 + 68, 1519 .vdisplay = 240, 1520 .vsync_start = 240 + 4, 1521 .vsync_end = 240 + 4 + 4, 1522 .vtotal = 240 + 4 + 4 + 14, 1523 .vrefresh = 60, 1524 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1525 }; 1526 1527 static const struct panel_desc edt_et035012dm6 = { 1528 .modes = &edt_et035012dm6_mode, 1529 .num_modes = 1, 1530 .bpc = 8, 1531 .size = { 1532 .width = 70, 1533 .height = 52, 1534 }, 1535 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1536 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1537 }; 1538 1539 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1540 .clock = 10870, 1541 .hdisplay = 480, 1542 .hsync_start = 480 + 8, 1543 .hsync_end = 480 + 8 + 4, 1544 .htotal = 480 + 8 + 4 + 41, 1545 1546 /* 1547 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1548 * fb_align 1549 */ 1550 1551 .vdisplay = 288, 1552 .vsync_start = 288 + 2, 1553 .vsync_end = 288 + 2 + 4, 1554 .vtotal = 288 + 2 + 4 + 10, 1555 .vrefresh = 60, 1556 }; 1557 1558 static const struct panel_desc edt_etm043080dh6gp = { 1559 .modes = &edt_etm043080dh6gp_mode, 1560 .num_modes = 1, 1561 .bpc = 8, 1562 .size = { 1563 .width = 100, 1564 .height = 65, 1565 }, 1566 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1567 .connector_type = DRM_MODE_CONNECTOR_DPI, 1568 }; 1569 1570 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1571 .clock = 9000, 1572 .hdisplay = 480, 1573 .hsync_start = 480 + 2, 1574 .hsync_end = 480 + 2 + 41, 1575 .htotal = 480 + 2 + 41 + 2, 1576 .vdisplay = 272, 1577 .vsync_start = 272 + 2, 1578 .vsync_end = 272 + 2 + 10, 1579 .vtotal = 272 + 2 + 10 + 2, 1580 .vrefresh = 60, 1581 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1582 }; 1583 1584 static const struct panel_desc edt_etm0430g0dh6 = { 1585 .modes = &edt_etm0430g0dh6_mode, 1586 .num_modes = 1, 1587 .bpc = 6, 1588 .size = { 1589 .width = 95, 1590 .height = 54, 1591 }, 1592 }; 1593 1594 static const struct drm_display_mode edt_et057090dhu_mode = { 1595 .clock = 25175, 1596 .hdisplay = 640, 1597 .hsync_start = 640 + 16, 1598 .hsync_end = 640 + 16 + 30, 1599 .htotal = 640 + 16 + 30 + 114, 1600 .vdisplay = 480, 1601 .vsync_start = 480 + 10, 1602 .vsync_end = 480 + 10 + 3, 1603 .vtotal = 480 + 10 + 3 + 32, 1604 .vrefresh = 60, 1605 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1606 }; 1607 1608 static const struct panel_desc edt_et057090dhu = { 1609 .modes = &edt_et057090dhu_mode, 1610 .num_modes = 1, 1611 .bpc = 6, 1612 .size = { 1613 .width = 115, 1614 .height = 86, 1615 }, 1616 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1617 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1618 }; 1619 1620 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1621 .clock = 33260, 1622 .hdisplay = 800, 1623 .hsync_start = 800 + 40, 1624 .hsync_end = 800 + 40 + 128, 1625 .htotal = 800 + 40 + 128 + 88, 1626 .vdisplay = 480, 1627 .vsync_start = 480 + 10, 1628 .vsync_end = 480 + 10 + 2, 1629 .vtotal = 480 + 10 + 2 + 33, 1630 .vrefresh = 60, 1631 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1632 }; 1633 1634 static const struct panel_desc edt_etm0700g0dh6 = { 1635 .modes = &edt_etm0700g0dh6_mode, 1636 .num_modes = 1, 1637 .bpc = 6, 1638 .size = { 1639 .width = 152, 1640 .height = 91, 1641 }, 1642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1643 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1644 }; 1645 1646 static const struct panel_desc edt_etm0700g0bdh6 = { 1647 .modes = &edt_etm0700g0dh6_mode, 1648 .num_modes = 1, 1649 .bpc = 6, 1650 .size = { 1651 .width = 152, 1652 .height = 91, 1653 }, 1654 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1655 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1656 }; 1657 1658 static const struct display_timing evervision_vgg804821_timing = { 1659 .pixelclock = { 27600000, 33300000, 50000000 }, 1660 .hactive = { 800, 800, 800 }, 1661 .hfront_porch = { 40, 66, 70 }, 1662 .hback_porch = { 40, 67, 70 }, 1663 .hsync_len = { 40, 67, 70 }, 1664 .vactive = { 480, 480, 480 }, 1665 .vfront_porch = { 6, 10, 10 }, 1666 .vback_porch = { 7, 11, 11 }, 1667 .vsync_len = { 7, 11, 11 }, 1668 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1669 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1670 DISPLAY_FLAGS_SYNC_NEGEDGE, 1671 }; 1672 1673 static const struct panel_desc evervision_vgg804821 = { 1674 .timings = &evervision_vgg804821_timing, 1675 .num_timings = 1, 1676 .bpc = 8, 1677 .size = { 1678 .width = 108, 1679 .height = 64, 1680 }, 1681 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1682 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1683 }; 1684 1685 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1686 .clock = 32260, 1687 .hdisplay = 800, 1688 .hsync_start = 800 + 168, 1689 .hsync_end = 800 + 168 + 64, 1690 .htotal = 800 + 168 + 64 + 88, 1691 .vdisplay = 480, 1692 .vsync_start = 480 + 37, 1693 .vsync_end = 480 + 37 + 2, 1694 .vtotal = 480 + 37 + 2 + 8, 1695 .vrefresh = 60, 1696 }; 1697 1698 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1699 .modes = &foxlink_fl500wvr00_a0t_mode, 1700 .num_modes = 1, 1701 .bpc = 8, 1702 .size = { 1703 .width = 108, 1704 .height = 65, 1705 }, 1706 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1707 }; 1708 1709 static const struct drm_display_mode frida_frd350h54004_mode = { 1710 .clock = 6000, 1711 .hdisplay = 320, 1712 .hsync_start = 320 + 44, 1713 .hsync_end = 320 + 44 + 16, 1714 .htotal = 320 + 44 + 16 + 20, 1715 .vdisplay = 240, 1716 .vsync_start = 240 + 2, 1717 .vsync_end = 240 + 2 + 6, 1718 .vtotal = 240 + 2 + 6 + 2, 1719 .vrefresh = 60, 1720 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1721 }; 1722 1723 static const struct panel_desc frida_frd350h54004 = { 1724 .modes = &frida_frd350h54004_mode, 1725 .num_modes = 1, 1726 .bpc = 8, 1727 .size = { 1728 .width = 77, 1729 .height = 64, 1730 }, 1731 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1732 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1733 .connector_type = DRM_MODE_CONNECTOR_DPI, 1734 }; 1735 1736 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1737 .clock = 67185, 1738 .hdisplay = 800, 1739 .hsync_start = 800 + 20, 1740 .hsync_end = 800 + 20 + 24, 1741 .htotal = 800 + 20 + 24 + 20, 1742 .vdisplay = 1280, 1743 .vsync_start = 1280 + 4, 1744 .vsync_end = 1280 + 4 + 8, 1745 .vtotal = 1280 + 4 + 8 + 4, 1746 .vrefresh = 60, 1747 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1748 }; 1749 1750 static const struct panel_desc friendlyarm_hd702e = { 1751 .modes = &friendlyarm_hd702e_mode, 1752 .num_modes = 1, 1753 .size = { 1754 .width = 94, 1755 .height = 151, 1756 }, 1757 }; 1758 1759 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1760 .clock = 9000, 1761 .hdisplay = 480, 1762 .hsync_start = 480 + 5, 1763 .hsync_end = 480 + 5 + 1, 1764 .htotal = 480 + 5 + 1 + 40, 1765 .vdisplay = 272, 1766 .vsync_start = 272 + 8, 1767 .vsync_end = 272 + 8 + 1, 1768 .vtotal = 272 + 8 + 1 + 8, 1769 .vrefresh = 60, 1770 }; 1771 1772 static const struct panel_desc giantplus_gpg482739qs5 = { 1773 .modes = &giantplus_gpg482739qs5_mode, 1774 .num_modes = 1, 1775 .bpc = 8, 1776 .size = { 1777 .width = 95, 1778 .height = 54, 1779 }, 1780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1781 }; 1782 1783 static const struct display_timing giantplus_gpm940b0_timing = { 1784 .pixelclock = { 13500000, 27000000, 27500000 }, 1785 .hactive = { 320, 320, 320 }, 1786 .hfront_porch = { 14, 686, 718 }, 1787 .hback_porch = { 50, 70, 255 }, 1788 .hsync_len = { 1, 1, 1 }, 1789 .vactive = { 240, 240, 240 }, 1790 .vfront_porch = { 1, 1, 179 }, 1791 .vback_porch = { 1, 21, 31 }, 1792 .vsync_len = { 1, 1, 6 }, 1793 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1794 }; 1795 1796 static const struct panel_desc giantplus_gpm940b0 = { 1797 .timings = &giantplus_gpm940b0_timing, 1798 .num_timings = 1, 1799 .bpc = 8, 1800 .size = { 1801 .width = 60, 1802 .height = 45, 1803 }, 1804 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1806 }; 1807 1808 static const struct display_timing hannstar_hsd070pww1_timing = { 1809 .pixelclock = { 64300000, 71100000, 82000000 }, 1810 .hactive = { 1280, 1280, 1280 }, 1811 .hfront_porch = { 1, 1, 10 }, 1812 .hback_porch = { 1, 1, 10 }, 1813 /* 1814 * According to the data sheet, the minimum horizontal blanking interval 1815 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1816 * minimum working horizontal blanking interval to be 60 clocks. 1817 */ 1818 .hsync_len = { 58, 158, 661 }, 1819 .vactive = { 800, 800, 800 }, 1820 .vfront_porch = { 1, 1, 10 }, 1821 .vback_porch = { 1, 1, 10 }, 1822 .vsync_len = { 1, 21, 203 }, 1823 .flags = DISPLAY_FLAGS_DE_HIGH, 1824 }; 1825 1826 static const struct panel_desc hannstar_hsd070pww1 = { 1827 .timings = &hannstar_hsd070pww1_timing, 1828 .num_timings = 1, 1829 .bpc = 6, 1830 .size = { 1831 .width = 151, 1832 .height = 94, 1833 }, 1834 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1835 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1836 }; 1837 1838 static const struct display_timing hannstar_hsd100pxn1_timing = { 1839 .pixelclock = { 55000000, 65000000, 75000000 }, 1840 .hactive = { 1024, 1024, 1024 }, 1841 .hfront_porch = { 40, 40, 40 }, 1842 .hback_porch = { 220, 220, 220 }, 1843 .hsync_len = { 20, 60, 100 }, 1844 .vactive = { 768, 768, 768 }, 1845 .vfront_porch = { 7, 7, 7 }, 1846 .vback_porch = { 21, 21, 21 }, 1847 .vsync_len = { 10, 10, 10 }, 1848 .flags = DISPLAY_FLAGS_DE_HIGH, 1849 }; 1850 1851 static const struct panel_desc hannstar_hsd100pxn1 = { 1852 .timings = &hannstar_hsd100pxn1_timing, 1853 .num_timings = 1, 1854 .bpc = 6, 1855 .size = { 1856 .width = 203, 1857 .height = 152, 1858 }, 1859 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1860 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1861 }; 1862 1863 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1864 .clock = 33333, 1865 .hdisplay = 800, 1866 .hsync_start = 800 + 85, 1867 .hsync_end = 800 + 85 + 86, 1868 .htotal = 800 + 85 + 86 + 85, 1869 .vdisplay = 480, 1870 .vsync_start = 480 + 16, 1871 .vsync_end = 480 + 16 + 13, 1872 .vtotal = 480 + 16 + 13 + 16, 1873 .vrefresh = 60, 1874 }; 1875 1876 static const struct panel_desc hitachi_tx23d38vm0caa = { 1877 .modes = &hitachi_tx23d38vm0caa_mode, 1878 .num_modes = 1, 1879 .bpc = 6, 1880 .size = { 1881 .width = 195, 1882 .height = 117, 1883 }, 1884 .delay = { 1885 .enable = 160, 1886 .disable = 160, 1887 }, 1888 }; 1889 1890 static const struct drm_display_mode innolux_at043tn24_mode = { 1891 .clock = 9000, 1892 .hdisplay = 480, 1893 .hsync_start = 480 + 2, 1894 .hsync_end = 480 + 2 + 41, 1895 .htotal = 480 + 2 + 41 + 2, 1896 .vdisplay = 272, 1897 .vsync_start = 272 + 2, 1898 .vsync_end = 272 + 2 + 10, 1899 .vtotal = 272 + 2 + 10 + 2, 1900 .vrefresh = 60, 1901 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1902 }; 1903 1904 static const struct panel_desc innolux_at043tn24 = { 1905 .modes = &innolux_at043tn24_mode, 1906 .num_modes = 1, 1907 .bpc = 8, 1908 .size = { 1909 .width = 95, 1910 .height = 54, 1911 }, 1912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1914 }; 1915 1916 static const struct drm_display_mode innolux_at070tn92_mode = { 1917 .clock = 33333, 1918 .hdisplay = 800, 1919 .hsync_start = 800 + 210, 1920 .hsync_end = 800 + 210 + 20, 1921 .htotal = 800 + 210 + 20 + 46, 1922 .vdisplay = 480, 1923 .vsync_start = 480 + 22, 1924 .vsync_end = 480 + 22 + 10, 1925 .vtotal = 480 + 22 + 23 + 10, 1926 .vrefresh = 60, 1927 }; 1928 1929 static const struct panel_desc innolux_at070tn92 = { 1930 .modes = &innolux_at070tn92_mode, 1931 .num_modes = 1, 1932 .size = { 1933 .width = 154, 1934 .height = 86, 1935 }, 1936 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1937 }; 1938 1939 static const struct display_timing innolux_g070y2_l01_timing = { 1940 .pixelclock = { 28000000, 29500000, 32000000 }, 1941 .hactive = { 800, 800, 800 }, 1942 .hfront_porch = { 61, 91, 141 }, 1943 .hback_porch = { 60, 90, 140 }, 1944 .hsync_len = { 12, 12, 12 }, 1945 .vactive = { 480, 480, 480 }, 1946 .vfront_porch = { 4, 9, 30 }, 1947 .vback_porch = { 4, 8, 28 }, 1948 .vsync_len = { 2, 2, 2 }, 1949 .flags = DISPLAY_FLAGS_DE_HIGH, 1950 }; 1951 1952 static const struct panel_desc innolux_g070y2_l01 = { 1953 .timings = &innolux_g070y2_l01_timing, 1954 .num_timings = 1, 1955 .bpc = 6, 1956 .size = { 1957 .width = 152, 1958 .height = 91, 1959 }, 1960 .delay = { 1961 .prepare = 10, 1962 .enable = 100, 1963 .disable = 100, 1964 .unprepare = 800, 1965 }, 1966 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1967 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1968 }; 1969 1970 static const struct display_timing innolux_g101ice_l01_timing = { 1971 .pixelclock = { 60400000, 71100000, 74700000 }, 1972 .hactive = { 1280, 1280, 1280 }, 1973 .hfront_porch = { 41, 80, 100 }, 1974 .hback_porch = { 40, 79, 99 }, 1975 .hsync_len = { 1, 1, 1 }, 1976 .vactive = { 800, 800, 800 }, 1977 .vfront_porch = { 5, 11, 14 }, 1978 .vback_porch = { 4, 11, 14 }, 1979 .vsync_len = { 1, 1, 1 }, 1980 .flags = DISPLAY_FLAGS_DE_HIGH, 1981 }; 1982 1983 static const struct panel_desc innolux_g101ice_l01 = { 1984 .timings = &innolux_g101ice_l01_timing, 1985 .num_timings = 1, 1986 .bpc = 8, 1987 .size = { 1988 .width = 217, 1989 .height = 135, 1990 }, 1991 .delay = { 1992 .enable = 200, 1993 .disable = 200, 1994 }, 1995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1997 }; 1998 1999 static const struct display_timing innolux_g121i1_l01_timing = { 2000 .pixelclock = { 67450000, 71000000, 74550000 }, 2001 .hactive = { 1280, 1280, 1280 }, 2002 .hfront_porch = { 40, 80, 160 }, 2003 .hback_porch = { 39, 79, 159 }, 2004 .hsync_len = { 1, 1, 1 }, 2005 .vactive = { 800, 800, 800 }, 2006 .vfront_porch = { 5, 11, 100 }, 2007 .vback_porch = { 4, 11, 99 }, 2008 .vsync_len = { 1, 1, 1 }, 2009 }; 2010 2011 static const struct panel_desc innolux_g121i1_l01 = { 2012 .timings = &innolux_g121i1_l01_timing, 2013 .num_timings = 1, 2014 .bpc = 6, 2015 .size = { 2016 .width = 261, 2017 .height = 163, 2018 }, 2019 .delay = { 2020 .enable = 200, 2021 .disable = 20, 2022 }, 2023 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2024 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2025 }; 2026 2027 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2028 .clock = 65000, 2029 .hdisplay = 1024, 2030 .hsync_start = 1024 + 0, 2031 .hsync_end = 1024 + 1, 2032 .htotal = 1024 + 0 + 1 + 320, 2033 .vdisplay = 768, 2034 .vsync_start = 768 + 38, 2035 .vsync_end = 768 + 38 + 1, 2036 .vtotal = 768 + 38 + 1 + 0, 2037 .vrefresh = 60, 2038 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2039 }; 2040 2041 static const struct panel_desc innolux_g121x1_l03 = { 2042 .modes = &innolux_g121x1_l03_mode, 2043 .num_modes = 1, 2044 .bpc = 6, 2045 .size = { 2046 .width = 246, 2047 .height = 185, 2048 }, 2049 .delay = { 2050 .enable = 200, 2051 .unprepare = 200, 2052 .disable = 400, 2053 }, 2054 }; 2055 2056 /* 2057 * Datasheet specifies that at 60 Hz refresh rate: 2058 * - total horizontal time: { 1506, 1592, 1716 } 2059 * - total vertical time: { 788, 800, 868 } 2060 * 2061 * ...but doesn't go into exactly how that should be split into a front 2062 * porch, back porch, or sync length. For now we'll leave a single setting 2063 * here which allows a bit of tweaking of the pixel clock at the expense of 2064 * refresh rate. 2065 */ 2066 static const struct display_timing innolux_n116bge_timing = { 2067 .pixelclock = { 72600000, 76420000, 80240000 }, 2068 .hactive = { 1366, 1366, 1366 }, 2069 .hfront_porch = { 136, 136, 136 }, 2070 .hback_porch = { 60, 60, 60 }, 2071 .hsync_len = { 30, 30, 30 }, 2072 .vactive = { 768, 768, 768 }, 2073 .vfront_porch = { 8, 8, 8 }, 2074 .vback_porch = { 12, 12, 12 }, 2075 .vsync_len = { 12, 12, 12 }, 2076 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2077 }; 2078 2079 static const struct panel_desc innolux_n116bge = { 2080 .timings = &innolux_n116bge_timing, 2081 .num_timings = 1, 2082 .bpc = 6, 2083 .size = { 2084 .width = 256, 2085 .height = 144, 2086 }, 2087 }; 2088 2089 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2090 .clock = 69300, 2091 .hdisplay = 1366, 2092 .hsync_start = 1366 + 16, 2093 .hsync_end = 1366 + 16 + 34, 2094 .htotal = 1366 + 16 + 34 + 50, 2095 .vdisplay = 768, 2096 .vsync_start = 768 + 2, 2097 .vsync_end = 768 + 2 + 6, 2098 .vtotal = 768 + 2 + 6 + 12, 2099 .vrefresh = 60, 2100 }; 2101 2102 static const struct panel_desc innolux_n156bge_l21 = { 2103 .modes = &innolux_n156bge_l21_mode, 2104 .num_modes = 1, 2105 .bpc = 6, 2106 .size = { 2107 .width = 344, 2108 .height = 193, 2109 }, 2110 }; 2111 2112 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2113 .clock = 206016, 2114 .hdisplay = 2160, 2115 .hsync_start = 2160 + 48, 2116 .hsync_end = 2160 + 48 + 32, 2117 .htotal = 2160 + 48 + 32 + 80, 2118 .vdisplay = 1440, 2119 .vsync_start = 1440 + 3, 2120 .vsync_end = 1440 + 3 + 10, 2121 .vtotal = 1440 + 3 + 10 + 27, 2122 .vrefresh = 60, 2123 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2124 }; 2125 2126 static const struct panel_desc innolux_p120zdg_bf1 = { 2127 .modes = &innolux_p120zdg_bf1_mode, 2128 .num_modes = 1, 2129 .bpc = 8, 2130 .size = { 2131 .width = 254, 2132 .height = 169, 2133 }, 2134 .delay = { 2135 .hpd_absent_delay = 200, 2136 .unprepare = 500, 2137 }, 2138 }; 2139 2140 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2141 .clock = 51501, 2142 .hdisplay = 1024, 2143 .hsync_start = 1024 + 128, 2144 .hsync_end = 1024 + 128 + 64, 2145 .htotal = 1024 + 128 + 64 + 128, 2146 .vdisplay = 600, 2147 .vsync_start = 600 + 16, 2148 .vsync_end = 600 + 16 + 4, 2149 .vtotal = 600 + 16 + 4 + 16, 2150 .vrefresh = 60, 2151 }; 2152 2153 static const struct panel_desc innolux_zj070na_01p = { 2154 .modes = &innolux_zj070na_01p_mode, 2155 .num_modes = 1, 2156 .bpc = 6, 2157 .size = { 2158 .width = 154, 2159 .height = 90, 2160 }, 2161 }; 2162 2163 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2164 .clock = 138778, 2165 .hdisplay = 1920, 2166 .hsync_start = 1920 + 24, 2167 .hsync_end = 1920 + 24 + 48, 2168 .htotal = 1920 + 24 + 48 + 88, 2169 .vdisplay = 1080, 2170 .vsync_start = 1080 + 3, 2171 .vsync_end = 1080 + 3 + 12, 2172 .vtotal = 1080 + 3 + 12 + 17, 2173 .vrefresh = 60, 2174 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2175 }; 2176 2177 static const struct panel_desc ivo_m133nwf4_r0 = { 2178 .modes = &ivo_m133nwf4_r0_mode, 2179 .num_modes = 1, 2180 .bpc = 8, 2181 .size = { 2182 .width = 294, 2183 .height = 165, 2184 }, 2185 .delay = { 2186 .hpd_absent_delay = 200, 2187 .unprepare = 500, 2188 }, 2189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2190 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2191 .connector_type = DRM_MODE_CONNECTOR_eDP, 2192 }; 2193 2194 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2195 .pixelclock = { 5580000, 5850000, 6200000 }, 2196 .hactive = { 320, 320, 320 }, 2197 .hfront_porch = { 30, 30, 30 }, 2198 .hback_porch = { 30, 30, 30 }, 2199 .hsync_len = { 1, 5, 17 }, 2200 .vactive = { 240, 240, 240 }, 2201 .vfront_porch = { 6, 6, 6 }, 2202 .vback_porch = { 5, 5, 5 }, 2203 .vsync_len = { 1, 2, 11 }, 2204 .flags = DISPLAY_FLAGS_DE_HIGH, 2205 }; 2206 2207 static const struct panel_desc koe_tx14d24vm1bpa = { 2208 .timings = &koe_tx14d24vm1bpa_timing, 2209 .num_timings = 1, 2210 .bpc = 6, 2211 .size = { 2212 .width = 115, 2213 .height = 86, 2214 }, 2215 }; 2216 2217 static const struct display_timing koe_tx31d200vm0baa_timing = { 2218 .pixelclock = { 39600000, 43200000, 48000000 }, 2219 .hactive = { 1280, 1280, 1280 }, 2220 .hfront_porch = { 16, 36, 56 }, 2221 .hback_porch = { 16, 36, 56 }, 2222 .hsync_len = { 8, 8, 8 }, 2223 .vactive = { 480, 480, 480 }, 2224 .vfront_porch = { 6, 21, 33 }, 2225 .vback_porch = { 6, 21, 33 }, 2226 .vsync_len = { 8, 8, 8 }, 2227 .flags = DISPLAY_FLAGS_DE_HIGH, 2228 }; 2229 2230 static const struct panel_desc koe_tx31d200vm0baa = { 2231 .timings = &koe_tx31d200vm0baa_timing, 2232 .num_timings = 1, 2233 .bpc = 6, 2234 .size = { 2235 .width = 292, 2236 .height = 109, 2237 }, 2238 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2240 }; 2241 2242 static const struct display_timing kyo_tcg121xglp_timing = { 2243 .pixelclock = { 52000000, 65000000, 71000000 }, 2244 .hactive = { 1024, 1024, 1024 }, 2245 .hfront_porch = { 2, 2, 2 }, 2246 .hback_porch = { 2, 2, 2 }, 2247 .hsync_len = { 86, 124, 244 }, 2248 .vactive = { 768, 768, 768 }, 2249 .vfront_porch = { 2, 2, 2 }, 2250 .vback_porch = { 2, 2, 2 }, 2251 .vsync_len = { 6, 34, 73 }, 2252 .flags = DISPLAY_FLAGS_DE_HIGH, 2253 }; 2254 2255 static const struct panel_desc kyo_tcg121xglp = { 2256 .timings = &kyo_tcg121xglp_timing, 2257 .num_timings = 1, 2258 .bpc = 8, 2259 .size = { 2260 .width = 246, 2261 .height = 184, 2262 }, 2263 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2264 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2265 }; 2266 2267 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2268 .clock = 7000, 2269 .hdisplay = 320, 2270 .hsync_start = 320 + 20, 2271 .hsync_end = 320 + 20 + 30, 2272 .htotal = 320 + 20 + 30 + 38, 2273 .vdisplay = 240, 2274 .vsync_start = 240 + 4, 2275 .vsync_end = 240 + 4 + 3, 2276 .vtotal = 240 + 4 + 3 + 15, 2277 .vrefresh = 60, 2278 }; 2279 2280 static const struct panel_desc lemaker_bl035_rgb_002 = { 2281 .modes = &lemaker_bl035_rgb_002_mode, 2282 .num_modes = 1, 2283 .size = { 2284 .width = 70, 2285 .height = 52, 2286 }, 2287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2288 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2289 }; 2290 2291 static const struct drm_display_mode lg_lb070wv8_mode = { 2292 .clock = 33246, 2293 .hdisplay = 800, 2294 .hsync_start = 800 + 88, 2295 .hsync_end = 800 + 88 + 80, 2296 .htotal = 800 + 88 + 80 + 88, 2297 .vdisplay = 480, 2298 .vsync_start = 480 + 10, 2299 .vsync_end = 480 + 10 + 25, 2300 .vtotal = 480 + 10 + 25 + 10, 2301 .vrefresh = 60, 2302 }; 2303 2304 static const struct panel_desc lg_lb070wv8 = { 2305 .modes = &lg_lb070wv8_mode, 2306 .num_modes = 1, 2307 .bpc = 16, 2308 .size = { 2309 .width = 151, 2310 .height = 91, 2311 }, 2312 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2313 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2314 }; 2315 2316 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2317 .clock = 200000, 2318 .hdisplay = 1536, 2319 .hsync_start = 1536 + 12, 2320 .hsync_end = 1536 + 12 + 16, 2321 .htotal = 1536 + 12 + 16 + 48, 2322 .vdisplay = 2048, 2323 .vsync_start = 2048 + 8, 2324 .vsync_end = 2048 + 8 + 4, 2325 .vtotal = 2048 + 8 + 4 + 8, 2326 .vrefresh = 60, 2327 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2328 }; 2329 2330 static const struct panel_desc lg_lp079qx1_sp0v = { 2331 .modes = &lg_lp079qx1_sp0v_mode, 2332 .num_modes = 1, 2333 .size = { 2334 .width = 129, 2335 .height = 171, 2336 }, 2337 }; 2338 2339 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2340 .clock = 205210, 2341 .hdisplay = 2048, 2342 .hsync_start = 2048 + 150, 2343 .hsync_end = 2048 + 150 + 5, 2344 .htotal = 2048 + 150 + 5 + 5, 2345 .vdisplay = 1536, 2346 .vsync_start = 1536 + 3, 2347 .vsync_end = 1536 + 3 + 1, 2348 .vtotal = 1536 + 3 + 1 + 9, 2349 .vrefresh = 60, 2350 }; 2351 2352 static const struct panel_desc lg_lp097qx1_spa1 = { 2353 .modes = &lg_lp097qx1_spa1_mode, 2354 .num_modes = 1, 2355 .size = { 2356 .width = 208, 2357 .height = 147, 2358 }, 2359 }; 2360 2361 static const struct drm_display_mode lg_lp120up1_mode = { 2362 .clock = 162300, 2363 .hdisplay = 1920, 2364 .hsync_start = 1920 + 40, 2365 .hsync_end = 1920 + 40 + 40, 2366 .htotal = 1920 + 40 + 40+ 80, 2367 .vdisplay = 1280, 2368 .vsync_start = 1280 + 4, 2369 .vsync_end = 1280 + 4 + 4, 2370 .vtotal = 1280 + 4 + 4 + 12, 2371 .vrefresh = 60, 2372 }; 2373 2374 static const struct panel_desc lg_lp120up1 = { 2375 .modes = &lg_lp120up1_mode, 2376 .num_modes = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 267, 2380 .height = 183, 2381 }, 2382 .connector_type = DRM_MODE_CONNECTOR_eDP, 2383 }; 2384 2385 static const struct drm_display_mode lg_lp129qe_mode = { 2386 .clock = 285250, 2387 .hdisplay = 2560, 2388 .hsync_start = 2560 + 48, 2389 .hsync_end = 2560 + 48 + 32, 2390 .htotal = 2560 + 48 + 32 + 80, 2391 .vdisplay = 1700, 2392 .vsync_start = 1700 + 3, 2393 .vsync_end = 1700 + 3 + 10, 2394 .vtotal = 1700 + 3 + 10 + 36, 2395 .vrefresh = 60, 2396 }; 2397 2398 static const struct panel_desc lg_lp129qe = { 2399 .modes = &lg_lp129qe_mode, 2400 .num_modes = 1, 2401 .bpc = 8, 2402 .size = { 2403 .width = 272, 2404 .height = 181, 2405 }, 2406 }; 2407 2408 static const struct display_timing logictechno_lt161010_2nh_timing = { 2409 .pixelclock = { 26400000, 33300000, 46800000 }, 2410 .hactive = { 800, 800, 800 }, 2411 .hfront_porch = { 16, 210, 354 }, 2412 .hback_porch = { 46, 46, 46 }, 2413 .hsync_len = { 1, 20, 40 }, 2414 .vactive = { 480, 480, 480 }, 2415 .vfront_porch = { 7, 22, 147 }, 2416 .vback_porch = { 23, 23, 23 }, 2417 .vsync_len = { 1, 10, 20 }, 2418 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2419 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2420 DISPLAY_FLAGS_SYNC_POSEDGE, 2421 }; 2422 2423 static const struct panel_desc logictechno_lt161010_2nh = { 2424 .timings = &logictechno_lt161010_2nh_timing, 2425 .num_timings = 1, 2426 .size = { 2427 .width = 154, 2428 .height = 86, 2429 }, 2430 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2431 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2432 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2433 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2434 .connector_type = DRM_MODE_CONNECTOR_DPI, 2435 }; 2436 2437 static const struct display_timing logictechno_lt170410_2whc_timing = { 2438 .pixelclock = { 68900000, 71100000, 73400000 }, 2439 .hactive = { 1280, 1280, 1280 }, 2440 .hfront_porch = { 23, 60, 71 }, 2441 .hback_porch = { 23, 60, 71 }, 2442 .hsync_len = { 15, 40, 47 }, 2443 .vactive = { 800, 800, 800 }, 2444 .vfront_porch = { 5, 7, 10 }, 2445 .vback_porch = { 5, 7, 10 }, 2446 .vsync_len = { 6, 9, 12 }, 2447 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2448 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2449 DISPLAY_FLAGS_SYNC_POSEDGE, 2450 }; 2451 2452 static const struct panel_desc logictechno_lt170410_2whc = { 2453 .timings = &logictechno_lt170410_2whc_timing, 2454 .num_timings = 1, 2455 .size = { 2456 .width = 217, 2457 .height = 136, 2458 }, 2459 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2460 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2461 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2462 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2464 }; 2465 2466 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2467 .clock = 30400, 2468 .hdisplay = 800, 2469 .hsync_start = 800 + 0, 2470 .hsync_end = 800 + 1, 2471 .htotal = 800 + 0 + 1 + 160, 2472 .vdisplay = 480, 2473 .vsync_start = 480 + 0, 2474 .vsync_end = 480 + 48 + 1, 2475 .vtotal = 480 + 48 + 1 + 0, 2476 .vrefresh = 60, 2477 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2478 }; 2479 2480 static const struct drm_display_mode logicpd_type_28_mode = { 2481 .clock = 9107, 2482 .hdisplay = 480, 2483 .hsync_start = 480 + 3, 2484 .hsync_end = 480 + 3 + 42, 2485 .htotal = 480 + 3 + 42 + 2, 2486 2487 .vdisplay = 272, 2488 .vsync_start = 272 + 2, 2489 .vsync_end = 272 + 2 + 11, 2490 .vtotal = 272 + 2 + 11 + 3, 2491 .vrefresh = 60, 2492 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2493 }; 2494 2495 static const struct panel_desc logicpd_type_28 = { 2496 .modes = &logicpd_type_28_mode, 2497 .num_modes = 1, 2498 .bpc = 8, 2499 .size = { 2500 .width = 105, 2501 .height = 67, 2502 }, 2503 .delay = { 2504 .prepare = 200, 2505 .enable = 200, 2506 .unprepare = 200, 2507 .disable = 200, 2508 }, 2509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2510 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2511 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2512 .connector_type = DRM_MODE_CONNECTOR_DPI, 2513 }; 2514 2515 static const struct panel_desc mitsubishi_aa070mc01 = { 2516 .modes = &mitsubishi_aa070mc01_mode, 2517 .num_modes = 1, 2518 .bpc = 8, 2519 .size = { 2520 .width = 152, 2521 .height = 91, 2522 }, 2523 2524 .delay = { 2525 .enable = 200, 2526 .unprepare = 200, 2527 .disable = 400, 2528 }, 2529 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2530 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2531 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2532 }; 2533 2534 static const struct display_timing nec_nl12880bc20_05_timing = { 2535 .pixelclock = { 67000000, 71000000, 75000000 }, 2536 .hactive = { 1280, 1280, 1280 }, 2537 .hfront_porch = { 2, 30, 30 }, 2538 .hback_porch = { 6, 100, 100 }, 2539 .hsync_len = { 2, 30, 30 }, 2540 .vactive = { 800, 800, 800 }, 2541 .vfront_porch = { 5, 5, 5 }, 2542 .vback_porch = { 11, 11, 11 }, 2543 .vsync_len = { 7, 7, 7 }, 2544 }; 2545 2546 static const struct panel_desc nec_nl12880bc20_05 = { 2547 .timings = &nec_nl12880bc20_05_timing, 2548 .num_timings = 1, 2549 .bpc = 8, 2550 .size = { 2551 .width = 261, 2552 .height = 163, 2553 }, 2554 .delay = { 2555 .enable = 50, 2556 .disable = 50, 2557 }, 2558 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2559 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2560 }; 2561 2562 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2563 .clock = 10870, 2564 .hdisplay = 480, 2565 .hsync_start = 480 + 2, 2566 .hsync_end = 480 + 2 + 41, 2567 .htotal = 480 + 2 + 41 + 2, 2568 .vdisplay = 272, 2569 .vsync_start = 272 + 2, 2570 .vsync_end = 272 + 2 + 4, 2571 .vtotal = 272 + 2 + 4 + 2, 2572 .vrefresh = 74, 2573 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2574 }; 2575 2576 static const struct panel_desc nec_nl4827hc19_05b = { 2577 .modes = &nec_nl4827hc19_05b_mode, 2578 .num_modes = 1, 2579 .bpc = 8, 2580 .size = { 2581 .width = 95, 2582 .height = 54, 2583 }, 2584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2585 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2586 }; 2587 2588 static const struct drm_display_mode netron_dy_e231732_mode = { 2589 .clock = 66000, 2590 .hdisplay = 1024, 2591 .hsync_start = 1024 + 160, 2592 .hsync_end = 1024 + 160 + 70, 2593 .htotal = 1024 + 160 + 70 + 90, 2594 .vdisplay = 600, 2595 .vsync_start = 600 + 127, 2596 .vsync_end = 600 + 127 + 20, 2597 .vtotal = 600 + 127 + 20 + 3, 2598 .vrefresh = 60, 2599 }; 2600 2601 static const struct panel_desc netron_dy_e231732 = { 2602 .modes = &netron_dy_e231732_mode, 2603 .num_modes = 1, 2604 .size = { 2605 .width = 154, 2606 .height = 87, 2607 }, 2608 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2609 }; 2610 2611 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2612 { 2613 .clock = 138500, 2614 .hdisplay = 1920, 2615 .hsync_start = 1920 + 48, 2616 .hsync_end = 1920 + 48 + 32, 2617 .htotal = 1920 + 48 + 32 + 80, 2618 .vdisplay = 1080, 2619 .vsync_start = 1080 + 3, 2620 .vsync_end = 1080 + 3 + 5, 2621 .vtotal = 1080 + 3 + 5 + 23, 2622 .vrefresh = 60, 2623 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2624 }, { 2625 .clock = 110920, 2626 .hdisplay = 1920, 2627 .hsync_start = 1920 + 48, 2628 .hsync_end = 1920 + 48 + 32, 2629 .htotal = 1920 + 48 + 32 + 80, 2630 .vdisplay = 1080, 2631 .vsync_start = 1080 + 3, 2632 .vsync_end = 1080 + 3 + 5, 2633 .vtotal = 1080 + 3 + 5 + 23, 2634 .vrefresh = 48, 2635 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2636 } 2637 }; 2638 2639 static const struct panel_desc neweast_wjfh116008a = { 2640 .modes = neweast_wjfh116008a_modes, 2641 .num_modes = 2, 2642 .bpc = 6, 2643 .size = { 2644 .width = 260, 2645 .height = 150, 2646 }, 2647 .delay = { 2648 .prepare = 110, 2649 .enable = 20, 2650 .unprepare = 500, 2651 }, 2652 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2653 .connector_type = DRM_MODE_CONNECTOR_eDP, 2654 }; 2655 2656 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2657 .clock = 9000, 2658 .hdisplay = 480, 2659 .hsync_start = 480 + 2, 2660 .hsync_end = 480 + 2 + 41, 2661 .htotal = 480 + 2 + 41 + 2, 2662 .vdisplay = 272, 2663 .vsync_start = 272 + 2, 2664 .vsync_end = 272 + 2 + 10, 2665 .vtotal = 272 + 2 + 10 + 2, 2666 .vrefresh = 60, 2667 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2668 }; 2669 2670 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2671 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2672 .num_modes = 1, 2673 .bpc = 8, 2674 .size = { 2675 .width = 95, 2676 .height = 54, 2677 }, 2678 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2679 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2680 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2681 .connector_type = DRM_MODE_CONNECTOR_DPI, 2682 }; 2683 2684 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2685 .pixelclock = { 130000000, 148350000, 163000000 }, 2686 .hactive = { 1920, 1920, 1920 }, 2687 .hfront_porch = { 80, 100, 100 }, 2688 .hback_porch = { 100, 120, 120 }, 2689 .hsync_len = { 50, 60, 60 }, 2690 .vactive = { 1080, 1080, 1080 }, 2691 .vfront_porch = { 12, 30, 30 }, 2692 .vback_porch = { 4, 10, 10 }, 2693 .vsync_len = { 4, 5, 5 }, 2694 }; 2695 2696 static const struct panel_desc nlt_nl192108ac18_02d = { 2697 .timings = &nlt_nl192108ac18_02d_timing, 2698 .num_timings = 1, 2699 .bpc = 8, 2700 .size = { 2701 .width = 344, 2702 .height = 194, 2703 }, 2704 .delay = { 2705 .unprepare = 500, 2706 }, 2707 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2708 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2709 }; 2710 2711 static const struct drm_display_mode nvd_9128_mode = { 2712 .clock = 29500, 2713 .hdisplay = 800, 2714 .hsync_start = 800 + 130, 2715 .hsync_end = 800 + 130 + 98, 2716 .htotal = 800 + 0 + 130 + 98, 2717 .vdisplay = 480, 2718 .vsync_start = 480 + 10, 2719 .vsync_end = 480 + 10 + 50, 2720 .vtotal = 480 + 0 + 10 + 50, 2721 }; 2722 2723 static const struct panel_desc nvd_9128 = { 2724 .modes = &nvd_9128_mode, 2725 .num_modes = 1, 2726 .bpc = 8, 2727 .size = { 2728 .width = 156, 2729 .height = 88, 2730 }, 2731 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2733 }; 2734 2735 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2736 .pixelclock = { 30000000, 30000000, 40000000 }, 2737 .hactive = { 800, 800, 800 }, 2738 .hfront_porch = { 40, 40, 40 }, 2739 .hback_porch = { 40, 40, 40 }, 2740 .hsync_len = { 1, 48, 48 }, 2741 .vactive = { 480, 480, 480 }, 2742 .vfront_porch = { 13, 13, 13 }, 2743 .vback_porch = { 29, 29, 29 }, 2744 .vsync_len = { 3, 3, 3 }, 2745 .flags = DISPLAY_FLAGS_DE_HIGH, 2746 }; 2747 2748 static const struct panel_desc okaya_rs800480t_7x0gp = { 2749 .timings = &okaya_rs800480t_7x0gp_timing, 2750 .num_timings = 1, 2751 .bpc = 6, 2752 .size = { 2753 .width = 154, 2754 .height = 87, 2755 }, 2756 .delay = { 2757 .prepare = 41, 2758 .enable = 50, 2759 .unprepare = 41, 2760 .disable = 50, 2761 }, 2762 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2763 }; 2764 2765 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2766 .clock = 9000, 2767 .hdisplay = 480, 2768 .hsync_start = 480 + 5, 2769 .hsync_end = 480 + 5 + 30, 2770 .htotal = 480 + 5 + 30 + 10, 2771 .vdisplay = 272, 2772 .vsync_start = 272 + 8, 2773 .vsync_end = 272 + 8 + 5, 2774 .vtotal = 272 + 8 + 5 + 3, 2775 .vrefresh = 60, 2776 }; 2777 2778 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2779 .modes = &olimex_lcd_olinuxino_43ts_mode, 2780 .num_modes = 1, 2781 .size = { 2782 .width = 95, 2783 .height = 54, 2784 }, 2785 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2786 }; 2787 2788 /* 2789 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2790 * pixel clocks, but this is the timing that was being used in the Adafruit 2791 * installation instructions. 2792 */ 2793 static const struct drm_display_mode ontat_yx700wv03_mode = { 2794 .clock = 29500, 2795 .hdisplay = 800, 2796 .hsync_start = 824, 2797 .hsync_end = 896, 2798 .htotal = 992, 2799 .vdisplay = 480, 2800 .vsync_start = 483, 2801 .vsync_end = 493, 2802 .vtotal = 500, 2803 .vrefresh = 60, 2804 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2805 }; 2806 2807 /* 2808 * Specification at: 2809 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2810 */ 2811 static const struct panel_desc ontat_yx700wv03 = { 2812 .modes = &ontat_yx700wv03_mode, 2813 .num_modes = 1, 2814 .bpc = 8, 2815 .size = { 2816 .width = 154, 2817 .height = 83, 2818 }, 2819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2820 }; 2821 2822 static const struct drm_display_mode ortustech_com37h3m_mode = { 2823 .clock = 22230, 2824 .hdisplay = 480, 2825 .hsync_start = 480 + 40, 2826 .hsync_end = 480 + 40 + 10, 2827 .htotal = 480 + 40 + 10 + 40, 2828 .vdisplay = 640, 2829 .vsync_start = 640 + 4, 2830 .vsync_end = 640 + 4 + 2, 2831 .vtotal = 640 + 4 + 2 + 4, 2832 .vrefresh = 60, 2833 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2834 }; 2835 2836 static const struct panel_desc ortustech_com37h3m = { 2837 .modes = &ortustech_com37h3m_mode, 2838 .num_modes = 1, 2839 .bpc = 8, 2840 .size = { 2841 .width = 56, /* 56.16mm */ 2842 .height = 75, /* 74.88mm */ 2843 }, 2844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2846 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2847 }; 2848 2849 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2850 .clock = 25000, 2851 .hdisplay = 480, 2852 .hsync_start = 480 + 10, 2853 .hsync_end = 480 + 10 + 10, 2854 .htotal = 480 + 10 + 10 + 15, 2855 .vdisplay = 800, 2856 .vsync_start = 800 + 3, 2857 .vsync_end = 800 + 3 + 3, 2858 .vtotal = 800 + 3 + 3 + 3, 2859 .vrefresh = 60, 2860 }; 2861 2862 static const struct panel_desc ortustech_com43h4m85ulc = { 2863 .modes = &ortustech_com43h4m85ulc_mode, 2864 .num_modes = 1, 2865 .bpc = 8, 2866 .size = { 2867 .width = 56, 2868 .height = 93, 2869 }, 2870 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2872 .connector_type = DRM_MODE_CONNECTOR_DPI, 2873 }; 2874 2875 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2876 .clock = 33000, 2877 .hdisplay = 800, 2878 .hsync_start = 800 + 210, 2879 .hsync_end = 800 + 210 + 30, 2880 .htotal = 800 + 210 + 30 + 16, 2881 .vdisplay = 480, 2882 .vsync_start = 480 + 22, 2883 .vsync_end = 480 + 22 + 13, 2884 .vtotal = 480 + 22 + 13 + 10, 2885 .vrefresh = 60, 2886 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2887 }; 2888 2889 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2890 .modes = &osddisplays_osd070t1718_19ts_mode, 2891 .num_modes = 1, 2892 .bpc = 8, 2893 .size = { 2894 .width = 152, 2895 .height = 91, 2896 }, 2897 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2898 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2899 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2900 .connector_type = DRM_MODE_CONNECTOR_DPI, 2901 }; 2902 2903 static const struct drm_display_mode pda_91_00156_a0_mode = { 2904 .clock = 33300, 2905 .hdisplay = 800, 2906 .hsync_start = 800 + 1, 2907 .hsync_end = 800 + 1 + 64, 2908 .htotal = 800 + 1 + 64 + 64, 2909 .vdisplay = 480, 2910 .vsync_start = 480 + 1, 2911 .vsync_end = 480 + 1 + 23, 2912 .vtotal = 480 + 1 + 23 + 22, 2913 .vrefresh = 60, 2914 }; 2915 2916 static const struct panel_desc pda_91_00156_a0 = { 2917 .modes = &pda_91_00156_a0_mode, 2918 .num_modes = 1, 2919 .size = { 2920 .width = 152, 2921 .height = 91, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2924 }; 2925 2926 2927 static const struct drm_display_mode qd43003c0_40_mode = { 2928 .clock = 9000, 2929 .hdisplay = 480, 2930 .hsync_start = 480 + 8, 2931 .hsync_end = 480 + 8 + 4, 2932 .htotal = 480 + 8 + 4 + 39, 2933 .vdisplay = 272, 2934 .vsync_start = 272 + 4, 2935 .vsync_end = 272 + 4 + 10, 2936 .vtotal = 272 + 4 + 10 + 2, 2937 .vrefresh = 60, 2938 }; 2939 2940 static const struct panel_desc qd43003c0_40 = { 2941 .modes = &qd43003c0_40_mode, 2942 .num_modes = 1, 2943 .bpc = 8, 2944 .size = { 2945 .width = 95, 2946 .height = 53, 2947 }, 2948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2949 }; 2950 2951 static const struct display_timing rocktech_rk070er9427_timing = { 2952 .pixelclock = { 26400000, 33300000, 46800000 }, 2953 .hactive = { 800, 800, 800 }, 2954 .hfront_porch = { 16, 210, 354 }, 2955 .hback_porch = { 46, 46, 46 }, 2956 .hsync_len = { 1, 1, 1 }, 2957 .vactive = { 480, 480, 480 }, 2958 .vfront_porch = { 7, 22, 147 }, 2959 .vback_porch = { 23, 23, 23 }, 2960 .vsync_len = { 1, 1, 1 }, 2961 .flags = DISPLAY_FLAGS_DE_HIGH, 2962 }; 2963 2964 static const struct panel_desc rocktech_rk070er9427 = { 2965 .timings = &rocktech_rk070er9427_timing, 2966 .num_timings = 1, 2967 .bpc = 6, 2968 .size = { 2969 .width = 154, 2970 .height = 86, 2971 }, 2972 .delay = { 2973 .prepare = 41, 2974 .enable = 50, 2975 .unprepare = 41, 2976 .disable = 50, 2977 }, 2978 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2979 }; 2980 2981 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2982 .clock = 71100, 2983 .hdisplay = 1280, 2984 .hsync_start = 1280 + 48, 2985 .hsync_end = 1280 + 48 + 32, 2986 .htotal = 1280 + 48 + 32 + 80, 2987 .vdisplay = 800, 2988 .vsync_start = 800 + 2, 2989 .vsync_end = 800 + 2 + 5, 2990 .vtotal = 800 + 2 + 5 + 16, 2991 .vrefresh = 60, 2992 }; 2993 2994 static const struct panel_desc rocktech_rk101ii01d_ct = { 2995 .modes = &rocktech_rk101ii01d_ct_mode, 2996 .num_modes = 1, 2997 .size = { 2998 .width = 217, 2999 .height = 136, 3000 }, 3001 .delay = { 3002 .prepare = 50, 3003 .disable = 50, 3004 }, 3005 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3006 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3007 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3008 }; 3009 3010 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3011 .clock = 271560, 3012 .hdisplay = 2560, 3013 .hsync_start = 2560 + 48, 3014 .hsync_end = 2560 + 48 + 32, 3015 .htotal = 2560 + 48 + 32 + 80, 3016 .vdisplay = 1600, 3017 .vsync_start = 1600 + 2, 3018 .vsync_end = 1600 + 2 + 5, 3019 .vtotal = 1600 + 2 + 5 + 57, 3020 .vrefresh = 60, 3021 }; 3022 3023 static const struct panel_desc samsung_lsn122dl01_c01 = { 3024 .modes = &samsung_lsn122dl01_c01_mode, 3025 .num_modes = 1, 3026 .size = { 3027 .width = 263, 3028 .height = 164, 3029 }, 3030 }; 3031 3032 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3033 .clock = 54030, 3034 .hdisplay = 1024, 3035 .hsync_start = 1024 + 24, 3036 .hsync_end = 1024 + 24 + 136, 3037 .htotal = 1024 + 24 + 136 + 160, 3038 .vdisplay = 600, 3039 .vsync_start = 600 + 3, 3040 .vsync_end = 600 + 3 + 6, 3041 .vtotal = 600 + 3 + 6 + 61, 3042 .vrefresh = 60, 3043 }; 3044 3045 static const struct panel_desc samsung_ltn101nt05 = { 3046 .modes = &samsung_ltn101nt05_mode, 3047 .num_modes = 1, 3048 .bpc = 6, 3049 .size = { 3050 .width = 223, 3051 .height = 125, 3052 }, 3053 }; 3054 3055 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3056 .clock = 76300, 3057 .hdisplay = 1366, 3058 .hsync_start = 1366 + 64, 3059 .hsync_end = 1366 + 64 + 48, 3060 .htotal = 1366 + 64 + 48 + 128, 3061 .vdisplay = 768, 3062 .vsync_start = 768 + 2, 3063 .vsync_end = 768 + 2 + 5, 3064 .vtotal = 768 + 2 + 5 + 17, 3065 .vrefresh = 60, 3066 }; 3067 3068 static const struct panel_desc samsung_ltn140at29_301 = { 3069 .modes = &samsung_ltn140at29_301_mode, 3070 .num_modes = 1, 3071 .bpc = 6, 3072 .size = { 3073 .width = 320, 3074 .height = 187, 3075 }, 3076 }; 3077 3078 static const struct display_timing satoz_sat050at40h12r2_timing = { 3079 .pixelclock = {33300000, 33300000, 50000000}, 3080 .hactive = {800, 800, 800}, 3081 .hfront_porch = {16, 210, 354}, 3082 .hback_porch = {46, 46, 46}, 3083 .hsync_len = {1, 1, 40}, 3084 .vactive = {480, 480, 480}, 3085 .vfront_porch = {7, 22, 147}, 3086 .vback_porch = {23, 23, 23}, 3087 .vsync_len = {1, 1, 20}, 3088 }; 3089 3090 static const struct panel_desc satoz_sat050at40h12r2 = { 3091 .timings = &satoz_sat050at40h12r2_timing, 3092 .num_timings = 1, 3093 .bpc = 8, 3094 .size = { 3095 .width = 108, 3096 .height = 65, 3097 }, 3098 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3100 }; 3101 3102 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3103 .clock = 168480, 3104 .hdisplay = 1920, 3105 .hsync_start = 1920 + 48, 3106 .hsync_end = 1920 + 48 + 32, 3107 .htotal = 1920 + 48 + 32 + 80, 3108 .vdisplay = 1280, 3109 .vsync_start = 1280 + 3, 3110 .vsync_end = 1280 + 3 + 10, 3111 .vtotal = 1280 + 3 + 10 + 57, 3112 .vrefresh = 60, 3113 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3114 }; 3115 3116 static const struct panel_desc sharp_ld_d5116z01b = { 3117 .modes = &sharp_ld_d5116z01b_mode, 3118 .num_modes = 1, 3119 .bpc = 8, 3120 .size = { 3121 .width = 260, 3122 .height = 120, 3123 }, 3124 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3125 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3126 }; 3127 3128 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3129 .clock = 33260, 3130 .hdisplay = 800, 3131 .hsync_start = 800 + 64, 3132 .hsync_end = 800 + 64 + 128, 3133 .htotal = 800 + 64 + 128 + 64, 3134 .vdisplay = 480, 3135 .vsync_start = 480 + 8, 3136 .vsync_end = 480 + 8 + 2, 3137 .vtotal = 480 + 8 + 2 + 35, 3138 .vrefresh = 60, 3139 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3140 }; 3141 3142 static const struct panel_desc sharp_lq070y3dg3b = { 3143 .modes = &sharp_lq070y3dg3b_mode, 3144 .num_modes = 1, 3145 .bpc = 8, 3146 .size = { 3147 .width = 152, /* 152.4mm */ 3148 .height = 91, /* 91.4mm */ 3149 }, 3150 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3151 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 3152 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3153 }; 3154 3155 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3156 .clock = 5500, 3157 .hdisplay = 240, 3158 .hsync_start = 240 + 16, 3159 .hsync_end = 240 + 16 + 7, 3160 .htotal = 240 + 16 + 7 + 5, 3161 .vdisplay = 320, 3162 .vsync_start = 320 + 9, 3163 .vsync_end = 320 + 9 + 1, 3164 .vtotal = 320 + 9 + 1 + 7, 3165 .vrefresh = 60, 3166 }; 3167 3168 static const struct panel_desc sharp_lq035q7db03 = { 3169 .modes = &sharp_lq035q7db03_mode, 3170 .num_modes = 1, 3171 .bpc = 6, 3172 .size = { 3173 .width = 54, 3174 .height = 72, 3175 }, 3176 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3177 }; 3178 3179 static const struct display_timing sharp_lq101k1ly04_timing = { 3180 .pixelclock = { 60000000, 65000000, 80000000 }, 3181 .hactive = { 1280, 1280, 1280 }, 3182 .hfront_porch = { 20, 20, 20 }, 3183 .hback_porch = { 20, 20, 20 }, 3184 .hsync_len = { 10, 10, 10 }, 3185 .vactive = { 800, 800, 800 }, 3186 .vfront_porch = { 4, 4, 4 }, 3187 .vback_porch = { 4, 4, 4 }, 3188 .vsync_len = { 4, 4, 4 }, 3189 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3190 }; 3191 3192 static const struct panel_desc sharp_lq101k1ly04 = { 3193 .timings = &sharp_lq101k1ly04_timing, 3194 .num_timings = 1, 3195 .bpc = 8, 3196 .size = { 3197 .width = 217, 3198 .height = 136, 3199 }, 3200 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3201 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3202 }; 3203 3204 static const struct display_timing sharp_lq123p1jx31_timing = { 3205 .pixelclock = { 252750000, 252750000, 266604720 }, 3206 .hactive = { 2400, 2400, 2400 }, 3207 .hfront_porch = { 48, 48, 48 }, 3208 .hback_porch = { 80, 80, 84 }, 3209 .hsync_len = { 32, 32, 32 }, 3210 .vactive = { 1600, 1600, 1600 }, 3211 .vfront_porch = { 3, 3, 3 }, 3212 .vback_porch = { 33, 33, 120 }, 3213 .vsync_len = { 10, 10, 10 }, 3214 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3215 }; 3216 3217 static const struct panel_desc sharp_lq123p1jx31 = { 3218 .timings = &sharp_lq123p1jx31_timing, 3219 .num_timings = 1, 3220 .bpc = 8, 3221 .size = { 3222 .width = 259, 3223 .height = 173, 3224 }, 3225 .delay = { 3226 .prepare = 110, 3227 .enable = 50, 3228 .unprepare = 550, 3229 }, 3230 }; 3231 3232 static const struct display_timing sharp_ls020b1dd01d_timing = { 3233 .pixelclock = { 2000000, 4200000, 5000000 }, 3234 .hactive = { 240, 240, 240 }, 3235 .hfront_porch = { 66, 66, 66 }, 3236 .hback_porch = { 1, 1, 1 }, 3237 .hsync_len = { 1, 1, 1 }, 3238 .vactive = { 160, 160, 160 }, 3239 .vfront_porch = { 52, 52, 52 }, 3240 .vback_porch = { 6, 6, 6 }, 3241 .vsync_len = { 10, 10, 10 }, 3242 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3243 }; 3244 3245 static const struct panel_desc sharp_ls020b1dd01d = { 3246 .timings = &sharp_ls020b1dd01d_timing, 3247 .num_timings = 1, 3248 .bpc = 6, 3249 .size = { 3250 .width = 42, 3251 .height = 28, 3252 }, 3253 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3254 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3255 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3256 | DRM_BUS_FLAG_SHARP_SIGNALS, 3257 }; 3258 3259 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3260 .clock = 33300, 3261 .hdisplay = 800, 3262 .hsync_start = 800 + 1, 3263 .hsync_end = 800 + 1 + 64, 3264 .htotal = 800 + 1 + 64 + 64, 3265 .vdisplay = 480, 3266 .vsync_start = 480 + 1, 3267 .vsync_end = 480 + 1 + 23, 3268 .vtotal = 480 + 1 + 23 + 22, 3269 .vrefresh = 60, 3270 }; 3271 3272 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3273 .modes = &shelly_sca07010_bfn_lnn_mode, 3274 .num_modes = 1, 3275 .size = { 3276 .width = 152, 3277 .height = 91, 3278 }, 3279 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3280 }; 3281 3282 static const struct drm_display_mode starry_kr070pe2t_mode = { 3283 .clock = 33000, 3284 .hdisplay = 800, 3285 .hsync_start = 800 + 209, 3286 .hsync_end = 800 + 209 + 1, 3287 .htotal = 800 + 209 + 1 + 45, 3288 .vdisplay = 480, 3289 .vsync_start = 480 + 22, 3290 .vsync_end = 480 + 22 + 1, 3291 .vtotal = 480 + 22 + 1 + 22, 3292 .vrefresh = 60, 3293 }; 3294 3295 static const struct panel_desc starry_kr070pe2t = { 3296 .modes = &starry_kr070pe2t_mode, 3297 .num_modes = 1, 3298 .bpc = 8, 3299 .size = { 3300 .width = 152, 3301 .height = 86, 3302 }, 3303 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3304 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3306 }; 3307 3308 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3309 .clock = 147000, 3310 .hdisplay = 1920, 3311 .hsync_start = 1920 + 16, 3312 .hsync_end = 1920 + 16 + 16, 3313 .htotal = 1920 + 16 + 16 + 32, 3314 .vdisplay = 1200, 3315 .vsync_start = 1200 + 15, 3316 .vsync_end = 1200 + 15 + 2, 3317 .vtotal = 1200 + 15 + 2 + 18, 3318 .vrefresh = 60, 3319 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3320 }; 3321 3322 static const struct panel_desc starry_kr122ea0sra = { 3323 .modes = &starry_kr122ea0sra_mode, 3324 .num_modes = 1, 3325 .size = { 3326 .width = 263, 3327 .height = 164, 3328 }, 3329 .delay = { 3330 .prepare = 10 + 200, 3331 .enable = 50, 3332 .unprepare = 10 + 500, 3333 }, 3334 }; 3335 3336 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3337 .clock = 30000, 3338 .hdisplay = 800, 3339 .hsync_start = 800 + 39, 3340 .hsync_end = 800 + 39 + 47, 3341 .htotal = 800 + 39 + 47 + 39, 3342 .vdisplay = 480, 3343 .vsync_start = 480 + 13, 3344 .vsync_end = 480 + 13 + 2, 3345 .vtotal = 480 + 13 + 2 + 29, 3346 .vrefresh = 62, 3347 }; 3348 3349 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3350 .modes = &tfc_s9700rtwv43tr_01b_mode, 3351 .num_modes = 1, 3352 .bpc = 8, 3353 .size = { 3354 .width = 155, 3355 .height = 90, 3356 }, 3357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3359 }; 3360 3361 static const struct display_timing tianma_tm070jdhg30_timing = { 3362 .pixelclock = { 62600000, 68200000, 78100000 }, 3363 .hactive = { 1280, 1280, 1280 }, 3364 .hfront_porch = { 15, 64, 159 }, 3365 .hback_porch = { 5, 5, 5 }, 3366 .hsync_len = { 1, 1, 256 }, 3367 .vactive = { 800, 800, 800 }, 3368 .vfront_porch = { 3, 40, 99 }, 3369 .vback_porch = { 2, 2, 2 }, 3370 .vsync_len = { 1, 1, 128 }, 3371 .flags = DISPLAY_FLAGS_DE_HIGH, 3372 }; 3373 3374 static const struct panel_desc tianma_tm070jdhg30 = { 3375 .timings = &tianma_tm070jdhg30_timing, 3376 .num_timings = 1, 3377 .bpc = 8, 3378 .size = { 3379 .width = 151, 3380 .height = 95, 3381 }, 3382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3383 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3384 }; 3385 3386 static const struct display_timing tianma_tm070rvhg71_timing = { 3387 .pixelclock = { 27700000, 29200000, 39600000 }, 3388 .hactive = { 800, 800, 800 }, 3389 .hfront_porch = { 12, 40, 212 }, 3390 .hback_porch = { 88, 88, 88 }, 3391 .hsync_len = { 1, 1, 40 }, 3392 .vactive = { 480, 480, 480 }, 3393 .vfront_porch = { 1, 13, 88 }, 3394 .vback_porch = { 32, 32, 32 }, 3395 .vsync_len = { 1, 1, 3 }, 3396 .flags = DISPLAY_FLAGS_DE_HIGH, 3397 }; 3398 3399 static const struct panel_desc tianma_tm070rvhg71 = { 3400 .timings = &tianma_tm070rvhg71_timing, 3401 .num_timings = 1, 3402 .bpc = 8, 3403 .size = { 3404 .width = 154, 3405 .height = 86, 3406 }, 3407 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3408 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3409 }; 3410 3411 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3412 { 3413 .clock = 10000, 3414 .hdisplay = 320, 3415 .hsync_start = 320 + 50, 3416 .hsync_end = 320 + 50 + 6, 3417 .htotal = 320 + 50 + 6 + 38, 3418 .vdisplay = 240, 3419 .vsync_start = 240 + 3, 3420 .vsync_end = 240 + 3 + 1, 3421 .vtotal = 240 + 3 + 1 + 17, 3422 .vrefresh = 60, 3423 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3424 }, 3425 }; 3426 3427 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3428 .modes = ti_nspire_cx_lcd_mode, 3429 .num_modes = 1, 3430 .bpc = 8, 3431 .size = { 3432 .width = 65, 3433 .height = 49, 3434 }, 3435 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3436 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3437 }; 3438 3439 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3440 { 3441 .clock = 10000, 3442 .hdisplay = 320, 3443 .hsync_start = 320 + 6, 3444 .hsync_end = 320 + 6 + 6, 3445 .htotal = 320 + 6 + 6 + 6, 3446 .vdisplay = 240, 3447 .vsync_start = 240 + 0, 3448 .vsync_end = 240 + 0 + 1, 3449 .vtotal = 240 + 0 + 1 + 0, 3450 .vrefresh = 60, 3451 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3452 }, 3453 }; 3454 3455 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3456 .modes = ti_nspire_classic_lcd_mode, 3457 .num_modes = 1, 3458 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3459 .bpc = 8, 3460 .size = { 3461 .width = 71, 3462 .height = 53, 3463 }, 3464 /* This is the grayscale bus format */ 3465 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3466 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3467 }; 3468 3469 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3470 .clock = 79500, 3471 .hdisplay = 1280, 3472 .hsync_start = 1280 + 192, 3473 .hsync_end = 1280 + 192 + 128, 3474 .htotal = 1280 + 192 + 128 + 64, 3475 .vdisplay = 768, 3476 .vsync_start = 768 + 20, 3477 .vsync_end = 768 + 20 + 7, 3478 .vtotal = 768 + 20 + 7 + 3, 3479 .vrefresh = 60, 3480 }; 3481 3482 static const struct panel_desc toshiba_lt089ac29000 = { 3483 .modes = &toshiba_lt089ac29000_mode, 3484 .num_modes = 1, 3485 .size = { 3486 .width = 194, 3487 .height = 116, 3488 }, 3489 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3492 }; 3493 3494 static const struct drm_display_mode tpk_f07a_0102_mode = { 3495 .clock = 33260, 3496 .hdisplay = 800, 3497 .hsync_start = 800 + 40, 3498 .hsync_end = 800 + 40 + 128, 3499 .htotal = 800 + 40 + 128 + 88, 3500 .vdisplay = 480, 3501 .vsync_start = 480 + 10, 3502 .vsync_end = 480 + 10 + 2, 3503 .vtotal = 480 + 10 + 2 + 33, 3504 .vrefresh = 60, 3505 }; 3506 3507 static const struct panel_desc tpk_f07a_0102 = { 3508 .modes = &tpk_f07a_0102_mode, 3509 .num_modes = 1, 3510 .size = { 3511 .width = 152, 3512 .height = 91, 3513 }, 3514 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3515 }; 3516 3517 static const struct drm_display_mode tpk_f10a_0102_mode = { 3518 .clock = 45000, 3519 .hdisplay = 1024, 3520 .hsync_start = 1024 + 176, 3521 .hsync_end = 1024 + 176 + 5, 3522 .htotal = 1024 + 176 + 5 + 88, 3523 .vdisplay = 600, 3524 .vsync_start = 600 + 20, 3525 .vsync_end = 600 + 20 + 5, 3526 .vtotal = 600 + 20 + 5 + 25, 3527 .vrefresh = 60, 3528 }; 3529 3530 static const struct panel_desc tpk_f10a_0102 = { 3531 .modes = &tpk_f10a_0102_mode, 3532 .num_modes = 1, 3533 .size = { 3534 .width = 223, 3535 .height = 125, 3536 }, 3537 }; 3538 3539 static const struct display_timing urt_umsh_8596md_timing = { 3540 .pixelclock = { 33260000, 33260000, 33260000 }, 3541 .hactive = { 800, 800, 800 }, 3542 .hfront_porch = { 41, 41, 41 }, 3543 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3544 .hsync_len = { 71, 128, 128 }, 3545 .vactive = { 480, 480, 480 }, 3546 .vfront_porch = { 10, 10, 10 }, 3547 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3548 .vsync_len = { 2, 2, 2 }, 3549 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3550 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3551 }; 3552 3553 static const struct panel_desc urt_umsh_8596md_lvds = { 3554 .timings = &urt_umsh_8596md_timing, 3555 .num_timings = 1, 3556 .bpc = 6, 3557 .size = { 3558 .width = 152, 3559 .height = 91, 3560 }, 3561 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3562 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3563 }; 3564 3565 static const struct panel_desc urt_umsh_8596md_parallel = { 3566 .timings = &urt_umsh_8596md_timing, 3567 .num_timings = 1, 3568 .bpc = 6, 3569 .size = { 3570 .width = 152, 3571 .height = 91, 3572 }, 3573 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3574 }; 3575 3576 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3577 .clock = 33333, 3578 .hdisplay = 800, 3579 .hsync_start = 800 + 210, 3580 .hsync_end = 800 + 210 + 20, 3581 .htotal = 800 + 210 + 20 + 46, 3582 .vdisplay = 480, 3583 .vsync_start = 480 + 22, 3584 .vsync_end = 480 + 22 + 10, 3585 .vtotal = 480 + 22 + 10 + 23, 3586 .vrefresh = 60, 3587 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3588 }; 3589 3590 static const struct panel_desc vl050_8048nt_c01 = { 3591 .modes = &vl050_8048nt_c01_mode, 3592 .num_modes = 1, 3593 .bpc = 8, 3594 .size = { 3595 .width = 120, 3596 .height = 76, 3597 }, 3598 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3599 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3600 }; 3601 3602 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3603 .clock = 6410, 3604 .hdisplay = 320, 3605 .hsync_start = 320 + 20, 3606 .hsync_end = 320 + 20 + 30, 3607 .htotal = 320 + 20 + 30 + 38, 3608 .vdisplay = 240, 3609 .vsync_start = 240 + 4, 3610 .vsync_end = 240 + 4 + 3, 3611 .vtotal = 240 + 4 + 3 + 15, 3612 .vrefresh = 60, 3613 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3614 }; 3615 3616 static const struct panel_desc winstar_wf35ltiacd = { 3617 .modes = &winstar_wf35ltiacd_mode, 3618 .num_modes = 1, 3619 .bpc = 8, 3620 .size = { 3621 .width = 70, 3622 .height = 53, 3623 }, 3624 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3625 }; 3626 3627 static const struct drm_display_mode arm_rtsm_mode[] = { 3628 { 3629 .clock = 65000, 3630 .hdisplay = 1024, 3631 .hsync_start = 1024 + 24, 3632 .hsync_end = 1024 + 24 + 136, 3633 .htotal = 1024 + 24 + 136 + 160, 3634 .vdisplay = 768, 3635 .vsync_start = 768 + 3, 3636 .vsync_end = 768 + 3 + 6, 3637 .vtotal = 768 + 3 + 6 + 29, 3638 .vrefresh = 60, 3639 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3640 }, 3641 }; 3642 3643 static const struct panel_desc arm_rtsm = { 3644 .modes = arm_rtsm_mode, 3645 .num_modes = 1, 3646 .bpc = 8, 3647 .size = { 3648 .width = 400, 3649 .height = 300, 3650 }, 3651 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3652 }; 3653 3654 static const struct of_device_id platform_of_match[] = { 3655 { 3656 .compatible = "ampire,am-480272h3tmqw-t01h", 3657 .data = &ire_am_480272h3tmqw_t01h, 3658 }, { 3659 .compatible = "ampire,am800480r3tmqwa1h", 3660 .data = &ire_am800480r3tmqwa1h, 3661 }, { 3662 .compatible = "arm,rtsm-display", 3663 .data = &arm_rtsm, 3664 }, { 3665 .compatible = "armadeus,st0700-adapt", 3666 .data = &armadeus_st0700_adapt, 3667 }, { 3668 .compatible = "auo,b101aw03", 3669 .data = &auo_b101aw03, 3670 }, { 3671 .compatible = "auo,b101ean01", 3672 .data = &auo_b101ean01, 3673 }, { 3674 .compatible = "auo,b101xtn01", 3675 .data = &auo_b101xtn01, 3676 }, { 3677 .compatible = "auo,b116xa01", 3678 .data = &auo_b116xak01, 3679 }, { 3680 .compatible = "auo,b116xw03", 3681 .data = &auo_b116xw03, 3682 }, { 3683 .compatible = "auo,b133htn01", 3684 .data = &auo_b133htn01, 3685 }, { 3686 .compatible = "auo,b133xtn01", 3687 .data = &auo_b133xtn01, 3688 }, { 3689 .compatible = "auo,g070vvn01", 3690 .data = &auo_g070vvn01, 3691 }, { 3692 .compatible = "auo,g101evn010", 3693 .data = &auo_g101evn010, 3694 }, { 3695 .compatible = "auo,g104sn02", 3696 .data = &auo_g104sn02, 3697 }, { 3698 .compatible = "auo,g121ean01", 3699 .data = &auo_g121ean01, 3700 }, { 3701 .compatible = "auo,g133han01", 3702 .data = &auo_g133han01, 3703 }, { 3704 .compatible = "auo,g156xtn01", 3705 .data = &auo_g156xtn01, 3706 }, { 3707 .compatible = "auo,g185han01", 3708 .data = &auo_g185han01, 3709 }, { 3710 .compatible = "auo,g190ean01", 3711 .data = &auo_g190ean01, 3712 }, { 3713 .compatible = "auo,p320hvn03", 3714 .data = &auo_p320hvn03, 3715 }, { 3716 .compatible = "auo,t215hvn01", 3717 .data = &auo_t215hvn01, 3718 }, { 3719 .compatible = "avic,tm070ddh03", 3720 .data = &avic_tm070ddh03, 3721 }, { 3722 .compatible = "bananapi,s070wv20-ct16", 3723 .data = &bananapi_s070wv20_ct16, 3724 }, { 3725 .compatible = "boe,hv070wsa-100", 3726 .data = &boe_hv070wsa 3727 }, { 3728 .compatible = "boe,nv101wxmn51", 3729 .data = &boe_nv101wxmn51, 3730 }, { 3731 .compatible = "boe,nv133fhm-n61", 3732 .data = &boe_nv133fhm_n61, 3733 }, { 3734 .compatible = "boe,nv133fhm-n62", 3735 .data = &boe_nv133fhm_n61, 3736 }, { 3737 .compatible = "boe,nv140fhmn49", 3738 .data = &boe_nv140fhmn49, 3739 }, { 3740 .compatible = "cdtech,s043wq26h-ct7", 3741 .data = &cdtech_s043wq26h_ct7, 3742 }, { 3743 .compatible = "cdtech,s070wv95-ct16", 3744 .data = &cdtech_s070wv95_ct16, 3745 }, { 3746 .compatible = "chunghwa,claa070wp03xg", 3747 .data = &chunghwa_claa070wp03xg, 3748 }, { 3749 .compatible = "chunghwa,claa101wa01a", 3750 .data = &chunghwa_claa101wa01a 3751 }, { 3752 .compatible = "chunghwa,claa101wb01", 3753 .data = &chunghwa_claa101wb01 3754 }, { 3755 .compatible = "dataimage,scf0700c48ggu18", 3756 .data = &dataimage_scf0700c48ggu18, 3757 }, { 3758 .compatible = "dlc,dlc0700yzg-1", 3759 .data = &dlc_dlc0700yzg_1, 3760 }, { 3761 .compatible = "dlc,dlc1010gig", 3762 .data = &dlc_dlc1010gig, 3763 }, { 3764 .compatible = "edt,et035012dm6", 3765 .data = &edt_et035012dm6, 3766 }, { 3767 .compatible = "edt,etm043080dh6gp", 3768 .data = &edt_etm043080dh6gp, 3769 }, { 3770 .compatible = "edt,etm0430g0dh6", 3771 .data = &edt_etm0430g0dh6, 3772 }, { 3773 .compatible = "edt,et057090dhu", 3774 .data = &edt_et057090dhu, 3775 }, { 3776 .compatible = "edt,et070080dh6", 3777 .data = &edt_etm0700g0dh6, 3778 }, { 3779 .compatible = "edt,etm0700g0dh6", 3780 .data = &edt_etm0700g0dh6, 3781 }, { 3782 .compatible = "edt,etm0700g0bdh6", 3783 .data = &edt_etm0700g0bdh6, 3784 }, { 3785 .compatible = "edt,etm0700g0edh6", 3786 .data = &edt_etm0700g0bdh6, 3787 }, { 3788 .compatible = "evervision,vgg804821", 3789 .data = &evervision_vgg804821, 3790 }, { 3791 .compatible = "foxlink,fl500wvr00-a0t", 3792 .data = &foxlink_fl500wvr00_a0t, 3793 }, { 3794 .compatible = "frida,frd350h54004", 3795 .data = &frida_frd350h54004, 3796 }, { 3797 .compatible = "friendlyarm,hd702e", 3798 .data = &friendlyarm_hd702e, 3799 }, { 3800 .compatible = "giantplus,gpg482739qs5", 3801 .data = &giantplus_gpg482739qs5 3802 }, { 3803 .compatible = "giantplus,gpm940b0", 3804 .data = &giantplus_gpm940b0, 3805 }, { 3806 .compatible = "hannstar,hsd070pww1", 3807 .data = &hannstar_hsd070pww1, 3808 }, { 3809 .compatible = "hannstar,hsd100pxn1", 3810 .data = &hannstar_hsd100pxn1, 3811 }, { 3812 .compatible = "hit,tx23d38vm0caa", 3813 .data = &hitachi_tx23d38vm0caa 3814 }, { 3815 .compatible = "innolux,at043tn24", 3816 .data = &innolux_at043tn24, 3817 }, { 3818 .compatible = "innolux,at070tn92", 3819 .data = &innolux_at070tn92, 3820 }, { 3821 .compatible = "innolux,g070y2-l01", 3822 .data = &innolux_g070y2_l01, 3823 }, { 3824 .compatible = "innolux,g101ice-l01", 3825 .data = &innolux_g101ice_l01 3826 }, { 3827 .compatible = "innolux,g121i1-l01", 3828 .data = &innolux_g121i1_l01 3829 }, { 3830 .compatible = "innolux,g121x1-l03", 3831 .data = &innolux_g121x1_l03, 3832 }, { 3833 .compatible = "innolux,n116bge", 3834 .data = &innolux_n116bge, 3835 }, { 3836 .compatible = "innolux,n156bge-l21", 3837 .data = &innolux_n156bge_l21, 3838 }, { 3839 .compatible = "innolux,p120zdg-bf1", 3840 .data = &innolux_p120zdg_bf1, 3841 }, { 3842 .compatible = "innolux,zj070na-01p", 3843 .data = &innolux_zj070na_01p, 3844 }, { 3845 .compatible = "ivo,m133nwf4-r0", 3846 .data = &ivo_m133nwf4_r0, 3847 }, { 3848 .compatible = "koe,tx14d24vm1bpa", 3849 .data = &koe_tx14d24vm1bpa, 3850 }, { 3851 .compatible = "koe,tx31d200vm0baa", 3852 .data = &koe_tx31d200vm0baa, 3853 }, { 3854 .compatible = "kyo,tcg121xglp", 3855 .data = &kyo_tcg121xglp, 3856 }, { 3857 .compatible = "lemaker,bl035-rgb-002", 3858 .data = &lemaker_bl035_rgb_002, 3859 }, { 3860 .compatible = "lg,lb070wv8", 3861 .data = &lg_lb070wv8, 3862 }, { 3863 .compatible = "lg,lp079qx1-sp0v", 3864 .data = &lg_lp079qx1_sp0v, 3865 }, { 3866 .compatible = "lg,lp097qx1-spa1", 3867 .data = &lg_lp097qx1_spa1, 3868 }, { 3869 .compatible = "lg,lp120up1", 3870 .data = &lg_lp120up1, 3871 }, { 3872 .compatible = "lg,lp129qe", 3873 .data = &lg_lp129qe, 3874 }, { 3875 .compatible = "logicpd,type28", 3876 .data = &logicpd_type_28, 3877 }, { 3878 .compatible = "logictechno,lt161010-2nhc", 3879 .data = &logictechno_lt161010_2nh, 3880 }, { 3881 .compatible = "logictechno,lt161010-2nhr", 3882 .data = &logictechno_lt161010_2nh, 3883 }, { 3884 .compatible = "logictechno,lt170410-2whc", 3885 .data = &logictechno_lt170410_2whc, 3886 }, { 3887 .compatible = "mitsubishi,aa070mc01-ca1", 3888 .data = &mitsubishi_aa070mc01, 3889 }, { 3890 .compatible = "nec,nl12880bc20-05", 3891 .data = &nec_nl12880bc20_05, 3892 }, { 3893 .compatible = "nec,nl4827hc19-05b", 3894 .data = &nec_nl4827hc19_05b, 3895 }, { 3896 .compatible = "netron-dy,e231732", 3897 .data = &netron_dy_e231732, 3898 }, { 3899 .compatible = "neweast,wjfh116008a", 3900 .data = &neweast_wjfh116008a, 3901 }, { 3902 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3903 .data = &newhaven_nhd_43_480272ef_atxl, 3904 }, { 3905 .compatible = "nlt,nl192108ac18-02d", 3906 .data = &nlt_nl192108ac18_02d, 3907 }, { 3908 .compatible = "nvd,9128", 3909 .data = &nvd_9128, 3910 }, { 3911 .compatible = "okaya,rs800480t-7x0gp", 3912 .data = &okaya_rs800480t_7x0gp, 3913 }, { 3914 .compatible = "olimex,lcd-olinuxino-43-ts", 3915 .data = &olimex_lcd_olinuxino_43ts, 3916 }, { 3917 .compatible = "ontat,yx700wv03", 3918 .data = &ontat_yx700wv03, 3919 }, { 3920 .compatible = "ortustech,com37h3m05dtc", 3921 .data = &ortustech_com37h3m, 3922 }, { 3923 .compatible = "ortustech,com37h3m99dtc", 3924 .data = &ortustech_com37h3m, 3925 }, { 3926 .compatible = "ortustech,com43h4m85ulc", 3927 .data = &ortustech_com43h4m85ulc, 3928 }, { 3929 .compatible = "osddisplays,osd070t1718-19ts", 3930 .data = &osddisplays_osd070t1718_19ts, 3931 }, { 3932 .compatible = "pda,91-00156-a0", 3933 .data = &pda_91_00156_a0, 3934 }, { 3935 .compatible = "qiaodian,qd43003c0-40", 3936 .data = &qd43003c0_40, 3937 }, { 3938 .compatible = "rocktech,rk070er9427", 3939 .data = &rocktech_rk070er9427, 3940 }, { 3941 .compatible = "rocktech,rk101ii01d-ct", 3942 .data = &rocktech_rk101ii01d_ct, 3943 }, { 3944 .compatible = "samsung,lsn122dl01-c01", 3945 .data = &samsung_lsn122dl01_c01, 3946 }, { 3947 .compatible = "samsung,ltn101nt05", 3948 .data = &samsung_ltn101nt05, 3949 }, { 3950 .compatible = "samsung,ltn140at29-301", 3951 .data = &samsung_ltn140at29_301, 3952 }, { 3953 .compatible = "satoz,sat050at40h12r2", 3954 .data = &satoz_sat050at40h12r2, 3955 }, { 3956 .compatible = "sharp,ld-d5116z01b", 3957 .data = &sharp_ld_d5116z01b, 3958 }, { 3959 .compatible = "sharp,lq035q7db03", 3960 .data = &sharp_lq035q7db03, 3961 }, { 3962 .compatible = "sharp,lq070y3dg3b", 3963 .data = &sharp_lq070y3dg3b, 3964 }, { 3965 .compatible = "sharp,lq101k1ly04", 3966 .data = &sharp_lq101k1ly04, 3967 }, { 3968 .compatible = "sharp,lq123p1jx31", 3969 .data = &sharp_lq123p1jx31, 3970 }, { 3971 .compatible = "sharp,ls020b1dd01d", 3972 .data = &sharp_ls020b1dd01d, 3973 }, { 3974 .compatible = "shelly,sca07010-bfn-lnn", 3975 .data = &shelly_sca07010_bfn_lnn, 3976 }, { 3977 .compatible = "starry,kr070pe2t", 3978 .data = &starry_kr070pe2t, 3979 }, { 3980 .compatible = "starry,kr122ea0sra", 3981 .data = &starry_kr122ea0sra, 3982 }, { 3983 .compatible = "tfc,s9700rtwv43tr-01b", 3984 .data = &tfc_s9700rtwv43tr_01b, 3985 }, { 3986 .compatible = "tianma,tm070jdhg30", 3987 .data = &tianma_tm070jdhg30, 3988 }, { 3989 .compatible = "tianma,tm070rvhg71", 3990 .data = &tianma_tm070rvhg71, 3991 }, { 3992 .compatible = "ti,nspire-cx-lcd-panel", 3993 .data = &ti_nspire_cx_lcd_panel, 3994 }, { 3995 .compatible = "ti,nspire-classic-lcd-panel", 3996 .data = &ti_nspire_classic_lcd_panel, 3997 }, { 3998 .compatible = "toshiba,lt089ac29000", 3999 .data = &toshiba_lt089ac29000, 4000 }, { 4001 .compatible = "tpk,f07a-0102", 4002 .data = &tpk_f07a_0102, 4003 }, { 4004 .compatible = "tpk,f10a-0102", 4005 .data = &tpk_f10a_0102, 4006 }, { 4007 .compatible = "urt,umsh-8596md-t", 4008 .data = &urt_umsh_8596md_parallel, 4009 }, { 4010 .compatible = "urt,umsh-8596md-1t", 4011 .data = &urt_umsh_8596md_parallel, 4012 }, { 4013 .compatible = "urt,umsh-8596md-7t", 4014 .data = &urt_umsh_8596md_parallel, 4015 }, { 4016 .compatible = "urt,umsh-8596md-11t", 4017 .data = &urt_umsh_8596md_lvds, 4018 }, { 4019 .compatible = "urt,umsh-8596md-19t", 4020 .data = &urt_umsh_8596md_lvds, 4021 }, { 4022 .compatible = "urt,umsh-8596md-20t", 4023 .data = &urt_umsh_8596md_parallel, 4024 }, { 4025 .compatible = "vxt,vl050-8048nt-c01", 4026 .data = &vl050_8048nt_c01, 4027 }, { 4028 .compatible = "winstar,wf35ltiacd", 4029 .data = &winstar_wf35ltiacd, 4030 }, { 4031 /* Must be the last entry */ 4032 .compatible = "panel-dpi", 4033 .data = &panel_dpi, 4034 }, { 4035 /* sentinel */ 4036 } 4037 }; 4038 MODULE_DEVICE_TABLE(of, platform_of_match); 4039 4040 static int panel_simple_platform_probe(struct platform_device *pdev) 4041 { 4042 const struct of_device_id *id; 4043 4044 id = of_match_node(platform_of_match, pdev->dev.of_node); 4045 if (!id) 4046 return -ENODEV; 4047 4048 return panel_simple_probe(&pdev->dev, id->data); 4049 } 4050 4051 static int panel_simple_platform_remove(struct platform_device *pdev) 4052 { 4053 return panel_simple_remove(&pdev->dev); 4054 } 4055 4056 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4057 { 4058 panel_simple_shutdown(&pdev->dev); 4059 } 4060 4061 static struct platform_driver panel_simple_platform_driver = { 4062 .driver = { 4063 .name = "panel-simple", 4064 .of_match_table = platform_of_match, 4065 }, 4066 .probe = panel_simple_platform_probe, 4067 .remove = panel_simple_platform_remove, 4068 .shutdown = panel_simple_platform_shutdown, 4069 }; 4070 4071 struct panel_desc_dsi { 4072 struct panel_desc desc; 4073 4074 unsigned long flags; 4075 enum mipi_dsi_pixel_format format; 4076 unsigned int lanes; 4077 }; 4078 4079 static const struct drm_display_mode auo_b080uan01_mode = { 4080 .clock = 154500, 4081 .hdisplay = 1200, 4082 .hsync_start = 1200 + 62, 4083 .hsync_end = 1200 + 62 + 4, 4084 .htotal = 1200 + 62 + 4 + 62, 4085 .vdisplay = 1920, 4086 .vsync_start = 1920 + 9, 4087 .vsync_end = 1920 + 9 + 2, 4088 .vtotal = 1920 + 9 + 2 + 8, 4089 .vrefresh = 60, 4090 }; 4091 4092 static const struct panel_desc_dsi auo_b080uan01 = { 4093 .desc = { 4094 .modes = &auo_b080uan01_mode, 4095 .num_modes = 1, 4096 .bpc = 8, 4097 .size = { 4098 .width = 108, 4099 .height = 272, 4100 }, 4101 }, 4102 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4103 .format = MIPI_DSI_FMT_RGB888, 4104 .lanes = 4, 4105 }; 4106 4107 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4108 .clock = 160000, 4109 .hdisplay = 1200, 4110 .hsync_start = 1200 + 120, 4111 .hsync_end = 1200 + 120 + 20, 4112 .htotal = 1200 + 120 + 20 + 21, 4113 .vdisplay = 1920, 4114 .vsync_start = 1920 + 21, 4115 .vsync_end = 1920 + 21 + 3, 4116 .vtotal = 1920 + 21 + 3 + 18, 4117 .vrefresh = 60, 4118 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4119 }; 4120 4121 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4122 .desc = { 4123 .modes = &boe_tv080wum_nl0_mode, 4124 .num_modes = 1, 4125 .size = { 4126 .width = 107, 4127 .height = 172, 4128 }, 4129 }, 4130 .flags = MIPI_DSI_MODE_VIDEO | 4131 MIPI_DSI_MODE_VIDEO_BURST | 4132 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4133 .format = MIPI_DSI_FMT_RGB888, 4134 .lanes = 4, 4135 }; 4136 4137 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4138 .clock = 71000, 4139 .hdisplay = 800, 4140 .hsync_start = 800 + 32, 4141 .hsync_end = 800 + 32 + 1, 4142 .htotal = 800 + 32 + 1 + 57, 4143 .vdisplay = 1280, 4144 .vsync_start = 1280 + 28, 4145 .vsync_end = 1280 + 28 + 1, 4146 .vtotal = 1280 + 28 + 1 + 14, 4147 .vrefresh = 60, 4148 }; 4149 4150 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4151 .desc = { 4152 .modes = &lg_ld070wx3_sl01_mode, 4153 .num_modes = 1, 4154 .bpc = 8, 4155 .size = { 4156 .width = 94, 4157 .height = 151, 4158 }, 4159 }, 4160 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4161 .format = MIPI_DSI_FMT_RGB888, 4162 .lanes = 4, 4163 }; 4164 4165 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4166 .clock = 67000, 4167 .hdisplay = 720, 4168 .hsync_start = 720 + 12, 4169 .hsync_end = 720 + 12 + 4, 4170 .htotal = 720 + 12 + 4 + 112, 4171 .vdisplay = 1280, 4172 .vsync_start = 1280 + 8, 4173 .vsync_end = 1280 + 8 + 4, 4174 .vtotal = 1280 + 8 + 4 + 12, 4175 .vrefresh = 60, 4176 }; 4177 4178 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4179 .desc = { 4180 .modes = &lg_lh500wx1_sd03_mode, 4181 .num_modes = 1, 4182 .bpc = 8, 4183 .size = { 4184 .width = 62, 4185 .height = 110, 4186 }, 4187 }, 4188 .flags = MIPI_DSI_MODE_VIDEO, 4189 .format = MIPI_DSI_FMT_RGB888, 4190 .lanes = 4, 4191 }; 4192 4193 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4194 .clock = 157200, 4195 .hdisplay = 1920, 4196 .hsync_start = 1920 + 154, 4197 .hsync_end = 1920 + 154 + 16, 4198 .htotal = 1920 + 154 + 16 + 32, 4199 .vdisplay = 1200, 4200 .vsync_start = 1200 + 17, 4201 .vsync_end = 1200 + 17 + 2, 4202 .vtotal = 1200 + 17 + 2 + 16, 4203 .vrefresh = 60, 4204 }; 4205 4206 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4207 .desc = { 4208 .modes = &panasonic_vvx10f004b00_mode, 4209 .num_modes = 1, 4210 .bpc = 8, 4211 .size = { 4212 .width = 217, 4213 .height = 136, 4214 }, 4215 }, 4216 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4217 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4218 .format = MIPI_DSI_FMT_RGB888, 4219 .lanes = 4, 4220 }; 4221 4222 static const struct drm_display_mode lg_acx467akm_7_mode = { 4223 .clock = 150000, 4224 .hdisplay = 1080, 4225 .hsync_start = 1080 + 2, 4226 .hsync_end = 1080 + 2 + 2, 4227 .htotal = 1080 + 2 + 2 + 2, 4228 .vdisplay = 1920, 4229 .vsync_start = 1920 + 2, 4230 .vsync_end = 1920 + 2 + 2, 4231 .vtotal = 1920 + 2 + 2 + 2, 4232 .vrefresh = 60, 4233 }; 4234 4235 static const struct panel_desc_dsi lg_acx467akm_7 = { 4236 .desc = { 4237 .modes = &lg_acx467akm_7_mode, 4238 .num_modes = 1, 4239 .bpc = 8, 4240 .size = { 4241 .width = 62, 4242 .height = 110, 4243 }, 4244 }, 4245 .flags = 0, 4246 .format = MIPI_DSI_FMT_RGB888, 4247 .lanes = 4, 4248 }; 4249 4250 static const struct drm_display_mode osd101t2045_53ts_mode = { 4251 .clock = 154500, 4252 .hdisplay = 1920, 4253 .hsync_start = 1920 + 112, 4254 .hsync_end = 1920 + 112 + 16, 4255 .htotal = 1920 + 112 + 16 + 32, 4256 .vdisplay = 1200, 4257 .vsync_start = 1200 + 16, 4258 .vsync_end = 1200 + 16 + 2, 4259 .vtotal = 1200 + 16 + 2 + 16, 4260 .vrefresh = 60, 4261 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4262 }; 4263 4264 static const struct panel_desc_dsi osd101t2045_53ts = { 4265 .desc = { 4266 .modes = &osd101t2045_53ts_mode, 4267 .num_modes = 1, 4268 .bpc = 8, 4269 .size = { 4270 .width = 217, 4271 .height = 136, 4272 }, 4273 }, 4274 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4275 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4276 MIPI_DSI_MODE_EOT_PACKET, 4277 .format = MIPI_DSI_FMT_RGB888, 4278 .lanes = 4, 4279 }; 4280 4281 static const struct of_device_id dsi_of_match[] = { 4282 { 4283 .compatible = "auo,b080uan01", 4284 .data = &auo_b080uan01 4285 }, { 4286 .compatible = "boe,tv080wum-nl0", 4287 .data = &boe_tv080wum_nl0 4288 }, { 4289 .compatible = "lg,ld070wx3-sl01", 4290 .data = &lg_ld070wx3_sl01 4291 }, { 4292 .compatible = "lg,lh500wx1-sd03", 4293 .data = &lg_lh500wx1_sd03 4294 }, { 4295 .compatible = "panasonic,vvx10f004b00", 4296 .data = &panasonic_vvx10f004b00 4297 }, { 4298 .compatible = "lg,acx467akm-7", 4299 .data = &lg_acx467akm_7 4300 }, { 4301 .compatible = "osddisplays,osd101t2045-53ts", 4302 .data = &osd101t2045_53ts 4303 }, { 4304 /* sentinel */ 4305 } 4306 }; 4307 MODULE_DEVICE_TABLE(of, dsi_of_match); 4308 4309 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4310 { 4311 const struct panel_desc_dsi *desc; 4312 const struct of_device_id *id; 4313 int err; 4314 4315 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4316 if (!id) 4317 return -ENODEV; 4318 4319 desc = id->data; 4320 4321 err = panel_simple_probe(&dsi->dev, &desc->desc); 4322 if (err < 0) 4323 return err; 4324 4325 dsi->mode_flags = desc->flags; 4326 dsi->format = desc->format; 4327 dsi->lanes = desc->lanes; 4328 4329 err = mipi_dsi_attach(dsi); 4330 if (err) { 4331 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4332 4333 drm_panel_remove(&panel->base); 4334 } 4335 4336 return err; 4337 } 4338 4339 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4340 { 4341 int err; 4342 4343 err = mipi_dsi_detach(dsi); 4344 if (err < 0) 4345 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4346 4347 return panel_simple_remove(&dsi->dev); 4348 } 4349 4350 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4351 { 4352 panel_simple_shutdown(&dsi->dev); 4353 } 4354 4355 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4356 .driver = { 4357 .name = "panel-simple-dsi", 4358 .of_match_table = dsi_of_match, 4359 }, 4360 .probe = panel_simple_dsi_probe, 4361 .remove = panel_simple_dsi_remove, 4362 .shutdown = panel_simple_dsi_shutdown, 4363 }; 4364 4365 static int __init panel_simple_init(void) 4366 { 4367 int err; 4368 4369 err = platform_driver_register(&panel_simple_platform_driver); 4370 if (err < 0) 4371 return err; 4372 4373 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4374 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4375 if (err < 0) 4376 return err; 4377 } 4378 4379 return 0; 4380 } 4381 module_init(panel_simple_init); 4382 4383 static void __exit panel_simple_exit(void) 4384 { 4385 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4386 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4387 4388 platform_driver_unregister(&panel_simple_platform_driver); 4389 } 4390 module_exit(panel_simple_exit); 4391 4392 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4393 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4394 MODULE_LICENSE("GPL and additional rights"); 4395