1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * struct panel_desc 43 * @modes: Pointer to array of fixed modes appropriate for this panel. If 44 * only one mode then this can just be the address of this the mode. 45 * NOTE: cannot be used with "timings" and also if this is specified 46 * then you cannot override the mode in the device tree. 47 * @num_modes: Number of elements in modes array. 48 * @timings: Pointer to array of display timings. NOTE: cannot be used with 49 * "modes" and also these will be used to validate a device tree 50 * override if one is present. 51 * @num_timings: Number of elements in timings array. 52 * @bpc: Bits per color. 53 * @size: Structure containing the physical size of this panel. 54 * @delay: Structure containing various delay values for this panel. 55 * @bus_format: See MEDIA_BUS_FMT_... defines. 56 * @bus_flags: See DRM_BUS_FLAG_... defines. 57 * @connector_type: LVDS, eDP, DSI, DPI, etc. 58 */ 59 struct panel_desc { 60 const struct drm_display_mode *modes; 61 unsigned int num_modes; 62 const struct display_timing *timings; 63 unsigned int num_timings; 64 65 unsigned int bpc; 66 67 /** 68 * @width: width (in millimeters) of the panel's active display area 69 * @height: height (in millimeters) of the panel's active display area 70 */ 71 struct { 72 unsigned int width; 73 unsigned int height; 74 } size; 75 76 /** 77 * @prepare: the time (in milliseconds) that it takes for the panel to 78 * become ready and start receiving video data 79 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 80 * Plug Detect isn't used. 81 * @enable: the time (in milliseconds) that it takes for the panel to 82 * display the first valid frame after starting to receive 83 * video data 84 * @disable: the time (in milliseconds) that it takes for the panel to 85 * turn the display off (no content is visible) 86 * @unprepare: the time (in milliseconds) that it takes for the panel 87 * to power itself down completely 88 */ 89 struct { 90 unsigned int prepare; 91 unsigned int hpd_absent_delay; 92 unsigned int enable; 93 unsigned int disable; 94 unsigned int unprepare; 95 } delay; 96 97 u32 bus_format; 98 u32 bus_flags; 99 int connector_type; 100 }; 101 102 struct panel_simple { 103 struct drm_panel base; 104 bool prepared; 105 bool enabled; 106 bool no_hpd; 107 108 const struct panel_desc *desc; 109 110 struct regulator *supply; 111 struct i2c_adapter *ddc; 112 113 struct gpio_desc *enable_gpio; 114 struct gpio_desc *hpd_gpio; 115 116 struct drm_display_mode override_mode; 117 118 enum drm_panel_orientation orientation; 119 }; 120 121 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 122 { 123 return container_of(panel, struct panel_simple, base); 124 } 125 126 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 127 struct drm_connector *connector) 128 { 129 struct drm_display_mode *mode; 130 unsigned int i, num = 0; 131 132 for (i = 0; i < panel->desc->num_timings; i++) { 133 const struct display_timing *dt = &panel->desc->timings[i]; 134 struct videomode vm; 135 136 videomode_from_timing(dt, &vm); 137 mode = drm_mode_create(connector->dev); 138 if (!mode) { 139 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 140 dt->hactive.typ, dt->vactive.typ); 141 continue; 142 } 143 144 drm_display_mode_from_videomode(&vm, mode); 145 146 mode->type |= DRM_MODE_TYPE_DRIVER; 147 148 if (panel->desc->num_timings == 1) 149 mode->type |= DRM_MODE_TYPE_PREFERRED; 150 151 drm_mode_probed_add(connector, mode); 152 num++; 153 } 154 155 return num; 156 } 157 158 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 159 struct drm_connector *connector) 160 { 161 struct drm_display_mode *mode; 162 unsigned int i, num = 0; 163 164 for (i = 0; i < panel->desc->num_modes; i++) { 165 const struct drm_display_mode *m = &panel->desc->modes[i]; 166 167 mode = drm_mode_duplicate(connector->dev, m); 168 if (!mode) { 169 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 170 m->hdisplay, m->vdisplay, 171 drm_mode_vrefresh(m)); 172 continue; 173 } 174 175 mode->type |= DRM_MODE_TYPE_DRIVER; 176 177 if (panel->desc->num_modes == 1) 178 mode->type |= DRM_MODE_TYPE_PREFERRED; 179 180 drm_mode_set_name(mode); 181 182 drm_mode_probed_add(connector, mode); 183 num++; 184 } 185 186 return num; 187 } 188 189 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 190 struct drm_connector *connector) 191 { 192 struct drm_display_mode *mode; 193 bool has_override = panel->override_mode.type; 194 unsigned int num = 0; 195 196 if (!panel->desc) 197 return 0; 198 199 if (has_override) { 200 mode = drm_mode_duplicate(connector->dev, 201 &panel->override_mode); 202 if (mode) { 203 drm_mode_probed_add(connector, mode); 204 num = 1; 205 } else { 206 dev_err(panel->base.dev, "failed to add override mode\n"); 207 } 208 } 209 210 /* Only add timings if override was not there or failed to validate */ 211 if (num == 0 && panel->desc->num_timings) 212 num = panel_simple_get_timings_modes(panel, connector); 213 214 /* 215 * Only add fixed modes if timings/override added no mode. 216 * 217 * We should only ever have either the display timings specified 218 * or a fixed mode. Anything else is rather bogus. 219 */ 220 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 221 if (num == 0) 222 num = panel_simple_get_display_modes(panel, connector); 223 224 connector->display_info.bpc = panel->desc->bpc; 225 connector->display_info.width_mm = panel->desc->size.width; 226 connector->display_info.height_mm = panel->desc->size.height; 227 if (panel->desc->bus_format) 228 drm_display_info_set_bus_formats(&connector->display_info, 229 &panel->desc->bus_format, 1); 230 connector->display_info.bus_flags = panel->desc->bus_flags; 231 232 return num; 233 } 234 235 static int panel_simple_disable(struct drm_panel *panel) 236 { 237 struct panel_simple *p = to_panel_simple(panel); 238 239 if (!p->enabled) 240 return 0; 241 242 if (p->desc->delay.disable) 243 msleep(p->desc->delay.disable); 244 245 p->enabled = false; 246 247 return 0; 248 } 249 250 static int panel_simple_unprepare(struct drm_panel *panel) 251 { 252 struct panel_simple *p = to_panel_simple(panel); 253 254 if (!p->prepared) 255 return 0; 256 257 gpiod_set_value_cansleep(p->enable_gpio, 0); 258 259 regulator_disable(p->supply); 260 261 if (p->desc->delay.unprepare) 262 msleep(p->desc->delay.unprepare); 263 264 p->prepared = false; 265 266 return 0; 267 } 268 269 static int panel_simple_get_hpd_gpio(struct device *dev, 270 struct panel_simple *p, bool from_probe) 271 { 272 int err; 273 274 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 275 if (IS_ERR(p->hpd_gpio)) { 276 err = PTR_ERR(p->hpd_gpio); 277 278 /* 279 * If we're called from probe we won't consider '-EPROBE_DEFER' 280 * to be an error--we'll leave the error code in "hpd_gpio". 281 * When we try to use it we'll try again. This allows for 282 * circular dependencies where the component providing the 283 * hpd gpio needs the panel to init before probing. 284 */ 285 if (err != -EPROBE_DEFER || !from_probe) { 286 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 287 return err; 288 } 289 } 290 291 return 0; 292 } 293 294 static int panel_simple_prepare(struct drm_panel *panel) 295 { 296 struct panel_simple *p = to_panel_simple(panel); 297 unsigned int delay; 298 int err; 299 int hpd_asserted; 300 301 if (p->prepared) 302 return 0; 303 304 err = regulator_enable(p->supply); 305 if (err < 0) { 306 dev_err(panel->dev, "failed to enable supply: %d\n", err); 307 return err; 308 } 309 310 gpiod_set_value_cansleep(p->enable_gpio, 1); 311 312 delay = p->desc->delay.prepare; 313 if (p->no_hpd) 314 delay += p->desc->delay.hpd_absent_delay; 315 if (delay) 316 msleep(delay); 317 318 if (p->hpd_gpio) { 319 if (IS_ERR(p->hpd_gpio)) { 320 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 321 if (err) 322 return err; 323 } 324 325 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 326 hpd_asserted, hpd_asserted, 327 1000, 2000000); 328 if (hpd_asserted < 0) 329 err = hpd_asserted; 330 331 if (err) { 332 dev_err(panel->dev, 333 "error waiting for hpd GPIO: %d\n", err); 334 return err; 335 } 336 } 337 338 p->prepared = true; 339 340 return 0; 341 } 342 343 static int panel_simple_enable(struct drm_panel *panel) 344 { 345 struct panel_simple *p = to_panel_simple(panel); 346 347 if (p->enabled) 348 return 0; 349 350 if (p->desc->delay.enable) 351 msleep(p->desc->delay.enable); 352 353 p->enabled = true; 354 355 return 0; 356 } 357 358 static int panel_simple_get_modes(struct drm_panel *panel, 359 struct drm_connector *connector) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int num = 0; 363 364 /* probe EDID if a DDC bus is available */ 365 if (p->ddc) { 366 struct edid *edid = drm_get_edid(connector, p->ddc); 367 368 drm_connector_update_edid_property(connector, edid); 369 if (edid) { 370 num += drm_add_edid_modes(connector, edid); 371 kfree(edid); 372 } 373 } 374 375 /* add hard-coded panel modes */ 376 num += panel_simple_get_non_edid_modes(p, connector); 377 378 /* set up connector's "panel orientation" property */ 379 drm_connector_set_panel_orientation(connector, p->orientation); 380 381 return num; 382 } 383 384 static int panel_simple_get_timings(struct drm_panel *panel, 385 unsigned int num_timings, 386 struct display_timing *timings) 387 { 388 struct panel_simple *p = to_panel_simple(panel); 389 unsigned int i; 390 391 if (p->desc->num_timings < num_timings) 392 num_timings = p->desc->num_timings; 393 394 if (timings) 395 for (i = 0; i < num_timings; i++) 396 timings[i] = p->desc->timings[i]; 397 398 return p->desc->num_timings; 399 } 400 401 static const struct drm_panel_funcs panel_simple_funcs = { 402 .disable = panel_simple_disable, 403 .unprepare = panel_simple_unprepare, 404 .prepare = panel_simple_prepare, 405 .enable = panel_simple_enable, 406 .get_modes = panel_simple_get_modes, 407 .get_timings = panel_simple_get_timings, 408 }; 409 410 static struct panel_desc panel_dpi; 411 412 static int panel_dpi_probe(struct device *dev, 413 struct panel_simple *panel) 414 { 415 struct display_timing *timing; 416 const struct device_node *np; 417 struct panel_desc *desc; 418 unsigned int bus_flags; 419 struct videomode vm; 420 int ret; 421 422 np = dev->of_node; 423 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 424 if (!desc) 425 return -ENOMEM; 426 427 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 428 if (!timing) 429 return -ENOMEM; 430 431 ret = of_get_display_timing(np, "panel-timing", timing); 432 if (ret < 0) { 433 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 434 np); 435 return ret; 436 } 437 438 desc->timings = timing; 439 desc->num_timings = 1; 440 441 of_property_read_u32(np, "width-mm", &desc->size.width); 442 of_property_read_u32(np, "height-mm", &desc->size.height); 443 444 /* Extract bus_flags from display_timing */ 445 bus_flags = 0; 446 vm.flags = timing->flags; 447 drm_bus_flags_from_videomode(&vm, &bus_flags); 448 desc->bus_flags = bus_flags; 449 450 /* We do not know the connector for the DT node, so guess it */ 451 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 452 453 panel->desc = desc; 454 455 return 0; 456 } 457 458 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 459 (to_check->field.typ >= bounds->field.min && \ 460 to_check->field.typ <= bounds->field.max) 461 static void panel_simple_parse_panel_timing_node(struct device *dev, 462 struct panel_simple *panel, 463 const struct display_timing *ot) 464 { 465 const struct panel_desc *desc = panel->desc; 466 struct videomode vm; 467 unsigned int i; 468 469 if (WARN_ON(desc->num_modes)) { 470 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 471 return; 472 } 473 if (WARN_ON(!desc->num_timings)) { 474 dev_err(dev, "Reject override mode: no timings specified\n"); 475 return; 476 } 477 478 for (i = 0; i < panel->desc->num_timings; i++) { 479 const struct display_timing *dt = &panel->desc->timings[i]; 480 481 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 487 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 488 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 489 continue; 490 491 if (ot->flags != dt->flags) 492 continue; 493 494 videomode_from_timing(ot, &vm); 495 drm_display_mode_from_videomode(&vm, &panel->override_mode); 496 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 497 DRM_MODE_TYPE_PREFERRED; 498 break; 499 } 500 501 if (WARN_ON(!panel->override_mode.type)) 502 dev_err(dev, "Reject override mode: No display_timing found\n"); 503 } 504 505 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 506 { 507 struct panel_simple *panel; 508 struct display_timing dt; 509 struct device_node *ddc; 510 int connector_type; 511 u32 bus_flags; 512 int err; 513 514 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 515 if (!panel) 516 return -ENOMEM; 517 518 panel->enabled = false; 519 panel->prepared = false; 520 panel->desc = desc; 521 522 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 523 if (!panel->no_hpd) { 524 err = panel_simple_get_hpd_gpio(dev, panel, true); 525 if (err) 526 return err; 527 } 528 529 panel->supply = devm_regulator_get(dev, "power"); 530 if (IS_ERR(panel->supply)) 531 return PTR_ERR(panel->supply); 532 533 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 534 GPIOD_OUT_LOW); 535 if (IS_ERR(panel->enable_gpio)) { 536 err = PTR_ERR(panel->enable_gpio); 537 if (err != -EPROBE_DEFER) 538 dev_err(dev, "failed to request GPIO: %d\n", err); 539 return err; 540 } 541 542 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 543 if (err) { 544 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 545 return err; 546 } 547 548 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 549 if (ddc) { 550 panel->ddc = of_find_i2c_adapter_by_node(ddc); 551 of_node_put(ddc); 552 553 if (!panel->ddc) 554 return -EPROBE_DEFER; 555 } 556 557 if (desc == &panel_dpi) { 558 /* Handle the generic panel-dpi binding */ 559 err = panel_dpi_probe(dev, panel); 560 if (err) 561 goto free_ddc; 562 } else { 563 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 564 panel_simple_parse_panel_timing_node(dev, panel, &dt); 565 } 566 567 connector_type = desc->connector_type; 568 /* Catch common mistakes for panels. */ 569 switch (connector_type) { 570 case 0: 571 dev_warn(dev, "Specify missing connector_type\n"); 572 connector_type = DRM_MODE_CONNECTOR_DPI; 573 break; 574 case DRM_MODE_CONNECTOR_LVDS: 575 WARN_ON(desc->bus_flags & 576 ~(DRM_BUS_FLAG_DE_LOW | 577 DRM_BUS_FLAG_DE_HIGH | 578 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 579 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 580 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 582 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 583 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 584 desc->bpc != 6); 585 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 586 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 587 desc->bpc != 8); 588 break; 589 case DRM_MODE_CONNECTOR_eDP: 590 if (desc->bus_format == 0) 591 dev_warn(dev, "Specify missing bus_format\n"); 592 if (desc->bpc != 6 && desc->bpc != 8) 593 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 594 break; 595 case DRM_MODE_CONNECTOR_DSI: 596 if (desc->bpc != 6 && desc->bpc != 8) 597 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 598 break; 599 case DRM_MODE_CONNECTOR_DPI: 600 bus_flags = DRM_BUS_FLAG_DE_LOW | 601 DRM_BUS_FLAG_DE_HIGH | 602 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 603 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 604 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 605 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 606 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 607 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 608 if (desc->bus_flags & ~bus_flags) 609 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 610 if (!(desc->bus_flags & bus_flags)) 611 dev_warn(dev, "Specify missing bus_flags\n"); 612 if (desc->bus_format == 0) 613 dev_warn(dev, "Specify missing bus_format\n"); 614 if (desc->bpc != 6 && desc->bpc != 8) 615 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 616 break; 617 default: 618 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 619 connector_type = DRM_MODE_CONNECTOR_DPI; 620 break; 621 } 622 623 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 624 625 err = drm_panel_of_backlight(&panel->base); 626 if (err) 627 goto free_ddc; 628 629 drm_panel_add(&panel->base); 630 631 dev_set_drvdata(dev, panel); 632 633 return 0; 634 635 free_ddc: 636 if (panel->ddc) 637 put_device(&panel->ddc->dev); 638 639 return err; 640 } 641 642 static int panel_simple_remove(struct device *dev) 643 { 644 struct panel_simple *panel = dev_get_drvdata(dev); 645 646 drm_panel_remove(&panel->base); 647 drm_panel_disable(&panel->base); 648 drm_panel_unprepare(&panel->base); 649 650 if (panel->ddc) 651 put_device(&panel->ddc->dev); 652 653 return 0; 654 } 655 656 static void panel_simple_shutdown(struct device *dev) 657 { 658 struct panel_simple *panel = dev_get_drvdata(dev); 659 660 drm_panel_disable(&panel->base); 661 drm_panel_unprepare(&panel->base); 662 } 663 664 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 665 .clock = 71100, 666 .hdisplay = 1280, 667 .hsync_start = 1280 + 40, 668 .hsync_end = 1280 + 40 + 80, 669 .htotal = 1280 + 40 + 80 + 40, 670 .vdisplay = 800, 671 .vsync_start = 800 + 3, 672 .vsync_end = 800 + 3 + 10, 673 .vtotal = 800 + 3 + 10 + 10, 674 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 675 }; 676 677 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 678 .modes = &ire_am_1280800n3tzqw_t00h_mode, 679 .num_modes = 1, 680 .bpc = 6, 681 .size = { 682 .width = 217, 683 .height = 136, 684 }, 685 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 687 .connector_type = DRM_MODE_CONNECTOR_LVDS, 688 }; 689 690 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 691 .clock = 9000, 692 .hdisplay = 480, 693 .hsync_start = 480 + 2, 694 .hsync_end = 480 + 2 + 41, 695 .htotal = 480 + 2 + 41 + 2, 696 .vdisplay = 272, 697 .vsync_start = 272 + 2, 698 .vsync_end = 272 + 2 + 10, 699 .vtotal = 272 + 2 + 10 + 2, 700 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 701 }; 702 703 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 704 .modes = &ire_am_480272h3tmqw_t01h_mode, 705 .num_modes = 1, 706 .bpc = 8, 707 .size = { 708 .width = 105, 709 .height = 67, 710 }, 711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 712 }; 713 714 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 715 .clock = 33333, 716 .hdisplay = 800, 717 .hsync_start = 800 + 0, 718 .hsync_end = 800 + 0 + 255, 719 .htotal = 800 + 0 + 255 + 0, 720 .vdisplay = 480, 721 .vsync_start = 480 + 2, 722 .vsync_end = 480 + 2 + 45, 723 .vtotal = 480 + 2 + 45 + 0, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am800480r3tmqwa1h = { 728 .modes = &ire_am800480r3tmqwa1h_mode, 729 .num_modes = 1, 730 .bpc = 6, 731 .size = { 732 .width = 152, 733 .height = 91, 734 }, 735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 736 }; 737 738 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 739 .pixelclock = { 26400000, 33300000, 46800000 }, 740 .hactive = { 800, 800, 800 }, 741 .hfront_porch = { 16, 210, 354 }, 742 .hback_porch = { 45, 36, 6 }, 743 .hsync_len = { 1, 10, 40 }, 744 .vactive = { 480, 480, 480 }, 745 .vfront_porch = { 7, 22, 147 }, 746 .vback_porch = { 22, 13, 3 }, 747 .vsync_len = { 1, 10, 20 }, 748 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 749 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 750 }; 751 752 static const struct panel_desc armadeus_st0700_adapt = { 753 .timings = &santek_st0700i5y_rbslw_f_timing, 754 .num_timings = 1, 755 .bpc = 6, 756 .size = { 757 .width = 154, 758 .height = 86, 759 }, 760 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 761 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 762 }; 763 764 static const struct drm_display_mode auo_b101aw03_mode = { 765 .clock = 51450, 766 .hdisplay = 1024, 767 .hsync_start = 1024 + 156, 768 .hsync_end = 1024 + 156 + 8, 769 .htotal = 1024 + 156 + 8 + 156, 770 .vdisplay = 600, 771 .vsync_start = 600 + 16, 772 .vsync_end = 600 + 16 + 6, 773 .vtotal = 600 + 16 + 6 + 16, 774 }; 775 776 static const struct panel_desc auo_b101aw03 = { 777 .modes = &auo_b101aw03_mode, 778 .num_modes = 1, 779 .bpc = 6, 780 .size = { 781 .width = 223, 782 .height = 125, 783 }, 784 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 785 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 787 }; 788 789 static const struct display_timing auo_b101ean01_timing = { 790 .pixelclock = { 65300000, 72500000, 75000000 }, 791 .hactive = { 1280, 1280, 1280 }, 792 .hfront_porch = { 18, 119, 119 }, 793 .hback_porch = { 21, 21, 21 }, 794 .hsync_len = { 32, 32, 32 }, 795 .vactive = { 800, 800, 800 }, 796 .vfront_porch = { 4, 4, 4 }, 797 .vback_porch = { 8, 8, 8 }, 798 .vsync_len = { 18, 20, 20 }, 799 }; 800 801 static const struct panel_desc auo_b101ean01 = { 802 .timings = &auo_b101ean01_timing, 803 .num_timings = 1, 804 .bpc = 6, 805 .size = { 806 .width = 217, 807 .height = 136, 808 }, 809 }; 810 811 static const struct drm_display_mode auo_b101xtn01_mode = { 812 .clock = 72000, 813 .hdisplay = 1366, 814 .hsync_start = 1366 + 20, 815 .hsync_end = 1366 + 20 + 70, 816 .htotal = 1366 + 20 + 70, 817 .vdisplay = 768, 818 .vsync_start = 768 + 14, 819 .vsync_end = 768 + 14 + 42, 820 .vtotal = 768 + 14 + 42, 821 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 822 }; 823 824 static const struct panel_desc auo_b101xtn01 = { 825 .modes = &auo_b101xtn01_mode, 826 .num_modes = 1, 827 .bpc = 6, 828 .size = { 829 .width = 223, 830 .height = 125, 831 }, 832 }; 833 834 static const struct drm_display_mode auo_b116xak01_mode = { 835 .clock = 69300, 836 .hdisplay = 1366, 837 .hsync_start = 1366 + 48, 838 .hsync_end = 1366 + 48 + 32, 839 .htotal = 1366 + 48 + 32 + 10, 840 .vdisplay = 768, 841 .vsync_start = 768 + 4, 842 .vsync_end = 768 + 4 + 6, 843 .vtotal = 768 + 4 + 6 + 15, 844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 845 }; 846 847 static const struct panel_desc auo_b116xak01 = { 848 .modes = &auo_b116xak01_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 256, 853 .height = 144, 854 }, 855 .delay = { 856 .hpd_absent_delay = 200, 857 }, 858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 859 .connector_type = DRM_MODE_CONNECTOR_eDP, 860 }; 861 862 static const struct drm_display_mode auo_b116xw03_mode = { 863 .clock = 70589, 864 .hdisplay = 1366, 865 .hsync_start = 1366 + 40, 866 .hsync_end = 1366 + 40 + 40, 867 .htotal = 1366 + 40 + 40 + 32, 868 .vdisplay = 768, 869 .vsync_start = 768 + 10, 870 .vsync_end = 768 + 10 + 12, 871 .vtotal = 768 + 10 + 12 + 6, 872 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 873 }; 874 875 static const struct panel_desc auo_b116xw03 = { 876 .modes = &auo_b116xw03_mode, 877 .num_modes = 1, 878 .bpc = 6, 879 .size = { 880 .width = 256, 881 .height = 144, 882 }, 883 .delay = { 884 .enable = 400, 885 }, 886 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 888 .connector_type = DRM_MODE_CONNECTOR_eDP, 889 }; 890 891 static const struct drm_display_mode auo_b133xtn01_mode = { 892 .clock = 69500, 893 .hdisplay = 1366, 894 .hsync_start = 1366 + 48, 895 .hsync_end = 1366 + 48 + 32, 896 .htotal = 1366 + 48 + 32 + 20, 897 .vdisplay = 768, 898 .vsync_start = 768 + 3, 899 .vsync_end = 768 + 3 + 6, 900 .vtotal = 768 + 3 + 6 + 13, 901 }; 902 903 static const struct panel_desc auo_b133xtn01 = { 904 .modes = &auo_b133xtn01_mode, 905 .num_modes = 1, 906 .bpc = 6, 907 .size = { 908 .width = 293, 909 .height = 165, 910 }, 911 }; 912 913 static const struct drm_display_mode auo_b133htn01_mode = { 914 .clock = 150660, 915 .hdisplay = 1920, 916 .hsync_start = 1920 + 172, 917 .hsync_end = 1920 + 172 + 80, 918 .htotal = 1920 + 172 + 80 + 60, 919 .vdisplay = 1080, 920 .vsync_start = 1080 + 25, 921 .vsync_end = 1080 + 25 + 10, 922 .vtotal = 1080 + 25 + 10 + 10, 923 }; 924 925 static const struct panel_desc auo_b133htn01 = { 926 .modes = &auo_b133htn01_mode, 927 .num_modes = 1, 928 .bpc = 6, 929 .size = { 930 .width = 293, 931 .height = 165, 932 }, 933 .delay = { 934 .prepare = 105, 935 .enable = 20, 936 .unprepare = 50, 937 }, 938 }; 939 940 static const struct display_timing auo_g070vvn01_timings = { 941 .pixelclock = { 33300000, 34209000, 45000000 }, 942 .hactive = { 800, 800, 800 }, 943 .hfront_porch = { 20, 40, 200 }, 944 .hback_porch = { 87, 40, 1 }, 945 .hsync_len = { 1, 48, 87 }, 946 .vactive = { 480, 480, 480 }, 947 .vfront_porch = { 5, 13, 200 }, 948 .vback_porch = { 31, 31, 29 }, 949 .vsync_len = { 1, 1, 3 }, 950 }; 951 952 static const struct panel_desc auo_g070vvn01 = { 953 .timings = &auo_g070vvn01_timings, 954 .num_timings = 1, 955 .bpc = 8, 956 .size = { 957 .width = 152, 958 .height = 91, 959 }, 960 .delay = { 961 .prepare = 200, 962 .enable = 50, 963 .disable = 50, 964 .unprepare = 1000, 965 }, 966 }; 967 968 static const struct drm_display_mode auo_g101evn010_mode = { 969 .clock = 68930, 970 .hdisplay = 1280, 971 .hsync_start = 1280 + 82, 972 .hsync_end = 1280 + 82 + 2, 973 .htotal = 1280 + 82 + 2 + 84, 974 .vdisplay = 800, 975 .vsync_start = 800 + 8, 976 .vsync_end = 800 + 8 + 2, 977 .vtotal = 800 + 8 + 2 + 6, 978 }; 979 980 static const struct panel_desc auo_g101evn010 = { 981 .modes = &auo_g101evn010_mode, 982 .num_modes = 1, 983 .bpc = 6, 984 .size = { 985 .width = 216, 986 .height = 135, 987 }, 988 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 989 .connector_type = DRM_MODE_CONNECTOR_LVDS, 990 }; 991 992 static const struct drm_display_mode auo_g104sn02_mode = { 993 .clock = 40000, 994 .hdisplay = 800, 995 .hsync_start = 800 + 40, 996 .hsync_end = 800 + 40 + 216, 997 .htotal = 800 + 40 + 216 + 128, 998 .vdisplay = 600, 999 .vsync_start = 600 + 10, 1000 .vsync_end = 600 + 10 + 35, 1001 .vtotal = 600 + 10 + 35 + 2, 1002 }; 1003 1004 static const struct panel_desc auo_g104sn02 = { 1005 .modes = &auo_g104sn02_mode, 1006 .num_modes = 1, 1007 .bpc = 8, 1008 .size = { 1009 .width = 211, 1010 .height = 158, 1011 }, 1012 }; 1013 1014 static const struct drm_display_mode auo_g121ean01_mode = { 1015 .clock = 66700, 1016 .hdisplay = 1280, 1017 .hsync_start = 1280 + 58, 1018 .hsync_end = 1280 + 58 + 8, 1019 .htotal = 1280 + 58 + 8 + 70, 1020 .vdisplay = 800, 1021 .vsync_start = 800 + 6, 1022 .vsync_end = 800 + 6 + 4, 1023 .vtotal = 800 + 6 + 4 + 10, 1024 }; 1025 1026 static const struct panel_desc auo_g121ean01 = { 1027 .modes = &auo_g121ean01_mode, 1028 .num_modes = 1, 1029 .bpc = 8, 1030 .size = { 1031 .width = 261, 1032 .height = 163, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g133han01_timings = { 1039 .pixelclock = { 134000000, 141200000, 149000000 }, 1040 .hactive = { 1920, 1920, 1920 }, 1041 .hfront_porch = { 39, 58, 77 }, 1042 .hback_porch = { 59, 88, 117 }, 1043 .hsync_len = { 28, 42, 56 }, 1044 .vactive = { 1080, 1080, 1080 }, 1045 .vfront_porch = { 3, 8, 11 }, 1046 .vback_porch = { 5, 14, 19 }, 1047 .vsync_len = { 4, 14, 19 }, 1048 }; 1049 1050 static const struct panel_desc auo_g133han01 = { 1051 .timings = &auo_g133han01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 293, 1056 .height = 165, 1057 }, 1058 .delay = { 1059 .prepare = 200, 1060 .enable = 50, 1061 .disable = 50, 1062 .unprepare = 1000, 1063 }, 1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1066 }; 1067 1068 static const struct drm_display_mode auo_g156xtn01_mode = { 1069 .clock = 76000, 1070 .hdisplay = 1366, 1071 .hsync_start = 1366 + 33, 1072 .hsync_end = 1366 + 33 + 67, 1073 .htotal = 1560, 1074 .vdisplay = 768, 1075 .vsync_start = 768 + 4, 1076 .vsync_end = 768 + 4 + 4, 1077 .vtotal = 806, 1078 }; 1079 1080 static const struct panel_desc auo_g156xtn01 = { 1081 .modes = &auo_g156xtn01_mode, 1082 .num_modes = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 344, 1086 .height = 194, 1087 }, 1088 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1089 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1090 }; 1091 1092 static const struct display_timing auo_g185han01_timings = { 1093 .pixelclock = { 120000000, 144000000, 175000000 }, 1094 .hactive = { 1920, 1920, 1920 }, 1095 .hfront_porch = { 36, 120, 148 }, 1096 .hback_porch = { 24, 88, 108 }, 1097 .hsync_len = { 20, 48, 64 }, 1098 .vactive = { 1080, 1080, 1080 }, 1099 .vfront_porch = { 6, 10, 40 }, 1100 .vback_porch = { 2, 5, 20 }, 1101 .vsync_len = { 2, 5, 20 }, 1102 }; 1103 1104 static const struct panel_desc auo_g185han01 = { 1105 .timings = &auo_g185han01_timings, 1106 .num_timings = 1, 1107 .bpc = 8, 1108 .size = { 1109 .width = 409, 1110 .height = 230, 1111 }, 1112 .delay = { 1113 .prepare = 50, 1114 .enable = 200, 1115 .disable = 110, 1116 .unprepare = 1000, 1117 }, 1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1119 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1120 }; 1121 1122 static const struct display_timing auo_g190ean01_timings = { 1123 .pixelclock = { 90000000, 108000000, 135000000 }, 1124 .hactive = { 1280, 1280, 1280 }, 1125 .hfront_porch = { 126, 184, 1266 }, 1126 .hback_porch = { 84, 122, 844 }, 1127 .hsync_len = { 70, 102, 704 }, 1128 .vactive = { 1024, 1024, 1024 }, 1129 .vfront_porch = { 4, 26, 76 }, 1130 .vback_porch = { 2, 8, 25 }, 1131 .vsync_len = { 2, 8, 25 }, 1132 }; 1133 1134 static const struct panel_desc auo_g190ean01 = { 1135 .timings = &auo_g190ean01_timings, 1136 .num_timings = 1, 1137 .bpc = 8, 1138 .size = { 1139 .width = 376, 1140 .height = 301, 1141 }, 1142 .delay = { 1143 .prepare = 50, 1144 .enable = 200, 1145 .disable = 110, 1146 .unprepare = 1000, 1147 }, 1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1149 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1150 }; 1151 1152 static const struct display_timing auo_p320hvn03_timings = { 1153 .pixelclock = { 106000000, 148500000, 164000000 }, 1154 .hactive = { 1920, 1920, 1920 }, 1155 .hfront_porch = { 25, 50, 130 }, 1156 .hback_porch = { 25, 50, 130 }, 1157 .hsync_len = { 20, 40, 105 }, 1158 .vactive = { 1080, 1080, 1080 }, 1159 .vfront_porch = { 8, 17, 150 }, 1160 .vback_porch = { 8, 17, 150 }, 1161 .vsync_len = { 4, 11, 100 }, 1162 }; 1163 1164 static const struct panel_desc auo_p320hvn03 = { 1165 .timings = &auo_p320hvn03_timings, 1166 .num_timings = 1, 1167 .bpc = 8, 1168 .size = { 1169 .width = 698, 1170 .height = 393, 1171 }, 1172 .delay = { 1173 .prepare = 1, 1174 .enable = 450, 1175 .unprepare = 500, 1176 }, 1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1178 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1179 }; 1180 1181 static const struct drm_display_mode auo_t215hvn01_mode = { 1182 .clock = 148800, 1183 .hdisplay = 1920, 1184 .hsync_start = 1920 + 88, 1185 .hsync_end = 1920 + 88 + 44, 1186 .htotal = 1920 + 88 + 44 + 148, 1187 .vdisplay = 1080, 1188 .vsync_start = 1080 + 4, 1189 .vsync_end = 1080 + 4 + 5, 1190 .vtotal = 1080 + 4 + 5 + 36, 1191 }; 1192 1193 static const struct panel_desc auo_t215hvn01 = { 1194 .modes = &auo_t215hvn01_mode, 1195 .num_modes = 1, 1196 .bpc = 8, 1197 .size = { 1198 .width = 430, 1199 .height = 270, 1200 }, 1201 .delay = { 1202 .disable = 5, 1203 .unprepare = 1000, 1204 } 1205 }; 1206 1207 static const struct drm_display_mode avic_tm070ddh03_mode = { 1208 .clock = 51200, 1209 .hdisplay = 1024, 1210 .hsync_start = 1024 + 160, 1211 .hsync_end = 1024 + 160 + 4, 1212 .htotal = 1024 + 160 + 4 + 156, 1213 .vdisplay = 600, 1214 .vsync_start = 600 + 17, 1215 .vsync_end = 600 + 17 + 1, 1216 .vtotal = 600 + 17 + 1 + 17, 1217 }; 1218 1219 static const struct panel_desc avic_tm070ddh03 = { 1220 .modes = &avic_tm070ddh03_mode, 1221 .num_modes = 1, 1222 .bpc = 8, 1223 .size = { 1224 .width = 154, 1225 .height = 90, 1226 }, 1227 .delay = { 1228 .prepare = 20, 1229 .enable = 200, 1230 .disable = 200, 1231 }, 1232 }; 1233 1234 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1235 .clock = 30000, 1236 .hdisplay = 800, 1237 .hsync_start = 800 + 40, 1238 .hsync_end = 800 + 40 + 48, 1239 .htotal = 800 + 40 + 48 + 40, 1240 .vdisplay = 480, 1241 .vsync_start = 480 + 13, 1242 .vsync_end = 480 + 13 + 3, 1243 .vtotal = 480 + 13 + 3 + 29, 1244 }; 1245 1246 static const struct panel_desc bananapi_s070wv20_ct16 = { 1247 .modes = &bananapi_s070wv20_ct16_mode, 1248 .num_modes = 1, 1249 .bpc = 6, 1250 .size = { 1251 .width = 154, 1252 .height = 86, 1253 }, 1254 }; 1255 1256 static const struct drm_display_mode boe_hv070wsa_mode = { 1257 .clock = 42105, 1258 .hdisplay = 1024, 1259 .hsync_start = 1024 + 30, 1260 .hsync_end = 1024 + 30 + 30, 1261 .htotal = 1024 + 30 + 30 + 30, 1262 .vdisplay = 600, 1263 .vsync_start = 600 + 10, 1264 .vsync_end = 600 + 10 + 10, 1265 .vtotal = 600 + 10 + 10 + 10, 1266 }; 1267 1268 static const struct panel_desc boe_hv070wsa = { 1269 .modes = &boe_hv070wsa_mode, 1270 .num_modes = 1, 1271 .bpc = 8, 1272 .size = { 1273 .width = 154, 1274 .height = 90, 1275 }, 1276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1277 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1279 }; 1280 1281 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1282 { 1283 .clock = 71900, 1284 .hdisplay = 1280, 1285 .hsync_start = 1280 + 48, 1286 .hsync_end = 1280 + 48 + 32, 1287 .htotal = 1280 + 48 + 32 + 80, 1288 .vdisplay = 800, 1289 .vsync_start = 800 + 3, 1290 .vsync_end = 800 + 3 + 5, 1291 .vtotal = 800 + 3 + 5 + 24, 1292 }, 1293 { 1294 .clock = 57500, 1295 .hdisplay = 1280, 1296 .hsync_start = 1280 + 48, 1297 .hsync_end = 1280 + 48 + 32, 1298 .htotal = 1280 + 48 + 32 + 80, 1299 .vdisplay = 800, 1300 .vsync_start = 800 + 3, 1301 .vsync_end = 800 + 3 + 5, 1302 .vtotal = 800 + 3 + 5 + 24, 1303 }, 1304 }; 1305 1306 static const struct panel_desc boe_nv101wxmn51 = { 1307 .modes = boe_nv101wxmn51_modes, 1308 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1309 .bpc = 8, 1310 .size = { 1311 .width = 217, 1312 .height = 136, 1313 }, 1314 .delay = { 1315 .prepare = 210, 1316 .enable = 50, 1317 .unprepare = 160, 1318 }, 1319 }; 1320 1321 /* Also used for boe_nv133fhm_n62 */ 1322 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1323 .clock = 147840, 1324 .hdisplay = 1920, 1325 .hsync_start = 1920 + 48, 1326 .hsync_end = 1920 + 48 + 32, 1327 .htotal = 1920 + 48 + 32 + 200, 1328 .vdisplay = 1080, 1329 .vsync_start = 1080 + 3, 1330 .vsync_end = 1080 + 3 + 6, 1331 .vtotal = 1080 + 3 + 6 + 31, 1332 }; 1333 1334 /* Also used for boe_nv133fhm_n62 */ 1335 static const struct panel_desc boe_nv133fhm_n61 = { 1336 .modes = &boe_nv133fhm_n61_modes, 1337 .num_modes = 1, 1338 .bpc = 6, 1339 .size = { 1340 .width = 294, 1341 .height = 165, 1342 }, 1343 .delay = { 1344 /* 1345 * When power is first given to the panel there's a short 1346 * spike on the HPD line. It was explained that this spike 1347 * was until the TCON data download was complete. On 1348 * one system this was measured at 8 ms. We'll put 15 ms 1349 * in the prepare delay just to be safe and take it away 1350 * from the hpd_absent_delay (which would otherwise be 200 ms) 1351 * to handle this. That means: 1352 * - If HPD isn't hooked up you still have 200 ms delay. 1353 * - If HPD is hooked up we won't try to look at it for the 1354 * first 15 ms. 1355 */ 1356 .prepare = 15, 1357 .hpd_absent_delay = 185, 1358 1359 .unprepare = 500, 1360 }, 1361 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1362 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1363 .connector_type = DRM_MODE_CONNECTOR_eDP, 1364 }; 1365 1366 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1367 { 1368 .clock = 148500, 1369 .hdisplay = 1920, 1370 .hsync_start = 1920 + 48, 1371 .hsync_end = 1920 + 48 + 32, 1372 .htotal = 2200, 1373 .vdisplay = 1080, 1374 .vsync_start = 1080 + 3, 1375 .vsync_end = 1080 + 3 + 5, 1376 .vtotal = 1125, 1377 }, 1378 }; 1379 1380 static const struct panel_desc boe_nv140fhmn49 = { 1381 .modes = boe_nv140fhmn49_modes, 1382 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1383 .bpc = 6, 1384 .size = { 1385 .width = 309, 1386 .height = 174, 1387 }, 1388 .delay = { 1389 .prepare = 210, 1390 .enable = 50, 1391 .unprepare = 160, 1392 }, 1393 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1394 .connector_type = DRM_MODE_CONNECTOR_eDP, 1395 }; 1396 1397 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1398 .clock = 9000, 1399 .hdisplay = 480, 1400 .hsync_start = 480 + 5, 1401 .hsync_end = 480 + 5 + 5, 1402 .htotal = 480 + 5 + 5 + 40, 1403 .vdisplay = 272, 1404 .vsync_start = 272 + 8, 1405 .vsync_end = 272 + 8 + 8, 1406 .vtotal = 272 + 8 + 8 + 8, 1407 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1408 }; 1409 1410 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1411 .modes = &cdtech_s043wq26h_ct7_mode, 1412 .num_modes = 1, 1413 .bpc = 8, 1414 .size = { 1415 .width = 95, 1416 .height = 54, 1417 }, 1418 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1419 }; 1420 1421 /* S070PWS19HP-FC21 2017/04/22 */ 1422 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1423 .clock = 51200, 1424 .hdisplay = 1024, 1425 .hsync_start = 1024 + 160, 1426 .hsync_end = 1024 + 160 + 20, 1427 .htotal = 1024 + 160 + 20 + 140, 1428 .vdisplay = 600, 1429 .vsync_start = 600 + 12, 1430 .vsync_end = 600 + 12 + 3, 1431 .vtotal = 600 + 12 + 3 + 20, 1432 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1433 }; 1434 1435 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1436 .modes = &cdtech_s070pws19hp_fc21_mode, 1437 .num_modes = 1, 1438 .bpc = 6, 1439 .size = { 1440 .width = 154, 1441 .height = 86, 1442 }, 1443 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1444 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1445 .connector_type = DRM_MODE_CONNECTOR_DPI, 1446 }; 1447 1448 /* S070SWV29HG-DC44 2017/09/21 */ 1449 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1450 .clock = 33300, 1451 .hdisplay = 800, 1452 .hsync_start = 800 + 210, 1453 .hsync_end = 800 + 210 + 2, 1454 .htotal = 800 + 210 + 2 + 44, 1455 .vdisplay = 480, 1456 .vsync_start = 480 + 22, 1457 .vsync_end = 480 + 22 + 2, 1458 .vtotal = 480 + 22 + 2 + 21, 1459 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1460 }; 1461 1462 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1463 .modes = &cdtech_s070swv29hg_dc44_mode, 1464 .num_modes = 1, 1465 .bpc = 6, 1466 .size = { 1467 .width = 154, 1468 .height = 86, 1469 }, 1470 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1472 .connector_type = DRM_MODE_CONNECTOR_DPI, 1473 }; 1474 1475 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1476 .clock = 35000, 1477 .hdisplay = 800, 1478 .hsync_start = 800 + 40, 1479 .hsync_end = 800 + 40 + 40, 1480 .htotal = 800 + 40 + 40 + 48, 1481 .vdisplay = 480, 1482 .vsync_start = 480 + 29, 1483 .vsync_end = 480 + 29 + 13, 1484 .vtotal = 480 + 29 + 13 + 3, 1485 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1486 }; 1487 1488 static const struct panel_desc cdtech_s070wv95_ct16 = { 1489 .modes = &cdtech_s070wv95_ct16_mode, 1490 .num_modes = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 154, 1494 .height = 85, 1495 }, 1496 }; 1497 1498 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1499 .pixelclock = { 68900000, 71100000, 73400000 }, 1500 .hactive = { 1280, 1280, 1280 }, 1501 .hfront_porch = { 65, 80, 95 }, 1502 .hback_porch = { 64, 79, 94 }, 1503 .hsync_len = { 1, 1, 1 }, 1504 .vactive = { 800, 800, 800 }, 1505 .vfront_porch = { 7, 11, 14 }, 1506 .vback_porch = { 7, 11, 14 }, 1507 .vsync_len = { 1, 1, 1 }, 1508 .flags = DISPLAY_FLAGS_DE_HIGH, 1509 }; 1510 1511 static const struct panel_desc chefree_ch101olhlwh_002 = { 1512 .timings = &chefree_ch101olhlwh_002_timing, 1513 .num_timings = 1, 1514 .bpc = 8, 1515 .size = { 1516 .width = 217, 1517 .height = 135, 1518 }, 1519 .delay = { 1520 .enable = 200, 1521 .disable = 200, 1522 }, 1523 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1525 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1526 }; 1527 1528 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1529 .clock = 66770, 1530 .hdisplay = 800, 1531 .hsync_start = 800 + 49, 1532 .hsync_end = 800 + 49 + 33, 1533 .htotal = 800 + 49 + 33 + 17, 1534 .vdisplay = 1280, 1535 .vsync_start = 1280 + 1, 1536 .vsync_end = 1280 + 1 + 7, 1537 .vtotal = 1280 + 1 + 7 + 15, 1538 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1539 }; 1540 1541 static const struct panel_desc chunghwa_claa070wp03xg = { 1542 .modes = &chunghwa_claa070wp03xg_mode, 1543 .num_modes = 1, 1544 .bpc = 6, 1545 .size = { 1546 .width = 94, 1547 .height = 150, 1548 }, 1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1550 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1551 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1552 }; 1553 1554 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1555 .clock = 72070, 1556 .hdisplay = 1366, 1557 .hsync_start = 1366 + 58, 1558 .hsync_end = 1366 + 58 + 58, 1559 .htotal = 1366 + 58 + 58 + 58, 1560 .vdisplay = 768, 1561 .vsync_start = 768 + 4, 1562 .vsync_end = 768 + 4 + 4, 1563 .vtotal = 768 + 4 + 4 + 4, 1564 }; 1565 1566 static const struct panel_desc chunghwa_claa101wa01a = { 1567 .modes = &chunghwa_claa101wa01a_mode, 1568 .num_modes = 1, 1569 .bpc = 6, 1570 .size = { 1571 .width = 220, 1572 .height = 120, 1573 }, 1574 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1575 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1577 }; 1578 1579 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1580 .clock = 69300, 1581 .hdisplay = 1366, 1582 .hsync_start = 1366 + 48, 1583 .hsync_end = 1366 + 48 + 32, 1584 .htotal = 1366 + 48 + 32 + 20, 1585 .vdisplay = 768, 1586 .vsync_start = 768 + 16, 1587 .vsync_end = 768 + 16 + 8, 1588 .vtotal = 768 + 16 + 8 + 16, 1589 }; 1590 1591 static const struct panel_desc chunghwa_claa101wb01 = { 1592 .modes = &chunghwa_claa101wb01_mode, 1593 .num_modes = 1, 1594 .bpc = 6, 1595 .size = { 1596 .width = 223, 1597 .height = 125, 1598 }, 1599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1600 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1601 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1602 }; 1603 1604 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1605 .clock = 33260, 1606 .hdisplay = 800, 1607 .hsync_start = 800 + 40, 1608 .hsync_end = 800 + 40 + 128, 1609 .htotal = 800 + 40 + 128 + 88, 1610 .vdisplay = 480, 1611 .vsync_start = 480 + 10, 1612 .vsync_end = 480 + 10 + 2, 1613 .vtotal = 480 + 10 + 2 + 33, 1614 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1615 }; 1616 1617 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1618 .modes = &dataimage_scf0700c48ggu18_mode, 1619 .num_modes = 1, 1620 .bpc = 8, 1621 .size = { 1622 .width = 152, 1623 .height = 91, 1624 }, 1625 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1627 }; 1628 1629 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1630 .pixelclock = { 45000000, 51200000, 57000000 }, 1631 .hactive = { 1024, 1024, 1024 }, 1632 .hfront_porch = { 100, 106, 113 }, 1633 .hback_porch = { 100, 106, 113 }, 1634 .hsync_len = { 100, 108, 114 }, 1635 .vactive = { 600, 600, 600 }, 1636 .vfront_porch = { 8, 11, 15 }, 1637 .vback_porch = { 8, 11, 15 }, 1638 .vsync_len = { 9, 13, 15 }, 1639 .flags = DISPLAY_FLAGS_DE_HIGH, 1640 }; 1641 1642 static const struct panel_desc dlc_dlc0700yzg_1 = { 1643 .timings = &dlc_dlc0700yzg_1_timing, 1644 .num_timings = 1, 1645 .bpc = 6, 1646 .size = { 1647 .width = 154, 1648 .height = 86, 1649 }, 1650 .delay = { 1651 .prepare = 30, 1652 .enable = 200, 1653 .disable = 200, 1654 }, 1655 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1656 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1657 }; 1658 1659 static const struct display_timing dlc_dlc1010gig_timing = { 1660 .pixelclock = { 68900000, 71100000, 73400000 }, 1661 .hactive = { 1280, 1280, 1280 }, 1662 .hfront_porch = { 43, 53, 63 }, 1663 .hback_porch = { 43, 53, 63 }, 1664 .hsync_len = { 44, 54, 64 }, 1665 .vactive = { 800, 800, 800 }, 1666 .vfront_porch = { 5, 8, 11 }, 1667 .vback_porch = { 5, 8, 11 }, 1668 .vsync_len = { 5, 7, 11 }, 1669 .flags = DISPLAY_FLAGS_DE_HIGH, 1670 }; 1671 1672 static const struct panel_desc dlc_dlc1010gig = { 1673 .timings = &dlc_dlc1010gig_timing, 1674 .num_timings = 1, 1675 .bpc = 8, 1676 .size = { 1677 .width = 216, 1678 .height = 135, 1679 }, 1680 .delay = { 1681 .prepare = 60, 1682 .enable = 150, 1683 .disable = 100, 1684 .unprepare = 60, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1687 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1688 }; 1689 1690 static const struct drm_display_mode edt_et035012dm6_mode = { 1691 .clock = 6500, 1692 .hdisplay = 320, 1693 .hsync_start = 320 + 20, 1694 .hsync_end = 320 + 20 + 30, 1695 .htotal = 320 + 20 + 68, 1696 .vdisplay = 240, 1697 .vsync_start = 240 + 4, 1698 .vsync_end = 240 + 4 + 4, 1699 .vtotal = 240 + 4 + 4 + 14, 1700 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1701 }; 1702 1703 static const struct panel_desc edt_et035012dm6 = { 1704 .modes = &edt_et035012dm6_mode, 1705 .num_modes = 1, 1706 .bpc = 8, 1707 .size = { 1708 .width = 70, 1709 .height = 52, 1710 }, 1711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1712 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1713 }; 1714 1715 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1716 .clock = 10870, 1717 .hdisplay = 480, 1718 .hsync_start = 480 + 8, 1719 .hsync_end = 480 + 8 + 4, 1720 .htotal = 480 + 8 + 4 + 41, 1721 1722 /* 1723 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1724 * fb_align 1725 */ 1726 1727 .vdisplay = 288, 1728 .vsync_start = 288 + 2, 1729 .vsync_end = 288 + 2 + 4, 1730 .vtotal = 288 + 2 + 4 + 10, 1731 }; 1732 1733 static const struct panel_desc edt_etm043080dh6gp = { 1734 .modes = &edt_etm043080dh6gp_mode, 1735 .num_modes = 1, 1736 .bpc = 8, 1737 .size = { 1738 .width = 100, 1739 .height = 65, 1740 }, 1741 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1742 .connector_type = DRM_MODE_CONNECTOR_DPI, 1743 }; 1744 1745 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1746 .clock = 9000, 1747 .hdisplay = 480, 1748 .hsync_start = 480 + 2, 1749 .hsync_end = 480 + 2 + 41, 1750 .htotal = 480 + 2 + 41 + 2, 1751 .vdisplay = 272, 1752 .vsync_start = 272 + 2, 1753 .vsync_end = 272 + 2 + 10, 1754 .vtotal = 272 + 2 + 10 + 2, 1755 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1756 }; 1757 1758 static const struct panel_desc edt_etm0430g0dh6 = { 1759 .modes = &edt_etm0430g0dh6_mode, 1760 .num_modes = 1, 1761 .bpc = 6, 1762 .size = { 1763 .width = 95, 1764 .height = 54, 1765 }, 1766 }; 1767 1768 static const struct drm_display_mode edt_et057090dhu_mode = { 1769 .clock = 25175, 1770 .hdisplay = 640, 1771 .hsync_start = 640 + 16, 1772 .hsync_end = 640 + 16 + 30, 1773 .htotal = 640 + 16 + 30 + 114, 1774 .vdisplay = 480, 1775 .vsync_start = 480 + 10, 1776 .vsync_end = 480 + 10 + 3, 1777 .vtotal = 480 + 10 + 3 + 32, 1778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1779 }; 1780 1781 static const struct panel_desc edt_et057090dhu = { 1782 .modes = &edt_et057090dhu_mode, 1783 .num_modes = 1, 1784 .bpc = 6, 1785 .size = { 1786 .width = 115, 1787 .height = 86, 1788 }, 1789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1791 .connector_type = DRM_MODE_CONNECTOR_DPI, 1792 }; 1793 1794 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1795 .clock = 33260, 1796 .hdisplay = 800, 1797 .hsync_start = 800 + 40, 1798 .hsync_end = 800 + 40 + 128, 1799 .htotal = 800 + 40 + 128 + 88, 1800 .vdisplay = 480, 1801 .vsync_start = 480 + 10, 1802 .vsync_end = 480 + 10 + 2, 1803 .vtotal = 480 + 10 + 2 + 33, 1804 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1805 }; 1806 1807 static const struct panel_desc edt_etm0700g0dh6 = { 1808 .modes = &edt_etm0700g0dh6_mode, 1809 .num_modes = 1, 1810 .bpc = 6, 1811 .size = { 1812 .width = 152, 1813 .height = 91, 1814 }, 1815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1817 }; 1818 1819 static const struct panel_desc edt_etm0700g0bdh6 = { 1820 .modes = &edt_etm0700g0dh6_mode, 1821 .num_modes = 1, 1822 .bpc = 6, 1823 .size = { 1824 .width = 152, 1825 .height = 91, 1826 }, 1827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1829 }; 1830 1831 static const struct display_timing evervision_vgg804821_timing = { 1832 .pixelclock = { 27600000, 33300000, 50000000 }, 1833 .hactive = { 800, 800, 800 }, 1834 .hfront_porch = { 40, 66, 70 }, 1835 .hback_porch = { 40, 67, 70 }, 1836 .hsync_len = { 40, 67, 70 }, 1837 .vactive = { 480, 480, 480 }, 1838 .vfront_porch = { 6, 10, 10 }, 1839 .vback_porch = { 7, 11, 11 }, 1840 .vsync_len = { 7, 11, 11 }, 1841 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1842 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1843 DISPLAY_FLAGS_SYNC_NEGEDGE, 1844 }; 1845 1846 static const struct panel_desc evervision_vgg804821 = { 1847 .timings = &evervision_vgg804821_timing, 1848 .num_timings = 1, 1849 .bpc = 8, 1850 .size = { 1851 .width = 108, 1852 .height = 64, 1853 }, 1854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1855 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1856 }; 1857 1858 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1859 .clock = 32260, 1860 .hdisplay = 800, 1861 .hsync_start = 800 + 168, 1862 .hsync_end = 800 + 168 + 64, 1863 .htotal = 800 + 168 + 64 + 88, 1864 .vdisplay = 480, 1865 .vsync_start = 480 + 37, 1866 .vsync_end = 480 + 37 + 2, 1867 .vtotal = 480 + 37 + 2 + 8, 1868 }; 1869 1870 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1871 .modes = &foxlink_fl500wvr00_a0t_mode, 1872 .num_modes = 1, 1873 .bpc = 8, 1874 .size = { 1875 .width = 108, 1876 .height = 65, 1877 }, 1878 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1879 }; 1880 1881 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1882 { /* 60 Hz */ 1883 .clock = 6000, 1884 .hdisplay = 320, 1885 .hsync_start = 320 + 44, 1886 .hsync_end = 320 + 44 + 16, 1887 .htotal = 320 + 44 + 16 + 20, 1888 .vdisplay = 240, 1889 .vsync_start = 240 + 2, 1890 .vsync_end = 240 + 2 + 6, 1891 .vtotal = 240 + 2 + 6 + 2, 1892 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1893 }, 1894 { /* 50 Hz */ 1895 .clock = 5400, 1896 .hdisplay = 320, 1897 .hsync_start = 320 + 56, 1898 .hsync_end = 320 + 56 + 16, 1899 .htotal = 320 + 56 + 16 + 40, 1900 .vdisplay = 240, 1901 .vsync_start = 240 + 2, 1902 .vsync_end = 240 + 2 + 6, 1903 .vtotal = 240 + 2 + 6 + 2, 1904 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1905 }, 1906 }; 1907 1908 static const struct panel_desc frida_frd350h54004 = { 1909 .modes = frida_frd350h54004_modes, 1910 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1911 .bpc = 8, 1912 .size = { 1913 .width = 77, 1914 .height = 64, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1918 .connector_type = DRM_MODE_CONNECTOR_DPI, 1919 }; 1920 1921 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1922 .clock = 67185, 1923 .hdisplay = 800, 1924 .hsync_start = 800 + 20, 1925 .hsync_end = 800 + 20 + 24, 1926 .htotal = 800 + 20 + 24 + 20, 1927 .vdisplay = 1280, 1928 .vsync_start = 1280 + 4, 1929 .vsync_end = 1280 + 4 + 8, 1930 .vtotal = 1280 + 4 + 8 + 4, 1931 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1932 }; 1933 1934 static const struct panel_desc friendlyarm_hd702e = { 1935 .modes = &friendlyarm_hd702e_mode, 1936 .num_modes = 1, 1937 .size = { 1938 .width = 94, 1939 .height = 151, 1940 }, 1941 }; 1942 1943 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1944 .clock = 9000, 1945 .hdisplay = 480, 1946 .hsync_start = 480 + 5, 1947 .hsync_end = 480 + 5 + 1, 1948 .htotal = 480 + 5 + 1 + 40, 1949 .vdisplay = 272, 1950 .vsync_start = 272 + 8, 1951 .vsync_end = 272 + 8 + 1, 1952 .vtotal = 272 + 8 + 1 + 8, 1953 }; 1954 1955 static const struct panel_desc giantplus_gpg482739qs5 = { 1956 .modes = &giantplus_gpg482739qs5_mode, 1957 .num_modes = 1, 1958 .bpc = 8, 1959 .size = { 1960 .width = 95, 1961 .height = 54, 1962 }, 1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1964 }; 1965 1966 static const struct display_timing giantplus_gpm940b0_timing = { 1967 .pixelclock = { 13500000, 27000000, 27500000 }, 1968 .hactive = { 320, 320, 320 }, 1969 .hfront_porch = { 14, 686, 718 }, 1970 .hback_porch = { 50, 70, 255 }, 1971 .hsync_len = { 1, 1, 1 }, 1972 .vactive = { 240, 240, 240 }, 1973 .vfront_porch = { 1, 1, 179 }, 1974 .vback_porch = { 1, 21, 31 }, 1975 .vsync_len = { 1, 1, 6 }, 1976 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1977 }; 1978 1979 static const struct panel_desc giantplus_gpm940b0 = { 1980 .timings = &giantplus_gpm940b0_timing, 1981 .num_timings = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 60, 1985 .height = 45, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1988 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct display_timing hannstar_hsd070pww1_timing = { 1992 .pixelclock = { 64300000, 71100000, 82000000 }, 1993 .hactive = { 1280, 1280, 1280 }, 1994 .hfront_porch = { 1, 1, 10 }, 1995 .hback_porch = { 1, 1, 10 }, 1996 /* 1997 * According to the data sheet, the minimum horizontal blanking interval 1998 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1999 * minimum working horizontal blanking interval to be 60 clocks. 2000 */ 2001 .hsync_len = { 58, 158, 661 }, 2002 .vactive = { 800, 800, 800 }, 2003 .vfront_porch = { 1, 1, 10 }, 2004 .vback_porch = { 1, 1, 10 }, 2005 .vsync_len = { 1, 21, 203 }, 2006 .flags = DISPLAY_FLAGS_DE_HIGH, 2007 }; 2008 2009 static const struct panel_desc hannstar_hsd070pww1 = { 2010 .timings = &hannstar_hsd070pww1_timing, 2011 .num_timings = 1, 2012 .bpc = 6, 2013 .size = { 2014 .width = 151, 2015 .height = 94, 2016 }, 2017 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2018 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2019 }; 2020 2021 static const struct display_timing hannstar_hsd100pxn1_timing = { 2022 .pixelclock = { 55000000, 65000000, 75000000 }, 2023 .hactive = { 1024, 1024, 1024 }, 2024 .hfront_porch = { 40, 40, 40 }, 2025 .hback_porch = { 220, 220, 220 }, 2026 .hsync_len = { 20, 60, 100 }, 2027 .vactive = { 768, 768, 768 }, 2028 .vfront_porch = { 7, 7, 7 }, 2029 .vback_porch = { 21, 21, 21 }, 2030 .vsync_len = { 10, 10, 10 }, 2031 .flags = DISPLAY_FLAGS_DE_HIGH, 2032 }; 2033 2034 static const struct panel_desc hannstar_hsd100pxn1 = { 2035 .timings = &hannstar_hsd100pxn1_timing, 2036 .num_timings = 1, 2037 .bpc = 6, 2038 .size = { 2039 .width = 203, 2040 .height = 152, 2041 }, 2042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2043 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2044 }; 2045 2046 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2047 .clock = 33333, 2048 .hdisplay = 800, 2049 .hsync_start = 800 + 85, 2050 .hsync_end = 800 + 85 + 86, 2051 .htotal = 800 + 85 + 86 + 85, 2052 .vdisplay = 480, 2053 .vsync_start = 480 + 16, 2054 .vsync_end = 480 + 16 + 13, 2055 .vtotal = 480 + 16 + 13 + 16, 2056 }; 2057 2058 static const struct panel_desc hitachi_tx23d38vm0caa = { 2059 .modes = &hitachi_tx23d38vm0caa_mode, 2060 .num_modes = 1, 2061 .bpc = 6, 2062 .size = { 2063 .width = 195, 2064 .height = 117, 2065 }, 2066 .delay = { 2067 .enable = 160, 2068 .disable = 160, 2069 }, 2070 }; 2071 2072 static const struct drm_display_mode innolux_at043tn24_mode = { 2073 .clock = 9000, 2074 .hdisplay = 480, 2075 .hsync_start = 480 + 2, 2076 .hsync_end = 480 + 2 + 41, 2077 .htotal = 480 + 2 + 41 + 2, 2078 .vdisplay = 272, 2079 .vsync_start = 272 + 2, 2080 .vsync_end = 272 + 2 + 10, 2081 .vtotal = 272 + 2 + 10 + 2, 2082 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2083 }; 2084 2085 static const struct panel_desc innolux_at043tn24 = { 2086 .modes = &innolux_at043tn24_mode, 2087 .num_modes = 1, 2088 .bpc = 8, 2089 .size = { 2090 .width = 95, 2091 .height = 54, 2092 }, 2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2094 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2095 }; 2096 2097 static const struct drm_display_mode innolux_at070tn92_mode = { 2098 .clock = 33333, 2099 .hdisplay = 800, 2100 .hsync_start = 800 + 210, 2101 .hsync_end = 800 + 210 + 20, 2102 .htotal = 800 + 210 + 20 + 46, 2103 .vdisplay = 480, 2104 .vsync_start = 480 + 22, 2105 .vsync_end = 480 + 22 + 10, 2106 .vtotal = 480 + 22 + 23 + 10, 2107 }; 2108 2109 static const struct panel_desc innolux_at070tn92 = { 2110 .modes = &innolux_at070tn92_mode, 2111 .num_modes = 1, 2112 .size = { 2113 .width = 154, 2114 .height = 86, 2115 }, 2116 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2117 }; 2118 2119 static const struct display_timing innolux_g070y2_l01_timing = { 2120 .pixelclock = { 28000000, 29500000, 32000000 }, 2121 .hactive = { 800, 800, 800 }, 2122 .hfront_porch = { 61, 91, 141 }, 2123 .hback_porch = { 60, 90, 140 }, 2124 .hsync_len = { 12, 12, 12 }, 2125 .vactive = { 480, 480, 480 }, 2126 .vfront_porch = { 4, 9, 30 }, 2127 .vback_porch = { 4, 8, 28 }, 2128 .vsync_len = { 2, 2, 2 }, 2129 .flags = DISPLAY_FLAGS_DE_HIGH, 2130 }; 2131 2132 static const struct panel_desc innolux_g070y2_l01 = { 2133 .timings = &innolux_g070y2_l01_timing, 2134 .num_timings = 1, 2135 .bpc = 6, 2136 .size = { 2137 .width = 152, 2138 .height = 91, 2139 }, 2140 .delay = { 2141 .prepare = 10, 2142 .enable = 100, 2143 .disable = 100, 2144 .unprepare = 800, 2145 }, 2146 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2147 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2148 }; 2149 2150 static const struct display_timing innolux_g101ice_l01_timing = { 2151 .pixelclock = { 60400000, 71100000, 74700000 }, 2152 .hactive = { 1280, 1280, 1280 }, 2153 .hfront_porch = { 41, 80, 100 }, 2154 .hback_porch = { 40, 79, 99 }, 2155 .hsync_len = { 1, 1, 1 }, 2156 .vactive = { 800, 800, 800 }, 2157 .vfront_porch = { 5, 11, 14 }, 2158 .vback_porch = { 4, 11, 14 }, 2159 .vsync_len = { 1, 1, 1 }, 2160 .flags = DISPLAY_FLAGS_DE_HIGH, 2161 }; 2162 2163 static const struct panel_desc innolux_g101ice_l01 = { 2164 .timings = &innolux_g101ice_l01_timing, 2165 .num_timings = 1, 2166 .bpc = 8, 2167 .size = { 2168 .width = 217, 2169 .height = 135, 2170 }, 2171 .delay = { 2172 .enable = 200, 2173 .disable = 200, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2177 }; 2178 2179 static const struct display_timing innolux_g121i1_l01_timing = { 2180 .pixelclock = { 67450000, 71000000, 74550000 }, 2181 .hactive = { 1280, 1280, 1280 }, 2182 .hfront_porch = { 40, 80, 160 }, 2183 .hback_porch = { 39, 79, 159 }, 2184 .hsync_len = { 1, 1, 1 }, 2185 .vactive = { 800, 800, 800 }, 2186 .vfront_porch = { 5, 11, 100 }, 2187 .vback_porch = { 4, 11, 99 }, 2188 .vsync_len = { 1, 1, 1 }, 2189 }; 2190 2191 static const struct panel_desc innolux_g121i1_l01 = { 2192 .timings = &innolux_g121i1_l01_timing, 2193 .num_timings = 1, 2194 .bpc = 6, 2195 .size = { 2196 .width = 261, 2197 .height = 163, 2198 }, 2199 .delay = { 2200 .enable = 200, 2201 .disable = 20, 2202 }, 2203 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2204 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2205 }; 2206 2207 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2208 .clock = 65000, 2209 .hdisplay = 1024, 2210 .hsync_start = 1024 + 0, 2211 .hsync_end = 1024 + 1, 2212 .htotal = 1024 + 0 + 1 + 320, 2213 .vdisplay = 768, 2214 .vsync_start = 768 + 38, 2215 .vsync_end = 768 + 38 + 1, 2216 .vtotal = 768 + 38 + 1 + 0, 2217 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2218 }; 2219 2220 static const struct panel_desc innolux_g121x1_l03 = { 2221 .modes = &innolux_g121x1_l03_mode, 2222 .num_modes = 1, 2223 .bpc = 6, 2224 .size = { 2225 .width = 246, 2226 .height = 185, 2227 }, 2228 .delay = { 2229 .enable = 200, 2230 .unprepare = 200, 2231 .disable = 400, 2232 }, 2233 }; 2234 2235 /* 2236 * Datasheet specifies that at 60 Hz refresh rate: 2237 * - total horizontal time: { 1506, 1592, 1716 } 2238 * - total vertical time: { 788, 800, 868 } 2239 * 2240 * ...but doesn't go into exactly how that should be split into a front 2241 * porch, back porch, or sync length. For now we'll leave a single setting 2242 * here which allows a bit of tweaking of the pixel clock at the expense of 2243 * refresh rate. 2244 */ 2245 static const struct display_timing innolux_n116bge_timing = { 2246 .pixelclock = { 72600000, 76420000, 80240000 }, 2247 .hactive = { 1366, 1366, 1366 }, 2248 .hfront_porch = { 136, 136, 136 }, 2249 .hback_porch = { 60, 60, 60 }, 2250 .hsync_len = { 30, 30, 30 }, 2251 .vactive = { 768, 768, 768 }, 2252 .vfront_porch = { 8, 8, 8 }, 2253 .vback_porch = { 12, 12, 12 }, 2254 .vsync_len = { 12, 12, 12 }, 2255 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2256 }; 2257 2258 static const struct panel_desc innolux_n116bge = { 2259 .timings = &innolux_n116bge_timing, 2260 .num_timings = 1, 2261 .bpc = 6, 2262 .size = { 2263 .width = 256, 2264 .height = 144, 2265 }, 2266 }; 2267 2268 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2269 .clock = 69300, 2270 .hdisplay = 1366, 2271 .hsync_start = 1366 + 16, 2272 .hsync_end = 1366 + 16 + 34, 2273 .htotal = 1366 + 16 + 34 + 50, 2274 .vdisplay = 768, 2275 .vsync_start = 768 + 2, 2276 .vsync_end = 768 + 2 + 6, 2277 .vtotal = 768 + 2 + 6 + 12, 2278 }; 2279 2280 static const struct panel_desc innolux_n156bge_l21 = { 2281 .modes = &innolux_n156bge_l21_mode, 2282 .num_modes = 1, 2283 .bpc = 6, 2284 .size = { 2285 .width = 344, 2286 .height = 193, 2287 }, 2288 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2289 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2290 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2291 }; 2292 2293 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2294 .clock = 206016, 2295 .hdisplay = 2160, 2296 .hsync_start = 2160 + 48, 2297 .hsync_end = 2160 + 48 + 32, 2298 .htotal = 2160 + 48 + 32 + 80, 2299 .vdisplay = 1440, 2300 .vsync_start = 1440 + 3, 2301 .vsync_end = 1440 + 3 + 10, 2302 .vtotal = 1440 + 3 + 10 + 27, 2303 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2304 }; 2305 2306 static const struct panel_desc innolux_p120zdg_bf1 = { 2307 .modes = &innolux_p120zdg_bf1_mode, 2308 .num_modes = 1, 2309 .bpc = 8, 2310 .size = { 2311 .width = 254, 2312 .height = 169, 2313 }, 2314 .delay = { 2315 .hpd_absent_delay = 200, 2316 .unprepare = 500, 2317 }, 2318 }; 2319 2320 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2321 .clock = 51501, 2322 .hdisplay = 1024, 2323 .hsync_start = 1024 + 128, 2324 .hsync_end = 1024 + 128 + 64, 2325 .htotal = 1024 + 128 + 64 + 128, 2326 .vdisplay = 600, 2327 .vsync_start = 600 + 16, 2328 .vsync_end = 600 + 16 + 4, 2329 .vtotal = 600 + 16 + 4 + 16, 2330 }; 2331 2332 static const struct panel_desc innolux_zj070na_01p = { 2333 .modes = &innolux_zj070na_01p_mode, 2334 .num_modes = 1, 2335 .bpc = 6, 2336 .size = { 2337 .width = 154, 2338 .height = 90, 2339 }, 2340 }; 2341 2342 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2343 .clock = 138778, 2344 .hdisplay = 1920, 2345 .hsync_start = 1920 + 24, 2346 .hsync_end = 1920 + 24 + 48, 2347 .htotal = 1920 + 24 + 48 + 88, 2348 .vdisplay = 1080, 2349 .vsync_start = 1080 + 3, 2350 .vsync_end = 1080 + 3 + 12, 2351 .vtotal = 1080 + 3 + 12 + 17, 2352 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2353 }; 2354 2355 static const struct panel_desc ivo_m133nwf4_r0 = { 2356 .modes = &ivo_m133nwf4_r0_mode, 2357 .num_modes = 1, 2358 .bpc = 8, 2359 .size = { 2360 .width = 294, 2361 .height = 165, 2362 }, 2363 .delay = { 2364 .hpd_absent_delay = 200, 2365 .unprepare = 500, 2366 }, 2367 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2368 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2369 .connector_type = DRM_MODE_CONNECTOR_eDP, 2370 }; 2371 2372 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2373 .clock = 81000, 2374 .hdisplay = 1366, 2375 .hsync_start = 1366 + 40, 2376 .hsync_end = 1366 + 40 + 32, 2377 .htotal = 1366 + 40 + 32 + 62, 2378 .vdisplay = 768, 2379 .vsync_start = 768 + 5, 2380 .vsync_end = 768 + 5 + 5, 2381 .vtotal = 768 + 5 + 5 + 122, 2382 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2383 }; 2384 2385 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2386 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2387 .num_modes = 1, 2388 .bpc = 6, 2389 .size = { 2390 .width = 256, 2391 .height = 144, 2392 }, 2393 .delay = { 2394 .hpd_absent_delay = 200, 2395 }, 2396 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2397 .connector_type = DRM_MODE_CONNECTOR_eDP, 2398 }; 2399 2400 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2401 .pixelclock = { 5580000, 5850000, 6200000 }, 2402 .hactive = { 320, 320, 320 }, 2403 .hfront_porch = { 30, 30, 30 }, 2404 .hback_porch = { 30, 30, 30 }, 2405 .hsync_len = { 1, 5, 17 }, 2406 .vactive = { 240, 240, 240 }, 2407 .vfront_porch = { 6, 6, 6 }, 2408 .vback_porch = { 5, 5, 5 }, 2409 .vsync_len = { 1, 2, 11 }, 2410 .flags = DISPLAY_FLAGS_DE_HIGH, 2411 }; 2412 2413 static const struct panel_desc koe_tx14d24vm1bpa = { 2414 .timings = &koe_tx14d24vm1bpa_timing, 2415 .num_timings = 1, 2416 .bpc = 6, 2417 .size = { 2418 .width = 115, 2419 .height = 86, 2420 }, 2421 }; 2422 2423 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2424 .pixelclock = { 151820000, 156720000, 159780000 }, 2425 .hactive = { 1920, 1920, 1920 }, 2426 .hfront_porch = { 105, 130, 142 }, 2427 .hback_porch = { 45, 70, 82 }, 2428 .hsync_len = { 30, 30, 30 }, 2429 .vactive = { 1200, 1200, 1200}, 2430 .vfront_porch = { 3, 5, 10 }, 2431 .vback_porch = { 2, 5, 10 }, 2432 .vsync_len = { 5, 5, 5 }, 2433 }; 2434 2435 static const struct panel_desc koe_tx26d202vm0bwa = { 2436 .timings = &koe_tx26d202vm0bwa_timing, 2437 .num_timings = 1, 2438 .bpc = 8, 2439 .size = { 2440 .width = 217, 2441 .height = 136, 2442 }, 2443 .delay = { 2444 .prepare = 1000, 2445 .enable = 1000, 2446 .unprepare = 1000, 2447 .disable = 1000, 2448 }, 2449 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2450 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2451 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2452 }; 2453 2454 static const struct display_timing koe_tx31d200vm0baa_timing = { 2455 .pixelclock = { 39600000, 43200000, 48000000 }, 2456 .hactive = { 1280, 1280, 1280 }, 2457 .hfront_porch = { 16, 36, 56 }, 2458 .hback_porch = { 16, 36, 56 }, 2459 .hsync_len = { 8, 8, 8 }, 2460 .vactive = { 480, 480, 480 }, 2461 .vfront_porch = { 6, 21, 33 }, 2462 .vback_porch = { 6, 21, 33 }, 2463 .vsync_len = { 8, 8, 8 }, 2464 .flags = DISPLAY_FLAGS_DE_HIGH, 2465 }; 2466 2467 static const struct panel_desc koe_tx31d200vm0baa = { 2468 .timings = &koe_tx31d200vm0baa_timing, 2469 .num_timings = 1, 2470 .bpc = 6, 2471 .size = { 2472 .width = 292, 2473 .height = 109, 2474 }, 2475 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2477 }; 2478 2479 static const struct display_timing kyo_tcg121xglp_timing = { 2480 .pixelclock = { 52000000, 65000000, 71000000 }, 2481 .hactive = { 1024, 1024, 1024 }, 2482 .hfront_porch = { 2, 2, 2 }, 2483 .hback_porch = { 2, 2, 2 }, 2484 .hsync_len = { 86, 124, 244 }, 2485 .vactive = { 768, 768, 768 }, 2486 .vfront_porch = { 2, 2, 2 }, 2487 .vback_porch = { 2, 2, 2 }, 2488 .vsync_len = { 6, 34, 73 }, 2489 .flags = DISPLAY_FLAGS_DE_HIGH, 2490 }; 2491 2492 static const struct panel_desc kyo_tcg121xglp = { 2493 .timings = &kyo_tcg121xglp_timing, 2494 .num_timings = 1, 2495 .bpc = 8, 2496 .size = { 2497 .width = 246, 2498 .height = 184, 2499 }, 2500 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2501 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2502 }; 2503 2504 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2505 .clock = 7000, 2506 .hdisplay = 320, 2507 .hsync_start = 320 + 20, 2508 .hsync_end = 320 + 20 + 30, 2509 .htotal = 320 + 20 + 30 + 38, 2510 .vdisplay = 240, 2511 .vsync_start = 240 + 4, 2512 .vsync_end = 240 + 4 + 3, 2513 .vtotal = 240 + 4 + 3 + 15, 2514 }; 2515 2516 static const struct panel_desc lemaker_bl035_rgb_002 = { 2517 .modes = &lemaker_bl035_rgb_002_mode, 2518 .num_modes = 1, 2519 .size = { 2520 .width = 70, 2521 .height = 52, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2524 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2525 }; 2526 2527 static const struct drm_display_mode lg_lb070wv8_mode = { 2528 .clock = 33246, 2529 .hdisplay = 800, 2530 .hsync_start = 800 + 88, 2531 .hsync_end = 800 + 88 + 80, 2532 .htotal = 800 + 88 + 80 + 88, 2533 .vdisplay = 480, 2534 .vsync_start = 480 + 10, 2535 .vsync_end = 480 + 10 + 25, 2536 .vtotal = 480 + 10 + 25 + 10, 2537 }; 2538 2539 static const struct panel_desc lg_lb070wv8 = { 2540 .modes = &lg_lb070wv8_mode, 2541 .num_modes = 1, 2542 .bpc = 8, 2543 .size = { 2544 .width = 151, 2545 .height = 91, 2546 }, 2547 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2549 }; 2550 2551 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2552 .clock = 200000, 2553 .hdisplay = 1536, 2554 .hsync_start = 1536 + 12, 2555 .hsync_end = 1536 + 12 + 16, 2556 .htotal = 1536 + 12 + 16 + 48, 2557 .vdisplay = 2048, 2558 .vsync_start = 2048 + 8, 2559 .vsync_end = 2048 + 8 + 4, 2560 .vtotal = 2048 + 8 + 4 + 8, 2561 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2562 }; 2563 2564 static const struct panel_desc lg_lp079qx1_sp0v = { 2565 .modes = &lg_lp079qx1_sp0v_mode, 2566 .num_modes = 1, 2567 .size = { 2568 .width = 129, 2569 .height = 171, 2570 }, 2571 }; 2572 2573 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2574 .clock = 205210, 2575 .hdisplay = 2048, 2576 .hsync_start = 2048 + 150, 2577 .hsync_end = 2048 + 150 + 5, 2578 .htotal = 2048 + 150 + 5 + 5, 2579 .vdisplay = 1536, 2580 .vsync_start = 1536 + 3, 2581 .vsync_end = 1536 + 3 + 1, 2582 .vtotal = 1536 + 3 + 1 + 9, 2583 }; 2584 2585 static const struct panel_desc lg_lp097qx1_spa1 = { 2586 .modes = &lg_lp097qx1_spa1_mode, 2587 .num_modes = 1, 2588 .size = { 2589 .width = 208, 2590 .height = 147, 2591 }, 2592 }; 2593 2594 static const struct drm_display_mode lg_lp120up1_mode = { 2595 .clock = 162300, 2596 .hdisplay = 1920, 2597 .hsync_start = 1920 + 40, 2598 .hsync_end = 1920 + 40 + 40, 2599 .htotal = 1920 + 40 + 40+ 80, 2600 .vdisplay = 1280, 2601 .vsync_start = 1280 + 4, 2602 .vsync_end = 1280 + 4 + 4, 2603 .vtotal = 1280 + 4 + 4 + 12, 2604 }; 2605 2606 static const struct panel_desc lg_lp120up1 = { 2607 .modes = &lg_lp120up1_mode, 2608 .num_modes = 1, 2609 .bpc = 8, 2610 .size = { 2611 .width = 267, 2612 .height = 183, 2613 }, 2614 .connector_type = DRM_MODE_CONNECTOR_eDP, 2615 }; 2616 2617 static const struct drm_display_mode lg_lp129qe_mode = { 2618 .clock = 285250, 2619 .hdisplay = 2560, 2620 .hsync_start = 2560 + 48, 2621 .hsync_end = 2560 + 48 + 32, 2622 .htotal = 2560 + 48 + 32 + 80, 2623 .vdisplay = 1700, 2624 .vsync_start = 1700 + 3, 2625 .vsync_end = 1700 + 3 + 10, 2626 .vtotal = 1700 + 3 + 10 + 36, 2627 }; 2628 2629 static const struct panel_desc lg_lp129qe = { 2630 .modes = &lg_lp129qe_mode, 2631 .num_modes = 1, 2632 .bpc = 8, 2633 .size = { 2634 .width = 272, 2635 .height = 181, 2636 }, 2637 }; 2638 2639 static const struct display_timing logictechno_lt161010_2nh_timing = { 2640 .pixelclock = { 26400000, 33300000, 46800000 }, 2641 .hactive = { 800, 800, 800 }, 2642 .hfront_porch = { 16, 210, 354 }, 2643 .hback_porch = { 46, 46, 46 }, 2644 .hsync_len = { 1, 20, 40 }, 2645 .vactive = { 480, 480, 480 }, 2646 .vfront_porch = { 7, 22, 147 }, 2647 .vback_porch = { 23, 23, 23 }, 2648 .vsync_len = { 1, 10, 20 }, 2649 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2650 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2651 DISPLAY_FLAGS_SYNC_POSEDGE, 2652 }; 2653 2654 static const struct panel_desc logictechno_lt161010_2nh = { 2655 .timings = &logictechno_lt161010_2nh_timing, 2656 .num_timings = 1, 2657 .size = { 2658 .width = 154, 2659 .height = 86, 2660 }, 2661 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2662 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2663 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2664 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2665 .connector_type = DRM_MODE_CONNECTOR_DPI, 2666 }; 2667 2668 static const struct display_timing logictechno_lt170410_2whc_timing = { 2669 .pixelclock = { 68900000, 71100000, 73400000 }, 2670 .hactive = { 1280, 1280, 1280 }, 2671 .hfront_porch = { 23, 60, 71 }, 2672 .hback_porch = { 23, 60, 71 }, 2673 .hsync_len = { 15, 40, 47 }, 2674 .vactive = { 800, 800, 800 }, 2675 .vfront_porch = { 5, 7, 10 }, 2676 .vback_porch = { 5, 7, 10 }, 2677 .vsync_len = { 6, 9, 12 }, 2678 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2679 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2680 DISPLAY_FLAGS_SYNC_POSEDGE, 2681 }; 2682 2683 static const struct panel_desc logictechno_lt170410_2whc = { 2684 .timings = &logictechno_lt170410_2whc_timing, 2685 .num_timings = 1, 2686 .size = { 2687 .width = 217, 2688 .height = 136, 2689 }, 2690 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2691 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2692 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2693 }; 2694 2695 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2696 .clock = 30400, 2697 .hdisplay = 800, 2698 .hsync_start = 800 + 0, 2699 .hsync_end = 800 + 1, 2700 .htotal = 800 + 0 + 1 + 160, 2701 .vdisplay = 480, 2702 .vsync_start = 480 + 0, 2703 .vsync_end = 480 + 48 + 1, 2704 .vtotal = 480 + 48 + 1 + 0, 2705 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2706 }; 2707 2708 static const struct drm_display_mode logicpd_type_28_mode = { 2709 .clock = 9107, 2710 .hdisplay = 480, 2711 .hsync_start = 480 + 3, 2712 .hsync_end = 480 + 3 + 42, 2713 .htotal = 480 + 3 + 42 + 2, 2714 2715 .vdisplay = 272, 2716 .vsync_start = 272 + 2, 2717 .vsync_end = 272 + 2 + 11, 2718 .vtotal = 272 + 2 + 11 + 3, 2719 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2720 }; 2721 2722 static const struct panel_desc logicpd_type_28 = { 2723 .modes = &logicpd_type_28_mode, 2724 .num_modes = 1, 2725 .bpc = 8, 2726 .size = { 2727 .width = 105, 2728 .height = 67, 2729 }, 2730 .delay = { 2731 .prepare = 200, 2732 .enable = 200, 2733 .unprepare = 200, 2734 .disable = 200, 2735 }, 2736 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2737 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2738 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2739 .connector_type = DRM_MODE_CONNECTOR_DPI, 2740 }; 2741 2742 static const struct panel_desc mitsubishi_aa070mc01 = { 2743 .modes = &mitsubishi_aa070mc01_mode, 2744 .num_modes = 1, 2745 .bpc = 8, 2746 .size = { 2747 .width = 152, 2748 .height = 91, 2749 }, 2750 2751 .delay = { 2752 .enable = 200, 2753 .unprepare = 200, 2754 .disable = 400, 2755 }, 2756 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2757 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2758 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2759 }; 2760 2761 static const struct display_timing nec_nl12880bc20_05_timing = { 2762 .pixelclock = { 67000000, 71000000, 75000000 }, 2763 .hactive = { 1280, 1280, 1280 }, 2764 .hfront_porch = { 2, 30, 30 }, 2765 .hback_porch = { 6, 100, 100 }, 2766 .hsync_len = { 2, 30, 30 }, 2767 .vactive = { 800, 800, 800 }, 2768 .vfront_porch = { 5, 5, 5 }, 2769 .vback_porch = { 11, 11, 11 }, 2770 .vsync_len = { 7, 7, 7 }, 2771 }; 2772 2773 static const struct panel_desc nec_nl12880bc20_05 = { 2774 .timings = &nec_nl12880bc20_05_timing, 2775 .num_timings = 1, 2776 .bpc = 8, 2777 .size = { 2778 .width = 261, 2779 .height = 163, 2780 }, 2781 .delay = { 2782 .enable = 50, 2783 .disable = 50, 2784 }, 2785 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2787 }; 2788 2789 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2790 .clock = 10870, 2791 .hdisplay = 480, 2792 .hsync_start = 480 + 2, 2793 .hsync_end = 480 + 2 + 41, 2794 .htotal = 480 + 2 + 41 + 2, 2795 .vdisplay = 272, 2796 .vsync_start = 272 + 2, 2797 .vsync_end = 272 + 2 + 4, 2798 .vtotal = 272 + 2 + 4 + 2, 2799 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2800 }; 2801 2802 static const struct panel_desc nec_nl4827hc19_05b = { 2803 .modes = &nec_nl4827hc19_05b_mode, 2804 .num_modes = 1, 2805 .bpc = 8, 2806 .size = { 2807 .width = 95, 2808 .height = 54, 2809 }, 2810 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2811 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2812 }; 2813 2814 static const struct drm_display_mode netron_dy_e231732_mode = { 2815 .clock = 66000, 2816 .hdisplay = 1024, 2817 .hsync_start = 1024 + 160, 2818 .hsync_end = 1024 + 160 + 70, 2819 .htotal = 1024 + 160 + 70 + 90, 2820 .vdisplay = 600, 2821 .vsync_start = 600 + 127, 2822 .vsync_end = 600 + 127 + 20, 2823 .vtotal = 600 + 127 + 20 + 3, 2824 }; 2825 2826 static const struct panel_desc netron_dy_e231732 = { 2827 .modes = &netron_dy_e231732_mode, 2828 .num_modes = 1, 2829 .size = { 2830 .width = 154, 2831 .height = 87, 2832 }, 2833 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2834 }; 2835 2836 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2837 { 2838 .clock = 138500, 2839 .hdisplay = 1920, 2840 .hsync_start = 1920 + 48, 2841 .hsync_end = 1920 + 48 + 32, 2842 .htotal = 1920 + 48 + 32 + 80, 2843 .vdisplay = 1080, 2844 .vsync_start = 1080 + 3, 2845 .vsync_end = 1080 + 3 + 5, 2846 .vtotal = 1080 + 3 + 5 + 23, 2847 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2848 }, { 2849 .clock = 110920, 2850 .hdisplay = 1920, 2851 .hsync_start = 1920 + 48, 2852 .hsync_end = 1920 + 48 + 32, 2853 .htotal = 1920 + 48 + 32 + 80, 2854 .vdisplay = 1080, 2855 .vsync_start = 1080 + 3, 2856 .vsync_end = 1080 + 3 + 5, 2857 .vtotal = 1080 + 3 + 5 + 23, 2858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2859 } 2860 }; 2861 2862 static const struct panel_desc neweast_wjfh116008a = { 2863 .modes = neweast_wjfh116008a_modes, 2864 .num_modes = 2, 2865 .bpc = 6, 2866 .size = { 2867 .width = 260, 2868 .height = 150, 2869 }, 2870 .delay = { 2871 .prepare = 110, 2872 .enable = 20, 2873 .unprepare = 500, 2874 }, 2875 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2876 .connector_type = DRM_MODE_CONNECTOR_eDP, 2877 }; 2878 2879 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2880 .clock = 9000, 2881 .hdisplay = 480, 2882 .hsync_start = 480 + 2, 2883 .hsync_end = 480 + 2 + 41, 2884 .htotal = 480 + 2 + 41 + 2, 2885 .vdisplay = 272, 2886 .vsync_start = 272 + 2, 2887 .vsync_end = 272 + 2 + 10, 2888 .vtotal = 272 + 2 + 10 + 2, 2889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2890 }; 2891 2892 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2893 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2894 .num_modes = 1, 2895 .bpc = 8, 2896 .size = { 2897 .width = 95, 2898 .height = 54, 2899 }, 2900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2902 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2903 .connector_type = DRM_MODE_CONNECTOR_DPI, 2904 }; 2905 2906 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2907 .pixelclock = { 130000000, 148350000, 163000000 }, 2908 .hactive = { 1920, 1920, 1920 }, 2909 .hfront_porch = { 80, 100, 100 }, 2910 .hback_porch = { 100, 120, 120 }, 2911 .hsync_len = { 50, 60, 60 }, 2912 .vactive = { 1080, 1080, 1080 }, 2913 .vfront_porch = { 12, 30, 30 }, 2914 .vback_porch = { 4, 10, 10 }, 2915 .vsync_len = { 4, 5, 5 }, 2916 }; 2917 2918 static const struct panel_desc nlt_nl192108ac18_02d = { 2919 .timings = &nlt_nl192108ac18_02d_timing, 2920 .num_timings = 1, 2921 .bpc = 8, 2922 .size = { 2923 .width = 344, 2924 .height = 194, 2925 }, 2926 .delay = { 2927 .unprepare = 500, 2928 }, 2929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2930 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2931 }; 2932 2933 static const struct drm_display_mode nvd_9128_mode = { 2934 .clock = 29500, 2935 .hdisplay = 800, 2936 .hsync_start = 800 + 130, 2937 .hsync_end = 800 + 130 + 98, 2938 .htotal = 800 + 0 + 130 + 98, 2939 .vdisplay = 480, 2940 .vsync_start = 480 + 10, 2941 .vsync_end = 480 + 10 + 50, 2942 .vtotal = 480 + 0 + 10 + 50, 2943 }; 2944 2945 static const struct panel_desc nvd_9128 = { 2946 .modes = &nvd_9128_mode, 2947 .num_modes = 1, 2948 .bpc = 8, 2949 .size = { 2950 .width = 156, 2951 .height = 88, 2952 }, 2953 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2954 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2955 }; 2956 2957 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2958 .pixelclock = { 30000000, 30000000, 40000000 }, 2959 .hactive = { 800, 800, 800 }, 2960 .hfront_porch = { 40, 40, 40 }, 2961 .hback_porch = { 40, 40, 40 }, 2962 .hsync_len = { 1, 48, 48 }, 2963 .vactive = { 480, 480, 480 }, 2964 .vfront_porch = { 13, 13, 13 }, 2965 .vback_porch = { 29, 29, 29 }, 2966 .vsync_len = { 3, 3, 3 }, 2967 .flags = DISPLAY_FLAGS_DE_HIGH, 2968 }; 2969 2970 static const struct panel_desc okaya_rs800480t_7x0gp = { 2971 .timings = &okaya_rs800480t_7x0gp_timing, 2972 .num_timings = 1, 2973 .bpc = 6, 2974 .size = { 2975 .width = 154, 2976 .height = 87, 2977 }, 2978 .delay = { 2979 .prepare = 41, 2980 .enable = 50, 2981 .unprepare = 41, 2982 .disable = 50, 2983 }, 2984 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2985 }; 2986 2987 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2988 .clock = 9000, 2989 .hdisplay = 480, 2990 .hsync_start = 480 + 5, 2991 .hsync_end = 480 + 5 + 30, 2992 .htotal = 480 + 5 + 30 + 10, 2993 .vdisplay = 272, 2994 .vsync_start = 272 + 8, 2995 .vsync_end = 272 + 8 + 5, 2996 .vtotal = 272 + 8 + 5 + 3, 2997 }; 2998 2999 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3000 .modes = &olimex_lcd_olinuxino_43ts_mode, 3001 .num_modes = 1, 3002 .size = { 3003 .width = 95, 3004 .height = 54, 3005 }, 3006 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3007 }; 3008 3009 /* 3010 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3011 * pixel clocks, but this is the timing that was being used in the Adafruit 3012 * installation instructions. 3013 */ 3014 static const struct drm_display_mode ontat_yx700wv03_mode = { 3015 .clock = 29500, 3016 .hdisplay = 800, 3017 .hsync_start = 824, 3018 .hsync_end = 896, 3019 .htotal = 992, 3020 .vdisplay = 480, 3021 .vsync_start = 483, 3022 .vsync_end = 493, 3023 .vtotal = 500, 3024 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3025 }; 3026 3027 /* 3028 * Specification at: 3029 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3030 */ 3031 static const struct panel_desc ontat_yx700wv03 = { 3032 .modes = &ontat_yx700wv03_mode, 3033 .num_modes = 1, 3034 .bpc = 8, 3035 .size = { 3036 .width = 154, 3037 .height = 83, 3038 }, 3039 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3040 }; 3041 3042 static const struct drm_display_mode ortustech_com37h3m_mode = { 3043 .clock = 22230, 3044 .hdisplay = 480, 3045 .hsync_start = 480 + 40, 3046 .hsync_end = 480 + 40 + 10, 3047 .htotal = 480 + 40 + 10 + 40, 3048 .vdisplay = 640, 3049 .vsync_start = 640 + 4, 3050 .vsync_end = 640 + 4 + 2, 3051 .vtotal = 640 + 4 + 2 + 4, 3052 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3053 }; 3054 3055 static const struct panel_desc ortustech_com37h3m = { 3056 .modes = &ortustech_com37h3m_mode, 3057 .num_modes = 1, 3058 .bpc = 8, 3059 .size = { 3060 .width = 56, /* 56.16mm */ 3061 .height = 75, /* 74.88mm */ 3062 }, 3063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3064 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3065 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3066 }; 3067 3068 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3069 .clock = 25000, 3070 .hdisplay = 480, 3071 .hsync_start = 480 + 10, 3072 .hsync_end = 480 + 10 + 10, 3073 .htotal = 480 + 10 + 10 + 15, 3074 .vdisplay = 800, 3075 .vsync_start = 800 + 3, 3076 .vsync_end = 800 + 3 + 3, 3077 .vtotal = 800 + 3 + 3 + 3, 3078 }; 3079 3080 static const struct panel_desc ortustech_com43h4m85ulc = { 3081 .modes = &ortustech_com43h4m85ulc_mode, 3082 .num_modes = 1, 3083 .bpc = 6, 3084 .size = { 3085 .width = 56, 3086 .height = 93, 3087 }, 3088 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3089 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3090 .connector_type = DRM_MODE_CONNECTOR_DPI, 3091 }; 3092 3093 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3094 .clock = 33000, 3095 .hdisplay = 800, 3096 .hsync_start = 800 + 210, 3097 .hsync_end = 800 + 210 + 30, 3098 .htotal = 800 + 210 + 30 + 16, 3099 .vdisplay = 480, 3100 .vsync_start = 480 + 22, 3101 .vsync_end = 480 + 22 + 13, 3102 .vtotal = 480 + 22 + 13 + 10, 3103 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3104 }; 3105 3106 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3107 .modes = &osddisplays_osd070t1718_19ts_mode, 3108 .num_modes = 1, 3109 .bpc = 8, 3110 .size = { 3111 .width = 152, 3112 .height = 91, 3113 }, 3114 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3115 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3116 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3117 .connector_type = DRM_MODE_CONNECTOR_DPI, 3118 }; 3119 3120 static const struct drm_display_mode pda_91_00156_a0_mode = { 3121 .clock = 33300, 3122 .hdisplay = 800, 3123 .hsync_start = 800 + 1, 3124 .hsync_end = 800 + 1 + 64, 3125 .htotal = 800 + 1 + 64 + 64, 3126 .vdisplay = 480, 3127 .vsync_start = 480 + 1, 3128 .vsync_end = 480 + 1 + 23, 3129 .vtotal = 480 + 1 + 23 + 22, 3130 }; 3131 3132 static const struct panel_desc pda_91_00156_a0 = { 3133 .modes = &pda_91_00156_a0_mode, 3134 .num_modes = 1, 3135 .size = { 3136 .width = 152, 3137 .height = 91, 3138 }, 3139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3140 }; 3141 3142 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3143 .clock = 24750, 3144 .hdisplay = 800, 3145 .hsync_start = 800 + 54, 3146 .hsync_end = 800 + 54 + 2, 3147 .htotal = 800 + 54 + 2 + 44, 3148 .vdisplay = 480, 3149 .vsync_start = 480 + 49, 3150 .vsync_end = 480 + 49 + 2, 3151 .vtotal = 480 + 49 + 2 + 22, 3152 }; 3153 3154 static const struct panel_desc powertip_ph800480t013_idf02 = { 3155 .modes = &powertip_ph800480t013_idf02_mode, 3156 .num_modes = 1, 3157 .size = { 3158 .width = 152, 3159 .height = 91, 3160 }, 3161 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3162 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3163 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3164 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3165 .connector_type = DRM_MODE_CONNECTOR_DPI, 3166 }; 3167 3168 static const struct drm_display_mode qd43003c0_40_mode = { 3169 .clock = 9000, 3170 .hdisplay = 480, 3171 .hsync_start = 480 + 8, 3172 .hsync_end = 480 + 8 + 4, 3173 .htotal = 480 + 8 + 4 + 39, 3174 .vdisplay = 272, 3175 .vsync_start = 272 + 4, 3176 .vsync_end = 272 + 4 + 10, 3177 .vtotal = 272 + 4 + 10 + 2, 3178 }; 3179 3180 static const struct panel_desc qd43003c0_40 = { 3181 .modes = &qd43003c0_40_mode, 3182 .num_modes = 1, 3183 .bpc = 8, 3184 .size = { 3185 .width = 95, 3186 .height = 53, 3187 }, 3188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3189 }; 3190 3191 static const struct display_timing rocktech_rk070er9427_timing = { 3192 .pixelclock = { 26400000, 33300000, 46800000 }, 3193 .hactive = { 800, 800, 800 }, 3194 .hfront_porch = { 16, 210, 354 }, 3195 .hback_porch = { 46, 46, 46 }, 3196 .hsync_len = { 1, 1, 1 }, 3197 .vactive = { 480, 480, 480 }, 3198 .vfront_porch = { 7, 22, 147 }, 3199 .vback_porch = { 23, 23, 23 }, 3200 .vsync_len = { 1, 1, 1 }, 3201 .flags = DISPLAY_FLAGS_DE_HIGH, 3202 }; 3203 3204 static const struct panel_desc rocktech_rk070er9427 = { 3205 .timings = &rocktech_rk070er9427_timing, 3206 .num_timings = 1, 3207 .bpc = 6, 3208 .size = { 3209 .width = 154, 3210 .height = 86, 3211 }, 3212 .delay = { 3213 .prepare = 41, 3214 .enable = 50, 3215 .unprepare = 41, 3216 .disable = 50, 3217 }, 3218 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3219 }; 3220 3221 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3222 .clock = 71100, 3223 .hdisplay = 1280, 3224 .hsync_start = 1280 + 48, 3225 .hsync_end = 1280 + 48 + 32, 3226 .htotal = 1280 + 48 + 32 + 80, 3227 .vdisplay = 800, 3228 .vsync_start = 800 + 2, 3229 .vsync_end = 800 + 2 + 5, 3230 .vtotal = 800 + 2 + 5 + 16, 3231 }; 3232 3233 static const struct panel_desc rocktech_rk101ii01d_ct = { 3234 .modes = &rocktech_rk101ii01d_ct_mode, 3235 .num_modes = 1, 3236 .size = { 3237 .width = 217, 3238 .height = 136, 3239 }, 3240 .delay = { 3241 .prepare = 50, 3242 .disable = 50, 3243 }, 3244 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3245 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3246 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3247 }; 3248 3249 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3250 .clock = 271560, 3251 .hdisplay = 2560, 3252 .hsync_start = 2560 + 48, 3253 .hsync_end = 2560 + 48 + 32, 3254 .htotal = 2560 + 48 + 32 + 80, 3255 .vdisplay = 1600, 3256 .vsync_start = 1600 + 2, 3257 .vsync_end = 1600 + 2 + 5, 3258 .vtotal = 1600 + 2 + 5 + 57, 3259 }; 3260 3261 static const struct panel_desc samsung_lsn122dl01_c01 = { 3262 .modes = &samsung_lsn122dl01_c01_mode, 3263 .num_modes = 1, 3264 .size = { 3265 .width = 263, 3266 .height = 164, 3267 }, 3268 }; 3269 3270 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3271 .clock = 54030, 3272 .hdisplay = 1024, 3273 .hsync_start = 1024 + 24, 3274 .hsync_end = 1024 + 24 + 136, 3275 .htotal = 1024 + 24 + 136 + 160, 3276 .vdisplay = 600, 3277 .vsync_start = 600 + 3, 3278 .vsync_end = 600 + 3 + 6, 3279 .vtotal = 600 + 3 + 6 + 61, 3280 }; 3281 3282 static const struct panel_desc samsung_ltn101nt05 = { 3283 .modes = &samsung_ltn101nt05_mode, 3284 .num_modes = 1, 3285 .bpc = 6, 3286 .size = { 3287 .width = 223, 3288 .height = 125, 3289 }, 3290 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3291 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3292 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3293 }; 3294 3295 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3296 .clock = 76300, 3297 .hdisplay = 1366, 3298 .hsync_start = 1366 + 64, 3299 .hsync_end = 1366 + 64 + 48, 3300 .htotal = 1366 + 64 + 48 + 128, 3301 .vdisplay = 768, 3302 .vsync_start = 768 + 2, 3303 .vsync_end = 768 + 2 + 5, 3304 .vtotal = 768 + 2 + 5 + 17, 3305 }; 3306 3307 static const struct panel_desc samsung_ltn140at29_301 = { 3308 .modes = &samsung_ltn140at29_301_mode, 3309 .num_modes = 1, 3310 .bpc = 6, 3311 .size = { 3312 .width = 320, 3313 .height = 187, 3314 }, 3315 }; 3316 3317 static const struct display_timing satoz_sat050at40h12r2_timing = { 3318 .pixelclock = {33300000, 33300000, 50000000}, 3319 .hactive = {800, 800, 800}, 3320 .hfront_porch = {16, 210, 354}, 3321 .hback_porch = {46, 46, 46}, 3322 .hsync_len = {1, 1, 40}, 3323 .vactive = {480, 480, 480}, 3324 .vfront_porch = {7, 22, 147}, 3325 .vback_porch = {23, 23, 23}, 3326 .vsync_len = {1, 1, 20}, 3327 }; 3328 3329 static const struct panel_desc satoz_sat050at40h12r2 = { 3330 .timings = &satoz_sat050at40h12r2_timing, 3331 .num_timings = 1, 3332 .bpc = 8, 3333 .size = { 3334 .width = 108, 3335 .height = 65, 3336 }, 3337 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3338 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3339 }; 3340 3341 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3342 .clock = 168480, 3343 .hdisplay = 1920, 3344 .hsync_start = 1920 + 48, 3345 .hsync_end = 1920 + 48 + 32, 3346 .htotal = 1920 + 48 + 32 + 80, 3347 .vdisplay = 1280, 3348 .vsync_start = 1280 + 3, 3349 .vsync_end = 1280 + 3 + 10, 3350 .vtotal = 1280 + 3 + 10 + 57, 3351 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3352 }; 3353 3354 static const struct panel_desc sharp_ld_d5116z01b = { 3355 .modes = &sharp_ld_d5116z01b_mode, 3356 .num_modes = 1, 3357 .bpc = 8, 3358 .size = { 3359 .width = 260, 3360 .height = 120, 3361 }, 3362 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3363 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3364 }; 3365 3366 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3367 .clock = 33260, 3368 .hdisplay = 800, 3369 .hsync_start = 800 + 64, 3370 .hsync_end = 800 + 64 + 128, 3371 .htotal = 800 + 64 + 128 + 64, 3372 .vdisplay = 480, 3373 .vsync_start = 480 + 8, 3374 .vsync_end = 480 + 8 + 2, 3375 .vtotal = 480 + 8 + 2 + 35, 3376 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3377 }; 3378 3379 static const struct panel_desc sharp_lq070y3dg3b = { 3380 .modes = &sharp_lq070y3dg3b_mode, 3381 .num_modes = 1, 3382 .bpc = 8, 3383 .size = { 3384 .width = 152, /* 152.4mm */ 3385 .height = 91, /* 91.4mm */ 3386 }, 3387 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3388 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3389 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3390 }; 3391 3392 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3393 .clock = 5500, 3394 .hdisplay = 240, 3395 .hsync_start = 240 + 16, 3396 .hsync_end = 240 + 16 + 7, 3397 .htotal = 240 + 16 + 7 + 5, 3398 .vdisplay = 320, 3399 .vsync_start = 320 + 9, 3400 .vsync_end = 320 + 9 + 1, 3401 .vtotal = 320 + 9 + 1 + 7, 3402 }; 3403 3404 static const struct panel_desc sharp_lq035q7db03 = { 3405 .modes = &sharp_lq035q7db03_mode, 3406 .num_modes = 1, 3407 .bpc = 6, 3408 .size = { 3409 .width = 54, 3410 .height = 72, 3411 }, 3412 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3413 }; 3414 3415 static const struct display_timing sharp_lq101k1ly04_timing = { 3416 .pixelclock = { 60000000, 65000000, 80000000 }, 3417 .hactive = { 1280, 1280, 1280 }, 3418 .hfront_porch = { 20, 20, 20 }, 3419 .hback_porch = { 20, 20, 20 }, 3420 .hsync_len = { 10, 10, 10 }, 3421 .vactive = { 800, 800, 800 }, 3422 .vfront_porch = { 4, 4, 4 }, 3423 .vback_porch = { 4, 4, 4 }, 3424 .vsync_len = { 4, 4, 4 }, 3425 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3426 }; 3427 3428 static const struct panel_desc sharp_lq101k1ly04 = { 3429 .timings = &sharp_lq101k1ly04_timing, 3430 .num_timings = 1, 3431 .bpc = 8, 3432 .size = { 3433 .width = 217, 3434 .height = 136, 3435 }, 3436 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3437 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3438 }; 3439 3440 static const struct display_timing sharp_lq123p1jx31_timing = { 3441 .pixelclock = { 252750000, 252750000, 266604720 }, 3442 .hactive = { 2400, 2400, 2400 }, 3443 .hfront_porch = { 48, 48, 48 }, 3444 .hback_porch = { 80, 80, 84 }, 3445 .hsync_len = { 32, 32, 32 }, 3446 .vactive = { 1600, 1600, 1600 }, 3447 .vfront_porch = { 3, 3, 3 }, 3448 .vback_porch = { 33, 33, 120 }, 3449 .vsync_len = { 10, 10, 10 }, 3450 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3451 }; 3452 3453 static const struct panel_desc sharp_lq123p1jx31 = { 3454 .timings = &sharp_lq123p1jx31_timing, 3455 .num_timings = 1, 3456 .bpc = 8, 3457 .size = { 3458 .width = 259, 3459 .height = 173, 3460 }, 3461 .delay = { 3462 .prepare = 110, 3463 .enable = 50, 3464 .unprepare = 550, 3465 }, 3466 }; 3467 3468 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3469 { /* 50 Hz */ 3470 .clock = 3000, 3471 .hdisplay = 240, 3472 .hsync_start = 240 + 58, 3473 .hsync_end = 240 + 58 + 1, 3474 .htotal = 240 + 58 + 1 + 1, 3475 .vdisplay = 160, 3476 .vsync_start = 160 + 24, 3477 .vsync_end = 160 + 24 + 10, 3478 .vtotal = 160 + 24 + 10 + 6, 3479 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3480 }, 3481 { /* 60 Hz */ 3482 .clock = 3000, 3483 .hdisplay = 240, 3484 .hsync_start = 240 + 8, 3485 .hsync_end = 240 + 8 + 1, 3486 .htotal = 240 + 8 + 1 + 1, 3487 .vdisplay = 160, 3488 .vsync_start = 160 + 24, 3489 .vsync_end = 160 + 24 + 10, 3490 .vtotal = 160 + 24 + 10 + 6, 3491 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3492 }, 3493 }; 3494 3495 static const struct panel_desc sharp_ls020b1dd01d = { 3496 .modes = sharp_ls020b1dd01d_modes, 3497 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3498 .bpc = 6, 3499 .size = { 3500 .width = 42, 3501 .height = 28, 3502 }, 3503 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3504 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3505 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3506 | DRM_BUS_FLAG_SHARP_SIGNALS, 3507 }; 3508 3509 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3510 .clock = 33300, 3511 .hdisplay = 800, 3512 .hsync_start = 800 + 1, 3513 .hsync_end = 800 + 1 + 64, 3514 .htotal = 800 + 1 + 64 + 64, 3515 .vdisplay = 480, 3516 .vsync_start = 480 + 1, 3517 .vsync_end = 480 + 1 + 23, 3518 .vtotal = 480 + 1 + 23 + 22, 3519 }; 3520 3521 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3522 .modes = &shelly_sca07010_bfn_lnn_mode, 3523 .num_modes = 1, 3524 .size = { 3525 .width = 152, 3526 .height = 91, 3527 }, 3528 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3529 }; 3530 3531 static const struct drm_display_mode starry_kr070pe2t_mode = { 3532 .clock = 33000, 3533 .hdisplay = 800, 3534 .hsync_start = 800 + 209, 3535 .hsync_end = 800 + 209 + 1, 3536 .htotal = 800 + 209 + 1 + 45, 3537 .vdisplay = 480, 3538 .vsync_start = 480 + 22, 3539 .vsync_end = 480 + 22 + 1, 3540 .vtotal = 480 + 22 + 1 + 22, 3541 }; 3542 3543 static const struct panel_desc starry_kr070pe2t = { 3544 .modes = &starry_kr070pe2t_mode, 3545 .num_modes = 1, 3546 .bpc = 8, 3547 .size = { 3548 .width = 152, 3549 .height = 86, 3550 }, 3551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3552 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3553 .connector_type = DRM_MODE_CONNECTOR_DPI, 3554 }; 3555 3556 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3557 .clock = 147000, 3558 .hdisplay = 1920, 3559 .hsync_start = 1920 + 16, 3560 .hsync_end = 1920 + 16 + 16, 3561 .htotal = 1920 + 16 + 16 + 32, 3562 .vdisplay = 1200, 3563 .vsync_start = 1200 + 15, 3564 .vsync_end = 1200 + 15 + 2, 3565 .vtotal = 1200 + 15 + 2 + 18, 3566 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3567 }; 3568 3569 static const struct panel_desc starry_kr122ea0sra = { 3570 .modes = &starry_kr122ea0sra_mode, 3571 .num_modes = 1, 3572 .size = { 3573 .width = 263, 3574 .height = 164, 3575 }, 3576 .delay = { 3577 .prepare = 10 + 200, 3578 .enable = 50, 3579 .unprepare = 10 + 500, 3580 }, 3581 }; 3582 3583 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3584 .clock = 30000, 3585 .hdisplay = 800, 3586 .hsync_start = 800 + 39, 3587 .hsync_end = 800 + 39 + 47, 3588 .htotal = 800 + 39 + 47 + 39, 3589 .vdisplay = 480, 3590 .vsync_start = 480 + 13, 3591 .vsync_end = 480 + 13 + 2, 3592 .vtotal = 480 + 13 + 2 + 29, 3593 }; 3594 3595 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3596 .modes = &tfc_s9700rtwv43tr_01b_mode, 3597 .num_modes = 1, 3598 .bpc = 8, 3599 .size = { 3600 .width = 155, 3601 .height = 90, 3602 }, 3603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3604 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3605 }; 3606 3607 static const struct display_timing tianma_tm070jdhg30_timing = { 3608 .pixelclock = { 62600000, 68200000, 78100000 }, 3609 .hactive = { 1280, 1280, 1280 }, 3610 .hfront_porch = { 15, 64, 159 }, 3611 .hback_porch = { 5, 5, 5 }, 3612 .hsync_len = { 1, 1, 256 }, 3613 .vactive = { 800, 800, 800 }, 3614 .vfront_porch = { 3, 40, 99 }, 3615 .vback_porch = { 2, 2, 2 }, 3616 .vsync_len = { 1, 1, 128 }, 3617 .flags = DISPLAY_FLAGS_DE_HIGH, 3618 }; 3619 3620 static const struct panel_desc tianma_tm070jdhg30 = { 3621 .timings = &tianma_tm070jdhg30_timing, 3622 .num_timings = 1, 3623 .bpc = 8, 3624 .size = { 3625 .width = 151, 3626 .height = 95, 3627 }, 3628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3629 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3630 }; 3631 3632 static const struct panel_desc tianma_tm070jvhg33 = { 3633 .timings = &tianma_tm070jdhg30_timing, 3634 .num_timings = 1, 3635 .bpc = 8, 3636 .size = { 3637 .width = 150, 3638 .height = 94, 3639 }, 3640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3642 }; 3643 3644 static const struct display_timing tianma_tm070rvhg71_timing = { 3645 .pixelclock = { 27700000, 29200000, 39600000 }, 3646 .hactive = { 800, 800, 800 }, 3647 .hfront_porch = { 12, 40, 212 }, 3648 .hback_porch = { 88, 88, 88 }, 3649 .hsync_len = { 1, 1, 40 }, 3650 .vactive = { 480, 480, 480 }, 3651 .vfront_porch = { 1, 13, 88 }, 3652 .vback_porch = { 32, 32, 32 }, 3653 .vsync_len = { 1, 1, 3 }, 3654 .flags = DISPLAY_FLAGS_DE_HIGH, 3655 }; 3656 3657 static const struct panel_desc tianma_tm070rvhg71 = { 3658 .timings = &tianma_tm070rvhg71_timing, 3659 .num_timings = 1, 3660 .bpc = 8, 3661 .size = { 3662 .width = 154, 3663 .height = 86, 3664 }, 3665 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3666 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3667 }; 3668 3669 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3670 { 3671 .clock = 10000, 3672 .hdisplay = 320, 3673 .hsync_start = 320 + 50, 3674 .hsync_end = 320 + 50 + 6, 3675 .htotal = 320 + 50 + 6 + 38, 3676 .vdisplay = 240, 3677 .vsync_start = 240 + 3, 3678 .vsync_end = 240 + 3 + 1, 3679 .vtotal = 240 + 3 + 1 + 17, 3680 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3681 }, 3682 }; 3683 3684 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3685 .modes = ti_nspire_cx_lcd_mode, 3686 .num_modes = 1, 3687 .bpc = 8, 3688 .size = { 3689 .width = 65, 3690 .height = 49, 3691 }, 3692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3693 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3694 }; 3695 3696 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3697 { 3698 .clock = 10000, 3699 .hdisplay = 320, 3700 .hsync_start = 320 + 6, 3701 .hsync_end = 320 + 6 + 6, 3702 .htotal = 320 + 6 + 6 + 6, 3703 .vdisplay = 240, 3704 .vsync_start = 240 + 0, 3705 .vsync_end = 240 + 0 + 1, 3706 .vtotal = 240 + 0 + 1 + 0, 3707 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3708 }, 3709 }; 3710 3711 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3712 .modes = ti_nspire_classic_lcd_mode, 3713 .num_modes = 1, 3714 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3715 .bpc = 8, 3716 .size = { 3717 .width = 71, 3718 .height = 53, 3719 }, 3720 /* This is the grayscale bus format */ 3721 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3722 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3723 }; 3724 3725 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3726 .clock = 79500, 3727 .hdisplay = 1280, 3728 .hsync_start = 1280 + 192, 3729 .hsync_end = 1280 + 192 + 128, 3730 .htotal = 1280 + 192 + 128 + 64, 3731 .vdisplay = 768, 3732 .vsync_start = 768 + 20, 3733 .vsync_end = 768 + 20 + 7, 3734 .vtotal = 768 + 20 + 7 + 3, 3735 }; 3736 3737 static const struct panel_desc toshiba_lt089ac29000 = { 3738 .modes = &toshiba_lt089ac29000_mode, 3739 .num_modes = 1, 3740 .size = { 3741 .width = 194, 3742 .height = 116, 3743 }, 3744 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3745 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3746 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3747 }; 3748 3749 static const struct drm_display_mode tpk_f07a_0102_mode = { 3750 .clock = 33260, 3751 .hdisplay = 800, 3752 .hsync_start = 800 + 40, 3753 .hsync_end = 800 + 40 + 128, 3754 .htotal = 800 + 40 + 128 + 88, 3755 .vdisplay = 480, 3756 .vsync_start = 480 + 10, 3757 .vsync_end = 480 + 10 + 2, 3758 .vtotal = 480 + 10 + 2 + 33, 3759 }; 3760 3761 static const struct panel_desc tpk_f07a_0102 = { 3762 .modes = &tpk_f07a_0102_mode, 3763 .num_modes = 1, 3764 .size = { 3765 .width = 152, 3766 .height = 91, 3767 }, 3768 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3769 }; 3770 3771 static const struct drm_display_mode tpk_f10a_0102_mode = { 3772 .clock = 45000, 3773 .hdisplay = 1024, 3774 .hsync_start = 1024 + 176, 3775 .hsync_end = 1024 + 176 + 5, 3776 .htotal = 1024 + 176 + 5 + 88, 3777 .vdisplay = 600, 3778 .vsync_start = 600 + 20, 3779 .vsync_end = 600 + 20 + 5, 3780 .vtotal = 600 + 20 + 5 + 25, 3781 }; 3782 3783 static const struct panel_desc tpk_f10a_0102 = { 3784 .modes = &tpk_f10a_0102_mode, 3785 .num_modes = 1, 3786 .size = { 3787 .width = 223, 3788 .height = 125, 3789 }, 3790 }; 3791 3792 static const struct display_timing urt_umsh_8596md_timing = { 3793 .pixelclock = { 33260000, 33260000, 33260000 }, 3794 .hactive = { 800, 800, 800 }, 3795 .hfront_porch = { 41, 41, 41 }, 3796 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3797 .hsync_len = { 71, 128, 128 }, 3798 .vactive = { 480, 480, 480 }, 3799 .vfront_porch = { 10, 10, 10 }, 3800 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3801 .vsync_len = { 2, 2, 2 }, 3802 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3803 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3804 }; 3805 3806 static const struct panel_desc urt_umsh_8596md_lvds = { 3807 .timings = &urt_umsh_8596md_timing, 3808 .num_timings = 1, 3809 .bpc = 6, 3810 .size = { 3811 .width = 152, 3812 .height = 91, 3813 }, 3814 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3815 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3816 }; 3817 3818 static const struct panel_desc urt_umsh_8596md_parallel = { 3819 .timings = &urt_umsh_8596md_timing, 3820 .num_timings = 1, 3821 .bpc = 6, 3822 .size = { 3823 .width = 152, 3824 .height = 91, 3825 }, 3826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3827 }; 3828 3829 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3830 .clock = 33333, 3831 .hdisplay = 800, 3832 .hsync_start = 800 + 210, 3833 .hsync_end = 800 + 210 + 20, 3834 .htotal = 800 + 210 + 20 + 46, 3835 .vdisplay = 480, 3836 .vsync_start = 480 + 22, 3837 .vsync_end = 480 + 22 + 10, 3838 .vtotal = 480 + 22 + 10 + 23, 3839 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3840 }; 3841 3842 static const struct panel_desc vl050_8048nt_c01 = { 3843 .modes = &vl050_8048nt_c01_mode, 3844 .num_modes = 1, 3845 .bpc = 8, 3846 .size = { 3847 .width = 120, 3848 .height = 76, 3849 }, 3850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3852 }; 3853 3854 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3855 .clock = 6410, 3856 .hdisplay = 320, 3857 .hsync_start = 320 + 20, 3858 .hsync_end = 320 + 20 + 30, 3859 .htotal = 320 + 20 + 30 + 38, 3860 .vdisplay = 240, 3861 .vsync_start = 240 + 4, 3862 .vsync_end = 240 + 4 + 3, 3863 .vtotal = 240 + 4 + 3 + 15, 3864 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3865 }; 3866 3867 static const struct panel_desc winstar_wf35ltiacd = { 3868 .modes = &winstar_wf35ltiacd_mode, 3869 .num_modes = 1, 3870 .bpc = 8, 3871 .size = { 3872 .width = 70, 3873 .height = 53, 3874 }, 3875 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3876 }; 3877 3878 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3879 .clock = 51200, 3880 .hdisplay = 1024, 3881 .hsync_start = 1024 + 100, 3882 .hsync_end = 1024 + 100 + 100, 3883 .htotal = 1024 + 100 + 100 + 120, 3884 .vdisplay = 600, 3885 .vsync_start = 600 + 10, 3886 .vsync_end = 600 + 10 + 10, 3887 .vtotal = 600 + 10 + 10 + 15, 3888 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3889 }; 3890 3891 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3892 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3893 .num_modes = 1, 3894 .bpc = 6, 3895 .size = { 3896 .width = 154, 3897 .height = 90, 3898 }, 3899 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3900 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3901 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3902 }; 3903 3904 static const struct drm_display_mode arm_rtsm_mode[] = { 3905 { 3906 .clock = 65000, 3907 .hdisplay = 1024, 3908 .hsync_start = 1024 + 24, 3909 .hsync_end = 1024 + 24 + 136, 3910 .htotal = 1024 + 24 + 136 + 160, 3911 .vdisplay = 768, 3912 .vsync_start = 768 + 3, 3913 .vsync_end = 768 + 3 + 6, 3914 .vtotal = 768 + 3 + 6 + 29, 3915 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3916 }, 3917 }; 3918 3919 static const struct panel_desc arm_rtsm = { 3920 .modes = arm_rtsm_mode, 3921 .num_modes = 1, 3922 .bpc = 8, 3923 .size = { 3924 .width = 400, 3925 .height = 300, 3926 }, 3927 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3928 }; 3929 3930 static const struct of_device_id platform_of_match[] = { 3931 { 3932 .compatible = "ampire,am-1280800n3tzqw-t00h", 3933 .data = &ire_am_1280800n3tzqw_t00h, 3934 }, { 3935 .compatible = "ampire,am-480272h3tmqw-t01h", 3936 .data = &ire_am_480272h3tmqw_t01h, 3937 }, { 3938 .compatible = "ampire,am800480r3tmqwa1h", 3939 .data = &ire_am800480r3tmqwa1h, 3940 }, { 3941 .compatible = "arm,rtsm-display", 3942 .data = &arm_rtsm, 3943 }, { 3944 .compatible = "armadeus,st0700-adapt", 3945 .data = &armadeus_st0700_adapt, 3946 }, { 3947 .compatible = "auo,b101aw03", 3948 .data = &auo_b101aw03, 3949 }, { 3950 .compatible = "auo,b101ean01", 3951 .data = &auo_b101ean01, 3952 }, { 3953 .compatible = "auo,b101xtn01", 3954 .data = &auo_b101xtn01, 3955 }, { 3956 .compatible = "auo,b116xa01", 3957 .data = &auo_b116xak01, 3958 }, { 3959 .compatible = "auo,b116xw03", 3960 .data = &auo_b116xw03, 3961 }, { 3962 .compatible = "auo,b133htn01", 3963 .data = &auo_b133htn01, 3964 }, { 3965 .compatible = "auo,b133xtn01", 3966 .data = &auo_b133xtn01, 3967 }, { 3968 .compatible = "auo,g070vvn01", 3969 .data = &auo_g070vvn01, 3970 }, { 3971 .compatible = "auo,g101evn010", 3972 .data = &auo_g101evn010, 3973 }, { 3974 .compatible = "auo,g104sn02", 3975 .data = &auo_g104sn02, 3976 }, { 3977 .compatible = "auo,g121ean01", 3978 .data = &auo_g121ean01, 3979 }, { 3980 .compatible = "auo,g133han01", 3981 .data = &auo_g133han01, 3982 }, { 3983 .compatible = "auo,g156xtn01", 3984 .data = &auo_g156xtn01, 3985 }, { 3986 .compatible = "auo,g185han01", 3987 .data = &auo_g185han01, 3988 }, { 3989 .compatible = "auo,g190ean01", 3990 .data = &auo_g190ean01, 3991 }, { 3992 .compatible = "auo,p320hvn03", 3993 .data = &auo_p320hvn03, 3994 }, { 3995 .compatible = "auo,t215hvn01", 3996 .data = &auo_t215hvn01, 3997 }, { 3998 .compatible = "avic,tm070ddh03", 3999 .data = &avic_tm070ddh03, 4000 }, { 4001 .compatible = "bananapi,s070wv20-ct16", 4002 .data = &bananapi_s070wv20_ct16, 4003 }, { 4004 .compatible = "boe,hv070wsa-100", 4005 .data = &boe_hv070wsa 4006 }, { 4007 .compatible = "boe,nv101wxmn51", 4008 .data = &boe_nv101wxmn51, 4009 }, { 4010 .compatible = "boe,nv133fhm-n61", 4011 .data = &boe_nv133fhm_n61, 4012 }, { 4013 .compatible = "boe,nv133fhm-n62", 4014 .data = &boe_nv133fhm_n61, 4015 }, { 4016 .compatible = "boe,nv140fhmn49", 4017 .data = &boe_nv140fhmn49, 4018 }, { 4019 .compatible = "cdtech,s043wq26h-ct7", 4020 .data = &cdtech_s043wq26h_ct7, 4021 }, { 4022 .compatible = "cdtech,s070pws19hp-fc21", 4023 .data = &cdtech_s070pws19hp_fc21, 4024 }, { 4025 .compatible = "cdtech,s070swv29hg-dc44", 4026 .data = &cdtech_s070swv29hg_dc44, 4027 }, { 4028 .compatible = "cdtech,s070wv95-ct16", 4029 .data = &cdtech_s070wv95_ct16, 4030 }, { 4031 .compatible = "chefree,ch101olhlwh-002", 4032 .data = &chefree_ch101olhlwh_002, 4033 }, { 4034 .compatible = "chunghwa,claa070wp03xg", 4035 .data = &chunghwa_claa070wp03xg, 4036 }, { 4037 .compatible = "chunghwa,claa101wa01a", 4038 .data = &chunghwa_claa101wa01a 4039 }, { 4040 .compatible = "chunghwa,claa101wb01", 4041 .data = &chunghwa_claa101wb01 4042 }, { 4043 .compatible = "dataimage,scf0700c48ggu18", 4044 .data = &dataimage_scf0700c48ggu18, 4045 }, { 4046 .compatible = "dlc,dlc0700yzg-1", 4047 .data = &dlc_dlc0700yzg_1, 4048 }, { 4049 .compatible = "dlc,dlc1010gig", 4050 .data = &dlc_dlc1010gig, 4051 }, { 4052 .compatible = "edt,et035012dm6", 4053 .data = &edt_et035012dm6, 4054 }, { 4055 .compatible = "edt,etm043080dh6gp", 4056 .data = &edt_etm043080dh6gp, 4057 }, { 4058 .compatible = "edt,etm0430g0dh6", 4059 .data = &edt_etm0430g0dh6, 4060 }, { 4061 .compatible = "edt,et057090dhu", 4062 .data = &edt_et057090dhu, 4063 }, { 4064 .compatible = "edt,et070080dh6", 4065 .data = &edt_etm0700g0dh6, 4066 }, { 4067 .compatible = "edt,etm0700g0dh6", 4068 .data = &edt_etm0700g0dh6, 4069 }, { 4070 .compatible = "edt,etm0700g0bdh6", 4071 .data = &edt_etm0700g0bdh6, 4072 }, { 4073 .compatible = "edt,etm0700g0edh6", 4074 .data = &edt_etm0700g0bdh6, 4075 }, { 4076 .compatible = "evervision,vgg804821", 4077 .data = &evervision_vgg804821, 4078 }, { 4079 .compatible = "foxlink,fl500wvr00-a0t", 4080 .data = &foxlink_fl500wvr00_a0t, 4081 }, { 4082 .compatible = "frida,frd350h54004", 4083 .data = &frida_frd350h54004, 4084 }, { 4085 .compatible = "friendlyarm,hd702e", 4086 .data = &friendlyarm_hd702e, 4087 }, { 4088 .compatible = "giantplus,gpg482739qs5", 4089 .data = &giantplus_gpg482739qs5 4090 }, { 4091 .compatible = "giantplus,gpm940b0", 4092 .data = &giantplus_gpm940b0, 4093 }, { 4094 .compatible = "hannstar,hsd070pww1", 4095 .data = &hannstar_hsd070pww1, 4096 }, { 4097 .compatible = "hannstar,hsd100pxn1", 4098 .data = &hannstar_hsd100pxn1, 4099 }, { 4100 .compatible = "hit,tx23d38vm0caa", 4101 .data = &hitachi_tx23d38vm0caa 4102 }, { 4103 .compatible = "innolux,at043tn24", 4104 .data = &innolux_at043tn24, 4105 }, { 4106 .compatible = "innolux,at070tn92", 4107 .data = &innolux_at070tn92, 4108 }, { 4109 .compatible = "innolux,g070y2-l01", 4110 .data = &innolux_g070y2_l01, 4111 }, { 4112 .compatible = "innolux,g101ice-l01", 4113 .data = &innolux_g101ice_l01 4114 }, { 4115 .compatible = "innolux,g121i1-l01", 4116 .data = &innolux_g121i1_l01 4117 }, { 4118 .compatible = "innolux,g121x1-l03", 4119 .data = &innolux_g121x1_l03, 4120 }, { 4121 .compatible = "innolux,n116bge", 4122 .data = &innolux_n116bge, 4123 }, { 4124 .compatible = "innolux,n156bge-l21", 4125 .data = &innolux_n156bge_l21, 4126 }, { 4127 .compatible = "innolux,p120zdg-bf1", 4128 .data = &innolux_p120zdg_bf1, 4129 }, { 4130 .compatible = "innolux,zj070na-01p", 4131 .data = &innolux_zj070na_01p, 4132 }, { 4133 .compatible = "ivo,m133nwf4-r0", 4134 .data = &ivo_m133nwf4_r0, 4135 }, { 4136 .compatible = "kingdisplay,kd116n21-30nv-a010", 4137 .data = &kingdisplay_kd116n21_30nv_a010, 4138 }, { 4139 .compatible = "koe,tx14d24vm1bpa", 4140 .data = &koe_tx14d24vm1bpa, 4141 }, { 4142 .compatible = "koe,tx26d202vm0bwa", 4143 .data = &koe_tx26d202vm0bwa, 4144 }, { 4145 .compatible = "koe,tx31d200vm0baa", 4146 .data = &koe_tx31d200vm0baa, 4147 }, { 4148 .compatible = "kyo,tcg121xglp", 4149 .data = &kyo_tcg121xglp, 4150 }, { 4151 .compatible = "lemaker,bl035-rgb-002", 4152 .data = &lemaker_bl035_rgb_002, 4153 }, { 4154 .compatible = "lg,lb070wv8", 4155 .data = &lg_lb070wv8, 4156 }, { 4157 .compatible = "lg,lp079qx1-sp0v", 4158 .data = &lg_lp079qx1_sp0v, 4159 }, { 4160 .compatible = "lg,lp097qx1-spa1", 4161 .data = &lg_lp097qx1_spa1, 4162 }, { 4163 .compatible = "lg,lp120up1", 4164 .data = &lg_lp120up1, 4165 }, { 4166 .compatible = "lg,lp129qe", 4167 .data = &lg_lp129qe, 4168 }, { 4169 .compatible = "logicpd,type28", 4170 .data = &logicpd_type_28, 4171 }, { 4172 .compatible = "logictechno,lt161010-2nhc", 4173 .data = &logictechno_lt161010_2nh, 4174 }, { 4175 .compatible = "logictechno,lt161010-2nhr", 4176 .data = &logictechno_lt161010_2nh, 4177 }, { 4178 .compatible = "logictechno,lt170410-2whc", 4179 .data = &logictechno_lt170410_2whc, 4180 }, { 4181 .compatible = "mitsubishi,aa070mc01-ca1", 4182 .data = &mitsubishi_aa070mc01, 4183 }, { 4184 .compatible = "nec,nl12880bc20-05", 4185 .data = &nec_nl12880bc20_05, 4186 }, { 4187 .compatible = "nec,nl4827hc19-05b", 4188 .data = &nec_nl4827hc19_05b, 4189 }, { 4190 .compatible = "netron-dy,e231732", 4191 .data = &netron_dy_e231732, 4192 }, { 4193 .compatible = "neweast,wjfh116008a", 4194 .data = &neweast_wjfh116008a, 4195 }, { 4196 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4197 .data = &newhaven_nhd_43_480272ef_atxl, 4198 }, { 4199 .compatible = "nlt,nl192108ac18-02d", 4200 .data = &nlt_nl192108ac18_02d, 4201 }, { 4202 .compatible = "nvd,9128", 4203 .data = &nvd_9128, 4204 }, { 4205 .compatible = "okaya,rs800480t-7x0gp", 4206 .data = &okaya_rs800480t_7x0gp, 4207 }, { 4208 .compatible = "olimex,lcd-olinuxino-43-ts", 4209 .data = &olimex_lcd_olinuxino_43ts, 4210 }, { 4211 .compatible = "ontat,yx700wv03", 4212 .data = &ontat_yx700wv03, 4213 }, { 4214 .compatible = "ortustech,com37h3m05dtc", 4215 .data = &ortustech_com37h3m, 4216 }, { 4217 .compatible = "ortustech,com37h3m99dtc", 4218 .data = &ortustech_com37h3m, 4219 }, { 4220 .compatible = "ortustech,com43h4m85ulc", 4221 .data = &ortustech_com43h4m85ulc, 4222 }, { 4223 .compatible = "osddisplays,osd070t1718-19ts", 4224 .data = &osddisplays_osd070t1718_19ts, 4225 }, { 4226 .compatible = "pda,91-00156-a0", 4227 .data = &pda_91_00156_a0, 4228 }, { 4229 .compatible = "powertip,ph800480t013-idf02", 4230 .data = &powertip_ph800480t013_idf02, 4231 }, { 4232 .compatible = "qiaodian,qd43003c0-40", 4233 .data = &qd43003c0_40, 4234 }, { 4235 .compatible = "rocktech,rk070er9427", 4236 .data = &rocktech_rk070er9427, 4237 }, { 4238 .compatible = "rocktech,rk101ii01d-ct", 4239 .data = &rocktech_rk101ii01d_ct, 4240 }, { 4241 .compatible = "samsung,lsn122dl01-c01", 4242 .data = &samsung_lsn122dl01_c01, 4243 }, { 4244 .compatible = "samsung,ltn101nt05", 4245 .data = &samsung_ltn101nt05, 4246 }, { 4247 .compatible = "samsung,ltn140at29-301", 4248 .data = &samsung_ltn140at29_301, 4249 }, { 4250 .compatible = "satoz,sat050at40h12r2", 4251 .data = &satoz_sat050at40h12r2, 4252 }, { 4253 .compatible = "sharp,ld-d5116z01b", 4254 .data = &sharp_ld_d5116z01b, 4255 }, { 4256 .compatible = "sharp,lq035q7db03", 4257 .data = &sharp_lq035q7db03, 4258 }, { 4259 .compatible = "sharp,lq070y3dg3b", 4260 .data = &sharp_lq070y3dg3b, 4261 }, { 4262 .compatible = "sharp,lq101k1ly04", 4263 .data = &sharp_lq101k1ly04, 4264 }, { 4265 .compatible = "sharp,lq123p1jx31", 4266 .data = &sharp_lq123p1jx31, 4267 }, { 4268 .compatible = "sharp,ls020b1dd01d", 4269 .data = &sharp_ls020b1dd01d, 4270 }, { 4271 .compatible = "shelly,sca07010-bfn-lnn", 4272 .data = &shelly_sca07010_bfn_lnn, 4273 }, { 4274 .compatible = "starry,kr070pe2t", 4275 .data = &starry_kr070pe2t, 4276 }, { 4277 .compatible = "starry,kr122ea0sra", 4278 .data = &starry_kr122ea0sra, 4279 }, { 4280 .compatible = "tfc,s9700rtwv43tr-01b", 4281 .data = &tfc_s9700rtwv43tr_01b, 4282 }, { 4283 .compatible = "tianma,tm070jdhg30", 4284 .data = &tianma_tm070jdhg30, 4285 }, { 4286 .compatible = "tianma,tm070jvhg33", 4287 .data = &tianma_tm070jvhg33, 4288 }, { 4289 .compatible = "tianma,tm070rvhg71", 4290 .data = &tianma_tm070rvhg71, 4291 }, { 4292 .compatible = "ti,nspire-cx-lcd-panel", 4293 .data = &ti_nspire_cx_lcd_panel, 4294 }, { 4295 .compatible = "ti,nspire-classic-lcd-panel", 4296 .data = &ti_nspire_classic_lcd_panel, 4297 }, { 4298 .compatible = "toshiba,lt089ac29000", 4299 .data = &toshiba_lt089ac29000, 4300 }, { 4301 .compatible = "tpk,f07a-0102", 4302 .data = &tpk_f07a_0102, 4303 }, { 4304 .compatible = "tpk,f10a-0102", 4305 .data = &tpk_f10a_0102, 4306 }, { 4307 .compatible = "urt,umsh-8596md-t", 4308 .data = &urt_umsh_8596md_parallel, 4309 }, { 4310 .compatible = "urt,umsh-8596md-1t", 4311 .data = &urt_umsh_8596md_parallel, 4312 }, { 4313 .compatible = "urt,umsh-8596md-7t", 4314 .data = &urt_umsh_8596md_parallel, 4315 }, { 4316 .compatible = "urt,umsh-8596md-11t", 4317 .data = &urt_umsh_8596md_lvds, 4318 }, { 4319 .compatible = "urt,umsh-8596md-19t", 4320 .data = &urt_umsh_8596md_lvds, 4321 }, { 4322 .compatible = "urt,umsh-8596md-20t", 4323 .data = &urt_umsh_8596md_parallel, 4324 }, { 4325 .compatible = "vxt,vl050-8048nt-c01", 4326 .data = &vl050_8048nt_c01, 4327 }, { 4328 .compatible = "winstar,wf35ltiacd", 4329 .data = &winstar_wf35ltiacd, 4330 }, { 4331 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4332 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4333 }, { 4334 /* Must be the last entry */ 4335 .compatible = "panel-dpi", 4336 .data = &panel_dpi, 4337 }, { 4338 /* sentinel */ 4339 } 4340 }; 4341 MODULE_DEVICE_TABLE(of, platform_of_match); 4342 4343 static int panel_simple_platform_probe(struct platform_device *pdev) 4344 { 4345 const struct of_device_id *id; 4346 4347 id = of_match_node(platform_of_match, pdev->dev.of_node); 4348 if (!id) 4349 return -ENODEV; 4350 4351 return panel_simple_probe(&pdev->dev, id->data); 4352 } 4353 4354 static int panel_simple_platform_remove(struct platform_device *pdev) 4355 { 4356 return panel_simple_remove(&pdev->dev); 4357 } 4358 4359 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4360 { 4361 panel_simple_shutdown(&pdev->dev); 4362 } 4363 4364 static struct platform_driver panel_simple_platform_driver = { 4365 .driver = { 4366 .name = "panel-simple", 4367 .of_match_table = platform_of_match, 4368 }, 4369 .probe = panel_simple_platform_probe, 4370 .remove = panel_simple_platform_remove, 4371 .shutdown = panel_simple_platform_shutdown, 4372 }; 4373 4374 struct panel_desc_dsi { 4375 struct panel_desc desc; 4376 4377 unsigned long flags; 4378 enum mipi_dsi_pixel_format format; 4379 unsigned int lanes; 4380 }; 4381 4382 static const struct drm_display_mode auo_b080uan01_mode = { 4383 .clock = 154500, 4384 .hdisplay = 1200, 4385 .hsync_start = 1200 + 62, 4386 .hsync_end = 1200 + 62 + 4, 4387 .htotal = 1200 + 62 + 4 + 62, 4388 .vdisplay = 1920, 4389 .vsync_start = 1920 + 9, 4390 .vsync_end = 1920 + 9 + 2, 4391 .vtotal = 1920 + 9 + 2 + 8, 4392 }; 4393 4394 static const struct panel_desc_dsi auo_b080uan01 = { 4395 .desc = { 4396 .modes = &auo_b080uan01_mode, 4397 .num_modes = 1, 4398 .bpc = 8, 4399 .size = { 4400 .width = 108, 4401 .height = 272, 4402 }, 4403 .connector_type = DRM_MODE_CONNECTOR_DSI, 4404 }, 4405 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4406 .format = MIPI_DSI_FMT_RGB888, 4407 .lanes = 4, 4408 }; 4409 4410 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4411 .clock = 160000, 4412 .hdisplay = 1200, 4413 .hsync_start = 1200 + 120, 4414 .hsync_end = 1200 + 120 + 20, 4415 .htotal = 1200 + 120 + 20 + 21, 4416 .vdisplay = 1920, 4417 .vsync_start = 1920 + 21, 4418 .vsync_end = 1920 + 21 + 3, 4419 .vtotal = 1920 + 21 + 3 + 18, 4420 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4421 }; 4422 4423 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4424 .desc = { 4425 .modes = &boe_tv080wum_nl0_mode, 4426 .num_modes = 1, 4427 .size = { 4428 .width = 107, 4429 .height = 172, 4430 }, 4431 .connector_type = DRM_MODE_CONNECTOR_DSI, 4432 }, 4433 .flags = MIPI_DSI_MODE_VIDEO | 4434 MIPI_DSI_MODE_VIDEO_BURST | 4435 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4436 .format = MIPI_DSI_FMT_RGB888, 4437 .lanes = 4, 4438 }; 4439 4440 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4441 .clock = 71000, 4442 .hdisplay = 800, 4443 .hsync_start = 800 + 32, 4444 .hsync_end = 800 + 32 + 1, 4445 .htotal = 800 + 32 + 1 + 57, 4446 .vdisplay = 1280, 4447 .vsync_start = 1280 + 28, 4448 .vsync_end = 1280 + 28 + 1, 4449 .vtotal = 1280 + 28 + 1 + 14, 4450 }; 4451 4452 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4453 .desc = { 4454 .modes = &lg_ld070wx3_sl01_mode, 4455 .num_modes = 1, 4456 .bpc = 8, 4457 .size = { 4458 .width = 94, 4459 .height = 151, 4460 }, 4461 .connector_type = DRM_MODE_CONNECTOR_DSI, 4462 }, 4463 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4464 .format = MIPI_DSI_FMT_RGB888, 4465 .lanes = 4, 4466 }; 4467 4468 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4469 .clock = 67000, 4470 .hdisplay = 720, 4471 .hsync_start = 720 + 12, 4472 .hsync_end = 720 + 12 + 4, 4473 .htotal = 720 + 12 + 4 + 112, 4474 .vdisplay = 1280, 4475 .vsync_start = 1280 + 8, 4476 .vsync_end = 1280 + 8 + 4, 4477 .vtotal = 1280 + 8 + 4 + 12, 4478 }; 4479 4480 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4481 .desc = { 4482 .modes = &lg_lh500wx1_sd03_mode, 4483 .num_modes = 1, 4484 .bpc = 8, 4485 .size = { 4486 .width = 62, 4487 .height = 110, 4488 }, 4489 .connector_type = DRM_MODE_CONNECTOR_DSI, 4490 }, 4491 .flags = MIPI_DSI_MODE_VIDEO, 4492 .format = MIPI_DSI_FMT_RGB888, 4493 .lanes = 4, 4494 }; 4495 4496 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4497 .clock = 157200, 4498 .hdisplay = 1920, 4499 .hsync_start = 1920 + 154, 4500 .hsync_end = 1920 + 154 + 16, 4501 .htotal = 1920 + 154 + 16 + 32, 4502 .vdisplay = 1200, 4503 .vsync_start = 1200 + 17, 4504 .vsync_end = 1200 + 17 + 2, 4505 .vtotal = 1200 + 17 + 2 + 16, 4506 }; 4507 4508 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4509 .desc = { 4510 .modes = &panasonic_vvx10f004b00_mode, 4511 .num_modes = 1, 4512 .bpc = 8, 4513 .size = { 4514 .width = 217, 4515 .height = 136, 4516 }, 4517 .connector_type = DRM_MODE_CONNECTOR_DSI, 4518 }, 4519 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4520 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4521 .format = MIPI_DSI_FMT_RGB888, 4522 .lanes = 4, 4523 }; 4524 4525 static const struct drm_display_mode lg_acx467akm_7_mode = { 4526 .clock = 150000, 4527 .hdisplay = 1080, 4528 .hsync_start = 1080 + 2, 4529 .hsync_end = 1080 + 2 + 2, 4530 .htotal = 1080 + 2 + 2 + 2, 4531 .vdisplay = 1920, 4532 .vsync_start = 1920 + 2, 4533 .vsync_end = 1920 + 2 + 2, 4534 .vtotal = 1920 + 2 + 2 + 2, 4535 }; 4536 4537 static const struct panel_desc_dsi lg_acx467akm_7 = { 4538 .desc = { 4539 .modes = &lg_acx467akm_7_mode, 4540 .num_modes = 1, 4541 .bpc = 8, 4542 .size = { 4543 .width = 62, 4544 .height = 110, 4545 }, 4546 .connector_type = DRM_MODE_CONNECTOR_DSI, 4547 }, 4548 .flags = 0, 4549 .format = MIPI_DSI_FMT_RGB888, 4550 .lanes = 4, 4551 }; 4552 4553 static const struct drm_display_mode osd101t2045_53ts_mode = { 4554 .clock = 154500, 4555 .hdisplay = 1920, 4556 .hsync_start = 1920 + 112, 4557 .hsync_end = 1920 + 112 + 16, 4558 .htotal = 1920 + 112 + 16 + 32, 4559 .vdisplay = 1200, 4560 .vsync_start = 1200 + 16, 4561 .vsync_end = 1200 + 16 + 2, 4562 .vtotal = 1200 + 16 + 2 + 16, 4563 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4564 }; 4565 4566 static const struct panel_desc_dsi osd101t2045_53ts = { 4567 .desc = { 4568 .modes = &osd101t2045_53ts_mode, 4569 .num_modes = 1, 4570 .bpc = 8, 4571 .size = { 4572 .width = 217, 4573 .height = 136, 4574 }, 4575 .connector_type = DRM_MODE_CONNECTOR_DSI, 4576 }, 4577 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4578 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4579 MIPI_DSI_MODE_EOT_PACKET, 4580 .format = MIPI_DSI_FMT_RGB888, 4581 .lanes = 4, 4582 }; 4583 4584 static const struct of_device_id dsi_of_match[] = { 4585 { 4586 .compatible = "auo,b080uan01", 4587 .data = &auo_b080uan01 4588 }, { 4589 .compatible = "boe,tv080wum-nl0", 4590 .data = &boe_tv080wum_nl0 4591 }, { 4592 .compatible = "lg,ld070wx3-sl01", 4593 .data = &lg_ld070wx3_sl01 4594 }, { 4595 .compatible = "lg,lh500wx1-sd03", 4596 .data = &lg_lh500wx1_sd03 4597 }, { 4598 .compatible = "panasonic,vvx10f004b00", 4599 .data = &panasonic_vvx10f004b00 4600 }, { 4601 .compatible = "lg,acx467akm-7", 4602 .data = &lg_acx467akm_7 4603 }, { 4604 .compatible = "osddisplays,osd101t2045-53ts", 4605 .data = &osd101t2045_53ts 4606 }, { 4607 /* sentinel */ 4608 } 4609 }; 4610 MODULE_DEVICE_TABLE(of, dsi_of_match); 4611 4612 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4613 { 4614 const struct panel_desc_dsi *desc; 4615 const struct of_device_id *id; 4616 int err; 4617 4618 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4619 if (!id) 4620 return -ENODEV; 4621 4622 desc = id->data; 4623 4624 err = panel_simple_probe(&dsi->dev, &desc->desc); 4625 if (err < 0) 4626 return err; 4627 4628 dsi->mode_flags = desc->flags; 4629 dsi->format = desc->format; 4630 dsi->lanes = desc->lanes; 4631 4632 err = mipi_dsi_attach(dsi); 4633 if (err) { 4634 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4635 4636 drm_panel_remove(&panel->base); 4637 } 4638 4639 return err; 4640 } 4641 4642 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4643 { 4644 int err; 4645 4646 err = mipi_dsi_detach(dsi); 4647 if (err < 0) 4648 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4649 4650 return panel_simple_remove(&dsi->dev); 4651 } 4652 4653 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4654 { 4655 panel_simple_shutdown(&dsi->dev); 4656 } 4657 4658 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4659 .driver = { 4660 .name = "panel-simple-dsi", 4661 .of_match_table = dsi_of_match, 4662 }, 4663 .probe = panel_simple_dsi_probe, 4664 .remove = panel_simple_dsi_remove, 4665 .shutdown = panel_simple_dsi_shutdown, 4666 }; 4667 4668 static int __init panel_simple_init(void) 4669 { 4670 int err; 4671 4672 err = platform_driver_register(&panel_simple_platform_driver); 4673 if (err < 0) 4674 return err; 4675 4676 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4677 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4678 if (err < 0) { 4679 platform_driver_unregister(&panel_simple_platform_driver); 4680 return err; 4681 } 4682 } 4683 4684 return 0; 4685 } 4686 module_init(panel_simple_init); 4687 4688 static void __exit panel_simple_exit(void) 4689 { 4690 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4691 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4692 4693 platform_driver_unregister(&panel_simple_platform_driver); 4694 } 4695 module_exit(panel_simple_exit); 4696 4697 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4698 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4699 MODULE_LICENSE("GPL and additional rights"); 4700