1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) { 579 err = PTR_ERR(panel->enable_gpio); 580 if (err != -EPROBE_DEFER) 581 dev_err(dev, "failed to request GPIO: %d\n", err); 582 return err; 583 } 584 585 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 586 if (err) { 587 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 588 return err; 589 } 590 591 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 592 if (ddc) { 593 panel->ddc = of_find_i2c_adapter_by_node(ddc); 594 of_node_put(ddc); 595 596 if (!panel->ddc) 597 return -EPROBE_DEFER; 598 } 599 600 if (desc == &panel_dpi) { 601 /* Handle the generic panel-dpi binding */ 602 err = panel_dpi_probe(dev, panel); 603 if (err) 604 goto free_ddc; 605 desc = panel->desc; 606 } else { 607 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 608 panel_simple_parse_panel_timing_node(dev, panel, &dt); 609 } 610 611 connector_type = desc->connector_type; 612 /* Catch common mistakes for panels. */ 613 switch (connector_type) { 614 case 0: 615 dev_warn(dev, "Specify missing connector_type\n"); 616 connector_type = DRM_MODE_CONNECTOR_DPI; 617 break; 618 case DRM_MODE_CONNECTOR_LVDS: 619 WARN_ON(desc->bus_flags & 620 ~(DRM_BUS_FLAG_DE_LOW | 621 DRM_BUS_FLAG_DE_HIGH | 622 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 623 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 624 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 626 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 627 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 628 desc->bpc != 6); 629 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 630 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 631 desc->bpc != 8); 632 break; 633 case DRM_MODE_CONNECTOR_eDP: 634 dev_warn(dev, "eDP panels moved to panel-edp\n"); 635 err = -EINVAL; 636 goto free_ddc; 637 case DRM_MODE_CONNECTOR_DSI: 638 if (desc->bpc != 6 && desc->bpc != 8) 639 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 640 break; 641 case DRM_MODE_CONNECTOR_DPI: 642 bus_flags = DRM_BUS_FLAG_DE_LOW | 643 DRM_BUS_FLAG_DE_HIGH | 644 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 645 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 646 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 647 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 648 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 649 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 650 if (desc->bus_flags & ~bus_flags) 651 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 652 if (!(desc->bus_flags & bus_flags)) 653 dev_warn(dev, "Specify missing bus_flags\n"); 654 if (desc->bus_format == 0) 655 dev_warn(dev, "Specify missing bus_format\n"); 656 if (desc->bpc != 6 && desc->bpc != 8) 657 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 658 break; 659 default: 660 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 661 connector_type = DRM_MODE_CONNECTOR_DPI; 662 break; 663 } 664 665 dev_set_drvdata(dev, panel); 666 667 /* 668 * We use runtime PM for prepare / unprepare since those power the panel 669 * on and off and those can be very slow operations. This is important 670 * to optimize powering the panel on briefly to read the EDID before 671 * fully enabling the panel. 672 */ 673 pm_runtime_enable(dev); 674 pm_runtime_set_autosuspend_delay(dev, 1000); 675 pm_runtime_use_autosuspend(dev); 676 677 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 678 679 err = drm_panel_of_backlight(&panel->base); 680 if (err) { 681 dev_err_probe(dev, err, "Could not find backlight\n"); 682 goto disable_pm_runtime; 683 } 684 685 drm_panel_add(&panel->base); 686 687 return 0; 688 689 disable_pm_runtime: 690 pm_runtime_dont_use_autosuspend(dev); 691 pm_runtime_disable(dev); 692 free_ddc: 693 if (panel->ddc) 694 put_device(&panel->ddc->dev); 695 696 return err; 697 } 698 699 static int panel_simple_remove(struct device *dev) 700 { 701 struct panel_simple *panel = dev_get_drvdata(dev); 702 703 drm_panel_remove(&panel->base); 704 drm_panel_disable(&panel->base); 705 drm_panel_unprepare(&panel->base); 706 707 pm_runtime_dont_use_autosuspend(dev); 708 pm_runtime_disable(dev); 709 if (panel->ddc) 710 put_device(&panel->ddc->dev); 711 712 return 0; 713 } 714 715 static void panel_simple_shutdown(struct device *dev) 716 { 717 struct panel_simple *panel = dev_get_drvdata(dev); 718 719 drm_panel_disable(&panel->base); 720 drm_panel_unprepare(&panel->base); 721 } 722 723 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 724 .clock = 71100, 725 .hdisplay = 1280, 726 .hsync_start = 1280 + 40, 727 .hsync_end = 1280 + 40 + 80, 728 .htotal = 1280 + 40 + 80 + 40, 729 .vdisplay = 800, 730 .vsync_start = 800 + 3, 731 .vsync_end = 800 + 3 + 10, 732 .vtotal = 800 + 3 + 10 + 10, 733 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 734 }; 735 736 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 737 .modes = &ire_am_1280800n3tzqw_t00h_mode, 738 .num_modes = 1, 739 .bpc = 8, 740 .size = { 741 .width = 217, 742 .height = 136, 743 }, 744 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 745 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 746 .connector_type = DRM_MODE_CONNECTOR_LVDS, 747 }; 748 749 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 750 .clock = 9000, 751 .hdisplay = 480, 752 .hsync_start = 480 + 2, 753 .hsync_end = 480 + 2 + 41, 754 .htotal = 480 + 2 + 41 + 2, 755 .vdisplay = 272, 756 .vsync_start = 272 + 2, 757 .vsync_end = 272 + 2 + 10, 758 .vtotal = 272 + 2 + 10 + 2, 759 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 760 }; 761 762 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 763 .modes = &ire_am_480272h3tmqw_t01h_mode, 764 .num_modes = 1, 765 .bpc = 8, 766 .size = { 767 .width = 105, 768 .height = 67, 769 }, 770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 771 }; 772 773 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 774 .clock = 33333, 775 .hdisplay = 800, 776 .hsync_start = 800 + 0, 777 .hsync_end = 800 + 0 + 255, 778 .htotal = 800 + 0 + 255 + 0, 779 .vdisplay = 480, 780 .vsync_start = 480 + 2, 781 .vsync_end = 480 + 2 + 45, 782 .vtotal = 480 + 2 + 45 + 0, 783 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 784 }; 785 786 static const struct panel_desc ampire_am800480r3tmqwa1h = { 787 .modes = &ire_am800480r3tmqwa1h_mode, 788 .num_modes = 1, 789 .bpc = 6, 790 .size = { 791 .width = 152, 792 .height = 91, 793 }, 794 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 795 }; 796 797 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 798 .pixelclock = { 34500000, 39600000, 50400000 }, 799 .hactive = { 800, 800, 800 }, 800 .hfront_porch = { 12, 112, 312 }, 801 .hback_porch = { 87, 87, 48 }, 802 .hsync_len = { 1, 1, 40 }, 803 .vactive = { 600, 600, 600 }, 804 .vfront_porch = { 1, 21, 61 }, 805 .vback_porch = { 38, 38, 19 }, 806 .vsync_len = { 1, 1, 20 }, 807 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 808 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 809 DISPLAY_FLAGS_SYNC_POSEDGE, 810 }; 811 812 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 813 .timings = &ire_am800600p5tmqw_tb8h_timing, 814 .num_timings = 1, 815 .bpc = 6, 816 .size = { 817 .width = 162, 818 .height = 122, 819 }, 820 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 821 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 822 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 823 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 824 .connector_type = DRM_MODE_CONNECTOR_DPI, 825 }; 826 827 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 828 .pixelclock = { 26400000, 33300000, 46800000 }, 829 .hactive = { 800, 800, 800 }, 830 .hfront_porch = { 16, 210, 354 }, 831 .hback_porch = { 45, 36, 6 }, 832 .hsync_len = { 1, 10, 40 }, 833 .vactive = { 480, 480, 480 }, 834 .vfront_porch = { 7, 22, 147 }, 835 .vback_porch = { 22, 13, 3 }, 836 .vsync_len = { 1, 10, 20 }, 837 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 838 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 839 }; 840 841 static const struct panel_desc armadeus_st0700_adapt = { 842 .timings = &santek_st0700i5y_rbslw_f_timing, 843 .num_timings = 1, 844 .bpc = 6, 845 .size = { 846 .width = 154, 847 .height = 86, 848 }, 849 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 850 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 851 }; 852 853 static const struct drm_display_mode auo_b101aw03_mode = { 854 .clock = 51450, 855 .hdisplay = 1024, 856 .hsync_start = 1024 + 156, 857 .hsync_end = 1024 + 156 + 8, 858 .htotal = 1024 + 156 + 8 + 156, 859 .vdisplay = 600, 860 .vsync_start = 600 + 16, 861 .vsync_end = 600 + 16 + 6, 862 .vtotal = 600 + 16 + 6 + 16, 863 }; 864 865 static const struct panel_desc auo_b101aw03 = { 866 .modes = &auo_b101aw03_mode, 867 .num_modes = 1, 868 .bpc = 6, 869 .size = { 870 .width = 223, 871 .height = 125, 872 }, 873 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 874 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 875 .connector_type = DRM_MODE_CONNECTOR_LVDS, 876 }; 877 878 static const struct drm_display_mode auo_b101xtn01_mode = { 879 .clock = 72000, 880 .hdisplay = 1366, 881 .hsync_start = 1366 + 20, 882 .hsync_end = 1366 + 20 + 70, 883 .htotal = 1366 + 20 + 70, 884 .vdisplay = 768, 885 .vsync_start = 768 + 14, 886 .vsync_end = 768 + 14 + 42, 887 .vtotal = 768 + 14 + 42, 888 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 889 }; 890 891 static const struct panel_desc auo_b101xtn01 = { 892 .modes = &auo_b101xtn01_mode, 893 .num_modes = 1, 894 .bpc = 6, 895 .size = { 896 .width = 223, 897 .height = 125, 898 }, 899 }; 900 901 static const struct display_timing auo_g070vvn01_timings = { 902 .pixelclock = { 33300000, 34209000, 45000000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 20, 40, 200 }, 905 .hback_porch = { 87, 40, 1 }, 906 .hsync_len = { 1, 48, 87 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 5, 13, 200 }, 909 .vback_porch = { 31, 31, 29 }, 910 .vsync_len = { 1, 1, 3 }, 911 }; 912 913 static const struct panel_desc auo_g070vvn01 = { 914 .timings = &auo_g070vvn01_timings, 915 .num_timings = 1, 916 .bpc = 8, 917 .size = { 918 .width = 152, 919 .height = 91, 920 }, 921 .delay = { 922 .prepare = 200, 923 .enable = 50, 924 .disable = 50, 925 .unprepare = 1000, 926 }, 927 }; 928 929 static const struct drm_display_mode auo_g101evn010_mode = { 930 .clock = 68930, 931 .hdisplay = 1280, 932 .hsync_start = 1280 + 82, 933 .hsync_end = 1280 + 82 + 2, 934 .htotal = 1280 + 82 + 2 + 84, 935 .vdisplay = 800, 936 .vsync_start = 800 + 8, 937 .vsync_end = 800 + 8 + 2, 938 .vtotal = 800 + 8 + 2 + 6, 939 }; 940 941 static const struct panel_desc auo_g101evn010 = { 942 .modes = &auo_g101evn010_mode, 943 .num_modes = 1, 944 .bpc = 6, 945 .size = { 946 .width = 216, 947 .height = 135, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 950 .connector_type = DRM_MODE_CONNECTOR_LVDS, 951 }; 952 953 static const struct drm_display_mode auo_g104sn02_mode = { 954 .clock = 40000, 955 .hdisplay = 800, 956 .hsync_start = 800 + 40, 957 .hsync_end = 800 + 40 + 216, 958 .htotal = 800 + 40 + 216 + 128, 959 .vdisplay = 600, 960 .vsync_start = 600 + 10, 961 .vsync_end = 600 + 10 + 35, 962 .vtotal = 600 + 10 + 35 + 2, 963 }; 964 965 static const struct panel_desc auo_g104sn02 = { 966 .modes = &auo_g104sn02_mode, 967 .num_modes = 1, 968 .bpc = 8, 969 .size = { 970 .width = 211, 971 .height = 158, 972 }, 973 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 974 .connector_type = DRM_MODE_CONNECTOR_LVDS, 975 }; 976 977 static const struct drm_display_mode auo_g121ean01_mode = { 978 .clock = 66700, 979 .hdisplay = 1280, 980 .hsync_start = 1280 + 58, 981 .hsync_end = 1280 + 58 + 8, 982 .htotal = 1280 + 58 + 8 + 70, 983 .vdisplay = 800, 984 .vsync_start = 800 + 6, 985 .vsync_end = 800 + 6 + 4, 986 .vtotal = 800 + 6 + 4 + 10, 987 }; 988 989 static const struct panel_desc auo_g121ean01 = { 990 .modes = &auo_g121ean01_mode, 991 .num_modes = 1, 992 .bpc = 8, 993 .size = { 994 .width = 261, 995 .height = 163, 996 }, 997 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 999 }; 1000 1001 static const struct display_timing auo_g133han01_timings = { 1002 .pixelclock = { 134000000, 141200000, 149000000 }, 1003 .hactive = { 1920, 1920, 1920 }, 1004 .hfront_porch = { 39, 58, 77 }, 1005 .hback_porch = { 59, 88, 117 }, 1006 .hsync_len = { 28, 42, 56 }, 1007 .vactive = { 1080, 1080, 1080 }, 1008 .vfront_porch = { 3, 8, 11 }, 1009 .vback_porch = { 5, 14, 19 }, 1010 .vsync_len = { 4, 14, 19 }, 1011 }; 1012 1013 static const struct panel_desc auo_g133han01 = { 1014 .timings = &auo_g133han01_timings, 1015 .num_timings = 1, 1016 .bpc = 8, 1017 .size = { 1018 .width = 293, 1019 .height = 165, 1020 }, 1021 .delay = { 1022 .prepare = 200, 1023 .enable = 50, 1024 .disable = 50, 1025 .unprepare = 1000, 1026 }, 1027 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1028 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1029 }; 1030 1031 static const struct drm_display_mode auo_g156xtn01_mode = { 1032 .clock = 76000, 1033 .hdisplay = 1366, 1034 .hsync_start = 1366 + 33, 1035 .hsync_end = 1366 + 33 + 67, 1036 .htotal = 1560, 1037 .vdisplay = 768, 1038 .vsync_start = 768 + 4, 1039 .vsync_end = 768 + 4 + 4, 1040 .vtotal = 806, 1041 }; 1042 1043 static const struct panel_desc auo_g156xtn01 = { 1044 .modes = &auo_g156xtn01_mode, 1045 .num_modes = 1, 1046 .bpc = 8, 1047 .size = { 1048 .width = 344, 1049 .height = 194, 1050 }, 1051 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1052 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1053 }; 1054 1055 static const struct display_timing auo_g185han01_timings = { 1056 .pixelclock = { 120000000, 144000000, 175000000 }, 1057 .hactive = { 1920, 1920, 1920 }, 1058 .hfront_porch = { 36, 120, 148 }, 1059 .hback_porch = { 24, 88, 108 }, 1060 .hsync_len = { 20, 48, 64 }, 1061 .vactive = { 1080, 1080, 1080 }, 1062 .vfront_porch = { 6, 10, 40 }, 1063 .vback_porch = { 2, 5, 20 }, 1064 .vsync_len = { 2, 5, 20 }, 1065 }; 1066 1067 static const struct panel_desc auo_g185han01 = { 1068 .timings = &auo_g185han01_timings, 1069 .num_timings = 1, 1070 .bpc = 8, 1071 .size = { 1072 .width = 409, 1073 .height = 230, 1074 }, 1075 .delay = { 1076 .prepare = 50, 1077 .enable = 200, 1078 .disable = 110, 1079 .unprepare = 1000, 1080 }, 1081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1082 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1083 }; 1084 1085 static const struct display_timing auo_g190ean01_timings = { 1086 .pixelclock = { 90000000, 108000000, 135000000 }, 1087 .hactive = { 1280, 1280, 1280 }, 1088 .hfront_porch = { 126, 184, 1266 }, 1089 .hback_porch = { 84, 122, 844 }, 1090 .hsync_len = { 70, 102, 704 }, 1091 .vactive = { 1024, 1024, 1024 }, 1092 .vfront_porch = { 4, 26, 76 }, 1093 .vback_porch = { 2, 8, 25 }, 1094 .vsync_len = { 2, 8, 25 }, 1095 }; 1096 1097 static const struct panel_desc auo_g190ean01 = { 1098 .timings = &auo_g190ean01_timings, 1099 .num_timings = 1, 1100 .bpc = 8, 1101 .size = { 1102 .width = 376, 1103 .height = 301, 1104 }, 1105 .delay = { 1106 .prepare = 50, 1107 .enable = 200, 1108 .disable = 110, 1109 .unprepare = 1000, 1110 }, 1111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1112 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1113 }; 1114 1115 static const struct display_timing auo_p320hvn03_timings = { 1116 .pixelclock = { 106000000, 148500000, 164000000 }, 1117 .hactive = { 1920, 1920, 1920 }, 1118 .hfront_porch = { 25, 50, 130 }, 1119 .hback_porch = { 25, 50, 130 }, 1120 .hsync_len = { 20, 40, 105 }, 1121 .vactive = { 1080, 1080, 1080 }, 1122 .vfront_porch = { 8, 17, 150 }, 1123 .vback_porch = { 8, 17, 150 }, 1124 .vsync_len = { 4, 11, 100 }, 1125 }; 1126 1127 static const struct panel_desc auo_p320hvn03 = { 1128 .timings = &auo_p320hvn03_timings, 1129 .num_timings = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 698, 1133 .height = 393, 1134 }, 1135 .delay = { 1136 .prepare = 1, 1137 .enable = 450, 1138 .unprepare = 500, 1139 }, 1140 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1141 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1142 }; 1143 1144 static const struct drm_display_mode auo_t215hvn01_mode = { 1145 .clock = 148800, 1146 .hdisplay = 1920, 1147 .hsync_start = 1920 + 88, 1148 .hsync_end = 1920 + 88 + 44, 1149 .htotal = 1920 + 88 + 44 + 148, 1150 .vdisplay = 1080, 1151 .vsync_start = 1080 + 4, 1152 .vsync_end = 1080 + 4 + 5, 1153 .vtotal = 1080 + 4 + 5 + 36, 1154 }; 1155 1156 static const struct panel_desc auo_t215hvn01 = { 1157 .modes = &auo_t215hvn01_mode, 1158 .num_modes = 1, 1159 .bpc = 8, 1160 .size = { 1161 .width = 430, 1162 .height = 270, 1163 }, 1164 .delay = { 1165 .disable = 5, 1166 .unprepare = 1000, 1167 } 1168 }; 1169 1170 static const struct drm_display_mode avic_tm070ddh03_mode = { 1171 .clock = 51200, 1172 .hdisplay = 1024, 1173 .hsync_start = 1024 + 160, 1174 .hsync_end = 1024 + 160 + 4, 1175 .htotal = 1024 + 160 + 4 + 156, 1176 .vdisplay = 600, 1177 .vsync_start = 600 + 17, 1178 .vsync_end = 600 + 17 + 1, 1179 .vtotal = 600 + 17 + 1 + 17, 1180 }; 1181 1182 static const struct panel_desc avic_tm070ddh03 = { 1183 .modes = &avic_tm070ddh03_mode, 1184 .num_modes = 1, 1185 .bpc = 8, 1186 .size = { 1187 .width = 154, 1188 .height = 90, 1189 }, 1190 .delay = { 1191 .prepare = 20, 1192 .enable = 200, 1193 .disable = 200, 1194 }, 1195 }; 1196 1197 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1198 .clock = 30000, 1199 .hdisplay = 800, 1200 .hsync_start = 800 + 40, 1201 .hsync_end = 800 + 40 + 48, 1202 .htotal = 800 + 40 + 48 + 40, 1203 .vdisplay = 480, 1204 .vsync_start = 480 + 13, 1205 .vsync_end = 480 + 13 + 3, 1206 .vtotal = 480 + 13 + 3 + 29, 1207 }; 1208 1209 static const struct panel_desc bananapi_s070wv20_ct16 = { 1210 .modes = &bananapi_s070wv20_ct16_mode, 1211 .num_modes = 1, 1212 .bpc = 6, 1213 .size = { 1214 .width = 154, 1215 .height = 86, 1216 }, 1217 }; 1218 1219 static const struct drm_display_mode boe_hv070wsa_mode = { 1220 .clock = 42105, 1221 .hdisplay = 1024, 1222 .hsync_start = 1024 + 30, 1223 .hsync_end = 1024 + 30 + 30, 1224 .htotal = 1024 + 30 + 30 + 30, 1225 .vdisplay = 600, 1226 .vsync_start = 600 + 10, 1227 .vsync_end = 600 + 10 + 10, 1228 .vtotal = 600 + 10 + 10 + 10, 1229 }; 1230 1231 static const struct panel_desc boe_hv070wsa = { 1232 .modes = &boe_hv070wsa_mode, 1233 .num_modes = 1, 1234 .bpc = 8, 1235 .size = { 1236 .width = 154, 1237 .height = 90, 1238 }, 1239 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1240 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1241 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1242 }; 1243 1244 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1245 .clock = 9000, 1246 .hdisplay = 480, 1247 .hsync_start = 480 + 5, 1248 .hsync_end = 480 + 5 + 5, 1249 .htotal = 480 + 5 + 5 + 40, 1250 .vdisplay = 272, 1251 .vsync_start = 272 + 8, 1252 .vsync_end = 272 + 8 + 8, 1253 .vtotal = 272 + 8 + 8 + 8, 1254 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1255 }; 1256 1257 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1258 .modes = &cdtech_s043wq26h_ct7_mode, 1259 .num_modes = 1, 1260 .bpc = 8, 1261 .size = { 1262 .width = 95, 1263 .height = 54, 1264 }, 1265 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1266 }; 1267 1268 /* S070PWS19HP-FC21 2017/04/22 */ 1269 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1270 .clock = 51200, 1271 .hdisplay = 1024, 1272 .hsync_start = 1024 + 160, 1273 .hsync_end = 1024 + 160 + 20, 1274 .htotal = 1024 + 160 + 20 + 140, 1275 .vdisplay = 600, 1276 .vsync_start = 600 + 12, 1277 .vsync_end = 600 + 12 + 3, 1278 .vtotal = 600 + 12 + 3 + 20, 1279 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1280 }; 1281 1282 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1283 .modes = &cdtech_s070pws19hp_fc21_mode, 1284 .num_modes = 1, 1285 .bpc = 6, 1286 .size = { 1287 .width = 154, 1288 .height = 86, 1289 }, 1290 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1291 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1292 .connector_type = DRM_MODE_CONNECTOR_DPI, 1293 }; 1294 1295 /* S070SWV29HG-DC44 2017/09/21 */ 1296 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1297 .clock = 33300, 1298 .hdisplay = 800, 1299 .hsync_start = 800 + 210, 1300 .hsync_end = 800 + 210 + 2, 1301 .htotal = 800 + 210 + 2 + 44, 1302 .vdisplay = 480, 1303 .vsync_start = 480 + 22, 1304 .vsync_end = 480 + 22 + 2, 1305 .vtotal = 480 + 22 + 2 + 21, 1306 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1307 }; 1308 1309 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1310 .modes = &cdtech_s070swv29hg_dc44_mode, 1311 .num_modes = 1, 1312 .bpc = 6, 1313 .size = { 1314 .width = 154, 1315 .height = 86, 1316 }, 1317 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1319 .connector_type = DRM_MODE_CONNECTOR_DPI, 1320 }; 1321 1322 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1323 .clock = 35000, 1324 .hdisplay = 800, 1325 .hsync_start = 800 + 40, 1326 .hsync_end = 800 + 40 + 40, 1327 .htotal = 800 + 40 + 40 + 48, 1328 .vdisplay = 480, 1329 .vsync_start = 480 + 29, 1330 .vsync_end = 480 + 29 + 13, 1331 .vtotal = 480 + 29 + 13 + 3, 1332 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1333 }; 1334 1335 static const struct panel_desc cdtech_s070wv95_ct16 = { 1336 .modes = &cdtech_s070wv95_ct16_mode, 1337 .num_modes = 1, 1338 .bpc = 8, 1339 .size = { 1340 .width = 154, 1341 .height = 85, 1342 }, 1343 }; 1344 1345 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1346 .pixelclock = { 68900000, 71100000, 73400000 }, 1347 .hactive = { 1280, 1280, 1280 }, 1348 .hfront_porch = { 65, 80, 95 }, 1349 .hback_porch = { 64, 79, 94 }, 1350 .hsync_len = { 1, 1, 1 }, 1351 .vactive = { 800, 800, 800 }, 1352 .vfront_porch = { 7, 11, 14 }, 1353 .vback_porch = { 7, 11, 14 }, 1354 .vsync_len = { 1, 1, 1 }, 1355 .flags = DISPLAY_FLAGS_DE_HIGH, 1356 }; 1357 1358 static const struct panel_desc chefree_ch101olhlwh_002 = { 1359 .timings = &chefree_ch101olhlwh_002_timing, 1360 .num_timings = 1, 1361 .bpc = 8, 1362 .size = { 1363 .width = 217, 1364 .height = 135, 1365 }, 1366 .delay = { 1367 .enable = 200, 1368 .disable = 200, 1369 }, 1370 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1372 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1373 }; 1374 1375 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1376 .clock = 66770, 1377 .hdisplay = 800, 1378 .hsync_start = 800 + 49, 1379 .hsync_end = 800 + 49 + 33, 1380 .htotal = 800 + 49 + 33 + 17, 1381 .vdisplay = 1280, 1382 .vsync_start = 1280 + 1, 1383 .vsync_end = 1280 + 1 + 7, 1384 .vtotal = 1280 + 1 + 7 + 15, 1385 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1386 }; 1387 1388 static const struct panel_desc chunghwa_claa070wp03xg = { 1389 .modes = &chunghwa_claa070wp03xg_mode, 1390 .num_modes = 1, 1391 .bpc = 6, 1392 .size = { 1393 .width = 94, 1394 .height = 150, 1395 }, 1396 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1397 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1399 }; 1400 1401 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1402 .clock = 72070, 1403 .hdisplay = 1366, 1404 .hsync_start = 1366 + 58, 1405 .hsync_end = 1366 + 58 + 58, 1406 .htotal = 1366 + 58 + 58 + 58, 1407 .vdisplay = 768, 1408 .vsync_start = 768 + 4, 1409 .vsync_end = 768 + 4 + 4, 1410 .vtotal = 768 + 4 + 4 + 4, 1411 }; 1412 1413 static const struct panel_desc chunghwa_claa101wa01a = { 1414 .modes = &chunghwa_claa101wa01a_mode, 1415 .num_modes = 1, 1416 .bpc = 6, 1417 .size = { 1418 .width = 220, 1419 .height = 120, 1420 }, 1421 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1422 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1423 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1424 }; 1425 1426 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1427 .clock = 69300, 1428 .hdisplay = 1366, 1429 .hsync_start = 1366 + 48, 1430 .hsync_end = 1366 + 48 + 32, 1431 .htotal = 1366 + 48 + 32 + 20, 1432 .vdisplay = 768, 1433 .vsync_start = 768 + 16, 1434 .vsync_end = 768 + 16 + 8, 1435 .vtotal = 768 + 16 + 8 + 16, 1436 }; 1437 1438 static const struct panel_desc chunghwa_claa101wb01 = { 1439 .modes = &chunghwa_claa101wb01_mode, 1440 .num_modes = 1, 1441 .bpc = 6, 1442 .size = { 1443 .width = 223, 1444 .height = 125, 1445 }, 1446 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1447 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1448 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1449 }; 1450 1451 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1452 .pixelclock = { 5000000, 9000000, 12000000 }, 1453 .hactive = { 480, 480, 480 }, 1454 .hfront_porch = { 12, 12, 12 }, 1455 .hback_porch = { 12, 12, 12 }, 1456 .hsync_len = { 21, 21, 21 }, 1457 .vactive = { 272, 272, 272 }, 1458 .vfront_porch = { 4, 4, 4 }, 1459 .vback_porch = { 4, 4, 4 }, 1460 .vsync_len = { 8, 8, 8 }, 1461 }; 1462 1463 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1464 .timings = &dataimage_fg040346dsswbg04_timing, 1465 .num_timings = 1, 1466 .bpc = 8, 1467 .size = { 1468 .width = 95, 1469 .height = 54, 1470 }, 1471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1473 .connector_type = DRM_MODE_CONNECTOR_DPI, 1474 }; 1475 1476 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1477 .pixelclock = { 68900000, 71110000, 73400000 }, 1478 .hactive = { 1280, 1280, 1280 }, 1479 .vactive = { 800, 800, 800 }, 1480 .hback_porch = { 100, 100, 100 }, 1481 .hfront_porch = { 100, 100, 100 }, 1482 .vback_porch = { 5, 5, 5 }, 1483 .vfront_porch = { 5, 5, 5 }, 1484 .hsync_len = { 24, 24, 24 }, 1485 .vsync_len = { 3, 3, 3 }, 1486 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1487 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1488 }; 1489 1490 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1491 .timings = &dataimage_fg1001l0dsswmg01_timing, 1492 .num_timings = 1, 1493 .bpc = 8, 1494 .size = { 1495 .width = 217, 1496 .height = 136, 1497 }, 1498 }; 1499 1500 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1501 .clock = 33260, 1502 .hdisplay = 800, 1503 .hsync_start = 800 + 40, 1504 .hsync_end = 800 + 40 + 128, 1505 .htotal = 800 + 40 + 128 + 88, 1506 .vdisplay = 480, 1507 .vsync_start = 480 + 10, 1508 .vsync_end = 480 + 10 + 2, 1509 .vtotal = 480 + 10 + 2 + 33, 1510 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1511 }; 1512 1513 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1514 .modes = &dataimage_scf0700c48ggu18_mode, 1515 .num_modes = 1, 1516 .bpc = 8, 1517 .size = { 1518 .width = 152, 1519 .height = 91, 1520 }, 1521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1522 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1523 }; 1524 1525 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1526 .pixelclock = { 45000000, 51200000, 57000000 }, 1527 .hactive = { 1024, 1024, 1024 }, 1528 .hfront_porch = { 100, 106, 113 }, 1529 .hback_porch = { 100, 106, 113 }, 1530 .hsync_len = { 100, 108, 114 }, 1531 .vactive = { 600, 600, 600 }, 1532 .vfront_porch = { 8, 11, 15 }, 1533 .vback_porch = { 8, 11, 15 }, 1534 .vsync_len = { 9, 13, 15 }, 1535 .flags = DISPLAY_FLAGS_DE_HIGH, 1536 }; 1537 1538 static const struct panel_desc dlc_dlc0700yzg_1 = { 1539 .timings = &dlc_dlc0700yzg_1_timing, 1540 .num_timings = 1, 1541 .bpc = 6, 1542 .size = { 1543 .width = 154, 1544 .height = 86, 1545 }, 1546 .delay = { 1547 .prepare = 30, 1548 .enable = 200, 1549 .disable = 200, 1550 }, 1551 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1552 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1553 }; 1554 1555 static const struct display_timing dlc_dlc1010gig_timing = { 1556 .pixelclock = { 68900000, 71100000, 73400000 }, 1557 .hactive = { 1280, 1280, 1280 }, 1558 .hfront_porch = { 43, 53, 63 }, 1559 .hback_porch = { 43, 53, 63 }, 1560 .hsync_len = { 44, 54, 64 }, 1561 .vactive = { 800, 800, 800 }, 1562 .vfront_porch = { 5, 8, 11 }, 1563 .vback_porch = { 5, 8, 11 }, 1564 .vsync_len = { 5, 7, 11 }, 1565 .flags = DISPLAY_FLAGS_DE_HIGH, 1566 }; 1567 1568 static const struct panel_desc dlc_dlc1010gig = { 1569 .timings = &dlc_dlc1010gig_timing, 1570 .num_timings = 1, 1571 .bpc = 8, 1572 .size = { 1573 .width = 216, 1574 .height = 135, 1575 }, 1576 .delay = { 1577 .prepare = 60, 1578 .enable = 150, 1579 .disable = 100, 1580 .unprepare = 60, 1581 }, 1582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1583 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1584 }; 1585 1586 static const struct drm_display_mode edt_et035012dm6_mode = { 1587 .clock = 6500, 1588 .hdisplay = 320, 1589 .hsync_start = 320 + 20, 1590 .hsync_end = 320 + 20 + 30, 1591 .htotal = 320 + 20 + 68, 1592 .vdisplay = 240, 1593 .vsync_start = 240 + 4, 1594 .vsync_end = 240 + 4 + 4, 1595 .vtotal = 240 + 4 + 4 + 14, 1596 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1597 }; 1598 1599 static const struct panel_desc edt_et035012dm6 = { 1600 .modes = &edt_et035012dm6_mode, 1601 .num_modes = 1, 1602 .bpc = 8, 1603 .size = { 1604 .width = 70, 1605 .height = 52, 1606 }, 1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1608 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1609 }; 1610 1611 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1612 .clock = 6520, 1613 .hdisplay = 320, 1614 .hsync_start = 320 + 20, 1615 .hsync_end = 320 + 20 + 68, 1616 .htotal = 320 + 20 + 68, 1617 .vdisplay = 240, 1618 .vsync_start = 240 + 4, 1619 .vsync_end = 240 + 4 + 18, 1620 .vtotal = 240 + 4 + 18, 1621 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1622 }; 1623 1624 static const struct panel_desc edt_etm0350g0dh6 = { 1625 .modes = &edt_etm0350g0dh6_mode, 1626 .num_modes = 1, 1627 .bpc = 6, 1628 .size = { 1629 .width = 70, 1630 .height = 53, 1631 }, 1632 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1633 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1634 .connector_type = DRM_MODE_CONNECTOR_DPI, 1635 }; 1636 1637 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1638 .clock = 10870, 1639 .hdisplay = 480, 1640 .hsync_start = 480 + 8, 1641 .hsync_end = 480 + 8 + 4, 1642 .htotal = 480 + 8 + 4 + 41, 1643 1644 /* 1645 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1646 * fb_align 1647 */ 1648 1649 .vdisplay = 288, 1650 .vsync_start = 288 + 2, 1651 .vsync_end = 288 + 2 + 4, 1652 .vtotal = 288 + 2 + 4 + 10, 1653 }; 1654 1655 static const struct panel_desc edt_etm043080dh6gp = { 1656 .modes = &edt_etm043080dh6gp_mode, 1657 .num_modes = 1, 1658 .bpc = 8, 1659 .size = { 1660 .width = 100, 1661 .height = 65, 1662 }, 1663 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1664 .connector_type = DRM_MODE_CONNECTOR_DPI, 1665 }; 1666 1667 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1668 .clock = 9000, 1669 .hdisplay = 480, 1670 .hsync_start = 480 + 2, 1671 .hsync_end = 480 + 2 + 41, 1672 .htotal = 480 + 2 + 41 + 2, 1673 .vdisplay = 272, 1674 .vsync_start = 272 + 2, 1675 .vsync_end = 272 + 2 + 10, 1676 .vtotal = 272 + 2 + 10 + 2, 1677 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1678 }; 1679 1680 static const struct panel_desc edt_etm0430g0dh6 = { 1681 .modes = &edt_etm0430g0dh6_mode, 1682 .num_modes = 1, 1683 .bpc = 6, 1684 .size = { 1685 .width = 95, 1686 .height = 54, 1687 }, 1688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1690 .connector_type = DRM_MODE_CONNECTOR_DPI, 1691 }; 1692 1693 static const struct drm_display_mode edt_et057090dhu_mode = { 1694 .clock = 25175, 1695 .hdisplay = 640, 1696 .hsync_start = 640 + 16, 1697 .hsync_end = 640 + 16 + 30, 1698 .htotal = 640 + 16 + 30 + 114, 1699 .vdisplay = 480, 1700 .vsync_start = 480 + 10, 1701 .vsync_end = 480 + 10 + 3, 1702 .vtotal = 480 + 10 + 3 + 32, 1703 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1704 }; 1705 1706 static const struct panel_desc edt_et057090dhu = { 1707 .modes = &edt_et057090dhu_mode, 1708 .num_modes = 1, 1709 .bpc = 6, 1710 .size = { 1711 .width = 115, 1712 .height = 86, 1713 }, 1714 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1715 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1716 .connector_type = DRM_MODE_CONNECTOR_DPI, 1717 }; 1718 1719 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1720 .clock = 33260, 1721 .hdisplay = 800, 1722 .hsync_start = 800 + 40, 1723 .hsync_end = 800 + 40 + 128, 1724 .htotal = 800 + 40 + 128 + 88, 1725 .vdisplay = 480, 1726 .vsync_start = 480 + 10, 1727 .vsync_end = 480 + 10 + 2, 1728 .vtotal = 480 + 10 + 2 + 33, 1729 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1730 }; 1731 1732 static const struct panel_desc edt_etm0700g0dh6 = { 1733 .modes = &edt_etm0700g0dh6_mode, 1734 .num_modes = 1, 1735 .bpc = 6, 1736 .size = { 1737 .width = 152, 1738 .height = 91, 1739 }, 1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1742 .connector_type = DRM_MODE_CONNECTOR_DPI, 1743 }; 1744 1745 static const struct panel_desc edt_etm0700g0bdh6 = { 1746 .modes = &edt_etm0700g0dh6_mode, 1747 .num_modes = 1, 1748 .bpc = 6, 1749 .size = { 1750 .width = 152, 1751 .height = 91, 1752 }, 1753 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1754 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1755 .connector_type = DRM_MODE_CONNECTOR_DPI, 1756 }; 1757 1758 static const struct display_timing edt_etml0700y5dha_timing = { 1759 .pixelclock = { 40800000, 51200000, 67200000 }, 1760 .hactive = { 1024, 1024, 1024 }, 1761 .hfront_porch = { 30, 106, 125 }, 1762 .hback_porch = { 30, 106, 125 }, 1763 .hsync_len = { 30, 108, 126 }, 1764 .vactive = { 600, 600, 600 }, 1765 .vfront_porch = { 3, 12, 67}, 1766 .vback_porch = { 3, 12, 67 }, 1767 .vsync_len = { 4, 11, 66 }, 1768 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1769 DISPLAY_FLAGS_DE_HIGH, 1770 }; 1771 1772 static const struct panel_desc edt_etml0700y5dha = { 1773 .timings = &edt_etml0700y5dha_timing, 1774 .num_timings = 1, 1775 .bpc = 8, 1776 .size = { 1777 .width = 155, 1778 .height = 86, 1779 }, 1780 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1781 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1782 }; 1783 1784 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1785 .clock = 25175, 1786 .hdisplay = 640, 1787 .hsync_start = 640, 1788 .hsync_end = 640 + 16, 1789 .htotal = 640 + 16 + 30 + 114, 1790 .vdisplay = 480, 1791 .vsync_start = 480 + 10, 1792 .vsync_end = 480 + 10 + 3, 1793 .vtotal = 480 + 10 + 3 + 35, 1794 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1795 }; 1796 1797 static const struct panel_desc edt_etmv570g2dhu = { 1798 .modes = &edt_etmv570g2dhu_mode, 1799 .num_modes = 1, 1800 .bpc = 6, 1801 .size = { 1802 .width = 115, 1803 .height = 86, 1804 }, 1805 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1806 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1807 .connector_type = DRM_MODE_CONNECTOR_DPI, 1808 }; 1809 1810 static const struct display_timing eink_vb3300_kca_timing = { 1811 .pixelclock = { 40000000, 40000000, 40000000 }, 1812 .hactive = { 334, 334, 334 }, 1813 .hfront_porch = { 1, 1, 1 }, 1814 .hback_porch = { 1, 1, 1 }, 1815 .hsync_len = { 1, 1, 1 }, 1816 .vactive = { 1405, 1405, 1405 }, 1817 .vfront_porch = { 1, 1, 1 }, 1818 .vback_porch = { 1, 1, 1 }, 1819 .vsync_len = { 1, 1, 1 }, 1820 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1821 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1822 }; 1823 1824 static const struct panel_desc eink_vb3300_kca = { 1825 .timings = &eink_vb3300_kca_timing, 1826 .num_timings = 1, 1827 .bpc = 6, 1828 .size = { 1829 .width = 157, 1830 .height = 209, 1831 }, 1832 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1833 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1834 .connector_type = DRM_MODE_CONNECTOR_DPI, 1835 }; 1836 1837 static const struct display_timing evervision_vgg804821_timing = { 1838 .pixelclock = { 27600000, 33300000, 50000000 }, 1839 .hactive = { 800, 800, 800 }, 1840 .hfront_porch = { 40, 66, 70 }, 1841 .hback_porch = { 40, 67, 70 }, 1842 .hsync_len = { 40, 67, 70 }, 1843 .vactive = { 480, 480, 480 }, 1844 .vfront_porch = { 6, 10, 10 }, 1845 .vback_porch = { 7, 11, 11 }, 1846 .vsync_len = { 7, 11, 11 }, 1847 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1848 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1849 DISPLAY_FLAGS_SYNC_NEGEDGE, 1850 }; 1851 1852 static const struct panel_desc evervision_vgg804821 = { 1853 .timings = &evervision_vgg804821_timing, 1854 .num_timings = 1, 1855 .bpc = 8, 1856 .size = { 1857 .width = 108, 1858 .height = 64, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1862 }; 1863 1864 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1865 .clock = 32260, 1866 .hdisplay = 800, 1867 .hsync_start = 800 + 168, 1868 .hsync_end = 800 + 168 + 64, 1869 .htotal = 800 + 168 + 64 + 88, 1870 .vdisplay = 480, 1871 .vsync_start = 480 + 37, 1872 .vsync_end = 480 + 37 + 2, 1873 .vtotal = 480 + 37 + 2 + 8, 1874 }; 1875 1876 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1877 .modes = &foxlink_fl500wvr00_a0t_mode, 1878 .num_modes = 1, 1879 .bpc = 8, 1880 .size = { 1881 .width = 108, 1882 .height = 65, 1883 }, 1884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1885 }; 1886 1887 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1888 { /* 60 Hz */ 1889 .clock = 6000, 1890 .hdisplay = 320, 1891 .hsync_start = 320 + 44, 1892 .hsync_end = 320 + 44 + 16, 1893 .htotal = 320 + 44 + 16 + 20, 1894 .vdisplay = 240, 1895 .vsync_start = 240 + 2, 1896 .vsync_end = 240 + 2 + 6, 1897 .vtotal = 240 + 2 + 6 + 2, 1898 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1899 }, 1900 { /* 50 Hz */ 1901 .clock = 5400, 1902 .hdisplay = 320, 1903 .hsync_start = 320 + 56, 1904 .hsync_end = 320 + 56 + 16, 1905 .htotal = 320 + 56 + 16 + 40, 1906 .vdisplay = 240, 1907 .vsync_start = 240 + 2, 1908 .vsync_end = 240 + 2 + 6, 1909 .vtotal = 240 + 2 + 6 + 2, 1910 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1911 }, 1912 }; 1913 1914 static const struct panel_desc frida_frd350h54004 = { 1915 .modes = frida_frd350h54004_modes, 1916 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1917 .bpc = 8, 1918 .size = { 1919 .width = 77, 1920 .height = 64, 1921 }, 1922 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1923 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1924 .connector_type = DRM_MODE_CONNECTOR_DPI, 1925 }; 1926 1927 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1928 .clock = 67185, 1929 .hdisplay = 800, 1930 .hsync_start = 800 + 20, 1931 .hsync_end = 800 + 20 + 24, 1932 .htotal = 800 + 20 + 24 + 20, 1933 .vdisplay = 1280, 1934 .vsync_start = 1280 + 4, 1935 .vsync_end = 1280 + 4 + 8, 1936 .vtotal = 1280 + 4 + 8 + 4, 1937 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1938 }; 1939 1940 static const struct panel_desc friendlyarm_hd702e = { 1941 .modes = &friendlyarm_hd702e_mode, 1942 .num_modes = 1, 1943 .size = { 1944 .width = 94, 1945 .height = 151, 1946 }, 1947 }; 1948 1949 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1950 .clock = 9000, 1951 .hdisplay = 480, 1952 .hsync_start = 480 + 5, 1953 .hsync_end = 480 + 5 + 1, 1954 .htotal = 480 + 5 + 1 + 40, 1955 .vdisplay = 272, 1956 .vsync_start = 272 + 8, 1957 .vsync_end = 272 + 8 + 1, 1958 .vtotal = 272 + 8 + 1 + 8, 1959 }; 1960 1961 static const struct panel_desc giantplus_gpg482739qs5 = { 1962 .modes = &giantplus_gpg482739qs5_mode, 1963 .num_modes = 1, 1964 .bpc = 8, 1965 .size = { 1966 .width = 95, 1967 .height = 54, 1968 }, 1969 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1970 }; 1971 1972 static const struct display_timing giantplus_gpm940b0_timing = { 1973 .pixelclock = { 13500000, 27000000, 27500000 }, 1974 .hactive = { 320, 320, 320 }, 1975 .hfront_porch = { 14, 686, 718 }, 1976 .hback_porch = { 50, 70, 255 }, 1977 .hsync_len = { 1, 1, 1 }, 1978 .vactive = { 240, 240, 240 }, 1979 .vfront_porch = { 1, 1, 179 }, 1980 .vback_porch = { 1, 21, 31 }, 1981 .vsync_len = { 1, 1, 6 }, 1982 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1983 }; 1984 1985 static const struct panel_desc giantplus_gpm940b0 = { 1986 .timings = &giantplus_gpm940b0_timing, 1987 .num_timings = 1, 1988 .bpc = 8, 1989 .size = { 1990 .width = 60, 1991 .height = 45, 1992 }, 1993 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1994 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1995 }; 1996 1997 static const struct display_timing hannstar_hsd070pww1_timing = { 1998 .pixelclock = { 64300000, 71100000, 82000000 }, 1999 .hactive = { 1280, 1280, 1280 }, 2000 .hfront_porch = { 1, 1, 10 }, 2001 .hback_porch = { 1, 1, 10 }, 2002 /* 2003 * According to the data sheet, the minimum horizontal blanking interval 2004 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2005 * minimum working horizontal blanking interval to be 60 clocks. 2006 */ 2007 .hsync_len = { 58, 158, 661 }, 2008 .vactive = { 800, 800, 800 }, 2009 .vfront_porch = { 1, 1, 10 }, 2010 .vback_porch = { 1, 1, 10 }, 2011 .vsync_len = { 1, 21, 203 }, 2012 .flags = DISPLAY_FLAGS_DE_HIGH, 2013 }; 2014 2015 static const struct panel_desc hannstar_hsd070pww1 = { 2016 .timings = &hannstar_hsd070pww1_timing, 2017 .num_timings = 1, 2018 .bpc = 6, 2019 .size = { 2020 .width = 151, 2021 .height = 94, 2022 }, 2023 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2024 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2025 }; 2026 2027 static const struct display_timing hannstar_hsd100pxn1_timing = { 2028 .pixelclock = { 55000000, 65000000, 75000000 }, 2029 .hactive = { 1024, 1024, 1024 }, 2030 .hfront_porch = { 40, 40, 40 }, 2031 .hback_porch = { 220, 220, 220 }, 2032 .hsync_len = { 20, 60, 100 }, 2033 .vactive = { 768, 768, 768 }, 2034 .vfront_porch = { 7, 7, 7 }, 2035 .vback_porch = { 21, 21, 21 }, 2036 .vsync_len = { 10, 10, 10 }, 2037 .flags = DISPLAY_FLAGS_DE_HIGH, 2038 }; 2039 2040 static const struct panel_desc hannstar_hsd100pxn1 = { 2041 .timings = &hannstar_hsd100pxn1_timing, 2042 .num_timings = 1, 2043 .bpc = 6, 2044 .size = { 2045 .width = 203, 2046 .height = 152, 2047 }, 2048 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2049 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2050 }; 2051 2052 static const struct display_timing hannstar_hsd101pww2_timing = { 2053 .pixelclock = { 64300000, 71100000, 82000000 }, 2054 .hactive = { 1280, 1280, 1280 }, 2055 .hfront_porch = { 1, 1, 10 }, 2056 .hback_porch = { 1, 1, 10 }, 2057 .hsync_len = { 58, 158, 661 }, 2058 .vactive = { 800, 800, 800 }, 2059 .vfront_porch = { 1, 1, 10 }, 2060 .vback_porch = { 1, 1, 10 }, 2061 .vsync_len = { 1, 21, 203 }, 2062 .flags = DISPLAY_FLAGS_DE_HIGH, 2063 }; 2064 2065 static const struct panel_desc hannstar_hsd101pww2 = { 2066 .timings = &hannstar_hsd101pww2_timing, 2067 .num_timings = 1, 2068 .bpc = 8, 2069 .size = { 2070 .width = 217, 2071 .height = 136, 2072 }, 2073 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2074 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2075 }; 2076 2077 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2078 .clock = 33333, 2079 .hdisplay = 800, 2080 .hsync_start = 800 + 85, 2081 .hsync_end = 800 + 85 + 86, 2082 .htotal = 800 + 85 + 86 + 85, 2083 .vdisplay = 480, 2084 .vsync_start = 480 + 16, 2085 .vsync_end = 480 + 16 + 13, 2086 .vtotal = 480 + 16 + 13 + 16, 2087 }; 2088 2089 static const struct panel_desc hitachi_tx23d38vm0caa = { 2090 .modes = &hitachi_tx23d38vm0caa_mode, 2091 .num_modes = 1, 2092 .bpc = 6, 2093 .size = { 2094 .width = 195, 2095 .height = 117, 2096 }, 2097 .delay = { 2098 .enable = 160, 2099 .disable = 160, 2100 }, 2101 }; 2102 2103 static const struct drm_display_mode innolux_at043tn24_mode = { 2104 .clock = 9000, 2105 .hdisplay = 480, 2106 .hsync_start = 480 + 2, 2107 .hsync_end = 480 + 2 + 41, 2108 .htotal = 480 + 2 + 41 + 2, 2109 .vdisplay = 272, 2110 .vsync_start = 272 + 2, 2111 .vsync_end = 272 + 2 + 10, 2112 .vtotal = 272 + 2 + 10 + 2, 2113 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2114 }; 2115 2116 static const struct panel_desc innolux_at043tn24 = { 2117 .modes = &innolux_at043tn24_mode, 2118 .num_modes = 1, 2119 .bpc = 8, 2120 .size = { 2121 .width = 95, 2122 .height = 54, 2123 }, 2124 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2125 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2126 }; 2127 2128 static const struct drm_display_mode innolux_at070tn92_mode = { 2129 .clock = 33333, 2130 .hdisplay = 800, 2131 .hsync_start = 800 + 210, 2132 .hsync_end = 800 + 210 + 20, 2133 .htotal = 800 + 210 + 20 + 46, 2134 .vdisplay = 480, 2135 .vsync_start = 480 + 22, 2136 .vsync_end = 480 + 22 + 10, 2137 .vtotal = 480 + 22 + 23 + 10, 2138 }; 2139 2140 static const struct panel_desc innolux_at070tn92 = { 2141 .modes = &innolux_at070tn92_mode, 2142 .num_modes = 1, 2143 .size = { 2144 .width = 154, 2145 .height = 86, 2146 }, 2147 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2148 }; 2149 2150 static const struct display_timing innolux_g070y2_l01_timing = { 2151 .pixelclock = { 28000000, 29500000, 32000000 }, 2152 .hactive = { 800, 800, 800 }, 2153 .hfront_porch = { 61, 91, 141 }, 2154 .hback_porch = { 60, 90, 140 }, 2155 .hsync_len = { 12, 12, 12 }, 2156 .vactive = { 480, 480, 480 }, 2157 .vfront_porch = { 4, 9, 30 }, 2158 .vback_porch = { 4, 8, 28 }, 2159 .vsync_len = { 2, 2, 2 }, 2160 .flags = DISPLAY_FLAGS_DE_HIGH, 2161 }; 2162 2163 static const struct panel_desc innolux_g070y2_l01 = { 2164 .timings = &innolux_g070y2_l01_timing, 2165 .num_timings = 1, 2166 .bpc = 8, 2167 .size = { 2168 .width = 152, 2169 .height = 91, 2170 }, 2171 .delay = { 2172 .prepare = 10, 2173 .enable = 100, 2174 .disable = 100, 2175 .unprepare = 800, 2176 }, 2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2179 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2180 }; 2181 2182 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2183 .clock = 33333, 2184 .hdisplay = 800, 2185 .hsync_start = 800 + 210, 2186 .hsync_end = 800 + 210 + 20, 2187 .htotal = 800 + 210 + 20 + 46, 2188 .vdisplay = 480, 2189 .vsync_start = 480 + 22, 2190 .vsync_end = 480 + 22 + 10, 2191 .vtotal = 480 + 22 + 23 + 10, 2192 }; 2193 2194 static const struct panel_desc innolux_g070y2_t02 = { 2195 .modes = &innolux_g070y2_t02_mode, 2196 .num_modes = 1, 2197 .bpc = 8, 2198 .size = { 2199 .width = 152, 2200 .height = 92, 2201 }, 2202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2203 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2204 .connector_type = DRM_MODE_CONNECTOR_DPI, 2205 }; 2206 2207 static const struct display_timing innolux_g101ice_l01_timing = { 2208 .pixelclock = { 60400000, 71100000, 74700000 }, 2209 .hactive = { 1280, 1280, 1280 }, 2210 .hfront_porch = { 41, 80, 100 }, 2211 .hback_porch = { 40, 79, 99 }, 2212 .hsync_len = { 1, 1, 1 }, 2213 .vactive = { 800, 800, 800 }, 2214 .vfront_porch = { 5, 11, 14 }, 2215 .vback_porch = { 4, 11, 14 }, 2216 .vsync_len = { 1, 1, 1 }, 2217 .flags = DISPLAY_FLAGS_DE_HIGH, 2218 }; 2219 2220 static const struct panel_desc innolux_g101ice_l01 = { 2221 .timings = &innolux_g101ice_l01_timing, 2222 .num_timings = 1, 2223 .bpc = 8, 2224 .size = { 2225 .width = 217, 2226 .height = 135, 2227 }, 2228 .delay = { 2229 .enable = 200, 2230 .disable = 200, 2231 }, 2232 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2233 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2234 }; 2235 2236 static const struct display_timing innolux_g121i1_l01_timing = { 2237 .pixelclock = { 67450000, 71000000, 74550000 }, 2238 .hactive = { 1280, 1280, 1280 }, 2239 .hfront_porch = { 40, 80, 160 }, 2240 .hback_porch = { 39, 79, 159 }, 2241 .hsync_len = { 1, 1, 1 }, 2242 .vactive = { 800, 800, 800 }, 2243 .vfront_porch = { 5, 11, 100 }, 2244 .vback_porch = { 4, 11, 99 }, 2245 .vsync_len = { 1, 1, 1 }, 2246 }; 2247 2248 static const struct panel_desc innolux_g121i1_l01 = { 2249 .timings = &innolux_g121i1_l01_timing, 2250 .num_timings = 1, 2251 .bpc = 6, 2252 .size = { 2253 .width = 261, 2254 .height = 163, 2255 }, 2256 .delay = { 2257 .enable = 200, 2258 .disable = 20, 2259 }, 2260 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2261 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2262 }; 2263 2264 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2265 .clock = 65000, 2266 .hdisplay = 1024, 2267 .hsync_start = 1024 + 0, 2268 .hsync_end = 1024 + 1, 2269 .htotal = 1024 + 0 + 1 + 320, 2270 .vdisplay = 768, 2271 .vsync_start = 768 + 38, 2272 .vsync_end = 768 + 38 + 1, 2273 .vtotal = 768 + 38 + 1 + 0, 2274 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2275 }; 2276 2277 static const struct panel_desc innolux_g121x1_l03 = { 2278 .modes = &innolux_g121x1_l03_mode, 2279 .num_modes = 1, 2280 .bpc = 6, 2281 .size = { 2282 .width = 246, 2283 .height = 185, 2284 }, 2285 .delay = { 2286 .enable = 200, 2287 .unprepare = 200, 2288 .disable = 400, 2289 }, 2290 }; 2291 2292 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2293 .clock = 69300, 2294 .hdisplay = 1366, 2295 .hsync_start = 1366 + 16, 2296 .hsync_end = 1366 + 16 + 34, 2297 .htotal = 1366 + 16 + 34 + 50, 2298 .vdisplay = 768, 2299 .vsync_start = 768 + 2, 2300 .vsync_end = 768 + 2 + 6, 2301 .vtotal = 768 + 2 + 6 + 12, 2302 }; 2303 2304 static const struct panel_desc innolux_n156bge_l21 = { 2305 .modes = &innolux_n156bge_l21_mode, 2306 .num_modes = 1, 2307 .bpc = 6, 2308 .size = { 2309 .width = 344, 2310 .height = 193, 2311 }, 2312 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2313 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2314 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2315 }; 2316 2317 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2318 .clock = 51501, 2319 .hdisplay = 1024, 2320 .hsync_start = 1024 + 128, 2321 .hsync_end = 1024 + 128 + 64, 2322 .htotal = 1024 + 128 + 64 + 128, 2323 .vdisplay = 600, 2324 .vsync_start = 600 + 16, 2325 .vsync_end = 600 + 16 + 4, 2326 .vtotal = 600 + 16 + 4 + 16, 2327 }; 2328 2329 static const struct panel_desc innolux_zj070na_01p = { 2330 .modes = &innolux_zj070na_01p_mode, 2331 .num_modes = 1, 2332 .bpc = 6, 2333 .size = { 2334 .width = 154, 2335 .height = 90, 2336 }, 2337 }; 2338 2339 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2340 .pixelclock = { 5580000, 5850000, 6200000 }, 2341 .hactive = { 320, 320, 320 }, 2342 .hfront_porch = { 30, 30, 30 }, 2343 .hback_porch = { 30, 30, 30 }, 2344 .hsync_len = { 1, 5, 17 }, 2345 .vactive = { 240, 240, 240 }, 2346 .vfront_porch = { 6, 6, 6 }, 2347 .vback_porch = { 5, 5, 5 }, 2348 .vsync_len = { 1, 2, 11 }, 2349 .flags = DISPLAY_FLAGS_DE_HIGH, 2350 }; 2351 2352 static const struct panel_desc koe_tx14d24vm1bpa = { 2353 .timings = &koe_tx14d24vm1bpa_timing, 2354 .num_timings = 1, 2355 .bpc = 6, 2356 .size = { 2357 .width = 115, 2358 .height = 86, 2359 }, 2360 }; 2361 2362 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2363 .pixelclock = { 151820000, 156720000, 159780000 }, 2364 .hactive = { 1920, 1920, 1920 }, 2365 .hfront_porch = { 105, 130, 142 }, 2366 .hback_porch = { 45, 70, 82 }, 2367 .hsync_len = { 30, 30, 30 }, 2368 .vactive = { 1200, 1200, 1200}, 2369 .vfront_porch = { 3, 5, 10 }, 2370 .vback_porch = { 2, 5, 10 }, 2371 .vsync_len = { 5, 5, 5 }, 2372 }; 2373 2374 static const struct panel_desc koe_tx26d202vm0bwa = { 2375 .timings = &koe_tx26d202vm0bwa_timing, 2376 .num_timings = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 217, 2380 .height = 136, 2381 }, 2382 .delay = { 2383 .prepare = 1000, 2384 .enable = 1000, 2385 .unprepare = 1000, 2386 .disable = 1000, 2387 }, 2388 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2389 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2390 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2391 }; 2392 2393 static const struct display_timing koe_tx31d200vm0baa_timing = { 2394 .pixelclock = { 39600000, 43200000, 48000000 }, 2395 .hactive = { 1280, 1280, 1280 }, 2396 .hfront_porch = { 16, 36, 56 }, 2397 .hback_porch = { 16, 36, 56 }, 2398 .hsync_len = { 8, 8, 8 }, 2399 .vactive = { 480, 480, 480 }, 2400 .vfront_porch = { 6, 21, 33 }, 2401 .vback_porch = { 6, 21, 33 }, 2402 .vsync_len = { 8, 8, 8 }, 2403 .flags = DISPLAY_FLAGS_DE_HIGH, 2404 }; 2405 2406 static const struct panel_desc koe_tx31d200vm0baa = { 2407 .timings = &koe_tx31d200vm0baa_timing, 2408 .num_timings = 1, 2409 .bpc = 6, 2410 .size = { 2411 .width = 292, 2412 .height = 109, 2413 }, 2414 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2415 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2416 }; 2417 2418 static const struct display_timing kyo_tcg121xglp_timing = { 2419 .pixelclock = { 52000000, 65000000, 71000000 }, 2420 .hactive = { 1024, 1024, 1024 }, 2421 .hfront_porch = { 2, 2, 2 }, 2422 .hback_porch = { 2, 2, 2 }, 2423 .hsync_len = { 86, 124, 244 }, 2424 .vactive = { 768, 768, 768 }, 2425 .vfront_porch = { 2, 2, 2 }, 2426 .vback_porch = { 2, 2, 2 }, 2427 .vsync_len = { 6, 34, 73 }, 2428 .flags = DISPLAY_FLAGS_DE_HIGH, 2429 }; 2430 2431 static const struct panel_desc kyo_tcg121xglp = { 2432 .timings = &kyo_tcg121xglp_timing, 2433 .num_timings = 1, 2434 .bpc = 8, 2435 .size = { 2436 .width = 246, 2437 .height = 184, 2438 }, 2439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2441 }; 2442 2443 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2444 .clock = 7000, 2445 .hdisplay = 320, 2446 .hsync_start = 320 + 20, 2447 .hsync_end = 320 + 20 + 30, 2448 .htotal = 320 + 20 + 30 + 38, 2449 .vdisplay = 240, 2450 .vsync_start = 240 + 4, 2451 .vsync_end = 240 + 4 + 3, 2452 .vtotal = 240 + 4 + 3 + 15, 2453 }; 2454 2455 static const struct panel_desc lemaker_bl035_rgb_002 = { 2456 .modes = &lemaker_bl035_rgb_002_mode, 2457 .num_modes = 1, 2458 .size = { 2459 .width = 70, 2460 .height = 52, 2461 }, 2462 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2463 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2464 }; 2465 2466 static const struct drm_display_mode lg_lb070wv8_mode = { 2467 .clock = 33246, 2468 .hdisplay = 800, 2469 .hsync_start = 800 + 88, 2470 .hsync_end = 800 + 88 + 80, 2471 .htotal = 800 + 88 + 80 + 88, 2472 .vdisplay = 480, 2473 .vsync_start = 480 + 10, 2474 .vsync_end = 480 + 10 + 25, 2475 .vtotal = 480 + 10 + 25 + 10, 2476 }; 2477 2478 static const struct panel_desc lg_lb070wv8 = { 2479 .modes = &lg_lb070wv8_mode, 2480 .num_modes = 1, 2481 .bpc = 8, 2482 .size = { 2483 .width = 151, 2484 .height = 91, 2485 }, 2486 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2488 }; 2489 2490 static const struct display_timing logictechno_lt161010_2nh_timing = { 2491 .pixelclock = { 26400000, 33300000, 46800000 }, 2492 .hactive = { 800, 800, 800 }, 2493 .hfront_porch = { 16, 210, 354 }, 2494 .hback_porch = { 46, 46, 46 }, 2495 .hsync_len = { 1, 20, 40 }, 2496 .vactive = { 480, 480, 480 }, 2497 .vfront_porch = { 7, 22, 147 }, 2498 .vback_porch = { 23, 23, 23 }, 2499 .vsync_len = { 1, 10, 20 }, 2500 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2501 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2502 DISPLAY_FLAGS_SYNC_POSEDGE, 2503 }; 2504 2505 static const struct panel_desc logictechno_lt161010_2nh = { 2506 .timings = &logictechno_lt161010_2nh_timing, 2507 .num_timings = 1, 2508 .size = { 2509 .width = 154, 2510 .height = 86, 2511 }, 2512 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2513 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2514 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2515 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2516 .connector_type = DRM_MODE_CONNECTOR_DPI, 2517 }; 2518 2519 static const struct display_timing logictechno_lt170410_2whc_timing = { 2520 .pixelclock = { 68900000, 71100000, 73400000 }, 2521 .hactive = { 1280, 1280, 1280 }, 2522 .hfront_porch = { 23, 60, 71 }, 2523 .hback_porch = { 23, 60, 71 }, 2524 .hsync_len = { 15, 40, 47 }, 2525 .vactive = { 800, 800, 800 }, 2526 .vfront_porch = { 5, 7, 10 }, 2527 .vback_porch = { 5, 7, 10 }, 2528 .vsync_len = { 6, 9, 12 }, 2529 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2530 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2531 DISPLAY_FLAGS_SYNC_POSEDGE, 2532 }; 2533 2534 static const struct panel_desc logictechno_lt170410_2whc = { 2535 .timings = &logictechno_lt170410_2whc_timing, 2536 .num_timings = 1, 2537 .size = { 2538 .width = 217, 2539 .height = 136, 2540 }, 2541 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2542 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2543 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2544 }; 2545 2546 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2547 .clock = 33000, 2548 .hdisplay = 800, 2549 .hsync_start = 800 + 112, 2550 .hsync_end = 800 + 112 + 3, 2551 .htotal = 800 + 112 + 3 + 85, 2552 .vdisplay = 480, 2553 .vsync_start = 480 + 38, 2554 .vsync_end = 480 + 38 + 3, 2555 .vtotal = 480 + 38 + 3 + 29, 2556 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2557 }; 2558 2559 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2560 .modes = &logictechno_lttd800480070_l2rt_mode, 2561 .num_modes = 1, 2562 .bpc = 8, 2563 .size = { 2564 .width = 154, 2565 .height = 86, 2566 }, 2567 .delay = { 2568 .prepare = 45, 2569 .enable = 100, 2570 .disable = 100, 2571 .unprepare = 45 2572 }, 2573 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2574 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2575 .connector_type = DRM_MODE_CONNECTOR_DPI, 2576 }; 2577 2578 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2579 .clock = 33000, 2580 .hdisplay = 800, 2581 .hsync_start = 800 + 154, 2582 .hsync_end = 800 + 154 + 3, 2583 .htotal = 800 + 154 + 3 + 43, 2584 .vdisplay = 480, 2585 .vsync_start = 480 + 47, 2586 .vsync_end = 480 + 47 + 3, 2587 .vtotal = 480 + 47 + 3 + 20, 2588 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2589 }; 2590 2591 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2592 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2593 .num_modes = 1, 2594 .bpc = 8, 2595 .size = { 2596 .width = 154, 2597 .height = 86, 2598 }, 2599 .delay = { 2600 .prepare = 45, 2601 .enable = 100, 2602 .disable = 100, 2603 .unprepare = 45 2604 }, 2605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2606 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2607 .connector_type = DRM_MODE_CONNECTOR_DPI, 2608 }; 2609 2610 static const struct drm_display_mode logicpd_type_28_mode = { 2611 .clock = 9107, 2612 .hdisplay = 480, 2613 .hsync_start = 480 + 3, 2614 .hsync_end = 480 + 3 + 42, 2615 .htotal = 480 + 3 + 42 + 2, 2616 2617 .vdisplay = 272, 2618 .vsync_start = 272 + 2, 2619 .vsync_end = 272 + 2 + 11, 2620 .vtotal = 272 + 2 + 11 + 3, 2621 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2622 }; 2623 2624 static const struct panel_desc logicpd_type_28 = { 2625 .modes = &logicpd_type_28_mode, 2626 .num_modes = 1, 2627 .bpc = 8, 2628 .size = { 2629 .width = 105, 2630 .height = 67, 2631 }, 2632 .delay = { 2633 .prepare = 200, 2634 .enable = 200, 2635 .unprepare = 200, 2636 .disable = 200, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2639 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2640 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2641 .connector_type = DRM_MODE_CONNECTOR_DPI, 2642 }; 2643 2644 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2645 .clock = 30400, 2646 .hdisplay = 800, 2647 .hsync_start = 800 + 0, 2648 .hsync_end = 800 + 1, 2649 .htotal = 800 + 0 + 1 + 160, 2650 .vdisplay = 480, 2651 .vsync_start = 480 + 0, 2652 .vsync_end = 480 + 48 + 1, 2653 .vtotal = 480 + 48 + 1 + 0, 2654 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2655 }; 2656 2657 static const struct panel_desc mitsubishi_aa070mc01 = { 2658 .modes = &mitsubishi_aa070mc01_mode, 2659 .num_modes = 1, 2660 .bpc = 8, 2661 .size = { 2662 .width = 152, 2663 .height = 91, 2664 }, 2665 2666 .delay = { 2667 .enable = 200, 2668 .unprepare = 200, 2669 .disable = 400, 2670 }, 2671 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2673 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2674 }; 2675 2676 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2677 .pixelclock = { 29000000, 33000000, 38000000 }, 2678 .hactive = { 800, 800, 800 }, 2679 .hfront_porch = { 180, 210, 240 }, 2680 .hback_porch = { 16, 16, 16 }, 2681 .hsync_len = { 30, 30, 30 }, 2682 .vactive = { 480, 480, 480 }, 2683 .vfront_porch = { 12, 22, 32 }, 2684 .vback_porch = { 10, 10, 10 }, 2685 .vsync_len = { 13, 13, 13 }, 2686 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2687 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2688 DISPLAY_FLAGS_SYNC_POSEDGE, 2689 }; 2690 2691 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2692 .timings = &multi_inno_mi0700s4t_6_timing, 2693 .num_timings = 1, 2694 .bpc = 8, 2695 .size = { 2696 .width = 154, 2697 .height = 86, 2698 }, 2699 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2700 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2701 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2702 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2703 .connector_type = DRM_MODE_CONNECTOR_DPI, 2704 }; 2705 2706 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2707 .pixelclock = { 68900000, 70000000, 73400000 }, 2708 .hactive = { 1280, 1280, 1280 }, 2709 .hfront_porch = { 30, 60, 71 }, 2710 .hback_porch = { 30, 60, 71 }, 2711 .hsync_len = { 10, 10, 48 }, 2712 .vactive = { 800, 800, 800 }, 2713 .vfront_porch = { 5, 10, 10 }, 2714 .vback_porch = { 5, 10, 10 }, 2715 .vsync_len = { 5, 6, 13 }, 2716 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2717 DISPLAY_FLAGS_DE_HIGH, 2718 }; 2719 2720 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2721 .timings = &multi_inno_mi1010ait_1cp_timing, 2722 .num_timings = 1, 2723 .bpc = 8, 2724 .size = { 2725 .width = 217, 2726 .height = 136, 2727 }, 2728 .delay = { 2729 .enable = 50, 2730 .disable = 50, 2731 }, 2732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2733 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2734 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2735 }; 2736 2737 static const struct display_timing nec_nl12880bc20_05_timing = { 2738 .pixelclock = { 67000000, 71000000, 75000000 }, 2739 .hactive = { 1280, 1280, 1280 }, 2740 .hfront_porch = { 2, 30, 30 }, 2741 .hback_porch = { 6, 100, 100 }, 2742 .hsync_len = { 2, 30, 30 }, 2743 .vactive = { 800, 800, 800 }, 2744 .vfront_porch = { 5, 5, 5 }, 2745 .vback_porch = { 11, 11, 11 }, 2746 .vsync_len = { 7, 7, 7 }, 2747 }; 2748 2749 static const struct panel_desc nec_nl12880bc20_05 = { 2750 .timings = &nec_nl12880bc20_05_timing, 2751 .num_timings = 1, 2752 .bpc = 8, 2753 .size = { 2754 .width = 261, 2755 .height = 163, 2756 }, 2757 .delay = { 2758 .enable = 50, 2759 .disable = 50, 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2762 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2763 }; 2764 2765 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2766 .clock = 10870, 2767 .hdisplay = 480, 2768 .hsync_start = 480 + 2, 2769 .hsync_end = 480 + 2 + 41, 2770 .htotal = 480 + 2 + 41 + 2, 2771 .vdisplay = 272, 2772 .vsync_start = 272 + 2, 2773 .vsync_end = 272 + 2 + 4, 2774 .vtotal = 272 + 2 + 4 + 2, 2775 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2776 }; 2777 2778 static const struct panel_desc nec_nl4827hc19_05b = { 2779 .modes = &nec_nl4827hc19_05b_mode, 2780 .num_modes = 1, 2781 .bpc = 8, 2782 .size = { 2783 .width = 95, 2784 .height = 54, 2785 }, 2786 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2787 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2788 }; 2789 2790 static const struct drm_display_mode netron_dy_e231732_mode = { 2791 .clock = 66000, 2792 .hdisplay = 1024, 2793 .hsync_start = 1024 + 160, 2794 .hsync_end = 1024 + 160 + 70, 2795 .htotal = 1024 + 160 + 70 + 90, 2796 .vdisplay = 600, 2797 .vsync_start = 600 + 127, 2798 .vsync_end = 600 + 127 + 20, 2799 .vtotal = 600 + 127 + 20 + 3, 2800 }; 2801 2802 static const struct panel_desc netron_dy_e231732 = { 2803 .modes = &netron_dy_e231732_mode, 2804 .num_modes = 1, 2805 .size = { 2806 .width = 154, 2807 .height = 87, 2808 }, 2809 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2810 }; 2811 2812 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2813 .clock = 9000, 2814 .hdisplay = 480, 2815 .hsync_start = 480 + 2, 2816 .hsync_end = 480 + 2 + 41, 2817 .htotal = 480 + 2 + 41 + 2, 2818 .vdisplay = 272, 2819 .vsync_start = 272 + 2, 2820 .vsync_end = 272 + 2 + 10, 2821 .vtotal = 272 + 2 + 10 + 2, 2822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2823 }; 2824 2825 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2826 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2827 .num_modes = 1, 2828 .bpc = 8, 2829 .size = { 2830 .width = 95, 2831 .height = 54, 2832 }, 2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2834 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2835 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2836 .connector_type = DRM_MODE_CONNECTOR_DPI, 2837 }; 2838 2839 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2840 .pixelclock = { 130000000, 148350000, 163000000 }, 2841 .hactive = { 1920, 1920, 1920 }, 2842 .hfront_porch = { 80, 100, 100 }, 2843 .hback_porch = { 100, 120, 120 }, 2844 .hsync_len = { 50, 60, 60 }, 2845 .vactive = { 1080, 1080, 1080 }, 2846 .vfront_porch = { 12, 30, 30 }, 2847 .vback_porch = { 4, 10, 10 }, 2848 .vsync_len = { 4, 5, 5 }, 2849 }; 2850 2851 static const struct panel_desc nlt_nl192108ac18_02d = { 2852 .timings = &nlt_nl192108ac18_02d_timing, 2853 .num_timings = 1, 2854 .bpc = 8, 2855 .size = { 2856 .width = 344, 2857 .height = 194, 2858 }, 2859 .delay = { 2860 .unprepare = 500, 2861 }, 2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2863 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2864 }; 2865 2866 static const struct drm_display_mode nvd_9128_mode = { 2867 .clock = 29500, 2868 .hdisplay = 800, 2869 .hsync_start = 800 + 130, 2870 .hsync_end = 800 + 130 + 98, 2871 .htotal = 800 + 0 + 130 + 98, 2872 .vdisplay = 480, 2873 .vsync_start = 480 + 10, 2874 .vsync_end = 480 + 10 + 50, 2875 .vtotal = 480 + 0 + 10 + 50, 2876 }; 2877 2878 static const struct panel_desc nvd_9128 = { 2879 .modes = &nvd_9128_mode, 2880 .num_modes = 1, 2881 .bpc = 8, 2882 .size = { 2883 .width = 156, 2884 .height = 88, 2885 }, 2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2887 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2888 }; 2889 2890 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2891 .pixelclock = { 30000000, 30000000, 40000000 }, 2892 .hactive = { 800, 800, 800 }, 2893 .hfront_porch = { 40, 40, 40 }, 2894 .hback_porch = { 40, 40, 40 }, 2895 .hsync_len = { 1, 48, 48 }, 2896 .vactive = { 480, 480, 480 }, 2897 .vfront_porch = { 13, 13, 13 }, 2898 .vback_porch = { 29, 29, 29 }, 2899 .vsync_len = { 3, 3, 3 }, 2900 .flags = DISPLAY_FLAGS_DE_HIGH, 2901 }; 2902 2903 static const struct panel_desc okaya_rs800480t_7x0gp = { 2904 .timings = &okaya_rs800480t_7x0gp_timing, 2905 .num_timings = 1, 2906 .bpc = 6, 2907 .size = { 2908 .width = 154, 2909 .height = 87, 2910 }, 2911 .delay = { 2912 .prepare = 41, 2913 .enable = 50, 2914 .unprepare = 41, 2915 .disable = 50, 2916 }, 2917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2918 }; 2919 2920 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2921 .clock = 9000, 2922 .hdisplay = 480, 2923 .hsync_start = 480 + 5, 2924 .hsync_end = 480 + 5 + 30, 2925 .htotal = 480 + 5 + 30 + 10, 2926 .vdisplay = 272, 2927 .vsync_start = 272 + 8, 2928 .vsync_end = 272 + 8 + 5, 2929 .vtotal = 272 + 8 + 5 + 3, 2930 }; 2931 2932 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2933 .modes = &olimex_lcd_olinuxino_43ts_mode, 2934 .num_modes = 1, 2935 .size = { 2936 .width = 95, 2937 .height = 54, 2938 }, 2939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2940 }; 2941 2942 /* 2943 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2944 * pixel clocks, but this is the timing that was being used in the Adafruit 2945 * installation instructions. 2946 */ 2947 static const struct drm_display_mode ontat_yx700wv03_mode = { 2948 .clock = 29500, 2949 .hdisplay = 800, 2950 .hsync_start = 824, 2951 .hsync_end = 896, 2952 .htotal = 992, 2953 .vdisplay = 480, 2954 .vsync_start = 483, 2955 .vsync_end = 493, 2956 .vtotal = 500, 2957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2958 }; 2959 2960 /* 2961 * Specification at: 2962 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2963 */ 2964 static const struct panel_desc ontat_yx700wv03 = { 2965 .modes = &ontat_yx700wv03_mode, 2966 .num_modes = 1, 2967 .bpc = 8, 2968 .size = { 2969 .width = 154, 2970 .height = 83, 2971 }, 2972 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2973 }; 2974 2975 static const struct drm_display_mode ortustech_com37h3m_mode = { 2976 .clock = 22230, 2977 .hdisplay = 480, 2978 .hsync_start = 480 + 40, 2979 .hsync_end = 480 + 40 + 10, 2980 .htotal = 480 + 40 + 10 + 40, 2981 .vdisplay = 640, 2982 .vsync_start = 640 + 4, 2983 .vsync_end = 640 + 4 + 2, 2984 .vtotal = 640 + 4 + 2 + 4, 2985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2986 }; 2987 2988 static const struct panel_desc ortustech_com37h3m = { 2989 .modes = &ortustech_com37h3m_mode, 2990 .num_modes = 1, 2991 .bpc = 8, 2992 .size = { 2993 .width = 56, /* 56.16mm */ 2994 .height = 75, /* 74.88mm */ 2995 }, 2996 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2998 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2999 }; 3000 3001 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3002 .clock = 25000, 3003 .hdisplay = 480, 3004 .hsync_start = 480 + 10, 3005 .hsync_end = 480 + 10 + 10, 3006 .htotal = 480 + 10 + 10 + 15, 3007 .vdisplay = 800, 3008 .vsync_start = 800 + 3, 3009 .vsync_end = 800 + 3 + 3, 3010 .vtotal = 800 + 3 + 3 + 3, 3011 }; 3012 3013 static const struct panel_desc ortustech_com43h4m85ulc = { 3014 .modes = &ortustech_com43h4m85ulc_mode, 3015 .num_modes = 1, 3016 .bpc = 6, 3017 .size = { 3018 .width = 56, 3019 .height = 93, 3020 }, 3021 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3023 .connector_type = DRM_MODE_CONNECTOR_DPI, 3024 }; 3025 3026 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3027 .clock = 33000, 3028 .hdisplay = 800, 3029 .hsync_start = 800 + 210, 3030 .hsync_end = 800 + 210 + 30, 3031 .htotal = 800 + 210 + 30 + 16, 3032 .vdisplay = 480, 3033 .vsync_start = 480 + 22, 3034 .vsync_end = 480 + 22 + 13, 3035 .vtotal = 480 + 22 + 13 + 10, 3036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3037 }; 3038 3039 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3040 .modes = &osddisplays_osd070t1718_19ts_mode, 3041 .num_modes = 1, 3042 .bpc = 8, 3043 .size = { 3044 .width = 152, 3045 .height = 91, 3046 }, 3047 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3048 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3049 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3050 .connector_type = DRM_MODE_CONNECTOR_DPI, 3051 }; 3052 3053 static const struct drm_display_mode pda_91_00156_a0_mode = { 3054 .clock = 33300, 3055 .hdisplay = 800, 3056 .hsync_start = 800 + 1, 3057 .hsync_end = 800 + 1 + 64, 3058 .htotal = 800 + 1 + 64 + 64, 3059 .vdisplay = 480, 3060 .vsync_start = 480 + 1, 3061 .vsync_end = 480 + 1 + 23, 3062 .vtotal = 480 + 1 + 23 + 22, 3063 }; 3064 3065 static const struct panel_desc pda_91_00156_a0 = { 3066 .modes = &pda_91_00156_a0_mode, 3067 .num_modes = 1, 3068 .size = { 3069 .width = 152, 3070 .height = 91, 3071 }, 3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3073 }; 3074 3075 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3076 .clock = 24750, 3077 .hdisplay = 800, 3078 .hsync_start = 800 + 54, 3079 .hsync_end = 800 + 54 + 2, 3080 .htotal = 800 + 54 + 2 + 44, 3081 .vdisplay = 480, 3082 .vsync_start = 480 + 49, 3083 .vsync_end = 480 + 49 + 2, 3084 .vtotal = 480 + 49 + 2 + 22, 3085 }; 3086 3087 static const struct panel_desc powertip_ph800480t013_idf02 = { 3088 .modes = &powertip_ph800480t013_idf02_mode, 3089 .num_modes = 1, 3090 .size = { 3091 .width = 152, 3092 .height = 91, 3093 }, 3094 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3095 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3096 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3098 .connector_type = DRM_MODE_CONNECTOR_DPI, 3099 }; 3100 3101 static const struct drm_display_mode qd43003c0_40_mode = { 3102 .clock = 9000, 3103 .hdisplay = 480, 3104 .hsync_start = 480 + 8, 3105 .hsync_end = 480 + 8 + 4, 3106 .htotal = 480 + 8 + 4 + 39, 3107 .vdisplay = 272, 3108 .vsync_start = 272 + 4, 3109 .vsync_end = 272 + 4 + 10, 3110 .vtotal = 272 + 4 + 10 + 2, 3111 }; 3112 3113 static const struct panel_desc qd43003c0_40 = { 3114 .modes = &qd43003c0_40_mode, 3115 .num_modes = 1, 3116 .bpc = 8, 3117 .size = { 3118 .width = 95, 3119 .height = 53, 3120 }, 3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3122 }; 3123 3124 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3125 { /* 60 Hz */ 3126 .clock = 10800, 3127 .hdisplay = 480, 3128 .hsync_start = 480 + 77, 3129 .hsync_end = 480 + 77 + 41, 3130 .htotal = 480 + 77 + 41 + 2, 3131 .vdisplay = 272, 3132 .vsync_start = 272 + 16, 3133 .vsync_end = 272 + 16 + 10, 3134 .vtotal = 272 + 16 + 10 + 2, 3135 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3136 }, 3137 { /* 50 Hz */ 3138 .clock = 10800, 3139 .hdisplay = 480, 3140 .hsync_start = 480 + 17, 3141 .hsync_end = 480 + 17 + 41, 3142 .htotal = 480 + 17 + 41 + 2, 3143 .vdisplay = 272, 3144 .vsync_start = 272 + 116, 3145 .vsync_end = 272 + 116 + 10, 3146 .vtotal = 272 + 116 + 10 + 2, 3147 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3148 }, 3149 }; 3150 3151 static const struct panel_desc qishenglong_gopher2b_lcd = { 3152 .modes = qishenglong_gopher2b_lcd_modes, 3153 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3154 .bpc = 8, 3155 .size = { 3156 .width = 95, 3157 .height = 54, 3158 }, 3159 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3160 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3161 .connector_type = DRM_MODE_CONNECTOR_DPI, 3162 }; 3163 3164 static const struct display_timing rocktech_rk070er9427_timing = { 3165 .pixelclock = { 26400000, 33300000, 46800000 }, 3166 .hactive = { 800, 800, 800 }, 3167 .hfront_porch = { 16, 210, 354 }, 3168 .hback_porch = { 46, 46, 46 }, 3169 .hsync_len = { 1, 1, 1 }, 3170 .vactive = { 480, 480, 480 }, 3171 .vfront_porch = { 7, 22, 147 }, 3172 .vback_porch = { 23, 23, 23 }, 3173 .vsync_len = { 1, 1, 1 }, 3174 .flags = DISPLAY_FLAGS_DE_HIGH, 3175 }; 3176 3177 static const struct panel_desc rocktech_rk070er9427 = { 3178 .timings = &rocktech_rk070er9427_timing, 3179 .num_timings = 1, 3180 .bpc = 6, 3181 .size = { 3182 .width = 154, 3183 .height = 86, 3184 }, 3185 .delay = { 3186 .prepare = 41, 3187 .enable = 50, 3188 .unprepare = 41, 3189 .disable = 50, 3190 }, 3191 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3192 }; 3193 3194 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3195 .clock = 71100, 3196 .hdisplay = 1280, 3197 .hsync_start = 1280 + 48, 3198 .hsync_end = 1280 + 48 + 32, 3199 .htotal = 1280 + 48 + 32 + 80, 3200 .vdisplay = 800, 3201 .vsync_start = 800 + 2, 3202 .vsync_end = 800 + 2 + 5, 3203 .vtotal = 800 + 2 + 5 + 16, 3204 }; 3205 3206 static const struct panel_desc rocktech_rk101ii01d_ct = { 3207 .modes = &rocktech_rk101ii01d_ct_mode, 3208 .bpc = 8, 3209 .num_modes = 1, 3210 .size = { 3211 .width = 217, 3212 .height = 136, 3213 }, 3214 .delay = { 3215 .prepare = 50, 3216 .disable = 50, 3217 }, 3218 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3221 }; 3222 3223 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3224 .clock = 54030, 3225 .hdisplay = 1024, 3226 .hsync_start = 1024 + 24, 3227 .hsync_end = 1024 + 24 + 136, 3228 .htotal = 1024 + 24 + 136 + 160, 3229 .vdisplay = 600, 3230 .vsync_start = 600 + 3, 3231 .vsync_end = 600 + 3 + 6, 3232 .vtotal = 600 + 3 + 6 + 61, 3233 }; 3234 3235 static const struct panel_desc samsung_ltn101nt05 = { 3236 .modes = &samsung_ltn101nt05_mode, 3237 .num_modes = 1, 3238 .bpc = 6, 3239 .size = { 3240 .width = 223, 3241 .height = 125, 3242 }, 3243 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3244 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3246 }; 3247 3248 static const struct display_timing satoz_sat050at40h12r2_timing = { 3249 .pixelclock = {33300000, 33300000, 50000000}, 3250 .hactive = {800, 800, 800}, 3251 .hfront_porch = {16, 210, 354}, 3252 .hback_porch = {46, 46, 46}, 3253 .hsync_len = {1, 1, 40}, 3254 .vactive = {480, 480, 480}, 3255 .vfront_porch = {7, 22, 147}, 3256 .vback_porch = {23, 23, 23}, 3257 .vsync_len = {1, 1, 20}, 3258 }; 3259 3260 static const struct panel_desc satoz_sat050at40h12r2 = { 3261 .timings = &satoz_sat050at40h12r2_timing, 3262 .num_timings = 1, 3263 .bpc = 8, 3264 .size = { 3265 .width = 108, 3266 .height = 65, 3267 }, 3268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3270 }; 3271 3272 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3273 .clock = 33260, 3274 .hdisplay = 800, 3275 .hsync_start = 800 + 64, 3276 .hsync_end = 800 + 64 + 128, 3277 .htotal = 800 + 64 + 128 + 64, 3278 .vdisplay = 480, 3279 .vsync_start = 480 + 8, 3280 .vsync_end = 480 + 8 + 2, 3281 .vtotal = 480 + 8 + 2 + 35, 3282 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3283 }; 3284 3285 static const struct panel_desc sharp_lq070y3dg3b = { 3286 .modes = &sharp_lq070y3dg3b_mode, 3287 .num_modes = 1, 3288 .bpc = 8, 3289 .size = { 3290 .width = 152, /* 152.4mm */ 3291 .height = 91, /* 91.4mm */ 3292 }, 3293 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3294 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3295 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3296 }; 3297 3298 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3299 .clock = 5500, 3300 .hdisplay = 240, 3301 .hsync_start = 240 + 16, 3302 .hsync_end = 240 + 16 + 7, 3303 .htotal = 240 + 16 + 7 + 5, 3304 .vdisplay = 320, 3305 .vsync_start = 320 + 9, 3306 .vsync_end = 320 + 9 + 1, 3307 .vtotal = 320 + 9 + 1 + 7, 3308 }; 3309 3310 static const struct panel_desc sharp_lq035q7db03 = { 3311 .modes = &sharp_lq035q7db03_mode, 3312 .num_modes = 1, 3313 .bpc = 6, 3314 .size = { 3315 .width = 54, 3316 .height = 72, 3317 }, 3318 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3319 }; 3320 3321 static const struct display_timing sharp_lq101k1ly04_timing = { 3322 .pixelclock = { 60000000, 65000000, 80000000 }, 3323 .hactive = { 1280, 1280, 1280 }, 3324 .hfront_porch = { 20, 20, 20 }, 3325 .hback_porch = { 20, 20, 20 }, 3326 .hsync_len = { 10, 10, 10 }, 3327 .vactive = { 800, 800, 800 }, 3328 .vfront_porch = { 4, 4, 4 }, 3329 .vback_porch = { 4, 4, 4 }, 3330 .vsync_len = { 4, 4, 4 }, 3331 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3332 }; 3333 3334 static const struct panel_desc sharp_lq101k1ly04 = { 3335 .timings = &sharp_lq101k1ly04_timing, 3336 .num_timings = 1, 3337 .bpc = 8, 3338 .size = { 3339 .width = 217, 3340 .height = 136, 3341 }, 3342 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3343 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3344 }; 3345 3346 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3347 { /* 50 Hz */ 3348 .clock = 3000, 3349 .hdisplay = 240, 3350 .hsync_start = 240 + 58, 3351 .hsync_end = 240 + 58 + 1, 3352 .htotal = 240 + 58 + 1 + 1, 3353 .vdisplay = 160, 3354 .vsync_start = 160 + 24, 3355 .vsync_end = 160 + 24 + 10, 3356 .vtotal = 160 + 24 + 10 + 6, 3357 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3358 }, 3359 { /* 60 Hz */ 3360 .clock = 3000, 3361 .hdisplay = 240, 3362 .hsync_start = 240 + 8, 3363 .hsync_end = 240 + 8 + 1, 3364 .htotal = 240 + 8 + 1 + 1, 3365 .vdisplay = 160, 3366 .vsync_start = 160 + 24, 3367 .vsync_end = 160 + 24 + 10, 3368 .vtotal = 160 + 24 + 10 + 6, 3369 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3370 }, 3371 }; 3372 3373 static const struct panel_desc sharp_ls020b1dd01d = { 3374 .modes = sharp_ls020b1dd01d_modes, 3375 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3376 .bpc = 6, 3377 .size = { 3378 .width = 42, 3379 .height = 28, 3380 }, 3381 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3382 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3383 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3384 | DRM_BUS_FLAG_SHARP_SIGNALS, 3385 }; 3386 3387 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3388 .clock = 33300, 3389 .hdisplay = 800, 3390 .hsync_start = 800 + 1, 3391 .hsync_end = 800 + 1 + 64, 3392 .htotal = 800 + 1 + 64 + 64, 3393 .vdisplay = 480, 3394 .vsync_start = 480 + 1, 3395 .vsync_end = 480 + 1 + 23, 3396 .vtotal = 480 + 1 + 23 + 22, 3397 }; 3398 3399 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3400 .modes = &shelly_sca07010_bfn_lnn_mode, 3401 .num_modes = 1, 3402 .size = { 3403 .width = 152, 3404 .height = 91, 3405 }, 3406 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3407 }; 3408 3409 static const struct drm_display_mode starry_kr070pe2t_mode = { 3410 .clock = 33000, 3411 .hdisplay = 800, 3412 .hsync_start = 800 + 209, 3413 .hsync_end = 800 + 209 + 1, 3414 .htotal = 800 + 209 + 1 + 45, 3415 .vdisplay = 480, 3416 .vsync_start = 480 + 22, 3417 .vsync_end = 480 + 22 + 1, 3418 .vtotal = 480 + 22 + 1 + 22, 3419 }; 3420 3421 static const struct panel_desc starry_kr070pe2t = { 3422 .modes = &starry_kr070pe2t_mode, 3423 .num_modes = 1, 3424 .bpc = 8, 3425 .size = { 3426 .width = 152, 3427 .height = 86, 3428 }, 3429 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3430 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3431 .connector_type = DRM_MODE_CONNECTOR_DPI, 3432 }; 3433 3434 static const struct display_timing startek_kd070wvfpa_mode = { 3435 .pixelclock = { 25200000, 27200000, 30500000 }, 3436 .hactive = { 800, 800, 800 }, 3437 .hfront_porch = { 19, 44, 115 }, 3438 .hback_porch = { 5, 16, 101 }, 3439 .hsync_len = { 1, 2, 100 }, 3440 .vactive = { 480, 480, 480 }, 3441 .vfront_porch = { 5, 43, 67 }, 3442 .vback_porch = { 5, 5, 67 }, 3443 .vsync_len = { 1, 2, 66 }, 3444 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3445 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3446 DISPLAY_FLAGS_SYNC_POSEDGE, 3447 }; 3448 3449 static const struct panel_desc startek_kd070wvfpa = { 3450 .timings = &startek_kd070wvfpa_mode, 3451 .num_timings = 1, 3452 .bpc = 8, 3453 .size = { 3454 .width = 152, 3455 .height = 91, 3456 }, 3457 .delay = { 3458 .prepare = 20, 3459 .enable = 200, 3460 .disable = 200, 3461 }, 3462 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3463 .connector_type = DRM_MODE_CONNECTOR_DPI, 3464 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3465 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3466 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3467 }; 3468 3469 static const struct display_timing tsd_tst043015cmhx_timing = { 3470 .pixelclock = { 5000000, 9000000, 12000000 }, 3471 .hactive = { 480, 480, 480 }, 3472 .hfront_porch = { 4, 5, 65 }, 3473 .hback_porch = { 36, 40, 255 }, 3474 .hsync_len = { 1, 1, 1 }, 3475 .vactive = { 272, 272, 272 }, 3476 .vfront_porch = { 2, 8, 97 }, 3477 .vback_porch = { 3, 8, 31 }, 3478 .vsync_len = { 1, 1, 1 }, 3479 3480 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3481 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3482 }; 3483 3484 static const struct panel_desc tsd_tst043015cmhx = { 3485 .timings = &tsd_tst043015cmhx_timing, 3486 .num_timings = 1, 3487 .bpc = 8, 3488 .size = { 3489 .width = 105, 3490 .height = 67, 3491 }, 3492 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3493 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3494 }; 3495 3496 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3497 .clock = 30000, 3498 .hdisplay = 800, 3499 .hsync_start = 800 + 39, 3500 .hsync_end = 800 + 39 + 47, 3501 .htotal = 800 + 39 + 47 + 39, 3502 .vdisplay = 480, 3503 .vsync_start = 480 + 13, 3504 .vsync_end = 480 + 13 + 2, 3505 .vtotal = 480 + 13 + 2 + 29, 3506 }; 3507 3508 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3509 .modes = &tfc_s9700rtwv43tr_01b_mode, 3510 .num_modes = 1, 3511 .bpc = 8, 3512 .size = { 3513 .width = 155, 3514 .height = 90, 3515 }, 3516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3518 }; 3519 3520 static const struct display_timing tianma_tm070jdhg30_timing = { 3521 .pixelclock = { 62600000, 68200000, 78100000 }, 3522 .hactive = { 1280, 1280, 1280 }, 3523 .hfront_porch = { 15, 64, 159 }, 3524 .hback_porch = { 5, 5, 5 }, 3525 .hsync_len = { 1, 1, 256 }, 3526 .vactive = { 800, 800, 800 }, 3527 .vfront_porch = { 3, 40, 99 }, 3528 .vback_porch = { 2, 2, 2 }, 3529 .vsync_len = { 1, 1, 128 }, 3530 .flags = DISPLAY_FLAGS_DE_HIGH, 3531 }; 3532 3533 static const struct panel_desc tianma_tm070jdhg30 = { 3534 .timings = &tianma_tm070jdhg30_timing, 3535 .num_timings = 1, 3536 .bpc = 8, 3537 .size = { 3538 .width = 151, 3539 .height = 95, 3540 }, 3541 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3542 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3543 }; 3544 3545 static const struct panel_desc tianma_tm070jvhg33 = { 3546 .timings = &tianma_tm070jdhg30_timing, 3547 .num_timings = 1, 3548 .bpc = 8, 3549 .size = { 3550 .width = 150, 3551 .height = 94, 3552 }, 3553 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3554 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3555 }; 3556 3557 static const struct display_timing tianma_tm070rvhg71_timing = { 3558 .pixelclock = { 27700000, 29200000, 39600000 }, 3559 .hactive = { 800, 800, 800 }, 3560 .hfront_porch = { 12, 40, 212 }, 3561 .hback_porch = { 88, 88, 88 }, 3562 .hsync_len = { 1, 1, 40 }, 3563 .vactive = { 480, 480, 480 }, 3564 .vfront_porch = { 1, 13, 88 }, 3565 .vback_porch = { 32, 32, 32 }, 3566 .vsync_len = { 1, 1, 3 }, 3567 .flags = DISPLAY_FLAGS_DE_HIGH, 3568 }; 3569 3570 static const struct panel_desc tianma_tm070rvhg71 = { 3571 .timings = &tianma_tm070rvhg71_timing, 3572 .num_timings = 1, 3573 .bpc = 8, 3574 .size = { 3575 .width = 154, 3576 .height = 86, 3577 }, 3578 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3579 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3580 }; 3581 3582 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3583 { 3584 .clock = 10000, 3585 .hdisplay = 320, 3586 .hsync_start = 320 + 50, 3587 .hsync_end = 320 + 50 + 6, 3588 .htotal = 320 + 50 + 6 + 38, 3589 .vdisplay = 240, 3590 .vsync_start = 240 + 3, 3591 .vsync_end = 240 + 3 + 1, 3592 .vtotal = 240 + 3 + 1 + 17, 3593 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3594 }, 3595 }; 3596 3597 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3598 .modes = ti_nspire_cx_lcd_mode, 3599 .num_modes = 1, 3600 .bpc = 8, 3601 .size = { 3602 .width = 65, 3603 .height = 49, 3604 }, 3605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3606 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3607 }; 3608 3609 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3610 { 3611 .clock = 10000, 3612 .hdisplay = 320, 3613 .hsync_start = 320 + 6, 3614 .hsync_end = 320 + 6 + 6, 3615 .htotal = 320 + 6 + 6 + 6, 3616 .vdisplay = 240, 3617 .vsync_start = 240 + 0, 3618 .vsync_end = 240 + 0 + 1, 3619 .vtotal = 240 + 0 + 1 + 0, 3620 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3621 }, 3622 }; 3623 3624 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3625 .modes = ti_nspire_classic_lcd_mode, 3626 .num_modes = 1, 3627 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3628 .bpc = 8, 3629 .size = { 3630 .width = 71, 3631 .height = 53, 3632 }, 3633 /* This is the grayscale bus format */ 3634 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3635 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3636 }; 3637 3638 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3639 .clock = 79500, 3640 .hdisplay = 1280, 3641 .hsync_start = 1280 + 192, 3642 .hsync_end = 1280 + 192 + 128, 3643 .htotal = 1280 + 192 + 128 + 64, 3644 .vdisplay = 768, 3645 .vsync_start = 768 + 20, 3646 .vsync_end = 768 + 20 + 7, 3647 .vtotal = 768 + 20 + 7 + 3, 3648 }; 3649 3650 static const struct panel_desc toshiba_lt089ac29000 = { 3651 .modes = &toshiba_lt089ac29000_mode, 3652 .num_modes = 1, 3653 .size = { 3654 .width = 194, 3655 .height = 116, 3656 }, 3657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3658 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3659 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3660 }; 3661 3662 static const struct drm_display_mode tpk_f07a_0102_mode = { 3663 .clock = 33260, 3664 .hdisplay = 800, 3665 .hsync_start = 800 + 40, 3666 .hsync_end = 800 + 40 + 128, 3667 .htotal = 800 + 40 + 128 + 88, 3668 .vdisplay = 480, 3669 .vsync_start = 480 + 10, 3670 .vsync_end = 480 + 10 + 2, 3671 .vtotal = 480 + 10 + 2 + 33, 3672 }; 3673 3674 static const struct panel_desc tpk_f07a_0102 = { 3675 .modes = &tpk_f07a_0102_mode, 3676 .num_modes = 1, 3677 .size = { 3678 .width = 152, 3679 .height = 91, 3680 }, 3681 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3682 }; 3683 3684 static const struct drm_display_mode tpk_f10a_0102_mode = { 3685 .clock = 45000, 3686 .hdisplay = 1024, 3687 .hsync_start = 1024 + 176, 3688 .hsync_end = 1024 + 176 + 5, 3689 .htotal = 1024 + 176 + 5 + 88, 3690 .vdisplay = 600, 3691 .vsync_start = 600 + 20, 3692 .vsync_end = 600 + 20 + 5, 3693 .vtotal = 600 + 20 + 5 + 25, 3694 }; 3695 3696 static const struct panel_desc tpk_f10a_0102 = { 3697 .modes = &tpk_f10a_0102_mode, 3698 .num_modes = 1, 3699 .size = { 3700 .width = 223, 3701 .height = 125, 3702 }, 3703 }; 3704 3705 static const struct display_timing urt_umsh_8596md_timing = { 3706 .pixelclock = { 33260000, 33260000, 33260000 }, 3707 .hactive = { 800, 800, 800 }, 3708 .hfront_porch = { 41, 41, 41 }, 3709 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3710 .hsync_len = { 71, 128, 128 }, 3711 .vactive = { 480, 480, 480 }, 3712 .vfront_porch = { 10, 10, 10 }, 3713 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3714 .vsync_len = { 2, 2, 2 }, 3715 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3716 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3717 }; 3718 3719 static const struct panel_desc urt_umsh_8596md_lvds = { 3720 .timings = &urt_umsh_8596md_timing, 3721 .num_timings = 1, 3722 .bpc = 6, 3723 .size = { 3724 .width = 152, 3725 .height = 91, 3726 }, 3727 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3728 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3729 }; 3730 3731 static const struct panel_desc urt_umsh_8596md_parallel = { 3732 .timings = &urt_umsh_8596md_timing, 3733 .num_timings = 1, 3734 .bpc = 6, 3735 .size = { 3736 .width = 152, 3737 .height = 91, 3738 }, 3739 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3740 }; 3741 3742 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3743 .clock = 60000, 3744 .hdisplay = 1024, 3745 .hsync_start = 1024 + 160, 3746 .hsync_end = 1024 + 160 + 100, 3747 .htotal = 1024 + 160 + 100 + 60, 3748 .vdisplay = 600, 3749 .vsync_start = 600 + 12, 3750 .vsync_end = 600 + 12 + 10, 3751 .vtotal = 600 + 12 + 10 + 13, 3752 }; 3753 3754 static const struct panel_desc vivax_tpc9150_panel = { 3755 .modes = &vivax_tpc9150_panel_mode, 3756 .num_modes = 1, 3757 .bpc = 6, 3758 .size = { 3759 .width = 200, 3760 .height = 115, 3761 }, 3762 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3763 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3764 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3765 }; 3766 3767 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3768 .clock = 33333, 3769 .hdisplay = 800, 3770 .hsync_start = 800 + 210, 3771 .hsync_end = 800 + 210 + 20, 3772 .htotal = 800 + 210 + 20 + 46, 3773 .vdisplay = 480, 3774 .vsync_start = 480 + 22, 3775 .vsync_end = 480 + 22 + 10, 3776 .vtotal = 480 + 22 + 10 + 23, 3777 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3778 }; 3779 3780 static const struct panel_desc vl050_8048nt_c01 = { 3781 .modes = &vl050_8048nt_c01_mode, 3782 .num_modes = 1, 3783 .bpc = 8, 3784 .size = { 3785 .width = 120, 3786 .height = 76, 3787 }, 3788 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3789 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3790 }; 3791 3792 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3793 .clock = 6410, 3794 .hdisplay = 320, 3795 .hsync_start = 320 + 20, 3796 .hsync_end = 320 + 20 + 30, 3797 .htotal = 320 + 20 + 30 + 38, 3798 .vdisplay = 240, 3799 .vsync_start = 240 + 4, 3800 .vsync_end = 240 + 4 + 3, 3801 .vtotal = 240 + 4 + 3 + 15, 3802 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3803 }; 3804 3805 static const struct panel_desc winstar_wf35ltiacd = { 3806 .modes = &winstar_wf35ltiacd_mode, 3807 .num_modes = 1, 3808 .bpc = 8, 3809 .size = { 3810 .width = 70, 3811 .height = 53, 3812 }, 3813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3814 }; 3815 3816 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3817 .clock = 51200, 3818 .hdisplay = 1024, 3819 .hsync_start = 1024 + 100, 3820 .hsync_end = 1024 + 100 + 100, 3821 .htotal = 1024 + 100 + 100 + 120, 3822 .vdisplay = 600, 3823 .vsync_start = 600 + 10, 3824 .vsync_end = 600 + 10 + 10, 3825 .vtotal = 600 + 10 + 10 + 15, 3826 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3827 }; 3828 3829 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3830 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3831 .num_modes = 1, 3832 .bpc = 8, 3833 .size = { 3834 .width = 154, 3835 .height = 90, 3836 }, 3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3838 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3839 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3840 }; 3841 3842 static const struct drm_display_mode arm_rtsm_mode[] = { 3843 { 3844 .clock = 65000, 3845 .hdisplay = 1024, 3846 .hsync_start = 1024 + 24, 3847 .hsync_end = 1024 + 24 + 136, 3848 .htotal = 1024 + 24 + 136 + 160, 3849 .vdisplay = 768, 3850 .vsync_start = 768 + 3, 3851 .vsync_end = 768 + 3 + 6, 3852 .vtotal = 768 + 3 + 6 + 29, 3853 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3854 }, 3855 }; 3856 3857 static const struct panel_desc arm_rtsm = { 3858 .modes = arm_rtsm_mode, 3859 .num_modes = 1, 3860 .bpc = 8, 3861 .size = { 3862 .width = 400, 3863 .height = 300, 3864 }, 3865 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3866 }; 3867 3868 static const struct of_device_id platform_of_match[] = { 3869 { 3870 .compatible = "ampire,am-1280800n3tzqw-t00h", 3871 .data = &ire_am_1280800n3tzqw_t00h, 3872 }, { 3873 .compatible = "ampire,am-480272h3tmqw-t01h", 3874 .data = &ire_am_480272h3tmqw_t01h, 3875 }, { 3876 .compatible = "ampire,am800480r3tmqwa1h", 3877 .data = &ire_am800480r3tmqwa1h, 3878 }, { 3879 .compatible = "ampire,am800600p5tmqw-tb8h", 3880 .data = &ire_am800600p5tmqwtb8h, 3881 }, { 3882 .compatible = "arm,rtsm-display", 3883 .data = &arm_rtsm, 3884 }, { 3885 .compatible = "armadeus,st0700-adapt", 3886 .data = &armadeus_st0700_adapt, 3887 }, { 3888 .compatible = "auo,b101aw03", 3889 .data = &auo_b101aw03, 3890 }, { 3891 .compatible = "auo,b101xtn01", 3892 .data = &auo_b101xtn01, 3893 }, { 3894 .compatible = "auo,g070vvn01", 3895 .data = &auo_g070vvn01, 3896 }, { 3897 .compatible = "auo,g101evn010", 3898 .data = &auo_g101evn010, 3899 }, { 3900 .compatible = "auo,g104sn02", 3901 .data = &auo_g104sn02, 3902 }, { 3903 .compatible = "auo,g121ean01", 3904 .data = &auo_g121ean01, 3905 }, { 3906 .compatible = "auo,g133han01", 3907 .data = &auo_g133han01, 3908 }, { 3909 .compatible = "auo,g156xtn01", 3910 .data = &auo_g156xtn01, 3911 }, { 3912 .compatible = "auo,g185han01", 3913 .data = &auo_g185han01, 3914 }, { 3915 .compatible = "auo,g190ean01", 3916 .data = &auo_g190ean01, 3917 }, { 3918 .compatible = "auo,p320hvn03", 3919 .data = &auo_p320hvn03, 3920 }, { 3921 .compatible = "auo,t215hvn01", 3922 .data = &auo_t215hvn01, 3923 }, { 3924 .compatible = "avic,tm070ddh03", 3925 .data = &avic_tm070ddh03, 3926 }, { 3927 .compatible = "bananapi,s070wv20-ct16", 3928 .data = &bananapi_s070wv20_ct16, 3929 }, { 3930 .compatible = "boe,hv070wsa-100", 3931 .data = &boe_hv070wsa 3932 }, { 3933 .compatible = "cdtech,s043wq26h-ct7", 3934 .data = &cdtech_s043wq26h_ct7, 3935 }, { 3936 .compatible = "cdtech,s070pws19hp-fc21", 3937 .data = &cdtech_s070pws19hp_fc21, 3938 }, { 3939 .compatible = "cdtech,s070swv29hg-dc44", 3940 .data = &cdtech_s070swv29hg_dc44, 3941 }, { 3942 .compatible = "cdtech,s070wv95-ct16", 3943 .data = &cdtech_s070wv95_ct16, 3944 }, { 3945 .compatible = "chefree,ch101olhlwh-002", 3946 .data = &chefree_ch101olhlwh_002, 3947 }, { 3948 .compatible = "chunghwa,claa070wp03xg", 3949 .data = &chunghwa_claa070wp03xg, 3950 }, { 3951 .compatible = "chunghwa,claa101wa01a", 3952 .data = &chunghwa_claa101wa01a 3953 }, { 3954 .compatible = "chunghwa,claa101wb01", 3955 .data = &chunghwa_claa101wb01 3956 }, { 3957 .compatible = "dataimage,fg040346dsswbg04", 3958 .data = &dataimage_fg040346dsswbg04, 3959 }, { 3960 .compatible = "dataimage,fg1001l0dsswmg01", 3961 .data = &dataimage_fg1001l0dsswmg01, 3962 }, { 3963 .compatible = "dataimage,scf0700c48ggu18", 3964 .data = &dataimage_scf0700c48ggu18, 3965 }, { 3966 .compatible = "dlc,dlc0700yzg-1", 3967 .data = &dlc_dlc0700yzg_1, 3968 }, { 3969 .compatible = "dlc,dlc1010gig", 3970 .data = &dlc_dlc1010gig, 3971 }, { 3972 .compatible = "edt,et035012dm6", 3973 .data = &edt_et035012dm6, 3974 }, { 3975 .compatible = "edt,etm0350g0dh6", 3976 .data = &edt_etm0350g0dh6, 3977 }, { 3978 .compatible = "edt,etm043080dh6gp", 3979 .data = &edt_etm043080dh6gp, 3980 }, { 3981 .compatible = "edt,etm0430g0dh6", 3982 .data = &edt_etm0430g0dh6, 3983 }, { 3984 .compatible = "edt,et057090dhu", 3985 .data = &edt_et057090dhu, 3986 }, { 3987 .compatible = "edt,et070080dh6", 3988 .data = &edt_etm0700g0dh6, 3989 }, { 3990 .compatible = "edt,etm0700g0dh6", 3991 .data = &edt_etm0700g0dh6, 3992 }, { 3993 .compatible = "edt,etm0700g0bdh6", 3994 .data = &edt_etm0700g0bdh6, 3995 }, { 3996 .compatible = "edt,etm0700g0edh6", 3997 .data = &edt_etm0700g0bdh6, 3998 }, { 3999 .compatible = "edt,etml0700y5dha", 4000 .data = &edt_etml0700y5dha, 4001 }, { 4002 .compatible = "edt,etmv570g2dhu", 4003 .data = &edt_etmv570g2dhu, 4004 }, { 4005 .compatible = "eink,vb3300-kca", 4006 .data = &eink_vb3300_kca, 4007 }, { 4008 .compatible = "evervision,vgg804821", 4009 .data = &evervision_vgg804821, 4010 }, { 4011 .compatible = "foxlink,fl500wvr00-a0t", 4012 .data = &foxlink_fl500wvr00_a0t, 4013 }, { 4014 .compatible = "frida,frd350h54004", 4015 .data = &frida_frd350h54004, 4016 }, { 4017 .compatible = "friendlyarm,hd702e", 4018 .data = &friendlyarm_hd702e, 4019 }, { 4020 .compatible = "giantplus,gpg482739qs5", 4021 .data = &giantplus_gpg482739qs5 4022 }, { 4023 .compatible = "giantplus,gpm940b0", 4024 .data = &giantplus_gpm940b0, 4025 }, { 4026 .compatible = "hannstar,hsd070pww1", 4027 .data = &hannstar_hsd070pww1, 4028 }, { 4029 .compatible = "hannstar,hsd100pxn1", 4030 .data = &hannstar_hsd100pxn1, 4031 }, { 4032 .compatible = "hannstar,hsd101pww2", 4033 .data = &hannstar_hsd101pww2, 4034 }, { 4035 .compatible = "hit,tx23d38vm0caa", 4036 .data = &hitachi_tx23d38vm0caa 4037 }, { 4038 .compatible = "innolux,at043tn24", 4039 .data = &innolux_at043tn24, 4040 }, { 4041 .compatible = "innolux,at070tn92", 4042 .data = &innolux_at070tn92, 4043 }, { 4044 .compatible = "innolux,g070y2-l01", 4045 .data = &innolux_g070y2_l01, 4046 }, { 4047 .compatible = "innolux,g070y2-t02", 4048 .data = &innolux_g070y2_t02, 4049 }, { 4050 .compatible = "innolux,g101ice-l01", 4051 .data = &innolux_g101ice_l01 4052 }, { 4053 .compatible = "innolux,g121i1-l01", 4054 .data = &innolux_g121i1_l01 4055 }, { 4056 .compatible = "innolux,g121x1-l03", 4057 .data = &innolux_g121x1_l03, 4058 }, { 4059 .compatible = "innolux,n156bge-l21", 4060 .data = &innolux_n156bge_l21, 4061 }, { 4062 .compatible = "innolux,zj070na-01p", 4063 .data = &innolux_zj070na_01p, 4064 }, { 4065 .compatible = "koe,tx14d24vm1bpa", 4066 .data = &koe_tx14d24vm1bpa, 4067 }, { 4068 .compatible = "koe,tx26d202vm0bwa", 4069 .data = &koe_tx26d202vm0bwa, 4070 }, { 4071 .compatible = "koe,tx31d200vm0baa", 4072 .data = &koe_tx31d200vm0baa, 4073 }, { 4074 .compatible = "kyo,tcg121xglp", 4075 .data = &kyo_tcg121xglp, 4076 }, { 4077 .compatible = "lemaker,bl035-rgb-002", 4078 .data = &lemaker_bl035_rgb_002, 4079 }, { 4080 .compatible = "lg,lb070wv8", 4081 .data = &lg_lb070wv8, 4082 }, { 4083 .compatible = "logicpd,type28", 4084 .data = &logicpd_type_28, 4085 }, { 4086 .compatible = "logictechno,lt161010-2nhc", 4087 .data = &logictechno_lt161010_2nh, 4088 }, { 4089 .compatible = "logictechno,lt161010-2nhr", 4090 .data = &logictechno_lt161010_2nh, 4091 }, { 4092 .compatible = "logictechno,lt170410-2whc", 4093 .data = &logictechno_lt170410_2whc, 4094 }, { 4095 .compatible = "logictechno,lttd800480070-l2rt", 4096 .data = &logictechno_lttd800480070_l2rt, 4097 }, { 4098 .compatible = "logictechno,lttd800480070-l6wh-rt", 4099 .data = &logictechno_lttd800480070_l6wh_rt, 4100 }, { 4101 .compatible = "mitsubishi,aa070mc01-ca1", 4102 .data = &mitsubishi_aa070mc01, 4103 }, { 4104 .compatible = "multi-inno,mi0700s4t-6", 4105 .data = &multi_inno_mi0700s4t_6, 4106 }, { 4107 .compatible = "multi-inno,mi1010ait-1cp", 4108 .data = &multi_inno_mi1010ait_1cp, 4109 }, { 4110 .compatible = "nec,nl12880bc20-05", 4111 .data = &nec_nl12880bc20_05, 4112 }, { 4113 .compatible = "nec,nl4827hc19-05b", 4114 .data = &nec_nl4827hc19_05b, 4115 }, { 4116 .compatible = "netron-dy,e231732", 4117 .data = &netron_dy_e231732, 4118 }, { 4119 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4120 .data = &newhaven_nhd_43_480272ef_atxl, 4121 }, { 4122 .compatible = "nlt,nl192108ac18-02d", 4123 .data = &nlt_nl192108ac18_02d, 4124 }, { 4125 .compatible = "nvd,9128", 4126 .data = &nvd_9128, 4127 }, { 4128 .compatible = "okaya,rs800480t-7x0gp", 4129 .data = &okaya_rs800480t_7x0gp, 4130 }, { 4131 .compatible = "olimex,lcd-olinuxino-43-ts", 4132 .data = &olimex_lcd_olinuxino_43ts, 4133 }, { 4134 .compatible = "ontat,yx700wv03", 4135 .data = &ontat_yx700wv03, 4136 }, { 4137 .compatible = "ortustech,com37h3m05dtc", 4138 .data = &ortustech_com37h3m, 4139 }, { 4140 .compatible = "ortustech,com37h3m99dtc", 4141 .data = &ortustech_com37h3m, 4142 }, { 4143 .compatible = "ortustech,com43h4m85ulc", 4144 .data = &ortustech_com43h4m85ulc, 4145 }, { 4146 .compatible = "osddisplays,osd070t1718-19ts", 4147 .data = &osddisplays_osd070t1718_19ts, 4148 }, { 4149 .compatible = "pda,91-00156-a0", 4150 .data = &pda_91_00156_a0, 4151 }, { 4152 .compatible = "powertip,ph800480t013-idf02", 4153 .data = &powertip_ph800480t013_idf02, 4154 }, { 4155 .compatible = "qiaodian,qd43003c0-40", 4156 .data = &qd43003c0_40, 4157 }, { 4158 .compatible = "qishenglong,gopher2b-lcd", 4159 .data = &qishenglong_gopher2b_lcd, 4160 }, { 4161 .compatible = "rocktech,rk070er9427", 4162 .data = &rocktech_rk070er9427, 4163 }, { 4164 .compatible = "rocktech,rk101ii01d-ct", 4165 .data = &rocktech_rk101ii01d_ct, 4166 }, { 4167 .compatible = "samsung,ltn101nt05", 4168 .data = &samsung_ltn101nt05, 4169 }, { 4170 .compatible = "satoz,sat050at40h12r2", 4171 .data = &satoz_sat050at40h12r2, 4172 }, { 4173 .compatible = "sharp,lq035q7db03", 4174 .data = &sharp_lq035q7db03, 4175 }, { 4176 .compatible = "sharp,lq070y3dg3b", 4177 .data = &sharp_lq070y3dg3b, 4178 }, { 4179 .compatible = "sharp,lq101k1ly04", 4180 .data = &sharp_lq101k1ly04, 4181 }, { 4182 .compatible = "sharp,ls020b1dd01d", 4183 .data = &sharp_ls020b1dd01d, 4184 }, { 4185 .compatible = "shelly,sca07010-bfn-lnn", 4186 .data = &shelly_sca07010_bfn_lnn, 4187 }, { 4188 .compatible = "starry,kr070pe2t", 4189 .data = &starry_kr070pe2t, 4190 }, { 4191 .compatible = "startek,kd070wvfpa", 4192 .data = &startek_kd070wvfpa, 4193 }, { 4194 .compatible = "team-source-display,tst043015cmhx", 4195 .data = &tsd_tst043015cmhx, 4196 }, { 4197 .compatible = "tfc,s9700rtwv43tr-01b", 4198 .data = &tfc_s9700rtwv43tr_01b, 4199 }, { 4200 .compatible = "tianma,tm070jdhg30", 4201 .data = &tianma_tm070jdhg30, 4202 }, { 4203 .compatible = "tianma,tm070jvhg33", 4204 .data = &tianma_tm070jvhg33, 4205 }, { 4206 .compatible = "tianma,tm070rvhg71", 4207 .data = &tianma_tm070rvhg71, 4208 }, { 4209 .compatible = "ti,nspire-cx-lcd-panel", 4210 .data = &ti_nspire_cx_lcd_panel, 4211 }, { 4212 .compatible = "ti,nspire-classic-lcd-panel", 4213 .data = &ti_nspire_classic_lcd_panel, 4214 }, { 4215 .compatible = "toshiba,lt089ac29000", 4216 .data = &toshiba_lt089ac29000, 4217 }, { 4218 .compatible = "tpk,f07a-0102", 4219 .data = &tpk_f07a_0102, 4220 }, { 4221 .compatible = "tpk,f10a-0102", 4222 .data = &tpk_f10a_0102, 4223 }, { 4224 .compatible = "urt,umsh-8596md-t", 4225 .data = &urt_umsh_8596md_parallel, 4226 }, { 4227 .compatible = "urt,umsh-8596md-1t", 4228 .data = &urt_umsh_8596md_parallel, 4229 }, { 4230 .compatible = "urt,umsh-8596md-7t", 4231 .data = &urt_umsh_8596md_parallel, 4232 }, { 4233 .compatible = "urt,umsh-8596md-11t", 4234 .data = &urt_umsh_8596md_lvds, 4235 }, { 4236 .compatible = "urt,umsh-8596md-19t", 4237 .data = &urt_umsh_8596md_lvds, 4238 }, { 4239 .compatible = "urt,umsh-8596md-20t", 4240 .data = &urt_umsh_8596md_parallel, 4241 }, { 4242 .compatible = "vivax,tpc9150-panel", 4243 .data = &vivax_tpc9150_panel, 4244 }, { 4245 .compatible = "vxt,vl050-8048nt-c01", 4246 .data = &vl050_8048nt_c01, 4247 }, { 4248 .compatible = "winstar,wf35ltiacd", 4249 .data = &winstar_wf35ltiacd, 4250 }, { 4251 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4252 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4253 }, { 4254 /* Must be the last entry */ 4255 .compatible = "panel-dpi", 4256 .data = &panel_dpi, 4257 }, { 4258 /* sentinel */ 4259 } 4260 }; 4261 MODULE_DEVICE_TABLE(of, platform_of_match); 4262 4263 static int panel_simple_platform_probe(struct platform_device *pdev) 4264 { 4265 const struct of_device_id *id; 4266 4267 id = of_match_node(platform_of_match, pdev->dev.of_node); 4268 if (!id) 4269 return -ENODEV; 4270 4271 return panel_simple_probe(&pdev->dev, id->data); 4272 } 4273 4274 static int panel_simple_platform_remove(struct platform_device *pdev) 4275 { 4276 return panel_simple_remove(&pdev->dev); 4277 } 4278 4279 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4280 { 4281 panel_simple_shutdown(&pdev->dev); 4282 } 4283 4284 static const struct dev_pm_ops panel_simple_pm_ops = { 4285 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4286 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4287 pm_runtime_force_resume) 4288 }; 4289 4290 static struct platform_driver panel_simple_platform_driver = { 4291 .driver = { 4292 .name = "panel-simple", 4293 .of_match_table = platform_of_match, 4294 .pm = &panel_simple_pm_ops, 4295 }, 4296 .probe = panel_simple_platform_probe, 4297 .remove = panel_simple_platform_remove, 4298 .shutdown = panel_simple_platform_shutdown, 4299 }; 4300 4301 struct panel_desc_dsi { 4302 struct panel_desc desc; 4303 4304 unsigned long flags; 4305 enum mipi_dsi_pixel_format format; 4306 unsigned int lanes; 4307 }; 4308 4309 static const struct drm_display_mode auo_b080uan01_mode = { 4310 .clock = 154500, 4311 .hdisplay = 1200, 4312 .hsync_start = 1200 + 62, 4313 .hsync_end = 1200 + 62 + 4, 4314 .htotal = 1200 + 62 + 4 + 62, 4315 .vdisplay = 1920, 4316 .vsync_start = 1920 + 9, 4317 .vsync_end = 1920 + 9 + 2, 4318 .vtotal = 1920 + 9 + 2 + 8, 4319 }; 4320 4321 static const struct panel_desc_dsi auo_b080uan01 = { 4322 .desc = { 4323 .modes = &auo_b080uan01_mode, 4324 .num_modes = 1, 4325 .bpc = 8, 4326 .size = { 4327 .width = 108, 4328 .height = 272, 4329 }, 4330 .connector_type = DRM_MODE_CONNECTOR_DSI, 4331 }, 4332 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4333 .format = MIPI_DSI_FMT_RGB888, 4334 .lanes = 4, 4335 }; 4336 4337 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4338 .clock = 160000, 4339 .hdisplay = 1200, 4340 .hsync_start = 1200 + 120, 4341 .hsync_end = 1200 + 120 + 20, 4342 .htotal = 1200 + 120 + 20 + 21, 4343 .vdisplay = 1920, 4344 .vsync_start = 1920 + 21, 4345 .vsync_end = 1920 + 21 + 3, 4346 .vtotal = 1920 + 21 + 3 + 18, 4347 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4348 }; 4349 4350 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4351 .desc = { 4352 .modes = &boe_tv080wum_nl0_mode, 4353 .num_modes = 1, 4354 .size = { 4355 .width = 107, 4356 .height = 172, 4357 }, 4358 .connector_type = DRM_MODE_CONNECTOR_DSI, 4359 }, 4360 .flags = MIPI_DSI_MODE_VIDEO | 4361 MIPI_DSI_MODE_VIDEO_BURST | 4362 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4363 .format = MIPI_DSI_FMT_RGB888, 4364 .lanes = 4, 4365 }; 4366 4367 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4368 .clock = 71000, 4369 .hdisplay = 800, 4370 .hsync_start = 800 + 32, 4371 .hsync_end = 800 + 32 + 1, 4372 .htotal = 800 + 32 + 1 + 57, 4373 .vdisplay = 1280, 4374 .vsync_start = 1280 + 28, 4375 .vsync_end = 1280 + 28 + 1, 4376 .vtotal = 1280 + 28 + 1 + 14, 4377 }; 4378 4379 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4380 .desc = { 4381 .modes = &lg_ld070wx3_sl01_mode, 4382 .num_modes = 1, 4383 .bpc = 8, 4384 .size = { 4385 .width = 94, 4386 .height = 151, 4387 }, 4388 .connector_type = DRM_MODE_CONNECTOR_DSI, 4389 }, 4390 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4391 .format = MIPI_DSI_FMT_RGB888, 4392 .lanes = 4, 4393 }; 4394 4395 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4396 .clock = 67000, 4397 .hdisplay = 720, 4398 .hsync_start = 720 + 12, 4399 .hsync_end = 720 + 12 + 4, 4400 .htotal = 720 + 12 + 4 + 112, 4401 .vdisplay = 1280, 4402 .vsync_start = 1280 + 8, 4403 .vsync_end = 1280 + 8 + 4, 4404 .vtotal = 1280 + 8 + 4 + 12, 4405 }; 4406 4407 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4408 .desc = { 4409 .modes = &lg_lh500wx1_sd03_mode, 4410 .num_modes = 1, 4411 .bpc = 8, 4412 .size = { 4413 .width = 62, 4414 .height = 110, 4415 }, 4416 .connector_type = DRM_MODE_CONNECTOR_DSI, 4417 }, 4418 .flags = MIPI_DSI_MODE_VIDEO, 4419 .format = MIPI_DSI_FMT_RGB888, 4420 .lanes = 4, 4421 }; 4422 4423 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4424 .clock = 157200, 4425 .hdisplay = 1920, 4426 .hsync_start = 1920 + 154, 4427 .hsync_end = 1920 + 154 + 16, 4428 .htotal = 1920 + 154 + 16 + 32, 4429 .vdisplay = 1200, 4430 .vsync_start = 1200 + 17, 4431 .vsync_end = 1200 + 17 + 2, 4432 .vtotal = 1200 + 17 + 2 + 16, 4433 }; 4434 4435 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4436 .desc = { 4437 .modes = &panasonic_vvx10f004b00_mode, 4438 .num_modes = 1, 4439 .bpc = 8, 4440 .size = { 4441 .width = 217, 4442 .height = 136, 4443 }, 4444 .connector_type = DRM_MODE_CONNECTOR_DSI, 4445 }, 4446 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4447 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4448 .format = MIPI_DSI_FMT_RGB888, 4449 .lanes = 4, 4450 }; 4451 4452 static const struct drm_display_mode lg_acx467akm_7_mode = { 4453 .clock = 150000, 4454 .hdisplay = 1080, 4455 .hsync_start = 1080 + 2, 4456 .hsync_end = 1080 + 2 + 2, 4457 .htotal = 1080 + 2 + 2 + 2, 4458 .vdisplay = 1920, 4459 .vsync_start = 1920 + 2, 4460 .vsync_end = 1920 + 2 + 2, 4461 .vtotal = 1920 + 2 + 2 + 2, 4462 }; 4463 4464 static const struct panel_desc_dsi lg_acx467akm_7 = { 4465 .desc = { 4466 .modes = &lg_acx467akm_7_mode, 4467 .num_modes = 1, 4468 .bpc = 8, 4469 .size = { 4470 .width = 62, 4471 .height = 110, 4472 }, 4473 .connector_type = DRM_MODE_CONNECTOR_DSI, 4474 }, 4475 .flags = 0, 4476 .format = MIPI_DSI_FMT_RGB888, 4477 .lanes = 4, 4478 }; 4479 4480 static const struct drm_display_mode osd101t2045_53ts_mode = { 4481 .clock = 154500, 4482 .hdisplay = 1920, 4483 .hsync_start = 1920 + 112, 4484 .hsync_end = 1920 + 112 + 16, 4485 .htotal = 1920 + 112 + 16 + 32, 4486 .vdisplay = 1200, 4487 .vsync_start = 1200 + 16, 4488 .vsync_end = 1200 + 16 + 2, 4489 .vtotal = 1200 + 16 + 2 + 16, 4490 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4491 }; 4492 4493 static const struct panel_desc_dsi osd101t2045_53ts = { 4494 .desc = { 4495 .modes = &osd101t2045_53ts_mode, 4496 .num_modes = 1, 4497 .bpc = 8, 4498 .size = { 4499 .width = 217, 4500 .height = 136, 4501 }, 4502 .connector_type = DRM_MODE_CONNECTOR_DSI, 4503 }, 4504 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4505 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4506 MIPI_DSI_MODE_NO_EOT_PACKET, 4507 .format = MIPI_DSI_FMT_RGB888, 4508 .lanes = 4, 4509 }; 4510 4511 static const struct of_device_id dsi_of_match[] = { 4512 { 4513 .compatible = "auo,b080uan01", 4514 .data = &auo_b080uan01 4515 }, { 4516 .compatible = "boe,tv080wum-nl0", 4517 .data = &boe_tv080wum_nl0 4518 }, { 4519 .compatible = "lg,ld070wx3-sl01", 4520 .data = &lg_ld070wx3_sl01 4521 }, { 4522 .compatible = "lg,lh500wx1-sd03", 4523 .data = &lg_lh500wx1_sd03 4524 }, { 4525 .compatible = "panasonic,vvx10f004b00", 4526 .data = &panasonic_vvx10f004b00 4527 }, { 4528 .compatible = "lg,acx467akm-7", 4529 .data = &lg_acx467akm_7 4530 }, { 4531 .compatible = "osddisplays,osd101t2045-53ts", 4532 .data = &osd101t2045_53ts 4533 }, { 4534 /* sentinel */ 4535 } 4536 }; 4537 MODULE_DEVICE_TABLE(of, dsi_of_match); 4538 4539 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4540 { 4541 const struct panel_desc_dsi *desc; 4542 const struct of_device_id *id; 4543 int err; 4544 4545 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4546 if (!id) 4547 return -ENODEV; 4548 4549 desc = id->data; 4550 4551 err = panel_simple_probe(&dsi->dev, &desc->desc); 4552 if (err < 0) 4553 return err; 4554 4555 dsi->mode_flags = desc->flags; 4556 dsi->format = desc->format; 4557 dsi->lanes = desc->lanes; 4558 4559 err = mipi_dsi_attach(dsi); 4560 if (err) { 4561 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4562 4563 drm_panel_remove(&panel->base); 4564 } 4565 4566 return err; 4567 } 4568 4569 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4570 { 4571 int err; 4572 4573 err = mipi_dsi_detach(dsi); 4574 if (err < 0) 4575 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4576 4577 return panel_simple_remove(&dsi->dev); 4578 } 4579 4580 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4581 { 4582 panel_simple_shutdown(&dsi->dev); 4583 } 4584 4585 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4586 .driver = { 4587 .name = "panel-simple-dsi", 4588 .of_match_table = dsi_of_match, 4589 .pm = &panel_simple_pm_ops, 4590 }, 4591 .probe = panel_simple_dsi_probe, 4592 .remove = panel_simple_dsi_remove, 4593 .shutdown = panel_simple_dsi_shutdown, 4594 }; 4595 4596 static int __init panel_simple_init(void) 4597 { 4598 int err; 4599 4600 err = platform_driver_register(&panel_simple_platform_driver); 4601 if (err < 0) 4602 return err; 4603 4604 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4605 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4606 if (err < 0) 4607 goto err_did_platform_register; 4608 } 4609 4610 return 0; 4611 4612 err_did_platform_register: 4613 platform_driver_unregister(&panel_simple_platform_driver); 4614 4615 return err; 4616 } 4617 module_init(panel_simple_init); 4618 4619 static void __exit panel_simple_exit(void) 4620 { 4621 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4622 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4623 4624 platform_driver_unregister(&panel_simple_platform_driver); 4625 } 4626 module_exit(panel_simple_exit); 4627 4628 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4629 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4630 MODULE_LICENSE("GPL and additional rights"); 4631