1 /*
2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the
12  * next paragraph) shall be included in all copies or substantial portions
13  * of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
33 
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37 
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43 
44 /**
45  * struct panel_desc - Describes a simple panel.
46  */
47 struct panel_desc {
48 	/**
49 	 * @modes: Pointer to array of fixed modes appropriate for this panel.
50 	 *
51 	 * If only one mode then this can just be the address of the mode.
52 	 * NOTE: cannot be used with "timings" and also if this is specified
53 	 * then you cannot override the mode in the device tree.
54 	 */
55 	const struct drm_display_mode *modes;
56 
57 	/** @num_modes: Number of elements in modes array. */
58 	unsigned int num_modes;
59 
60 	/**
61 	 * @timings: Pointer to array of display timings
62 	 *
63 	 * NOTE: cannot be used with "modes" and also these will be used to
64 	 * validate a device tree override if one is present.
65 	 */
66 	const struct display_timing *timings;
67 
68 	/** @num_timings: Number of elements in timings array. */
69 	unsigned int num_timings;
70 
71 	/** @bpc: Bits per color. */
72 	unsigned int bpc;
73 
74 	/** @size: Structure containing the physical size of this panel. */
75 	struct {
76 		/**
77 		 * @size.width: Width (in mm) of the active display area.
78 		 */
79 		unsigned int width;
80 
81 		/**
82 		 * @size.height: Height (in mm) of the active display area.
83 		 */
84 		unsigned int height;
85 	} size;
86 
87 	/** @delay: Structure containing various delay values for this panel. */
88 	struct {
89 		/**
90 		 * @delay.prepare: Time for the panel to become ready.
91 		 *
92 		 * The time (in milliseconds) that it takes for the panel to
93 		 * become ready and start receiving video data
94 		 */
95 		unsigned int prepare;
96 
97 		/**
98 		 * @delay.enable: Time for the panel to display a valid frame.
99 		 *
100 		 * The time (in milliseconds) that it takes for the panel to
101 		 * display the first valid frame after starting to receive
102 		 * video data.
103 		 */
104 		unsigned int enable;
105 
106 		/**
107 		 * @delay.disable: Time for the panel to turn the display off.
108 		 *
109 		 * The time (in milliseconds) that it takes for the panel to
110 		 * turn the display off (no content is visible).
111 		 */
112 		unsigned int disable;
113 
114 		/**
115 		 * @delay.unprepare: Time to power down completely.
116 		 *
117 		 * The time (in milliseconds) that it takes for the panel
118 		 * to power itself down completely.
119 		 *
120 		 * This time is used to prevent a future "prepare" from
121 		 * starting until at least this many milliseconds has passed.
122 		 * If at prepare time less time has passed since unprepare
123 		 * finished, the driver waits for the remaining time.
124 		 */
125 		unsigned int unprepare;
126 	} delay;
127 
128 	/** @bus_format: See MEDIA_BUS_FMT_... defines. */
129 	u32 bus_format;
130 
131 	/** @bus_flags: See DRM_BUS_FLAG_... defines. */
132 	u32 bus_flags;
133 
134 	/** @connector_type: LVDS, eDP, DSI, DPI, etc. */
135 	int connector_type;
136 };
137 
138 struct panel_simple {
139 	struct drm_panel base;
140 	bool enabled;
141 
142 	bool prepared;
143 
144 	ktime_t prepared_time;
145 	ktime_t unprepared_time;
146 
147 	const struct panel_desc *desc;
148 
149 	struct regulator *supply;
150 	struct i2c_adapter *ddc;
151 
152 	struct gpio_desc *enable_gpio;
153 
154 	struct edid *edid;
155 
156 	struct drm_display_mode override_mode;
157 
158 	enum drm_panel_orientation orientation;
159 };
160 
161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
162 {
163 	return container_of(panel, struct panel_simple, base);
164 }
165 
166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 						   struct drm_connector *connector)
168 {
169 	struct drm_display_mode *mode;
170 	unsigned int i, num = 0;
171 
172 	for (i = 0; i < panel->desc->num_timings; i++) {
173 		const struct display_timing *dt = &panel->desc->timings[i];
174 		struct videomode vm;
175 
176 		videomode_from_timing(dt, &vm);
177 		mode = drm_mode_create(connector->dev);
178 		if (!mode) {
179 			dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 				dt->hactive.typ, dt->vactive.typ);
181 			continue;
182 		}
183 
184 		drm_display_mode_from_videomode(&vm, mode);
185 
186 		mode->type |= DRM_MODE_TYPE_DRIVER;
187 
188 		if (panel->desc->num_timings == 1)
189 			mode->type |= DRM_MODE_TYPE_PREFERRED;
190 
191 		drm_mode_probed_add(connector, mode);
192 		num++;
193 	}
194 
195 	return num;
196 }
197 
198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 						   struct drm_connector *connector)
200 {
201 	struct drm_display_mode *mode;
202 	unsigned int i, num = 0;
203 
204 	for (i = 0; i < panel->desc->num_modes; i++) {
205 		const struct drm_display_mode *m = &panel->desc->modes[i];
206 
207 		mode = drm_mode_duplicate(connector->dev, m);
208 		if (!mode) {
209 			dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 				m->hdisplay, m->vdisplay,
211 				drm_mode_vrefresh(m));
212 			continue;
213 		}
214 
215 		mode->type |= DRM_MODE_TYPE_DRIVER;
216 
217 		if (panel->desc->num_modes == 1)
218 			mode->type |= DRM_MODE_TYPE_PREFERRED;
219 
220 		drm_mode_set_name(mode);
221 
222 		drm_mode_probed_add(connector, mode);
223 		num++;
224 	}
225 
226 	return num;
227 }
228 
229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 					   struct drm_connector *connector)
231 {
232 	struct drm_display_mode *mode;
233 	bool has_override = panel->override_mode.type;
234 	unsigned int num = 0;
235 
236 	if (!panel->desc)
237 		return 0;
238 
239 	if (has_override) {
240 		mode = drm_mode_duplicate(connector->dev,
241 					  &panel->override_mode);
242 		if (mode) {
243 			drm_mode_probed_add(connector, mode);
244 			num = 1;
245 		} else {
246 			dev_err(panel->base.dev, "failed to add override mode\n");
247 		}
248 	}
249 
250 	/* Only add timings if override was not there or failed to validate */
251 	if (num == 0 && panel->desc->num_timings)
252 		num = panel_simple_get_timings_modes(panel, connector);
253 
254 	/*
255 	 * Only add fixed modes if timings/override added no mode.
256 	 *
257 	 * We should only ever have either the display timings specified
258 	 * or a fixed mode. Anything else is rather bogus.
259 	 */
260 	WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
261 	if (num == 0)
262 		num = panel_simple_get_display_modes(panel, connector);
263 
264 	connector->display_info.bpc = panel->desc->bpc;
265 	connector->display_info.width_mm = panel->desc->size.width;
266 	connector->display_info.height_mm = panel->desc->size.height;
267 	if (panel->desc->bus_format)
268 		drm_display_info_set_bus_formats(&connector->display_info,
269 						 &panel->desc->bus_format, 1);
270 	connector->display_info.bus_flags = panel->desc->bus_flags;
271 
272 	return num;
273 }
274 
275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
276 {
277 	ktime_t now_ktime, min_ktime;
278 
279 	if (!min_ms)
280 		return;
281 
282 	min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 	now_ktime = ktime_get_boottime();
284 
285 	if (ktime_before(now_ktime, min_ktime))
286 		msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
287 }
288 
289 static int panel_simple_disable(struct drm_panel *panel)
290 {
291 	struct panel_simple *p = to_panel_simple(panel);
292 
293 	if (!p->enabled)
294 		return 0;
295 
296 	if (p->desc->delay.disable)
297 		msleep(p->desc->delay.disable);
298 
299 	p->enabled = false;
300 
301 	return 0;
302 }
303 
304 static int panel_simple_suspend(struct device *dev)
305 {
306 	struct panel_simple *p = dev_get_drvdata(dev);
307 
308 	gpiod_set_value_cansleep(p->enable_gpio, 0);
309 	regulator_disable(p->supply);
310 	p->unprepared_time = ktime_get_boottime();
311 
312 	kfree(p->edid);
313 	p->edid = NULL;
314 
315 	return 0;
316 }
317 
318 static int panel_simple_unprepare(struct drm_panel *panel)
319 {
320 	struct panel_simple *p = to_panel_simple(panel);
321 	int ret;
322 
323 	/* Unpreparing when already unprepared is a no-op */
324 	if (!p->prepared)
325 		return 0;
326 
327 	pm_runtime_mark_last_busy(panel->dev);
328 	ret = pm_runtime_put_autosuspend(panel->dev);
329 	if (ret < 0)
330 		return ret;
331 	p->prepared = false;
332 
333 	return 0;
334 }
335 
336 static int panel_simple_resume(struct device *dev)
337 {
338 	struct panel_simple *p = dev_get_drvdata(dev);
339 	int err;
340 
341 	panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
342 
343 	err = regulator_enable(p->supply);
344 	if (err < 0) {
345 		dev_err(dev, "failed to enable supply: %d\n", err);
346 		return err;
347 	}
348 
349 	gpiod_set_value_cansleep(p->enable_gpio, 1);
350 
351 	if (p->desc->delay.prepare)
352 		msleep(p->desc->delay.prepare);
353 
354 	p->prepared_time = ktime_get_boottime();
355 
356 	return 0;
357 }
358 
359 static int panel_simple_prepare(struct drm_panel *panel)
360 {
361 	struct panel_simple *p = to_panel_simple(panel);
362 	int ret;
363 
364 	/* Preparing when already prepared is a no-op */
365 	if (p->prepared)
366 		return 0;
367 
368 	ret = pm_runtime_get_sync(panel->dev);
369 	if (ret < 0) {
370 		pm_runtime_put_autosuspend(panel->dev);
371 		return ret;
372 	}
373 
374 	p->prepared = true;
375 
376 	return 0;
377 }
378 
379 static int panel_simple_enable(struct drm_panel *panel)
380 {
381 	struct panel_simple *p = to_panel_simple(panel);
382 
383 	if (p->enabled)
384 		return 0;
385 
386 	if (p->desc->delay.enable)
387 		msleep(p->desc->delay.enable);
388 
389 	p->enabled = true;
390 
391 	return 0;
392 }
393 
394 static int panel_simple_get_modes(struct drm_panel *panel,
395 				  struct drm_connector *connector)
396 {
397 	struct panel_simple *p = to_panel_simple(panel);
398 	int num = 0;
399 
400 	/* probe EDID if a DDC bus is available */
401 	if (p->ddc) {
402 		pm_runtime_get_sync(panel->dev);
403 
404 		if (!p->edid)
405 			p->edid = drm_get_edid(connector, p->ddc);
406 
407 		if (p->edid)
408 			num += drm_add_edid_modes(connector, p->edid);
409 
410 		pm_runtime_mark_last_busy(panel->dev);
411 		pm_runtime_put_autosuspend(panel->dev);
412 	}
413 
414 	/* add hard-coded panel modes */
415 	num += panel_simple_get_non_edid_modes(p, connector);
416 
417 	/*
418 	 * TODO: Remove once all drm drivers call
419 	 * drm_connector_set_orientation_from_panel()
420 	 */
421 	drm_connector_set_panel_orientation(connector, p->orientation);
422 
423 	return num;
424 }
425 
426 static int panel_simple_get_timings(struct drm_panel *panel,
427 				    unsigned int num_timings,
428 				    struct display_timing *timings)
429 {
430 	struct panel_simple *p = to_panel_simple(panel);
431 	unsigned int i;
432 
433 	if (p->desc->num_timings < num_timings)
434 		num_timings = p->desc->num_timings;
435 
436 	if (timings)
437 		for (i = 0; i < num_timings; i++)
438 			timings[i] = p->desc->timings[i];
439 
440 	return p->desc->num_timings;
441 }
442 
443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
444 {
445 	struct panel_simple *p = to_panel_simple(panel);
446 
447 	return p->orientation;
448 }
449 
450 static const struct drm_panel_funcs panel_simple_funcs = {
451 	.disable = panel_simple_disable,
452 	.unprepare = panel_simple_unprepare,
453 	.prepare = panel_simple_prepare,
454 	.enable = panel_simple_enable,
455 	.get_modes = panel_simple_get_modes,
456 	.get_orientation = panel_simple_get_orientation,
457 	.get_timings = panel_simple_get_timings,
458 };
459 
460 static struct panel_desc panel_dpi;
461 
462 static int panel_dpi_probe(struct device *dev,
463 			   struct panel_simple *panel)
464 {
465 	struct display_timing *timing;
466 	const struct device_node *np;
467 	struct panel_desc *desc;
468 	unsigned int bus_flags;
469 	struct videomode vm;
470 	int ret;
471 
472 	np = dev->of_node;
473 	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
474 	if (!desc)
475 		return -ENOMEM;
476 
477 	timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
478 	if (!timing)
479 		return -ENOMEM;
480 
481 	ret = of_get_display_timing(np, "panel-timing", timing);
482 	if (ret < 0) {
483 		dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
484 			np);
485 		return ret;
486 	}
487 
488 	desc->timings = timing;
489 	desc->num_timings = 1;
490 
491 	of_property_read_u32(np, "width-mm", &desc->size.width);
492 	of_property_read_u32(np, "height-mm", &desc->size.height);
493 
494 	/* Extract bus_flags from display_timing */
495 	bus_flags = 0;
496 	vm.flags = timing->flags;
497 	drm_bus_flags_from_videomode(&vm, &bus_flags);
498 	desc->bus_flags = bus_flags;
499 
500 	/* We do not know the connector for the DT node, so guess it */
501 	desc->connector_type = DRM_MODE_CONNECTOR_DPI;
502 
503 	panel->desc = desc;
504 
505 	return 0;
506 }
507 
508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
509 	(to_check->field.typ >= bounds->field.min && \
510 	 to_check->field.typ <= bounds->field.max)
511 static void panel_simple_parse_panel_timing_node(struct device *dev,
512 						 struct panel_simple *panel,
513 						 const struct display_timing *ot)
514 {
515 	const struct panel_desc *desc = panel->desc;
516 	struct videomode vm;
517 	unsigned int i;
518 
519 	if (WARN_ON(desc->num_modes)) {
520 		dev_err(dev, "Reject override mode: panel has a fixed mode\n");
521 		return;
522 	}
523 	if (WARN_ON(!desc->num_timings)) {
524 		dev_err(dev, "Reject override mode: no timings specified\n");
525 		return;
526 	}
527 
528 	for (i = 0; i < panel->desc->num_timings; i++) {
529 		const struct display_timing *dt = &panel->desc->timings[i];
530 
531 		if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
532 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
533 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
534 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
535 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
536 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
537 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
538 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
539 			continue;
540 
541 		if (ot->flags != dt->flags)
542 			continue;
543 
544 		videomode_from_timing(ot, &vm);
545 		drm_display_mode_from_videomode(&vm, &panel->override_mode);
546 		panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
547 					     DRM_MODE_TYPE_PREFERRED;
548 		break;
549 	}
550 
551 	if (WARN_ON(!panel->override_mode.type))
552 		dev_err(dev, "Reject override mode: No display_timing found\n");
553 }
554 
555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
556 {
557 	struct panel_simple *panel;
558 	struct display_timing dt;
559 	struct device_node *ddc;
560 	int connector_type;
561 	u32 bus_flags;
562 	int err;
563 
564 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
565 	if (!panel)
566 		return -ENOMEM;
567 
568 	panel->enabled = false;
569 	panel->prepared_time = 0;
570 	panel->desc = desc;
571 
572 	panel->supply = devm_regulator_get(dev, "power");
573 	if (IS_ERR(panel->supply))
574 		return PTR_ERR(panel->supply);
575 
576 	panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
577 						     GPIOD_OUT_LOW);
578 	if (IS_ERR(panel->enable_gpio))
579 		return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
580 				     "failed to request GPIO\n");
581 
582 	err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
583 	if (err) {
584 		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
585 		return err;
586 	}
587 
588 	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
589 	if (ddc) {
590 		panel->ddc = of_find_i2c_adapter_by_node(ddc);
591 		of_node_put(ddc);
592 
593 		if (!panel->ddc)
594 			return -EPROBE_DEFER;
595 	}
596 
597 	if (desc == &panel_dpi) {
598 		/* Handle the generic panel-dpi binding */
599 		err = panel_dpi_probe(dev, panel);
600 		if (err)
601 			goto free_ddc;
602 		desc = panel->desc;
603 	} else {
604 		if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
605 			panel_simple_parse_panel_timing_node(dev, panel, &dt);
606 	}
607 
608 	connector_type = desc->connector_type;
609 	/* Catch common mistakes for panels. */
610 	switch (connector_type) {
611 	case 0:
612 		dev_warn(dev, "Specify missing connector_type\n");
613 		connector_type = DRM_MODE_CONNECTOR_DPI;
614 		break;
615 	case DRM_MODE_CONNECTOR_LVDS:
616 		WARN_ON(desc->bus_flags &
617 			~(DRM_BUS_FLAG_DE_LOW |
618 			  DRM_BUS_FLAG_DE_HIGH |
619 			  DRM_BUS_FLAG_DATA_MSB_TO_LSB |
620 			  DRM_BUS_FLAG_DATA_LSB_TO_MSB));
621 		WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
622 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
623 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
624 		WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
625 			desc->bpc != 6);
626 		WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
627 			 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
628 			desc->bpc != 8);
629 		break;
630 	case DRM_MODE_CONNECTOR_eDP:
631 		dev_warn(dev, "eDP panels moved to panel-edp\n");
632 		err = -EINVAL;
633 		goto free_ddc;
634 	case DRM_MODE_CONNECTOR_DSI:
635 		if (desc->bpc != 6 && desc->bpc != 8)
636 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
637 		break;
638 	case DRM_MODE_CONNECTOR_DPI:
639 		bus_flags = DRM_BUS_FLAG_DE_LOW |
640 			    DRM_BUS_FLAG_DE_HIGH |
641 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
642 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
643 			    DRM_BUS_FLAG_DATA_MSB_TO_LSB |
644 			    DRM_BUS_FLAG_DATA_LSB_TO_MSB |
645 			    DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
646 			    DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
647 		if (desc->bus_flags & ~bus_flags)
648 			dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
649 		if (!(desc->bus_flags & bus_flags))
650 			dev_warn(dev, "Specify missing bus_flags\n");
651 		if (desc->bus_format == 0)
652 			dev_warn(dev, "Specify missing bus_format\n");
653 		if (desc->bpc != 6 && desc->bpc != 8)
654 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
655 		break;
656 	default:
657 		dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
658 		connector_type = DRM_MODE_CONNECTOR_DPI;
659 		break;
660 	}
661 
662 	dev_set_drvdata(dev, panel);
663 
664 	/*
665 	 * We use runtime PM for prepare / unprepare since those power the panel
666 	 * on and off and those can be very slow operations. This is important
667 	 * to optimize powering the panel on briefly to read the EDID before
668 	 * fully enabling the panel.
669 	 */
670 	pm_runtime_enable(dev);
671 	pm_runtime_set_autosuspend_delay(dev, 1000);
672 	pm_runtime_use_autosuspend(dev);
673 
674 	drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
675 
676 	err = drm_panel_of_backlight(&panel->base);
677 	if (err) {
678 		dev_err_probe(dev, err, "Could not find backlight\n");
679 		goto disable_pm_runtime;
680 	}
681 
682 	drm_panel_add(&panel->base);
683 
684 	return 0;
685 
686 disable_pm_runtime:
687 	pm_runtime_dont_use_autosuspend(dev);
688 	pm_runtime_disable(dev);
689 free_ddc:
690 	if (panel->ddc)
691 		put_device(&panel->ddc->dev);
692 
693 	return err;
694 }
695 
696 static void panel_simple_remove(struct device *dev)
697 {
698 	struct panel_simple *panel = dev_get_drvdata(dev);
699 
700 	drm_panel_remove(&panel->base);
701 	drm_panel_disable(&panel->base);
702 	drm_panel_unprepare(&panel->base);
703 
704 	pm_runtime_dont_use_autosuspend(dev);
705 	pm_runtime_disable(dev);
706 	if (panel->ddc)
707 		put_device(&panel->ddc->dev);
708 }
709 
710 static void panel_simple_shutdown(struct device *dev)
711 {
712 	struct panel_simple *panel = dev_get_drvdata(dev);
713 
714 	drm_panel_disable(&panel->base);
715 	drm_panel_unprepare(&panel->base);
716 }
717 
718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
719 	.clock = 71100,
720 	.hdisplay = 1280,
721 	.hsync_start = 1280 + 40,
722 	.hsync_end = 1280 + 40 + 80,
723 	.htotal = 1280 + 40 + 80 + 40,
724 	.vdisplay = 800,
725 	.vsync_start = 800 + 3,
726 	.vsync_end = 800 + 3 + 10,
727 	.vtotal = 800 + 3 + 10 + 10,
728 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
729 };
730 
731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
732 	.modes = &ampire_am_1280800n3tzqw_t00h_mode,
733 	.num_modes = 1,
734 	.bpc = 8,
735 	.size = {
736 		.width = 217,
737 		.height = 136,
738 	},
739 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
740 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
741 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
742 };
743 
744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
745 	.clock = 9000,
746 	.hdisplay = 480,
747 	.hsync_start = 480 + 2,
748 	.hsync_end = 480 + 2 + 41,
749 	.htotal = 480 + 2 + 41 + 2,
750 	.vdisplay = 272,
751 	.vsync_start = 272 + 2,
752 	.vsync_end = 272 + 2 + 10,
753 	.vtotal = 272 + 2 + 10 + 2,
754 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
755 };
756 
757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
758 	.modes = &ampire_am_480272h3tmqw_t01h_mode,
759 	.num_modes = 1,
760 	.bpc = 8,
761 	.size = {
762 		.width = 99,
763 		.height = 58,
764 	},
765 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
766 };
767 
768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
769 	.clock = 33333,
770 	.hdisplay = 800,
771 	.hsync_start = 800 + 0,
772 	.hsync_end = 800 + 0 + 255,
773 	.htotal = 800 + 0 + 255 + 0,
774 	.vdisplay = 480,
775 	.vsync_start = 480 + 2,
776 	.vsync_end = 480 + 2 + 45,
777 	.vtotal = 480 + 2 + 45 + 0,
778 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
779 };
780 
781 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
782 	.pixelclock = { 29930000, 33260000, 36590000 },
783 	.hactive = { 800, 800, 800 },
784 	.hfront_porch = { 1, 40, 168 },
785 	.hback_porch = { 88, 88, 88 },
786 	.hsync_len = { 1, 128, 128 },
787 	.vactive = { 480, 480, 480 },
788 	.vfront_porch = { 1, 35, 37 },
789 	.vback_porch = { 8, 8, 8 },
790 	.vsync_len = { 1, 2, 2 },
791 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
793 		 DISPLAY_FLAGS_SYNC_POSEDGE,
794 };
795 
796 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
797 	.timings = &ampire_am_800480l1tmqw_t00h_timing,
798 	.num_timings = 1,
799 	.bpc = 8,
800 	.size = {
801 		.width = 111,
802 		.height = 67,
803 	},
804 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
805 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
806 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
807 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
808 	.connector_type = DRM_MODE_CONNECTOR_DPI,
809 };
810 
811 static const struct panel_desc ampire_am800480r3tmqwa1h = {
812 	.modes = &ampire_am800480r3tmqwa1h_mode,
813 	.num_modes = 1,
814 	.bpc = 6,
815 	.size = {
816 		.width = 152,
817 		.height = 91,
818 	},
819 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
820 };
821 
822 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
823 	.pixelclock = { 34500000, 39600000, 50400000 },
824 	.hactive = { 800, 800, 800 },
825 	.hfront_porch = { 12, 112, 312 },
826 	.hback_porch = { 87, 87, 48 },
827 	.hsync_len = { 1, 1, 40 },
828 	.vactive = { 600, 600, 600 },
829 	.vfront_porch = { 1, 21, 61 },
830 	.vback_porch = { 38, 38, 19 },
831 	.vsync_len = { 1, 1, 20 },
832 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
833 		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
834 		DISPLAY_FLAGS_SYNC_POSEDGE,
835 };
836 
837 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
838 	.timings = &ampire_am800600p5tmqw_tb8h_timing,
839 	.num_timings = 1,
840 	.bpc = 6,
841 	.size = {
842 		.width = 162,
843 		.height = 122,
844 	},
845 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
846 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
847 		DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
848 		DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
849 	.connector_type = DRM_MODE_CONNECTOR_DPI,
850 };
851 
852 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
853 	.pixelclock = { 26400000, 33300000, 46800000 },
854 	.hactive = { 800, 800, 800 },
855 	.hfront_porch = { 16, 210, 354 },
856 	.hback_porch = { 45, 36, 6 },
857 	.hsync_len = { 1, 10, 40 },
858 	.vactive = { 480, 480, 480 },
859 	.vfront_porch = { 7, 22, 147 },
860 	.vback_porch = { 22, 13, 3 },
861 	.vsync_len = { 1, 10, 20 },
862 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
863 		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
864 };
865 
866 static const struct panel_desc armadeus_st0700_adapt = {
867 	.timings = &santek_st0700i5y_rbslw_f_timing,
868 	.num_timings = 1,
869 	.bpc = 6,
870 	.size = {
871 		.width = 154,
872 		.height = 86,
873 	},
874 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
875 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
876 };
877 
878 static const struct drm_display_mode auo_b101aw03_mode = {
879 	.clock = 51450,
880 	.hdisplay = 1024,
881 	.hsync_start = 1024 + 156,
882 	.hsync_end = 1024 + 156 + 8,
883 	.htotal = 1024 + 156 + 8 + 156,
884 	.vdisplay = 600,
885 	.vsync_start = 600 + 16,
886 	.vsync_end = 600 + 16 + 6,
887 	.vtotal = 600 + 16 + 6 + 16,
888 };
889 
890 static const struct panel_desc auo_b101aw03 = {
891 	.modes = &auo_b101aw03_mode,
892 	.num_modes = 1,
893 	.bpc = 6,
894 	.size = {
895 		.width = 223,
896 		.height = 125,
897 	},
898 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
899 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
900 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
901 };
902 
903 static const struct drm_display_mode auo_b101xtn01_mode = {
904 	.clock = 72000,
905 	.hdisplay = 1366,
906 	.hsync_start = 1366 + 20,
907 	.hsync_end = 1366 + 20 + 70,
908 	.htotal = 1366 + 20 + 70,
909 	.vdisplay = 768,
910 	.vsync_start = 768 + 14,
911 	.vsync_end = 768 + 14 + 42,
912 	.vtotal = 768 + 14 + 42,
913 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
914 };
915 
916 static const struct panel_desc auo_b101xtn01 = {
917 	.modes = &auo_b101xtn01_mode,
918 	.num_modes = 1,
919 	.bpc = 6,
920 	.size = {
921 		.width = 223,
922 		.height = 125,
923 	},
924 };
925 
926 static const struct display_timing auo_g070vvn01_timings = {
927 	.pixelclock = { 33300000, 34209000, 45000000 },
928 	.hactive = { 800, 800, 800 },
929 	.hfront_porch = { 20, 40, 200 },
930 	.hback_porch = { 87, 40, 1 },
931 	.hsync_len = { 1, 48, 87 },
932 	.vactive = { 480, 480, 480 },
933 	.vfront_porch = { 5, 13, 200 },
934 	.vback_porch = { 31, 31, 29 },
935 	.vsync_len = { 1, 1, 3 },
936 };
937 
938 static const struct panel_desc auo_g070vvn01 = {
939 	.timings = &auo_g070vvn01_timings,
940 	.num_timings = 1,
941 	.bpc = 8,
942 	.size = {
943 		.width = 152,
944 		.height = 91,
945 	},
946 	.delay = {
947 		.prepare = 200,
948 		.enable = 50,
949 		.disable = 50,
950 		.unprepare = 1000,
951 	},
952 };
953 
954 static const struct drm_display_mode auo_g101evn010_mode = {
955 	.clock = 68930,
956 	.hdisplay = 1280,
957 	.hsync_start = 1280 + 82,
958 	.hsync_end = 1280 + 82 + 2,
959 	.htotal = 1280 + 82 + 2 + 84,
960 	.vdisplay = 800,
961 	.vsync_start = 800 + 8,
962 	.vsync_end = 800 + 8 + 2,
963 	.vtotal = 800 + 8 + 2 + 6,
964 };
965 
966 static const struct panel_desc auo_g101evn010 = {
967 	.modes = &auo_g101evn010_mode,
968 	.num_modes = 1,
969 	.bpc = 6,
970 	.size = {
971 		.width = 216,
972 		.height = 135,
973 	},
974 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
975 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
976 };
977 
978 static const struct drm_display_mode auo_g104sn02_mode = {
979 	.clock = 40000,
980 	.hdisplay = 800,
981 	.hsync_start = 800 + 40,
982 	.hsync_end = 800 + 40 + 216,
983 	.htotal = 800 + 40 + 216 + 128,
984 	.vdisplay = 600,
985 	.vsync_start = 600 + 10,
986 	.vsync_end = 600 + 10 + 35,
987 	.vtotal = 600 + 10 + 35 + 2,
988 };
989 
990 static const struct panel_desc auo_g104sn02 = {
991 	.modes = &auo_g104sn02_mode,
992 	.num_modes = 1,
993 	.bpc = 8,
994 	.size = {
995 		.width = 211,
996 		.height = 158,
997 	},
998 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
999 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1000 };
1001 
1002 static const struct drm_display_mode auo_g121ean01_mode = {
1003 	.clock = 66700,
1004 	.hdisplay = 1280,
1005 	.hsync_start = 1280 + 58,
1006 	.hsync_end = 1280 + 58 + 8,
1007 	.htotal = 1280 + 58 + 8 + 70,
1008 	.vdisplay = 800,
1009 	.vsync_start = 800 + 6,
1010 	.vsync_end = 800 + 6 + 4,
1011 	.vtotal = 800 + 6 + 4 + 10,
1012 };
1013 
1014 static const struct panel_desc auo_g121ean01 = {
1015 	.modes = &auo_g121ean01_mode,
1016 	.num_modes = 1,
1017 	.bpc = 8,
1018 	.size = {
1019 		.width = 261,
1020 		.height = 163,
1021 	},
1022 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1023 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1024 };
1025 
1026 static const struct display_timing auo_g133han01_timings = {
1027 	.pixelclock = { 134000000, 141200000, 149000000 },
1028 	.hactive = { 1920, 1920, 1920 },
1029 	.hfront_porch = { 39, 58, 77 },
1030 	.hback_porch = { 59, 88, 117 },
1031 	.hsync_len = { 28, 42, 56 },
1032 	.vactive = { 1080, 1080, 1080 },
1033 	.vfront_porch = { 3, 8, 11 },
1034 	.vback_porch = { 5, 14, 19 },
1035 	.vsync_len = { 4, 14, 19 },
1036 };
1037 
1038 static const struct panel_desc auo_g133han01 = {
1039 	.timings = &auo_g133han01_timings,
1040 	.num_timings = 1,
1041 	.bpc = 8,
1042 	.size = {
1043 		.width = 293,
1044 		.height = 165,
1045 	},
1046 	.delay = {
1047 		.prepare = 200,
1048 		.enable = 50,
1049 		.disable = 50,
1050 		.unprepare = 1000,
1051 	},
1052 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1053 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1054 };
1055 
1056 static const struct drm_display_mode auo_g156xtn01_mode = {
1057 	.clock = 76000,
1058 	.hdisplay = 1366,
1059 	.hsync_start = 1366 + 33,
1060 	.hsync_end = 1366 + 33 + 67,
1061 	.htotal = 1560,
1062 	.vdisplay = 768,
1063 	.vsync_start = 768 + 4,
1064 	.vsync_end = 768 + 4 + 4,
1065 	.vtotal = 806,
1066 };
1067 
1068 static const struct panel_desc auo_g156xtn01 = {
1069 	.modes = &auo_g156xtn01_mode,
1070 	.num_modes = 1,
1071 	.bpc = 8,
1072 	.size = {
1073 		.width = 344,
1074 		.height = 194,
1075 	},
1076 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1077 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1078 };
1079 
1080 static const struct display_timing auo_g185han01_timings = {
1081 	.pixelclock = { 120000000, 144000000, 175000000 },
1082 	.hactive = { 1920, 1920, 1920 },
1083 	.hfront_porch = { 36, 120, 148 },
1084 	.hback_porch = { 24, 88, 108 },
1085 	.hsync_len = { 20, 48, 64 },
1086 	.vactive = { 1080, 1080, 1080 },
1087 	.vfront_porch = { 6, 10, 40 },
1088 	.vback_porch = { 2, 5, 20 },
1089 	.vsync_len = { 2, 5, 20 },
1090 };
1091 
1092 static const struct panel_desc auo_g185han01 = {
1093 	.timings = &auo_g185han01_timings,
1094 	.num_timings = 1,
1095 	.bpc = 8,
1096 	.size = {
1097 		.width = 409,
1098 		.height = 230,
1099 	},
1100 	.delay = {
1101 		.prepare = 50,
1102 		.enable = 200,
1103 		.disable = 110,
1104 		.unprepare = 1000,
1105 	},
1106 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1107 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1108 };
1109 
1110 static const struct display_timing auo_g190ean01_timings = {
1111 	.pixelclock = { 90000000, 108000000, 135000000 },
1112 	.hactive = { 1280, 1280, 1280 },
1113 	.hfront_porch = { 126, 184, 1266 },
1114 	.hback_porch = { 84, 122, 844 },
1115 	.hsync_len = { 70, 102, 704 },
1116 	.vactive = { 1024, 1024, 1024 },
1117 	.vfront_porch = { 4, 26, 76 },
1118 	.vback_porch = { 2, 8, 25 },
1119 	.vsync_len = { 2, 8, 25 },
1120 };
1121 
1122 static const struct panel_desc auo_g190ean01 = {
1123 	.timings = &auo_g190ean01_timings,
1124 	.num_timings = 1,
1125 	.bpc = 8,
1126 	.size = {
1127 		.width = 376,
1128 		.height = 301,
1129 	},
1130 	.delay = {
1131 		.prepare = 50,
1132 		.enable = 200,
1133 		.disable = 110,
1134 		.unprepare = 1000,
1135 	},
1136 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1137 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1138 };
1139 
1140 static const struct display_timing auo_p320hvn03_timings = {
1141 	.pixelclock = { 106000000, 148500000, 164000000 },
1142 	.hactive = { 1920, 1920, 1920 },
1143 	.hfront_porch = { 25, 50, 130 },
1144 	.hback_porch = { 25, 50, 130 },
1145 	.hsync_len = { 20, 40, 105 },
1146 	.vactive = { 1080, 1080, 1080 },
1147 	.vfront_porch = { 8, 17, 150 },
1148 	.vback_porch = { 8, 17, 150 },
1149 	.vsync_len = { 4, 11, 100 },
1150 };
1151 
1152 static const struct panel_desc auo_p320hvn03 = {
1153 	.timings = &auo_p320hvn03_timings,
1154 	.num_timings = 1,
1155 	.bpc = 8,
1156 	.size = {
1157 		.width = 698,
1158 		.height = 393,
1159 	},
1160 	.delay = {
1161 		.prepare = 1,
1162 		.enable = 450,
1163 		.unprepare = 500,
1164 	},
1165 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1166 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1167 };
1168 
1169 static const struct drm_display_mode auo_t215hvn01_mode = {
1170 	.clock = 148800,
1171 	.hdisplay = 1920,
1172 	.hsync_start = 1920 + 88,
1173 	.hsync_end = 1920 + 88 + 44,
1174 	.htotal = 1920 + 88 + 44 + 148,
1175 	.vdisplay = 1080,
1176 	.vsync_start = 1080 + 4,
1177 	.vsync_end = 1080 + 4 + 5,
1178 	.vtotal = 1080 + 4 + 5 + 36,
1179 };
1180 
1181 static const struct panel_desc auo_t215hvn01 = {
1182 	.modes = &auo_t215hvn01_mode,
1183 	.num_modes = 1,
1184 	.bpc = 8,
1185 	.size = {
1186 		.width = 430,
1187 		.height = 270,
1188 	},
1189 	.delay = {
1190 		.disable = 5,
1191 		.unprepare = 1000,
1192 	}
1193 };
1194 
1195 static const struct drm_display_mode avic_tm070ddh03_mode = {
1196 	.clock = 51200,
1197 	.hdisplay = 1024,
1198 	.hsync_start = 1024 + 160,
1199 	.hsync_end = 1024 + 160 + 4,
1200 	.htotal = 1024 + 160 + 4 + 156,
1201 	.vdisplay = 600,
1202 	.vsync_start = 600 + 17,
1203 	.vsync_end = 600 + 17 + 1,
1204 	.vtotal = 600 + 17 + 1 + 17,
1205 };
1206 
1207 static const struct panel_desc avic_tm070ddh03 = {
1208 	.modes = &avic_tm070ddh03_mode,
1209 	.num_modes = 1,
1210 	.bpc = 8,
1211 	.size = {
1212 		.width = 154,
1213 		.height = 90,
1214 	},
1215 	.delay = {
1216 		.prepare = 20,
1217 		.enable = 200,
1218 		.disable = 200,
1219 	},
1220 };
1221 
1222 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1223 	.clock = 30000,
1224 	.hdisplay = 800,
1225 	.hsync_start = 800 + 40,
1226 	.hsync_end = 800 + 40 + 48,
1227 	.htotal = 800 + 40 + 48 + 40,
1228 	.vdisplay = 480,
1229 	.vsync_start = 480 + 13,
1230 	.vsync_end = 480 + 13 + 3,
1231 	.vtotal = 480 + 13 + 3 + 29,
1232 };
1233 
1234 static const struct panel_desc bananapi_s070wv20_ct16 = {
1235 	.modes = &bananapi_s070wv20_ct16_mode,
1236 	.num_modes = 1,
1237 	.bpc = 6,
1238 	.size = {
1239 		.width = 154,
1240 		.height = 86,
1241 	},
1242 };
1243 
1244 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1245 	.pixelclock = { 69922000, 71000000, 72293000 },
1246 	.hactive = { 1280, 1280, 1280 },
1247 	.hfront_porch = { 48, 48, 48 },
1248 	.hback_porch = { 80, 80, 80 },
1249 	.hsync_len = { 32, 32, 32 },
1250 	.vactive = { 800, 800, 800 },
1251 	.vfront_porch = { 3, 3, 3 },
1252 	.vback_porch = { 14, 14, 14 },
1253 	.vsync_len = { 6, 6, 6 },
1254 };
1255 
1256 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1257 	.timings = &boe_ev121wxm_n10_1850_timing,
1258 	.num_timings = 1,
1259 	.bpc = 8,
1260 	.size = {
1261 		.width = 261,
1262 		.height = 163,
1263 	},
1264 	.delay = {
1265 		.prepare = 9,
1266 		.enable = 300,
1267 		.unprepare = 300,
1268 		.disable = 560,
1269 	},
1270 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1271 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1272 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1273 };
1274 
1275 static const struct drm_display_mode boe_hv070wsa_mode = {
1276 	.clock = 42105,
1277 	.hdisplay = 1024,
1278 	.hsync_start = 1024 + 30,
1279 	.hsync_end = 1024 + 30 + 30,
1280 	.htotal = 1024 + 30 + 30 + 30,
1281 	.vdisplay = 600,
1282 	.vsync_start = 600 + 10,
1283 	.vsync_end = 600 + 10 + 10,
1284 	.vtotal = 600 + 10 + 10 + 10,
1285 };
1286 
1287 static const struct panel_desc boe_hv070wsa = {
1288 	.modes = &boe_hv070wsa_mode,
1289 	.num_modes = 1,
1290 	.bpc = 8,
1291 	.size = {
1292 		.width = 154,
1293 		.height = 90,
1294 	},
1295 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1296 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1297 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1298 };
1299 
1300 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1301 	.clock = 9000,
1302 	.hdisplay = 480,
1303 	.hsync_start = 480 + 5,
1304 	.hsync_end = 480 + 5 + 5,
1305 	.htotal = 480 + 5 + 5 + 40,
1306 	.vdisplay = 272,
1307 	.vsync_start = 272 + 8,
1308 	.vsync_end = 272 + 8 + 8,
1309 	.vtotal = 272 + 8 + 8 + 8,
1310 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1311 };
1312 
1313 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1314 	.modes = &cdtech_s043wq26h_ct7_mode,
1315 	.num_modes = 1,
1316 	.bpc = 8,
1317 	.size = {
1318 		.width = 95,
1319 		.height = 54,
1320 	},
1321 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1322 };
1323 
1324 /* S070PWS19HP-FC21 2017/04/22 */
1325 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1326 	.clock = 51200,
1327 	.hdisplay = 1024,
1328 	.hsync_start = 1024 + 160,
1329 	.hsync_end = 1024 + 160 + 20,
1330 	.htotal = 1024 + 160 + 20 + 140,
1331 	.vdisplay = 600,
1332 	.vsync_start = 600 + 12,
1333 	.vsync_end = 600 + 12 + 3,
1334 	.vtotal = 600 + 12 + 3 + 20,
1335 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1336 };
1337 
1338 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1339 	.modes = &cdtech_s070pws19hp_fc21_mode,
1340 	.num_modes = 1,
1341 	.bpc = 6,
1342 	.size = {
1343 		.width = 154,
1344 		.height = 86,
1345 	},
1346 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1347 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1348 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1349 };
1350 
1351 /* S070SWV29HG-DC44 2017/09/21 */
1352 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1353 	.clock = 33300,
1354 	.hdisplay = 800,
1355 	.hsync_start = 800 + 210,
1356 	.hsync_end = 800 + 210 + 2,
1357 	.htotal = 800 + 210 + 2 + 44,
1358 	.vdisplay = 480,
1359 	.vsync_start = 480 + 22,
1360 	.vsync_end = 480 + 22 + 2,
1361 	.vtotal = 480 + 22 + 2 + 21,
1362 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1363 };
1364 
1365 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1366 	.modes = &cdtech_s070swv29hg_dc44_mode,
1367 	.num_modes = 1,
1368 	.bpc = 6,
1369 	.size = {
1370 		.width = 154,
1371 		.height = 86,
1372 	},
1373 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1374 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1375 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1376 };
1377 
1378 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1379 	.clock = 35000,
1380 	.hdisplay = 800,
1381 	.hsync_start = 800 + 40,
1382 	.hsync_end = 800 + 40 + 40,
1383 	.htotal = 800 + 40 + 40 + 48,
1384 	.vdisplay = 480,
1385 	.vsync_start = 480 + 29,
1386 	.vsync_end = 480 + 29 + 13,
1387 	.vtotal = 480 + 29 + 13 + 3,
1388 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1389 };
1390 
1391 static const struct panel_desc cdtech_s070wv95_ct16 = {
1392 	.modes = &cdtech_s070wv95_ct16_mode,
1393 	.num_modes = 1,
1394 	.bpc = 8,
1395 	.size = {
1396 		.width = 154,
1397 		.height = 85,
1398 	},
1399 };
1400 
1401 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1402 	.pixelclock = { 68900000, 71100000, 73400000 },
1403 	.hactive = { 1280, 1280, 1280 },
1404 	.hfront_porch = { 65, 80, 95 },
1405 	.hback_porch = { 64, 79, 94 },
1406 	.hsync_len = { 1, 1, 1 },
1407 	.vactive = { 800, 800, 800 },
1408 	.vfront_porch = { 7, 11, 14 },
1409 	.vback_porch = { 7, 11, 14 },
1410 	.vsync_len = { 1, 1, 1 },
1411 	.flags = DISPLAY_FLAGS_DE_HIGH,
1412 };
1413 
1414 static const struct panel_desc chefree_ch101olhlwh_002 = {
1415 	.timings = &chefree_ch101olhlwh_002_timing,
1416 	.num_timings = 1,
1417 	.bpc = 8,
1418 	.size = {
1419 		.width = 217,
1420 		.height = 135,
1421 	},
1422 	.delay = {
1423 		.enable = 200,
1424 		.disable = 200,
1425 	},
1426 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1427 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1428 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1429 };
1430 
1431 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1432 	.clock = 66770,
1433 	.hdisplay = 800,
1434 	.hsync_start = 800 + 49,
1435 	.hsync_end = 800 + 49 + 33,
1436 	.htotal = 800 + 49 + 33 + 17,
1437 	.vdisplay = 1280,
1438 	.vsync_start = 1280 + 1,
1439 	.vsync_end = 1280 + 1 + 7,
1440 	.vtotal = 1280 + 1 + 7 + 15,
1441 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1442 };
1443 
1444 static const struct panel_desc chunghwa_claa070wp03xg = {
1445 	.modes = &chunghwa_claa070wp03xg_mode,
1446 	.num_modes = 1,
1447 	.bpc = 6,
1448 	.size = {
1449 		.width = 94,
1450 		.height = 150,
1451 	},
1452 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1453 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1454 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1455 };
1456 
1457 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1458 	.clock = 72070,
1459 	.hdisplay = 1366,
1460 	.hsync_start = 1366 + 58,
1461 	.hsync_end = 1366 + 58 + 58,
1462 	.htotal = 1366 + 58 + 58 + 58,
1463 	.vdisplay = 768,
1464 	.vsync_start = 768 + 4,
1465 	.vsync_end = 768 + 4 + 4,
1466 	.vtotal = 768 + 4 + 4 + 4,
1467 };
1468 
1469 static const struct panel_desc chunghwa_claa101wa01a = {
1470 	.modes = &chunghwa_claa101wa01a_mode,
1471 	.num_modes = 1,
1472 	.bpc = 6,
1473 	.size = {
1474 		.width = 220,
1475 		.height = 120,
1476 	},
1477 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1478 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1479 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1480 };
1481 
1482 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1483 	.clock = 69300,
1484 	.hdisplay = 1366,
1485 	.hsync_start = 1366 + 48,
1486 	.hsync_end = 1366 + 48 + 32,
1487 	.htotal = 1366 + 48 + 32 + 20,
1488 	.vdisplay = 768,
1489 	.vsync_start = 768 + 16,
1490 	.vsync_end = 768 + 16 + 8,
1491 	.vtotal = 768 + 16 + 8 + 16,
1492 };
1493 
1494 static const struct panel_desc chunghwa_claa101wb01 = {
1495 	.modes = &chunghwa_claa101wb01_mode,
1496 	.num_modes = 1,
1497 	.bpc = 6,
1498 	.size = {
1499 		.width = 223,
1500 		.height = 125,
1501 	},
1502 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1503 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1504 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1505 };
1506 
1507 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1508 	.pixelclock = { 5000000, 9000000, 12000000 },
1509 	.hactive = { 480, 480, 480 },
1510 	.hfront_porch = { 12, 12, 12 },
1511 	.hback_porch = { 12, 12, 12 },
1512 	.hsync_len = { 21, 21, 21 },
1513 	.vactive = { 272, 272, 272 },
1514 	.vfront_porch = { 4, 4, 4 },
1515 	.vback_porch = { 4, 4, 4 },
1516 	.vsync_len = { 8, 8, 8 },
1517 };
1518 
1519 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1520 	.timings = &dataimage_fg040346dsswbg04_timing,
1521 	.num_timings = 1,
1522 	.bpc = 8,
1523 	.size = {
1524 		.width = 95,
1525 		.height = 54,
1526 	},
1527 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1528 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1529 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1530 };
1531 
1532 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1533 	.pixelclock = { 68900000, 71110000, 73400000 },
1534 	.hactive = { 1280, 1280, 1280 },
1535 	.vactive = { 800, 800, 800 },
1536 	.hback_porch = { 100, 100, 100 },
1537 	.hfront_porch = { 100, 100, 100 },
1538 	.vback_porch = { 5, 5, 5 },
1539 	.vfront_porch = { 5, 5, 5 },
1540 	.hsync_len = { 24, 24, 24 },
1541 	.vsync_len = { 3, 3, 3 },
1542 	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1543 		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1544 };
1545 
1546 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1547 	.timings = &dataimage_fg1001l0dsswmg01_timing,
1548 	.num_timings = 1,
1549 	.bpc = 8,
1550 	.size = {
1551 		.width = 217,
1552 		.height = 136,
1553 	},
1554 };
1555 
1556 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1557 	.clock = 33260,
1558 	.hdisplay = 800,
1559 	.hsync_start = 800 + 40,
1560 	.hsync_end = 800 + 40 + 128,
1561 	.htotal = 800 + 40 + 128 + 88,
1562 	.vdisplay = 480,
1563 	.vsync_start = 480 + 10,
1564 	.vsync_end = 480 + 10 + 2,
1565 	.vtotal = 480 + 10 + 2 + 33,
1566 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1567 };
1568 
1569 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1570 	.modes = &dataimage_scf0700c48ggu18_mode,
1571 	.num_modes = 1,
1572 	.bpc = 8,
1573 	.size = {
1574 		.width = 152,
1575 		.height = 91,
1576 	},
1577 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1578 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1579 };
1580 
1581 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1582 	.pixelclock = { 45000000, 51200000, 57000000 },
1583 	.hactive = { 1024, 1024, 1024 },
1584 	.hfront_porch = { 100, 106, 113 },
1585 	.hback_porch = { 100, 106, 113 },
1586 	.hsync_len = { 100, 108, 114 },
1587 	.vactive = { 600, 600, 600 },
1588 	.vfront_porch = { 8, 11, 15 },
1589 	.vback_porch = { 8, 11, 15 },
1590 	.vsync_len = { 9, 13, 15 },
1591 	.flags = DISPLAY_FLAGS_DE_HIGH,
1592 };
1593 
1594 static const struct panel_desc dlc_dlc0700yzg_1 = {
1595 	.timings = &dlc_dlc0700yzg_1_timing,
1596 	.num_timings = 1,
1597 	.bpc = 6,
1598 	.size = {
1599 		.width = 154,
1600 		.height = 86,
1601 	},
1602 	.delay = {
1603 		.prepare = 30,
1604 		.enable = 200,
1605 		.disable = 200,
1606 	},
1607 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1608 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1609 };
1610 
1611 static const struct display_timing dlc_dlc1010gig_timing = {
1612 	.pixelclock = { 68900000, 71100000, 73400000 },
1613 	.hactive = { 1280, 1280, 1280 },
1614 	.hfront_porch = { 43, 53, 63 },
1615 	.hback_porch = { 43, 53, 63 },
1616 	.hsync_len = { 44, 54, 64 },
1617 	.vactive = { 800, 800, 800 },
1618 	.vfront_porch = { 5, 8, 11 },
1619 	.vback_porch = { 5, 8, 11 },
1620 	.vsync_len = { 5, 7, 11 },
1621 	.flags = DISPLAY_FLAGS_DE_HIGH,
1622 };
1623 
1624 static const struct panel_desc dlc_dlc1010gig = {
1625 	.timings = &dlc_dlc1010gig_timing,
1626 	.num_timings = 1,
1627 	.bpc = 8,
1628 	.size = {
1629 		.width = 216,
1630 		.height = 135,
1631 	},
1632 	.delay = {
1633 		.prepare = 60,
1634 		.enable = 150,
1635 		.disable = 100,
1636 		.unprepare = 60,
1637 	},
1638 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1639 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1640 };
1641 
1642 static const struct drm_display_mode edt_et035012dm6_mode = {
1643 	.clock = 6500,
1644 	.hdisplay = 320,
1645 	.hsync_start = 320 + 20,
1646 	.hsync_end = 320 + 20 + 30,
1647 	.htotal = 320 + 20 + 68,
1648 	.vdisplay = 240,
1649 	.vsync_start = 240 + 4,
1650 	.vsync_end = 240 + 4 + 4,
1651 	.vtotal = 240 + 4 + 4 + 14,
1652 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1653 };
1654 
1655 static const struct panel_desc edt_et035012dm6 = {
1656 	.modes = &edt_et035012dm6_mode,
1657 	.num_modes = 1,
1658 	.bpc = 8,
1659 	.size = {
1660 		.width = 70,
1661 		.height = 52,
1662 	},
1663 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1664 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1665 };
1666 
1667 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1668 	.clock = 6520,
1669 	.hdisplay = 320,
1670 	.hsync_start = 320 + 20,
1671 	.hsync_end = 320 + 20 + 68,
1672 	.htotal = 320 + 20 + 68,
1673 	.vdisplay = 240,
1674 	.vsync_start = 240 + 4,
1675 	.vsync_end = 240 + 4 + 18,
1676 	.vtotal = 240 + 4 + 18,
1677 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1678 };
1679 
1680 static const struct panel_desc edt_etm0350g0dh6 = {
1681 	.modes = &edt_etm0350g0dh6_mode,
1682 	.num_modes = 1,
1683 	.bpc = 6,
1684 	.size = {
1685 		.width = 70,
1686 		.height = 53,
1687 	},
1688 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1689 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1690 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1691 };
1692 
1693 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1694 	.clock = 10870,
1695 	.hdisplay = 480,
1696 	.hsync_start = 480 + 8,
1697 	.hsync_end = 480 + 8 + 4,
1698 	.htotal = 480 + 8 + 4 + 41,
1699 
1700 	/*
1701 	 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1702 	 * fb_align
1703 	 */
1704 
1705 	.vdisplay = 288,
1706 	.vsync_start = 288 + 2,
1707 	.vsync_end = 288 + 2 + 4,
1708 	.vtotal = 288 + 2 + 4 + 10,
1709 };
1710 
1711 static const struct panel_desc edt_etm043080dh6gp = {
1712 	.modes = &edt_etm043080dh6gp_mode,
1713 	.num_modes = 1,
1714 	.bpc = 8,
1715 	.size = {
1716 		.width = 100,
1717 		.height = 65,
1718 	},
1719 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1720 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1721 };
1722 
1723 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1724 	.clock = 9000,
1725 	.hdisplay = 480,
1726 	.hsync_start = 480 + 2,
1727 	.hsync_end = 480 + 2 + 41,
1728 	.htotal = 480 + 2 + 41 + 2,
1729 	.vdisplay = 272,
1730 	.vsync_start = 272 + 2,
1731 	.vsync_end = 272 + 2 + 10,
1732 	.vtotal = 272 + 2 + 10 + 2,
1733 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1734 };
1735 
1736 static const struct panel_desc edt_etm0430g0dh6 = {
1737 	.modes = &edt_etm0430g0dh6_mode,
1738 	.num_modes = 1,
1739 	.bpc = 6,
1740 	.size = {
1741 		.width = 95,
1742 		.height = 54,
1743 	},
1744 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1745 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1746 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1747 };
1748 
1749 static const struct drm_display_mode edt_et057090dhu_mode = {
1750 	.clock = 25175,
1751 	.hdisplay = 640,
1752 	.hsync_start = 640 + 16,
1753 	.hsync_end = 640 + 16 + 30,
1754 	.htotal = 640 + 16 + 30 + 114,
1755 	.vdisplay = 480,
1756 	.vsync_start = 480 + 10,
1757 	.vsync_end = 480 + 10 + 3,
1758 	.vtotal = 480 + 10 + 3 + 32,
1759 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1760 };
1761 
1762 static const struct panel_desc edt_et057090dhu = {
1763 	.modes = &edt_et057090dhu_mode,
1764 	.num_modes = 1,
1765 	.bpc = 6,
1766 	.size = {
1767 		.width = 115,
1768 		.height = 86,
1769 	},
1770 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1771 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1772 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1773 };
1774 
1775 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1776 	.clock = 33260,
1777 	.hdisplay = 800,
1778 	.hsync_start = 800 + 40,
1779 	.hsync_end = 800 + 40 + 128,
1780 	.htotal = 800 + 40 + 128 + 88,
1781 	.vdisplay = 480,
1782 	.vsync_start = 480 + 10,
1783 	.vsync_end = 480 + 10 + 2,
1784 	.vtotal = 480 + 10 + 2 + 33,
1785 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1786 };
1787 
1788 static const struct panel_desc edt_etm0700g0dh6 = {
1789 	.modes = &edt_etm0700g0dh6_mode,
1790 	.num_modes = 1,
1791 	.bpc = 6,
1792 	.size = {
1793 		.width = 152,
1794 		.height = 91,
1795 	},
1796 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1797 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1798 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1799 };
1800 
1801 static const struct panel_desc edt_etm0700g0bdh6 = {
1802 	.modes = &edt_etm0700g0dh6_mode,
1803 	.num_modes = 1,
1804 	.bpc = 6,
1805 	.size = {
1806 		.width = 152,
1807 		.height = 91,
1808 	},
1809 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1810 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1811 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1812 };
1813 
1814 static const struct display_timing edt_etml0700y5dha_timing = {
1815 	.pixelclock = { 40800000, 51200000, 67200000 },
1816 	.hactive = { 1024, 1024, 1024 },
1817 	.hfront_porch = { 30, 106, 125 },
1818 	.hback_porch = { 30, 106, 125 },
1819 	.hsync_len = { 30, 108, 126 },
1820 	.vactive = { 600, 600, 600 },
1821 	.vfront_porch = { 3, 12, 67},
1822 	.vback_porch = { 3, 12, 67 },
1823 	.vsync_len = { 4, 11, 66 },
1824 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1825 		 DISPLAY_FLAGS_DE_HIGH,
1826 };
1827 
1828 static const struct panel_desc edt_etml0700y5dha = {
1829 	.timings = &edt_etml0700y5dha_timing,
1830 	.num_timings = 1,
1831 	.bpc = 8,
1832 	.size = {
1833 		.width = 155,
1834 		.height = 86,
1835 	},
1836 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1837 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1838 };
1839 
1840 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1841 	.clock = 25175,
1842 	.hdisplay = 640,
1843 	.hsync_start = 640,
1844 	.hsync_end = 640 + 16,
1845 	.htotal = 640 + 16 + 30 + 114,
1846 	.vdisplay = 480,
1847 	.vsync_start = 480 + 10,
1848 	.vsync_end = 480 + 10 + 3,
1849 	.vtotal = 480 + 10 + 3 + 35,
1850 	.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1851 };
1852 
1853 static const struct panel_desc edt_etmv570g2dhu = {
1854 	.modes = &edt_etmv570g2dhu_mode,
1855 	.num_modes = 1,
1856 	.bpc = 6,
1857 	.size = {
1858 		.width = 115,
1859 		.height = 86,
1860 	},
1861 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1862 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1863 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1864 };
1865 
1866 static const struct display_timing eink_vb3300_kca_timing = {
1867 	.pixelclock = { 40000000, 40000000, 40000000 },
1868 	.hactive = { 334, 334, 334 },
1869 	.hfront_porch = { 1, 1, 1 },
1870 	.hback_porch = { 1, 1, 1 },
1871 	.hsync_len = { 1, 1, 1 },
1872 	.vactive = { 1405, 1405, 1405 },
1873 	.vfront_porch = { 1, 1, 1 },
1874 	.vback_porch = { 1, 1, 1 },
1875 	.vsync_len = { 1, 1, 1 },
1876 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1877 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1878 };
1879 
1880 static const struct panel_desc eink_vb3300_kca = {
1881 	.timings = &eink_vb3300_kca_timing,
1882 	.num_timings = 1,
1883 	.bpc = 6,
1884 	.size = {
1885 		.width = 157,
1886 		.height = 209,
1887 	},
1888 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1889 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1890 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1891 };
1892 
1893 static const struct display_timing evervision_vgg804821_timing = {
1894 	.pixelclock = { 27600000, 33300000, 50000000 },
1895 	.hactive = { 800, 800, 800 },
1896 	.hfront_porch = { 40, 66, 70 },
1897 	.hback_porch = { 40, 67, 70 },
1898 	.hsync_len = { 40, 67, 70 },
1899 	.vactive = { 480, 480, 480 },
1900 	.vfront_porch = { 6, 10, 10 },
1901 	.vback_porch = { 7, 11, 11 },
1902 	.vsync_len = { 7, 11, 11 },
1903 	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1904 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1905 		 DISPLAY_FLAGS_SYNC_NEGEDGE,
1906 };
1907 
1908 static const struct panel_desc evervision_vgg804821 = {
1909 	.timings = &evervision_vgg804821_timing,
1910 	.num_timings = 1,
1911 	.bpc = 8,
1912 	.size = {
1913 		.width = 108,
1914 		.height = 64,
1915 	},
1916 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1917 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1918 };
1919 
1920 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1921 	.clock = 32260,
1922 	.hdisplay = 800,
1923 	.hsync_start = 800 + 168,
1924 	.hsync_end = 800 + 168 + 64,
1925 	.htotal = 800 + 168 + 64 + 88,
1926 	.vdisplay = 480,
1927 	.vsync_start = 480 + 37,
1928 	.vsync_end = 480 + 37 + 2,
1929 	.vtotal = 480 + 37 + 2 + 8,
1930 };
1931 
1932 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1933 	.modes = &foxlink_fl500wvr00_a0t_mode,
1934 	.num_modes = 1,
1935 	.bpc = 8,
1936 	.size = {
1937 		.width = 108,
1938 		.height = 65,
1939 	},
1940 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1941 };
1942 
1943 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1944 	{ /* 60 Hz */
1945 		.clock = 6000,
1946 		.hdisplay = 320,
1947 		.hsync_start = 320 + 44,
1948 		.hsync_end = 320 + 44 + 16,
1949 		.htotal = 320 + 44 + 16 + 20,
1950 		.vdisplay = 240,
1951 		.vsync_start = 240 + 2,
1952 		.vsync_end = 240 + 2 + 6,
1953 		.vtotal = 240 + 2 + 6 + 2,
1954 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1955 	},
1956 	{ /* 50 Hz */
1957 		.clock = 5400,
1958 		.hdisplay = 320,
1959 		.hsync_start = 320 + 56,
1960 		.hsync_end = 320 + 56 + 16,
1961 		.htotal = 320 + 56 + 16 + 40,
1962 		.vdisplay = 240,
1963 		.vsync_start = 240 + 2,
1964 		.vsync_end = 240 + 2 + 6,
1965 		.vtotal = 240 + 2 + 6 + 2,
1966 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1967 	},
1968 };
1969 
1970 static const struct panel_desc frida_frd350h54004 = {
1971 	.modes = frida_frd350h54004_modes,
1972 	.num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1973 	.bpc = 8,
1974 	.size = {
1975 		.width = 77,
1976 		.height = 64,
1977 	},
1978 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1979 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1980 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1981 };
1982 
1983 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1984 	.clock		= 67185,
1985 	.hdisplay	= 800,
1986 	.hsync_start	= 800 + 20,
1987 	.hsync_end	= 800 + 20 + 24,
1988 	.htotal		= 800 + 20 + 24 + 20,
1989 	.vdisplay	= 1280,
1990 	.vsync_start	= 1280 + 4,
1991 	.vsync_end	= 1280 + 4 + 8,
1992 	.vtotal		= 1280 + 4 + 8 + 4,
1993 	.flags		= DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1994 };
1995 
1996 static const struct panel_desc friendlyarm_hd702e = {
1997 	.modes = &friendlyarm_hd702e_mode,
1998 	.num_modes = 1,
1999 	.size = {
2000 		.width	= 94,
2001 		.height	= 151,
2002 	},
2003 };
2004 
2005 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2006 	.clock = 9000,
2007 	.hdisplay = 480,
2008 	.hsync_start = 480 + 5,
2009 	.hsync_end = 480 + 5 + 1,
2010 	.htotal = 480 + 5 + 1 + 40,
2011 	.vdisplay = 272,
2012 	.vsync_start = 272 + 8,
2013 	.vsync_end = 272 + 8 + 1,
2014 	.vtotal = 272 + 8 + 1 + 8,
2015 };
2016 
2017 static const struct panel_desc giantplus_gpg482739qs5 = {
2018 	.modes = &giantplus_gpg482739qs5_mode,
2019 	.num_modes = 1,
2020 	.bpc = 8,
2021 	.size = {
2022 		.width = 95,
2023 		.height = 54,
2024 	},
2025 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2026 };
2027 
2028 static const struct display_timing giantplus_gpm940b0_timing = {
2029 	.pixelclock = { 13500000, 27000000, 27500000 },
2030 	.hactive = { 320, 320, 320 },
2031 	.hfront_porch = { 14, 686, 718 },
2032 	.hback_porch = { 50, 70, 255 },
2033 	.hsync_len = { 1, 1, 1 },
2034 	.vactive = { 240, 240, 240 },
2035 	.vfront_porch = { 1, 1, 179 },
2036 	.vback_porch = { 1, 21, 31 },
2037 	.vsync_len = { 1, 1, 6 },
2038 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2039 };
2040 
2041 static const struct panel_desc giantplus_gpm940b0 = {
2042 	.timings = &giantplus_gpm940b0_timing,
2043 	.num_timings = 1,
2044 	.bpc = 8,
2045 	.size = {
2046 		.width = 60,
2047 		.height = 45,
2048 	},
2049 	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2050 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2051 };
2052 
2053 static const struct display_timing hannstar_hsd070pww1_timing = {
2054 	.pixelclock = { 64300000, 71100000, 82000000 },
2055 	.hactive = { 1280, 1280, 1280 },
2056 	.hfront_porch = { 1, 1, 10 },
2057 	.hback_porch = { 1, 1, 10 },
2058 	/*
2059 	 * According to the data sheet, the minimum horizontal blanking interval
2060 	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2061 	 * minimum working horizontal blanking interval to be 60 clocks.
2062 	 */
2063 	.hsync_len = { 58, 158, 661 },
2064 	.vactive = { 800, 800, 800 },
2065 	.vfront_porch = { 1, 1, 10 },
2066 	.vback_porch = { 1, 1, 10 },
2067 	.vsync_len = { 1, 21, 203 },
2068 	.flags = DISPLAY_FLAGS_DE_HIGH,
2069 };
2070 
2071 static const struct panel_desc hannstar_hsd070pww1 = {
2072 	.timings = &hannstar_hsd070pww1_timing,
2073 	.num_timings = 1,
2074 	.bpc = 6,
2075 	.size = {
2076 		.width = 151,
2077 		.height = 94,
2078 	},
2079 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2080 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2081 };
2082 
2083 static const struct display_timing hannstar_hsd100pxn1_timing = {
2084 	.pixelclock = { 55000000, 65000000, 75000000 },
2085 	.hactive = { 1024, 1024, 1024 },
2086 	.hfront_porch = { 40, 40, 40 },
2087 	.hback_porch = { 220, 220, 220 },
2088 	.hsync_len = { 20, 60, 100 },
2089 	.vactive = { 768, 768, 768 },
2090 	.vfront_porch = { 7, 7, 7 },
2091 	.vback_porch = { 21, 21, 21 },
2092 	.vsync_len = { 10, 10, 10 },
2093 	.flags = DISPLAY_FLAGS_DE_HIGH,
2094 };
2095 
2096 static const struct panel_desc hannstar_hsd100pxn1 = {
2097 	.timings = &hannstar_hsd100pxn1_timing,
2098 	.num_timings = 1,
2099 	.bpc = 6,
2100 	.size = {
2101 		.width = 203,
2102 		.height = 152,
2103 	},
2104 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2105 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2106 };
2107 
2108 static const struct display_timing hannstar_hsd101pww2_timing = {
2109 	.pixelclock = { 64300000, 71100000, 82000000 },
2110 	.hactive = { 1280, 1280, 1280 },
2111 	.hfront_porch = { 1, 1, 10 },
2112 	.hback_porch = { 1, 1, 10 },
2113 	.hsync_len = { 58, 158, 661 },
2114 	.vactive = { 800, 800, 800 },
2115 	.vfront_porch = { 1, 1, 10 },
2116 	.vback_porch = { 1, 1, 10 },
2117 	.vsync_len = { 1, 21, 203 },
2118 	.flags = DISPLAY_FLAGS_DE_HIGH,
2119 };
2120 
2121 static const struct panel_desc hannstar_hsd101pww2 = {
2122 	.timings = &hannstar_hsd101pww2_timing,
2123 	.num_timings = 1,
2124 	.bpc = 8,
2125 	.size = {
2126 		.width = 217,
2127 		.height = 136,
2128 	},
2129 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2130 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2131 };
2132 
2133 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2134 	.clock = 33333,
2135 	.hdisplay = 800,
2136 	.hsync_start = 800 + 85,
2137 	.hsync_end = 800 + 85 + 86,
2138 	.htotal = 800 + 85 + 86 + 85,
2139 	.vdisplay = 480,
2140 	.vsync_start = 480 + 16,
2141 	.vsync_end = 480 + 16 + 13,
2142 	.vtotal = 480 + 16 + 13 + 16,
2143 };
2144 
2145 static const struct panel_desc hitachi_tx23d38vm0caa = {
2146 	.modes = &hitachi_tx23d38vm0caa_mode,
2147 	.num_modes = 1,
2148 	.bpc = 6,
2149 	.size = {
2150 		.width = 195,
2151 		.height = 117,
2152 	},
2153 	.delay = {
2154 		.enable = 160,
2155 		.disable = 160,
2156 	},
2157 };
2158 
2159 static const struct drm_display_mode innolux_at043tn24_mode = {
2160 	.clock = 9000,
2161 	.hdisplay = 480,
2162 	.hsync_start = 480 + 2,
2163 	.hsync_end = 480 + 2 + 41,
2164 	.htotal = 480 + 2 + 41 + 2,
2165 	.vdisplay = 272,
2166 	.vsync_start = 272 + 2,
2167 	.vsync_end = 272 + 2 + 10,
2168 	.vtotal = 272 + 2 + 10 + 2,
2169 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2170 };
2171 
2172 static const struct panel_desc innolux_at043tn24 = {
2173 	.modes = &innolux_at043tn24_mode,
2174 	.num_modes = 1,
2175 	.bpc = 8,
2176 	.size = {
2177 		.width = 95,
2178 		.height = 54,
2179 	},
2180 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2181 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2182 };
2183 
2184 static const struct drm_display_mode innolux_at070tn92_mode = {
2185 	.clock = 33333,
2186 	.hdisplay = 800,
2187 	.hsync_start = 800 + 210,
2188 	.hsync_end = 800 + 210 + 20,
2189 	.htotal = 800 + 210 + 20 + 46,
2190 	.vdisplay = 480,
2191 	.vsync_start = 480 + 22,
2192 	.vsync_end = 480 + 22 + 10,
2193 	.vtotal = 480 + 22 + 23 + 10,
2194 };
2195 
2196 static const struct panel_desc innolux_at070tn92 = {
2197 	.modes = &innolux_at070tn92_mode,
2198 	.num_modes = 1,
2199 	.size = {
2200 		.width = 154,
2201 		.height = 86,
2202 	},
2203 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2204 };
2205 
2206 static const struct display_timing innolux_g070ace_l01_timing = {
2207 	.pixelclock = { 25200000, 35000000, 35700000 },
2208 	.hactive = { 800, 800, 800 },
2209 	.hfront_porch = { 30, 32, 87 },
2210 	.hback_porch = { 30, 32, 87 },
2211 	.hsync_len = { 1, 1, 1 },
2212 	.vactive = { 480, 480, 480 },
2213 	.vfront_porch = { 3, 3, 3 },
2214 	.vback_porch = { 13, 13, 13 },
2215 	.vsync_len = { 1, 1, 4 },
2216 	.flags = DISPLAY_FLAGS_DE_HIGH,
2217 };
2218 
2219 static const struct panel_desc innolux_g070ace_l01 = {
2220 	.timings = &innolux_g070ace_l01_timing,
2221 	.num_timings = 1,
2222 	.bpc = 8,
2223 	.size = {
2224 		.width = 152,
2225 		.height = 91,
2226 	},
2227 	.delay = {
2228 		.prepare = 10,
2229 		.enable = 50,
2230 		.disable = 50,
2231 		.unprepare = 500,
2232 	},
2233 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2234 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2235 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2236 };
2237 
2238 static const struct display_timing innolux_g070y2_l01_timing = {
2239 	.pixelclock = { 28000000, 29500000, 32000000 },
2240 	.hactive = { 800, 800, 800 },
2241 	.hfront_porch = { 61, 91, 141 },
2242 	.hback_porch = { 60, 90, 140 },
2243 	.hsync_len = { 12, 12, 12 },
2244 	.vactive = { 480, 480, 480 },
2245 	.vfront_porch = { 4, 9, 30 },
2246 	.vback_porch = { 4, 8, 28 },
2247 	.vsync_len = { 2, 2, 2 },
2248 	.flags = DISPLAY_FLAGS_DE_HIGH,
2249 };
2250 
2251 static const struct panel_desc innolux_g070y2_l01 = {
2252 	.timings = &innolux_g070y2_l01_timing,
2253 	.num_timings = 1,
2254 	.bpc = 8,
2255 	.size = {
2256 		.width = 152,
2257 		.height = 91,
2258 	},
2259 	.delay = {
2260 		.prepare = 10,
2261 		.enable = 100,
2262 		.disable = 100,
2263 		.unprepare = 800,
2264 	},
2265 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2266 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2267 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2268 };
2269 
2270 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2271 	.clock = 33333,
2272 	.hdisplay = 800,
2273 	.hsync_start = 800 + 210,
2274 	.hsync_end = 800 + 210 + 20,
2275 	.htotal = 800 + 210 + 20 + 46,
2276 	.vdisplay = 480,
2277 	.vsync_start = 480 + 22,
2278 	.vsync_end = 480 + 22 + 10,
2279 	.vtotal = 480 + 22 + 23 + 10,
2280 };
2281 
2282 static const struct panel_desc innolux_g070y2_t02 = {
2283 	.modes = &innolux_g070y2_t02_mode,
2284 	.num_modes = 1,
2285 	.bpc = 8,
2286 	.size = {
2287 		.width = 152,
2288 		.height = 92,
2289 	},
2290 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2291 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2292 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2293 };
2294 
2295 static const struct display_timing innolux_g101ice_l01_timing = {
2296 	.pixelclock = { 60400000, 71100000, 74700000 },
2297 	.hactive = { 1280, 1280, 1280 },
2298 	.hfront_porch = { 41, 80, 100 },
2299 	.hback_porch = { 40, 79, 99 },
2300 	.hsync_len = { 1, 1, 1 },
2301 	.vactive = { 800, 800, 800 },
2302 	.vfront_porch = { 5, 11, 14 },
2303 	.vback_porch = { 4, 11, 14 },
2304 	.vsync_len = { 1, 1, 1 },
2305 	.flags = DISPLAY_FLAGS_DE_HIGH,
2306 };
2307 
2308 static const struct panel_desc innolux_g101ice_l01 = {
2309 	.timings = &innolux_g101ice_l01_timing,
2310 	.num_timings = 1,
2311 	.bpc = 8,
2312 	.size = {
2313 		.width = 217,
2314 		.height = 135,
2315 	},
2316 	.delay = {
2317 		.enable = 200,
2318 		.disable = 200,
2319 	},
2320 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2321 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2322 };
2323 
2324 static const struct display_timing innolux_g121i1_l01_timing = {
2325 	.pixelclock = { 67450000, 71000000, 74550000 },
2326 	.hactive = { 1280, 1280, 1280 },
2327 	.hfront_porch = { 40, 80, 160 },
2328 	.hback_porch = { 39, 79, 159 },
2329 	.hsync_len = { 1, 1, 1 },
2330 	.vactive = { 800, 800, 800 },
2331 	.vfront_porch = { 5, 11, 100 },
2332 	.vback_porch = { 4, 11, 99 },
2333 	.vsync_len = { 1, 1, 1 },
2334 };
2335 
2336 static const struct panel_desc innolux_g121i1_l01 = {
2337 	.timings = &innolux_g121i1_l01_timing,
2338 	.num_timings = 1,
2339 	.bpc = 6,
2340 	.size = {
2341 		.width = 261,
2342 		.height = 163,
2343 	},
2344 	.delay = {
2345 		.enable = 200,
2346 		.disable = 20,
2347 	},
2348 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2349 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2350 };
2351 
2352 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2353 	.clock = 65000,
2354 	.hdisplay = 1024,
2355 	.hsync_start = 1024 + 0,
2356 	.hsync_end = 1024 + 1,
2357 	.htotal = 1024 + 0 + 1 + 320,
2358 	.vdisplay = 768,
2359 	.vsync_start = 768 + 38,
2360 	.vsync_end = 768 + 38 + 1,
2361 	.vtotal = 768 + 38 + 1 + 0,
2362 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2363 };
2364 
2365 static const struct panel_desc innolux_g121x1_l03 = {
2366 	.modes = &innolux_g121x1_l03_mode,
2367 	.num_modes = 1,
2368 	.bpc = 6,
2369 	.size = {
2370 		.width = 246,
2371 		.height = 185,
2372 	},
2373 	.delay = {
2374 		.enable = 200,
2375 		.unprepare = 200,
2376 		.disable = 400,
2377 	},
2378 };
2379 
2380 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2381 	.clock = 69300,
2382 	.hdisplay = 1366,
2383 	.hsync_start = 1366 + 16,
2384 	.hsync_end = 1366 + 16 + 34,
2385 	.htotal = 1366 + 16 + 34 + 50,
2386 	.vdisplay = 768,
2387 	.vsync_start = 768 + 2,
2388 	.vsync_end = 768 + 2 + 6,
2389 	.vtotal = 768 + 2 + 6 + 12,
2390 };
2391 
2392 static const struct panel_desc innolux_n156bge_l21 = {
2393 	.modes = &innolux_n156bge_l21_mode,
2394 	.num_modes = 1,
2395 	.bpc = 6,
2396 	.size = {
2397 		.width = 344,
2398 		.height = 193,
2399 	},
2400 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2401 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2402 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2403 };
2404 
2405 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2406 	.clock = 51501,
2407 	.hdisplay = 1024,
2408 	.hsync_start = 1024 + 128,
2409 	.hsync_end = 1024 + 128 + 64,
2410 	.htotal = 1024 + 128 + 64 + 128,
2411 	.vdisplay = 600,
2412 	.vsync_start = 600 + 16,
2413 	.vsync_end = 600 + 16 + 4,
2414 	.vtotal = 600 + 16 + 4 + 16,
2415 };
2416 
2417 static const struct panel_desc innolux_zj070na_01p = {
2418 	.modes = &innolux_zj070na_01p_mode,
2419 	.num_modes = 1,
2420 	.bpc = 6,
2421 	.size = {
2422 		.width = 154,
2423 		.height = 90,
2424 	},
2425 };
2426 
2427 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2428 	.pixelclock = { 5580000, 5850000, 6200000 },
2429 	.hactive = { 320, 320, 320 },
2430 	.hfront_porch = { 30, 30, 30 },
2431 	.hback_porch = { 30, 30, 30 },
2432 	.hsync_len = { 1, 5, 17 },
2433 	.vactive = { 240, 240, 240 },
2434 	.vfront_porch = { 6, 6, 6 },
2435 	.vback_porch = { 5, 5, 5 },
2436 	.vsync_len = { 1, 2, 11 },
2437 	.flags = DISPLAY_FLAGS_DE_HIGH,
2438 };
2439 
2440 static const struct panel_desc koe_tx14d24vm1bpa = {
2441 	.timings = &koe_tx14d24vm1bpa_timing,
2442 	.num_timings = 1,
2443 	.bpc = 6,
2444 	.size = {
2445 		.width = 115,
2446 		.height = 86,
2447 	},
2448 };
2449 
2450 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2451 	.pixelclock = { 151820000, 156720000, 159780000 },
2452 	.hactive = { 1920, 1920, 1920 },
2453 	.hfront_porch = { 105, 130, 142 },
2454 	.hback_porch = { 45, 70, 82 },
2455 	.hsync_len = { 30, 30, 30 },
2456 	.vactive = { 1200, 1200, 1200},
2457 	.vfront_porch = { 3, 5, 10 },
2458 	.vback_porch = { 2, 5, 10 },
2459 	.vsync_len = { 5, 5, 5 },
2460 };
2461 
2462 static const struct panel_desc koe_tx26d202vm0bwa = {
2463 	.timings = &koe_tx26d202vm0bwa_timing,
2464 	.num_timings = 1,
2465 	.bpc = 8,
2466 	.size = {
2467 		.width = 217,
2468 		.height = 136,
2469 	},
2470 	.delay = {
2471 		.prepare = 1000,
2472 		.enable = 1000,
2473 		.unprepare = 1000,
2474 		.disable = 1000,
2475 	},
2476 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2477 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2478 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2479 };
2480 
2481 static const struct display_timing koe_tx31d200vm0baa_timing = {
2482 	.pixelclock = { 39600000, 43200000, 48000000 },
2483 	.hactive = { 1280, 1280, 1280 },
2484 	.hfront_porch = { 16, 36, 56 },
2485 	.hback_porch = { 16, 36, 56 },
2486 	.hsync_len = { 8, 8, 8 },
2487 	.vactive = { 480, 480, 480 },
2488 	.vfront_porch = { 6, 21, 33 },
2489 	.vback_porch = { 6, 21, 33 },
2490 	.vsync_len = { 8, 8, 8 },
2491 	.flags = DISPLAY_FLAGS_DE_HIGH,
2492 };
2493 
2494 static const struct panel_desc koe_tx31d200vm0baa = {
2495 	.timings = &koe_tx31d200vm0baa_timing,
2496 	.num_timings = 1,
2497 	.bpc = 6,
2498 	.size = {
2499 		.width = 292,
2500 		.height = 109,
2501 	},
2502 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2503 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2504 };
2505 
2506 static const struct display_timing kyo_tcg121xglp_timing = {
2507 	.pixelclock = { 52000000, 65000000, 71000000 },
2508 	.hactive = { 1024, 1024, 1024 },
2509 	.hfront_porch = { 2, 2, 2 },
2510 	.hback_porch = { 2, 2, 2 },
2511 	.hsync_len = { 86, 124, 244 },
2512 	.vactive = { 768, 768, 768 },
2513 	.vfront_porch = { 2, 2, 2 },
2514 	.vback_porch = { 2, 2, 2 },
2515 	.vsync_len = { 6, 34, 73 },
2516 	.flags = DISPLAY_FLAGS_DE_HIGH,
2517 };
2518 
2519 static const struct panel_desc kyo_tcg121xglp = {
2520 	.timings = &kyo_tcg121xglp_timing,
2521 	.num_timings = 1,
2522 	.bpc = 8,
2523 	.size = {
2524 		.width = 246,
2525 		.height = 184,
2526 	},
2527 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2528 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2529 };
2530 
2531 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2532 	.clock = 7000,
2533 	.hdisplay = 320,
2534 	.hsync_start = 320 + 20,
2535 	.hsync_end = 320 + 20 + 30,
2536 	.htotal = 320 + 20 + 30 + 38,
2537 	.vdisplay = 240,
2538 	.vsync_start = 240 + 4,
2539 	.vsync_end = 240 + 4 + 3,
2540 	.vtotal = 240 + 4 + 3 + 15,
2541 };
2542 
2543 static const struct panel_desc lemaker_bl035_rgb_002 = {
2544 	.modes = &lemaker_bl035_rgb_002_mode,
2545 	.num_modes = 1,
2546 	.size = {
2547 		.width = 70,
2548 		.height = 52,
2549 	},
2550 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2551 	.bus_flags = DRM_BUS_FLAG_DE_LOW,
2552 };
2553 
2554 static const struct drm_display_mode lg_lb070wv8_mode = {
2555 	.clock = 33246,
2556 	.hdisplay = 800,
2557 	.hsync_start = 800 + 88,
2558 	.hsync_end = 800 + 88 + 80,
2559 	.htotal = 800 + 88 + 80 + 88,
2560 	.vdisplay = 480,
2561 	.vsync_start = 480 + 10,
2562 	.vsync_end = 480 + 10 + 25,
2563 	.vtotal = 480 + 10 + 25 + 10,
2564 };
2565 
2566 static const struct panel_desc lg_lb070wv8 = {
2567 	.modes = &lg_lb070wv8_mode,
2568 	.num_modes = 1,
2569 	.bpc = 8,
2570 	.size = {
2571 		.width = 151,
2572 		.height = 91,
2573 	},
2574 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2575 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2576 };
2577 
2578 static const struct display_timing logictechno_lt161010_2nh_timing = {
2579 	.pixelclock = { 26400000, 33300000, 46800000 },
2580 	.hactive = { 800, 800, 800 },
2581 	.hfront_porch = { 16, 210, 354 },
2582 	.hback_porch = { 46, 46, 46 },
2583 	.hsync_len = { 1, 20, 40 },
2584 	.vactive = { 480, 480, 480 },
2585 	.vfront_porch = { 7, 22, 147 },
2586 	.vback_porch = { 23, 23, 23 },
2587 	.vsync_len = { 1, 10, 20 },
2588 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2589 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2590 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2591 };
2592 
2593 static const struct panel_desc logictechno_lt161010_2nh = {
2594 	.timings = &logictechno_lt161010_2nh_timing,
2595 	.num_timings = 1,
2596 	.bpc = 6,
2597 	.size = {
2598 		.width = 154,
2599 		.height = 86,
2600 	},
2601 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2602 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2603 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2604 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2605 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2606 };
2607 
2608 static const struct display_timing logictechno_lt170410_2whc_timing = {
2609 	.pixelclock = { 68900000, 71100000, 73400000 },
2610 	.hactive = { 1280, 1280, 1280 },
2611 	.hfront_porch = { 23, 60, 71 },
2612 	.hback_porch = { 23, 60, 71 },
2613 	.hsync_len = { 15, 40, 47 },
2614 	.vactive = { 800, 800, 800 },
2615 	.vfront_porch = { 5, 7, 10 },
2616 	.vback_porch = { 5, 7, 10 },
2617 	.vsync_len = { 6, 9, 12 },
2618 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2619 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2620 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2621 };
2622 
2623 static const struct panel_desc logictechno_lt170410_2whc = {
2624 	.timings = &logictechno_lt170410_2whc_timing,
2625 	.num_timings = 1,
2626 	.bpc = 8,
2627 	.size = {
2628 		.width = 217,
2629 		.height = 136,
2630 	},
2631 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2632 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2633 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2634 };
2635 
2636 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2637 	.clock = 33000,
2638 	.hdisplay = 800,
2639 	.hsync_start = 800 + 112,
2640 	.hsync_end = 800 + 112 + 3,
2641 	.htotal = 800 + 112 + 3 + 85,
2642 	.vdisplay = 480,
2643 	.vsync_start = 480 + 38,
2644 	.vsync_end = 480 + 38 + 3,
2645 	.vtotal = 480 + 38 + 3 + 29,
2646 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2647 };
2648 
2649 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2650 	.modes = &logictechno_lttd800480070_l2rt_mode,
2651 	.num_modes = 1,
2652 	.bpc = 8,
2653 	.size = {
2654 		.width = 154,
2655 		.height = 86,
2656 	},
2657 	.delay = {
2658 		.prepare = 45,
2659 		.enable = 100,
2660 		.disable = 100,
2661 		.unprepare = 45
2662 	},
2663 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2664 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2665 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2666 };
2667 
2668 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2669 	.clock = 33000,
2670 	.hdisplay = 800,
2671 	.hsync_start = 800 + 154,
2672 	.hsync_end = 800 + 154 + 3,
2673 	.htotal = 800 + 154 + 3 + 43,
2674 	.vdisplay = 480,
2675 	.vsync_start = 480 + 47,
2676 	.vsync_end = 480 + 47 + 3,
2677 	.vtotal = 480 + 47 + 3 + 20,
2678 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2679 };
2680 
2681 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2682 	.modes = &logictechno_lttd800480070_l6wh_rt_mode,
2683 	.num_modes = 1,
2684 	.bpc = 8,
2685 	.size = {
2686 		.width = 154,
2687 		.height = 86,
2688 	},
2689 	.delay = {
2690 		.prepare = 45,
2691 		.enable = 100,
2692 		.disable = 100,
2693 		.unprepare = 45
2694 	},
2695 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2696 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2697 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2698 };
2699 
2700 static const struct drm_display_mode logicpd_type_28_mode = {
2701 	.clock = 9107,
2702 	.hdisplay = 480,
2703 	.hsync_start = 480 + 3,
2704 	.hsync_end = 480 + 3 + 42,
2705 	.htotal = 480 + 3 + 42 + 2,
2706 
2707 	.vdisplay = 272,
2708 	.vsync_start = 272 + 2,
2709 	.vsync_end = 272 + 2 + 11,
2710 	.vtotal = 272 + 2 + 11 + 3,
2711 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2712 };
2713 
2714 static const struct panel_desc logicpd_type_28 = {
2715 	.modes = &logicpd_type_28_mode,
2716 	.num_modes = 1,
2717 	.bpc = 8,
2718 	.size = {
2719 		.width = 105,
2720 		.height = 67,
2721 	},
2722 	.delay = {
2723 		.prepare = 200,
2724 		.enable = 200,
2725 		.unprepare = 200,
2726 		.disable = 200,
2727 	},
2728 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2729 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2730 		     DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2731 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2732 };
2733 
2734 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2735 	.clock = 30400,
2736 	.hdisplay = 800,
2737 	.hsync_start = 800 + 0,
2738 	.hsync_end = 800 + 1,
2739 	.htotal = 800 + 0 + 1 + 160,
2740 	.vdisplay = 480,
2741 	.vsync_start = 480 + 0,
2742 	.vsync_end = 480 + 48 + 1,
2743 	.vtotal = 480 + 48 + 1 + 0,
2744 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2745 };
2746 
2747 static const struct panel_desc mitsubishi_aa070mc01 = {
2748 	.modes = &mitsubishi_aa070mc01_mode,
2749 	.num_modes = 1,
2750 	.bpc = 8,
2751 	.size = {
2752 		.width = 152,
2753 		.height = 91,
2754 	},
2755 
2756 	.delay = {
2757 		.enable = 200,
2758 		.unprepare = 200,
2759 		.disable = 400,
2760 	},
2761 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2762 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2763 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2764 };
2765 
2766 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2767 	.pixelclock = { 29000000, 33000000, 38000000 },
2768 	.hactive = { 800, 800, 800 },
2769 	.hfront_porch = { 180, 210, 240 },
2770 	.hback_porch = { 16, 16, 16 },
2771 	.hsync_len = { 30, 30, 30 },
2772 	.vactive = { 480, 480, 480 },
2773 	.vfront_porch = { 12, 22, 32 },
2774 	.vback_porch = { 10, 10, 10 },
2775 	.vsync_len = { 13, 13, 13 },
2776 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2777 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2778 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2779 };
2780 
2781 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2782 	.timings = &multi_inno_mi0700s4t_6_timing,
2783 	.num_timings = 1,
2784 	.bpc = 8,
2785 	.size = {
2786 		.width = 154,
2787 		.height = 86,
2788 	},
2789 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2790 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2791 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2792 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2793 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2794 };
2795 
2796 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2797 	.pixelclock = { 32000000, 40000000, 50000000 },
2798 	.hactive = { 800, 800, 800 },
2799 	.hfront_porch = { 16, 210, 354 },
2800 	.hback_porch = { 6, 26, 45 },
2801 	.hsync_len = { 1, 20, 40 },
2802 	.vactive = { 600, 600, 600 },
2803 	.vfront_porch = { 1, 12, 77 },
2804 	.vback_porch = { 3, 13, 22 },
2805 	.vsync_len = { 1, 10, 20 },
2806 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2807 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2808 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2809 };
2810 
2811 static const struct panel_desc multi_inno_mi0800ft_9 = {
2812 	.timings = &multi_inno_mi0800ft_9_timing,
2813 	.num_timings = 1,
2814 	.bpc = 8,
2815 	.size = {
2816 		.width = 162,
2817 		.height = 122,
2818 	},
2819 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2820 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2821 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2822 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2823 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2824 };
2825 
2826 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2827 	.pixelclock = { 68900000, 70000000, 73400000 },
2828 	.hactive = { 1280, 1280, 1280 },
2829 	.hfront_porch = { 30, 60, 71 },
2830 	.hback_porch = { 30, 60, 71 },
2831 	.hsync_len = { 10, 10, 48 },
2832 	.vactive = { 800, 800, 800 },
2833 	.vfront_porch = { 5, 10, 10 },
2834 	.vback_porch = { 5, 10, 10 },
2835 	.vsync_len = { 5, 6, 13 },
2836 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2837 		 DISPLAY_FLAGS_DE_HIGH,
2838 };
2839 
2840 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2841 	.timings = &multi_inno_mi1010ait_1cp_timing,
2842 	.num_timings = 1,
2843 	.bpc = 8,
2844 	.size = {
2845 		.width = 217,
2846 		.height = 136,
2847 	},
2848 	.delay = {
2849 		.enable = 50,
2850 		.disable = 50,
2851 	},
2852 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2853 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2854 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2855 };
2856 
2857 static const struct display_timing nec_nl12880bc20_05_timing = {
2858 	.pixelclock = { 67000000, 71000000, 75000000 },
2859 	.hactive = { 1280, 1280, 1280 },
2860 	.hfront_porch = { 2, 30, 30 },
2861 	.hback_porch = { 6, 100, 100 },
2862 	.hsync_len = { 2, 30, 30 },
2863 	.vactive = { 800, 800, 800 },
2864 	.vfront_porch = { 5, 5, 5 },
2865 	.vback_porch = { 11, 11, 11 },
2866 	.vsync_len = { 7, 7, 7 },
2867 };
2868 
2869 static const struct panel_desc nec_nl12880bc20_05 = {
2870 	.timings = &nec_nl12880bc20_05_timing,
2871 	.num_timings = 1,
2872 	.bpc = 8,
2873 	.size = {
2874 		.width = 261,
2875 		.height = 163,
2876 	},
2877 	.delay = {
2878 		.enable = 50,
2879 		.disable = 50,
2880 	},
2881 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2882 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2883 };
2884 
2885 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2886 	.clock = 10870,
2887 	.hdisplay = 480,
2888 	.hsync_start = 480 + 2,
2889 	.hsync_end = 480 + 2 + 41,
2890 	.htotal = 480 + 2 + 41 + 2,
2891 	.vdisplay = 272,
2892 	.vsync_start = 272 + 2,
2893 	.vsync_end = 272 + 2 + 4,
2894 	.vtotal = 272 + 2 + 4 + 2,
2895 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2896 };
2897 
2898 static const struct panel_desc nec_nl4827hc19_05b = {
2899 	.modes = &nec_nl4827hc19_05b_mode,
2900 	.num_modes = 1,
2901 	.bpc = 8,
2902 	.size = {
2903 		.width = 95,
2904 		.height = 54,
2905 	},
2906 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2907 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2908 };
2909 
2910 static const struct drm_display_mode netron_dy_e231732_mode = {
2911 	.clock = 66000,
2912 	.hdisplay = 1024,
2913 	.hsync_start = 1024 + 160,
2914 	.hsync_end = 1024 + 160 + 70,
2915 	.htotal = 1024 + 160 + 70 + 90,
2916 	.vdisplay = 600,
2917 	.vsync_start = 600 + 127,
2918 	.vsync_end = 600 + 127 + 20,
2919 	.vtotal = 600 + 127 + 20 + 3,
2920 };
2921 
2922 static const struct panel_desc netron_dy_e231732 = {
2923 	.modes = &netron_dy_e231732_mode,
2924 	.num_modes = 1,
2925 	.size = {
2926 		.width = 154,
2927 		.height = 87,
2928 	},
2929 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2930 };
2931 
2932 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2933 	.clock = 9000,
2934 	.hdisplay = 480,
2935 	.hsync_start = 480 + 2,
2936 	.hsync_end = 480 + 2 + 41,
2937 	.htotal = 480 + 2 + 41 + 2,
2938 	.vdisplay = 272,
2939 	.vsync_start = 272 + 2,
2940 	.vsync_end = 272 + 2 + 10,
2941 	.vtotal = 272 + 2 + 10 + 2,
2942 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2943 };
2944 
2945 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2946 	.modes = &newhaven_nhd_43_480272ef_atxl_mode,
2947 	.num_modes = 1,
2948 	.bpc = 8,
2949 	.size = {
2950 		.width = 95,
2951 		.height = 54,
2952 	},
2953 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2954 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2955 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2956 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2957 };
2958 
2959 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2960 	.pixelclock = { 130000000, 148350000, 163000000 },
2961 	.hactive = { 1920, 1920, 1920 },
2962 	.hfront_porch = { 80, 100, 100 },
2963 	.hback_porch = { 100, 120, 120 },
2964 	.hsync_len = { 50, 60, 60 },
2965 	.vactive = { 1080, 1080, 1080 },
2966 	.vfront_porch = { 12, 30, 30 },
2967 	.vback_porch = { 4, 10, 10 },
2968 	.vsync_len = { 4, 5, 5 },
2969 };
2970 
2971 static const struct panel_desc nlt_nl192108ac18_02d = {
2972 	.timings = &nlt_nl192108ac18_02d_timing,
2973 	.num_timings = 1,
2974 	.bpc = 8,
2975 	.size = {
2976 		.width = 344,
2977 		.height = 194,
2978 	},
2979 	.delay = {
2980 		.unprepare = 500,
2981 	},
2982 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2983 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2984 };
2985 
2986 static const struct drm_display_mode nvd_9128_mode = {
2987 	.clock = 29500,
2988 	.hdisplay = 800,
2989 	.hsync_start = 800 + 130,
2990 	.hsync_end = 800 + 130 + 98,
2991 	.htotal = 800 + 0 + 130 + 98,
2992 	.vdisplay = 480,
2993 	.vsync_start = 480 + 10,
2994 	.vsync_end = 480 + 10 + 50,
2995 	.vtotal = 480 + 0 + 10 + 50,
2996 };
2997 
2998 static const struct panel_desc nvd_9128 = {
2999 	.modes = &nvd_9128_mode,
3000 	.num_modes = 1,
3001 	.bpc = 8,
3002 	.size = {
3003 		.width = 156,
3004 		.height = 88,
3005 	},
3006 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3007 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3008 };
3009 
3010 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3011 	.pixelclock = { 30000000, 30000000, 40000000 },
3012 	.hactive = { 800, 800, 800 },
3013 	.hfront_porch = { 40, 40, 40 },
3014 	.hback_porch = { 40, 40, 40 },
3015 	.hsync_len = { 1, 48, 48 },
3016 	.vactive = { 480, 480, 480 },
3017 	.vfront_porch = { 13, 13, 13 },
3018 	.vback_porch = { 29, 29, 29 },
3019 	.vsync_len = { 3, 3, 3 },
3020 	.flags = DISPLAY_FLAGS_DE_HIGH,
3021 };
3022 
3023 static const struct panel_desc okaya_rs800480t_7x0gp = {
3024 	.timings = &okaya_rs800480t_7x0gp_timing,
3025 	.num_timings = 1,
3026 	.bpc = 6,
3027 	.size = {
3028 		.width = 154,
3029 		.height = 87,
3030 	},
3031 	.delay = {
3032 		.prepare = 41,
3033 		.enable = 50,
3034 		.unprepare = 41,
3035 		.disable = 50,
3036 	},
3037 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3038 };
3039 
3040 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3041 	.clock = 9000,
3042 	.hdisplay = 480,
3043 	.hsync_start = 480 + 5,
3044 	.hsync_end = 480 + 5 + 30,
3045 	.htotal = 480 + 5 + 30 + 10,
3046 	.vdisplay = 272,
3047 	.vsync_start = 272 + 8,
3048 	.vsync_end = 272 + 8 + 5,
3049 	.vtotal = 272 + 8 + 5 + 3,
3050 };
3051 
3052 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3053 	.modes = &olimex_lcd_olinuxino_43ts_mode,
3054 	.num_modes = 1,
3055 	.size = {
3056 		.width = 95,
3057 		.height = 54,
3058 	},
3059 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3060 };
3061 
3062 /*
3063  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3064  * pixel clocks, but this is the timing that was being used in the Adafruit
3065  * installation instructions.
3066  */
3067 static const struct drm_display_mode ontat_yx700wv03_mode = {
3068 	.clock = 29500,
3069 	.hdisplay = 800,
3070 	.hsync_start = 824,
3071 	.hsync_end = 896,
3072 	.htotal = 992,
3073 	.vdisplay = 480,
3074 	.vsync_start = 483,
3075 	.vsync_end = 493,
3076 	.vtotal = 500,
3077 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3078 };
3079 
3080 /*
3081  * Specification at:
3082  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3083  */
3084 static const struct panel_desc ontat_yx700wv03 = {
3085 	.modes = &ontat_yx700wv03_mode,
3086 	.num_modes = 1,
3087 	.bpc = 8,
3088 	.size = {
3089 		.width = 154,
3090 		.height = 83,
3091 	},
3092 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3093 };
3094 
3095 static const struct drm_display_mode ortustech_com37h3m_mode  = {
3096 	.clock = 22230,
3097 	.hdisplay = 480,
3098 	.hsync_start = 480 + 40,
3099 	.hsync_end = 480 + 40 + 10,
3100 	.htotal = 480 + 40 + 10 + 40,
3101 	.vdisplay = 640,
3102 	.vsync_start = 640 + 4,
3103 	.vsync_end = 640 + 4 + 2,
3104 	.vtotal = 640 + 4 + 2 + 4,
3105 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3106 };
3107 
3108 static const struct panel_desc ortustech_com37h3m = {
3109 	.modes = &ortustech_com37h3m_mode,
3110 	.num_modes = 1,
3111 	.bpc = 8,
3112 	.size = {
3113 		.width = 56,	/* 56.16mm */
3114 		.height = 75,	/* 74.88mm */
3115 	},
3116 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3117 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3118 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3119 };
3120 
3121 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
3122 	.clock = 25000,
3123 	.hdisplay = 480,
3124 	.hsync_start = 480 + 10,
3125 	.hsync_end = 480 + 10 + 10,
3126 	.htotal = 480 + 10 + 10 + 15,
3127 	.vdisplay = 800,
3128 	.vsync_start = 800 + 3,
3129 	.vsync_end = 800 + 3 + 3,
3130 	.vtotal = 800 + 3 + 3 + 3,
3131 };
3132 
3133 static const struct panel_desc ortustech_com43h4m85ulc = {
3134 	.modes = &ortustech_com43h4m85ulc_mode,
3135 	.num_modes = 1,
3136 	.bpc = 6,
3137 	.size = {
3138 		.width = 56,
3139 		.height = 93,
3140 	},
3141 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3142 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3143 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3144 };
3145 
3146 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
3147 	.clock = 33000,
3148 	.hdisplay = 800,
3149 	.hsync_start = 800 + 210,
3150 	.hsync_end = 800 + 210 + 30,
3151 	.htotal = 800 + 210 + 30 + 16,
3152 	.vdisplay = 480,
3153 	.vsync_start = 480 + 22,
3154 	.vsync_end = 480 + 22 + 13,
3155 	.vtotal = 480 + 22 + 13 + 10,
3156 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3157 };
3158 
3159 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3160 	.modes = &osddisplays_osd070t1718_19ts_mode,
3161 	.num_modes = 1,
3162 	.bpc = 8,
3163 	.size = {
3164 		.width = 152,
3165 		.height = 91,
3166 	},
3167 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3168 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3169 		DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3170 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3171 };
3172 
3173 static const struct drm_display_mode pda_91_00156_a0_mode = {
3174 	.clock = 33300,
3175 	.hdisplay = 800,
3176 	.hsync_start = 800 + 1,
3177 	.hsync_end = 800 + 1 + 64,
3178 	.htotal = 800 + 1 + 64 + 64,
3179 	.vdisplay = 480,
3180 	.vsync_start = 480 + 1,
3181 	.vsync_end = 480 + 1 + 23,
3182 	.vtotal = 480 + 1 + 23 + 22,
3183 };
3184 
3185 static const struct panel_desc pda_91_00156_a0  = {
3186 	.modes = &pda_91_00156_a0_mode,
3187 	.num_modes = 1,
3188 	.size = {
3189 		.width = 152,
3190 		.height = 91,
3191 	},
3192 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3193 };
3194 
3195 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3196 	.clock = 24750,
3197 	.hdisplay = 800,
3198 	.hsync_start = 800 + 54,
3199 	.hsync_end = 800 + 54 + 2,
3200 	.htotal = 800 + 54 + 2 + 44,
3201 	.vdisplay = 480,
3202 	.vsync_start = 480 + 49,
3203 	.vsync_end = 480 + 49 + 2,
3204 	.vtotal = 480 + 49 + 2 + 22,
3205 };
3206 
3207 static const struct panel_desc powertip_ph800480t013_idf02  = {
3208 	.modes = &powertip_ph800480t013_idf02_mode,
3209 	.num_modes = 1,
3210 	.size = {
3211 		.width = 152,
3212 		.height = 91,
3213 	},
3214 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
3215 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3216 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3217 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3218 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3219 };
3220 
3221 static const struct drm_display_mode qd43003c0_40_mode = {
3222 	.clock = 9000,
3223 	.hdisplay = 480,
3224 	.hsync_start = 480 + 8,
3225 	.hsync_end = 480 + 8 + 4,
3226 	.htotal = 480 + 8 + 4 + 39,
3227 	.vdisplay = 272,
3228 	.vsync_start = 272 + 4,
3229 	.vsync_end = 272 + 4 + 10,
3230 	.vtotal = 272 + 4 + 10 + 2,
3231 };
3232 
3233 static const struct panel_desc qd43003c0_40 = {
3234 	.modes = &qd43003c0_40_mode,
3235 	.num_modes = 1,
3236 	.bpc = 8,
3237 	.size = {
3238 		.width = 95,
3239 		.height = 53,
3240 	},
3241 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3242 };
3243 
3244 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3245 	{ /* 60 Hz */
3246 		.clock = 10800,
3247 		.hdisplay = 480,
3248 		.hsync_start = 480 + 77,
3249 		.hsync_end = 480 + 77 + 41,
3250 		.htotal = 480 + 77 + 41 + 2,
3251 		.vdisplay = 272,
3252 		.vsync_start = 272 + 16,
3253 		.vsync_end = 272 + 16 + 10,
3254 		.vtotal = 272 + 16 + 10 + 2,
3255 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3256 	},
3257 	{ /* 50 Hz */
3258 		.clock = 10800,
3259 		.hdisplay = 480,
3260 		.hsync_start = 480 + 17,
3261 		.hsync_end = 480 + 17 + 41,
3262 		.htotal = 480 + 17 + 41 + 2,
3263 		.vdisplay = 272,
3264 		.vsync_start = 272 + 116,
3265 		.vsync_end = 272 + 116 + 10,
3266 		.vtotal = 272 + 116 + 10 + 2,
3267 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3268 	},
3269 };
3270 
3271 static const struct panel_desc qishenglong_gopher2b_lcd = {
3272 	.modes = qishenglong_gopher2b_lcd_modes,
3273 	.num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3274 	.bpc = 8,
3275 	.size = {
3276 		.width = 95,
3277 		.height = 54,
3278 	},
3279 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3280 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3281 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3282 };
3283 
3284 static const struct display_timing rocktech_rk070er9427_timing = {
3285 	.pixelclock = { 26400000, 33300000, 46800000 },
3286 	.hactive = { 800, 800, 800 },
3287 	.hfront_porch = { 16, 210, 354 },
3288 	.hback_porch = { 46, 46, 46 },
3289 	.hsync_len = { 1, 1, 1 },
3290 	.vactive = { 480, 480, 480 },
3291 	.vfront_porch = { 7, 22, 147 },
3292 	.vback_porch = { 23, 23, 23 },
3293 	.vsync_len = { 1, 1, 1 },
3294 	.flags = DISPLAY_FLAGS_DE_HIGH,
3295 };
3296 
3297 static const struct panel_desc rocktech_rk070er9427 = {
3298 	.timings = &rocktech_rk070er9427_timing,
3299 	.num_timings = 1,
3300 	.bpc = 6,
3301 	.size = {
3302 		.width = 154,
3303 		.height = 86,
3304 	},
3305 	.delay = {
3306 		.prepare = 41,
3307 		.enable = 50,
3308 		.unprepare = 41,
3309 		.disable = 50,
3310 	},
3311 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3312 };
3313 
3314 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3315 	.clock = 71100,
3316 	.hdisplay = 1280,
3317 	.hsync_start = 1280 + 48,
3318 	.hsync_end = 1280 + 48 + 32,
3319 	.htotal = 1280 + 48 + 32 + 80,
3320 	.vdisplay = 800,
3321 	.vsync_start = 800 + 2,
3322 	.vsync_end = 800 + 2 + 5,
3323 	.vtotal = 800 + 2 + 5 + 16,
3324 };
3325 
3326 static const struct panel_desc rocktech_rk101ii01d_ct = {
3327 	.modes = &rocktech_rk101ii01d_ct_mode,
3328 	.bpc = 8,
3329 	.num_modes = 1,
3330 	.size = {
3331 		.width = 217,
3332 		.height = 136,
3333 	},
3334 	.delay = {
3335 		.prepare = 50,
3336 		.disable = 50,
3337 	},
3338 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3339 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3340 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3341 };
3342 
3343 static const struct display_timing samsung_ltl101al01_timing = {
3344 	.pixelclock = { 66663000, 66663000, 66663000 },
3345 	.hactive = { 1280, 1280, 1280 },
3346 	.hfront_porch = { 18, 18, 18 },
3347 	.hback_porch = { 36, 36, 36 },
3348 	.hsync_len = { 16, 16, 16 },
3349 	.vactive = { 800, 800, 800 },
3350 	.vfront_porch = { 4, 4, 4 },
3351 	.vback_porch = { 16, 16, 16 },
3352 	.vsync_len = { 3, 3, 3 },
3353 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3354 };
3355 
3356 static const struct panel_desc samsung_ltl101al01 = {
3357 	.timings = &samsung_ltl101al01_timing,
3358 	.num_timings = 1,
3359 	.bpc = 8,
3360 	.size = {
3361 		.width = 217,
3362 		.height = 135,
3363 	},
3364 	.delay = {
3365 		.prepare = 40,
3366 		.enable = 300,
3367 		.disable = 200,
3368 		.unprepare = 600,
3369 	},
3370 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3371 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3372 };
3373 
3374 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3375 	.clock = 54030,
3376 	.hdisplay = 1024,
3377 	.hsync_start = 1024 + 24,
3378 	.hsync_end = 1024 + 24 + 136,
3379 	.htotal = 1024 + 24 + 136 + 160,
3380 	.vdisplay = 600,
3381 	.vsync_start = 600 + 3,
3382 	.vsync_end = 600 + 3 + 6,
3383 	.vtotal = 600 + 3 + 6 + 61,
3384 };
3385 
3386 static const struct panel_desc samsung_ltn101nt05 = {
3387 	.modes = &samsung_ltn101nt05_mode,
3388 	.num_modes = 1,
3389 	.bpc = 6,
3390 	.size = {
3391 		.width = 223,
3392 		.height = 125,
3393 	},
3394 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3395 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3396 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3397 };
3398 
3399 static const struct display_timing satoz_sat050at40h12r2_timing = {
3400 	.pixelclock = {33300000, 33300000, 50000000},
3401 	.hactive = {800, 800, 800},
3402 	.hfront_porch = {16, 210, 354},
3403 	.hback_porch = {46, 46, 46},
3404 	.hsync_len = {1, 1, 40},
3405 	.vactive = {480, 480, 480},
3406 	.vfront_porch = {7, 22, 147},
3407 	.vback_porch = {23, 23, 23},
3408 	.vsync_len = {1, 1, 20},
3409 };
3410 
3411 static const struct panel_desc satoz_sat050at40h12r2 = {
3412 	.timings = &satoz_sat050at40h12r2_timing,
3413 	.num_timings = 1,
3414 	.bpc = 8,
3415 	.size = {
3416 		.width = 108,
3417 		.height = 65,
3418 	},
3419 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3420 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3421 };
3422 
3423 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3424 	.clock = 33260,
3425 	.hdisplay = 800,
3426 	.hsync_start = 800 + 64,
3427 	.hsync_end = 800 + 64 + 128,
3428 	.htotal = 800 + 64 + 128 + 64,
3429 	.vdisplay = 480,
3430 	.vsync_start = 480 + 8,
3431 	.vsync_end = 480 + 8 + 2,
3432 	.vtotal = 480 + 8 + 2 + 35,
3433 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3434 };
3435 
3436 static const struct panel_desc sharp_lq070y3dg3b = {
3437 	.modes = &sharp_lq070y3dg3b_mode,
3438 	.num_modes = 1,
3439 	.bpc = 8,
3440 	.size = {
3441 		.width = 152,	/* 152.4mm */
3442 		.height = 91,	/* 91.4mm */
3443 	},
3444 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3445 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3446 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3447 };
3448 
3449 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3450 	.clock = 5500,
3451 	.hdisplay = 240,
3452 	.hsync_start = 240 + 16,
3453 	.hsync_end = 240 + 16 + 7,
3454 	.htotal = 240 + 16 + 7 + 5,
3455 	.vdisplay = 320,
3456 	.vsync_start = 320 + 9,
3457 	.vsync_end = 320 + 9 + 1,
3458 	.vtotal = 320 + 9 + 1 + 7,
3459 };
3460 
3461 static const struct panel_desc sharp_lq035q7db03 = {
3462 	.modes = &sharp_lq035q7db03_mode,
3463 	.num_modes = 1,
3464 	.bpc = 6,
3465 	.size = {
3466 		.width = 54,
3467 		.height = 72,
3468 	},
3469 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3470 };
3471 
3472 static const struct display_timing sharp_lq101k1ly04_timing = {
3473 	.pixelclock = { 60000000, 65000000, 80000000 },
3474 	.hactive = { 1280, 1280, 1280 },
3475 	.hfront_porch = { 20, 20, 20 },
3476 	.hback_porch = { 20, 20, 20 },
3477 	.hsync_len = { 10, 10, 10 },
3478 	.vactive = { 800, 800, 800 },
3479 	.vfront_porch = { 4, 4, 4 },
3480 	.vback_porch = { 4, 4, 4 },
3481 	.vsync_len = { 4, 4, 4 },
3482 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3483 };
3484 
3485 static const struct panel_desc sharp_lq101k1ly04 = {
3486 	.timings = &sharp_lq101k1ly04_timing,
3487 	.num_timings = 1,
3488 	.bpc = 8,
3489 	.size = {
3490 		.width = 217,
3491 		.height = 136,
3492 	},
3493 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3494 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3495 };
3496 
3497 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3498 	{ /* 50 Hz */
3499 		.clock = 3000,
3500 		.hdisplay = 240,
3501 		.hsync_start = 240 + 58,
3502 		.hsync_end = 240 + 58 + 1,
3503 		.htotal = 240 + 58 + 1 + 1,
3504 		.vdisplay = 160,
3505 		.vsync_start = 160 + 24,
3506 		.vsync_end = 160 + 24 + 10,
3507 		.vtotal = 160 + 24 + 10 + 6,
3508 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3509 	},
3510 	{ /* 60 Hz */
3511 		.clock = 3000,
3512 		.hdisplay = 240,
3513 		.hsync_start = 240 + 8,
3514 		.hsync_end = 240 + 8 + 1,
3515 		.htotal = 240 + 8 + 1 + 1,
3516 		.vdisplay = 160,
3517 		.vsync_start = 160 + 24,
3518 		.vsync_end = 160 + 24 + 10,
3519 		.vtotal = 160 + 24 + 10 + 6,
3520 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3521 	},
3522 };
3523 
3524 static const struct panel_desc sharp_ls020b1dd01d = {
3525 	.modes = sharp_ls020b1dd01d_modes,
3526 	.num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3527 	.bpc = 6,
3528 	.size = {
3529 		.width = 42,
3530 		.height = 28,
3531 	},
3532 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3533 	.bus_flags = DRM_BUS_FLAG_DE_HIGH
3534 		   | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3535 		   | DRM_BUS_FLAG_SHARP_SIGNALS,
3536 };
3537 
3538 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3539 	.clock = 33300,
3540 	.hdisplay = 800,
3541 	.hsync_start = 800 + 1,
3542 	.hsync_end = 800 + 1 + 64,
3543 	.htotal = 800 + 1 + 64 + 64,
3544 	.vdisplay = 480,
3545 	.vsync_start = 480 + 1,
3546 	.vsync_end = 480 + 1 + 23,
3547 	.vtotal = 480 + 1 + 23 + 22,
3548 };
3549 
3550 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3551 	.modes = &shelly_sca07010_bfn_lnn_mode,
3552 	.num_modes = 1,
3553 	.size = {
3554 		.width = 152,
3555 		.height = 91,
3556 	},
3557 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3558 };
3559 
3560 static const struct drm_display_mode starry_kr070pe2t_mode = {
3561 	.clock = 33000,
3562 	.hdisplay = 800,
3563 	.hsync_start = 800 + 209,
3564 	.hsync_end = 800 + 209 + 1,
3565 	.htotal = 800 + 209 + 1 + 45,
3566 	.vdisplay = 480,
3567 	.vsync_start = 480 + 22,
3568 	.vsync_end = 480 + 22 + 1,
3569 	.vtotal = 480 + 22 + 1 + 22,
3570 };
3571 
3572 static const struct panel_desc starry_kr070pe2t = {
3573 	.modes = &starry_kr070pe2t_mode,
3574 	.num_modes = 1,
3575 	.bpc = 8,
3576 	.size = {
3577 		.width = 152,
3578 		.height = 86,
3579 	},
3580 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3581 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3582 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3583 };
3584 
3585 static const struct display_timing startek_kd070wvfpa_mode = {
3586 	.pixelclock = { 25200000, 27200000, 30500000 },
3587 	.hactive = { 800, 800, 800 },
3588 	.hfront_porch = { 19, 44, 115 },
3589 	.hback_porch = { 5, 16, 101 },
3590 	.hsync_len = { 1, 2, 100 },
3591 	.vactive = { 480, 480, 480 },
3592 	.vfront_porch = { 5, 43, 67 },
3593 	.vback_porch = { 5, 5, 67 },
3594 	.vsync_len = { 1, 2, 66 },
3595 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3596 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3597 		 DISPLAY_FLAGS_SYNC_POSEDGE,
3598 };
3599 
3600 static const struct panel_desc startek_kd070wvfpa = {
3601 	.timings = &startek_kd070wvfpa_mode,
3602 	.num_timings = 1,
3603 	.bpc = 8,
3604 	.size = {
3605 		.width = 152,
3606 		.height = 91,
3607 	},
3608 	.delay = {
3609 		.prepare = 20,
3610 		.enable = 200,
3611 		.disable = 200,
3612 	},
3613 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3614 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3615 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
3616 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3617 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3618 };
3619 
3620 static const struct display_timing tsd_tst043015cmhx_timing = {
3621 	.pixelclock = { 5000000, 9000000, 12000000 },
3622 	.hactive = { 480, 480, 480 },
3623 	.hfront_porch = { 4, 5, 65 },
3624 	.hback_porch = { 36, 40, 255 },
3625 	.hsync_len = { 1, 1, 1 },
3626 	.vactive = { 272, 272, 272 },
3627 	.vfront_porch = { 2, 8, 97 },
3628 	.vback_porch = { 3, 8, 31 },
3629 	.vsync_len = { 1, 1, 1 },
3630 
3631 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3632 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3633 };
3634 
3635 static const struct panel_desc tsd_tst043015cmhx = {
3636 	.timings = &tsd_tst043015cmhx_timing,
3637 	.num_timings = 1,
3638 	.bpc = 8,
3639 	.size = {
3640 		.width = 105,
3641 		.height = 67,
3642 	},
3643 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3644 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3645 };
3646 
3647 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3648 	.clock = 30000,
3649 	.hdisplay = 800,
3650 	.hsync_start = 800 + 39,
3651 	.hsync_end = 800 + 39 + 47,
3652 	.htotal = 800 + 39 + 47 + 39,
3653 	.vdisplay = 480,
3654 	.vsync_start = 480 + 13,
3655 	.vsync_end = 480 + 13 + 2,
3656 	.vtotal = 480 + 13 + 2 + 29,
3657 };
3658 
3659 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3660 	.modes = &tfc_s9700rtwv43tr_01b_mode,
3661 	.num_modes = 1,
3662 	.bpc = 8,
3663 	.size = {
3664 		.width = 155,
3665 		.height = 90,
3666 	},
3667 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3668 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3669 };
3670 
3671 static const struct display_timing tianma_tm070jdhg30_timing = {
3672 	.pixelclock = { 62600000, 68200000, 78100000 },
3673 	.hactive = { 1280, 1280, 1280 },
3674 	.hfront_porch = { 15, 64, 159 },
3675 	.hback_porch = { 5, 5, 5 },
3676 	.hsync_len = { 1, 1, 256 },
3677 	.vactive = { 800, 800, 800 },
3678 	.vfront_porch = { 3, 40, 99 },
3679 	.vback_porch = { 2, 2, 2 },
3680 	.vsync_len = { 1, 1, 128 },
3681 	.flags = DISPLAY_FLAGS_DE_HIGH,
3682 };
3683 
3684 static const struct panel_desc tianma_tm070jdhg30 = {
3685 	.timings = &tianma_tm070jdhg30_timing,
3686 	.num_timings = 1,
3687 	.bpc = 8,
3688 	.size = {
3689 		.width = 151,
3690 		.height = 95,
3691 	},
3692 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3693 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3694 };
3695 
3696 static const struct panel_desc tianma_tm070jvhg33 = {
3697 	.timings = &tianma_tm070jdhg30_timing,
3698 	.num_timings = 1,
3699 	.bpc = 8,
3700 	.size = {
3701 		.width = 150,
3702 		.height = 94,
3703 	},
3704 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3705 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3706 };
3707 
3708 static const struct display_timing tianma_tm070rvhg71_timing = {
3709 	.pixelclock = { 27700000, 29200000, 39600000 },
3710 	.hactive = { 800, 800, 800 },
3711 	.hfront_porch = { 12, 40, 212 },
3712 	.hback_porch = { 88, 88, 88 },
3713 	.hsync_len = { 1, 1, 40 },
3714 	.vactive = { 480, 480, 480 },
3715 	.vfront_porch = { 1, 13, 88 },
3716 	.vback_porch = { 32, 32, 32 },
3717 	.vsync_len = { 1, 1, 3 },
3718 	.flags = DISPLAY_FLAGS_DE_HIGH,
3719 };
3720 
3721 static const struct panel_desc tianma_tm070rvhg71 = {
3722 	.timings = &tianma_tm070rvhg71_timing,
3723 	.num_timings = 1,
3724 	.bpc = 8,
3725 	.size = {
3726 		.width = 154,
3727 		.height = 86,
3728 	},
3729 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3730 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3731 };
3732 
3733 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3734 	{
3735 		.clock = 10000,
3736 		.hdisplay = 320,
3737 		.hsync_start = 320 + 50,
3738 		.hsync_end = 320 + 50 + 6,
3739 		.htotal = 320 + 50 + 6 + 38,
3740 		.vdisplay = 240,
3741 		.vsync_start = 240 + 3,
3742 		.vsync_end = 240 + 3 + 1,
3743 		.vtotal = 240 + 3 + 1 + 17,
3744 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3745 	},
3746 };
3747 
3748 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3749 	.modes = ti_nspire_cx_lcd_mode,
3750 	.num_modes = 1,
3751 	.bpc = 8,
3752 	.size = {
3753 		.width = 65,
3754 		.height = 49,
3755 	},
3756 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3757 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3758 };
3759 
3760 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3761 	{
3762 		.clock = 10000,
3763 		.hdisplay = 320,
3764 		.hsync_start = 320 + 6,
3765 		.hsync_end = 320 + 6 + 6,
3766 		.htotal = 320 + 6 + 6 + 6,
3767 		.vdisplay = 240,
3768 		.vsync_start = 240 + 0,
3769 		.vsync_end = 240 + 0 + 1,
3770 		.vtotal = 240 + 0 + 1 + 0,
3771 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3772 	},
3773 };
3774 
3775 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3776 	.modes = ti_nspire_classic_lcd_mode,
3777 	.num_modes = 1,
3778 	/* The grayscale panel has 8 bit for the color .. Y (black) */
3779 	.bpc = 8,
3780 	.size = {
3781 		.width = 71,
3782 		.height = 53,
3783 	},
3784 	/* This is the grayscale bus format */
3785 	.bus_format = MEDIA_BUS_FMT_Y8_1X8,
3786 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3787 };
3788 
3789 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3790 	.clock = 79500,
3791 	.hdisplay = 1280,
3792 	.hsync_start = 1280 + 192,
3793 	.hsync_end = 1280 + 192 + 128,
3794 	.htotal = 1280 + 192 + 128 + 64,
3795 	.vdisplay = 768,
3796 	.vsync_start = 768 + 20,
3797 	.vsync_end = 768 + 20 + 7,
3798 	.vtotal = 768 + 20 + 7 + 3,
3799 };
3800 
3801 static const struct panel_desc toshiba_lt089ac29000 = {
3802 	.modes = &toshiba_lt089ac29000_mode,
3803 	.num_modes = 1,
3804 	.size = {
3805 		.width = 194,
3806 		.height = 116,
3807 	},
3808 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3809 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3810 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3811 };
3812 
3813 static const struct drm_display_mode tpk_f07a_0102_mode = {
3814 	.clock = 33260,
3815 	.hdisplay = 800,
3816 	.hsync_start = 800 + 40,
3817 	.hsync_end = 800 + 40 + 128,
3818 	.htotal = 800 + 40 + 128 + 88,
3819 	.vdisplay = 480,
3820 	.vsync_start = 480 + 10,
3821 	.vsync_end = 480 + 10 + 2,
3822 	.vtotal = 480 + 10 + 2 + 33,
3823 };
3824 
3825 static const struct panel_desc tpk_f07a_0102 = {
3826 	.modes = &tpk_f07a_0102_mode,
3827 	.num_modes = 1,
3828 	.size = {
3829 		.width = 152,
3830 		.height = 91,
3831 	},
3832 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3833 };
3834 
3835 static const struct drm_display_mode tpk_f10a_0102_mode = {
3836 	.clock = 45000,
3837 	.hdisplay = 1024,
3838 	.hsync_start = 1024 + 176,
3839 	.hsync_end = 1024 + 176 + 5,
3840 	.htotal = 1024 + 176 + 5 + 88,
3841 	.vdisplay = 600,
3842 	.vsync_start = 600 + 20,
3843 	.vsync_end = 600 + 20 + 5,
3844 	.vtotal = 600 + 20 + 5 + 25,
3845 };
3846 
3847 static const struct panel_desc tpk_f10a_0102 = {
3848 	.modes = &tpk_f10a_0102_mode,
3849 	.num_modes = 1,
3850 	.size = {
3851 		.width = 223,
3852 		.height = 125,
3853 	},
3854 };
3855 
3856 static const struct display_timing urt_umsh_8596md_timing = {
3857 	.pixelclock = { 33260000, 33260000, 33260000 },
3858 	.hactive = { 800, 800, 800 },
3859 	.hfront_porch = { 41, 41, 41 },
3860 	.hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3861 	.hsync_len = { 71, 128, 128 },
3862 	.vactive = { 480, 480, 480 },
3863 	.vfront_porch = { 10, 10, 10 },
3864 	.vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3865 	.vsync_len = { 2, 2, 2 },
3866 	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3867 		DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3868 };
3869 
3870 static const struct panel_desc urt_umsh_8596md_lvds = {
3871 	.timings = &urt_umsh_8596md_timing,
3872 	.num_timings = 1,
3873 	.bpc = 6,
3874 	.size = {
3875 		.width = 152,
3876 		.height = 91,
3877 	},
3878 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3879 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3880 };
3881 
3882 static const struct panel_desc urt_umsh_8596md_parallel = {
3883 	.timings = &urt_umsh_8596md_timing,
3884 	.num_timings = 1,
3885 	.bpc = 6,
3886 	.size = {
3887 		.width = 152,
3888 		.height = 91,
3889 	},
3890 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3891 };
3892 
3893 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3894 	.clock = 60000,
3895 	.hdisplay = 1024,
3896 	.hsync_start = 1024 + 160,
3897 	.hsync_end = 1024 + 160 + 100,
3898 	.htotal = 1024 + 160 + 100 + 60,
3899 	.vdisplay = 600,
3900 	.vsync_start = 600 + 12,
3901 	.vsync_end = 600 + 12 + 10,
3902 	.vtotal = 600 + 12 + 10 + 13,
3903 };
3904 
3905 static const struct panel_desc vivax_tpc9150_panel = {
3906 	.modes = &vivax_tpc9150_panel_mode,
3907 	.num_modes = 1,
3908 	.bpc = 6,
3909 	.size = {
3910 		.width = 200,
3911 		.height = 115,
3912 	},
3913 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3914 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3915 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3916 };
3917 
3918 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3919 	.clock = 33333,
3920 	.hdisplay = 800,
3921 	.hsync_start = 800 + 210,
3922 	.hsync_end = 800 + 210 + 20,
3923 	.htotal = 800 + 210 + 20 + 46,
3924 	.vdisplay =  480,
3925 	.vsync_start = 480 + 22,
3926 	.vsync_end = 480 + 22 + 10,
3927 	.vtotal = 480 + 22 + 10 + 23,
3928 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3929 };
3930 
3931 static const struct panel_desc vl050_8048nt_c01 = {
3932 	.modes = &vl050_8048nt_c01_mode,
3933 	.num_modes = 1,
3934 	.bpc = 8,
3935 	.size = {
3936 		.width = 120,
3937 		.height = 76,
3938 	},
3939 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3940 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3941 };
3942 
3943 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3944 	.clock = 6410,
3945 	.hdisplay = 320,
3946 	.hsync_start = 320 + 20,
3947 	.hsync_end = 320 + 20 + 30,
3948 	.htotal = 320 + 20 + 30 + 38,
3949 	.vdisplay = 240,
3950 	.vsync_start = 240 + 4,
3951 	.vsync_end = 240 + 4 + 3,
3952 	.vtotal = 240 + 4 + 3 + 15,
3953 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3954 };
3955 
3956 static const struct panel_desc winstar_wf35ltiacd = {
3957 	.modes = &winstar_wf35ltiacd_mode,
3958 	.num_modes = 1,
3959 	.bpc = 8,
3960 	.size = {
3961 		.width = 70,
3962 		.height = 53,
3963 	},
3964 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3965 };
3966 
3967 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3968 	.clock = 51200,
3969 	.hdisplay = 1024,
3970 	.hsync_start = 1024 + 100,
3971 	.hsync_end = 1024 + 100 + 100,
3972 	.htotal = 1024 + 100 + 100 + 120,
3973 	.vdisplay = 600,
3974 	.vsync_start = 600 + 10,
3975 	.vsync_end = 600 + 10 + 10,
3976 	.vtotal = 600 + 10 + 10 + 15,
3977 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3978 };
3979 
3980 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3981 	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3982 	.num_modes = 1,
3983 	.bpc = 8,
3984 	.size = {
3985 		.width = 154,
3986 		.height = 90,
3987 	},
3988 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3989 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3990 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3991 };
3992 
3993 static const struct drm_display_mode arm_rtsm_mode[] = {
3994 	{
3995 		.clock = 65000,
3996 		.hdisplay = 1024,
3997 		.hsync_start = 1024 + 24,
3998 		.hsync_end = 1024 + 24 + 136,
3999 		.htotal = 1024 + 24 + 136 + 160,
4000 		.vdisplay = 768,
4001 		.vsync_start = 768 + 3,
4002 		.vsync_end = 768 + 3 + 6,
4003 		.vtotal = 768 + 3 + 6 + 29,
4004 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4005 	},
4006 };
4007 
4008 static const struct panel_desc arm_rtsm = {
4009 	.modes = arm_rtsm_mode,
4010 	.num_modes = 1,
4011 	.bpc = 8,
4012 	.size = {
4013 		.width = 400,
4014 		.height = 300,
4015 	},
4016 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4017 };
4018 
4019 static const struct of_device_id platform_of_match[] = {
4020 	{
4021 		.compatible = "ampire,am-1280800n3tzqw-t00h",
4022 		.data = &ampire_am_1280800n3tzqw_t00h,
4023 	}, {
4024 		.compatible = "ampire,am-480272h3tmqw-t01h",
4025 		.data = &ampire_am_480272h3tmqw_t01h,
4026 	}, {
4027 		.compatible = "ampire,am-800480l1tmqw-t00h",
4028 		.data = &ampire_am_800480l1tmqw_t00h,
4029 	}, {
4030 		.compatible = "ampire,am800480r3tmqwa1h",
4031 		.data = &ampire_am800480r3tmqwa1h,
4032 	}, {
4033 		.compatible = "ampire,am800600p5tmqw-tb8h",
4034 		.data = &ampire_am800600p5tmqwtb8h,
4035 	}, {
4036 		.compatible = "arm,rtsm-display",
4037 		.data = &arm_rtsm,
4038 	}, {
4039 		.compatible = "armadeus,st0700-adapt",
4040 		.data = &armadeus_st0700_adapt,
4041 	}, {
4042 		.compatible = "auo,b101aw03",
4043 		.data = &auo_b101aw03,
4044 	}, {
4045 		.compatible = "auo,b101xtn01",
4046 		.data = &auo_b101xtn01,
4047 	}, {
4048 		.compatible = "auo,g070vvn01",
4049 		.data = &auo_g070vvn01,
4050 	}, {
4051 		.compatible = "auo,g101evn010",
4052 		.data = &auo_g101evn010,
4053 	}, {
4054 		.compatible = "auo,g104sn02",
4055 		.data = &auo_g104sn02,
4056 	}, {
4057 		.compatible = "auo,g121ean01",
4058 		.data = &auo_g121ean01,
4059 	}, {
4060 		.compatible = "auo,g133han01",
4061 		.data = &auo_g133han01,
4062 	}, {
4063 		.compatible = "auo,g156xtn01",
4064 		.data = &auo_g156xtn01,
4065 	}, {
4066 		.compatible = "auo,g185han01",
4067 		.data = &auo_g185han01,
4068 	}, {
4069 		.compatible = "auo,g190ean01",
4070 		.data = &auo_g190ean01,
4071 	}, {
4072 		.compatible = "auo,p320hvn03",
4073 		.data = &auo_p320hvn03,
4074 	}, {
4075 		.compatible = "auo,t215hvn01",
4076 		.data = &auo_t215hvn01,
4077 	}, {
4078 		.compatible = "avic,tm070ddh03",
4079 		.data = &avic_tm070ddh03,
4080 	}, {
4081 		.compatible = "bananapi,s070wv20-ct16",
4082 		.data = &bananapi_s070wv20_ct16,
4083 	}, {
4084 		.compatible = "boe,ev121wxm-n10-1850",
4085 		.data = &boe_ev121wxm_n10_1850,
4086 	}, {
4087 		.compatible = "boe,hv070wsa-100",
4088 		.data = &boe_hv070wsa
4089 	}, {
4090 		.compatible = "cdtech,s043wq26h-ct7",
4091 		.data = &cdtech_s043wq26h_ct7,
4092 	}, {
4093 		.compatible = "cdtech,s070pws19hp-fc21",
4094 		.data = &cdtech_s070pws19hp_fc21,
4095 	}, {
4096 		.compatible = "cdtech,s070swv29hg-dc44",
4097 		.data = &cdtech_s070swv29hg_dc44,
4098 	}, {
4099 		.compatible = "cdtech,s070wv95-ct16",
4100 		.data = &cdtech_s070wv95_ct16,
4101 	}, {
4102 		.compatible = "chefree,ch101olhlwh-002",
4103 		.data = &chefree_ch101olhlwh_002,
4104 	}, {
4105 		.compatible = "chunghwa,claa070wp03xg",
4106 		.data = &chunghwa_claa070wp03xg,
4107 	}, {
4108 		.compatible = "chunghwa,claa101wa01a",
4109 		.data = &chunghwa_claa101wa01a
4110 	}, {
4111 		.compatible = "chunghwa,claa101wb01",
4112 		.data = &chunghwa_claa101wb01
4113 	}, {
4114 		.compatible = "dataimage,fg040346dsswbg04",
4115 		.data = &dataimage_fg040346dsswbg04,
4116 	}, {
4117 		.compatible = "dataimage,fg1001l0dsswmg01",
4118 		.data = &dataimage_fg1001l0dsswmg01,
4119 	}, {
4120 		.compatible = "dataimage,scf0700c48ggu18",
4121 		.data = &dataimage_scf0700c48ggu18,
4122 	}, {
4123 		.compatible = "dlc,dlc0700yzg-1",
4124 		.data = &dlc_dlc0700yzg_1,
4125 	}, {
4126 		.compatible = "dlc,dlc1010gig",
4127 		.data = &dlc_dlc1010gig,
4128 	}, {
4129 		.compatible = "edt,et035012dm6",
4130 		.data = &edt_et035012dm6,
4131 	}, {
4132 		.compatible = "edt,etm0350g0dh6",
4133 		.data = &edt_etm0350g0dh6,
4134 	}, {
4135 		.compatible = "edt,etm043080dh6gp",
4136 		.data = &edt_etm043080dh6gp,
4137 	}, {
4138 		.compatible = "edt,etm0430g0dh6",
4139 		.data = &edt_etm0430g0dh6,
4140 	}, {
4141 		.compatible = "edt,et057090dhu",
4142 		.data = &edt_et057090dhu,
4143 	}, {
4144 		.compatible = "edt,et070080dh6",
4145 		.data = &edt_etm0700g0dh6,
4146 	}, {
4147 		.compatible = "edt,etm0700g0dh6",
4148 		.data = &edt_etm0700g0dh6,
4149 	}, {
4150 		.compatible = "edt,etm0700g0bdh6",
4151 		.data = &edt_etm0700g0bdh6,
4152 	}, {
4153 		.compatible = "edt,etm0700g0edh6",
4154 		.data = &edt_etm0700g0bdh6,
4155 	}, {
4156 		.compatible = "edt,etml0700y5dha",
4157 		.data = &edt_etml0700y5dha,
4158 	}, {
4159 		.compatible = "edt,etmv570g2dhu",
4160 		.data = &edt_etmv570g2dhu,
4161 	}, {
4162 		.compatible = "eink,vb3300-kca",
4163 		.data = &eink_vb3300_kca,
4164 	}, {
4165 		.compatible = "evervision,vgg804821",
4166 		.data = &evervision_vgg804821,
4167 	}, {
4168 		.compatible = "foxlink,fl500wvr00-a0t",
4169 		.data = &foxlink_fl500wvr00_a0t,
4170 	}, {
4171 		.compatible = "frida,frd350h54004",
4172 		.data = &frida_frd350h54004,
4173 	}, {
4174 		.compatible = "friendlyarm,hd702e",
4175 		.data = &friendlyarm_hd702e,
4176 	}, {
4177 		.compatible = "giantplus,gpg482739qs5",
4178 		.data = &giantplus_gpg482739qs5
4179 	}, {
4180 		.compatible = "giantplus,gpm940b0",
4181 		.data = &giantplus_gpm940b0,
4182 	}, {
4183 		.compatible = "hannstar,hsd070pww1",
4184 		.data = &hannstar_hsd070pww1,
4185 	}, {
4186 		.compatible = "hannstar,hsd100pxn1",
4187 		.data = &hannstar_hsd100pxn1,
4188 	}, {
4189 		.compatible = "hannstar,hsd101pww2",
4190 		.data = &hannstar_hsd101pww2,
4191 	}, {
4192 		.compatible = "hit,tx23d38vm0caa",
4193 		.data = &hitachi_tx23d38vm0caa
4194 	}, {
4195 		.compatible = "innolux,at043tn24",
4196 		.data = &innolux_at043tn24,
4197 	}, {
4198 		.compatible = "innolux,at070tn92",
4199 		.data = &innolux_at070tn92,
4200 	}, {
4201 		.compatible = "innolux,g070ace-l01",
4202 		.data = &innolux_g070ace_l01,
4203 	}, {
4204 		.compatible = "innolux,g070y2-l01",
4205 		.data = &innolux_g070y2_l01,
4206 	}, {
4207 		.compatible = "innolux,g070y2-t02",
4208 		.data = &innolux_g070y2_t02,
4209 	}, {
4210 		.compatible = "innolux,g101ice-l01",
4211 		.data = &innolux_g101ice_l01
4212 	}, {
4213 		.compatible = "innolux,g121i1-l01",
4214 		.data = &innolux_g121i1_l01
4215 	}, {
4216 		.compatible = "innolux,g121x1-l03",
4217 		.data = &innolux_g121x1_l03,
4218 	}, {
4219 		.compatible = "innolux,n156bge-l21",
4220 		.data = &innolux_n156bge_l21,
4221 	}, {
4222 		.compatible = "innolux,zj070na-01p",
4223 		.data = &innolux_zj070na_01p,
4224 	}, {
4225 		.compatible = "koe,tx14d24vm1bpa",
4226 		.data = &koe_tx14d24vm1bpa,
4227 	}, {
4228 		.compatible = "koe,tx26d202vm0bwa",
4229 		.data = &koe_tx26d202vm0bwa,
4230 	}, {
4231 		.compatible = "koe,tx31d200vm0baa",
4232 		.data = &koe_tx31d200vm0baa,
4233 	}, {
4234 		.compatible = "kyo,tcg121xglp",
4235 		.data = &kyo_tcg121xglp,
4236 	}, {
4237 		.compatible = "lemaker,bl035-rgb-002",
4238 		.data = &lemaker_bl035_rgb_002,
4239 	}, {
4240 		.compatible = "lg,lb070wv8",
4241 		.data = &lg_lb070wv8,
4242 	}, {
4243 		.compatible = "logicpd,type28",
4244 		.data = &logicpd_type_28,
4245 	}, {
4246 		.compatible = "logictechno,lt161010-2nhc",
4247 		.data = &logictechno_lt161010_2nh,
4248 	}, {
4249 		.compatible = "logictechno,lt161010-2nhr",
4250 		.data = &logictechno_lt161010_2nh,
4251 	}, {
4252 		.compatible = "logictechno,lt170410-2whc",
4253 		.data = &logictechno_lt170410_2whc,
4254 	}, {
4255 		.compatible = "logictechno,lttd800480070-l2rt",
4256 		.data = &logictechno_lttd800480070_l2rt,
4257 	}, {
4258 		.compatible = "logictechno,lttd800480070-l6wh-rt",
4259 		.data = &logictechno_lttd800480070_l6wh_rt,
4260 	}, {
4261 		.compatible = "mitsubishi,aa070mc01-ca1",
4262 		.data = &mitsubishi_aa070mc01,
4263 	}, {
4264 		.compatible = "multi-inno,mi0700s4t-6",
4265 		.data = &multi_inno_mi0700s4t_6,
4266 	}, {
4267 		.compatible = "multi-inno,mi0800ft-9",
4268 		.data = &multi_inno_mi0800ft_9,
4269 	}, {
4270 		.compatible = "multi-inno,mi1010ait-1cp",
4271 		.data = &multi_inno_mi1010ait_1cp,
4272 	}, {
4273 		.compatible = "nec,nl12880bc20-05",
4274 		.data = &nec_nl12880bc20_05,
4275 	}, {
4276 		.compatible = "nec,nl4827hc19-05b",
4277 		.data = &nec_nl4827hc19_05b,
4278 	}, {
4279 		.compatible = "netron-dy,e231732",
4280 		.data = &netron_dy_e231732,
4281 	}, {
4282 		.compatible = "newhaven,nhd-4.3-480272ef-atxl",
4283 		.data = &newhaven_nhd_43_480272ef_atxl,
4284 	}, {
4285 		.compatible = "nlt,nl192108ac18-02d",
4286 		.data = &nlt_nl192108ac18_02d,
4287 	}, {
4288 		.compatible = "nvd,9128",
4289 		.data = &nvd_9128,
4290 	}, {
4291 		.compatible = "okaya,rs800480t-7x0gp",
4292 		.data = &okaya_rs800480t_7x0gp,
4293 	}, {
4294 		.compatible = "olimex,lcd-olinuxino-43-ts",
4295 		.data = &olimex_lcd_olinuxino_43ts,
4296 	}, {
4297 		.compatible = "ontat,yx700wv03",
4298 		.data = &ontat_yx700wv03,
4299 	}, {
4300 		.compatible = "ortustech,com37h3m05dtc",
4301 		.data = &ortustech_com37h3m,
4302 	}, {
4303 		.compatible = "ortustech,com37h3m99dtc",
4304 		.data = &ortustech_com37h3m,
4305 	}, {
4306 		.compatible = "ortustech,com43h4m85ulc",
4307 		.data = &ortustech_com43h4m85ulc,
4308 	}, {
4309 		.compatible = "osddisplays,osd070t1718-19ts",
4310 		.data = &osddisplays_osd070t1718_19ts,
4311 	}, {
4312 		.compatible = "pda,91-00156-a0",
4313 		.data = &pda_91_00156_a0,
4314 	}, {
4315 		.compatible = "powertip,ph800480t013-idf02",
4316 		.data = &powertip_ph800480t013_idf02,
4317 	}, {
4318 		.compatible = "qiaodian,qd43003c0-40",
4319 		.data = &qd43003c0_40,
4320 	}, {
4321 		.compatible = "qishenglong,gopher2b-lcd",
4322 		.data = &qishenglong_gopher2b_lcd,
4323 	}, {
4324 		.compatible = "rocktech,rk070er9427",
4325 		.data = &rocktech_rk070er9427,
4326 	}, {
4327 		.compatible = "rocktech,rk101ii01d-ct",
4328 		.data = &rocktech_rk101ii01d_ct,
4329 	}, {
4330 		.compatible = "samsung,ltl101al01",
4331 		.data = &samsung_ltl101al01,
4332 	}, {
4333 		.compatible = "samsung,ltn101nt05",
4334 		.data = &samsung_ltn101nt05,
4335 	}, {
4336 		.compatible = "satoz,sat050at40h12r2",
4337 		.data = &satoz_sat050at40h12r2,
4338 	}, {
4339 		.compatible = "sharp,lq035q7db03",
4340 		.data = &sharp_lq035q7db03,
4341 	}, {
4342 		.compatible = "sharp,lq070y3dg3b",
4343 		.data = &sharp_lq070y3dg3b,
4344 	}, {
4345 		.compatible = "sharp,lq101k1ly04",
4346 		.data = &sharp_lq101k1ly04,
4347 	}, {
4348 		.compatible = "sharp,ls020b1dd01d",
4349 		.data = &sharp_ls020b1dd01d,
4350 	}, {
4351 		.compatible = "shelly,sca07010-bfn-lnn",
4352 		.data = &shelly_sca07010_bfn_lnn,
4353 	}, {
4354 		.compatible = "starry,kr070pe2t",
4355 		.data = &starry_kr070pe2t,
4356 	}, {
4357 		.compatible = "startek,kd070wvfpa",
4358 		.data = &startek_kd070wvfpa,
4359 	}, {
4360 		.compatible = "team-source-display,tst043015cmhx",
4361 		.data = &tsd_tst043015cmhx,
4362 	}, {
4363 		.compatible = "tfc,s9700rtwv43tr-01b",
4364 		.data = &tfc_s9700rtwv43tr_01b,
4365 	}, {
4366 		.compatible = "tianma,tm070jdhg30",
4367 		.data = &tianma_tm070jdhg30,
4368 	}, {
4369 		.compatible = "tianma,tm070jvhg33",
4370 		.data = &tianma_tm070jvhg33,
4371 	}, {
4372 		.compatible = "tianma,tm070rvhg71",
4373 		.data = &tianma_tm070rvhg71,
4374 	}, {
4375 		.compatible = "ti,nspire-cx-lcd-panel",
4376 		.data = &ti_nspire_cx_lcd_panel,
4377 	}, {
4378 		.compatible = "ti,nspire-classic-lcd-panel",
4379 		.data = &ti_nspire_classic_lcd_panel,
4380 	}, {
4381 		.compatible = "toshiba,lt089ac29000",
4382 		.data = &toshiba_lt089ac29000,
4383 	}, {
4384 		.compatible = "tpk,f07a-0102",
4385 		.data = &tpk_f07a_0102,
4386 	}, {
4387 		.compatible = "tpk,f10a-0102",
4388 		.data = &tpk_f10a_0102,
4389 	}, {
4390 		.compatible = "urt,umsh-8596md-t",
4391 		.data = &urt_umsh_8596md_parallel,
4392 	}, {
4393 		.compatible = "urt,umsh-8596md-1t",
4394 		.data = &urt_umsh_8596md_parallel,
4395 	}, {
4396 		.compatible = "urt,umsh-8596md-7t",
4397 		.data = &urt_umsh_8596md_parallel,
4398 	}, {
4399 		.compatible = "urt,umsh-8596md-11t",
4400 		.data = &urt_umsh_8596md_lvds,
4401 	}, {
4402 		.compatible = "urt,umsh-8596md-19t",
4403 		.data = &urt_umsh_8596md_lvds,
4404 	}, {
4405 		.compatible = "urt,umsh-8596md-20t",
4406 		.data = &urt_umsh_8596md_parallel,
4407 	}, {
4408 		.compatible = "vivax,tpc9150-panel",
4409 		.data = &vivax_tpc9150_panel,
4410 	}, {
4411 		.compatible = "vxt,vl050-8048nt-c01",
4412 		.data = &vl050_8048nt_c01,
4413 	}, {
4414 		.compatible = "winstar,wf35ltiacd",
4415 		.data = &winstar_wf35ltiacd,
4416 	}, {
4417 		.compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4418 		.data = &yes_optoelectronics_ytc700tlag_05_201c,
4419 	}, {
4420 		/* Must be the last entry */
4421 		.compatible = "panel-dpi",
4422 		.data = &panel_dpi,
4423 	}, {
4424 		/* sentinel */
4425 	}
4426 };
4427 MODULE_DEVICE_TABLE(of, platform_of_match);
4428 
4429 static int panel_simple_platform_probe(struct platform_device *pdev)
4430 {
4431 	const struct of_device_id *id;
4432 
4433 	id = of_match_node(platform_of_match, pdev->dev.of_node);
4434 	if (!id)
4435 		return -ENODEV;
4436 
4437 	return panel_simple_probe(&pdev->dev, id->data);
4438 }
4439 
4440 static int panel_simple_platform_remove(struct platform_device *pdev)
4441 {
4442 	panel_simple_remove(&pdev->dev);
4443 
4444 	return 0;
4445 }
4446 
4447 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4448 {
4449 	panel_simple_shutdown(&pdev->dev);
4450 }
4451 
4452 static const struct dev_pm_ops panel_simple_pm_ops = {
4453 	SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4454 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4455 				pm_runtime_force_resume)
4456 };
4457 
4458 static struct platform_driver panel_simple_platform_driver = {
4459 	.driver = {
4460 		.name = "panel-simple",
4461 		.of_match_table = platform_of_match,
4462 		.pm = &panel_simple_pm_ops,
4463 	},
4464 	.probe = panel_simple_platform_probe,
4465 	.remove = panel_simple_platform_remove,
4466 	.shutdown = panel_simple_platform_shutdown,
4467 };
4468 
4469 struct panel_desc_dsi {
4470 	struct panel_desc desc;
4471 
4472 	unsigned long flags;
4473 	enum mipi_dsi_pixel_format format;
4474 	unsigned int lanes;
4475 };
4476 
4477 static const struct drm_display_mode auo_b080uan01_mode = {
4478 	.clock = 154500,
4479 	.hdisplay = 1200,
4480 	.hsync_start = 1200 + 62,
4481 	.hsync_end = 1200 + 62 + 4,
4482 	.htotal = 1200 + 62 + 4 + 62,
4483 	.vdisplay = 1920,
4484 	.vsync_start = 1920 + 9,
4485 	.vsync_end = 1920 + 9 + 2,
4486 	.vtotal = 1920 + 9 + 2 + 8,
4487 };
4488 
4489 static const struct panel_desc_dsi auo_b080uan01 = {
4490 	.desc = {
4491 		.modes = &auo_b080uan01_mode,
4492 		.num_modes = 1,
4493 		.bpc = 8,
4494 		.size = {
4495 			.width = 108,
4496 			.height = 272,
4497 		},
4498 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4499 	},
4500 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4501 	.format = MIPI_DSI_FMT_RGB888,
4502 	.lanes = 4,
4503 };
4504 
4505 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4506 	.clock = 160000,
4507 	.hdisplay = 1200,
4508 	.hsync_start = 1200 + 120,
4509 	.hsync_end = 1200 + 120 + 20,
4510 	.htotal = 1200 + 120 + 20 + 21,
4511 	.vdisplay = 1920,
4512 	.vsync_start = 1920 + 21,
4513 	.vsync_end = 1920 + 21 + 3,
4514 	.vtotal = 1920 + 21 + 3 + 18,
4515 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4516 };
4517 
4518 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4519 	.desc = {
4520 		.modes = &boe_tv080wum_nl0_mode,
4521 		.num_modes = 1,
4522 		.size = {
4523 			.width = 107,
4524 			.height = 172,
4525 		},
4526 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4527 	},
4528 	.flags = MIPI_DSI_MODE_VIDEO |
4529 		 MIPI_DSI_MODE_VIDEO_BURST |
4530 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4531 	.format = MIPI_DSI_FMT_RGB888,
4532 	.lanes = 4,
4533 };
4534 
4535 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4536 	.clock = 71000,
4537 	.hdisplay = 800,
4538 	.hsync_start = 800 + 32,
4539 	.hsync_end = 800 + 32 + 1,
4540 	.htotal = 800 + 32 + 1 + 57,
4541 	.vdisplay = 1280,
4542 	.vsync_start = 1280 + 28,
4543 	.vsync_end = 1280 + 28 + 1,
4544 	.vtotal = 1280 + 28 + 1 + 14,
4545 };
4546 
4547 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4548 	.desc = {
4549 		.modes = &lg_ld070wx3_sl01_mode,
4550 		.num_modes = 1,
4551 		.bpc = 8,
4552 		.size = {
4553 			.width = 94,
4554 			.height = 151,
4555 		},
4556 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4557 	},
4558 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4559 	.format = MIPI_DSI_FMT_RGB888,
4560 	.lanes = 4,
4561 };
4562 
4563 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4564 	.clock = 67000,
4565 	.hdisplay = 720,
4566 	.hsync_start = 720 + 12,
4567 	.hsync_end = 720 + 12 + 4,
4568 	.htotal = 720 + 12 + 4 + 112,
4569 	.vdisplay = 1280,
4570 	.vsync_start = 1280 + 8,
4571 	.vsync_end = 1280 + 8 + 4,
4572 	.vtotal = 1280 + 8 + 4 + 12,
4573 };
4574 
4575 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4576 	.desc = {
4577 		.modes = &lg_lh500wx1_sd03_mode,
4578 		.num_modes = 1,
4579 		.bpc = 8,
4580 		.size = {
4581 			.width = 62,
4582 			.height = 110,
4583 		},
4584 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4585 	},
4586 	.flags = MIPI_DSI_MODE_VIDEO,
4587 	.format = MIPI_DSI_FMT_RGB888,
4588 	.lanes = 4,
4589 };
4590 
4591 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4592 	.clock = 157200,
4593 	.hdisplay = 1920,
4594 	.hsync_start = 1920 + 154,
4595 	.hsync_end = 1920 + 154 + 16,
4596 	.htotal = 1920 + 154 + 16 + 32,
4597 	.vdisplay = 1200,
4598 	.vsync_start = 1200 + 17,
4599 	.vsync_end = 1200 + 17 + 2,
4600 	.vtotal = 1200 + 17 + 2 + 16,
4601 };
4602 
4603 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4604 	.desc = {
4605 		.modes = &panasonic_vvx10f004b00_mode,
4606 		.num_modes = 1,
4607 		.bpc = 8,
4608 		.size = {
4609 			.width = 217,
4610 			.height = 136,
4611 		},
4612 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4613 	},
4614 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4615 		 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4616 	.format = MIPI_DSI_FMT_RGB888,
4617 	.lanes = 4,
4618 };
4619 
4620 static const struct drm_display_mode lg_acx467akm_7_mode = {
4621 	.clock = 150000,
4622 	.hdisplay = 1080,
4623 	.hsync_start = 1080 + 2,
4624 	.hsync_end = 1080 + 2 + 2,
4625 	.htotal = 1080 + 2 + 2 + 2,
4626 	.vdisplay = 1920,
4627 	.vsync_start = 1920 + 2,
4628 	.vsync_end = 1920 + 2 + 2,
4629 	.vtotal = 1920 + 2 + 2 + 2,
4630 };
4631 
4632 static const struct panel_desc_dsi lg_acx467akm_7 = {
4633 	.desc = {
4634 		.modes = &lg_acx467akm_7_mode,
4635 		.num_modes = 1,
4636 		.bpc = 8,
4637 		.size = {
4638 			.width = 62,
4639 			.height = 110,
4640 		},
4641 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4642 	},
4643 	.flags = 0,
4644 	.format = MIPI_DSI_FMT_RGB888,
4645 	.lanes = 4,
4646 };
4647 
4648 static const struct drm_display_mode osd101t2045_53ts_mode = {
4649 	.clock = 154500,
4650 	.hdisplay = 1920,
4651 	.hsync_start = 1920 + 112,
4652 	.hsync_end = 1920 + 112 + 16,
4653 	.htotal = 1920 + 112 + 16 + 32,
4654 	.vdisplay = 1200,
4655 	.vsync_start = 1200 + 16,
4656 	.vsync_end = 1200 + 16 + 2,
4657 	.vtotal = 1200 + 16 + 2 + 16,
4658 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4659 };
4660 
4661 static const struct panel_desc_dsi osd101t2045_53ts = {
4662 	.desc = {
4663 		.modes = &osd101t2045_53ts_mode,
4664 		.num_modes = 1,
4665 		.bpc = 8,
4666 		.size = {
4667 			.width = 217,
4668 			.height = 136,
4669 		},
4670 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4671 	},
4672 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4673 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4674 		 MIPI_DSI_MODE_NO_EOT_PACKET,
4675 	.format = MIPI_DSI_FMT_RGB888,
4676 	.lanes = 4,
4677 };
4678 
4679 static const struct of_device_id dsi_of_match[] = {
4680 	{
4681 		.compatible = "auo,b080uan01",
4682 		.data = &auo_b080uan01
4683 	}, {
4684 		.compatible = "boe,tv080wum-nl0",
4685 		.data = &boe_tv080wum_nl0
4686 	}, {
4687 		.compatible = "lg,ld070wx3-sl01",
4688 		.data = &lg_ld070wx3_sl01
4689 	}, {
4690 		.compatible = "lg,lh500wx1-sd03",
4691 		.data = &lg_lh500wx1_sd03
4692 	}, {
4693 		.compatible = "panasonic,vvx10f004b00",
4694 		.data = &panasonic_vvx10f004b00
4695 	}, {
4696 		.compatible = "lg,acx467akm-7",
4697 		.data = &lg_acx467akm_7
4698 	}, {
4699 		.compatible = "osddisplays,osd101t2045-53ts",
4700 		.data = &osd101t2045_53ts
4701 	}, {
4702 		/* sentinel */
4703 	}
4704 };
4705 MODULE_DEVICE_TABLE(of, dsi_of_match);
4706 
4707 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4708 {
4709 	const struct panel_desc_dsi *desc;
4710 	const struct of_device_id *id;
4711 	int err;
4712 
4713 	id = of_match_node(dsi_of_match, dsi->dev.of_node);
4714 	if (!id)
4715 		return -ENODEV;
4716 
4717 	desc = id->data;
4718 
4719 	err = panel_simple_probe(&dsi->dev, &desc->desc);
4720 	if (err < 0)
4721 		return err;
4722 
4723 	dsi->mode_flags = desc->flags;
4724 	dsi->format = desc->format;
4725 	dsi->lanes = desc->lanes;
4726 
4727 	err = mipi_dsi_attach(dsi);
4728 	if (err) {
4729 		struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4730 
4731 		drm_panel_remove(&panel->base);
4732 	}
4733 
4734 	return err;
4735 }
4736 
4737 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4738 {
4739 	int err;
4740 
4741 	err = mipi_dsi_detach(dsi);
4742 	if (err < 0)
4743 		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4744 
4745 	panel_simple_remove(&dsi->dev);
4746 }
4747 
4748 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4749 {
4750 	panel_simple_shutdown(&dsi->dev);
4751 }
4752 
4753 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4754 	.driver = {
4755 		.name = "panel-simple-dsi",
4756 		.of_match_table = dsi_of_match,
4757 		.pm = &panel_simple_pm_ops,
4758 	},
4759 	.probe = panel_simple_dsi_probe,
4760 	.remove = panel_simple_dsi_remove,
4761 	.shutdown = panel_simple_dsi_shutdown,
4762 };
4763 
4764 static int __init panel_simple_init(void)
4765 {
4766 	int err;
4767 
4768 	err = platform_driver_register(&panel_simple_platform_driver);
4769 	if (err < 0)
4770 		return err;
4771 
4772 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4773 		err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4774 		if (err < 0)
4775 			goto err_did_platform_register;
4776 	}
4777 
4778 	return 0;
4779 
4780 err_did_platform_register:
4781 	platform_driver_unregister(&panel_simple_platform_driver);
4782 
4783 	return err;
4784 }
4785 module_init(panel_simple_init);
4786 
4787 static void __exit panel_simple_exit(void)
4788 {
4789 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4790 		mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4791 
4792 	platform_driver_unregister(&panel_simple_platform_driver);
4793 }
4794 module_exit(panel_simple_exit);
4795 
4796 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4797 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4798 MODULE_LICENSE("GPL and additional rights");
4799