1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, 167 drm_mode_vrefresh(m)); 168 continue; 169 } 170 171 mode->type |= DRM_MODE_TYPE_DRIVER; 172 173 if (panel->desc->num_modes == 1) 174 mode->type |= DRM_MODE_TYPE_PREFERRED; 175 176 drm_mode_set_name(mode); 177 178 drm_mode_probed_add(connector, mode); 179 num++; 180 } 181 182 return num; 183 } 184 185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 186 struct drm_connector *connector) 187 { 188 struct drm_display_mode *mode; 189 bool has_override = panel->override_mode.type; 190 unsigned int num = 0; 191 192 if (!panel->desc) 193 return 0; 194 195 if (has_override) { 196 mode = drm_mode_duplicate(connector->dev, 197 &panel->override_mode); 198 if (mode) { 199 drm_mode_probed_add(connector, mode); 200 num = 1; 201 } else { 202 dev_err(panel->base.dev, "failed to add override mode\n"); 203 } 204 } 205 206 /* Only add timings if override was not there or failed to validate */ 207 if (num == 0 && panel->desc->num_timings) 208 num = panel_simple_get_timings_modes(panel, connector); 209 210 /* 211 * Only add fixed modes if timings/override added no mode. 212 * 213 * We should only ever have either the display timings specified 214 * or a fixed mode. Anything else is rather bogus. 215 */ 216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 217 if (num == 0) 218 num = panel_simple_get_display_modes(panel, connector); 219 220 connector->display_info.bpc = panel->desc->bpc; 221 connector->display_info.width_mm = panel->desc->size.width; 222 connector->display_info.height_mm = panel->desc->size.height; 223 if (panel->desc->bus_format) 224 drm_display_info_set_bus_formats(&connector->display_info, 225 &panel->desc->bus_format, 1); 226 connector->display_info.bus_flags = panel->desc->bus_flags; 227 228 return num; 229 } 230 231 static int panel_simple_disable(struct drm_panel *panel) 232 { 233 struct panel_simple *p = to_panel_simple(panel); 234 235 if (!p->enabled) 236 return 0; 237 238 if (p->desc->delay.disable) 239 msleep(p->desc->delay.disable); 240 241 p->enabled = false; 242 243 return 0; 244 } 245 246 static int panel_simple_unprepare(struct drm_panel *panel) 247 { 248 struct panel_simple *p = to_panel_simple(panel); 249 250 if (!p->prepared) 251 return 0; 252 253 gpiod_set_value_cansleep(p->enable_gpio, 0); 254 255 regulator_disable(p->supply); 256 257 if (p->desc->delay.unprepare) 258 msleep(p->desc->delay.unprepare); 259 260 p->prepared = false; 261 262 return 0; 263 } 264 265 static int panel_simple_get_hpd_gpio(struct device *dev, 266 struct panel_simple *p, bool from_probe) 267 { 268 int err; 269 270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 271 if (IS_ERR(p->hpd_gpio)) { 272 err = PTR_ERR(p->hpd_gpio); 273 274 /* 275 * If we're called from probe we won't consider '-EPROBE_DEFER' 276 * to be an error--we'll leave the error code in "hpd_gpio". 277 * When we try to use it we'll try again. This allows for 278 * circular dependencies where the component providing the 279 * hpd gpio needs the panel to init before probing. 280 */ 281 if (err != -EPROBE_DEFER || !from_probe) { 282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 283 return err; 284 } 285 } 286 287 return 0; 288 } 289 290 static int panel_simple_prepare(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 unsigned int delay; 294 int err; 295 int hpd_asserted; 296 297 if (p->prepared) 298 return 0; 299 300 err = regulator_enable(p->supply); 301 if (err < 0) { 302 dev_err(panel->dev, "failed to enable supply: %d\n", err); 303 return err; 304 } 305 306 gpiod_set_value_cansleep(p->enable_gpio, 1); 307 308 delay = p->desc->delay.prepare; 309 if (p->no_hpd) 310 delay += p->desc->delay.hpd_absent_delay; 311 if (delay) 312 msleep(delay); 313 314 if (p->hpd_gpio) { 315 if (IS_ERR(p->hpd_gpio)) { 316 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 317 if (err) 318 return err; 319 } 320 321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 322 hpd_asserted, hpd_asserted, 323 1000, 2000000); 324 if (hpd_asserted < 0) 325 err = hpd_asserted; 326 327 if (err) { 328 dev_err(panel->dev, 329 "error waiting for hpd GPIO: %d\n", err); 330 return err; 331 } 332 } 333 334 p->prepared = true; 335 336 return 0; 337 } 338 339 static int panel_simple_enable(struct drm_panel *panel) 340 { 341 struct panel_simple *p = to_panel_simple(panel); 342 343 if (p->enabled) 344 return 0; 345 346 if (p->desc->delay.enable) 347 msleep(p->desc->delay.enable); 348 349 p->enabled = true; 350 351 return 0; 352 } 353 354 static int panel_simple_get_modes(struct drm_panel *panel, 355 struct drm_connector *connector) 356 { 357 struct panel_simple *p = to_panel_simple(panel); 358 int num = 0; 359 360 /* probe EDID if a DDC bus is available */ 361 if (p->ddc) { 362 struct edid *edid = drm_get_edid(connector, p->ddc); 363 364 drm_connector_update_edid_property(connector, edid); 365 if (edid) { 366 num += drm_add_edid_modes(connector, edid); 367 kfree(edid); 368 } 369 } 370 371 /* add hard-coded panel modes */ 372 num += panel_simple_get_non_edid_modes(p, connector); 373 374 return num; 375 } 376 377 static int panel_simple_get_timings(struct drm_panel *panel, 378 unsigned int num_timings, 379 struct display_timing *timings) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 unsigned int i; 383 384 if (p->desc->num_timings < num_timings) 385 num_timings = p->desc->num_timings; 386 387 if (timings) 388 for (i = 0; i < num_timings; i++) 389 timings[i] = p->desc->timings[i]; 390 391 return p->desc->num_timings; 392 } 393 394 static const struct drm_panel_funcs panel_simple_funcs = { 395 .disable = panel_simple_disable, 396 .unprepare = panel_simple_unprepare, 397 .prepare = panel_simple_prepare, 398 .enable = panel_simple_enable, 399 .get_modes = panel_simple_get_modes, 400 .get_timings = panel_simple_get_timings, 401 }; 402 403 static struct panel_desc panel_dpi; 404 405 static int panel_dpi_probe(struct device *dev, 406 struct panel_simple *panel) 407 { 408 struct display_timing *timing; 409 const struct device_node *np; 410 struct panel_desc *desc; 411 unsigned int bus_flags; 412 struct videomode vm; 413 int ret; 414 415 np = dev->of_node; 416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 417 if (!desc) 418 return -ENOMEM; 419 420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 421 if (!timing) 422 return -ENOMEM; 423 424 ret = of_get_display_timing(np, "panel-timing", timing); 425 if (ret < 0) { 426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 427 np); 428 return ret; 429 } 430 431 desc->timings = timing; 432 desc->num_timings = 1; 433 434 of_property_read_u32(np, "width-mm", &desc->size.width); 435 of_property_read_u32(np, "height-mm", &desc->size.height); 436 437 /* Extract bus_flags from display_timing */ 438 bus_flags = 0; 439 vm.flags = timing->flags; 440 drm_bus_flags_from_videomode(&vm, &bus_flags); 441 desc->bus_flags = bus_flags; 442 443 /* We do not know the connector for the DT node, so guess it */ 444 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 445 446 panel->desc = desc; 447 448 return 0; 449 } 450 451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 452 (to_check->field.typ >= bounds->field.min && \ 453 to_check->field.typ <= bounds->field.max) 454 static void panel_simple_parse_panel_timing_node(struct device *dev, 455 struct panel_simple *panel, 456 const struct display_timing *ot) 457 { 458 const struct panel_desc *desc = panel->desc; 459 struct videomode vm; 460 unsigned int i; 461 462 if (WARN_ON(desc->num_modes)) { 463 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 464 return; 465 } 466 if (WARN_ON(!desc->num_timings)) { 467 dev_err(dev, "Reject override mode: no timings specified\n"); 468 return; 469 } 470 471 for (i = 0; i < panel->desc->num_timings; i++) { 472 const struct display_timing *dt = &panel->desc->timings[i]; 473 474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 482 continue; 483 484 if (ot->flags != dt->flags) 485 continue; 486 487 videomode_from_timing(ot, &vm); 488 drm_display_mode_from_videomode(&vm, &panel->override_mode); 489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 490 DRM_MODE_TYPE_PREFERRED; 491 break; 492 } 493 494 if (WARN_ON(!panel->override_mode.type)) 495 dev_err(dev, "Reject override mode: No display_timing found\n"); 496 } 497 498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 499 { 500 struct panel_simple *panel; 501 struct display_timing dt; 502 struct device_node *ddc; 503 int err; 504 505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 506 if (!panel) 507 return -ENOMEM; 508 509 panel->enabled = false; 510 panel->prepared = false; 511 panel->desc = desc; 512 513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 514 if (!panel->no_hpd) { 515 err = panel_simple_get_hpd_gpio(dev, panel, true); 516 if (err) 517 return err; 518 } 519 520 panel->supply = devm_regulator_get(dev, "power"); 521 if (IS_ERR(panel->supply)) 522 return PTR_ERR(panel->supply); 523 524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 525 GPIOD_OUT_LOW); 526 if (IS_ERR(panel->enable_gpio)) { 527 err = PTR_ERR(panel->enable_gpio); 528 if (err != -EPROBE_DEFER) 529 dev_err(dev, "failed to request GPIO: %d\n", err); 530 return err; 531 } 532 533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 534 if (ddc) { 535 panel->ddc = of_find_i2c_adapter_by_node(ddc); 536 of_node_put(ddc); 537 538 if (!panel->ddc) 539 return -EPROBE_DEFER; 540 } 541 542 if (desc == &panel_dpi) { 543 /* Handle the generic panel-dpi binding */ 544 err = panel_dpi_probe(dev, panel); 545 if (err) 546 goto free_ddc; 547 } else { 548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 549 panel_simple_parse_panel_timing_node(dev, panel, &dt); 550 } 551 552 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 553 desc->connector_type); 554 555 err = drm_panel_of_backlight(&panel->base); 556 if (err) 557 goto free_ddc; 558 559 err = drm_panel_add(&panel->base); 560 if (err < 0) 561 goto free_ddc; 562 563 dev_set_drvdata(dev, panel); 564 565 return 0; 566 567 free_ddc: 568 if (panel->ddc) 569 put_device(&panel->ddc->dev); 570 571 return err; 572 } 573 574 static int panel_simple_remove(struct device *dev) 575 { 576 struct panel_simple *panel = dev_get_drvdata(dev); 577 578 drm_panel_remove(&panel->base); 579 drm_panel_disable(&panel->base); 580 drm_panel_unprepare(&panel->base); 581 582 if (panel->ddc) 583 put_device(&panel->ddc->dev); 584 585 return 0; 586 } 587 588 static void panel_simple_shutdown(struct device *dev) 589 { 590 struct panel_simple *panel = dev_get_drvdata(dev); 591 592 drm_panel_disable(&panel->base); 593 drm_panel_unprepare(&panel->base); 594 } 595 596 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 597 .clock = 9000, 598 .hdisplay = 480, 599 .hsync_start = 480 + 2, 600 .hsync_end = 480 + 2 + 41, 601 .htotal = 480 + 2 + 41 + 2, 602 .vdisplay = 272, 603 .vsync_start = 272 + 2, 604 .vsync_end = 272 + 2 + 10, 605 .vtotal = 272 + 2 + 10 + 2, 606 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 607 }; 608 609 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 610 .modes = &ire_am_480272h3tmqw_t01h_mode, 611 .num_modes = 1, 612 .bpc = 8, 613 .size = { 614 .width = 105, 615 .height = 67, 616 }, 617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 618 }; 619 620 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 621 .clock = 33333, 622 .hdisplay = 800, 623 .hsync_start = 800 + 0, 624 .hsync_end = 800 + 0 + 255, 625 .htotal = 800 + 0 + 255 + 0, 626 .vdisplay = 480, 627 .vsync_start = 480 + 2, 628 .vsync_end = 480 + 2 + 45, 629 .vtotal = 480 + 2 + 45 + 0, 630 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 631 }; 632 633 static const struct panel_desc ampire_am800480r3tmqwa1h = { 634 .modes = &ire_am800480r3tmqwa1h_mode, 635 .num_modes = 1, 636 .bpc = 6, 637 .size = { 638 .width = 152, 639 .height = 91, 640 }, 641 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 642 }; 643 644 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 645 .pixelclock = { 26400000, 33300000, 46800000 }, 646 .hactive = { 800, 800, 800 }, 647 .hfront_porch = { 16, 210, 354 }, 648 .hback_porch = { 45, 36, 6 }, 649 .hsync_len = { 1, 10, 40 }, 650 .vactive = { 480, 480, 480 }, 651 .vfront_porch = { 7, 22, 147 }, 652 .vback_porch = { 22, 13, 3 }, 653 .vsync_len = { 1, 10, 20 }, 654 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 655 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 656 }; 657 658 static const struct panel_desc armadeus_st0700_adapt = { 659 .timings = &santek_st0700i5y_rbslw_f_timing, 660 .num_timings = 1, 661 .bpc = 6, 662 .size = { 663 .width = 154, 664 .height = 86, 665 }, 666 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 667 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 668 }; 669 670 static const struct drm_display_mode auo_b101aw03_mode = { 671 .clock = 51450, 672 .hdisplay = 1024, 673 .hsync_start = 1024 + 156, 674 .hsync_end = 1024 + 156 + 8, 675 .htotal = 1024 + 156 + 8 + 156, 676 .vdisplay = 600, 677 .vsync_start = 600 + 16, 678 .vsync_end = 600 + 16 + 6, 679 .vtotal = 600 + 16 + 6 + 16, 680 }; 681 682 static const struct panel_desc auo_b101aw03 = { 683 .modes = &auo_b101aw03_mode, 684 .num_modes = 1, 685 .bpc = 6, 686 .size = { 687 .width = 223, 688 .height = 125, 689 }, 690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 691 }; 692 693 static const struct display_timing auo_b101ean01_timing = { 694 .pixelclock = { 65300000, 72500000, 75000000 }, 695 .hactive = { 1280, 1280, 1280 }, 696 .hfront_porch = { 18, 119, 119 }, 697 .hback_porch = { 21, 21, 21 }, 698 .hsync_len = { 32, 32, 32 }, 699 .vactive = { 800, 800, 800 }, 700 .vfront_porch = { 4, 4, 4 }, 701 .vback_porch = { 8, 8, 8 }, 702 .vsync_len = { 18, 20, 20 }, 703 }; 704 705 static const struct panel_desc auo_b101ean01 = { 706 .timings = &auo_b101ean01_timing, 707 .num_timings = 1, 708 .bpc = 6, 709 .size = { 710 .width = 217, 711 .height = 136, 712 }, 713 }; 714 715 static const struct drm_display_mode auo_b101xtn01_mode = { 716 .clock = 72000, 717 .hdisplay = 1366, 718 .hsync_start = 1366 + 20, 719 .hsync_end = 1366 + 20 + 70, 720 .htotal = 1366 + 20 + 70, 721 .vdisplay = 768, 722 .vsync_start = 768 + 14, 723 .vsync_end = 768 + 14 + 42, 724 .vtotal = 768 + 14 + 42, 725 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 726 }; 727 728 static const struct panel_desc auo_b101xtn01 = { 729 .modes = &auo_b101xtn01_mode, 730 .num_modes = 1, 731 .bpc = 6, 732 .size = { 733 .width = 223, 734 .height = 125, 735 }, 736 }; 737 738 static const struct drm_display_mode auo_b116xak01_mode = { 739 .clock = 69300, 740 .hdisplay = 1366, 741 .hsync_start = 1366 + 48, 742 .hsync_end = 1366 + 48 + 32, 743 .htotal = 1366 + 48 + 32 + 10, 744 .vdisplay = 768, 745 .vsync_start = 768 + 4, 746 .vsync_end = 768 + 4 + 6, 747 .vtotal = 768 + 4 + 6 + 15, 748 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 749 }; 750 751 static const struct panel_desc auo_b116xak01 = { 752 .modes = &auo_b116xak01_mode, 753 .num_modes = 1, 754 .bpc = 6, 755 .size = { 756 .width = 256, 757 .height = 144, 758 }, 759 .delay = { 760 .hpd_absent_delay = 200, 761 }, 762 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 763 .connector_type = DRM_MODE_CONNECTOR_eDP, 764 }; 765 766 static const struct drm_display_mode auo_b116xw03_mode = { 767 .clock = 70589, 768 .hdisplay = 1366, 769 .hsync_start = 1366 + 40, 770 .hsync_end = 1366 + 40 + 40, 771 .htotal = 1366 + 40 + 40 + 32, 772 .vdisplay = 768, 773 .vsync_start = 768 + 10, 774 .vsync_end = 768 + 10 + 12, 775 .vtotal = 768 + 10 + 12 + 6, 776 }; 777 778 static const struct panel_desc auo_b116xw03 = { 779 .modes = &auo_b116xw03_mode, 780 .num_modes = 1, 781 .bpc = 6, 782 .size = { 783 .width = 256, 784 .height = 144, 785 }, 786 }; 787 788 static const struct drm_display_mode auo_b133xtn01_mode = { 789 .clock = 69500, 790 .hdisplay = 1366, 791 .hsync_start = 1366 + 48, 792 .hsync_end = 1366 + 48 + 32, 793 .htotal = 1366 + 48 + 32 + 20, 794 .vdisplay = 768, 795 .vsync_start = 768 + 3, 796 .vsync_end = 768 + 3 + 6, 797 .vtotal = 768 + 3 + 6 + 13, 798 }; 799 800 static const struct panel_desc auo_b133xtn01 = { 801 .modes = &auo_b133xtn01_mode, 802 .num_modes = 1, 803 .bpc = 6, 804 .size = { 805 .width = 293, 806 .height = 165, 807 }, 808 }; 809 810 static const struct drm_display_mode auo_b133htn01_mode = { 811 .clock = 150660, 812 .hdisplay = 1920, 813 .hsync_start = 1920 + 172, 814 .hsync_end = 1920 + 172 + 80, 815 .htotal = 1920 + 172 + 80 + 60, 816 .vdisplay = 1080, 817 .vsync_start = 1080 + 25, 818 .vsync_end = 1080 + 25 + 10, 819 .vtotal = 1080 + 25 + 10 + 10, 820 }; 821 822 static const struct panel_desc auo_b133htn01 = { 823 .modes = &auo_b133htn01_mode, 824 .num_modes = 1, 825 .bpc = 6, 826 .size = { 827 .width = 293, 828 .height = 165, 829 }, 830 .delay = { 831 .prepare = 105, 832 .enable = 20, 833 .unprepare = 50, 834 }, 835 }; 836 837 static const struct display_timing auo_g070vvn01_timings = { 838 .pixelclock = { 33300000, 34209000, 45000000 }, 839 .hactive = { 800, 800, 800 }, 840 .hfront_porch = { 20, 40, 200 }, 841 .hback_porch = { 87, 40, 1 }, 842 .hsync_len = { 1, 48, 87 }, 843 .vactive = { 480, 480, 480 }, 844 .vfront_porch = { 5, 13, 200 }, 845 .vback_porch = { 31, 31, 29 }, 846 .vsync_len = { 1, 1, 3 }, 847 }; 848 849 static const struct panel_desc auo_g070vvn01 = { 850 .timings = &auo_g070vvn01_timings, 851 .num_timings = 1, 852 .bpc = 8, 853 .size = { 854 .width = 152, 855 .height = 91, 856 }, 857 .delay = { 858 .prepare = 200, 859 .enable = 50, 860 .disable = 50, 861 .unprepare = 1000, 862 }, 863 }; 864 865 static const struct drm_display_mode auo_g101evn010_mode = { 866 .clock = 68930, 867 .hdisplay = 1280, 868 .hsync_start = 1280 + 82, 869 .hsync_end = 1280 + 82 + 2, 870 .htotal = 1280 + 82 + 2 + 84, 871 .vdisplay = 800, 872 .vsync_start = 800 + 8, 873 .vsync_end = 800 + 8 + 2, 874 .vtotal = 800 + 8 + 2 + 6, 875 }; 876 877 static const struct panel_desc auo_g101evn010 = { 878 .modes = &auo_g101evn010_mode, 879 .num_modes = 1, 880 .bpc = 6, 881 .size = { 882 .width = 216, 883 .height = 135, 884 }, 885 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 886 .connector_type = DRM_MODE_CONNECTOR_LVDS, 887 }; 888 889 static const struct drm_display_mode auo_g104sn02_mode = { 890 .clock = 40000, 891 .hdisplay = 800, 892 .hsync_start = 800 + 40, 893 .hsync_end = 800 + 40 + 216, 894 .htotal = 800 + 40 + 216 + 128, 895 .vdisplay = 600, 896 .vsync_start = 600 + 10, 897 .vsync_end = 600 + 10 + 35, 898 .vtotal = 600 + 10 + 35 + 2, 899 }; 900 901 static const struct panel_desc auo_g104sn02 = { 902 .modes = &auo_g104sn02_mode, 903 .num_modes = 1, 904 .bpc = 8, 905 .size = { 906 .width = 211, 907 .height = 158, 908 }, 909 }; 910 911 static const struct drm_display_mode auo_g121ean01_mode = { 912 .clock = 66700, 913 .hdisplay = 1280, 914 .hsync_start = 1280 + 58, 915 .hsync_end = 1280 + 58 + 8, 916 .htotal = 1280 + 58 + 8 + 70, 917 .vdisplay = 800, 918 .vsync_start = 800 + 6, 919 .vsync_end = 800 + 6 + 4, 920 .vtotal = 800 + 6 + 4 + 10, 921 }; 922 923 static const struct panel_desc auo_g121ean01 = { 924 .modes = &auo_g121ean01_mode, 925 .num_modes = 1, 926 .bpc = 8, 927 .size = { 928 .width = 261, 929 .height = 163, 930 }, 931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 933 }; 934 935 static const struct display_timing auo_g133han01_timings = { 936 .pixelclock = { 134000000, 141200000, 149000000 }, 937 .hactive = { 1920, 1920, 1920 }, 938 .hfront_porch = { 39, 58, 77 }, 939 .hback_porch = { 59, 88, 117 }, 940 .hsync_len = { 28, 42, 56 }, 941 .vactive = { 1080, 1080, 1080 }, 942 .vfront_porch = { 3, 8, 11 }, 943 .vback_porch = { 5, 14, 19 }, 944 .vsync_len = { 4, 14, 19 }, 945 }; 946 947 static const struct panel_desc auo_g133han01 = { 948 .timings = &auo_g133han01_timings, 949 .num_timings = 1, 950 .bpc = 8, 951 .size = { 952 .width = 293, 953 .height = 165, 954 }, 955 .delay = { 956 .prepare = 200, 957 .enable = 50, 958 .disable = 50, 959 .unprepare = 1000, 960 }, 961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 962 .connector_type = DRM_MODE_CONNECTOR_LVDS, 963 }; 964 965 static const struct drm_display_mode auo_g156xtn01_mode = { 966 .clock = 76000, 967 .hdisplay = 1366, 968 .hsync_start = 1366 + 33, 969 .hsync_end = 1366 + 33 + 67, 970 .htotal = 1560, 971 .vdisplay = 768, 972 .vsync_start = 768 + 4, 973 .vsync_end = 768 + 4 + 4, 974 .vtotal = 806, 975 }; 976 977 static const struct panel_desc auo_g156xtn01 = { 978 .modes = &auo_g156xtn01_mode, 979 .num_modes = 1, 980 .bpc = 8, 981 .size = { 982 .width = 344, 983 .height = 194, 984 }, 985 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 986 .connector_type = DRM_MODE_CONNECTOR_LVDS, 987 }; 988 989 static const struct display_timing auo_g185han01_timings = { 990 .pixelclock = { 120000000, 144000000, 175000000 }, 991 .hactive = { 1920, 1920, 1920 }, 992 .hfront_porch = { 36, 120, 148 }, 993 .hback_porch = { 24, 88, 108 }, 994 .hsync_len = { 20, 48, 64 }, 995 .vactive = { 1080, 1080, 1080 }, 996 .vfront_porch = { 6, 10, 40 }, 997 .vback_porch = { 2, 5, 20 }, 998 .vsync_len = { 2, 5, 20 }, 999 }; 1000 1001 static const struct panel_desc auo_g185han01 = { 1002 .timings = &auo_g185han01_timings, 1003 .num_timings = 1, 1004 .bpc = 8, 1005 .size = { 1006 .width = 409, 1007 .height = 230, 1008 }, 1009 .delay = { 1010 .prepare = 50, 1011 .enable = 200, 1012 .disable = 110, 1013 .unprepare = 1000, 1014 }, 1015 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1016 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1017 }; 1018 1019 static const struct display_timing auo_g190ean01_timings = { 1020 .pixelclock = { 90000000, 108000000, 135000000 }, 1021 .hactive = { 1280, 1280, 1280 }, 1022 .hfront_porch = { 126, 184, 1266 }, 1023 .hback_porch = { 84, 122, 844 }, 1024 .hsync_len = { 70, 102, 704 }, 1025 .vactive = { 1024, 1024, 1024 }, 1026 .vfront_porch = { 4, 26, 76 }, 1027 .vback_porch = { 2, 8, 25 }, 1028 .vsync_len = { 2, 8, 25 }, 1029 }; 1030 1031 static const struct panel_desc auo_g190ean01 = { 1032 .timings = &auo_g190ean01_timings, 1033 .num_timings = 1, 1034 .bpc = 8, 1035 .size = { 1036 .width = 376, 1037 .height = 301, 1038 }, 1039 .delay = { 1040 .prepare = 50, 1041 .enable = 200, 1042 .disable = 110, 1043 .unprepare = 1000, 1044 }, 1045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1047 }; 1048 1049 static const struct display_timing auo_p320hvn03_timings = { 1050 .pixelclock = { 106000000, 148500000, 164000000 }, 1051 .hactive = { 1920, 1920, 1920 }, 1052 .hfront_porch = { 25, 50, 130 }, 1053 .hback_porch = { 25, 50, 130 }, 1054 .hsync_len = { 20, 40, 105 }, 1055 .vactive = { 1080, 1080, 1080 }, 1056 .vfront_porch = { 8, 17, 150 }, 1057 .vback_porch = { 8, 17, 150 }, 1058 .vsync_len = { 4, 11, 100 }, 1059 }; 1060 1061 static const struct panel_desc auo_p320hvn03 = { 1062 .timings = &auo_p320hvn03_timings, 1063 .num_timings = 1, 1064 .bpc = 8, 1065 .size = { 1066 .width = 698, 1067 .height = 393, 1068 }, 1069 .delay = { 1070 .prepare = 1, 1071 .enable = 450, 1072 .unprepare = 500, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_t215hvn01_mode = { 1079 .clock = 148800, 1080 .hdisplay = 1920, 1081 .hsync_start = 1920 + 88, 1082 .hsync_end = 1920 + 88 + 44, 1083 .htotal = 1920 + 88 + 44 + 148, 1084 .vdisplay = 1080, 1085 .vsync_start = 1080 + 4, 1086 .vsync_end = 1080 + 4 + 5, 1087 .vtotal = 1080 + 4 + 5 + 36, 1088 }; 1089 1090 static const struct panel_desc auo_t215hvn01 = { 1091 .modes = &auo_t215hvn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 430, 1096 .height = 270, 1097 }, 1098 .delay = { 1099 .disable = 5, 1100 .unprepare = 1000, 1101 } 1102 }; 1103 1104 static const struct drm_display_mode avic_tm070ddh03_mode = { 1105 .clock = 51200, 1106 .hdisplay = 1024, 1107 .hsync_start = 1024 + 160, 1108 .hsync_end = 1024 + 160 + 4, 1109 .htotal = 1024 + 160 + 4 + 156, 1110 .vdisplay = 600, 1111 .vsync_start = 600 + 17, 1112 .vsync_end = 600 + 17 + 1, 1113 .vtotal = 600 + 17 + 1 + 17, 1114 }; 1115 1116 static const struct panel_desc avic_tm070ddh03 = { 1117 .modes = &avic_tm070ddh03_mode, 1118 .num_modes = 1, 1119 .bpc = 8, 1120 .size = { 1121 .width = 154, 1122 .height = 90, 1123 }, 1124 .delay = { 1125 .prepare = 20, 1126 .enable = 200, 1127 .disable = 200, 1128 }, 1129 }; 1130 1131 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1132 .clock = 30000, 1133 .hdisplay = 800, 1134 .hsync_start = 800 + 40, 1135 .hsync_end = 800 + 40 + 48, 1136 .htotal = 800 + 40 + 48 + 40, 1137 .vdisplay = 480, 1138 .vsync_start = 480 + 13, 1139 .vsync_end = 480 + 13 + 3, 1140 .vtotal = 480 + 13 + 3 + 29, 1141 }; 1142 1143 static const struct panel_desc bananapi_s070wv20_ct16 = { 1144 .modes = &bananapi_s070wv20_ct16_mode, 1145 .num_modes = 1, 1146 .bpc = 6, 1147 .size = { 1148 .width = 154, 1149 .height = 86, 1150 }, 1151 }; 1152 1153 static const struct drm_display_mode boe_hv070wsa_mode = { 1154 .clock = 42105, 1155 .hdisplay = 1024, 1156 .hsync_start = 1024 + 30, 1157 .hsync_end = 1024 + 30 + 30, 1158 .htotal = 1024 + 30 + 30 + 30, 1159 .vdisplay = 600, 1160 .vsync_start = 600 + 10, 1161 .vsync_end = 600 + 10 + 10, 1162 .vtotal = 600 + 10 + 10 + 10, 1163 }; 1164 1165 static const struct panel_desc boe_hv070wsa = { 1166 .modes = &boe_hv070wsa_mode, 1167 .num_modes = 1, 1168 .size = { 1169 .width = 154, 1170 .height = 90, 1171 }, 1172 }; 1173 1174 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1175 { 1176 .clock = 71900, 1177 .hdisplay = 1280, 1178 .hsync_start = 1280 + 48, 1179 .hsync_end = 1280 + 48 + 32, 1180 .htotal = 1280 + 48 + 32 + 80, 1181 .vdisplay = 800, 1182 .vsync_start = 800 + 3, 1183 .vsync_end = 800 + 3 + 5, 1184 .vtotal = 800 + 3 + 5 + 24, 1185 }, 1186 { 1187 .clock = 57500, 1188 .hdisplay = 1280, 1189 .hsync_start = 1280 + 48, 1190 .hsync_end = 1280 + 48 + 32, 1191 .htotal = 1280 + 48 + 32 + 80, 1192 .vdisplay = 800, 1193 .vsync_start = 800 + 3, 1194 .vsync_end = 800 + 3 + 5, 1195 .vtotal = 800 + 3 + 5 + 24, 1196 }, 1197 }; 1198 1199 static const struct panel_desc boe_nv101wxmn51 = { 1200 .modes = boe_nv101wxmn51_modes, 1201 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1202 .bpc = 8, 1203 .size = { 1204 .width = 217, 1205 .height = 136, 1206 }, 1207 .delay = { 1208 .prepare = 210, 1209 .enable = 50, 1210 .unprepare = 160, 1211 }, 1212 }; 1213 1214 /* Also used for boe_nv133fhm_n62 */ 1215 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1216 .clock = 147840, 1217 .hdisplay = 1920, 1218 .hsync_start = 1920 + 48, 1219 .hsync_end = 1920 + 48 + 32, 1220 .htotal = 1920 + 48 + 32 + 200, 1221 .vdisplay = 1080, 1222 .vsync_start = 1080 + 3, 1223 .vsync_end = 1080 + 3 + 6, 1224 .vtotal = 1080 + 3 + 6 + 31, 1225 }; 1226 1227 /* Also used for boe_nv133fhm_n62 */ 1228 static const struct panel_desc boe_nv133fhm_n61 = { 1229 .modes = &boe_nv133fhm_n61_modes, 1230 .num_modes = 1, 1231 .bpc = 6, 1232 .size = { 1233 .width = 294, 1234 .height = 165, 1235 }, 1236 .delay = { 1237 .hpd_absent_delay = 200, 1238 .unprepare = 500, 1239 }, 1240 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1241 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1242 .connector_type = DRM_MODE_CONNECTOR_eDP, 1243 }; 1244 1245 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1246 { 1247 .clock = 148500, 1248 .hdisplay = 1920, 1249 .hsync_start = 1920 + 48, 1250 .hsync_end = 1920 + 48 + 32, 1251 .htotal = 2200, 1252 .vdisplay = 1080, 1253 .vsync_start = 1080 + 3, 1254 .vsync_end = 1080 + 3 + 5, 1255 .vtotal = 1125, 1256 }, 1257 }; 1258 1259 static const struct panel_desc boe_nv140fhmn49 = { 1260 .modes = boe_nv140fhmn49_modes, 1261 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1262 .bpc = 6, 1263 .size = { 1264 .width = 309, 1265 .height = 174, 1266 }, 1267 .delay = { 1268 .prepare = 210, 1269 .enable = 50, 1270 .unprepare = 160, 1271 }, 1272 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1273 .connector_type = DRM_MODE_CONNECTOR_eDP, 1274 }; 1275 1276 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1277 .clock = 9000, 1278 .hdisplay = 480, 1279 .hsync_start = 480 + 5, 1280 .hsync_end = 480 + 5 + 5, 1281 .htotal = 480 + 5 + 5 + 40, 1282 .vdisplay = 272, 1283 .vsync_start = 272 + 8, 1284 .vsync_end = 272 + 8 + 8, 1285 .vtotal = 272 + 8 + 8 + 8, 1286 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1287 }; 1288 1289 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1290 .modes = &cdtech_s043wq26h_ct7_mode, 1291 .num_modes = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 95, 1295 .height = 54, 1296 }, 1297 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1298 }; 1299 1300 /* S070PWS19HP-FC21 2017/04/22 */ 1301 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1302 .clock = 51200, 1303 .hdisplay = 1024, 1304 .hsync_start = 1024 + 160, 1305 .hsync_end = 1024 + 160 + 20, 1306 .htotal = 1024 + 160 + 20 + 140, 1307 .vdisplay = 600, 1308 .vsync_start = 600 + 12, 1309 .vsync_end = 600 + 12 + 3, 1310 .vtotal = 600 + 12 + 3 + 20, 1311 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1312 }; 1313 1314 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1315 .modes = &cdtech_s070pws19hp_fc21_mode, 1316 .num_modes = 1, 1317 .bpc = 6, 1318 .size = { 1319 .width = 154, 1320 .height = 86, 1321 }, 1322 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1323 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1324 .connector_type = DRM_MODE_CONNECTOR_DPI, 1325 }; 1326 1327 /* S070SWV29HG-DC44 2017/09/21 */ 1328 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1329 .clock = 33300, 1330 .hdisplay = 800, 1331 .hsync_start = 800 + 210, 1332 .hsync_end = 800 + 210 + 2, 1333 .htotal = 800 + 210 + 2 + 44, 1334 .vdisplay = 480, 1335 .vsync_start = 480 + 22, 1336 .vsync_end = 480 + 22 + 2, 1337 .vtotal = 480 + 22 + 2 + 21, 1338 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1339 }; 1340 1341 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1342 .modes = &cdtech_s070swv29hg_dc44_mode, 1343 .num_modes = 1, 1344 .bpc = 6, 1345 .size = { 1346 .width = 154, 1347 .height = 86, 1348 }, 1349 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1350 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1351 .connector_type = DRM_MODE_CONNECTOR_DPI, 1352 }; 1353 1354 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1355 .clock = 35000, 1356 .hdisplay = 800, 1357 .hsync_start = 800 + 40, 1358 .hsync_end = 800 + 40 + 40, 1359 .htotal = 800 + 40 + 40 + 48, 1360 .vdisplay = 480, 1361 .vsync_start = 480 + 29, 1362 .vsync_end = 480 + 29 + 13, 1363 .vtotal = 480 + 29 + 13 + 3, 1364 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1365 }; 1366 1367 static const struct panel_desc cdtech_s070wv95_ct16 = { 1368 .modes = &cdtech_s070wv95_ct16_mode, 1369 .num_modes = 1, 1370 .bpc = 8, 1371 .size = { 1372 .width = 154, 1373 .height = 85, 1374 }, 1375 }; 1376 1377 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1378 .clock = 66770, 1379 .hdisplay = 800, 1380 .hsync_start = 800 + 49, 1381 .hsync_end = 800 + 49 + 33, 1382 .htotal = 800 + 49 + 33 + 17, 1383 .vdisplay = 1280, 1384 .vsync_start = 1280 + 1, 1385 .vsync_end = 1280 + 1 + 7, 1386 .vtotal = 1280 + 1 + 7 + 15, 1387 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1388 }; 1389 1390 static const struct panel_desc chunghwa_claa070wp03xg = { 1391 .modes = &chunghwa_claa070wp03xg_mode, 1392 .num_modes = 1, 1393 .bpc = 6, 1394 .size = { 1395 .width = 94, 1396 .height = 150, 1397 }, 1398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1399 }; 1400 1401 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1402 .clock = 72070, 1403 .hdisplay = 1366, 1404 .hsync_start = 1366 + 58, 1405 .hsync_end = 1366 + 58 + 58, 1406 .htotal = 1366 + 58 + 58 + 58, 1407 .vdisplay = 768, 1408 .vsync_start = 768 + 4, 1409 .vsync_end = 768 + 4 + 4, 1410 .vtotal = 768 + 4 + 4 + 4, 1411 }; 1412 1413 static const struct panel_desc chunghwa_claa101wa01a = { 1414 .modes = &chunghwa_claa101wa01a_mode, 1415 .num_modes = 1, 1416 .bpc = 6, 1417 .size = { 1418 .width = 220, 1419 .height = 120, 1420 }, 1421 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1422 }; 1423 1424 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1425 .clock = 69300, 1426 .hdisplay = 1366, 1427 .hsync_start = 1366 + 48, 1428 .hsync_end = 1366 + 48 + 32, 1429 .htotal = 1366 + 48 + 32 + 20, 1430 .vdisplay = 768, 1431 .vsync_start = 768 + 16, 1432 .vsync_end = 768 + 16 + 8, 1433 .vtotal = 768 + 16 + 8 + 16, 1434 }; 1435 1436 static const struct panel_desc chunghwa_claa101wb01 = { 1437 .modes = &chunghwa_claa101wb01_mode, 1438 .num_modes = 1, 1439 .bpc = 6, 1440 .size = { 1441 .width = 223, 1442 .height = 125, 1443 }, 1444 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1445 }; 1446 1447 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1448 .clock = 33260, 1449 .hdisplay = 800, 1450 .hsync_start = 800 + 40, 1451 .hsync_end = 800 + 40 + 128, 1452 .htotal = 800 + 40 + 128 + 88, 1453 .vdisplay = 480, 1454 .vsync_start = 480 + 10, 1455 .vsync_end = 480 + 10 + 2, 1456 .vtotal = 480 + 10 + 2 + 33, 1457 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1458 }; 1459 1460 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1461 .modes = &dataimage_scf0700c48ggu18_mode, 1462 .num_modes = 1, 1463 .bpc = 8, 1464 .size = { 1465 .width = 152, 1466 .height = 91, 1467 }, 1468 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1470 }; 1471 1472 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1473 .pixelclock = { 45000000, 51200000, 57000000 }, 1474 .hactive = { 1024, 1024, 1024 }, 1475 .hfront_porch = { 100, 106, 113 }, 1476 .hback_porch = { 100, 106, 113 }, 1477 .hsync_len = { 100, 108, 114 }, 1478 .vactive = { 600, 600, 600 }, 1479 .vfront_porch = { 8, 11, 15 }, 1480 .vback_porch = { 8, 11, 15 }, 1481 .vsync_len = { 9, 13, 15 }, 1482 .flags = DISPLAY_FLAGS_DE_HIGH, 1483 }; 1484 1485 static const struct panel_desc dlc_dlc0700yzg_1 = { 1486 .timings = &dlc_dlc0700yzg_1_timing, 1487 .num_timings = 1, 1488 .bpc = 6, 1489 .size = { 1490 .width = 154, 1491 .height = 86, 1492 }, 1493 .delay = { 1494 .prepare = 30, 1495 .enable = 200, 1496 .disable = 200, 1497 }, 1498 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1499 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1500 }; 1501 1502 static const struct display_timing dlc_dlc1010gig_timing = { 1503 .pixelclock = { 68900000, 71100000, 73400000 }, 1504 .hactive = { 1280, 1280, 1280 }, 1505 .hfront_porch = { 43, 53, 63 }, 1506 .hback_porch = { 43, 53, 63 }, 1507 .hsync_len = { 44, 54, 64 }, 1508 .vactive = { 800, 800, 800 }, 1509 .vfront_porch = { 5, 8, 11 }, 1510 .vback_porch = { 5, 8, 11 }, 1511 .vsync_len = { 5, 7, 11 }, 1512 .flags = DISPLAY_FLAGS_DE_HIGH, 1513 }; 1514 1515 static const struct panel_desc dlc_dlc1010gig = { 1516 .timings = &dlc_dlc1010gig_timing, 1517 .num_timings = 1, 1518 .bpc = 8, 1519 .size = { 1520 .width = 216, 1521 .height = 135, 1522 }, 1523 .delay = { 1524 .prepare = 60, 1525 .enable = 150, 1526 .disable = 100, 1527 .unprepare = 60, 1528 }, 1529 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1530 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1531 }; 1532 1533 static const struct drm_display_mode edt_et035012dm6_mode = { 1534 .clock = 6500, 1535 .hdisplay = 320, 1536 .hsync_start = 320 + 20, 1537 .hsync_end = 320 + 20 + 30, 1538 .htotal = 320 + 20 + 68, 1539 .vdisplay = 240, 1540 .vsync_start = 240 + 4, 1541 .vsync_end = 240 + 4 + 4, 1542 .vtotal = 240 + 4 + 4 + 14, 1543 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1544 }; 1545 1546 static const struct panel_desc edt_et035012dm6 = { 1547 .modes = &edt_et035012dm6_mode, 1548 .num_modes = 1, 1549 .bpc = 8, 1550 .size = { 1551 .width = 70, 1552 .height = 52, 1553 }, 1554 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1555 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1556 }; 1557 1558 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1559 .clock = 10870, 1560 .hdisplay = 480, 1561 .hsync_start = 480 + 8, 1562 .hsync_end = 480 + 8 + 4, 1563 .htotal = 480 + 8 + 4 + 41, 1564 1565 /* 1566 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1567 * fb_align 1568 */ 1569 1570 .vdisplay = 288, 1571 .vsync_start = 288 + 2, 1572 .vsync_end = 288 + 2 + 4, 1573 .vtotal = 288 + 2 + 4 + 10, 1574 }; 1575 1576 static const struct panel_desc edt_etm043080dh6gp = { 1577 .modes = &edt_etm043080dh6gp_mode, 1578 .num_modes = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 100, 1582 .height = 65, 1583 }, 1584 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1585 .connector_type = DRM_MODE_CONNECTOR_DPI, 1586 }; 1587 1588 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1589 .clock = 9000, 1590 .hdisplay = 480, 1591 .hsync_start = 480 + 2, 1592 .hsync_end = 480 + 2 + 41, 1593 .htotal = 480 + 2 + 41 + 2, 1594 .vdisplay = 272, 1595 .vsync_start = 272 + 2, 1596 .vsync_end = 272 + 2 + 10, 1597 .vtotal = 272 + 2 + 10 + 2, 1598 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1599 }; 1600 1601 static const struct panel_desc edt_etm0430g0dh6 = { 1602 .modes = &edt_etm0430g0dh6_mode, 1603 .num_modes = 1, 1604 .bpc = 6, 1605 .size = { 1606 .width = 95, 1607 .height = 54, 1608 }, 1609 }; 1610 1611 static const struct drm_display_mode edt_et057090dhu_mode = { 1612 .clock = 25175, 1613 .hdisplay = 640, 1614 .hsync_start = 640 + 16, 1615 .hsync_end = 640 + 16 + 30, 1616 .htotal = 640 + 16 + 30 + 114, 1617 .vdisplay = 480, 1618 .vsync_start = 480 + 10, 1619 .vsync_end = 480 + 10 + 3, 1620 .vtotal = 480 + 10 + 3 + 32, 1621 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1622 }; 1623 1624 static const struct panel_desc edt_et057090dhu = { 1625 .modes = &edt_et057090dhu_mode, 1626 .num_modes = 1, 1627 .bpc = 6, 1628 .size = { 1629 .width = 115, 1630 .height = 86, 1631 }, 1632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1633 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1634 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1635 }; 1636 1637 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1638 .clock = 33260, 1639 .hdisplay = 800, 1640 .hsync_start = 800 + 40, 1641 .hsync_end = 800 + 40 + 128, 1642 .htotal = 800 + 40 + 128 + 88, 1643 .vdisplay = 480, 1644 .vsync_start = 480 + 10, 1645 .vsync_end = 480 + 10 + 2, 1646 .vtotal = 480 + 10 + 2 + 33, 1647 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1648 }; 1649 1650 static const struct panel_desc edt_etm0700g0dh6 = { 1651 .modes = &edt_etm0700g0dh6_mode, 1652 .num_modes = 1, 1653 .bpc = 6, 1654 .size = { 1655 .width = 152, 1656 .height = 91, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1659 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1660 }; 1661 1662 static const struct panel_desc edt_etm0700g0bdh6 = { 1663 .modes = &edt_etm0700g0dh6_mode, 1664 .num_modes = 1, 1665 .bpc = 6, 1666 .size = { 1667 .width = 152, 1668 .height = 91, 1669 }, 1670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1672 }; 1673 1674 static const struct display_timing evervision_vgg804821_timing = { 1675 .pixelclock = { 27600000, 33300000, 50000000 }, 1676 .hactive = { 800, 800, 800 }, 1677 .hfront_porch = { 40, 66, 70 }, 1678 .hback_porch = { 40, 67, 70 }, 1679 .hsync_len = { 40, 67, 70 }, 1680 .vactive = { 480, 480, 480 }, 1681 .vfront_porch = { 6, 10, 10 }, 1682 .vback_porch = { 7, 11, 11 }, 1683 .vsync_len = { 7, 11, 11 }, 1684 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1685 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1686 DISPLAY_FLAGS_SYNC_NEGEDGE, 1687 }; 1688 1689 static const struct panel_desc evervision_vgg804821 = { 1690 .timings = &evervision_vgg804821_timing, 1691 .num_timings = 1, 1692 .bpc = 8, 1693 .size = { 1694 .width = 108, 1695 .height = 64, 1696 }, 1697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1699 }; 1700 1701 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1702 .clock = 32260, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 168, 1705 .hsync_end = 800 + 168 + 64, 1706 .htotal = 800 + 168 + 64 + 88, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 37, 1709 .vsync_end = 480 + 37 + 2, 1710 .vtotal = 480 + 37 + 2 + 8, 1711 }; 1712 1713 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1714 .modes = &foxlink_fl500wvr00_a0t_mode, 1715 .num_modes = 1, 1716 .bpc = 8, 1717 .size = { 1718 .width = 108, 1719 .height = 65, 1720 }, 1721 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1722 }; 1723 1724 static const struct drm_display_mode frida_frd350h54004_mode = { 1725 .clock = 6000, 1726 .hdisplay = 320, 1727 .hsync_start = 320 + 44, 1728 .hsync_end = 320 + 44 + 16, 1729 .htotal = 320 + 44 + 16 + 20, 1730 .vdisplay = 240, 1731 .vsync_start = 240 + 2, 1732 .vsync_end = 240 + 2 + 6, 1733 .vtotal = 240 + 2 + 6 + 2, 1734 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1735 }; 1736 1737 static const struct panel_desc frida_frd350h54004 = { 1738 .modes = &frida_frd350h54004_mode, 1739 .num_modes = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 77, 1743 .height = 64, 1744 }, 1745 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1746 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1747 .connector_type = DRM_MODE_CONNECTOR_DPI, 1748 }; 1749 1750 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1751 .clock = 67185, 1752 .hdisplay = 800, 1753 .hsync_start = 800 + 20, 1754 .hsync_end = 800 + 20 + 24, 1755 .htotal = 800 + 20 + 24 + 20, 1756 .vdisplay = 1280, 1757 .vsync_start = 1280 + 4, 1758 .vsync_end = 1280 + 4 + 8, 1759 .vtotal = 1280 + 4 + 8 + 4, 1760 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1761 }; 1762 1763 static const struct panel_desc friendlyarm_hd702e = { 1764 .modes = &friendlyarm_hd702e_mode, 1765 .num_modes = 1, 1766 .size = { 1767 .width = 94, 1768 .height = 151, 1769 }, 1770 }; 1771 1772 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1773 .clock = 9000, 1774 .hdisplay = 480, 1775 .hsync_start = 480 + 5, 1776 .hsync_end = 480 + 5 + 1, 1777 .htotal = 480 + 5 + 1 + 40, 1778 .vdisplay = 272, 1779 .vsync_start = 272 + 8, 1780 .vsync_end = 272 + 8 + 1, 1781 .vtotal = 272 + 8 + 1 + 8, 1782 }; 1783 1784 static const struct panel_desc giantplus_gpg482739qs5 = { 1785 .modes = &giantplus_gpg482739qs5_mode, 1786 .num_modes = 1, 1787 .bpc = 8, 1788 .size = { 1789 .width = 95, 1790 .height = 54, 1791 }, 1792 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1793 }; 1794 1795 static const struct display_timing giantplus_gpm940b0_timing = { 1796 .pixelclock = { 13500000, 27000000, 27500000 }, 1797 .hactive = { 320, 320, 320 }, 1798 .hfront_porch = { 14, 686, 718 }, 1799 .hback_porch = { 50, 70, 255 }, 1800 .hsync_len = { 1, 1, 1 }, 1801 .vactive = { 240, 240, 240 }, 1802 .vfront_porch = { 1, 1, 179 }, 1803 .vback_porch = { 1, 21, 31 }, 1804 .vsync_len = { 1, 1, 6 }, 1805 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1806 }; 1807 1808 static const struct panel_desc giantplus_gpm940b0 = { 1809 .timings = &giantplus_gpm940b0_timing, 1810 .num_timings = 1, 1811 .bpc = 8, 1812 .size = { 1813 .width = 60, 1814 .height = 45, 1815 }, 1816 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1818 }; 1819 1820 static const struct display_timing hannstar_hsd070pww1_timing = { 1821 .pixelclock = { 64300000, 71100000, 82000000 }, 1822 .hactive = { 1280, 1280, 1280 }, 1823 .hfront_porch = { 1, 1, 10 }, 1824 .hback_porch = { 1, 1, 10 }, 1825 /* 1826 * According to the data sheet, the minimum horizontal blanking interval 1827 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1828 * minimum working horizontal blanking interval to be 60 clocks. 1829 */ 1830 .hsync_len = { 58, 158, 661 }, 1831 .vactive = { 800, 800, 800 }, 1832 .vfront_porch = { 1, 1, 10 }, 1833 .vback_porch = { 1, 1, 10 }, 1834 .vsync_len = { 1, 21, 203 }, 1835 .flags = DISPLAY_FLAGS_DE_HIGH, 1836 }; 1837 1838 static const struct panel_desc hannstar_hsd070pww1 = { 1839 .timings = &hannstar_hsd070pww1_timing, 1840 .num_timings = 1, 1841 .bpc = 6, 1842 .size = { 1843 .width = 151, 1844 .height = 94, 1845 }, 1846 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1847 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1848 }; 1849 1850 static const struct display_timing hannstar_hsd100pxn1_timing = { 1851 .pixelclock = { 55000000, 65000000, 75000000 }, 1852 .hactive = { 1024, 1024, 1024 }, 1853 .hfront_porch = { 40, 40, 40 }, 1854 .hback_porch = { 220, 220, 220 }, 1855 .hsync_len = { 20, 60, 100 }, 1856 .vactive = { 768, 768, 768 }, 1857 .vfront_porch = { 7, 7, 7 }, 1858 .vback_porch = { 21, 21, 21 }, 1859 .vsync_len = { 10, 10, 10 }, 1860 .flags = DISPLAY_FLAGS_DE_HIGH, 1861 }; 1862 1863 static const struct panel_desc hannstar_hsd100pxn1 = { 1864 .timings = &hannstar_hsd100pxn1_timing, 1865 .num_timings = 1, 1866 .bpc = 6, 1867 .size = { 1868 .width = 203, 1869 .height = 152, 1870 }, 1871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1872 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1873 }; 1874 1875 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1876 .clock = 33333, 1877 .hdisplay = 800, 1878 .hsync_start = 800 + 85, 1879 .hsync_end = 800 + 85 + 86, 1880 .htotal = 800 + 85 + 86 + 85, 1881 .vdisplay = 480, 1882 .vsync_start = 480 + 16, 1883 .vsync_end = 480 + 16 + 13, 1884 .vtotal = 480 + 16 + 13 + 16, 1885 }; 1886 1887 static const struct panel_desc hitachi_tx23d38vm0caa = { 1888 .modes = &hitachi_tx23d38vm0caa_mode, 1889 .num_modes = 1, 1890 .bpc = 6, 1891 .size = { 1892 .width = 195, 1893 .height = 117, 1894 }, 1895 .delay = { 1896 .enable = 160, 1897 .disable = 160, 1898 }, 1899 }; 1900 1901 static const struct drm_display_mode innolux_at043tn24_mode = { 1902 .clock = 9000, 1903 .hdisplay = 480, 1904 .hsync_start = 480 + 2, 1905 .hsync_end = 480 + 2 + 41, 1906 .htotal = 480 + 2 + 41 + 2, 1907 .vdisplay = 272, 1908 .vsync_start = 272 + 2, 1909 .vsync_end = 272 + 2 + 10, 1910 .vtotal = 272 + 2 + 10 + 2, 1911 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1912 }; 1913 1914 static const struct panel_desc innolux_at043tn24 = { 1915 .modes = &innolux_at043tn24_mode, 1916 .num_modes = 1, 1917 .bpc = 8, 1918 .size = { 1919 .width = 95, 1920 .height = 54, 1921 }, 1922 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1923 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1924 }; 1925 1926 static const struct drm_display_mode innolux_at070tn92_mode = { 1927 .clock = 33333, 1928 .hdisplay = 800, 1929 .hsync_start = 800 + 210, 1930 .hsync_end = 800 + 210 + 20, 1931 .htotal = 800 + 210 + 20 + 46, 1932 .vdisplay = 480, 1933 .vsync_start = 480 + 22, 1934 .vsync_end = 480 + 22 + 10, 1935 .vtotal = 480 + 22 + 23 + 10, 1936 }; 1937 1938 static const struct panel_desc innolux_at070tn92 = { 1939 .modes = &innolux_at070tn92_mode, 1940 .num_modes = 1, 1941 .size = { 1942 .width = 154, 1943 .height = 86, 1944 }, 1945 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1946 }; 1947 1948 static const struct display_timing innolux_g070y2_l01_timing = { 1949 .pixelclock = { 28000000, 29500000, 32000000 }, 1950 .hactive = { 800, 800, 800 }, 1951 .hfront_porch = { 61, 91, 141 }, 1952 .hback_porch = { 60, 90, 140 }, 1953 .hsync_len = { 12, 12, 12 }, 1954 .vactive = { 480, 480, 480 }, 1955 .vfront_porch = { 4, 9, 30 }, 1956 .vback_porch = { 4, 8, 28 }, 1957 .vsync_len = { 2, 2, 2 }, 1958 .flags = DISPLAY_FLAGS_DE_HIGH, 1959 }; 1960 1961 static const struct panel_desc innolux_g070y2_l01 = { 1962 .timings = &innolux_g070y2_l01_timing, 1963 .num_timings = 1, 1964 .bpc = 6, 1965 .size = { 1966 .width = 152, 1967 .height = 91, 1968 }, 1969 .delay = { 1970 .prepare = 10, 1971 .enable = 100, 1972 .disable = 100, 1973 .unprepare = 800, 1974 }, 1975 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1976 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1977 }; 1978 1979 static const struct display_timing innolux_g101ice_l01_timing = { 1980 .pixelclock = { 60400000, 71100000, 74700000 }, 1981 .hactive = { 1280, 1280, 1280 }, 1982 .hfront_porch = { 41, 80, 100 }, 1983 .hback_porch = { 40, 79, 99 }, 1984 .hsync_len = { 1, 1, 1 }, 1985 .vactive = { 800, 800, 800 }, 1986 .vfront_porch = { 5, 11, 14 }, 1987 .vback_porch = { 4, 11, 14 }, 1988 .vsync_len = { 1, 1, 1 }, 1989 .flags = DISPLAY_FLAGS_DE_HIGH, 1990 }; 1991 1992 static const struct panel_desc innolux_g101ice_l01 = { 1993 .timings = &innolux_g101ice_l01_timing, 1994 .num_timings = 1, 1995 .bpc = 8, 1996 .size = { 1997 .width = 217, 1998 .height = 135, 1999 }, 2000 .delay = { 2001 .enable = 200, 2002 .disable = 200, 2003 }, 2004 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2006 }; 2007 2008 static const struct display_timing innolux_g121i1_l01_timing = { 2009 .pixelclock = { 67450000, 71000000, 74550000 }, 2010 .hactive = { 1280, 1280, 1280 }, 2011 .hfront_porch = { 40, 80, 160 }, 2012 .hback_porch = { 39, 79, 159 }, 2013 .hsync_len = { 1, 1, 1 }, 2014 .vactive = { 800, 800, 800 }, 2015 .vfront_porch = { 5, 11, 100 }, 2016 .vback_porch = { 4, 11, 99 }, 2017 .vsync_len = { 1, 1, 1 }, 2018 }; 2019 2020 static const struct panel_desc innolux_g121i1_l01 = { 2021 .timings = &innolux_g121i1_l01_timing, 2022 .num_timings = 1, 2023 .bpc = 6, 2024 .size = { 2025 .width = 261, 2026 .height = 163, 2027 }, 2028 .delay = { 2029 .enable = 200, 2030 .disable = 20, 2031 }, 2032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2033 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2034 }; 2035 2036 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2037 .clock = 65000, 2038 .hdisplay = 1024, 2039 .hsync_start = 1024 + 0, 2040 .hsync_end = 1024 + 1, 2041 .htotal = 1024 + 0 + 1 + 320, 2042 .vdisplay = 768, 2043 .vsync_start = 768 + 38, 2044 .vsync_end = 768 + 38 + 1, 2045 .vtotal = 768 + 38 + 1 + 0, 2046 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2047 }; 2048 2049 static const struct panel_desc innolux_g121x1_l03 = { 2050 .modes = &innolux_g121x1_l03_mode, 2051 .num_modes = 1, 2052 .bpc = 6, 2053 .size = { 2054 .width = 246, 2055 .height = 185, 2056 }, 2057 .delay = { 2058 .enable = 200, 2059 .unprepare = 200, 2060 .disable = 400, 2061 }, 2062 }; 2063 2064 /* 2065 * Datasheet specifies that at 60 Hz refresh rate: 2066 * - total horizontal time: { 1506, 1592, 1716 } 2067 * - total vertical time: { 788, 800, 868 } 2068 * 2069 * ...but doesn't go into exactly how that should be split into a front 2070 * porch, back porch, or sync length. For now we'll leave a single setting 2071 * here which allows a bit of tweaking of the pixel clock at the expense of 2072 * refresh rate. 2073 */ 2074 static const struct display_timing innolux_n116bge_timing = { 2075 .pixelclock = { 72600000, 76420000, 80240000 }, 2076 .hactive = { 1366, 1366, 1366 }, 2077 .hfront_porch = { 136, 136, 136 }, 2078 .hback_porch = { 60, 60, 60 }, 2079 .hsync_len = { 30, 30, 30 }, 2080 .vactive = { 768, 768, 768 }, 2081 .vfront_porch = { 8, 8, 8 }, 2082 .vback_porch = { 12, 12, 12 }, 2083 .vsync_len = { 12, 12, 12 }, 2084 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2085 }; 2086 2087 static const struct panel_desc innolux_n116bge = { 2088 .timings = &innolux_n116bge_timing, 2089 .num_timings = 1, 2090 .bpc = 6, 2091 .size = { 2092 .width = 256, 2093 .height = 144, 2094 }, 2095 }; 2096 2097 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2098 .clock = 69300, 2099 .hdisplay = 1366, 2100 .hsync_start = 1366 + 16, 2101 .hsync_end = 1366 + 16 + 34, 2102 .htotal = 1366 + 16 + 34 + 50, 2103 .vdisplay = 768, 2104 .vsync_start = 768 + 2, 2105 .vsync_end = 768 + 2 + 6, 2106 .vtotal = 768 + 2 + 6 + 12, 2107 }; 2108 2109 static const struct panel_desc innolux_n156bge_l21 = { 2110 .modes = &innolux_n156bge_l21_mode, 2111 .num_modes = 1, 2112 .bpc = 6, 2113 .size = { 2114 .width = 344, 2115 .height = 193, 2116 }, 2117 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2118 }; 2119 2120 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2121 .clock = 206016, 2122 .hdisplay = 2160, 2123 .hsync_start = 2160 + 48, 2124 .hsync_end = 2160 + 48 + 32, 2125 .htotal = 2160 + 48 + 32 + 80, 2126 .vdisplay = 1440, 2127 .vsync_start = 1440 + 3, 2128 .vsync_end = 1440 + 3 + 10, 2129 .vtotal = 1440 + 3 + 10 + 27, 2130 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2131 }; 2132 2133 static const struct panel_desc innolux_p120zdg_bf1 = { 2134 .modes = &innolux_p120zdg_bf1_mode, 2135 .num_modes = 1, 2136 .bpc = 8, 2137 .size = { 2138 .width = 254, 2139 .height = 169, 2140 }, 2141 .delay = { 2142 .hpd_absent_delay = 200, 2143 .unprepare = 500, 2144 }, 2145 }; 2146 2147 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2148 .clock = 51501, 2149 .hdisplay = 1024, 2150 .hsync_start = 1024 + 128, 2151 .hsync_end = 1024 + 128 + 64, 2152 .htotal = 1024 + 128 + 64 + 128, 2153 .vdisplay = 600, 2154 .vsync_start = 600 + 16, 2155 .vsync_end = 600 + 16 + 4, 2156 .vtotal = 600 + 16 + 4 + 16, 2157 }; 2158 2159 static const struct panel_desc innolux_zj070na_01p = { 2160 .modes = &innolux_zj070na_01p_mode, 2161 .num_modes = 1, 2162 .bpc = 6, 2163 .size = { 2164 .width = 154, 2165 .height = 90, 2166 }, 2167 }; 2168 2169 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2170 .clock = 138778, 2171 .hdisplay = 1920, 2172 .hsync_start = 1920 + 24, 2173 .hsync_end = 1920 + 24 + 48, 2174 .htotal = 1920 + 24 + 48 + 88, 2175 .vdisplay = 1080, 2176 .vsync_start = 1080 + 3, 2177 .vsync_end = 1080 + 3 + 12, 2178 .vtotal = 1080 + 3 + 12 + 17, 2179 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2180 }; 2181 2182 static const struct panel_desc ivo_m133nwf4_r0 = { 2183 .modes = &ivo_m133nwf4_r0_mode, 2184 .num_modes = 1, 2185 .bpc = 8, 2186 .size = { 2187 .width = 294, 2188 .height = 165, 2189 }, 2190 .delay = { 2191 .hpd_absent_delay = 200, 2192 .unprepare = 500, 2193 }, 2194 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2195 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2196 .connector_type = DRM_MODE_CONNECTOR_eDP, 2197 }; 2198 2199 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2200 .pixelclock = { 5580000, 5850000, 6200000 }, 2201 .hactive = { 320, 320, 320 }, 2202 .hfront_porch = { 30, 30, 30 }, 2203 .hback_porch = { 30, 30, 30 }, 2204 .hsync_len = { 1, 5, 17 }, 2205 .vactive = { 240, 240, 240 }, 2206 .vfront_porch = { 6, 6, 6 }, 2207 .vback_porch = { 5, 5, 5 }, 2208 .vsync_len = { 1, 2, 11 }, 2209 .flags = DISPLAY_FLAGS_DE_HIGH, 2210 }; 2211 2212 static const struct panel_desc koe_tx14d24vm1bpa = { 2213 .timings = &koe_tx14d24vm1bpa_timing, 2214 .num_timings = 1, 2215 .bpc = 6, 2216 .size = { 2217 .width = 115, 2218 .height = 86, 2219 }, 2220 }; 2221 2222 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2223 .pixelclock = { 151820000, 156720000, 159780000 }, 2224 .hactive = { 1920, 1920, 1920 }, 2225 .hfront_porch = { 105, 130, 142 }, 2226 .hback_porch = { 45, 70, 82 }, 2227 .hsync_len = { 30, 30, 30 }, 2228 .vactive = { 1200, 1200, 1200}, 2229 .vfront_porch = { 3, 5, 10 }, 2230 .vback_porch = { 2, 5, 10 }, 2231 .vsync_len = { 5, 5, 5 }, 2232 }; 2233 2234 static const struct panel_desc koe_tx26d202vm0bwa = { 2235 .timings = &koe_tx26d202vm0bwa_timing, 2236 .num_timings = 1, 2237 .bpc = 8, 2238 .size = { 2239 .width = 217, 2240 .height = 136, 2241 }, 2242 .delay = { 2243 .prepare = 1000, 2244 .enable = 1000, 2245 .unprepare = 1000, 2246 .disable = 1000, 2247 }, 2248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2249 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2250 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2251 }; 2252 2253 static const struct display_timing koe_tx31d200vm0baa_timing = { 2254 .pixelclock = { 39600000, 43200000, 48000000 }, 2255 .hactive = { 1280, 1280, 1280 }, 2256 .hfront_porch = { 16, 36, 56 }, 2257 .hback_porch = { 16, 36, 56 }, 2258 .hsync_len = { 8, 8, 8 }, 2259 .vactive = { 480, 480, 480 }, 2260 .vfront_porch = { 6, 21, 33 }, 2261 .vback_porch = { 6, 21, 33 }, 2262 .vsync_len = { 8, 8, 8 }, 2263 .flags = DISPLAY_FLAGS_DE_HIGH, 2264 }; 2265 2266 static const struct panel_desc koe_tx31d200vm0baa = { 2267 .timings = &koe_tx31d200vm0baa_timing, 2268 .num_timings = 1, 2269 .bpc = 6, 2270 .size = { 2271 .width = 292, 2272 .height = 109, 2273 }, 2274 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2276 }; 2277 2278 static const struct display_timing kyo_tcg121xglp_timing = { 2279 .pixelclock = { 52000000, 65000000, 71000000 }, 2280 .hactive = { 1024, 1024, 1024 }, 2281 .hfront_porch = { 2, 2, 2 }, 2282 .hback_porch = { 2, 2, 2 }, 2283 .hsync_len = { 86, 124, 244 }, 2284 .vactive = { 768, 768, 768 }, 2285 .vfront_porch = { 2, 2, 2 }, 2286 .vback_porch = { 2, 2, 2 }, 2287 .vsync_len = { 6, 34, 73 }, 2288 .flags = DISPLAY_FLAGS_DE_HIGH, 2289 }; 2290 2291 static const struct panel_desc kyo_tcg121xglp = { 2292 .timings = &kyo_tcg121xglp_timing, 2293 .num_timings = 1, 2294 .bpc = 8, 2295 .size = { 2296 .width = 246, 2297 .height = 184, 2298 }, 2299 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2300 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2301 }; 2302 2303 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2304 .clock = 7000, 2305 .hdisplay = 320, 2306 .hsync_start = 320 + 20, 2307 .hsync_end = 320 + 20 + 30, 2308 .htotal = 320 + 20 + 30 + 38, 2309 .vdisplay = 240, 2310 .vsync_start = 240 + 4, 2311 .vsync_end = 240 + 4 + 3, 2312 .vtotal = 240 + 4 + 3 + 15, 2313 }; 2314 2315 static const struct panel_desc lemaker_bl035_rgb_002 = { 2316 .modes = &lemaker_bl035_rgb_002_mode, 2317 .num_modes = 1, 2318 .size = { 2319 .width = 70, 2320 .height = 52, 2321 }, 2322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2323 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2324 }; 2325 2326 static const struct drm_display_mode lg_lb070wv8_mode = { 2327 .clock = 33246, 2328 .hdisplay = 800, 2329 .hsync_start = 800 + 88, 2330 .hsync_end = 800 + 88 + 80, 2331 .htotal = 800 + 88 + 80 + 88, 2332 .vdisplay = 480, 2333 .vsync_start = 480 + 10, 2334 .vsync_end = 480 + 10 + 25, 2335 .vtotal = 480 + 10 + 25 + 10, 2336 }; 2337 2338 static const struct panel_desc lg_lb070wv8 = { 2339 .modes = &lg_lb070wv8_mode, 2340 .num_modes = 1, 2341 .bpc = 16, 2342 .size = { 2343 .width = 151, 2344 .height = 91, 2345 }, 2346 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2347 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2348 }; 2349 2350 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2351 .clock = 200000, 2352 .hdisplay = 1536, 2353 .hsync_start = 1536 + 12, 2354 .hsync_end = 1536 + 12 + 16, 2355 .htotal = 1536 + 12 + 16 + 48, 2356 .vdisplay = 2048, 2357 .vsync_start = 2048 + 8, 2358 .vsync_end = 2048 + 8 + 4, 2359 .vtotal = 2048 + 8 + 4 + 8, 2360 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2361 }; 2362 2363 static const struct panel_desc lg_lp079qx1_sp0v = { 2364 .modes = &lg_lp079qx1_sp0v_mode, 2365 .num_modes = 1, 2366 .size = { 2367 .width = 129, 2368 .height = 171, 2369 }, 2370 }; 2371 2372 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2373 .clock = 205210, 2374 .hdisplay = 2048, 2375 .hsync_start = 2048 + 150, 2376 .hsync_end = 2048 + 150 + 5, 2377 .htotal = 2048 + 150 + 5 + 5, 2378 .vdisplay = 1536, 2379 .vsync_start = 1536 + 3, 2380 .vsync_end = 1536 + 3 + 1, 2381 .vtotal = 1536 + 3 + 1 + 9, 2382 }; 2383 2384 static const struct panel_desc lg_lp097qx1_spa1 = { 2385 .modes = &lg_lp097qx1_spa1_mode, 2386 .num_modes = 1, 2387 .size = { 2388 .width = 208, 2389 .height = 147, 2390 }, 2391 }; 2392 2393 static const struct drm_display_mode lg_lp120up1_mode = { 2394 .clock = 162300, 2395 .hdisplay = 1920, 2396 .hsync_start = 1920 + 40, 2397 .hsync_end = 1920 + 40 + 40, 2398 .htotal = 1920 + 40 + 40+ 80, 2399 .vdisplay = 1280, 2400 .vsync_start = 1280 + 4, 2401 .vsync_end = 1280 + 4 + 4, 2402 .vtotal = 1280 + 4 + 4 + 12, 2403 }; 2404 2405 static const struct panel_desc lg_lp120up1 = { 2406 .modes = &lg_lp120up1_mode, 2407 .num_modes = 1, 2408 .bpc = 8, 2409 .size = { 2410 .width = 267, 2411 .height = 183, 2412 }, 2413 .connector_type = DRM_MODE_CONNECTOR_eDP, 2414 }; 2415 2416 static const struct drm_display_mode lg_lp129qe_mode = { 2417 .clock = 285250, 2418 .hdisplay = 2560, 2419 .hsync_start = 2560 + 48, 2420 .hsync_end = 2560 + 48 + 32, 2421 .htotal = 2560 + 48 + 32 + 80, 2422 .vdisplay = 1700, 2423 .vsync_start = 1700 + 3, 2424 .vsync_end = 1700 + 3 + 10, 2425 .vtotal = 1700 + 3 + 10 + 36, 2426 }; 2427 2428 static const struct panel_desc lg_lp129qe = { 2429 .modes = &lg_lp129qe_mode, 2430 .num_modes = 1, 2431 .bpc = 8, 2432 .size = { 2433 .width = 272, 2434 .height = 181, 2435 }, 2436 }; 2437 2438 static const struct display_timing logictechno_lt161010_2nh_timing = { 2439 .pixelclock = { 26400000, 33300000, 46800000 }, 2440 .hactive = { 800, 800, 800 }, 2441 .hfront_porch = { 16, 210, 354 }, 2442 .hback_porch = { 46, 46, 46 }, 2443 .hsync_len = { 1, 20, 40 }, 2444 .vactive = { 480, 480, 480 }, 2445 .vfront_porch = { 7, 22, 147 }, 2446 .vback_porch = { 23, 23, 23 }, 2447 .vsync_len = { 1, 10, 20 }, 2448 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2449 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2450 DISPLAY_FLAGS_SYNC_POSEDGE, 2451 }; 2452 2453 static const struct panel_desc logictechno_lt161010_2nh = { 2454 .timings = &logictechno_lt161010_2nh_timing, 2455 .num_timings = 1, 2456 .size = { 2457 .width = 154, 2458 .height = 86, 2459 }, 2460 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2461 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2462 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2463 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2464 .connector_type = DRM_MODE_CONNECTOR_DPI, 2465 }; 2466 2467 static const struct display_timing logictechno_lt170410_2whc_timing = { 2468 .pixelclock = { 68900000, 71100000, 73400000 }, 2469 .hactive = { 1280, 1280, 1280 }, 2470 .hfront_porch = { 23, 60, 71 }, 2471 .hback_porch = { 23, 60, 71 }, 2472 .hsync_len = { 15, 40, 47 }, 2473 .vactive = { 800, 800, 800 }, 2474 .vfront_porch = { 5, 7, 10 }, 2475 .vback_porch = { 5, 7, 10 }, 2476 .vsync_len = { 6, 9, 12 }, 2477 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2478 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2479 DISPLAY_FLAGS_SYNC_POSEDGE, 2480 }; 2481 2482 static const struct panel_desc logictechno_lt170410_2whc = { 2483 .timings = &logictechno_lt170410_2whc_timing, 2484 .num_timings = 1, 2485 .size = { 2486 .width = 217, 2487 .height = 136, 2488 }, 2489 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2491 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2492 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2493 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2494 }; 2495 2496 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2497 .clock = 30400, 2498 .hdisplay = 800, 2499 .hsync_start = 800 + 0, 2500 .hsync_end = 800 + 1, 2501 .htotal = 800 + 0 + 1 + 160, 2502 .vdisplay = 480, 2503 .vsync_start = 480 + 0, 2504 .vsync_end = 480 + 48 + 1, 2505 .vtotal = 480 + 48 + 1 + 0, 2506 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2507 }; 2508 2509 static const struct drm_display_mode logicpd_type_28_mode = { 2510 .clock = 9107, 2511 .hdisplay = 480, 2512 .hsync_start = 480 + 3, 2513 .hsync_end = 480 + 3 + 42, 2514 .htotal = 480 + 3 + 42 + 2, 2515 2516 .vdisplay = 272, 2517 .vsync_start = 272 + 2, 2518 .vsync_end = 272 + 2 + 11, 2519 .vtotal = 272 + 2 + 11 + 3, 2520 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2521 }; 2522 2523 static const struct panel_desc logicpd_type_28 = { 2524 .modes = &logicpd_type_28_mode, 2525 .num_modes = 1, 2526 .bpc = 8, 2527 .size = { 2528 .width = 105, 2529 .height = 67, 2530 }, 2531 .delay = { 2532 .prepare = 200, 2533 .enable = 200, 2534 .unprepare = 200, 2535 .disable = 200, 2536 }, 2537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2538 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2539 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2540 }; 2541 2542 static const struct panel_desc mitsubishi_aa070mc01 = { 2543 .modes = &mitsubishi_aa070mc01_mode, 2544 .num_modes = 1, 2545 .bpc = 8, 2546 .size = { 2547 .width = 152, 2548 .height = 91, 2549 }, 2550 2551 .delay = { 2552 .enable = 200, 2553 .unprepare = 200, 2554 .disable = 400, 2555 }, 2556 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2557 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2558 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2559 }; 2560 2561 static const struct display_timing nec_nl12880bc20_05_timing = { 2562 .pixelclock = { 67000000, 71000000, 75000000 }, 2563 .hactive = { 1280, 1280, 1280 }, 2564 .hfront_porch = { 2, 30, 30 }, 2565 .hback_porch = { 6, 100, 100 }, 2566 .hsync_len = { 2, 30, 30 }, 2567 .vactive = { 800, 800, 800 }, 2568 .vfront_porch = { 5, 5, 5 }, 2569 .vback_porch = { 11, 11, 11 }, 2570 .vsync_len = { 7, 7, 7 }, 2571 }; 2572 2573 static const struct panel_desc nec_nl12880bc20_05 = { 2574 .timings = &nec_nl12880bc20_05_timing, 2575 .num_timings = 1, 2576 .bpc = 8, 2577 .size = { 2578 .width = 261, 2579 .height = 163, 2580 }, 2581 .delay = { 2582 .enable = 50, 2583 .disable = 50, 2584 }, 2585 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2586 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2587 }; 2588 2589 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2590 .clock = 10870, 2591 .hdisplay = 480, 2592 .hsync_start = 480 + 2, 2593 .hsync_end = 480 + 2 + 41, 2594 .htotal = 480 + 2 + 41 + 2, 2595 .vdisplay = 272, 2596 .vsync_start = 272 + 2, 2597 .vsync_end = 272 + 2 + 4, 2598 .vtotal = 272 + 2 + 4 + 2, 2599 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2600 }; 2601 2602 static const struct panel_desc nec_nl4827hc19_05b = { 2603 .modes = &nec_nl4827hc19_05b_mode, 2604 .num_modes = 1, 2605 .bpc = 8, 2606 .size = { 2607 .width = 95, 2608 .height = 54, 2609 }, 2610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2611 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2612 }; 2613 2614 static const struct drm_display_mode netron_dy_e231732_mode = { 2615 .clock = 66000, 2616 .hdisplay = 1024, 2617 .hsync_start = 1024 + 160, 2618 .hsync_end = 1024 + 160 + 70, 2619 .htotal = 1024 + 160 + 70 + 90, 2620 .vdisplay = 600, 2621 .vsync_start = 600 + 127, 2622 .vsync_end = 600 + 127 + 20, 2623 .vtotal = 600 + 127 + 20 + 3, 2624 }; 2625 2626 static const struct panel_desc netron_dy_e231732 = { 2627 .modes = &netron_dy_e231732_mode, 2628 .num_modes = 1, 2629 .size = { 2630 .width = 154, 2631 .height = 87, 2632 }, 2633 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2634 }; 2635 2636 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2637 { 2638 .clock = 138500, 2639 .hdisplay = 1920, 2640 .hsync_start = 1920 + 48, 2641 .hsync_end = 1920 + 48 + 32, 2642 .htotal = 1920 + 48 + 32 + 80, 2643 .vdisplay = 1080, 2644 .vsync_start = 1080 + 3, 2645 .vsync_end = 1080 + 3 + 5, 2646 .vtotal = 1080 + 3 + 5 + 23, 2647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2648 }, { 2649 .clock = 110920, 2650 .hdisplay = 1920, 2651 .hsync_start = 1920 + 48, 2652 .hsync_end = 1920 + 48 + 32, 2653 .htotal = 1920 + 48 + 32 + 80, 2654 .vdisplay = 1080, 2655 .vsync_start = 1080 + 3, 2656 .vsync_end = 1080 + 3 + 5, 2657 .vtotal = 1080 + 3 + 5 + 23, 2658 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2659 } 2660 }; 2661 2662 static const struct panel_desc neweast_wjfh116008a = { 2663 .modes = neweast_wjfh116008a_modes, 2664 .num_modes = 2, 2665 .bpc = 6, 2666 .size = { 2667 .width = 260, 2668 .height = 150, 2669 }, 2670 .delay = { 2671 .prepare = 110, 2672 .enable = 20, 2673 .unprepare = 500, 2674 }, 2675 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2676 .connector_type = DRM_MODE_CONNECTOR_eDP, 2677 }; 2678 2679 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2680 .clock = 9000, 2681 .hdisplay = 480, 2682 .hsync_start = 480 + 2, 2683 .hsync_end = 480 + 2 + 41, 2684 .htotal = 480 + 2 + 41 + 2, 2685 .vdisplay = 272, 2686 .vsync_start = 272 + 2, 2687 .vsync_end = 272 + 2 + 10, 2688 .vtotal = 272 + 2 + 10 + 2, 2689 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2690 }; 2691 2692 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2693 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2694 .num_modes = 1, 2695 .bpc = 8, 2696 .size = { 2697 .width = 95, 2698 .height = 54, 2699 }, 2700 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2701 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2702 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2703 }; 2704 2705 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2706 .pixelclock = { 130000000, 148350000, 163000000 }, 2707 .hactive = { 1920, 1920, 1920 }, 2708 .hfront_porch = { 80, 100, 100 }, 2709 .hback_porch = { 100, 120, 120 }, 2710 .hsync_len = { 50, 60, 60 }, 2711 .vactive = { 1080, 1080, 1080 }, 2712 .vfront_porch = { 12, 30, 30 }, 2713 .vback_porch = { 4, 10, 10 }, 2714 .vsync_len = { 4, 5, 5 }, 2715 }; 2716 2717 static const struct panel_desc nlt_nl192108ac18_02d = { 2718 .timings = &nlt_nl192108ac18_02d_timing, 2719 .num_timings = 1, 2720 .bpc = 8, 2721 .size = { 2722 .width = 344, 2723 .height = 194, 2724 }, 2725 .delay = { 2726 .unprepare = 500, 2727 }, 2728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2729 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2730 }; 2731 2732 static const struct drm_display_mode nvd_9128_mode = { 2733 .clock = 29500, 2734 .hdisplay = 800, 2735 .hsync_start = 800 + 130, 2736 .hsync_end = 800 + 130 + 98, 2737 .htotal = 800 + 0 + 130 + 98, 2738 .vdisplay = 480, 2739 .vsync_start = 480 + 10, 2740 .vsync_end = 480 + 10 + 50, 2741 .vtotal = 480 + 0 + 10 + 50, 2742 }; 2743 2744 static const struct panel_desc nvd_9128 = { 2745 .modes = &nvd_9128_mode, 2746 .num_modes = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 156, 2750 .height = 88, 2751 }, 2752 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2753 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2754 }; 2755 2756 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2757 .pixelclock = { 30000000, 30000000, 40000000 }, 2758 .hactive = { 800, 800, 800 }, 2759 .hfront_porch = { 40, 40, 40 }, 2760 .hback_porch = { 40, 40, 40 }, 2761 .hsync_len = { 1, 48, 48 }, 2762 .vactive = { 480, 480, 480 }, 2763 .vfront_porch = { 13, 13, 13 }, 2764 .vback_porch = { 29, 29, 29 }, 2765 .vsync_len = { 3, 3, 3 }, 2766 .flags = DISPLAY_FLAGS_DE_HIGH, 2767 }; 2768 2769 static const struct panel_desc okaya_rs800480t_7x0gp = { 2770 .timings = &okaya_rs800480t_7x0gp_timing, 2771 .num_timings = 1, 2772 .bpc = 6, 2773 .size = { 2774 .width = 154, 2775 .height = 87, 2776 }, 2777 .delay = { 2778 .prepare = 41, 2779 .enable = 50, 2780 .unprepare = 41, 2781 .disable = 50, 2782 }, 2783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2784 }; 2785 2786 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2787 .clock = 9000, 2788 .hdisplay = 480, 2789 .hsync_start = 480 + 5, 2790 .hsync_end = 480 + 5 + 30, 2791 .htotal = 480 + 5 + 30 + 10, 2792 .vdisplay = 272, 2793 .vsync_start = 272 + 8, 2794 .vsync_end = 272 + 8 + 5, 2795 .vtotal = 272 + 8 + 5 + 3, 2796 }; 2797 2798 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2799 .modes = &olimex_lcd_olinuxino_43ts_mode, 2800 .num_modes = 1, 2801 .size = { 2802 .width = 95, 2803 .height = 54, 2804 }, 2805 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2806 }; 2807 2808 /* 2809 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2810 * pixel clocks, but this is the timing that was being used in the Adafruit 2811 * installation instructions. 2812 */ 2813 static const struct drm_display_mode ontat_yx700wv03_mode = { 2814 .clock = 29500, 2815 .hdisplay = 800, 2816 .hsync_start = 824, 2817 .hsync_end = 896, 2818 .htotal = 992, 2819 .vdisplay = 480, 2820 .vsync_start = 483, 2821 .vsync_end = 493, 2822 .vtotal = 500, 2823 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2824 }; 2825 2826 /* 2827 * Specification at: 2828 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2829 */ 2830 static const struct panel_desc ontat_yx700wv03 = { 2831 .modes = &ontat_yx700wv03_mode, 2832 .num_modes = 1, 2833 .bpc = 8, 2834 .size = { 2835 .width = 154, 2836 .height = 83, 2837 }, 2838 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2839 }; 2840 2841 static const struct drm_display_mode ortustech_com37h3m_mode = { 2842 .clock = 22230, 2843 .hdisplay = 480, 2844 .hsync_start = 480 + 40, 2845 .hsync_end = 480 + 40 + 10, 2846 .htotal = 480 + 40 + 10 + 40, 2847 .vdisplay = 640, 2848 .vsync_start = 640 + 4, 2849 .vsync_end = 640 + 4 + 2, 2850 .vtotal = 640 + 4 + 2 + 4, 2851 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2852 }; 2853 2854 static const struct panel_desc ortustech_com37h3m = { 2855 .modes = &ortustech_com37h3m_mode, 2856 .num_modes = 1, 2857 .bpc = 8, 2858 .size = { 2859 .width = 56, /* 56.16mm */ 2860 .height = 75, /* 74.88mm */ 2861 }, 2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2863 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2864 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2865 }; 2866 2867 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2868 .clock = 25000, 2869 .hdisplay = 480, 2870 .hsync_start = 480 + 10, 2871 .hsync_end = 480 + 10 + 10, 2872 .htotal = 480 + 10 + 10 + 15, 2873 .vdisplay = 800, 2874 .vsync_start = 800 + 3, 2875 .vsync_end = 800 + 3 + 3, 2876 .vtotal = 800 + 3 + 3 + 3, 2877 }; 2878 2879 static const struct panel_desc ortustech_com43h4m85ulc = { 2880 .modes = &ortustech_com43h4m85ulc_mode, 2881 .num_modes = 1, 2882 .bpc = 8, 2883 .size = { 2884 .width = 56, 2885 .height = 93, 2886 }, 2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2888 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2889 .connector_type = DRM_MODE_CONNECTOR_DPI, 2890 }; 2891 2892 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2893 .clock = 33000, 2894 .hdisplay = 800, 2895 .hsync_start = 800 + 210, 2896 .hsync_end = 800 + 210 + 30, 2897 .htotal = 800 + 210 + 30 + 16, 2898 .vdisplay = 480, 2899 .vsync_start = 480 + 22, 2900 .vsync_end = 480 + 22 + 13, 2901 .vtotal = 480 + 22 + 13 + 10, 2902 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2903 }; 2904 2905 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2906 .modes = &osddisplays_osd070t1718_19ts_mode, 2907 .num_modes = 1, 2908 .bpc = 8, 2909 .size = { 2910 .width = 152, 2911 .height = 91, 2912 }, 2913 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2914 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2915 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2916 .connector_type = DRM_MODE_CONNECTOR_DPI, 2917 }; 2918 2919 static const struct drm_display_mode pda_91_00156_a0_mode = { 2920 .clock = 33300, 2921 .hdisplay = 800, 2922 .hsync_start = 800 + 1, 2923 .hsync_end = 800 + 1 + 64, 2924 .htotal = 800 + 1 + 64 + 64, 2925 .vdisplay = 480, 2926 .vsync_start = 480 + 1, 2927 .vsync_end = 480 + 1 + 23, 2928 .vtotal = 480 + 1 + 23 + 22, 2929 }; 2930 2931 static const struct panel_desc pda_91_00156_a0 = { 2932 .modes = &pda_91_00156_a0_mode, 2933 .num_modes = 1, 2934 .size = { 2935 .width = 152, 2936 .height = 91, 2937 }, 2938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2939 }; 2940 2941 2942 static const struct drm_display_mode qd43003c0_40_mode = { 2943 .clock = 9000, 2944 .hdisplay = 480, 2945 .hsync_start = 480 + 8, 2946 .hsync_end = 480 + 8 + 4, 2947 .htotal = 480 + 8 + 4 + 39, 2948 .vdisplay = 272, 2949 .vsync_start = 272 + 4, 2950 .vsync_end = 272 + 4 + 10, 2951 .vtotal = 272 + 4 + 10 + 2, 2952 }; 2953 2954 static const struct panel_desc qd43003c0_40 = { 2955 .modes = &qd43003c0_40_mode, 2956 .num_modes = 1, 2957 .bpc = 8, 2958 .size = { 2959 .width = 95, 2960 .height = 53, 2961 }, 2962 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2963 }; 2964 2965 static const struct display_timing rocktech_rk070er9427_timing = { 2966 .pixelclock = { 26400000, 33300000, 46800000 }, 2967 .hactive = { 800, 800, 800 }, 2968 .hfront_porch = { 16, 210, 354 }, 2969 .hback_porch = { 46, 46, 46 }, 2970 .hsync_len = { 1, 1, 1 }, 2971 .vactive = { 480, 480, 480 }, 2972 .vfront_porch = { 7, 22, 147 }, 2973 .vback_porch = { 23, 23, 23 }, 2974 .vsync_len = { 1, 1, 1 }, 2975 .flags = DISPLAY_FLAGS_DE_HIGH, 2976 }; 2977 2978 static const struct panel_desc rocktech_rk070er9427 = { 2979 .timings = &rocktech_rk070er9427_timing, 2980 .num_timings = 1, 2981 .bpc = 6, 2982 .size = { 2983 .width = 154, 2984 .height = 86, 2985 }, 2986 .delay = { 2987 .prepare = 41, 2988 .enable = 50, 2989 .unprepare = 41, 2990 .disable = 50, 2991 }, 2992 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2993 }; 2994 2995 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2996 .clock = 71100, 2997 .hdisplay = 1280, 2998 .hsync_start = 1280 + 48, 2999 .hsync_end = 1280 + 48 + 32, 3000 .htotal = 1280 + 48 + 32 + 80, 3001 .vdisplay = 800, 3002 .vsync_start = 800 + 2, 3003 .vsync_end = 800 + 2 + 5, 3004 .vtotal = 800 + 2 + 5 + 16, 3005 }; 3006 3007 static const struct panel_desc rocktech_rk101ii01d_ct = { 3008 .modes = &rocktech_rk101ii01d_ct_mode, 3009 .num_modes = 1, 3010 .size = { 3011 .width = 217, 3012 .height = 136, 3013 }, 3014 .delay = { 3015 .prepare = 50, 3016 .disable = 50, 3017 }, 3018 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3019 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3020 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3021 }; 3022 3023 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3024 .clock = 271560, 3025 .hdisplay = 2560, 3026 .hsync_start = 2560 + 48, 3027 .hsync_end = 2560 + 48 + 32, 3028 .htotal = 2560 + 48 + 32 + 80, 3029 .vdisplay = 1600, 3030 .vsync_start = 1600 + 2, 3031 .vsync_end = 1600 + 2 + 5, 3032 .vtotal = 1600 + 2 + 5 + 57, 3033 }; 3034 3035 static const struct panel_desc samsung_lsn122dl01_c01 = { 3036 .modes = &samsung_lsn122dl01_c01_mode, 3037 .num_modes = 1, 3038 .size = { 3039 .width = 263, 3040 .height = 164, 3041 }, 3042 }; 3043 3044 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3045 .clock = 54030, 3046 .hdisplay = 1024, 3047 .hsync_start = 1024 + 24, 3048 .hsync_end = 1024 + 24 + 136, 3049 .htotal = 1024 + 24 + 136 + 160, 3050 .vdisplay = 600, 3051 .vsync_start = 600 + 3, 3052 .vsync_end = 600 + 3 + 6, 3053 .vtotal = 600 + 3 + 6 + 61, 3054 }; 3055 3056 static const struct panel_desc samsung_ltn101nt05 = { 3057 .modes = &samsung_ltn101nt05_mode, 3058 .num_modes = 1, 3059 .bpc = 6, 3060 .size = { 3061 .width = 223, 3062 .height = 125, 3063 }, 3064 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3065 }; 3066 3067 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3068 .clock = 76300, 3069 .hdisplay = 1366, 3070 .hsync_start = 1366 + 64, 3071 .hsync_end = 1366 + 64 + 48, 3072 .htotal = 1366 + 64 + 48 + 128, 3073 .vdisplay = 768, 3074 .vsync_start = 768 + 2, 3075 .vsync_end = 768 + 2 + 5, 3076 .vtotal = 768 + 2 + 5 + 17, 3077 }; 3078 3079 static const struct panel_desc samsung_ltn140at29_301 = { 3080 .modes = &samsung_ltn140at29_301_mode, 3081 .num_modes = 1, 3082 .bpc = 6, 3083 .size = { 3084 .width = 320, 3085 .height = 187, 3086 }, 3087 }; 3088 3089 static const struct display_timing satoz_sat050at40h12r2_timing = { 3090 .pixelclock = {33300000, 33300000, 50000000}, 3091 .hactive = {800, 800, 800}, 3092 .hfront_porch = {16, 210, 354}, 3093 .hback_porch = {46, 46, 46}, 3094 .hsync_len = {1, 1, 40}, 3095 .vactive = {480, 480, 480}, 3096 .vfront_porch = {7, 22, 147}, 3097 .vback_porch = {23, 23, 23}, 3098 .vsync_len = {1, 1, 20}, 3099 }; 3100 3101 static const struct panel_desc satoz_sat050at40h12r2 = { 3102 .timings = &satoz_sat050at40h12r2_timing, 3103 .num_timings = 1, 3104 .bpc = 8, 3105 .size = { 3106 .width = 108, 3107 .height = 65, 3108 }, 3109 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3111 }; 3112 3113 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3114 .clock = 168480, 3115 .hdisplay = 1920, 3116 .hsync_start = 1920 + 48, 3117 .hsync_end = 1920 + 48 + 32, 3118 .htotal = 1920 + 48 + 32 + 80, 3119 .vdisplay = 1280, 3120 .vsync_start = 1280 + 3, 3121 .vsync_end = 1280 + 3 + 10, 3122 .vtotal = 1280 + 3 + 10 + 57, 3123 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3124 }; 3125 3126 static const struct panel_desc sharp_ld_d5116z01b = { 3127 .modes = &sharp_ld_d5116z01b_mode, 3128 .num_modes = 1, 3129 .bpc = 8, 3130 .size = { 3131 .width = 260, 3132 .height = 120, 3133 }, 3134 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3135 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3136 }; 3137 3138 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3139 .clock = 33260, 3140 .hdisplay = 800, 3141 .hsync_start = 800 + 64, 3142 .hsync_end = 800 + 64 + 128, 3143 .htotal = 800 + 64 + 128 + 64, 3144 .vdisplay = 480, 3145 .vsync_start = 480 + 8, 3146 .vsync_end = 480 + 8 + 2, 3147 .vtotal = 480 + 8 + 2 + 35, 3148 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3149 }; 3150 3151 static const struct panel_desc sharp_lq070y3dg3b = { 3152 .modes = &sharp_lq070y3dg3b_mode, 3153 .num_modes = 1, 3154 .bpc = 8, 3155 .size = { 3156 .width = 152, /* 152.4mm */ 3157 .height = 91, /* 91.4mm */ 3158 }, 3159 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3160 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 3161 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3162 }; 3163 3164 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3165 .clock = 5500, 3166 .hdisplay = 240, 3167 .hsync_start = 240 + 16, 3168 .hsync_end = 240 + 16 + 7, 3169 .htotal = 240 + 16 + 7 + 5, 3170 .vdisplay = 320, 3171 .vsync_start = 320 + 9, 3172 .vsync_end = 320 + 9 + 1, 3173 .vtotal = 320 + 9 + 1 + 7, 3174 }; 3175 3176 static const struct panel_desc sharp_lq035q7db03 = { 3177 .modes = &sharp_lq035q7db03_mode, 3178 .num_modes = 1, 3179 .bpc = 6, 3180 .size = { 3181 .width = 54, 3182 .height = 72, 3183 }, 3184 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3185 }; 3186 3187 static const struct display_timing sharp_lq101k1ly04_timing = { 3188 .pixelclock = { 60000000, 65000000, 80000000 }, 3189 .hactive = { 1280, 1280, 1280 }, 3190 .hfront_porch = { 20, 20, 20 }, 3191 .hback_porch = { 20, 20, 20 }, 3192 .hsync_len = { 10, 10, 10 }, 3193 .vactive = { 800, 800, 800 }, 3194 .vfront_porch = { 4, 4, 4 }, 3195 .vback_porch = { 4, 4, 4 }, 3196 .vsync_len = { 4, 4, 4 }, 3197 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3198 }; 3199 3200 static const struct panel_desc sharp_lq101k1ly04 = { 3201 .timings = &sharp_lq101k1ly04_timing, 3202 .num_timings = 1, 3203 .bpc = 8, 3204 .size = { 3205 .width = 217, 3206 .height = 136, 3207 }, 3208 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3209 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3210 }; 3211 3212 static const struct display_timing sharp_lq123p1jx31_timing = { 3213 .pixelclock = { 252750000, 252750000, 266604720 }, 3214 .hactive = { 2400, 2400, 2400 }, 3215 .hfront_porch = { 48, 48, 48 }, 3216 .hback_porch = { 80, 80, 84 }, 3217 .hsync_len = { 32, 32, 32 }, 3218 .vactive = { 1600, 1600, 1600 }, 3219 .vfront_porch = { 3, 3, 3 }, 3220 .vback_porch = { 33, 33, 120 }, 3221 .vsync_len = { 10, 10, 10 }, 3222 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3223 }; 3224 3225 static const struct panel_desc sharp_lq123p1jx31 = { 3226 .timings = &sharp_lq123p1jx31_timing, 3227 .num_timings = 1, 3228 .bpc = 8, 3229 .size = { 3230 .width = 259, 3231 .height = 173, 3232 }, 3233 .delay = { 3234 .prepare = 110, 3235 .enable = 50, 3236 .unprepare = 550, 3237 }, 3238 }; 3239 3240 static const struct display_timing sharp_ls020b1dd01d_timing = { 3241 .pixelclock = { 2000000, 4200000, 5000000 }, 3242 .hactive = { 240, 240, 240 }, 3243 .hfront_porch = { 66, 66, 66 }, 3244 .hback_porch = { 1, 1, 1 }, 3245 .hsync_len = { 1, 1, 1 }, 3246 .vactive = { 160, 160, 160 }, 3247 .vfront_porch = { 52, 52, 52 }, 3248 .vback_porch = { 6, 6, 6 }, 3249 .vsync_len = { 10, 10, 10 }, 3250 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3251 }; 3252 3253 static const struct panel_desc sharp_ls020b1dd01d = { 3254 .timings = &sharp_ls020b1dd01d_timing, 3255 .num_timings = 1, 3256 .bpc = 6, 3257 .size = { 3258 .width = 42, 3259 .height = 28, 3260 }, 3261 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3262 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3263 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3264 | DRM_BUS_FLAG_SHARP_SIGNALS, 3265 }; 3266 3267 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3268 .clock = 33300, 3269 .hdisplay = 800, 3270 .hsync_start = 800 + 1, 3271 .hsync_end = 800 + 1 + 64, 3272 .htotal = 800 + 1 + 64 + 64, 3273 .vdisplay = 480, 3274 .vsync_start = 480 + 1, 3275 .vsync_end = 480 + 1 + 23, 3276 .vtotal = 480 + 1 + 23 + 22, 3277 }; 3278 3279 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3280 .modes = &shelly_sca07010_bfn_lnn_mode, 3281 .num_modes = 1, 3282 .size = { 3283 .width = 152, 3284 .height = 91, 3285 }, 3286 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3287 }; 3288 3289 static const struct drm_display_mode starry_kr070pe2t_mode = { 3290 .clock = 33000, 3291 .hdisplay = 800, 3292 .hsync_start = 800 + 209, 3293 .hsync_end = 800 + 209 + 1, 3294 .htotal = 800 + 209 + 1 + 45, 3295 .vdisplay = 480, 3296 .vsync_start = 480 + 22, 3297 .vsync_end = 480 + 22 + 1, 3298 .vtotal = 480 + 22 + 1 + 22, 3299 }; 3300 3301 static const struct panel_desc starry_kr070pe2t = { 3302 .modes = &starry_kr070pe2t_mode, 3303 .num_modes = 1, 3304 .bpc = 8, 3305 .size = { 3306 .width = 152, 3307 .height = 86, 3308 }, 3309 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3310 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3311 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3312 }; 3313 3314 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3315 .clock = 147000, 3316 .hdisplay = 1920, 3317 .hsync_start = 1920 + 16, 3318 .hsync_end = 1920 + 16 + 16, 3319 .htotal = 1920 + 16 + 16 + 32, 3320 .vdisplay = 1200, 3321 .vsync_start = 1200 + 15, 3322 .vsync_end = 1200 + 15 + 2, 3323 .vtotal = 1200 + 15 + 2 + 18, 3324 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3325 }; 3326 3327 static const struct panel_desc starry_kr122ea0sra = { 3328 .modes = &starry_kr122ea0sra_mode, 3329 .num_modes = 1, 3330 .size = { 3331 .width = 263, 3332 .height = 164, 3333 }, 3334 .delay = { 3335 .prepare = 10 + 200, 3336 .enable = 50, 3337 .unprepare = 10 + 500, 3338 }, 3339 }; 3340 3341 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3342 .clock = 30000, 3343 .hdisplay = 800, 3344 .hsync_start = 800 + 39, 3345 .hsync_end = 800 + 39 + 47, 3346 .htotal = 800 + 39 + 47 + 39, 3347 .vdisplay = 480, 3348 .vsync_start = 480 + 13, 3349 .vsync_end = 480 + 13 + 2, 3350 .vtotal = 480 + 13 + 2 + 29, 3351 }; 3352 3353 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3354 .modes = &tfc_s9700rtwv43tr_01b_mode, 3355 .num_modes = 1, 3356 .bpc = 8, 3357 .size = { 3358 .width = 155, 3359 .height = 90, 3360 }, 3361 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3362 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3363 }; 3364 3365 static const struct display_timing tianma_tm070jdhg30_timing = { 3366 .pixelclock = { 62600000, 68200000, 78100000 }, 3367 .hactive = { 1280, 1280, 1280 }, 3368 .hfront_porch = { 15, 64, 159 }, 3369 .hback_porch = { 5, 5, 5 }, 3370 .hsync_len = { 1, 1, 256 }, 3371 .vactive = { 800, 800, 800 }, 3372 .vfront_porch = { 3, 40, 99 }, 3373 .vback_porch = { 2, 2, 2 }, 3374 .vsync_len = { 1, 1, 128 }, 3375 .flags = DISPLAY_FLAGS_DE_HIGH, 3376 }; 3377 3378 static const struct panel_desc tianma_tm070jdhg30 = { 3379 .timings = &tianma_tm070jdhg30_timing, 3380 .num_timings = 1, 3381 .bpc = 8, 3382 .size = { 3383 .width = 151, 3384 .height = 95, 3385 }, 3386 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3387 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3388 }; 3389 3390 static const struct panel_desc tianma_tm070jvhg33 = { 3391 .timings = &tianma_tm070jdhg30_timing, 3392 .num_timings = 1, 3393 .bpc = 8, 3394 .size = { 3395 .width = 150, 3396 .height = 94, 3397 }, 3398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3399 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3400 }; 3401 3402 static const struct display_timing tianma_tm070rvhg71_timing = { 3403 .pixelclock = { 27700000, 29200000, 39600000 }, 3404 .hactive = { 800, 800, 800 }, 3405 .hfront_porch = { 12, 40, 212 }, 3406 .hback_porch = { 88, 88, 88 }, 3407 .hsync_len = { 1, 1, 40 }, 3408 .vactive = { 480, 480, 480 }, 3409 .vfront_porch = { 1, 13, 88 }, 3410 .vback_porch = { 32, 32, 32 }, 3411 .vsync_len = { 1, 1, 3 }, 3412 .flags = DISPLAY_FLAGS_DE_HIGH, 3413 }; 3414 3415 static const struct panel_desc tianma_tm070rvhg71 = { 3416 .timings = &tianma_tm070rvhg71_timing, 3417 .num_timings = 1, 3418 .bpc = 8, 3419 .size = { 3420 .width = 154, 3421 .height = 86, 3422 }, 3423 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3425 }; 3426 3427 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3428 { 3429 .clock = 10000, 3430 .hdisplay = 320, 3431 .hsync_start = 320 + 50, 3432 .hsync_end = 320 + 50 + 6, 3433 .htotal = 320 + 50 + 6 + 38, 3434 .vdisplay = 240, 3435 .vsync_start = 240 + 3, 3436 .vsync_end = 240 + 3 + 1, 3437 .vtotal = 240 + 3 + 1 + 17, 3438 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3439 }, 3440 }; 3441 3442 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3443 .modes = ti_nspire_cx_lcd_mode, 3444 .num_modes = 1, 3445 .bpc = 8, 3446 .size = { 3447 .width = 65, 3448 .height = 49, 3449 }, 3450 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3451 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3452 }; 3453 3454 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3455 { 3456 .clock = 10000, 3457 .hdisplay = 320, 3458 .hsync_start = 320 + 6, 3459 .hsync_end = 320 + 6 + 6, 3460 .htotal = 320 + 6 + 6 + 6, 3461 .vdisplay = 240, 3462 .vsync_start = 240 + 0, 3463 .vsync_end = 240 + 0 + 1, 3464 .vtotal = 240 + 0 + 1 + 0, 3465 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3466 }, 3467 }; 3468 3469 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3470 .modes = ti_nspire_classic_lcd_mode, 3471 .num_modes = 1, 3472 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3473 .bpc = 8, 3474 .size = { 3475 .width = 71, 3476 .height = 53, 3477 }, 3478 /* This is the grayscale bus format */ 3479 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3480 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3481 }; 3482 3483 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3484 .clock = 79500, 3485 .hdisplay = 1280, 3486 .hsync_start = 1280 + 192, 3487 .hsync_end = 1280 + 192 + 128, 3488 .htotal = 1280 + 192 + 128 + 64, 3489 .vdisplay = 768, 3490 .vsync_start = 768 + 20, 3491 .vsync_end = 768 + 20 + 7, 3492 .vtotal = 768 + 20 + 7 + 3, 3493 }; 3494 3495 static const struct panel_desc toshiba_lt089ac29000 = { 3496 .modes = &toshiba_lt089ac29000_mode, 3497 .num_modes = 1, 3498 .size = { 3499 .width = 194, 3500 .height = 116, 3501 }, 3502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3503 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3504 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3505 }; 3506 3507 static const struct drm_display_mode tpk_f07a_0102_mode = { 3508 .clock = 33260, 3509 .hdisplay = 800, 3510 .hsync_start = 800 + 40, 3511 .hsync_end = 800 + 40 + 128, 3512 .htotal = 800 + 40 + 128 + 88, 3513 .vdisplay = 480, 3514 .vsync_start = 480 + 10, 3515 .vsync_end = 480 + 10 + 2, 3516 .vtotal = 480 + 10 + 2 + 33, 3517 }; 3518 3519 static const struct panel_desc tpk_f07a_0102 = { 3520 .modes = &tpk_f07a_0102_mode, 3521 .num_modes = 1, 3522 .size = { 3523 .width = 152, 3524 .height = 91, 3525 }, 3526 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3527 }; 3528 3529 static const struct drm_display_mode tpk_f10a_0102_mode = { 3530 .clock = 45000, 3531 .hdisplay = 1024, 3532 .hsync_start = 1024 + 176, 3533 .hsync_end = 1024 + 176 + 5, 3534 .htotal = 1024 + 176 + 5 + 88, 3535 .vdisplay = 600, 3536 .vsync_start = 600 + 20, 3537 .vsync_end = 600 + 20 + 5, 3538 .vtotal = 600 + 20 + 5 + 25, 3539 }; 3540 3541 static const struct panel_desc tpk_f10a_0102 = { 3542 .modes = &tpk_f10a_0102_mode, 3543 .num_modes = 1, 3544 .size = { 3545 .width = 223, 3546 .height = 125, 3547 }, 3548 }; 3549 3550 static const struct display_timing urt_umsh_8596md_timing = { 3551 .pixelclock = { 33260000, 33260000, 33260000 }, 3552 .hactive = { 800, 800, 800 }, 3553 .hfront_porch = { 41, 41, 41 }, 3554 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3555 .hsync_len = { 71, 128, 128 }, 3556 .vactive = { 480, 480, 480 }, 3557 .vfront_porch = { 10, 10, 10 }, 3558 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3559 .vsync_len = { 2, 2, 2 }, 3560 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3561 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3562 }; 3563 3564 static const struct panel_desc urt_umsh_8596md_lvds = { 3565 .timings = &urt_umsh_8596md_timing, 3566 .num_timings = 1, 3567 .bpc = 6, 3568 .size = { 3569 .width = 152, 3570 .height = 91, 3571 }, 3572 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3573 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3574 }; 3575 3576 static const struct panel_desc urt_umsh_8596md_parallel = { 3577 .timings = &urt_umsh_8596md_timing, 3578 .num_timings = 1, 3579 .bpc = 6, 3580 .size = { 3581 .width = 152, 3582 .height = 91, 3583 }, 3584 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3585 }; 3586 3587 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3588 .clock = 33333, 3589 .hdisplay = 800, 3590 .hsync_start = 800 + 210, 3591 .hsync_end = 800 + 210 + 20, 3592 .htotal = 800 + 210 + 20 + 46, 3593 .vdisplay = 480, 3594 .vsync_start = 480 + 22, 3595 .vsync_end = 480 + 22 + 10, 3596 .vtotal = 480 + 22 + 10 + 23, 3597 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3598 }; 3599 3600 static const struct panel_desc vl050_8048nt_c01 = { 3601 .modes = &vl050_8048nt_c01_mode, 3602 .num_modes = 1, 3603 .bpc = 8, 3604 .size = { 3605 .width = 120, 3606 .height = 76, 3607 }, 3608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3609 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3610 }; 3611 3612 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3613 .clock = 6410, 3614 .hdisplay = 320, 3615 .hsync_start = 320 + 20, 3616 .hsync_end = 320 + 20 + 30, 3617 .htotal = 320 + 20 + 30 + 38, 3618 .vdisplay = 240, 3619 .vsync_start = 240 + 4, 3620 .vsync_end = 240 + 4 + 3, 3621 .vtotal = 240 + 4 + 3 + 15, 3622 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3623 }; 3624 3625 static const struct panel_desc winstar_wf35ltiacd = { 3626 .modes = &winstar_wf35ltiacd_mode, 3627 .num_modes = 1, 3628 .bpc = 8, 3629 .size = { 3630 .width = 70, 3631 .height = 53, 3632 }, 3633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3634 }; 3635 3636 static const struct drm_display_mode arm_rtsm_mode[] = { 3637 { 3638 .clock = 65000, 3639 .hdisplay = 1024, 3640 .hsync_start = 1024 + 24, 3641 .hsync_end = 1024 + 24 + 136, 3642 .htotal = 1024 + 24 + 136 + 160, 3643 .vdisplay = 768, 3644 .vsync_start = 768 + 3, 3645 .vsync_end = 768 + 3 + 6, 3646 .vtotal = 768 + 3 + 6 + 29, 3647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3648 }, 3649 }; 3650 3651 static const struct panel_desc arm_rtsm = { 3652 .modes = arm_rtsm_mode, 3653 .num_modes = 1, 3654 .bpc = 8, 3655 .size = { 3656 .width = 400, 3657 .height = 300, 3658 }, 3659 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3660 }; 3661 3662 static const struct of_device_id platform_of_match[] = { 3663 { 3664 .compatible = "ampire,am-480272h3tmqw-t01h", 3665 .data = &ire_am_480272h3tmqw_t01h, 3666 }, { 3667 .compatible = "ampire,am800480r3tmqwa1h", 3668 .data = &ire_am800480r3tmqwa1h, 3669 }, { 3670 .compatible = "arm,rtsm-display", 3671 .data = &arm_rtsm, 3672 }, { 3673 .compatible = "armadeus,st0700-adapt", 3674 .data = &armadeus_st0700_adapt, 3675 }, { 3676 .compatible = "auo,b101aw03", 3677 .data = &auo_b101aw03, 3678 }, { 3679 .compatible = "auo,b101ean01", 3680 .data = &auo_b101ean01, 3681 }, { 3682 .compatible = "auo,b101xtn01", 3683 .data = &auo_b101xtn01, 3684 }, { 3685 .compatible = "auo,b116xa01", 3686 .data = &auo_b116xak01, 3687 }, { 3688 .compatible = "auo,b116xw03", 3689 .data = &auo_b116xw03, 3690 }, { 3691 .compatible = "auo,b133htn01", 3692 .data = &auo_b133htn01, 3693 }, { 3694 .compatible = "auo,b133xtn01", 3695 .data = &auo_b133xtn01, 3696 }, { 3697 .compatible = "auo,g070vvn01", 3698 .data = &auo_g070vvn01, 3699 }, { 3700 .compatible = "auo,g101evn010", 3701 .data = &auo_g101evn010, 3702 }, { 3703 .compatible = "auo,g104sn02", 3704 .data = &auo_g104sn02, 3705 }, { 3706 .compatible = "auo,g121ean01", 3707 .data = &auo_g121ean01, 3708 }, { 3709 .compatible = "auo,g133han01", 3710 .data = &auo_g133han01, 3711 }, { 3712 .compatible = "auo,g156xtn01", 3713 .data = &auo_g156xtn01, 3714 }, { 3715 .compatible = "auo,g185han01", 3716 .data = &auo_g185han01, 3717 }, { 3718 .compatible = "auo,g190ean01", 3719 .data = &auo_g190ean01, 3720 }, { 3721 .compatible = "auo,p320hvn03", 3722 .data = &auo_p320hvn03, 3723 }, { 3724 .compatible = "auo,t215hvn01", 3725 .data = &auo_t215hvn01, 3726 }, { 3727 .compatible = "avic,tm070ddh03", 3728 .data = &avic_tm070ddh03, 3729 }, { 3730 .compatible = "bananapi,s070wv20-ct16", 3731 .data = &bananapi_s070wv20_ct16, 3732 }, { 3733 .compatible = "boe,hv070wsa-100", 3734 .data = &boe_hv070wsa 3735 }, { 3736 .compatible = "boe,nv101wxmn51", 3737 .data = &boe_nv101wxmn51, 3738 }, { 3739 .compatible = "boe,nv133fhm-n61", 3740 .data = &boe_nv133fhm_n61, 3741 }, { 3742 .compatible = "boe,nv133fhm-n62", 3743 .data = &boe_nv133fhm_n61, 3744 }, { 3745 .compatible = "boe,nv140fhmn49", 3746 .data = &boe_nv140fhmn49, 3747 }, { 3748 .compatible = "cdtech,s043wq26h-ct7", 3749 .data = &cdtech_s043wq26h_ct7, 3750 }, { 3751 .compatible = "cdtech,s070pws19hp-fc21", 3752 .data = &cdtech_s070pws19hp_fc21, 3753 }, { 3754 .compatible = "cdtech,s070swv29hg-dc44", 3755 .data = &cdtech_s070swv29hg_dc44, 3756 }, { 3757 .compatible = "cdtech,s070wv95-ct16", 3758 .data = &cdtech_s070wv95_ct16, 3759 }, { 3760 .compatible = "chunghwa,claa070wp03xg", 3761 .data = &chunghwa_claa070wp03xg, 3762 }, { 3763 .compatible = "chunghwa,claa101wa01a", 3764 .data = &chunghwa_claa101wa01a 3765 }, { 3766 .compatible = "chunghwa,claa101wb01", 3767 .data = &chunghwa_claa101wb01 3768 }, { 3769 .compatible = "dataimage,scf0700c48ggu18", 3770 .data = &dataimage_scf0700c48ggu18, 3771 }, { 3772 .compatible = "dlc,dlc0700yzg-1", 3773 .data = &dlc_dlc0700yzg_1, 3774 }, { 3775 .compatible = "dlc,dlc1010gig", 3776 .data = &dlc_dlc1010gig, 3777 }, { 3778 .compatible = "edt,et035012dm6", 3779 .data = &edt_et035012dm6, 3780 }, { 3781 .compatible = "edt,etm043080dh6gp", 3782 .data = &edt_etm043080dh6gp, 3783 }, { 3784 .compatible = "edt,etm0430g0dh6", 3785 .data = &edt_etm0430g0dh6, 3786 }, { 3787 .compatible = "edt,et057090dhu", 3788 .data = &edt_et057090dhu, 3789 }, { 3790 .compatible = "edt,et070080dh6", 3791 .data = &edt_etm0700g0dh6, 3792 }, { 3793 .compatible = "edt,etm0700g0dh6", 3794 .data = &edt_etm0700g0dh6, 3795 }, { 3796 .compatible = "edt,etm0700g0bdh6", 3797 .data = &edt_etm0700g0bdh6, 3798 }, { 3799 .compatible = "edt,etm0700g0edh6", 3800 .data = &edt_etm0700g0bdh6, 3801 }, { 3802 .compatible = "evervision,vgg804821", 3803 .data = &evervision_vgg804821, 3804 }, { 3805 .compatible = "foxlink,fl500wvr00-a0t", 3806 .data = &foxlink_fl500wvr00_a0t, 3807 }, { 3808 .compatible = "frida,frd350h54004", 3809 .data = &frida_frd350h54004, 3810 }, { 3811 .compatible = "friendlyarm,hd702e", 3812 .data = &friendlyarm_hd702e, 3813 }, { 3814 .compatible = "giantplus,gpg482739qs5", 3815 .data = &giantplus_gpg482739qs5 3816 }, { 3817 .compatible = "giantplus,gpm940b0", 3818 .data = &giantplus_gpm940b0, 3819 }, { 3820 .compatible = "hannstar,hsd070pww1", 3821 .data = &hannstar_hsd070pww1, 3822 }, { 3823 .compatible = "hannstar,hsd100pxn1", 3824 .data = &hannstar_hsd100pxn1, 3825 }, { 3826 .compatible = "hit,tx23d38vm0caa", 3827 .data = &hitachi_tx23d38vm0caa 3828 }, { 3829 .compatible = "innolux,at043tn24", 3830 .data = &innolux_at043tn24, 3831 }, { 3832 .compatible = "innolux,at070tn92", 3833 .data = &innolux_at070tn92, 3834 }, { 3835 .compatible = "innolux,g070y2-l01", 3836 .data = &innolux_g070y2_l01, 3837 }, { 3838 .compatible = "innolux,g101ice-l01", 3839 .data = &innolux_g101ice_l01 3840 }, { 3841 .compatible = "innolux,g121i1-l01", 3842 .data = &innolux_g121i1_l01 3843 }, { 3844 .compatible = "innolux,g121x1-l03", 3845 .data = &innolux_g121x1_l03, 3846 }, { 3847 .compatible = "innolux,n116bge", 3848 .data = &innolux_n116bge, 3849 }, { 3850 .compatible = "innolux,n156bge-l21", 3851 .data = &innolux_n156bge_l21, 3852 }, { 3853 .compatible = "innolux,p120zdg-bf1", 3854 .data = &innolux_p120zdg_bf1, 3855 }, { 3856 .compatible = "innolux,zj070na-01p", 3857 .data = &innolux_zj070na_01p, 3858 }, { 3859 .compatible = "ivo,m133nwf4-r0", 3860 .data = &ivo_m133nwf4_r0, 3861 }, { 3862 .compatible = "koe,tx14d24vm1bpa", 3863 .data = &koe_tx14d24vm1bpa, 3864 }, { 3865 .compatible = "koe,tx26d202vm0bwa", 3866 .data = &koe_tx26d202vm0bwa, 3867 }, { 3868 .compatible = "koe,tx31d200vm0baa", 3869 .data = &koe_tx31d200vm0baa, 3870 }, { 3871 .compatible = "kyo,tcg121xglp", 3872 .data = &kyo_tcg121xglp, 3873 }, { 3874 .compatible = "lemaker,bl035-rgb-002", 3875 .data = &lemaker_bl035_rgb_002, 3876 }, { 3877 .compatible = "lg,lb070wv8", 3878 .data = &lg_lb070wv8, 3879 }, { 3880 .compatible = "lg,lp079qx1-sp0v", 3881 .data = &lg_lp079qx1_sp0v, 3882 }, { 3883 .compatible = "lg,lp097qx1-spa1", 3884 .data = &lg_lp097qx1_spa1, 3885 }, { 3886 .compatible = "lg,lp120up1", 3887 .data = &lg_lp120up1, 3888 }, { 3889 .compatible = "lg,lp129qe", 3890 .data = &lg_lp129qe, 3891 }, { 3892 .compatible = "logicpd,type28", 3893 .data = &logicpd_type_28, 3894 }, { 3895 .compatible = "logictechno,lt161010-2nhc", 3896 .data = &logictechno_lt161010_2nh, 3897 }, { 3898 .compatible = "logictechno,lt161010-2nhr", 3899 .data = &logictechno_lt161010_2nh, 3900 }, { 3901 .compatible = "logictechno,lt170410-2whc", 3902 .data = &logictechno_lt170410_2whc, 3903 }, { 3904 .compatible = "mitsubishi,aa070mc01-ca1", 3905 .data = &mitsubishi_aa070mc01, 3906 }, { 3907 .compatible = "nec,nl12880bc20-05", 3908 .data = &nec_nl12880bc20_05, 3909 }, { 3910 .compatible = "nec,nl4827hc19-05b", 3911 .data = &nec_nl4827hc19_05b, 3912 }, { 3913 .compatible = "netron-dy,e231732", 3914 .data = &netron_dy_e231732, 3915 }, { 3916 .compatible = "neweast,wjfh116008a", 3917 .data = &neweast_wjfh116008a, 3918 }, { 3919 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3920 .data = &newhaven_nhd_43_480272ef_atxl, 3921 }, { 3922 .compatible = "nlt,nl192108ac18-02d", 3923 .data = &nlt_nl192108ac18_02d, 3924 }, { 3925 .compatible = "nvd,9128", 3926 .data = &nvd_9128, 3927 }, { 3928 .compatible = "okaya,rs800480t-7x0gp", 3929 .data = &okaya_rs800480t_7x0gp, 3930 }, { 3931 .compatible = "olimex,lcd-olinuxino-43-ts", 3932 .data = &olimex_lcd_olinuxino_43ts, 3933 }, { 3934 .compatible = "ontat,yx700wv03", 3935 .data = &ontat_yx700wv03, 3936 }, { 3937 .compatible = "ortustech,com37h3m05dtc", 3938 .data = &ortustech_com37h3m, 3939 }, { 3940 .compatible = "ortustech,com37h3m99dtc", 3941 .data = &ortustech_com37h3m, 3942 }, { 3943 .compatible = "ortustech,com43h4m85ulc", 3944 .data = &ortustech_com43h4m85ulc, 3945 }, { 3946 .compatible = "osddisplays,osd070t1718-19ts", 3947 .data = &osddisplays_osd070t1718_19ts, 3948 }, { 3949 .compatible = "pda,91-00156-a0", 3950 .data = &pda_91_00156_a0, 3951 }, { 3952 .compatible = "qiaodian,qd43003c0-40", 3953 .data = &qd43003c0_40, 3954 }, { 3955 .compatible = "rocktech,rk070er9427", 3956 .data = &rocktech_rk070er9427, 3957 }, { 3958 .compatible = "rocktech,rk101ii01d-ct", 3959 .data = &rocktech_rk101ii01d_ct, 3960 }, { 3961 .compatible = "samsung,lsn122dl01-c01", 3962 .data = &samsung_lsn122dl01_c01, 3963 }, { 3964 .compatible = "samsung,ltn101nt05", 3965 .data = &samsung_ltn101nt05, 3966 }, { 3967 .compatible = "samsung,ltn140at29-301", 3968 .data = &samsung_ltn140at29_301, 3969 }, { 3970 .compatible = "satoz,sat050at40h12r2", 3971 .data = &satoz_sat050at40h12r2, 3972 }, { 3973 .compatible = "sharp,ld-d5116z01b", 3974 .data = &sharp_ld_d5116z01b, 3975 }, { 3976 .compatible = "sharp,lq035q7db03", 3977 .data = &sharp_lq035q7db03, 3978 }, { 3979 .compatible = "sharp,lq070y3dg3b", 3980 .data = &sharp_lq070y3dg3b, 3981 }, { 3982 .compatible = "sharp,lq101k1ly04", 3983 .data = &sharp_lq101k1ly04, 3984 }, { 3985 .compatible = "sharp,lq123p1jx31", 3986 .data = &sharp_lq123p1jx31, 3987 }, { 3988 .compatible = "sharp,ls020b1dd01d", 3989 .data = &sharp_ls020b1dd01d, 3990 }, { 3991 .compatible = "shelly,sca07010-bfn-lnn", 3992 .data = &shelly_sca07010_bfn_lnn, 3993 }, { 3994 .compatible = "starry,kr070pe2t", 3995 .data = &starry_kr070pe2t, 3996 }, { 3997 .compatible = "starry,kr122ea0sra", 3998 .data = &starry_kr122ea0sra, 3999 }, { 4000 .compatible = "tfc,s9700rtwv43tr-01b", 4001 .data = &tfc_s9700rtwv43tr_01b, 4002 }, { 4003 .compatible = "tianma,tm070jdhg30", 4004 .data = &tianma_tm070jdhg30, 4005 }, { 4006 .compatible = "tianma,tm070jvhg33", 4007 .data = &tianma_tm070jvhg33, 4008 }, { 4009 .compatible = "tianma,tm070rvhg71", 4010 .data = &tianma_tm070rvhg71, 4011 }, { 4012 .compatible = "ti,nspire-cx-lcd-panel", 4013 .data = &ti_nspire_cx_lcd_panel, 4014 }, { 4015 .compatible = "ti,nspire-classic-lcd-panel", 4016 .data = &ti_nspire_classic_lcd_panel, 4017 }, { 4018 .compatible = "toshiba,lt089ac29000", 4019 .data = &toshiba_lt089ac29000, 4020 }, { 4021 .compatible = "tpk,f07a-0102", 4022 .data = &tpk_f07a_0102, 4023 }, { 4024 .compatible = "tpk,f10a-0102", 4025 .data = &tpk_f10a_0102, 4026 }, { 4027 .compatible = "urt,umsh-8596md-t", 4028 .data = &urt_umsh_8596md_parallel, 4029 }, { 4030 .compatible = "urt,umsh-8596md-1t", 4031 .data = &urt_umsh_8596md_parallel, 4032 }, { 4033 .compatible = "urt,umsh-8596md-7t", 4034 .data = &urt_umsh_8596md_parallel, 4035 }, { 4036 .compatible = "urt,umsh-8596md-11t", 4037 .data = &urt_umsh_8596md_lvds, 4038 }, { 4039 .compatible = "urt,umsh-8596md-19t", 4040 .data = &urt_umsh_8596md_lvds, 4041 }, { 4042 .compatible = "urt,umsh-8596md-20t", 4043 .data = &urt_umsh_8596md_parallel, 4044 }, { 4045 .compatible = "vxt,vl050-8048nt-c01", 4046 .data = &vl050_8048nt_c01, 4047 }, { 4048 .compatible = "winstar,wf35ltiacd", 4049 .data = &winstar_wf35ltiacd, 4050 }, { 4051 /* Must be the last entry */ 4052 .compatible = "panel-dpi", 4053 .data = &panel_dpi, 4054 }, { 4055 /* sentinel */ 4056 } 4057 }; 4058 MODULE_DEVICE_TABLE(of, platform_of_match); 4059 4060 static int panel_simple_platform_probe(struct platform_device *pdev) 4061 { 4062 const struct of_device_id *id; 4063 4064 id = of_match_node(platform_of_match, pdev->dev.of_node); 4065 if (!id) 4066 return -ENODEV; 4067 4068 return panel_simple_probe(&pdev->dev, id->data); 4069 } 4070 4071 static int panel_simple_platform_remove(struct platform_device *pdev) 4072 { 4073 return panel_simple_remove(&pdev->dev); 4074 } 4075 4076 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4077 { 4078 panel_simple_shutdown(&pdev->dev); 4079 } 4080 4081 static struct platform_driver panel_simple_platform_driver = { 4082 .driver = { 4083 .name = "panel-simple", 4084 .of_match_table = platform_of_match, 4085 }, 4086 .probe = panel_simple_platform_probe, 4087 .remove = panel_simple_platform_remove, 4088 .shutdown = panel_simple_platform_shutdown, 4089 }; 4090 4091 struct panel_desc_dsi { 4092 struct panel_desc desc; 4093 4094 unsigned long flags; 4095 enum mipi_dsi_pixel_format format; 4096 unsigned int lanes; 4097 }; 4098 4099 static const struct drm_display_mode auo_b080uan01_mode = { 4100 .clock = 154500, 4101 .hdisplay = 1200, 4102 .hsync_start = 1200 + 62, 4103 .hsync_end = 1200 + 62 + 4, 4104 .htotal = 1200 + 62 + 4 + 62, 4105 .vdisplay = 1920, 4106 .vsync_start = 1920 + 9, 4107 .vsync_end = 1920 + 9 + 2, 4108 .vtotal = 1920 + 9 + 2 + 8, 4109 }; 4110 4111 static const struct panel_desc_dsi auo_b080uan01 = { 4112 .desc = { 4113 .modes = &auo_b080uan01_mode, 4114 .num_modes = 1, 4115 .bpc = 8, 4116 .size = { 4117 .width = 108, 4118 .height = 272, 4119 }, 4120 .connector_type = DRM_MODE_CONNECTOR_DSI, 4121 }, 4122 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4123 .format = MIPI_DSI_FMT_RGB888, 4124 .lanes = 4, 4125 }; 4126 4127 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4128 .clock = 160000, 4129 .hdisplay = 1200, 4130 .hsync_start = 1200 + 120, 4131 .hsync_end = 1200 + 120 + 20, 4132 .htotal = 1200 + 120 + 20 + 21, 4133 .vdisplay = 1920, 4134 .vsync_start = 1920 + 21, 4135 .vsync_end = 1920 + 21 + 3, 4136 .vtotal = 1920 + 21 + 3 + 18, 4137 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4138 }; 4139 4140 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4141 .desc = { 4142 .modes = &boe_tv080wum_nl0_mode, 4143 .num_modes = 1, 4144 .size = { 4145 .width = 107, 4146 .height = 172, 4147 }, 4148 .connector_type = DRM_MODE_CONNECTOR_DSI, 4149 }, 4150 .flags = MIPI_DSI_MODE_VIDEO | 4151 MIPI_DSI_MODE_VIDEO_BURST | 4152 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4153 .format = MIPI_DSI_FMT_RGB888, 4154 .lanes = 4, 4155 }; 4156 4157 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4158 .clock = 71000, 4159 .hdisplay = 800, 4160 .hsync_start = 800 + 32, 4161 .hsync_end = 800 + 32 + 1, 4162 .htotal = 800 + 32 + 1 + 57, 4163 .vdisplay = 1280, 4164 .vsync_start = 1280 + 28, 4165 .vsync_end = 1280 + 28 + 1, 4166 .vtotal = 1280 + 28 + 1 + 14, 4167 }; 4168 4169 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4170 .desc = { 4171 .modes = &lg_ld070wx3_sl01_mode, 4172 .num_modes = 1, 4173 .bpc = 8, 4174 .size = { 4175 .width = 94, 4176 .height = 151, 4177 }, 4178 .connector_type = DRM_MODE_CONNECTOR_DSI, 4179 }, 4180 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4181 .format = MIPI_DSI_FMT_RGB888, 4182 .lanes = 4, 4183 }; 4184 4185 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4186 .clock = 67000, 4187 .hdisplay = 720, 4188 .hsync_start = 720 + 12, 4189 .hsync_end = 720 + 12 + 4, 4190 .htotal = 720 + 12 + 4 + 112, 4191 .vdisplay = 1280, 4192 .vsync_start = 1280 + 8, 4193 .vsync_end = 1280 + 8 + 4, 4194 .vtotal = 1280 + 8 + 4 + 12, 4195 }; 4196 4197 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4198 .desc = { 4199 .modes = &lg_lh500wx1_sd03_mode, 4200 .num_modes = 1, 4201 .bpc = 8, 4202 .size = { 4203 .width = 62, 4204 .height = 110, 4205 }, 4206 .connector_type = DRM_MODE_CONNECTOR_DSI, 4207 }, 4208 .flags = MIPI_DSI_MODE_VIDEO, 4209 .format = MIPI_DSI_FMT_RGB888, 4210 .lanes = 4, 4211 }; 4212 4213 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4214 .clock = 157200, 4215 .hdisplay = 1920, 4216 .hsync_start = 1920 + 154, 4217 .hsync_end = 1920 + 154 + 16, 4218 .htotal = 1920 + 154 + 16 + 32, 4219 .vdisplay = 1200, 4220 .vsync_start = 1200 + 17, 4221 .vsync_end = 1200 + 17 + 2, 4222 .vtotal = 1200 + 17 + 2 + 16, 4223 }; 4224 4225 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4226 .desc = { 4227 .modes = &panasonic_vvx10f004b00_mode, 4228 .num_modes = 1, 4229 .bpc = 8, 4230 .size = { 4231 .width = 217, 4232 .height = 136, 4233 }, 4234 .connector_type = DRM_MODE_CONNECTOR_DSI, 4235 }, 4236 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4237 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4238 .format = MIPI_DSI_FMT_RGB888, 4239 .lanes = 4, 4240 }; 4241 4242 static const struct drm_display_mode lg_acx467akm_7_mode = { 4243 .clock = 150000, 4244 .hdisplay = 1080, 4245 .hsync_start = 1080 + 2, 4246 .hsync_end = 1080 + 2 + 2, 4247 .htotal = 1080 + 2 + 2 + 2, 4248 .vdisplay = 1920, 4249 .vsync_start = 1920 + 2, 4250 .vsync_end = 1920 + 2 + 2, 4251 .vtotal = 1920 + 2 + 2 + 2, 4252 }; 4253 4254 static const struct panel_desc_dsi lg_acx467akm_7 = { 4255 .desc = { 4256 .modes = &lg_acx467akm_7_mode, 4257 .num_modes = 1, 4258 .bpc = 8, 4259 .size = { 4260 .width = 62, 4261 .height = 110, 4262 }, 4263 .connector_type = DRM_MODE_CONNECTOR_DSI, 4264 }, 4265 .flags = 0, 4266 .format = MIPI_DSI_FMT_RGB888, 4267 .lanes = 4, 4268 }; 4269 4270 static const struct drm_display_mode osd101t2045_53ts_mode = { 4271 .clock = 154500, 4272 .hdisplay = 1920, 4273 .hsync_start = 1920 + 112, 4274 .hsync_end = 1920 + 112 + 16, 4275 .htotal = 1920 + 112 + 16 + 32, 4276 .vdisplay = 1200, 4277 .vsync_start = 1200 + 16, 4278 .vsync_end = 1200 + 16 + 2, 4279 .vtotal = 1200 + 16 + 2 + 16, 4280 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4281 }; 4282 4283 static const struct panel_desc_dsi osd101t2045_53ts = { 4284 .desc = { 4285 .modes = &osd101t2045_53ts_mode, 4286 .num_modes = 1, 4287 .bpc = 8, 4288 .size = { 4289 .width = 217, 4290 .height = 136, 4291 }, 4292 .connector_type = DRM_MODE_CONNECTOR_DSI, 4293 }, 4294 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4295 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4296 MIPI_DSI_MODE_EOT_PACKET, 4297 .format = MIPI_DSI_FMT_RGB888, 4298 .lanes = 4, 4299 }; 4300 4301 static const struct of_device_id dsi_of_match[] = { 4302 { 4303 .compatible = "auo,b080uan01", 4304 .data = &auo_b080uan01 4305 }, { 4306 .compatible = "boe,tv080wum-nl0", 4307 .data = &boe_tv080wum_nl0 4308 }, { 4309 .compatible = "lg,ld070wx3-sl01", 4310 .data = &lg_ld070wx3_sl01 4311 }, { 4312 .compatible = "lg,lh500wx1-sd03", 4313 .data = &lg_lh500wx1_sd03 4314 }, { 4315 .compatible = "panasonic,vvx10f004b00", 4316 .data = &panasonic_vvx10f004b00 4317 }, { 4318 .compatible = "lg,acx467akm-7", 4319 .data = &lg_acx467akm_7 4320 }, { 4321 .compatible = "osddisplays,osd101t2045-53ts", 4322 .data = &osd101t2045_53ts 4323 }, { 4324 /* sentinel */ 4325 } 4326 }; 4327 MODULE_DEVICE_TABLE(of, dsi_of_match); 4328 4329 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4330 { 4331 const struct panel_desc_dsi *desc; 4332 const struct of_device_id *id; 4333 int err; 4334 4335 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4336 if (!id) 4337 return -ENODEV; 4338 4339 desc = id->data; 4340 4341 err = panel_simple_probe(&dsi->dev, &desc->desc); 4342 if (err < 0) 4343 return err; 4344 4345 dsi->mode_flags = desc->flags; 4346 dsi->format = desc->format; 4347 dsi->lanes = desc->lanes; 4348 4349 err = mipi_dsi_attach(dsi); 4350 if (err) { 4351 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4352 4353 drm_panel_remove(&panel->base); 4354 } 4355 4356 return err; 4357 } 4358 4359 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4360 { 4361 int err; 4362 4363 err = mipi_dsi_detach(dsi); 4364 if (err < 0) 4365 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4366 4367 return panel_simple_remove(&dsi->dev); 4368 } 4369 4370 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4371 { 4372 panel_simple_shutdown(&dsi->dev); 4373 } 4374 4375 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4376 .driver = { 4377 .name = "panel-simple-dsi", 4378 .of_match_table = dsi_of_match, 4379 }, 4380 .probe = panel_simple_dsi_probe, 4381 .remove = panel_simple_dsi_remove, 4382 .shutdown = panel_simple_dsi_shutdown, 4383 }; 4384 4385 static int __init panel_simple_init(void) 4386 { 4387 int err; 4388 4389 err = platform_driver_register(&panel_simple_platform_driver); 4390 if (err < 0) 4391 return err; 4392 4393 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4394 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4395 if (err < 0) 4396 return err; 4397 } 4398 4399 return 0; 4400 } 4401 module_init(panel_simple_init); 4402 4403 static void __exit panel_simple_exit(void) 4404 { 4405 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4406 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4407 4408 platform_driver_unregister(&panel_simple_platform_driver); 4409 } 4410 module_exit(panel_simple_exit); 4411 4412 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4413 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4414 MODULE_LICENSE("GPL and additional rights"); 4415