1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t unprepared_time; 145 146 const struct panel_desc *desc; 147 148 struct regulator *supply; 149 struct i2c_adapter *ddc; 150 151 struct gpio_desc *enable_gpio; 152 153 struct edid *edid; 154 155 struct drm_display_mode override_mode; 156 157 enum drm_panel_orientation orientation; 158 }; 159 160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 161 { 162 return container_of(panel, struct panel_simple, base); 163 } 164 165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 166 struct drm_connector *connector) 167 { 168 struct drm_display_mode *mode; 169 unsigned int i, num = 0; 170 171 for (i = 0; i < panel->desc->num_timings; i++) { 172 const struct display_timing *dt = &panel->desc->timings[i]; 173 struct videomode vm; 174 175 videomode_from_timing(dt, &vm); 176 mode = drm_mode_create(connector->dev); 177 if (!mode) { 178 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 179 dt->hactive.typ, dt->vactive.typ); 180 continue; 181 } 182 183 drm_display_mode_from_videomode(&vm, mode); 184 185 mode->type |= DRM_MODE_TYPE_DRIVER; 186 187 if (panel->desc->num_timings == 1) 188 mode->type |= DRM_MODE_TYPE_PREFERRED; 189 190 drm_mode_probed_add(connector, mode); 191 num++; 192 } 193 194 return num; 195 } 196 197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 198 struct drm_connector *connector) 199 { 200 struct drm_display_mode *mode; 201 unsigned int i, num = 0; 202 203 for (i = 0; i < panel->desc->num_modes; i++) { 204 const struct drm_display_mode *m = &panel->desc->modes[i]; 205 206 mode = drm_mode_duplicate(connector->dev, m); 207 if (!mode) { 208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 209 m->hdisplay, m->vdisplay, 210 drm_mode_vrefresh(m)); 211 continue; 212 } 213 214 mode->type |= DRM_MODE_TYPE_DRIVER; 215 216 if (panel->desc->num_modes == 1) 217 mode->type |= DRM_MODE_TYPE_PREFERRED; 218 219 drm_mode_set_name(mode); 220 221 drm_mode_probed_add(connector, mode); 222 num++; 223 } 224 225 return num; 226 } 227 228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 229 struct drm_connector *connector) 230 { 231 struct drm_display_mode *mode; 232 bool has_override = panel->override_mode.type; 233 unsigned int num = 0; 234 235 if (!panel->desc) 236 return 0; 237 238 if (has_override) { 239 mode = drm_mode_duplicate(connector->dev, 240 &panel->override_mode); 241 if (mode) { 242 drm_mode_probed_add(connector, mode); 243 num = 1; 244 } else { 245 dev_err(panel->base.dev, "failed to add override mode\n"); 246 } 247 } 248 249 /* Only add timings if override was not there or failed to validate */ 250 if (num == 0 && panel->desc->num_timings) 251 num = panel_simple_get_timings_modes(panel, connector); 252 253 /* 254 * Only add fixed modes if timings/override added no mode. 255 * 256 * We should only ever have either the display timings specified 257 * or a fixed mode. Anything else is rather bogus. 258 */ 259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 260 if (num == 0) 261 num = panel_simple_get_display_modes(panel, connector); 262 263 connector->display_info.bpc = panel->desc->bpc; 264 connector->display_info.width_mm = panel->desc->size.width; 265 connector->display_info.height_mm = panel->desc->size.height; 266 if (panel->desc->bus_format) 267 drm_display_info_set_bus_formats(&connector->display_info, 268 &panel->desc->bus_format, 1); 269 connector->display_info.bus_flags = panel->desc->bus_flags; 270 271 return num; 272 } 273 274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 275 { 276 ktime_t now_ktime, min_ktime; 277 278 if (!min_ms) 279 return; 280 281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 282 now_ktime = ktime_get_boottime(); 283 284 if (ktime_before(now_ktime, min_ktime)) 285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 286 } 287 288 static int panel_simple_disable(struct drm_panel *panel) 289 { 290 struct panel_simple *p = to_panel_simple(panel); 291 292 if (!p->enabled) 293 return 0; 294 295 if (p->desc->delay.disable) 296 msleep(p->desc->delay.disable); 297 298 p->enabled = false; 299 300 return 0; 301 } 302 303 static int panel_simple_suspend(struct device *dev) 304 { 305 struct panel_simple *p = dev_get_drvdata(dev); 306 307 gpiod_set_value_cansleep(p->enable_gpio, 0); 308 regulator_disable(p->supply); 309 p->unprepared_time = ktime_get_boottime(); 310 311 kfree(p->edid); 312 p->edid = NULL; 313 314 return 0; 315 } 316 317 static int panel_simple_unprepare(struct drm_panel *panel) 318 { 319 struct panel_simple *p = to_panel_simple(panel); 320 int ret; 321 322 /* Unpreparing when already unprepared is a no-op */ 323 if (!p->prepared) 324 return 0; 325 326 pm_runtime_mark_last_busy(panel->dev); 327 ret = pm_runtime_put_autosuspend(panel->dev); 328 if (ret < 0) 329 return ret; 330 p->prepared = false; 331 332 return 0; 333 } 334 335 static int panel_simple_resume(struct device *dev) 336 { 337 struct panel_simple *p = dev_get_drvdata(dev); 338 int err; 339 340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 341 342 err = regulator_enable(p->supply); 343 if (err < 0) { 344 dev_err(dev, "failed to enable supply: %d\n", err); 345 return err; 346 } 347 348 gpiod_set_value_cansleep(p->enable_gpio, 1); 349 350 if (p->desc->delay.prepare) 351 msleep(p->desc->delay.prepare); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* 415 * TODO: Remove once all drm drivers call 416 * drm_connector_set_orientation_from_panel() 417 */ 418 drm_connector_set_panel_orientation(connector, p->orientation); 419 420 return num; 421 } 422 423 static int panel_simple_get_timings(struct drm_panel *panel, 424 unsigned int num_timings, 425 struct display_timing *timings) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 unsigned int i; 429 430 if (p->desc->num_timings < num_timings) 431 num_timings = p->desc->num_timings; 432 433 if (timings) 434 for (i = 0; i < num_timings; i++) 435 timings[i] = p->desc->timings[i]; 436 437 return p->desc->num_timings; 438 } 439 440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 441 { 442 struct panel_simple *p = to_panel_simple(panel); 443 444 return p->orientation; 445 } 446 447 static const struct drm_panel_funcs panel_simple_funcs = { 448 .disable = panel_simple_disable, 449 .unprepare = panel_simple_unprepare, 450 .prepare = panel_simple_prepare, 451 .enable = panel_simple_enable, 452 .get_modes = panel_simple_get_modes, 453 .get_orientation = panel_simple_get_orientation, 454 .get_timings = panel_simple_get_timings, 455 }; 456 457 static struct panel_desc panel_dpi; 458 459 static int panel_dpi_probe(struct device *dev, 460 struct panel_simple *panel) 461 { 462 struct display_timing *timing; 463 const struct device_node *np; 464 struct panel_desc *desc; 465 unsigned int bus_flags; 466 struct videomode vm; 467 int ret; 468 469 np = dev->of_node; 470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 471 if (!desc) 472 return -ENOMEM; 473 474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 475 if (!timing) 476 return -ENOMEM; 477 478 ret = of_get_display_timing(np, "panel-timing", timing); 479 if (ret < 0) { 480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 481 np); 482 return ret; 483 } 484 485 desc->timings = timing; 486 desc->num_timings = 1; 487 488 of_property_read_u32(np, "width-mm", &desc->size.width); 489 of_property_read_u32(np, "height-mm", &desc->size.height); 490 491 /* Extract bus_flags from display_timing */ 492 bus_flags = 0; 493 vm.flags = timing->flags; 494 drm_bus_flags_from_videomode(&vm, &bus_flags); 495 desc->bus_flags = bus_flags; 496 497 /* We do not know the connector for the DT node, so guess it */ 498 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 499 500 panel->desc = desc; 501 502 return 0; 503 } 504 505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 506 (to_check->field.typ >= bounds->field.min && \ 507 to_check->field.typ <= bounds->field.max) 508 static void panel_simple_parse_panel_timing_node(struct device *dev, 509 struct panel_simple *panel, 510 const struct display_timing *ot) 511 { 512 const struct panel_desc *desc = panel->desc; 513 struct videomode vm; 514 unsigned int i; 515 516 if (WARN_ON(desc->num_modes)) { 517 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 518 return; 519 } 520 if (WARN_ON(!desc->num_timings)) { 521 dev_err(dev, "Reject override mode: no timings specified\n"); 522 return; 523 } 524 525 for (i = 0; i < panel->desc->num_timings; i++) { 526 const struct display_timing *dt = &panel->desc->timings[i]; 527 528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 536 continue; 537 538 if (ot->flags != dt->flags) 539 continue; 540 541 videomode_from_timing(ot, &vm); 542 drm_display_mode_from_videomode(&vm, &panel->override_mode); 543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 544 DRM_MODE_TYPE_PREFERRED; 545 break; 546 } 547 548 if (WARN_ON(!panel->override_mode.type)) 549 dev_err(dev, "Reject override mode: No display_timing found\n"); 550 } 551 552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 553 { 554 struct panel_simple *panel; 555 struct display_timing dt; 556 struct device_node *ddc; 557 int connector_type; 558 u32 bus_flags; 559 int err; 560 561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 562 if (!panel) 563 return -ENOMEM; 564 565 panel->enabled = false; 566 panel->desc = desc; 567 568 panel->supply = devm_regulator_get(dev, "power"); 569 if (IS_ERR(panel->supply)) 570 return PTR_ERR(panel->supply); 571 572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 573 GPIOD_OUT_LOW); 574 if (IS_ERR(panel->enable_gpio)) 575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 576 "failed to request GPIO\n"); 577 578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 579 if (err) { 580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 581 return err; 582 } 583 584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 585 if (ddc) { 586 panel->ddc = of_find_i2c_adapter_by_node(ddc); 587 of_node_put(ddc); 588 589 if (!panel->ddc) 590 return -EPROBE_DEFER; 591 } 592 593 if (desc == &panel_dpi) { 594 /* Handle the generic panel-dpi binding */ 595 err = panel_dpi_probe(dev, panel); 596 if (err) 597 goto free_ddc; 598 desc = panel->desc; 599 } else { 600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 601 panel_simple_parse_panel_timing_node(dev, panel, &dt); 602 } 603 604 connector_type = desc->connector_type; 605 /* Catch common mistakes for panels. */ 606 switch (connector_type) { 607 case 0: 608 dev_warn(dev, "Specify missing connector_type\n"); 609 connector_type = DRM_MODE_CONNECTOR_DPI; 610 break; 611 case DRM_MODE_CONNECTOR_LVDS: 612 WARN_ON(desc->bus_flags & 613 ~(DRM_BUS_FLAG_DE_LOW | 614 DRM_BUS_FLAG_DE_HIGH | 615 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 616 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 621 desc->bpc != 6); 622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 624 desc->bpc != 8); 625 break; 626 case DRM_MODE_CONNECTOR_eDP: 627 dev_warn(dev, "eDP panels moved to panel-edp\n"); 628 err = -EINVAL; 629 goto free_ddc; 630 case DRM_MODE_CONNECTOR_DSI: 631 if (desc->bpc != 6 && desc->bpc != 8) 632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 633 break; 634 case DRM_MODE_CONNECTOR_DPI: 635 bus_flags = DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 639 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 640 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 643 if (desc->bus_flags & ~bus_flags) 644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 645 if (!(desc->bus_flags & bus_flags)) 646 dev_warn(dev, "Specify missing bus_flags\n"); 647 if (desc->bus_format == 0) 648 dev_warn(dev, "Specify missing bus_format\n"); 649 if (desc->bpc != 6 && desc->bpc != 8) 650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 651 break; 652 default: 653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 654 connector_type = DRM_MODE_CONNECTOR_DPI; 655 break; 656 } 657 658 dev_set_drvdata(dev, panel); 659 660 /* 661 * We use runtime PM for prepare / unprepare since those power the panel 662 * on and off and those can be very slow operations. This is important 663 * to optimize powering the panel on briefly to read the EDID before 664 * fully enabling the panel. 665 */ 666 pm_runtime_enable(dev); 667 pm_runtime_set_autosuspend_delay(dev, 1000); 668 pm_runtime_use_autosuspend(dev); 669 670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 671 672 err = drm_panel_of_backlight(&panel->base); 673 if (err) { 674 dev_err_probe(dev, err, "Could not find backlight\n"); 675 goto disable_pm_runtime; 676 } 677 678 drm_panel_add(&panel->base); 679 680 return 0; 681 682 disable_pm_runtime: 683 pm_runtime_dont_use_autosuspend(dev); 684 pm_runtime_disable(dev); 685 free_ddc: 686 if (panel->ddc) 687 put_device(&panel->ddc->dev); 688 689 return err; 690 } 691 692 static void panel_simple_remove(struct device *dev) 693 { 694 struct panel_simple *panel = dev_get_drvdata(dev); 695 696 drm_panel_remove(&panel->base); 697 drm_panel_disable(&panel->base); 698 drm_panel_unprepare(&panel->base); 699 700 pm_runtime_dont_use_autosuspend(dev); 701 pm_runtime_disable(dev); 702 if (panel->ddc) 703 put_device(&panel->ddc->dev); 704 } 705 706 static void panel_simple_shutdown(struct device *dev) 707 { 708 struct panel_simple *panel = dev_get_drvdata(dev); 709 710 drm_panel_disable(&panel->base); 711 drm_panel_unprepare(&panel->base); 712 } 713 714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 715 .clock = 71100, 716 .hdisplay = 1280, 717 .hsync_start = 1280 + 40, 718 .hsync_end = 1280 + 40 + 80, 719 .htotal = 1280 + 40 + 80 + 40, 720 .vdisplay = 800, 721 .vsync_start = 800 + 3, 722 .vsync_end = 800 + 3 + 10, 723 .vtotal = 800 + 3 + 10 + 10, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 728 .modes = &ire_am_1280800n3tzqw_t00h_mode, 729 .num_modes = 1, 730 .bpc = 8, 731 .size = { 732 .width = 217, 733 .height = 136, 734 }, 735 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 738 }; 739 740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 741 .clock = 9000, 742 .hdisplay = 480, 743 .hsync_start = 480 + 2, 744 .hsync_end = 480 + 2 + 41, 745 .htotal = 480 + 2 + 41 + 2, 746 .vdisplay = 272, 747 .vsync_start = 272 + 2, 748 .vsync_end = 272 + 2 + 10, 749 .vtotal = 272 + 2 + 10 + 2, 750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 751 }; 752 753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 754 .modes = &ire_am_480272h3tmqw_t01h_mode, 755 .num_modes = 1, 756 .bpc = 8, 757 .size = { 758 .width = 99, 759 .height = 58, 760 }, 761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 762 }; 763 764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 765 .clock = 33333, 766 .hdisplay = 800, 767 .hsync_start = 800 + 0, 768 .hsync_end = 800 + 0 + 255, 769 .htotal = 800 + 0 + 255 + 0, 770 .vdisplay = 480, 771 .vsync_start = 480 + 2, 772 .vsync_end = 480 + 2 + 45, 773 .vtotal = 480 + 2 + 45 + 0, 774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 775 }; 776 777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 778 .pixelclock = { 29930000, 33260000, 36590000 }, 779 .hactive = { 800, 800, 800 }, 780 .hfront_porch = { 1, 40, 168 }, 781 .hback_porch = { 88, 88, 88 }, 782 .hsync_len = { 1, 128, 128 }, 783 .vactive = { 480, 480, 480 }, 784 .vfront_porch = { 1, 35, 37 }, 785 .vback_porch = { 8, 8, 8 }, 786 .vsync_len = { 1, 2, 2 }, 787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 789 DISPLAY_FLAGS_SYNC_POSEDGE, 790 }; 791 792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 793 .timings = &ire_am_800480l1tmqw_t00h_timing, 794 .num_timings = 1, 795 .bpc = 8, 796 .size = { 797 .width = 111, 798 .height = 67, 799 }, 800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 804 .connector_type = DRM_MODE_CONNECTOR_DPI, 805 }; 806 807 static const struct panel_desc ampire_am800480r3tmqwa1h = { 808 .modes = &ire_am800480r3tmqwa1h_mode, 809 .num_modes = 1, 810 .bpc = 6, 811 .size = { 812 .width = 152, 813 .height = 91, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 }; 817 818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 819 .pixelclock = { 34500000, 39600000, 50400000 }, 820 .hactive = { 800, 800, 800 }, 821 .hfront_porch = { 12, 112, 312 }, 822 .hback_porch = { 87, 87, 48 }, 823 .hsync_len = { 1, 1, 40 }, 824 .vactive = { 600, 600, 600 }, 825 .vfront_porch = { 1, 21, 61 }, 826 .vback_porch = { 38, 38, 19 }, 827 .vsync_len = { 1, 1, 20 }, 828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 830 DISPLAY_FLAGS_SYNC_POSEDGE, 831 }; 832 833 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 834 .timings = &ire_am800600p5tmqw_tb8h_timing, 835 .num_timings = 1, 836 .bpc = 6, 837 .size = { 838 .width = 162, 839 .height = 122, 840 }, 841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 845 .connector_type = DRM_MODE_CONNECTOR_DPI, 846 }; 847 848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 849 .pixelclock = { 26400000, 33300000, 46800000 }, 850 .hactive = { 800, 800, 800 }, 851 .hfront_porch = { 16, 210, 354 }, 852 .hback_porch = { 45, 36, 6 }, 853 .hsync_len = { 1, 10, 40 }, 854 .vactive = { 480, 480, 480 }, 855 .vfront_porch = { 7, 22, 147 }, 856 .vback_porch = { 22, 13, 3 }, 857 .vsync_len = { 1, 10, 20 }, 858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 860 }; 861 862 static const struct panel_desc armadeus_st0700_adapt = { 863 .timings = &santek_st0700i5y_rbslw_f_timing, 864 .num_timings = 1, 865 .bpc = 6, 866 .size = { 867 .width = 154, 868 .height = 86, 869 }, 870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 872 }; 873 874 static const struct drm_display_mode auo_b101aw03_mode = { 875 .clock = 51450, 876 .hdisplay = 1024, 877 .hsync_start = 1024 + 156, 878 .hsync_end = 1024 + 156 + 8, 879 .htotal = 1024 + 156 + 8 + 156, 880 .vdisplay = 600, 881 .vsync_start = 600 + 16, 882 .vsync_end = 600 + 16 + 6, 883 .vtotal = 600 + 16 + 6 + 16, 884 }; 885 886 static const struct panel_desc auo_b101aw03 = { 887 .modes = &auo_b101aw03_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897 }; 898 899 static const struct drm_display_mode auo_b101xtn01_mode = { 900 .clock = 72000, 901 .hdisplay = 1366, 902 .hsync_start = 1366 + 20, 903 .hsync_end = 1366 + 20 + 70, 904 .htotal = 1366 + 20 + 70, 905 .vdisplay = 768, 906 .vsync_start = 768 + 14, 907 .vsync_end = 768 + 14 + 42, 908 .vtotal = 768 + 14 + 42, 909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 910 }; 911 912 static const struct panel_desc auo_b101xtn01 = { 913 .modes = &auo_b101xtn01_mode, 914 .num_modes = 1, 915 .bpc = 6, 916 .size = { 917 .width = 223, 918 .height = 125, 919 }, 920 }; 921 922 static const struct drm_display_mode auo_b116xw03_mode = { 923 .clock = 70589, 924 .hdisplay = 1366, 925 .hsync_start = 1366 + 40, 926 .hsync_end = 1366 + 40 + 40, 927 .htotal = 1366 + 40 + 40 + 32, 928 .vdisplay = 768, 929 .vsync_start = 768 + 10, 930 .vsync_end = 768 + 10 + 12, 931 .vtotal = 768 + 10 + 12 + 6, 932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 933 }; 934 935 static const struct panel_desc auo_b116xw03 = { 936 .modes = &auo_b116xw03_mode, 937 .num_modes = 1, 938 .bpc = 6, 939 .size = { 940 .width = 256, 941 .height = 144, 942 }, 943 .delay = { 944 .prepare = 1, 945 .enable = 200, 946 .disable = 200, 947 .unprepare = 500, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 950 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952 }; 953 954 static const struct display_timing auo_g070vvn01_timings = { 955 .pixelclock = { 33300000, 34209000, 45000000 }, 956 .hactive = { 800, 800, 800 }, 957 .hfront_porch = { 20, 40, 200 }, 958 .hback_porch = { 87, 40, 1 }, 959 .hsync_len = { 1, 48, 87 }, 960 .vactive = { 480, 480, 480 }, 961 .vfront_porch = { 5, 13, 200 }, 962 .vback_porch = { 31, 31, 29 }, 963 .vsync_len = { 1, 1, 3 }, 964 }; 965 966 static const struct panel_desc auo_g070vvn01 = { 967 .timings = &auo_g070vvn01_timings, 968 .num_timings = 1, 969 .bpc = 8, 970 .size = { 971 .width = 152, 972 .height = 91, 973 }, 974 .delay = { 975 .prepare = 200, 976 .enable = 50, 977 .disable = 50, 978 .unprepare = 1000, 979 }, 980 }; 981 982 static const struct drm_display_mode auo_g101evn010_mode = { 983 .clock = 68930, 984 .hdisplay = 1280, 985 .hsync_start = 1280 + 82, 986 .hsync_end = 1280 + 82 + 2, 987 .htotal = 1280 + 82 + 2 + 84, 988 .vdisplay = 800, 989 .vsync_start = 800 + 8, 990 .vsync_end = 800 + 8 + 2, 991 .vtotal = 800 + 8 + 2 + 6, 992 }; 993 994 static const struct panel_desc auo_g101evn010 = { 995 .modes = &auo_g101evn010_mode, 996 .num_modes = 1, 997 .bpc = 6, 998 .size = { 999 .width = 216, 1000 .height = 135, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1004 }; 1005 1006 static const struct drm_display_mode auo_g104sn02_mode = { 1007 .clock = 40000, 1008 .hdisplay = 800, 1009 .hsync_start = 800 + 40, 1010 .hsync_end = 800 + 40 + 216, 1011 .htotal = 800 + 40 + 216 + 128, 1012 .vdisplay = 600, 1013 .vsync_start = 600 + 10, 1014 .vsync_end = 600 + 10 + 35, 1015 .vtotal = 600 + 10 + 35 + 2, 1016 }; 1017 1018 static const struct panel_desc auo_g104sn02 = { 1019 .modes = &auo_g104sn02_mode, 1020 .num_modes = 1, 1021 .bpc = 8, 1022 .size = { 1023 .width = 211, 1024 .height = 158, 1025 }, 1026 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1027 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1028 }; 1029 1030 static const struct display_timing auo_g121ean01_timing = { 1031 .pixelclock = { 60000000, 74400000, 90000000 }, 1032 .hactive = { 1280, 1280, 1280 }, 1033 .hfront_porch = { 20, 50, 100 }, 1034 .hback_porch = { 20, 50, 100 }, 1035 .hsync_len = { 30, 100, 200 }, 1036 .vactive = { 800, 800, 800 }, 1037 .vfront_porch = { 2, 10, 25 }, 1038 .vback_porch = { 2, 10, 25 }, 1039 .vsync_len = { 4, 18, 50 }, 1040 }; 1041 1042 static const struct panel_desc auo_g121ean01 = { 1043 .timings = &auo_g121ean01_timing, 1044 .num_timings = 1, 1045 .bpc = 8, 1046 .size = { 1047 .width = 261, 1048 .height = 163, 1049 }, 1050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct display_timing auo_g133han01_timings = { 1055 .pixelclock = { 134000000, 141200000, 149000000 }, 1056 .hactive = { 1920, 1920, 1920 }, 1057 .hfront_porch = { 39, 58, 77 }, 1058 .hback_porch = { 59, 88, 117 }, 1059 .hsync_len = { 28, 42, 56 }, 1060 .vactive = { 1080, 1080, 1080 }, 1061 .vfront_porch = { 3, 8, 11 }, 1062 .vback_porch = { 5, 14, 19 }, 1063 .vsync_len = { 4, 14, 19 }, 1064 }; 1065 1066 static const struct panel_desc auo_g133han01 = { 1067 .timings = &auo_g133han01_timings, 1068 .num_timings = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 293, 1072 .height = 165, 1073 }, 1074 .delay = { 1075 .prepare = 200, 1076 .enable = 50, 1077 .disable = 50, 1078 .unprepare = 1000, 1079 }, 1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1082 }; 1083 1084 static const struct drm_display_mode auo_g156xtn01_mode = { 1085 .clock = 76000, 1086 .hdisplay = 1366, 1087 .hsync_start = 1366 + 33, 1088 .hsync_end = 1366 + 33 + 67, 1089 .htotal = 1560, 1090 .vdisplay = 768, 1091 .vsync_start = 768 + 4, 1092 .vsync_end = 768 + 4 + 4, 1093 .vtotal = 806, 1094 }; 1095 1096 static const struct panel_desc auo_g156xtn01 = { 1097 .modes = &auo_g156xtn01_mode, 1098 .num_modes = 1, 1099 .bpc = 8, 1100 .size = { 1101 .width = 344, 1102 .height = 194, 1103 }, 1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1106 }; 1107 1108 static const struct display_timing auo_g185han01_timings = { 1109 .pixelclock = { 120000000, 144000000, 175000000 }, 1110 .hactive = { 1920, 1920, 1920 }, 1111 .hfront_porch = { 36, 120, 148 }, 1112 .hback_porch = { 24, 88, 108 }, 1113 .hsync_len = { 20, 48, 64 }, 1114 .vactive = { 1080, 1080, 1080 }, 1115 .vfront_porch = { 6, 10, 40 }, 1116 .vback_porch = { 2, 5, 20 }, 1117 .vsync_len = { 2, 5, 20 }, 1118 }; 1119 1120 static const struct panel_desc auo_g185han01 = { 1121 .timings = &auo_g185han01_timings, 1122 .num_timings = 1, 1123 .bpc = 8, 1124 .size = { 1125 .width = 409, 1126 .height = 230, 1127 }, 1128 .delay = { 1129 .prepare = 50, 1130 .enable = 200, 1131 .disable = 110, 1132 .unprepare = 1000, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g190ean01_timings = { 1139 .pixelclock = { 90000000, 108000000, 135000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 126, 184, 1266 }, 1142 .hback_porch = { 84, 122, 844 }, 1143 .hsync_len = { 70, 102, 704 }, 1144 .vactive = { 1024, 1024, 1024 }, 1145 .vfront_porch = { 4, 26, 76 }, 1146 .vback_porch = { 2, 8, 25 }, 1147 .vsync_len = { 2, 8, 25 }, 1148 }; 1149 1150 static const struct panel_desc auo_g190ean01 = { 1151 .timings = &auo_g190ean01_timings, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 376, 1156 .height = 301, 1157 }, 1158 .delay = { 1159 .prepare = 50, 1160 .enable = 200, 1161 .disable = 110, 1162 .unprepare = 1000, 1163 }, 1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166 }; 1167 1168 static const struct display_timing auo_p320hvn03_timings = { 1169 .pixelclock = { 106000000, 148500000, 164000000 }, 1170 .hactive = { 1920, 1920, 1920 }, 1171 .hfront_porch = { 25, 50, 130 }, 1172 .hback_porch = { 25, 50, 130 }, 1173 .hsync_len = { 20, 40, 105 }, 1174 .vactive = { 1080, 1080, 1080 }, 1175 .vfront_porch = { 8, 17, 150 }, 1176 .vback_porch = { 8, 17, 150 }, 1177 .vsync_len = { 4, 11, 100 }, 1178 }; 1179 1180 static const struct panel_desc auo_p320hvn03 = { 1181 .timings = &auo_p320hvn03_timings, 1182 .num_timings = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 698, 1186 .height = 393, 1187 }, 1188 .delay = { 1189 .prepare = 1, 1190 .enable = 450, 1191 .unprepare = 500, 1192 }, 1193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1195 }; 1196 1197 static const struct drm_display_mode auo_t215hvn01_mode = { 1198 .clock = 148800, 1199 .hdisplay = 1920, 1200 .hsync_start = 1920 + 88, 1201 .hsync_end = 1920 + 88 + 44, 1202 .htotal = 1920 + 88 + 44 + 148, 1203 .vdisplay = 1080, 1204 .vsync_start = 1080 + 4, 1205 .vsync_end = 1080 + 4 + 5, 1206 .vtotal = 1080 + 4 + 5 + 36, 1207 }; 1208 1209 static const struct panel_desc auo_t215hvn01 = { 1210 .modes = &auo_t215hvn01_mode, 1211 .num_modes = 1, 1212 .bpc = 8, 1213 .size = { 1214 .width = 430, 1215 .height = 270, 1216 }, 1217 .delay = { 1218 .disable = 5, 1219 .unprepare = 1000, 1220 }, 1221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1223 }; 1224 1225 static const struct drm_display_mode avic_tm070ddh03_mode = { 1226 .clock = 51200, 1227 .hdisplay = 1024, 1228 .hsync_start = 1024 + 160, 1229 .hsync_end = 1024 + 160 + 4, 1230 .htotal = 1024 + 160 + 4 + 156, 1231 .vdisplay = 600, 1232 .vsync_start = 600 + 17, 1233 .vsync_end = 600 + 17 + 1, 1234 .vtotal = 600 + 17 + 1 + 17, 1235 }; 1236 1237 static const struct panel_desc avic_tm070ddh03 = { 1238 .modes = &avic_tm070ddh03_mode, 1239 .num_modes = 1, 1240 .bpc = 8, 1241 .size = { 1242 .width = 154, 1243 .height = 90, 1244 }, 1245 .delay = { 1246 .prepare = 20, 1247 .enable = 200, 1248 .disable = 200, 1249 }, 1250 }; 1251 1252 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1253 .clock = 30000, 1254 .hdisplay = 800, 1255 .hsync_start = 800 + 40, 1256 .hsync_end = 800 + 40 + 48, 1257 .htotal = 800 + 40 + 48 + 40, 1258 .vdisplay = 480, 1259 .vsync_start = 480 + 13, 1260 .vsync_end = 480 + 13 + 3, 1261 .vtotal = 480 + 13 + 3 + 29, 1262 }; 1263 1264 static const struct panel_desc bananapi_s070wv20_ct16 = { 1265 .modes = &bananapi_s070wv20_ct16_mode, 1266 .num_modes = 1, 1267 .bpc = 6, 1268 .size = { 1269 .width = 154, 1270 .height = 86, 1271 }, 1272 }; 1273 1274 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1275 .pixelclock = { 69922000, 71000000, 72293000 }, 1276 .hactive = { 1280, 1280, 1280 }, 1277 .hfront_porch = { 48, 48, 48 }, 1278 .hback_porch = { 80, 80, 80 }, 1279 .hsync_len = { 32, 32, 32 }, 1280 .vactive = { 800, 800, 800 }, 1281 .vfront_porch = { 3, 3, 3 }, 1282 .vback_porch = { 14, 14, 14 }, 1283 .vsync_len = { 6, 6, 6 }, 1284 }; 1285 1286 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1287 .timings = &boe_ev121wxm_n10_1850_timing, 1288 .num_timings = 1, 1289 .bpc = 8, 1290 .size = { 1291 .width = 261, 1292 .height = 163, 1293 }, 1294 .delay = { 1295 .prepare = 9, 1296 .enable = 300, 1297 .unprepare = 300, 1298 .disable = 560, 1299 }, 1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1301 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1302 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1303 }; 1304 1305 static const struct drm_display_mode boe_hv070wsa_mode = { 1306 .clock = 42105, 1307 .hdisplay = 1024, 1308 .hsync_start = 1024 + 30, 1309 .hsync_end = 1024 + 30 + 30, 1310 .htotal = 1024 + 30 + 30 + 30, 1311 .vdisplay = 600, 1312 .vsync_start = 600 + 10, 1313 .vsync_end = 600 + 10 + 10, 1314 .vtotal = 600 + 10 + 10 + 10, 1315 }; 1316 1317 static const struct panel_desc boe_hv070wsa = { 1318 .modes = &boe_hv070wsa_mode, 1319 .num_modes = 1, 1320 .bpc = 8, 1321 .size = { 1322 .width = 154, 1323 .height = 90, 1324 }, 1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1326 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1328 }; 1329 1330 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1331 .clock = 9000, 1332 .hdisplay = 480, 1333 .hsync_start = 480 + 5, 1334 .hsync_end = 480 + 5 + 5, 1335 .htotal = 480 + 5 + 5 + 40, 1336 .vdisplay = 272, 1337 .vsync_start = 272 + 8, 1338 .vsync_end = 272 + 8 + 8, 1339 .vtotal = 272 + 8 + 8 + 8, 1340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1341 }; 1342 1343 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1344 .modes = &cdtech_s043wq26h_ct7_mode, 1345 .num_modes = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 95, 1349 .height = 54, 1350 }, 1351 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1352 }; 1353 1354 /* S070PWS19HP-FC21 2017/04/22 */ 1355 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1356 .clock = 51200, 1357 .hdisplay = 1024, 1358 .hsync_start = 1024 + 160, 1359 .hsync_end = 1024 + 160 + 20, 1360 .htotal = 1024 + 160 + 20 + 140, 1361 .vdisplay = 600, 1362 .vsync_start = 600 + 12, 1363 .vsync_end = 600 + 12 + 3, 1364 .vtotal = 600 + 12 + 3 + 20, 1365 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1366 }; 1367 1368 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1369 .modes = &cdtech_s070pws19hp_fc21_mode, 1370 .num_modes = 1, 1371 .bpc = 6, 1372 .size = { 1373 .width = 154, 1374 .height = 86, 1375 }, 1376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1378 .connector_type = DRM_MODE_CONNECTOR_DPI, 1379 }; 1380 1381 /* S070SWV29HG-DC44 2017/09/21 */ 1382 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1383 .clock = 33300, 1384 .hdisplay = 800, 1385 .hsync_start = 800 + 210, 1386 .hsync_end = 800 + 210 + 2, 1387 .htotal = 800 + 210 + 2 + 44, 1388 .vdisplay = 480, 1389 .vsync_start = 480 + 22, 1390 .vsync_end = 480 + 22 + 2, 1391 .vtotal = 480 + 22 + 2 + 21, 1392 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1393 }; 1394 1395 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1396 .modes = &cdtech_s070swv29hg_dc44_mode, 1397 .num_modes = 1, 1398 .bpc = 6, 1399 .size = { 1400 .width = 154, 1401 .height = 86, 1402 }, 1403 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1404 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1405 .connector_type = DRM_MODE_CONNECTOR_DPI, 1406 }; 1407 1408 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1409 .clock = 35000, 1410 .hdisplay = 800, 1411 .hsync_start = 800 + 40, 1412 .hsync_end = 800 + 40 + 40, 1413 .htotal = 800 + 40 + 40 + 48, 1414 .vdisplay = 480, 1415 .vsync_start = 480 + 29, 1416 .vsync_end = 480 + 29 + 13, 1417 .vtotal = 480 + 29 + 13 + 3, 1418 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1419 }; 1420 1421 static const struct panel_desc cdtech_s070wv95_ct16 = { 1422 .modes = &cdtech_s070wv95_ct16_mode, 1423 .num_modes = 1, 1424 .bpc = 8, 1425 .size = { 1426 .width = 154, 1427 .height = 85, 1428 }, 1429 }; 1430 1431 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1432 .pixelclock = { 68900000, 71100000, 73400000 }, 1433 .hactive = { 1280, 1280, 1280 }, 1434 .hfront_porch = { 65, 80, 95 }, 1435 .hback_porch = { 64, 79, 94 }, 1436 .hsync_len = { 1, 1, 1 }, 1437 .vactive = { 800, 800, 800 }, 1438 .vfront_porch = { 7, 11, 14 }, 1439 .vback_porch = { 7, 11, 14 }, 1440 .vsync_len = { 1, 1, 1 }, 1441 .flags = DISPLAY_FLAGS_DE_HIGH, 1442 }; 1443 1444 static const struct panel_desc chefree_ch101olhlwh_002 = { 1445 .timings = &chefree_ch101olhlwh_002_timing, 1446 .num_timings = 1, 1447 .bpc = 8, 1448 .size = { 1449 .width = 217, 1450 .height = 135, 1451 }, 1452 .delay = { 1453 .enable = 200, 1454 .disable = 200, 1455 }, 1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1457 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1458 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1459 }; 1460 1461 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1462 .clock = 66770, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 49, 1465 .hsync_end = 800 + 49 + 33, 1466 .htotal = 800 + 49 + 33 + 17, 1467 .vdisplay = 1280, 1468 .vsync_start = 1280 + 1, 1469 .vsync_end = 1280 + 1 + 7, 1470 .vtotal = 1280 + 1 + 7 + 15, 1471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1472 }; 1473 1474 static const struct panel_desc chunghwa_claa070wp03xg = { 1475 .modes = &chunghwa_claa070wp03xg_mode, 1476 .num_modes = 1, 1477 .bpc = 6, 1478 .size = { 1479 .width = 94, 1480 .height = 150, 1481 }, 1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1485 }; 1486 1487 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1488 .clock = 72070, 1489 .hdisplay = 1366, 1490 .hsync_start = 1366 + 58, 1491 .hsync_end = 1366 + 58 + 58, 1492 .htotal = 1366 + 58 + 58 + 58, 1493 .vdisplay = 768, 1494 .vsync_start = 768 + 4, 1495 .vsync_end = 768 + 4 + 4, 1496 .vtotal = 768 + 4 + 4 + 4, 1497 }; 1498 1499 static const struct panel_desc chunghwa_claa101wa01a = { 1500 .modes = &chunghwa_claa101wa01a_mode, 1501 .num_modes = 1, 1502 .bpc = 6, 1503 .size = { 1504 .width = 220, 1505 .height = 120, 1506 }, 1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510 }; 1511 1512 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1513 .clock = 69300, 1514 .hdisplay = 1366, 1515 .hsync_start = 1366 + 48, 1516 .hsync_end = 1366 + 48 + 32, 1517 .htotal = 1366 + 48 + 32 + 20, 1518 .vdisplay = 768, 1519 .vsync_start = 768 + 16, 1520 .vsync_end = 768 + 16 + 8, 1521 .vtotal = 768 + 16 + 8 + 16, 1522 }; 1523 1524 static const struct panel_desc chunghwa_claa101wb01 = { 1525 .modes = &chunghwa_claa101wb01_mode, 1526 .num_modes = 1, 1527 .bpc = 6, 1528 .size = { 1529 .width = 223, 1530 .height = 125, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535 }; 1536 1537 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1538 .pixelclock = { 5000000, 9000000, 12000000 }, 1539 .hactive = { 480, 480, 480 }, 1540 .hfront_porch = { 12, 12, 12 }, 1541 .hback_porch = { 12, 12, 12 }, 1542 .hsync_len = { 21, 21, 21 }, 1543 .vactive = { 272, 272, 272 }, 1544 .vfront_porch = { 4, 4, 4 }, 1545 .vback_porch = { 4, 4, 4 }, 1546 .vsync_len = { 8, 8, 8 }, 1547 }; 1548 1549 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1550 .timings = &dataimage_fg040346dsswbg04_timing, 1551 .num_timings = 1, 1552 .bpc = 8, 1553 .size = { 1554 .width = 95, 1555 .height = 54, 1556 }, 1557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1559 .connector_type = DRM_MODE_CONNECTOR_DPI, 1560 }; 1561 1562 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1563 .pixelclock = { 68900000, 71110000, 73400000 }, 1564 .hactive = { 1280, 1280, 1280 }, 1565 .vactive = { 800, 800, 800 }, 1566 .hback_porch = { 100, 100, 100 }, 1567 .hfront_porch = { 100, 100, 100 }, 1568 .vback_porch = { 5, 5, 5 }, 1569 .vfront_porch = { 5, 5, 5 }, 1570 .hsync_len = { 24, 24, 24 }, 1571 .vsync_len = { 3, 3, 3 }, 1572 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1573 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1574 }; 1575 1576 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1577 .timings = &dataimage_fg1001l0dsswmg01_timing, 1578 .num_timings = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 217, 1582 .height = 136, 1583 }, 1584 }; 1585 1586 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1587 .clock = 33260, 1588 .hdisplay = 800, 1589 .hsync_start = 800 + 40, 1590 .hsync_end = 800 + 40 + 128, 1591 .htotal = 800 + 40 + 128 + 88, 1592 .vdisplay = 480, 1593 .vsync_start = 480 + 10, 1594 .vsync_end = 480 + 10 + 2, 1595 .vtotal = 480 + 10 + 2 + 33, 1596 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1597 }; 1598 1599 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1600 .modes = &dataimage_scf0700c48ggu18_mode, 1601 .num_modes = 1, 1602 .bpc = 8, 1603 .size = { 1604 .width = 152, 1605 .height = 91, 1606 }, 1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1609 }; 1610 1611 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1612 .pixelclock = { 45000000, 51200000, 57000000 }, 1613 .hactive = { 1024, 1024, 1024 }, 1614 .hfront_porch = { 100, 106, 113 }, 1615 .hback_porch = { 100, 106, 113 }, 1616 .hsync_len = { 100, 108, 114 }, 1617 .vactive = { 600, 600, 600 }, 1618 .vfront_porch = { 8, 11, 15 }, 1619 .vback_porch = { 8, 11, 15 }, 1620 .vsync_len = { 9, 13, 15 }, 1621 .flags = DISPLAY_FLAGS_DE_HIGH, 1622 }; 1623 1624 static const struct panel_desc dlc_dlc0700yzg_1 = { 1625 .timings = &dlc_dlc0700yzg_1_timing, 1626 .num_timings = 1, 1627 .bpc = 6, 1628 .size = { 1629 .width = 154, 1630 .height = 86, 1631 }, 1632 .delay = { 1633 .prepare = 30, 1634 .enable = 200, 1635 .disable = 200, 1636 }, 1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1638 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1639 }; 1640 1641 static const struct display_timing dlc_dlc1010gig_timing = { 1642 .pixelclock = { 68900000, 71100000, 73400000 }, 1643 .hactive = { 1280, 1280, 1280 }, 1644 .hfront_porch = { 43, 53, 63 }, 1645 .hback_porch = { 43, 53, 63 }, 1646 .hsync_len = { 44, 54, 64 }, 1647 .vactive = { 800, 800, 800 }, 1648 .vfront_porch = { 5, 8, 11 }, 1649 .vback_porch = { 5, 8, 11 }, 1650 .vsync_len = { 5, 7, 11 }, 1651 .flags = DISPLAY_FLAGS_DE_HIGH, 1652 }; 1653 1654 static const struct panel_desc dlc_dlc1010gig = { 1655 .timings = &dlc_dlc1010gig_timing, 1656 .num_timings = 1, 1657 .bpc = 8, 1658 .size = { 1659 .width = 216, 1660 .height = 135, 1661 }, 1662 .delay = { 1663 .prepare = 60, 1664 .enable = 150, 1665 .disable = 100, 1666 .unprepare = 60, 1667 }, 1668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1669 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1670 }; 1671 1672 static const struct drm_display_mode edt_et035012dm6_mode = { 1673 .clock = 6500, 1674 .hdisplay = 320, 1675 .hsync_start = 320 + 20, 1676 .hsync_end = 320 + 20 + 30, 1677 .htotal = 320 + 20 + 68, 1678 .vdisplay = 240, 1679 .vsync_start = 240 + 4, 1680 .vsync_end = 240 + 4 + 4, 1681 .vtotal = 240 + 4 + 4 + 14, 1682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1683 }; 1684 1685 static const struct panel_desc edt_et035012dm6 = { 1686 .modes = &edt_et035012dm6_mode, 1687 .num_modes = 1, 1688 .bpc = 8, 1689 .size = { 1690 .width = 70, 1691 .height = 52, 1692 }, 1693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1694 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1695 }; 1696 1697 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1698 .clock = 6520, 1699 .hdisplay = 320, 1700 .hsync_start = 320 + 20, 1701 .hsync_end = 320 + 20 + 68, 1702 .htotal = 320 + 20 + 68, 1703 .vdisplay = 240, 1704 .vsync_start = 240 + 4, 1705 .vsync_end = 240 + 4 + 18, 1706 .vtotal = 240 + 4 + 18, 1707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1708 }; 1709 1710 static const struct panel_desc edt_etm0350g0dh6 = { 1711 .modes = &edt_etm0350g0dh6_mode, 1712 .num_modes = 1, 1713 .bpc = 6, 1714 .size = { 1715 .width = 70, 1716 .height = 53, 1717 }, 1718 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1719 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1720 .connector_type = DRM_MODE_CONNECTOR_DPI, 1721 }; 1722 1723 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1724 .clock = 10870, 1725 .hdisplay = 480, 1726 .hsync_start = 480 + 8, 1727 .hsync_end = 480 + 8 + 4, 1728 .htotal = 480 + 8 + 4 + 41, 1729 1730 /* 1731 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1732 * fb_align 1733 */ 1734 1735 .vdisplay = 288, 1736 .vsync_start = 288 + 2, 1737 .vsync_end = 288 + 2 + 4, 1738 .vtotal = 288 + 2 + 4 + 10, 1739 }; 1740 1741 static const struct panel_desc edt_etm043080dh6gp = { 1742 .modes = &edt_etm043080dh6gp_mode, 1743 .num_modes = 1, 1744 .bpc = 8, 1745 .size = { 1746 .width = 100, 1747 .height = 65, 1748 }, 1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1750 .connector_type = DRM_MODE_CONNECTOR_DPI, 1751 }; 1752 1753 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1754 .clock = 9000, 1755 .hdisplay = 480, 1756 .hsync_start = 480 + 2, 1757 .hsync_end = 480 + 2 + 41, 1758 .htotal = 480 + 2 + 41 + 2, 1759 .vdisplay = 272, 1760 .vsync_start = 272 + 2, 1761 .vsync_end = 272 + 2 + 10, 1762 .vtotal = 272 + 2 + 10 + 2, 1763 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1764 }; 1765 1766 static const struct panel_desc edt_etm0430g0dh6 = { 1767 .modes = &edt_etm0430g0dh6_mode, 1768 .num_modes = 1, 1769 .bpc = 6, 1770 .size = { 1771 .width = 95, 1772 .height = 54, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1776 .connector_type = DRM_MODE_CONNECTOR_DPI, 1777 }; 1778 1779 static const struct drm_display_mode edt_et057090dhu_mode = { 1780 .clock = 25175, 1781 .hdisplay = 640, 1782 .hsync_start = 640 + 16, 1783 .hsync_end = 640 + 16 + 30, 1784 .htotal = 640 + 16 + 30 + 114, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 3, 1788 .vtotal = 480 + 10 + 3 + 32, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790 }; 1791 1792 static const struct panel_desc edt_et057090dhu = { 1793 .modes = &edt_et057090dhu_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 115, 1798 .height = 86, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1806 .clock = 33260, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 40, 1809 .hsync_end = 800 + 40 + 128, 1810 .htotal = 800 + 40 + 128 + 88, 1811 .vdisplay = 480, 1812 .vsync_start = 480 + 10, 1813 .vsync_end = 480 + 10 + 2, 1814 .vtotal = 480 + 10 + 2 + 33, 1815 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1816 }; 1817 1818 static const struct panel_desc edt_etm0700g0dh6 = { 1819 .modes = &edt_etm0700g0dh6_mode, 1820 .num_modes = 1, 1821 .bpc = 6, 1822 .size = { 1823 .width = 152, 1824 .height = 91, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1828 .connector_type = DRM_MODE_CONNECTOR_DPI, 1829 }; 1830 1831 static const struct panel_desc edt_etm0700g0bdh6 = { 1832 .modes = &edt_etm0700g0dh6_mode, 1833 .num_modes = 1, 1834 .bpc = 6, 1835 .size = { 1836 .width = 152, 1837 .height = 91, 1838 }, 1839 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1840 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1841 .connector_type = DRM_MODE_CONNECTOR_DPI, 1842 }; 1843 1844 static const struct display_timing edt_etml0700y5dha_timing = { 1845 .pixelclock = { 40800000, 51200000, 67200000 }, 1846 .hactive = { 1024, 1024, 1024 }, 1847 .hfront_porch = { 30, 106, 125 }, 1848 .hback_porch = { 30, 106, 125 }, 1849 .hsync_len = { 30, 108, 126 }, 1850 .vactive = { 600, 600, 600 }, 1851 .vfront_porch = { 3, 12, 67}, 1852 .vback_porch = { 3, 12, 67 }, 1853 .vsync_len = { 4, 11, 66 }, 1854 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1855 DISPLAY_FLAGS_DE_HIGH, 1856 }; 1857 1858 static const struct panel_desc edt_etml0700y5dha = { 1859 .timings = &edt_etml0700y5dha_timing, 1860 .num_timings = 1, 1861 .bpc = 8, 1862 .size = { 1863 .width = 155, 1864 .height = 86, 1865 }, 1866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1868 }; 1869 1870 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1871 .clock = 25175, 1872 .hdisplay = 640, 1873 .hsync_start = 640, 1874 .hsync_end = 640 + 16, 1875 .htotal = 640 + 16 + 30 + 114, 1876 .vdisplay = 480, 1877 .vsync_start = 480 + 10, 1878 .vsync_end = 480 + 10 + 3, 1879 .vtotal = 480 + 10 + 3 + 35, 1880 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1881 }; 1882 1883 static const struct panel_desc edt_etmv570g2dhu = { 1884 .modes = &edt_etmv570g2dhu_mode, 1885 .num_modes = 1, 1886 .bpc = 6, 1887 .size = { 1888 .width = 115, 1889 .height = 86, 1890 }, 1891 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1892 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1893 .connector_type = DRM_MODE_CONNECTOR_DPI, 1894 }; 1895 1896 static const struct display_timing eink_vb3300_kca_timing = { 1897 .pixelclock = { 40000000, 40000000, 40000000 }, 1898 .hactive = { 334, 334, 334 }, 1899 .hfront_porch = { 1, 1, 1 }, 1900 .hback_porch = { 1, 1, 1 }, 1901 .hsync_len = { 1, 1, 1 }, 1902 .vactive = { 1405, 1405, 1405 }, 1903 .vfront_porch = { 1, 1, 1 }, 1904 .vback_porch = { 1, 1, 1 }, 1905 .vsync_len = { 1, 1, 1 }, 1906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1908 }; 1909 1910 static const struct panel_desc eink_vb3300_kca = { 1911 .timings = &eink_vb3300_kca_timing, 1912 .num_timings = 1, 1913 .bpc = 6, 1914 .size = { 1915 .width = 157, 1916 .height = 209, 1917 }, 1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1920 .connector_type = DRM_MODE_CONNECTOR_DPI, 1921 }; 1922 1923 static const struct display_timing evervision_vgg804821_timing = { 1924 .pixelclock = { 27600000, 33300000, 50000000 }, 1925 .hactive = { 800, 800, 800 }, 1926 .hfront_porch = { 40, 66, 70 }, 1927 .hback_porch = { 40, 67, 70 }, 1928 .hsync_len = { 40, 67, 70 }, 1929 .vactive = { 480, 480, 480 }, 1930 .vfront_porch = { 6, 10, 10 }, 1931 .vback_porch = { 7, 11, 11 }, 1932 .vsync_len = { 7, 11, 11 }, 1933 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1935 DISPLAY_FLAGS_SYNC_NEGEDGE, 1936 }; 1937 1938 static const struct panel_desc evervision_vgg804821 = { 1939 .timings = &evervision_vgg804821_timing, 1940 .num_timings = 1, 1941 .bpc = 8, 1942 .size = { 1943 .width = 108, 1944 .height = 64, 1945 }, 1946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1948 }; 1949 1950 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1951 .clock = 32260, 1952 .hdisplay = 800, 1953 .hsync_start = 800 + 168, 1954 .hsync_end = 800 + 168 + 64, 1955 .htotal = 800 + 168 + 64 + 88, 1956 .vdisplay = 480, 1957 .vsync_start = 480 + 37, 1958 .vsync_end = 480 + 37 + 2, 1959 .vtotal = 480 + 37 + 2 + 8, 1960 }; 1961 1962 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1963 .modes = &foxlink_fl500wvr00_a0t_mode, 1964 .num_modes = 1, 1965 .bpc = 8, 1966 .size = { 1967 .width = 108, 1968 .height = 65, 1969 }, 1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1971 }; 1972 1973 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1974 { /* 60 Hz */ 1975 .clock = 6000, 1976 .hdisplay = 320, 1977 .hsync_start = 320 + 44, 1978 .hsync_end = 320 + 44 + 16, 1979 .htotal = 320 + 44 + 16 + 20, 1980 .vdisplay = 240, 1981 .vsync_start = 240 + 2, 1982 .vsync_end = 240 + 2 + 6, 1983 .vtotal = 240 + 2 + 6 + 2, 1984 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1985 }, 1986 { /* 50 Hz */ 1987 .clock = 5400, 1988 .hdisplay = 320, 1989 .hsync_start = 320 + 56, 1990 .hsync_end = 320 + 56 + 16, 1991 .htotal = 320 + 56 + 16 + 40, 1992 .vdisplay = 240, 1993 .vsync_start = 240 + 2, 1994 .vsync_end = 240 + 2 + 6, 1995 .vtotal = 240 + 2 + 6 + 2, 1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1997 }, 1998 }; 1999 2000 static const struct panel_desc frida_frd350h54004 = { 2001 .modes = frida_frd350h54004_modes, 2002 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2003 .bpc = 8, 2004 .size = { 2005 .width = 77, 2006 .height = 64, 2007 }, 2008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2010 .connector_type = DRM_MODE_CONNECTOR_DPI, 2011 }; 2012 2013 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2014 .clock = 67185, 2015 .hdisplay = 800, 2016 .hsync_start = 800 + 20, 2017 .hsync_end = 800 + 20 + 24, 2018 .htotal = 800 + 20 + 24 + 20, 2019 .vdisplay = 1280, 2020 .vsync_start = 1280 + 4, 2021 .vsync_end = 1280 + 4 + 8, 2022 .vtotal = 1280 + 4 + 8 + 4, 2023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2024 }; 2025 2026 static const struct panel_desc friendlyarm_hd702e = { 2027 .modes = &friendlyarm_hd702e_mode, 2028 .num_modes = 1, 2029 .size = { 2030 .width = 94, 2031 .height = 151, 2032 }, 2033 }; 2034 2035 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2036 .clock = 9000, 2037 .hdisplay = 480, 2038 .hsync_start = 480 + 5, 2039 .hsync_end = 480 + 5 + 1, 2040 .htotal = 480 + 5 + 1 + 40, 2041 .vdisplay = 272, 2042 .vsync_start = 272 + 8, 2043 .vsync_end = 272 + 8 + 1, 2044 .vtotal = 272 + 8 + 1 + 8, 2045 }; 2046 2047 static const struct panel_desc giantplus_gpg482739qs5 = { 2048 .modes = &giantplus_gpg482739qs5_mode, 2049 .num_modes = 1, 2050 .bpc = 8, 2051 .size = { 2052 .width = 95, 2053 .height = 54, 2054 }, 2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2056 }; 2057 2058 static const struct display_timing giantplus_gpm940b0_timing = { 2059 .pixelclock = { 13500000, 27000000, 27500000 }, 2060 .hactive = { 320, 320, 320 }, 2061 .hfront_porch = { 14, 686, 718 }, 2062 .hback_porch = { 50, 70, 255 }, 2063 .hsync_len = { 1, 1, 1 }, 2064 .vactive = { 240, 240, 240 }, 2065 .vfront_porch = { 1, 1, 179 }, 2066 .vback_porch = { 1, 21, 31 }, 2067 .vsync_len = { 1, 1, 6 }, 2068 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2069 }; 2070 2071 static const struct panel_desc giantplus_gpm940b0 = { 2072 .timings = &giantplus_gpm940b0_timing, 2073 .num_timings = 1, 2074 .bpc = 8, 2075 .size = { 2076 .width = 60, 2077 .height = 45, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2081 }; 2082 2083 static const struct display_timing hannstar_hsd070pww1_timing = { 2084 .pixelclock = { 64300000, 71100000, 82000000 }, 2085 .hactive = { 1280, 1280, 1280 }, 2086 .hfront_porch = { 1, 1, 10 }, 2087 .hback_porch = { 1, 1, 10 }, 2088 /* 2089 * According to the data sheet, the minimum horizontal blanking interval 2090 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2091 * minimum working horizontal blanking interval to be 60 clocks. 2092 */ 2093 .hsync_len = { 58, 158, 661 }, 2094 .vactive = { 800, 800, 800 }, 2095 .vfront_porch = { 1, 1, 10 }, 2096 .vback_porch = { 1, 1, 10 }, 2097 .vsync_len = { 1, 21, 203 }, 2098 .flags = DISPLAY_FLAGS_DE_HIGH, 2099 }; 2100 2101 static const struct panel_desc hannstar_hsd070pww1 = { 2102 .timings = &hannstar_hsd070pww1_timing, 2103 .num_timings = 1, 2104 .bpc = 6, 2105 .size = { 2106 .width = 151, 2107 .height = 94, 2108 }, 2109 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2111 }; 2112 2113 static const struct display_timing hannstar_hsd100pxn1_timing = { 2114 .pixelclock = { 55000000, 65000000, 75000000 }, 2115 .hactive = { 1024, 1024, 1024 }, 2116 .hfront_porch = { 40, 40, 40 }, 2117 .hback_porch = { 220, 220, 220 }, 2118 .hsync_len = { 20, 60, 100 }, 2119 .vactive = { 768, 768, 768 }, 2120 .vfront_porch = { 7, 7, 7 }, 2121 .vback_porch = { 21, 21, 21 }, 2122 .vsync_len = { 10, 10, 10 }, 2123 .flags = DISPLAY_FLAGS_DE_HIGH, 2124 }; 2125 2126 static const struct panel_desc hannstar_hsd100pxn1 = { 2127 .timings = &hannstar_hsd100pxn1_timing, 2128 .num_timings = 1, 2129 .bpc = 6, 2130 .size = { 2131 .width = 203, 2132 .height = 152, 2133 }, 2134 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2136 }; 2137 2138 static const struct display_timing hannstar_hsd101pww2_timing = { 2139 .pixelclock = { 64300000, 71100000, 82000000 }, 2140 .hactive = { 1280, 1280, 1280 }, 2141 .hfront_porch = { 1, 1, 10 }, 2142 .hback_porch = { 1, 1, 10 }, 2143 .hsync_len = { 58, 158, 661 }, 2144 .vactive = { 800, 800, 800 }, 2145 .vfront_porch = { 1, 1, 10 }, 2146 .vback_porch = { 1, 1, 10 }, 2147 .vsync_len = { 1, 21, 203 }, 2148 .flags = DISPLAY_FLAGS_DE_HIGH, 2149 }; 2150 2151 static const struct panel_desc hannstar_hsd101pww2 = { 2152 .timings = &hannstar_hsd101pww2_timing, 2153 .num_timings = 1, 2154 .bpc = 8, 2155 .size = { 2156 .width = 217, 2157 .height = 136, 2158 }, 2159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2161 }; 2162 2163 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2164 .clock = 33333, 2165 .hdisplay = 800, 2166 .hsync_start = 800 + 85, 2167 .hsync_end = 800 + 85 + 86, 2168 .htotal = 800 + 85 + 86 + 85, 2169 .vdisplay = 480, 2170 .vsync_start = 480 + 16, 2171 .vsync_end = 480 + 16 + 13, 2172 .vtotal = 480 + 16 + 13 + 16, 2173 }; 2174 2175 static const struct panel_desc hitachi_tx23d38vm0caa = { 2176 .modes = &hitachi_tx23d38vm0caa_mode, 2177 .num_modes = 1, 2178 .bpc = 6, 2179 .size = { 2180 .width = 195, 2181 .height = 117, 2182 }, 2183 .delay = { 2184 .enable = 160, 2185 .disable = 160, 2186 }, 2187 }; 2188 2189 static const struct drm_display_mode innolux_at043tn24_mode = { 2190 .clock = 9000, 2191 .hdisplay = 480, 2192 .hsync_start = 480 + 2, 2193 .hsync_end = 480 + 2 + 41, 2194 .htotal = 480 + 2 + 41 + 2, 2195 .vdisplay = 272, 2196 .vsync_start = 272 + 2, 2197 .vsync_end = 272 + 2 + 10, 2198 .vtotal = 272 + 2 + 10 + 2, 2199 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2200 }; 2201 2202 static const struct panel_desc innolux_at043tn24 = { 2203 .modes = &innolux_at043tn24_mode, 2204 .num_modes = 1, 2205 .bpc = 8, 2206 .size = { 2207 .width = 95, 2208 .height = 54, 2209 }, 2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2211 .connector_type = DRM_MODE_CONNECTOR_DPI, 2212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2213 }; 2214 2215 static const struct drm_display_mode innolux_at070tn92_mode = { 2216 .clock = 33333, 2217 .hdisplay = 800, 2218 .hsync_start = 800 + 210, 2219 .hsync_end = 800 + 210 + 20, 2220 .htotal = 800 + 210 + 20 + 46, 2221 .vdisplay = 480, 2222 .vsync_start = 480 + 22, 2223 .vsync_end = 480 + 22 + 10, 2224 .vtotal = 480 + 22 + 23 + 10, 2225 }; 2226 2227 static const struct panel_desc innolux_at070tn92 = { 2228 .modes = &innolux_at070tn92_mode, 2229 .num_modes = 1, 2230 .size = { 2231 .width = 154, 2232 .height = 86, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2235 }; 2236 2237 static const struct display_timing innolux_g070ace_l01_timing = { 2238 .pixelclock = { 25200000, 35000000, 35700000 }, 2239 .hactive = { 800, 800, 800 }, 2240 .hfront_porch = { 30, 32, 87 }, 2241 .hback_porch = { 30, 32, 87 }, 2242 .hsync_len = { 1, 1, 1 }, 2243 .vactive = { 480, 480, 480 }, 2244 .vfront_porch = { 3, 3, 3 }, 2245 .vback_porch = { 13, 13, 13 }, 2246 .vsync_len = { 1, 1, 4 }, 2247 .flags = DISPLAY_FLAGS_DE_HIGH, 2248 }; 2249 2250 static const struct panel_desc innolux_g070ace_l01 = { 2251 .timings = &innolux_g070ace_l01_timing, 2252 .num_timings = 1, 2253 .bpc = 8, 2254 .size = { 2255 .width = 152, 2256 .height = 91, 2257 }, 2258 .delay = { 2259 .prepare = 10, 2260 .enable = 50, 2261 .disable = 50, 2262 .unprepare = 500, 2263 }, 2264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2266 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2267 }; 2268 2269 static const struct display_timing innolux_g070y2_l01_timing = { 2270 .pixelclock = { 28000000, 29500000, 32000000 }, 2271 .hactive = { 800, 800, 800 }, 2272 .hfront_porch = { 61, 91, 141 }, 2273 .hback_porch = { 60, 90, 140 }, 2274 .hsync_len = { 12, 12, 12 }, 2275 .vactive = { 480, 480, 480 }, 2276 .vfront_porch = { 4, 9, 30 }, 2277 .vback_porch = { 4, 8, 28 }, 2278 .vsync_len = { 2, 2, 2 }, 2279 .flags = DISPLAY_FLAGS_DE_HIGH, 2280 }; 2281 2282 static const struct panel_desc innolux_g070y2_l01 = { 2283 .timings = &innolux_g070y2_l01_timing, 2284 .num_timings = 1, 2285 .bpc = 8, 2286 .size = { 2287 .width = 152, 2288 .height = 91, 2289 }, 2290 .delay = { 2291 .prepare = 10, 2292 .enable = 100, 2293 .disable = 100, 2294 .unprepare = 800, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299 }; 2300 2301 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2302 .clock = 33333, 2303 .hdisplay = 800, 2304 .hsync_start = 800 + 210, 2305 .hsync_end = 800 + 210 + 20, 2306 .htotal = 800 + 210 + 20 + 46, 2307 .vdisplay = 480, 2308 .vsync_start = 480 + 22, 2309 .vsync_end = 480 + 22 + 10, 2310 .vtotal = 480 + 22 + 23 + 10, 2311 }; 2312 2313 static const struct panel_desc innolux_g070y2_t02 = { 2314 .modes = &innolux_g070y2_t02_mode, 2315 .num_modes = 1, 2316 .bpc = 8, 2317 .size = { 2318 .width = 152, 2319 .height = 92, 2320 }, 2321 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2322 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2323 .connector_type = DRM_MODE_CONNECTOR_DPI, 2324 }; 2325 2326 static const struct display_timing innolux_g101ice_l01_timing = { 2327 .pixelclock = { 60400000, 71100000, 74700000 }, 2328 .hactive = { 1280, 1280, 1280 }, 2329 .hfront_porch = { 30, 60, 70 }, 2330 .hback_porch = { 30, 60, 70 }, 2331 .hsync_len = { 22, 40, 60 }, 2332 .vactive = { 800, 800, 800 }, 2333 .vfront_porch = { 3, 8, 14 }, 2334 .vback_porch = { 3, 8, 14 }, 2335 .vsync_len = { 4, 7, 12 }, 2336 .flags = DISPLAY_FLAGS_DE_HIGH, 2337 }; 2338 2339 static const struct panel_desc innolux_g101ice_l01 = { 2340 .timings = &innolux_g101ice_l01_timing, 2341 .num_timings = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 217, 2345 .height = 135, 2346 }, 2347 .delay = { 2348 .enable = 200, 2349 .disable = 200, 2350 }, 2351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2352 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2353 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2354 }; 2355 2356 static const struct display_timing innolux_g121i1_l01_timing = { 2357 .pixelclock = { 67450000, 71000000, 74550000 }, 2358 .hactive = { 1280, 1280, 1280 }, 2359 .hfront_porch = { 40, 80, 160 }, 2360 .hback_porch = { 39, 79, 159 }, 2361 .hsync_len = { 1, 1, 1 }, 2362 .vactive = { 800, 800, 800 }, 2363 .vfront_porch = { 5, 11, 100 }, 2364 .vback_porch = { 4, 11, 99 }, 2365 .vsync_len = { 1, 1, 1 }, 2366 }; 2367 2368 static const struct panel_desc innolux_g121i1_l01 = { 2369 .timings = &innolux_g121i1_l01_timing, 2370 .num_timings = 1, 2371 .bpc = 6, 2372 .size = { 2373 .width = 261, 2374 .height = 163, 2375 }, 2376 .delay = { 2377 .enable = 200, 2378 .disable = 20, 2379 }, 2380 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2381 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2382 }; 2383 2384 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2385 .clock = 65000, 2386 .hdisplay = 1024, 2387 .hsync_start = 1024 + 0, 2388 .hsync_end = 1024 + 1, 2389 .htotal = 1024 + 0 + 1 + 320, 2390 .vdisplay = 768, 2391 .vsync_start = 768 + 38, 2392 .vsync_end = 768 + 38 + 1, 2393 .vtotal = 768 + 38 + 1 + 0, 2394 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2395 }; 2396 2397 static const struct panel_desc innolux_g121x1_l03 = { 2398 .modes = &innolux_g121x1_l03_mode, 2399 .num_modes = 1, 2400 .bpc = 6, 2401 .size = { 2402 .width = 246, 2403 .height = 185, 2404 }, 2405 .delay = { 2406 .enable = 200, 2407 .unprepare = 200, 2408 .disable = 400, 2409 }, 2410 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2411 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2413 }; 2414 2415 static const struct display_timing innolux_g156hce_l01_timings = { 2416 .pixelclock = { 120000000, 141860000, 150000000 }, 2417 .hactive = { 1920, 1920, 1920 }, 2418 .hfront_porch = { 80, 90, 100 }, 2419 .hback_porch = { 80, 90, 100 }, 2420 .hsync_len = { 20, 30, 30 }, 2421 .vactive = { 1080, 1080, 1080 }, 2422 .vfront_porch = { 3, 10, 20 }, 2423 .vback_porch = { 3, 10, 20 }, 2424 .vsync_len = { 4, 10, 10 }, 2425 }; 2426 2427 static const struct panel_desc innolux_g156hce_l01 = { 2428 .timings = &innolux_g156hce_l01_timings, 2429 .num_timings = 1, 2430 .bpc = 8, 2431 .size = { 2432 .width = 344, 2433 .height = 194, 2434 }, 2435 .delay = { 2436 .prepare = 1, /* T1+T2 */ 2437 .enable = 450, /* T5 */ 2438 .disable = 200, /* T6 */ 2439 .unprepare = 10, /* T3+T7 */ 2440 }, 2441 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2443 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2444 }; 2445 2446 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2447 .clock = 69300, 2448 .hdisplay = 1366, 2449 .hsync_start = 1366 + 16, 2450 .hsync_end = 1366 + 16 + 34, 2451 .htotal = 1366 + 16 + 34 + 50, 2452 .vdisplay = 768, 2453 .vsync_start = 768 + 2, 2454 .vsync_end = 768 + 2 + 6, 2455 .vtotal = 768 + 2 + 6 + 12, 2456 }; 2457 2458 static const struct panel_desc innolux_n156bge_l21 = { 2459 .modes = &innolux_n156bge_l21_mode, 2460 .num_modes = 1, 2461 .bpc = 6, 2462 .size = { 2463 .width = 344, 2464 .height = 193, 2465 }, 2466 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2467 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2468 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2469 }; 2470 2471 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2472 .clock = 51501, 2473 .hdisplay = 1024, 2474 .hsync_start = 1024 + 128, 2475 .hsync_end = 1024 + 128 + 64, 2476 .htotal = 1024 + 128 + 64 + 128, 2477 .vdisplay = 600, 2478 .vsync_start = 600 + 16, 2479 .vsync_end = 600 + 16 + 4, 2480 .vtotal = 600 + 16 + 4 + 16, 2481 }; 2482 2483 static const struct panel_desc innolux_zj070na_01p = { 2484 .modes = &innolux_zj070na_01p_mode, 2485 .num_modes = 1, 2486 .bpc = 6, 2487 .size = { 2488 .width = 154, 2489 .height = 90, 2490 }, 2491 }; 2492 2493 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2494 .pixelclock = { 5580000, 5850000, 6200000 }, 2495 .hactive = { 320, 320, 320 }, 2496 .hfront_porch = { 30, 30, 30 }, 2497 .hback_porch = { 30, 30, 30 }, 2498 .hsync_len = { 1, 5, 17 }, 2499 .vactive = { 240, 240, 240 }, 2500 .vfront_porch = { 6, 6, 6 }, 2501 .vback_porch = { 5, 5, 5 }, 2502 .vsync_len = { 1, 2, 11 }, 2503 .flags = DISPLAY_FLAGS_DE_HIGH, 2504 }; 2505 2506 static const struct panel_desc koe_tx14d24vm1bpa = { 2507 .timings = &koe_tx14d24vm1bpa_timing, 2508 .num_timings = 1, 2509 .bpc = 6, 2510 .size = { 2511 .width = 115, 2512 .height = 86, 2513 }, 2514 }; 2515 2516 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2517 .pixelclock = { 151820000, 156720000, 159780000 }, 2518 .hactive = { 1920, 1920, 1920 }, 2519 .hfront_porch = { 105, 130, 142 }, 2520 .hback_porch = { 45, 70, 82 }, 2521 .hsync_len = { 30, 30, 30 }, 2522 .vactive = { 1200, 1200, 1200}, 2523 .vfront_porch = { 3, 5, 10 }, 2524 .vback_porch = { 2, 5, 10 }, 2525 .vsync_len = { 5, 5, 5 }, 2526 }; 2527 2528 static const struct panel_desc koe_tx26d202vm0bwa = { 2529 .timings = &koe_tx26d202vm0bwa_timing, 2530 .num_timings = 1, 2531 .bpc = 8, 2532 .size = { 2533 .width = 217, 2534 .height = 136, 2535 }, 2536 .delay = { 2537 .prepare = 1000, 2538 .enable = 1000, 2539 .unprepare = 1000, 2540 .disable = 1000, 2541 }, 2542 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2543 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2544 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2545 }; 2546 2547 static const struct display_timing koe_tx31d200vm0baa_timing = { 2548 .pixelclock = { 39600000, 43200000, 48000000 }, 2549 .hactive = { 1280, 1280, 1280 }, 2550 .hfront_porch = { 16, 36, 56 }, 2551 .hback_porch = { 16, 36, 56 }, 2552 .hsync_len = { 8, 8, 8 }, 2553 .vactive = { 480, 480, 480 }, 2554 .vfront_porch = { 6, 21, 33 }, 2555 .vback_porch = { 6, 21, 33 }, 2556 .vsync_len = { 8, 8, 8 }, 2557 .flags = DISPLAY_FLAGS_DE_HIGH, 2558 }; 2559 2560 static const struct panel_desc koe_tx31d200vm0baa = { 2561 .timings = &koe_tx31d200vm0baa_timing, 2562 .num_timings = 1, 2563 .bpc = 6, 2564 .size = { 2565 .width = 292, 2566 .height = 109, 2567 }, 2568 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2570 }; 2571 2572 static const struct display_timing kyo_tcg121xglp_timing = { 2573 .pixelclock = { 52000000, 65000000, 71000000 }, 2574 .hactive = { 1024, 1024, 1024 }, 2575 .hfront_porch = { 2, 2, 2 }, 2576 .hback_porch = { 2, 2, 2 }, 2577 .hsync_len = { 86, 124, 244 }, 2578 .vactive = { 768, 768, 768 }, 2579 .vfront_porch = { 2, 2, 2 }, 2580 .vback_porch = { 2, 2, 2 }, 2581 .vsync_len = { 6, 34, 73 }, 2582 .flags = DISPLAY_FLAGS_DE_HIGH, 2583 }; 2584 2585 static const struct panel_desc kyo_tcg121xglp = { 2586 .timings = &kyo_tcg121xglp_timing, 2587 .num_timings = 1, 2588 .bpc = 8, 2589 .size = { 2590 .width = 246, 2591 .height = 184, 2592 }, 2593 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2595 }; 2596 2597 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2598 .clock = 7000, 2599 .hdisplay = 320, 2600 .hsync_start = 320 + 20, 2601 .hsync_end = 320 + 20 + 30, 2602 .htotal = 320 + 20 + 30 + 38, 2603 .vdisplay = 240, 2604 .vsync_start = 240 + 4, 2605 .vsync_end = 240 + 4 + 3, 2606 .vtotal = 240 + 4 + 3 + 15, 2607 }; 2608 2609 static const struct panel_desc lemaker_bl035_rgb_002 = { 2610 .modes = &lemaker_bl035_rgb_002_mode, 2611 .num_modes = 1, 2612 .size = { 2613 .width = 70, 2614 .height = 52, 2615 }, 2616 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2617 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2618 }; 2619 2620 static const struct drm_display_mode lg_lb070wv8_mode = { 2621 .clock = 33246, 2622 .hdisplay = 800, 2623 .hsync_start = 800 + 88, 2624 .hsync_end = 800 + 88 + 80, 2625 .htotal = 800 + 88 + 80 + 88, 2626 .vdisplay = 480, 2627 .vsync_start = 480 + 10, 2628 .vsync_end = 480 + 10 + 25, 2629 .vtotal = 480 + 10 + 25 + 10, 2630 }; 2631 2632 static const struct panel_desc lg_lb070wv8 = { 2633 .modes = &lg_lb070wv8_mode, 2634 .num_modes = 1, 2635 .bpc = 8, 2636 .size = { 2637 .width = 151, 2638 .height = 91, 2639 }, 2640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2642 }; 2643 2644 static const struct display_timing logictechno_lt161010_2nh_timing = { 2645 .pixelclock = { 26400000, 33300000, 46800000 }, 2646 .hactive = { 800, 800, 800 }, 2647 .hfront_porch = { 16, 210, 354 }, 2648 .hback_porch = { 46, 46, 46 }, 2649 .hsync_len = { 1, 20, 40 }, 2650 .vactive = { 480, 480, 480 }, 2651 .vfront_porch = { 7, 22, 147 }, 2652 .vback_porch = { 23, 23, 23 }, 2653 .vsync_len = { 1, 10, 20 }, 2654 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2655 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2656 DISPLAY_FLAGS_SYNC_POSEDGE, 2657 }; 2658 2659 static const struct panel_desc logictechno_lt161010_2nh = { 2660 .timings = &logictechno_lt161010_2nh_timing, 2661 .num_timings = 1, 2662 .bpc = 6, 2663 .size = { 2664 .width = 154, 2665 .height = 86, 2666 }, 2667 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2669 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2670 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2671 .connector_type = DRM_MODE_CONNECTOR_DPI, 2672 }; 2673 2674 static const struct display_timing logictechno_lt170410_2whc_timing = { 2675 .pixelclock = { 68900000, 71100000, 73400000 }, 2676 .hactive = { 1280, 1280, 1280 }, 2677 .hfront_porch = { 23, 60, 71 }, 2678 .hback_porch = { 23, 60, 71 }, 2679 .hsync_len = { 15, 40, 47 }, 2680 .vactive = { 800, 800, 800 }, 2681 .vfront_porch = { 5, 7, 10 }, 2682 .vback_porch = { 5, 7, 10 }, 2683 .vsync_len = { 6, 9, 12 }, 2684 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2685 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2686 DISPLAY_FLAGS_SYNC_POSEDGE, 2687 }; 2688 2689 static const struct panel_desc logictechno_lt170410_2whc = { 2690 .timings = &logictechno_lt170410_2whc_timing, 2691 .num_timings = 1, 2692 .bpc = 8, 2693 .size = { 2694 .width = 217, 2695 .height = 136, 2696 }, 2697 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2698 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2699 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2700 }; 2701 2702 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2703 .clock = 33000, 2704 .hdisplay = 800, 2705 .hsync_start = 800 + 112, 2706 .hsync_end = 800 + 112 + 3, 2707 .htotal = 800 + 112 + 3 + 85, 2708 .vdisplay = 480, 2709 .vsync_start = 480 + 38, 2710 .vsync_end = 480 + 38 + 3, 2711 .vtotal = 480 + 38 + 3 + 29, 2712 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2713 }; 2714 2715 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2716 .modes = &logictechno_lttd800480070_l2rt_mode, 2717 .num_modes = 1, 2718 .bpc = 8, 2719 .size = { 2720 .width = 154, 2721 .height = 86, 2722 }, 2723 .delay = { 2724 .prepare = 45, 2725 .enable = 100, 2726 .disable = 100, 2727 .unprepare = 45 2728 }, 2729 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2730 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2731 .connector_type = DRM_MODE_CONNECTOR_DPI, 2732 }; 2733 2734 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2735 .clock = 33000, 2736 .hdisplay = 800, 2737 .hsync_start = 800 + 154, 2738 .hsync_end = 800 + 154 + 3, 2739 .htotal = 800 + 154 + 3 + 43, 2740 .vdisplay = 480, 2741 .vsync_start = 480 + 47, 2742 .vsync_end = 480 + 47 + 3, 2743 .vtotal = 480 + 47 + 3 + 20, 2744 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2745 }; 2746 2747 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2748 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2749 .num_modes = 1, 2750 .bpc = 8, 2751 .size = { 2752 .width = 154, 2753 .height = 86, 2754 }, 2755 .delay = { 2756 .prepare = 45, 2757 .enable = 100, 2758 .disable = 100, 2759 .unprepare = 45 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2762 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2763 .connector_type = DRM_MODE_CONNECTOR_DPI, 2764 }; 2765 2766 static const struct drm_display_mode logicpd_type_28_mode = { 2767 .clock = 9107, 2768 .hdisplay = 480, 2769 .hsync_start = 480 + 3, 2770 .hsync_end = 480 + 3 + 42, 2771 .htotal = 480 + 3 + 42 + 2, 2772 2773 .vdisplay = 272, 2774 .vsync_start = 272 + 2, 2775 .vsync_end = 272 + 2 + 11, 2776 .vtotal = 272 + 2 + 11 + 3, 2777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2778 }; 2779 2780 static const struct panel_desc logicpd_type_28 = { 2781 .modes = &logicpd_type_28_mode, 2782 .num_modes = 1, 2783 .bpc = 8, 2784 .size = { 2785 .width = 105, 2786 .height = 67, 2787 }, 2788 .delay = { 2789 .prepare = 200, 2790 .enable = 200, 2791 .unprepare = 200, 2792 .disable = 200, 2793 }, 2794 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2795 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2796 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2797 .connector_type = DRM_MODE_CONNECTOR_DPI, 2798 }; 2799 2800 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2801 .clock = 30400, 2802 .hdisplay = 800, 2803 .hsync_start = 800 + 0, 2804 .hsync_end = 800 + 1, 2805 .htotal = 800 + 0 + 1 + 160, 2806 .vdisplay = 480, 2807 .vsync_start = 480 + 0, 2808 .vsync_end = 480 + 48 + 1, 2809 .vtotal = 480 + 48 + 1 + 0, 2810 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2811 }; 2812 2813 static const struct panel_desc mitsubishi_aa070mc01 = { 2814 .modes = &mitsubishi_aa070mc01_mode, 2815 .num_modes = 1, 2816 .bpc = 8, 2817 .size = { 2818 .width = 152, 2819 .height = 91, 2820 }, 2821 2822 .delay = { 2823 .enable = 200, 2824 .unprepare = 200, 2825 .disable = 400, 2826 }, 2827 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2828 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2829 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2830 }; 2831 2832 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2833 .pixelclock = { 29000000, 33000000, 38000000 }, 2834 .hactive = { 800, 800, 800 }, 2835 .hfront_porch = { 180, 210, 240 }, 2836 .hback_porch = { 16, 16, 16 }, 2837 .hsync_len = { 30, 30, 30 }, 2838 .vactive = { 480, 480, 480 }, 2839 .vfront_porch = { 12, 22, 32 }, 2840 .vback_porch = { 10, 10, 10 }, 2841 .vsync_len = { 13, 13, 13 }, 2842 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2843 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2844 DISPLAY_FLAGS_SYNC_POSEDGE, 2845 }; 2846 2847 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2848 .timings = &multi_inno_mi0700s4t_6_timing, 2849 .num_timings = 1, 2850 .bpc = 8, 2851 .size = { 2852 .width = 154, 2853 .height = 86, 2854 }, 2855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2856 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2857 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2858 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2859 .connector_type = DRM_MODE_CONNECTOR_DPI, 2860 }; 2861 2862 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2863 .pixelclock = { 32000000, 40000000, 50000000 }, 2864 .hactive = { 800, 800, 800 }, 2865 .hfront_porch = { 16, 210, 354 }, 2866 .hback_porch = { 6, 26, 45 }, 2867 .hsync_len = { 1, 20, 40 }, 2868 .vactive = { 600, 600, 600 }, 2869 .vfront_porch = { 1, 12, 77 }, 2870 .vback_porch = { 3, 13, 22 }, 2871 .vsync_len = { 1, 10, 20 }, 2872 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2873 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2874 DISPLAY_FLAGS_SYNC_POSEDGE, 2875 }; 2876 2877 static const struct panel_desc multi_inno_mi0800ft_9 = { 2878 .timings = &multi_inno_mi0800ft_9_timing, 2879 .num_timings = 1, 2880 .bpc = 8, 2881 .size = { 2882 .width = 162, 2883 .height = 122, 2884 }, 2885 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2886 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2887 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2888 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2889 .connector_type = DRM_MODE_CONNECTOR_DPI, 2890 }; 2891 2892 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2893 .pixelclock = { 68900000, 70000000, 73400000 }, 2894 .hactive = { 1280, 1280, 1280 }, 2895 .hfront_porch = { 30, 60, 71 }, 2896 .hback_porch = { 30, 60, 71 }, 2897 .hsync_len = { 10, 10, 48 }, 2898 .vactive = { 800, 800, 800 }, 2899 .vfront_porch = { 5, 10, 10 }, 2900 .vback_porch = { 5, 10, 10 }, 2901 .vsync_len = { 5, 6, 13 }, 2902 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2903 DISPLAY_FLAGS_DE_HIGH, 2904 }; 2905 2906 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2907 .timings = &multi_inno_mi1010ait_1cp_timing, 2908 .num_timings = 1, 2909 .bpc = 8, 2910 .size = { 2911 .width = 217, 2912 .height = 136, 2913 }, 2914 .delay = { 2915 .enable = 50, 2916 .disable = 50, 2917 }, 2918 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2919 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2920 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2921 }; 2922 2923 static const struct display_timing nec_nl12880bc20_05_timing = { 2924 .pixelclock = { 67000000, 71000000, 75000000 }, 2925 .hactive = { 1280, 1280, 1280 }, 2926 .hfront_porch = { 2, 30, 30 }, 2927 .hback_porch = { 6, 100, 100 }, 2928 .hsync_len = { 2, 30, 30 }, 2929 .vactive = { 800, 800, 800 }, 2930 .vfront_porch = { 5, 5, 5 }, 2931 .vback_porch = { 11, 11, 11 }, 2932 .vsync_len = { 7, 7, 7 }, 2933 }; 2934 2935 static const struct panel_desc nec_nl12880bc20_05 = { 2936 .timings = &nec_nl12880bc20_05_timing, 2937 .num_timings = 1, 2938 .bpc = 8, 2939 .size = { 2940 .width = 261, 2941 .height = 163, 2942 }, 2943 .delay = { 2944 .enable = 50, 2945 .disable = 50, 2946 }, 2947 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2948 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2949 }; 2950 2951 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2952 .clock = 10870, 2953 .hdisplay = 480, 2954 .hsync_start = 480 + 2, 2955 .hsync_end = 480 + 2 + 41, 2956 .htotal = 480 + 2 + 41 + 2, 2957 .vdisplay = 272, 2958 .vsync_start = 272 + 2, 2959 .vsync_end = 272 + 2 + 4, 2960 .vtotal = 272 + 2 + 4 + 2, 2961 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2962 }; 2963 2964 static const struct panel_desc nec_nl4827hc19_05b = { 2965 .modes = &nec_nl4827hc19_05b_mode, 2966 .num_modes = 1, 2967 .bpc = 8, 2968 .size = { 2969 .width = 95, 2970 .height = 54, 2971 }, 2972 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2973 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2974 }; 2975 2976 static const struct drm_display_mode netron_dy_e231732_mode = { 2977 .clock = 66000, 2978 .hdisplay = 1024, 2979 .hsync_start = 1024 + 160, 2980 .hsync_end = 1024 + 160 + 70, 2981 .htotal = 1024 + 160 + 70 + 90, 2982 .vdisplay = 600, 2983 .vsync_start = 600 + 127, 2984 .vsync_end = 600 + 127 + 20, 2985 .vtotal = 600 + 127 + 20 + 3, 2986 }; 2987 2988 static const struct panel_desc netron_dy_e231732 = { 2989 .modes = &netron_dy_e231732_mode, 2990 .num_modes = 1, 2991 .size = { 2992 .width = 154, 2993 .height = 87, 2994 }, 2995 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2996 }; 2997 2998 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2999 .clock = 9000, 3000 .hdisplay = 480, 3001 .hsync_start = 480 + 2, 3002 .hsync_end = 480 + 2 + 41, 3003 .htotal = 480 + 2 + 41 + 2, 3004 .vdisplay = 272, 3005 .vsync_start = 272 + 2, 3006 .vsync_end = 272 + 2 + 10, 3007 .vtotal = 272 + 2 + 10 + 2, 3008 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3009 }; 3010 3011 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3012 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3013 .num_modes = 1, 3014 .bpc = 8, 3015 .size = { 3016 .width = 95, 3017 .height = 54, 3018 }, 3019 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3021 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3022 .connector_type = DRM_MODE_CONNECTOR_DPI, 3023 }; 3024 3025 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3026 .pixelclock = { 130000000, 148350000, 163000000 }, 3027 .hactive = { 1920, 1920, 1920 }, 3028 .hfront_porch = { 80, 100, 100 }, 3029 .hback_porch = { 100, 120, 120 }, 3030 .hsync_len = { 50, 60, 60 }, 3031 .vactive = { 1080, 1080, 1080 }, 3032 .vfront_porch = { 12, 30, 30 }, 3033 .vback_porch = { 4, 10, 10 }, 3034 .vsync_len = { 4, 5, 5 }, 3035 }; 3036 3037 static const struct panel_desc nlt_nl192108ac18_02d = { 3038 .timings = &nlt_nl192108ac18_02d_timing, 3039 .num_timings = 1, 3040 .bpc = 8, 3041 .size = { 3042 .width = 344, 3043 .height = 194, 3044 }, 3045 .delay = { 3046 .unprepare = 500, 3047 }, 3048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3049 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3050 }; 3051 3052 static const struct drm_display_mode nvd_9128_mode = { 3053 .clock = 29500, 3054 .hdisplay = 800, 3055 .hsync_start = 800 + 130, 3056 .hsync_end = 800 + 130 + 98, 3057 .htotal = 800 + 0 + 130 + 98, 3058 .vdisplay = 480, 3059 .vsync_start = 480 + 10, 3060 .vsync_end = 480 + 10 + 50, 3061 .vtotal = 480 + 0 + 10 + 50, 3062 }; 3063 3064 static const struct panel_desc nvd_9128 = { 3065 .modes = &nvd_9128_mode, 3066 .num_modes = 1, 3067 .bpc = 8, 3068 .size = { 3069 .width = 156, 3070 .height = 88, 3071 }, 3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3073 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3074 }; 3075 3076 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3077 .pixelclock = { 30000000, 30000000, 40000000 }, 3078 .hactive = { 800, 800, 800 }, 3079 .hfront_porch = { 40, 40, 40 }, 3080 .hback_porch = { 40, 40, 40 }, 3081 .hsync_len = { 1, 48, 48 }, 3082 .vactive = { 480, 480, 480 }, 3083 .vfront_porch = { 13, 13, 13 }, 3084 .vback_porch = { 29, 29, 29 }, 3085 .vsync_len = { 3, 3, 3 }, 3086 .flags = DISPLAY_FLAGS_DE_HIGH, 3087 }; 3088 3089 static const struct panel_desc okaya_rs800480t_7x0gp = { 3090 .timings = &okaya_rs800480t_7x0gp_timing, 3091 .num_timings = 1, 3092 .bpc = 6, 3093 .size = { 3094 .width = 154, 3095 .height = 87, 3096 }, 3097 .delay = { 3098 .prepare = 41, 3099 .enable = 50, 3100 .unprepare = 41, 3101 .disable = 50, 3102 }, 3103 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3104 }; 3105 3106 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3107 .clock = 9000, 3108 .hdisplay = 480, 3109 .hsync_start = 480 + 5, 3110 .hsync_end = 480 + 5 + 30, 3111 .htotal = 480 + 5 + 30 + 10, 3112 .vdisplay = 272, 3113 .vsync_start = 272 + 8, 3114 .vsync_end = 272 + 8 + 5, 3115 .vtotal = 272 + 8 + 5 + 3, 3116 }; 3117 3118 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3119 .modes = &olimex_lcd_olinuxino_43ts_mode, 3120 .num_modes = 1, 3121 .size = { 3122 .width = 95, 3123 .height = 54, 3124 }, 3125 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3126 }; 3127 3128 /* 3129 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3130 * pixel clocks, but this is the timing that was being used in the Adafruit 3131 * installation instructions. 3132 */ 3133 static const struct drm_display_mode ontat_yx700wv03_mode = { 3134 .clock = 29500, 3135 .hdisplay = 800, 3136 .hsync_start = 824, 3137 .hsync_end = 896, 3138 .htotal = 992, 3139 .vdisplay = 480, 3140 .vsync_start = 483, 3141 .vsync_end = 493, 3142 .vtotal = 500, 3143 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3144 }; 3145 3146 /* 3147 * Specification at: 3148 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3149 */ 3150 static const struct panel_desc ontat_yx700wv03 = { 3151 .modes = &ontat_yx700wv03_mode, 3152 .num_modes = 1, 3153 .bpc = 8, 3154 .size = { 3155 .width = 154, 3156 .height = 83, 3157 }, 3158 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3159 }; 3160 3161 static const struct drm_display_mode ortustech_com37h3m_mode = { 3162 .clock = 22230, 3163 .hdisplay = 480, 3164 .hsync_start = 480 + 40, 3165 .hsync_end = 480 + 40 + 10, 3166 .htotal = 480 + 40 + 10 + 40, 3167 .vdisplay = 640, 3168 .vsync_start = 640 + 4, 3169 .vsync_end = 640 + 4 + 2, 3170 .vtotal = 640 + 4 + 2 + 4, 3171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3172 }; 3173 3174 static const struct panel_desc ortustech_com37h3m = { 3175 .modes = &ortustech_com37h3m_mode, 3176 .num_modes = 1, 3177 .bpc = 8, 3178 .size = { 3179 .width = 56, /* 56.16mm */ 3180 .height = 75, /* 74.88mm */ 3181 }, 3182 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3184 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3185 }; 3186 3187 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3188 .clock = 25000, 3189 .hdisplay = 480, 3190 .hsync_start = 480 + 10, 3191 .hsync_end = 480 + 10 + 10, 3192 .htotal = 480 + 10 + 10 + 15, 3193 .vdisplay = 800, 3194 .vsync_start = 800 + 3, 3195 .vsync_end = 800 + 3 + 3, 3196 .vtotal = 800 + 3 + 3 + 3, 3197 }; 3198 3199 static const struct panel_desc ortustech_com43h4m85ulc = { 3200 .modes = &ortustech_com43h4m85ulc_mode, 3201 .num_modes = 1, 3202 .bpc = 6, 3203 .size = { 3204 .width = 56, 3205 .height = 93, 3206 }, 3207 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3209 .connector_type = DRM_MODE_CONNECTOR_DPI, 3210 }; 3211 3212 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3213 .clock = 33000, 3214 .hdisplay = 800, 3215 .hsync_start = 800 + 210, 3216 .hsync_end = 800 + 210 + 30, 3217 .htotal = 800 + 210 + 30 + 16, 3218 .vdisplay = 480, 3219 .vsync_start = 480 + 22, 3220 .vsync_end = 480 + 22 + 13, 3221 .vtotal = 480 + 22 + 13 + 10, 3222 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3223 }; 3224 3225 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3226 .modes = &osddisplays_osd070t1718_19ts_mode, 3227 .num_modes = 1, 3228 .bpc = 8, 3229 .size = { 3230 .width = 152, 3231 .height = 91, 3232 }, 3233 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3234 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3235 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3236 .connector_type = DRM_MODE_CONNECTOR_DPI, 3237 }; 3238 3239 static const struct drm_display_mode pda_91_00156_a0_mode = { 3240 .clock = 33300, 3241 .hdisplay = 800, 3242 .hsync_start = 800 + 1, 3243 .hsync_end = 800 + 1 + 64, 3244 .htotal = 800 + 1 + 64 + 64, 3245 .vdisplay = 480, 3246 .vsync_start = 480 + 1, 3247 .vsync_end = 480 + 1 + 23, 3248 .vtotal = 480 + 1 + 23 + 22, 3249 }; 3250 3251 static const struct panel_desc pda_91_00156_a0 = { 3252 .modes = &pda_91_00156_a0_mode, 3253 .num_modes = 1, 3254 .size = { 3255 .width = 152, 3256 .height = 91, 3257 }, 3258 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3259 }; 3260 3261 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3262 .clock = 24750, 3263 .hdisplay = 800, 3264 .hsync_start = 800 + 54, 3265 .hsync_end = 800 + 54 + 2, 3266 .htotal = 800 + 54 + 2 + 44, 3267 .vdisplay = 480, 3268 .vsync_start = 480 + 49, 3269 .vsync_end = 480 + 49 + 2, 3270 .vtotal = 480 + 49 + 2 + 22, 3271 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3272 }; 3273 3274 static const struct panel_desc powertip_ph800480t013_idf02 = { 3275 .modes = &powertip_ph800480t013_idf02_mode, 3276 .num_modes = 1, 3277 .bpc = 8, 3278 .size = { 3279 .width = 152, 3280 .height = 91, 3281 }, 3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3283 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3284 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3285 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3286 .connector_type = DRM_MODE_CONNECTOR_DPI, 3287 }; 3288 3289 static const struct drm_display_mode qd43003c0_40_mode = { 3290 .clock = 9000, 3291 .hdisplay = 480, 3292 .hsync_start = 480 + 8, 3293 .hsync_end = 480 + 8 + 4, 3294 .htotal = 480 + 8 + 4 + 39, 3295 .vdisplay = 272, 3296 .vsync_start = 272 + 4, 3297 .vsync_end = 272 + 4 + 10, 3298 .vtotal = 272 + 4 + 10 + 2, 3299 }; 3300 3301 static const struct panel_desc qd43003c0_40 = { 3302 .modes = &qd43003c0_40_mode, 3303 .num_modes = 1, 3304 .bpc = 8, 3305 .size = { 3306 .width = 95, 3307 .height = 53, 3308 }, 3309 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3310 }; 3311 3312 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3313 { /* 60 Hz */ 3314 .clock = 10800, 3315 .hdisplay = 480, 3316 .hsync_start = 480 + 77, 3317 .hsync_end = 480 + 77 + 41, 3318 .htotal = 480 + 77 + 41 + 2, 3319 .vdisplay = 272, 3320 .vsync_start = 272 + 16, 3321 .vsync_end = 272 + 16 + 10, 3322 .vtotal = 272 + 16 + 10 + 2, 3323 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3324 }, 3325 { /* 50 Hz */ 3326 .clock = 10800, 3327 .hdisplay = 480, 3328 .hsync_start = 480 + 17, 3329 .hsync_end = 480 + 17 + 41, 3330 .htotal = 480 + 17 + 41 + 2, 3331 .vdisplay = 272, 3332 .vsync_start = 272 + 116, 3333 .vsync_end = 272 + 116 + 10, 3334 .vtotal = 272 + 116 + 10 + 2, 3335 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3336 }, 3337 }; 3338 3339 static const struct panel_desc qishenglong_gopher2b_lcd = { 3340 .modes = qishenglong_gopher2b_lcd_modes, 3341 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3342 .bpc = 8, 3343 .size = { 3344 .width = 95, 3345 .height = 54, 3346 }, 3347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3348 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3349 .connector_type = DRM_MODE_CONNECTOR_DPI, 3350 }; 3351 3352 static const struct display_timing rocktech_rk043fn48h_timing = { 3353 .pixelclock = { 6000000, 9000000, 12000000 }, 3354 .hactive = { 480, 480, 480 }, 3355 .hback_porch = { 8, 43, 43 }, 3356 .hfront_porch = { 2, 8, 8 }, 3357 .hsync_len = { 1, 1, 1 }, 3358 .vactive = { 272, 272, 272 }, 3359 .vback_porch = { 2, 12, 12 }, 3360 .vfront_porch = { 1, 4, 4 }, 3361 .vsync_len = { 1, 10, 10 }, 3362 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3363 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3364 }; 3365 3366 static const struct panel_desc rocktech_rk043fn48h = { 3367 .timings = &rocktech_rk043fn48h_timing, 3368 .num_timings = 1, 3369 .bpc = 8, 3370 .size = { 3371 .width = 95, 3372 .height = 54, 3373 }, 3374 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3375 .connector_type = DRM_MODE_CONNECTOR_DPI, 3376 }; 3377 3378 static const struct display_timing rocktech_rk070er9427_timing = { 3379 .pixelclock = { 26400000, 33300000, 46800000 }, 3380 .hactive = { 800, 800, 800 }, 3381 .hfront_porch = { 16, 210, 354 }, 3382 .hback_porch = { 46, 46, 46 }, 3383 .hsync_len = { 1, 1, 1 }, 3384 .vactive = { 480, 480, 480 }, 3385 .vfront_porch = { 7, 22, 147 }, 3386 .vback_porch = { 23, 23, 23 }, 3387 .vsync_len = { 1, 1, 1 }, 3388 .flags = DISPLAY_FLAGS_DE_HIGH, 3389 }; 3390 3391 static const struct panel_desc rocktech_rk070er9427 = { 3392 .timings = &rocktech_rk070er9427_timing, 3393 .num_timings = 1, 3394 .bpc = 6, 3395 .size = { 3396 .width = 154, 3397 .height = 86, 3398 }, 3399 .delay = { 3400 .prepare = 41, 3401 .enable = 50, 3402 .unprepare = 41, 3403 .disable = 50, 3404 }, 3405 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3406 }; 3407 3408 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3409 .clock = 71100, 3410 .hdisplay = 1280, 3411 .hsync_start = 1280 + 48, 3412 .hsync_end = 1280 + 48 + 32, 3413 .htotal = 1280 + 48 + 32 + 80, 3414 .vdisplay = 800, 3415 .vsync_start = 800 + 2, 3416 .vsync_end = 800 + 2 + 5, 3417 .vtotal = 800 + 2 + 5 + 16, 3418 }; 3419 3420 static const struct panel_desc rocktech_rk101ii01d_ct = { 3421 .modes = &rocktech_rk101ii01d_ct_mode, 3422 .bpc = 8, 3423 .num_modes = 1, 3424 .size = { 3425 .width = 217, 3426 .height = 136, 3427 }, 3428 .delay = { 3429 .prepare = 50, 3430 .disable = 50, 3431 }, 3432 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3434 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3435 }; 3436 3437 static const struct display_timing samsung_ltl101al01_timing = { 3438 .pixelclock = { 66663000, 66663000, 66663000 }, 3439 .hactive = { 1280, 1280, 1280 }, 3440 .hfront_porch = { 18, 18, 18 }, 3441 .hback_porch = { 36, 36, 36 }, 3442 .hsync_len = { 16, 16, 16 }, 3443 .vactive = { 800, 800, 800 }, 3444 .vfront_porch = { 4, 4, 4 }, 3445 .vback_porch = { 16, 16, 16 }, 3446 .vsync_len = { 3, 3, 3 }, 3447 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3448 }; 3449 3450 static const struct panel_desc samsung_ltl101al01 = { 3451 .timings = &samsung_ltl101al01_timing, 3452 .num_timings = 1, 3453 .bpc = 8, 3454 .size = { 3455 .width = 217, 3456 .height = 135, 3457 }, 3458 .delay = { 3459 .prepare = 40, 3460 .enable = 300, 3461 .disable = 200, 3462 .unprepare = 600, 3463 }, 3464 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3465 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3466 }; 3467 3468 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3469 .clock = 54030, 3470 .hdisplay = 1024, 3471 .hsync_start = 1024 + 24, 3472 .hsync_end = 1024 + 24 + 136, 3473 .htotal = 1024 + 24 + 136 + 160, 3474 .vdisplay = 600, 3475 .vsync_start = 600 + 3, 3476 .vsync_end = 600 + 3 + 6, 3477 .vtotal = 600 + 3 + 6 + 61, 3478 }; 3479 3480 static const struct panel_desc samsung_ltn101nt05 = { 3481 .modes = &samsung_ltn101nt05_mode, 3482 .num_modes = 1, 3483 .bpc = 6, 3484 .size = { 3485 .width = 223, 3486 .height = 125, 3487 }, 3488 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3489 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3490 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3491 }; 3492 3493 static const struct display_timing satoz_sat050at40h12r2_timing = { 3494 .pixelclock = {33300000, 33300000, 50000000}, 3495 .hactive = {800, 800, 800}, 3496 .hfront_porch = {16, 210, 354}, 3497 .hback_porch = {46, 46, 46}, 3498 .hsync_len = {1, 1, 40}, 3499 .vactive = {480, 480, 480}, 3500 .vfront_porch = {7, 22, 147}, 3501 .vback_porch = {23, 23, 23}, 3502 .vsync_len = {1, 1, 20}, 3503 }; 3504 3505 static const struct panel_desc satoz_sat050at40h12r2 = { 3506 .timings = &satoz_sat050at40h12r2_timing, 3507 .num_timings = 1, 3508 .bpc = 8, 3509 .size = { 3510 .width = 108, 3511 .height = 65, 3512 }, 3513 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3514 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3515 }; 3516 3517 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3518 .clock = 33260, 3519 .hdisplay = 800, 3520 .hsync_start = 800 + 64, 3521 .hsync_end = 800 + 64 + 128, 3522 .htotal = 800 + 64 + 128 + 64, 3523 .vdisplay = 480, 3524 .vsync_start = 480 + 8, 3525 .vsync_end = 480 + 8 + 2, 3526 .vtotal = 480 + 8 + 2 + 35, 3527 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3528 }; 3529 3530 static const struct panel_desc sharp_lq070y3dg3b = { 3531 .modes = &sharp_lq070y3dg3b_mode, 3532 .num_modes = 1, 3533 .bpc = 8, 3534 .size = { 3535 .width = 152, /* 152.4mm */ 3536 .height = 91, /* 91.4mm */ 3537 }, 3538 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3539 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3540 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3541 }; 3542 3543 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3544 .clock = 5500, 3545 .hdisplay = 240, 3546 .hsync_start = 240 + 16, 3547 .hsync_end = 240 + 16 + 7, 3548 .htotal = 240 + 16 + 7 + 5, 3549 .vdisplay = 320, 3550 .vsync_start = 320 + 9, 3551 .vsync_end = 320 + 9 + 1, 3552 .vtotal = 320 + 9 + 1 + 7, 3553 }; 3554 3555 static const struct panel_desc sharp_lq035q7db03 = { 3556 .modes = &sharp_lq035q7db03_mode, 3557 .num_modes = 1, 3558 .bpc = 6, 3559 .size = { 3560 .width = 54, 3561 .height = 72, 3562 }, 3563 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3564 }; 3565 3566 static const struct display_timing sharp_lq101k1ly04_timing = { 3567 .pixelclock = { 60000000, 65000000, 80000000 }, 3568 .hactive = { 1280, 1280, 1280 }, 3569 .hfront_porch = { 20, 20, 20 }, 3570 .hback_porch = { 20, 20, 20 }, 3571 .hsync_len = { 10, 10, 10 }, 3572 .vactive = { 800, 800, 800 }, 3573 .vfront_porch = { 4, 4, 4 }, 3574 .vback_porch = { 4, 4, 4 }, 3575 .vsync_len = { 4, 4, 4 }, 3576 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3577 }; 3578 3579 static const struct panel_desc sharp_lq101k1ly04 = { 3580 .timings = &sharp_lq101k1ly04_timing, 3581 .num_timings = 1, 3582 .bpc = 8, 3583 .size = { 3584 .width = 217, 3585 .height = 136, 3586 }, 3587 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3588 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3589 }; 3590 3591 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3592 { /* 50 Hz */ 3593 .clock = 3000, 3594 .hdisplay = 240, 3595 .hsync_start = 240 + 58, 3596 .hsync_end = 240 + 58 + 1, 3597 .htotal = 240 + 58 + 1 + 1, 3598 .vdisplay = 160, 3599 .vsync_start = 160 + 24, 3600 .vsync_end = 160 + 24 + 10, 3601 .vtotal = 160 + 24 + 10 + 6, 3602 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3603 }, 3604 { /* 60 Hz */ 3605 .clock = 3000, 3606 .hdisplay = 240, 3607 .hsync_start = 240 + 8, 3608 .hsync_end = 240 + 8 + 1, 3609 .htotal = 240 + 8 + 1 + 1, 3610 .vdisplay = 160, 3611 .vsync_start = 160 + 24, 3612 .vsync_end = 160 + 24 + 10, 3613 .vtotal = 160 + 24 + 10 + 6, 3614 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3615 }, 3616 }; 3617 3618 static const struct panel_desc sharp_ls020b1dd01d = { 3619 .modes = sharp_ls020b1dd01d_modes, 3620 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3621 .bpc = 6, 3622 .size = { 3623 .width = 42, 3624 .height = 28, 3625 }, 3626 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3627 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3628 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3629 | DRM_BUS_FLAG_SHARP_SIGNALS, 3630 }; 3631 3632 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3633 .clock = 33300, 3634 .hdisplay = 800, 3635 .hsync_start = 800 + 1, 3636 .hsync_end = 800 + 1 + 64, 3637 .htotal = 800 + 1 + 64 + 64, 3638 .vdisplay = 480, 3639 .vsync_start = 480 + 1, 3640 .vsync_end = 480 + 1 + 23, 3641 .vtotal = 480 + 1 + 23 + 22, 3642 }; 3643 3644 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3645 .modes = &shelly_sca07010_bfn_lnn_mode, 3646 .num_modes = 1, 3647 .size = { 3648 .width = 152, 3649 .height = 91, 3650 }, 3651 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3652 }; 3653 3654 static const struct drm_display_mode starry_kr070pe2t_mode = { 3655 .clock = 33000, 3656 .hdisplay = 800, 3657 .hsync_start = 800 + 209, 3658 .hsync_end = 800 + 209 + 1, 3659 .htotal = 800 + 209 + 1 + 45, 3660 .vdisplay = 480, 3661 .vsync_start = 480 + 22, 3662 .vsync_end = 480 + 22 + 1, 3663 .vtotal = 480 + 22 + 1 + 22, 3664 }; 3665 3666 static const struct panel_desc starry_kr070pe2t = { 3667 .modes = &starry_kr070pe2t_mode, 3668 .num_modes = 1, 3669 .bpc = 8, 3670 .size = { 3671 .width = 152, 3672 .height = 86, 3673 }, 3674 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3675 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3676 .connector_type = DRM_MODE_CONNECTOR_DPI, 3677 }; 3678 3679 static const struct display_timing startek_kd070wvfpa_mode = { 3680 .pixelclock = { 25200000, 27200000, 30500000 }, 3681 .hactive = { 800, 800, 800 }, 3682 .hfront_porch = { 19, 44, 115 }, 3683 .hback_porch = { 5, 16, 101 }, 3684 .hsync_len = { 1, 2, 100 }, 3685 .vactive = { 480, 480, 480 }, 3686 .vfront_porch = { 5, 43, 67 }, 3687 .vback_porch = { 5, 5, 67 }, 3688 .vsync_len = { 1, 2, 66 }, 3689 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3690 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3691 DISPLAY_FLAGS_SYNC_POSEDGE, 3692 }; 3693 3694 static const struct panel_desc startek_kd070wvfpa = { 3695 .timings = &startek_kd070wvfpa_mode, 3696 .num_timings = 1, 3697 .bpc = 8, 3698 .size = { 3699 .width = 152, 3700 .height = 91, 3701 }, 3702 .delay = { 3703 .prepare = 20, 3704 .enable = 200, 3705 .disable = 200, 3706 }, 3707 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3708 .connector_type = DRM_MODE_CONNECTOR_DPI, 3709 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3710 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3711 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3712 }; 3713 3714 static const struct display_timing tsd_tst043015cmhx_timing = { 3715 .pixelclock = { 5000000, 9000000, 12000000 }, 3716 .hactive = { 480, 480, 480 }, 3717 .hfront_porch = { 4, 5, 65 }, 3718 .hback_porch = { 36, 40, 255 }, 3719 .hsync_len = { 1, 1, 1 }, 3720 .vactive = { 272, 272, 272 }, 3721 .vfront_porch = { 2, 8, 97 }, 3722 .vback_porch = { 3, 8, 31 }, 3723 .vsync_len = { 1, 1, 1 }, 3724 3725 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3726 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3727 }; 3728 3729 static const struct panel_desc tsd_tst043015cmhx = { 3730 .timings = &tsd_tst043015cmhx_timing, 3731 .num_timings = 1, 3732 .bpc = 8, 3733 .size = { 3734 .width = 105, 3735 .height = 67, 3736 }, 3737 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3738 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3739 }; 3740 3741 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3742 .clock = 30000, 3743 .hdisplay = 800, 3744 .hsync_start = 800 + 39, 3745 .hsync_end = 800 + 39 + 47, 3746 .htotal = 800 + 39 + 47 + 39, 3747 .vdisplay = 480, 3748 .vsync_start = 480 + 13, 3749 .vsync_end = 480 + 13 + 2, 3750 .vtotal = 480 + 13 + 2 + 29, 3751 }; 3752 3753 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3754 .modes = &tfc_s9700rtwv43tr_01b_mode, 3755 .num_modes = 1, 3756 .bpc = 8, 3757 .size = { 3758 .width = 155, 3759 .height = 90, 3760 }, 3761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3762 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3763 }; 3764 3765 static const struct display_timing tianma_tm070jdhg30_timing = { 3766 .pixelclock = { 62600000, 68200000, 78100000 }, 3767 .hactive = { 1280, 1280, 1280 }, 3768 .hfront_porch = { 15, 64, 159 }, 3769 .hback_porch = { 5, 5, 5 }, 3770 .hsync_len = { 1, 1, 256 }, 3771 .vactive = { 800, 800, 800 }, 3772 .vfront_porch = { 3, 40, 99 }, 3773 .vback_porch = { 2, 2, 2 }, 3774 .vsync_len = { 1, 1, 128 }, 3775 .flags = DISPLAY_FLAGS_DE_HIGH, 3776 }; 3777 3778 static const struct panel_desc tianma_tm070jdhg30 = { 3779 .timings = &tianma_tm070jdhg30_timing, 3780 .num_timings = 1, 3781 .bpc = 8, 3782 .size = { 3783 .width = 151, 3784 .height = 95, 3785 }, 3786 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3787 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3789 }; 3790 3791 static const struct panel_desc tianma_tm070jvhg33 = { 3792 .timings = &tianma_tm070jdhg30_timing, 3793 .num_timings = 1, 3794 .bpc = 8, 3795 .size = { 3796 .width = 150, 3797 .height = 94, 3798 }, 3799 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3800 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3802 }; 3803 3804 static const struct display_timing tianma_tm070rvhg71_timing = { 3805 .pixelclock = { 27700000, 29200000, 39600000 }, 3806 .hactive = { 800, 800, 800 }, 3807 .hfront_porch = { 12, 40, 212 }, 3808 .hback_porch = { 88, 88, 88 }, 3809 .hsync_len = { 1, 1, 40 }, 3810 .vactive = { 480, 480, 480 }, 3811 .vfront_porch = { 1, 13, 88 }, 3812 .vback_porch = { 32, 32, 32 }, 3813 .vsync_len = { 1, 1, 3 }, 3814 .flags = DISPLAY_FLAGS_DE_HIGH, 3815 }; 3816 3817 static const struct panel_desc tianma_tm070rvhg71 = { 3818 .timings = &tianma_tm070rvhg71_timing, 3819 .num_timings = 1, 3820 .bpc = 8, 3821 .size = { 3822 .width = 154, 3823 .height = 86, 3824 }, 3825 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3826 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3827 }; 3828 3829 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3830 { 3831 .clock = 10000, 3832 .hdisplay = 320, 3833 .hsync_start = 320 + 50, 3834 .hsync_end = 320 + 50 + 6, 3835 .htotal = 320 + 50 + 6 + 38, 3836 .vdisplay = 240, 3837 .vsync_start = 240 + 3, 3838 .vsync_end = 240 + 3 + 1, 3839 .vtotal = 240 + 3 + 1 + 17, 3840 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3841 }, 3842 }; 3843 3844 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3845 .modes = ti_nspire_cx_lcd_mode, 3846 .num_modes = 1, 3847 .bpc = 8, 3848 .size = { 3849 .width = 65, 3850 .height = 49, 3851 }, 3852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3853 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3854 }; 3855 3856 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3857 { 3858 .clock = 10000, 3859 .hdisplay = 320, 3860 .hsync_start = 320 + 6, 3861 .hsync_end = 320 + 6 + 6, 3862 .htotal = 320 + 6 + 6 + 6, 3863 .vdisplay = 240, 3864 .vsync_start = 240 + 0, 3865 .vsync_end = 240 + 0 + 1, 3866 .vtotal = 240 + 0 + 1 + 0, 3867 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3868 }, 3869 }; 3870 3871 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3872 .modes = ti_nspire_classic_lcd_mode, 3873 .num_modes = 1, 3874 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3875 .bpc = 8, 3876 .size = { 3877 .width = 71, 3878 .height = 53, 3879 }, 3880 /* This is the grayscale bus format */ 3881 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3882 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3883 }; 3884 3885 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3886 .clock = 79500, 3887 .hdisplay = 1280, 3888 .hsync_start = 1280 + 192, 3889 .hsync_end = 1280 + 192 + 128, 3890 .htotal = 1280 + 192 + 128 + 64, 3891 .vdisplay = 768, 3892 .vsync_start = 768 + 20, 3893 .vsync_end = 768 + 20 + 7, 3894 .vtotal = 768 + 20 + 7 + 3, 3895 }; 3896 3897 static const struct panel_desc toshiba_lt089ac29000 = { 3898 .modes = &toshiba_lt089ac29000_mode, 3899 .num_modes = 1, 3900 .size = { 3901 .width = 194, 3902 .height = 116, 3903 }, 3904 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3905 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3906 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3907 }; 3908 3909 static const struct drm_display_mode tpk_f07a_0102_mode = { 3910 .clock = 33260, 3911 .hdisplay = 800, 3912 .hsync_start = 800 + 40, 3913 .hsync_end = 800 + 40 + 128, 3914 .htotal = 800 + 40 + 128 + 88, 3915 .vdisplay = 480, 3916 .vsync_start = 480 + 10, 3917 .vsync_end = 480 + 10 + 2, 3918 .vtotal = 480 + 10 + 2 + 33, 3919 }; 3920 3921 static const struct panel_desc tpk_f07a_0102 = { 3922 .modes = &tpk_f07a_0102_mode, 3923 .num_modes = 1, 3924 .size = { 3925 .width = 152, 3926 .height = 91, 3927 }, 3928 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3929 }; 3930 3931 static const struct drm_display_mode tpk_f10a_0102_mode = { 3932 .clock = 45000, 3933 .hdisplay = 1024, 3934 .hsync_start = 1024 + 176, 3935 .hsync_end = 1024 + 176 + 5, 3936 .htotal = 1024 + 176 + 5 + 88, 3937 .vdisplay = 600, 3938 .vsync_start = 600 + 20, 3939 .vsync_end = 600 + 20 + 5, 3940 .vtotal = 600 + 20 + 5 + 25, 3941 }; 3942 3943 static const struct panel_desc tpk_f10a_0102 = { 3944 .modes = &tpk_f10a_0102_mode, 3945 .num_modes = 1, 3946 .size = { 3947 .width = 223, 3948 .height = 125, 3949 }, 3950 }; 3951 3952 static const struct display_timing urt_umsh_8596md_timing = { 3953 .pixelclock = { 33260000, 33260000, 33260000 }, 3954 .hactive = { 800, 800, 800 }, 3955 .hfront_porch = { 41, 41, 41 }, 3956 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3957 .hsync_len = { 71, 128, 128 }, 3958 .vactive = { 480, 480, 480 }, 3959 .vfront_porch = { 10, 10, 10 }, 3960 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3961 .vsync_len = { 2, 2, 2 }, 3962 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3963 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3964 }; 3965 3966 static const struct panel_desc urt_umsh_8596md_lvds = { 3967 .timings = &urt_umsh_8596md_timing, 3968 .num_timings = 1, 3969 .bpc = 6, 3970 .size = { 3971 .width = 152, 3972 .height = 91, 3973 }, 3974 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3975 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3976 }; 3977 3978 static const struct panel_desc urt_umsh_8596md_parallel = { 3979 .timings = &urt_umsh_8596md_timing, 3980 .num_timings = 1, 3981 .bpc = 6, 3982 .size = { 3983 .width = 152, 3984 .height = 91, 3985 }, 3986 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3987 }; 3988 3989 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3990 .clock = 60000, 3991 .hdisplay = 1024, 3992 .hsync_start = 1024 + 160, 3993 .hsync_end = 1024 + 160 + 100, 3994 .htotal = 1024 + 160 + 100 + 60, 3995 .vdisplay = 600, 3996 .vsync_start = 600 + 12, 3997 .vsync_end = 600 + 12 + 10, 3998 .vtotal = 600 + 12 + 10 + 13, 3999 }; 4000 4001 static const struct panel_desc vivax_tpc9150_panel = { 4002 .modes = &vivax_tpc9150_panel_mode, 4003 .num_modes = 1, 4004 .bpc = 6, 4005 .size = { 4006 .width = 200, 4007 .height = 115, 4008 }, 4009 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4010 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4011 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4012 }; 4013 4014 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4015 .clock = 33333, 4016 .hdisplay = 800, 4017 .hsync_start = 800 + 210, 4018 .hsync_end = 800 + 210 + 20, 4019 .htotal = 800 + 210 + 20 + 46, 4020 .vdisplay = 480, 4021 .vsync_start = 480 + 22, 4022 .vsync_end = 480 + 22 + 10, 4023 .vtotal = 480 + 22 + 10 + 23, 4024 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4025 }; 4026 4027 static const struct panel_desc vl050_8048nt_c01 = { 4028 .modes = &vl050_8048nt_c01_mode, 4029 .num_modes = 1, 4030 .bpc = 8, 4031 .size = { 4032 .width = 120, 4033 .height = 76, 4034 }, 4035 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4036 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4037 }; 4038 4039 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4040 .clock = 6410, 4041 .hdisplay = 320, 4042 .hsync_start = 320 + 20, 4043 .hsync_end = 320 + 20 + 30, 4044 .htotal = 320 + 20 + 30 + 38, 4045 .vdisplay = 240, 4046 .vsync_start = 240 + 4, 4047 .vsync_end = 240 + 4 + 3, 4048 .vtotal = 240 + 4 + 3 + 15, 4049 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4050 }; 4051 4052 static const struct panel_desc winstar_wf35ltiacd = { 4053 .modes = &winstar_wf35ltiacd_mode, 4054 .num_modes = 1, 4055 .bpc = 8, 4056 .size = { 4057 .width = 70, 4058 .height = 53, 4059 }, 4060 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4061 }; 4062 4063 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4064 .clock = 51200, 4065 .hdisplay = 1024, 4066 .hsync_start = 1024 + 100, 4067 .hsync_end = 1024 + 100 + 100, 4068 .htotal = 1024 + 100 + 100 + 120, 4069 .vdisplay = 600, 4070 .vsync_start = 600 + 10, 4071 .vsync_end = 600 + 10 + 10, 4072 .vtotal = 600 + 10 + 10 + 15, 4073 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4074 }; 4075 4076 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4077 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4078 .num_modes = 1, 4079 .bpc = 8, 4080 .size = { 4081 .width = 154, 4082 .height = 90, 4083 }, 4084 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4085 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4086 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4087 }; 4088 4089 static const struct drm_display_mode arm_rtsm_mode[] = { 4090 { 4091 .clock = 65000, 4092 .hdisplay = 1024, 4093 .hsync_start = 1024 + 24, 4094 .hsync_end = 1024 + 24 + 136, 4095 .htotal = 1024 + 24 + 136 + 160, 4096 .vdisplay = 768, 4097 .vsync_start = 768 + 3, 4098 .vsync_end = 768 + 3 + 6, 4099 .vtotal = 768 + 3 + 6 + 29, 4100 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4101 }, 4102 }; 4103 4104 static const struct panel_desc arm_rtsm = { 4105 .modes = arm_rtsm_mode, 4106 .num_modes = 1, 4107 .bpc = 8, 4108 .size = { 4109 .width = 400, 4110 .height = 300, 4111 }, 4112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4113 }; 4114 4115 static const struct of_device_id platform_of_match[] = { 4116 { 4117 .compatible = "ampire,am-1280800n3tzqw-t00h", 4118 .data = &ire_am_1280800n3tzqw_t00h, 4119 }, { 4120 .compatible = "ampire,am-480272h3tmqw-t01h", 4121 .data = &ire_am_480272h3tmqw_t01h, 4122 }, { 4123 .compatible = "ampire,am-800480l1tmqw-t00h", 4124 .data = &ire_am_800480l1tmqw_t00h, 4125 }, { 4126 .compatible = "ampire,am800480r3tmqwa1h", 4127 .data = &ire_am800480r3tmqwa1h, 4128 }, { 4129 .compatible = "ampire,am800600p5tmqw-tb8h", 4130 .data = &ire_am800600p5tmqwtb8h, 4131 }, { 4132 .compatible = "arm,rtsm-display", 4133 .data = &arm_rtsm, 4134 }, { 4135 .compatible = "armadeus,st0700-adapt", 4136 .data = &armadeus_st0700_adapt, 4137 }, { 4138 .compatible = "auo,b101aw03", 4139 .data = &auo_b101aw03, 4140 }, { 4141 .compatible = "auo,b101xtn01", 4142 .data = &auo_b101xtn01, 4143 }, { 4144 .compatible = "auo,b116xw03", 4145 .data = &auo_b116xw03, 4146 }, { 4147 .compatible = "auo,g070vvn01", 4148 .data = &auo_g070vvn01, 4149 }, { 4150 .compatible = "auo,g101evn010", 4151 .data = &auo_g101evn010, 4152 }, { 4153 .compatible = "auo,g104sn02", 4154 .data = &auo_g104sn02, 4155 }, { 4156 .compatible = "auo,g121ean01", 4157 .data = &auo_g121ean01, 4158 }, { 4159 .compatible = "auo,g133han01", 4160 .data = &auo_g133han01, 4161 }, { 4162 .compatible = "auo,g156xtn01", 4163 .data = &auo_g156xtn01, 4164 }, { 4165 .compatible = "auo,g185han01", 4166 .data = &auo_g185han01, 4167 }, { 4168 .compatible = "auo,g190ean01", 4169 .data = &auo_g190ean01, 4170 }, { 4171 .compatible = "auo,p320hvn03", 4172 .data = &auo_p320hvn03, 4173 }, { 4174 .compatible = "auo,t215hvn01", 4175 .data = &auo_t215hvn01, 4176 }, { 4177 .compatible = "avic,tm070ddh03", 4178 .data = &avic_tm070ddh03, 4179 }, { 4180 .compatible = "bananapi,s070wv20-ct16", 4181 .data = &bananapi_s070wv20_ct16, 4182 }, { 4183 .compatible = "boe,ev121wxm-n10-1850", 4184 .data = &boe_ev121wxm_n10_1850, 4185 }, { 4186 .compatible = "boe,hv070wsa-100", 4187 .data = &boe_hv070wsa 4188 }, { 4189 .compatible = "cdtech,s043wq26h-ct7", 4190 .data = &cdtech_s043wq26h_ct7, 4191 }, { 4192 .compatible = "cdtech,s070pws19hp-fc21", 4193 .data = &cdtech_s070pws19hp_fc21, 4194 }, { 4195 .compatible = "cdtech,s070swv29hg-dc44", 4196 .data = &cdtech_s070swv29hg_dc44, 4197 }, { 4198 .compatible = "cdtech,s070wv95-ct16", 4199 .data = &cdtech_s070wv95_ct16, 4200 }, { 4201 .compatible = "chefree,ch101olhlwh-002", 4202 .data = &chefree_ch101olhlwh_002, 4203 }, { 4204 .compatible = "chunghwa,claa070wp03xg", 4205 .data = &chunghwa_claa070wp03xg, 4206 }, { 4207 .compatible = "chunghwa,claa101wa01a", 4208 .data = &chunghwa_claa101wa01a 4209 }, { 4210 .compatible = "chunghwa,claa101wb01", 4211 .data = &chunghwa_claa101wb01 4212 }, { 4213 .compatible = "dataimage,fg040346dsswbg04", 4214 .data = &dataimage_fg040346dsswbg04, 4215 }, { 4216 .compatible = "dataimage,fg1001l0dsswmg01", 4217 .data = &dataimage_fg1001l0dsswmg01, 4218 }, { 4219 .compatible = "dataimage,scf0700c48ggu18", 4220 .data = &dataimage_scf0700c48ggu18, 4221 }, { 4222 .compatible = "dlc,dlc0700yzg-1", 4223 .data = &dlc_dlc0700yzg_1, 4224 }, { 4225 .compatible = "dlc,dlc1010gig", 4226 .data = &dlc_dlc1010gig, 4227 }, { 4228 .compatible = "edt,et035012dm6", 4229 .data = &edt_et035012dm6, 4230 }, { 4231 .compatible = "edt,etm0350g0dh6", 4232 .data = &edt_etm0350g0dh6, 4233 }, { 4234 .compatible = "edt,etm043080dh6gp", 4235 .data = &edt_etm043080dh6gp, 4236 }, { 4237 .compatible = "edt,etm0430g0dh6", 4238 .data = &edt_etm0430g0dh6, 4239 }, { 4240 .compatible = "edt,et057090dhu", 4241 .data = &edt_et057090dhu, 4242 }, { 4243 .compatible = "edt,et070080dh6", 4244 .data = &edt_etm0700g0dh6, 4245 }, { 4246 .compatible = "edt,etm0700g0dh6", 4247 .data = &edt_etm0700g0dh6, 4248 }, { 4249 .compatible = "edt,etm0700g0bdh6", 4250 .data = &edt_etm0700g0bdh6, 4251 }, { 4252 .compatible = "edt,etm0700g0edh6", 4253 .data = &edt_etm0700g0bdh6, 4254 }, { 4255 .compatible = "edt,etml0700y5dha", 4256 .data = &edt_etml0700y5dha, 4257 }, { 4258 .compatible = "edt,etmv570g2dhu", 4259 .data = &edt_etmv570g2dhu, 4260 }, { 4261 .compatible = "eink,vb3300-kca", 4262 .data = &eink_vb3300_kca, 4263 }, { 4264 .compatible = "evervision,vgg804821", 4265 .data = &evervision_vgg804821, 4266 }, { 4267 .compatible = "foxlink,fl500wvr00-a0t", 4268 .data = &foxlink_fl500wvr00_a0t, 4269 }, { 4270 .compatible = "frida,frd350h54004", 4271 .data = &frida_frd350h54004, 4272 }, { 4273 .compatible = "friendlyarm,hd702e", 4274 .data = &friendlyarm_hd702e, 4275 }, { 4276 .compatible = "giantplus,gpg482739qs5", 4277 .data = &giantplus_gpg482739qs5 4278 }, { 4279 .compatible = "giantplus,gpm940b0", 4280 .data = &giantplus_gpm940b0, 4281 }, { 4282 .compatible = "hannstar,hsd070pww1", 4283 .data = &hannstar_hsd070pww1, 4284 }, { 4285 .compatible = "hannstar,hsd100pxn1", 4286 .data = &hannstar_hsd100pxn1, 4287 }, { 4288 .compatible = "hannstar,hsd101pww2", 4289 .data = &hannstar_hsd101pww2, 4290 }, { 4291 .compatible = "hit,tx23d38vm0caa", 4292 .data = &hitachi_tx23d38vm0caa 4293 }, { 4294 .compatible = "innolux,at043tn24", 4295 .data = &innolux_at043tn24, 4296 }, { 4297 .compatible = "innolux,at070tn92", 4298 .data = &innolux_at070tn92, 4299 }, { 4300 .compatible = "innolux,g070ace-l01", 4301 .data = &innolux_g070ace_l01, 4302 }, { 4303 .compatible = "innolux,g070y2-l01", 4304 .data = &innolux_g070y2_l01, 4305 }, { 4306 .compatible = "innolux,g070y2-t02", 4307 .data = &innolux_g070y2_t02, 4308 }, { 4309 .compatible = "innolux,g101ice-l01", 4310 .data = &innolux_g101ice_l01 4311 }, { 4312 .compatible = "innolux,g121i1-l01", 4313 .data = &innolux_g121i1_l01 4314 }, { 4315 .compatible = "innolux,g121x1-l03", 4316 .data = &innolux_g121x1_l03, 4317 }, { 4318 .compatible = "innolux,g156hce-l01", 4319 .data = &innolux_g156hce_l01, 4320 }, { 4321 .compatible = "innolux,n156bge-l21", 4322 .data = &innolux_n156bge_l21, 4323 }, { 4324 .compatible = "innolux,zj070na-01p", 4325 .data = &innolux_zj070na_01p, 4326 }, { 4327 .compatible = "koe,tx14d24vm1bpa", 4328 .data = &koe_tx14d24vm1bpa, 4329 }, { 4330 .compatible = "koe,tx26d202vm0bwa", 4331 .data = &koe_tx26d202vm0bwa, 4332 }, { 4333 .compatible = "koe,tx31d200vm0baa", 4334 .data = &koe_tx31d200vm0baa, 4335 }, { 4336 .compatible = "kyo,tcg121xglp", 4337 .data = &kyo_tcg121xglp, 4338 }, { 4339 .compatible = "lemaker,bl035-rgb-002", 4340 .data = &lemaker_bl035_rgb_002, 4341 }, { 4342 .compatible = "lg,lb070wv8", 4343 .data = &lg_lb070wv8, 4344 }, { 4345 .compatible = "logicpd,type28", 4346 .data = &logicpd_type_28, 4347 }, { 4348 .compatible = "logictechno,lt161010-2nhc", 4349 .data = &logictechno_lt161010_2nh, 4350 }, { 4351 .compatible = "logictechno,lt161010-2nhr", 4352 .data = &logictechno_lt161010_2nh, 4353 }, { 4354 .compatible = "logictechno,lt170410-2whc", 4355 .data = &logictechno_lt170410_2whc, 4356 }, { 4357 .compatible = "logictechno,lttd800480070-l2rt", 4358 .data = &logictechno_lttd800480070_l2rt, 4359 }, { 4360 .compatible = "logictechno,lttd800480070-l6wh-rt", 4361 .data = &logictechno_lttd800480070_l6wh_rt, 4362 }, { 4363 .compatible = "mitsubishi,aa070mc01-ca1", 4364 .data = &mitsubishi_aa070mc01, 4365 }, { 4366 .compatible = "multi-inno,mi0700s4t-6", 4367 .data = &multi_inno_mi0700s4t_6, 4368 }, { 4369 .compatible = "multi-inno,mi0800ft-9", 4370 .data = &multi_inno_mi0800ft_9, 4371 }, { 4372 .compatible = "multi-inno,mi1010ait-1cp", 4373 .data = &multi_inno_mi1010ait_1cp, 4374 }, { 4375 .compatible = "nec,nl12880bc20-05", 4376 .data = &nec_nl12880bc20_05, 4377 }, { 4378 .compatible = "nec,nl4827hc19-05b", 4379 .data = &nec_nl4827hc19_05b, 4380 }, { 4381 .compatible = "netron-dy,e231732", 4382 .data = &netron_dy_e231732, 4383 }, { 4384 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4385 .data = &newhaven_nhd_43_480272ef_atxl, 4386 }, { 4387 .compatible = "nlt,nl192108ac18-02d", 4388 .data = &nlt_nl192108ac18_02d, 4389 }, { 4390 .compatible = "nvd,9128", 4391 .data = &nvd_9128, 4392 }, { 4393 .compatible = "okaya,rs800480t-7x0gp", 4394 .data = &okaya_rs800480t_7x0gp, 4395 }, { 4396 .compatible = "olimex,lcd-olinuxino-43-ts", 4397 .data = &olimex_lcd_olinuxino_43ts, 4398 }, { 4399 .compatible = "ontat,yx700wv03", 4400 .data = &ontat_yx700wv03, 4401 }, { 4402 .compatible = "ortustech,com37h3m05dtc", 4403 .data = &ortustech_com37h3m, 4404 }, { 4405 .compatible = "ortustech,com37h3m99dtc", 4406 .data = &ortustech_com37h3m, 4407 }, { 4408 .compatible = "ortustech,com43h4m85ulc", 4409 .data = &ortustech_com43h4m85ulc, 4410 }, { 4411 .compatible = "osddisplays,osd070t1718-19ts", 4412 .data = &osddisplays_osd070t1718_19ts, 4413 }, { 4414 .compatible = "pda,91-00156-a0", 4415 .data = &pda_91_00156_a0, 4416 }, { 4417 .compatible = "powertip,ph800480t013-idf02", 4418 .data = &powertip_ph800480t013_idf02, 4419 }, { 4420 .compatible = "qiaodian,qd43003c0-40", 4421 .data = &qd43003c0_40, 4422 }, { 4423 .compatible = "qishenglong,gopher2b-lcd", 4424 .data = &qishenglong_gopher2b_lcd, 4425 }, { 4426 .compatible = "rocktech,rk043fn48h", 4427 .data = &rocktech_rk043fn48h, 4428 }, { 4429 .compatible = "rocktech,rk070er9427", 4430 .data = &rocktech_rk070er9427, 4431 }, { 4432 .compatible = "rocktech,rk101ii01d-ct", 4433 .data = &rocktech_rk101ii01d_ct, 4434 }, { 4435 .compatible = "samsung,ltl101al01", 4436 .data = &samsung_ltl101al01, 4437 }, { 4438 .compatible = "samsung,ltn101nt05", 4439 .data = &samsung_ltn101nt05, 4440 }, { 4441 .compatible = "satoz,sat050at40h12r2", 4442 .data = &satoz_sat050at40h12r2, 4443 }, { 4444 .compatible = "sharp,lq035q7db03", 4445 .data = &sharp_lq035q7db03, 4446 }, { 4447 .compatible = "sharp,lq070y3dg3b", 4448 .data = &sharp_lq070y3dg3b, 4449 }, { 4450 .compatible = "sharp,lq101k1ly04", 4451 .data = &sharp_lq101k1ly04, 4452 }, { 4453 .compatible = "sharp,ls020b1dd01d", 4454 .data = &sharp_ls020b1dd01d, 4455 }, { 4456 .compatible = "shelly,sca07010-bfn-lnn", 4457 .data = &shelly_sca07010_bfn_lnn, 4458 }, { 4459 .compatible = "starry,kr070pe2t", 4460 .data = &starry_kr070pe2t, 4461 }, { 4462 .compatible = "startek,kd070wvfpa", 4463 .data = &startek_kd070wvfpa, 4464 }, { 4465 .compatible = "team-source-display,tst043015cmhx", 4466 .data = &tsd_tst043015cmhx, 4467 }, { 4468 .compatible = "tfc,s9700rtwv43tr-01b", 4469 .data = &tfc_s9700rtwv43tr_01b, 4470 }, { 4471 .compatible = "tianma,tm070jdhg30", 4472 .data = &tianma_tm070jdhg30, 4473 }, { 4474 .compatible = "tianma,tm070jvhg33", 4475 .data = &tianma_tm070jvhg33, 4476 }, { 4477 .compatible = "tianma,tm070rvhg71", 4478 .data = &tianma_tm070rvhg71, 4479 }, { 4480 .compatible = "ti,nspire-cx-lcd-panel", 4481 .data = &ti_nspire_cx_lcd_panel, 4482 }, { 4483 .compatible = "ti,nspire-classic-lcd-panel", 4484 .data = &ti_nspire_classic_lcd_panel, 4485 }, { 4486 .compatible = "toshiba,lt089ac29000", 4487 .data = &toshiba_lt089ac29000, 4488 }, { 4489 .compatible = "tpk,f07a-0102", 4490 .data = &tpk_f07a_0102, 4491 }, { 4492 .compatible = "tpk,f10a-0102", 4493 .data = &tpk_f10a_0102, 4494 }, { 4495 .compatible = "urt,umsh-8596md-t", 4496 .data = &urt_umsh_8596md_parallel, 4497 }, { 4498 .compatible = "urt,umsh-8596md-1t", 4499 .data = &urt_umsh_8596md_parallel, 4500 }, { 4501 .compatible = "urt,umsh-8596md-7t", 4502 .data = &urt_umsh_8596md_parallel, 4503 }, { 4504 .compatible = "urt,umsh-8596md-11t", 4505 .data = &urt_umsh_8596md_lvds, 4506 }, { 4507 .compatible = "urt,umsh-8596md-19t", 4508 .data = &urt_umsh_8596md_lvds, 4509 }, { 4510 .compatible = "urt,umsh-8596md-20t", 4511 .data = &urt_umsh_8596md_parallel, 4512 }, { 4513 .compatible = "vivax,tpc9150-panel", 4514 .data = &vivax_tpc9150_panel, 4515 }, { 4516 .compatible = "vxt,vl050-8048nt-c01", 4517 .data = &vl050_8048nt_c01, 4518 }, { 4519 .compatible = "winstar,wf35ltiacd", 4520 .data = &winstar_wf35ltiacd, 4521 }, { 4522 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4523 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4524 }, { 4525 /* Must be the last entry */ 4526 .compatible = "panel-dpi", 4527 .data = &panel_dpi, 4528 }, { 4529 /* sentinel */ 4530 } 4531 }; 4532 MODULE_DEVICE_TABLE(of, platform_of_match); 4533 4534 static int panel_simple_platform_probe(struct platform_device *pdev) 4535 { 4536 const struct panel_desc *desc; 4537 4538 desc = of_device_get_match_data(&pdev->dev); 4539 if (!desc) 4540 return -ENODEV; 4541 4542 return panel_simple_probe(&pdev->dev, desc); 4543 } 4544 4545 static void panel_simple_platform_remove(struct platform_device *pdev) 4546 { 4547 panel_simple_remove(&pdev->dev); 4548 } 4549 4550 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4551 { 4552 panel_simple_shutdown(&pdev->dev); 4553 } 4554 4555 static const struct dev_pm_ops panel_simple_pm_ops = { 4556 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4557 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4558 pm_runtime_force_resume) 4559 }; 4560 4561 static struct platform_driver panel_simple_platform_driver = { 4562 .driver = { 4563 .name = "panel-simple", 4564 .of_match_table = platform_of_match, 4565 .pm = &panel_simple_pm_ops, 4566 }, 4567 .probe = panel_simple_platform_probe, 4568 .remove_new = panel_simple_platform_remove, 4569 .shutdown = panel_simple_platform_shutdown, 4570 }; 4571 4572 struct panel_desc_dsi { 4573 struct panel_desc desc; 4574 4575 unsigned long flags; 4576 enum mipi_dsi_pixel_format format; 4577 unsigned int lanes; 4578 }; 4579 4580 static const struct drm_display_mode auo_b080uan01_mode = { 4581 .clock = 154500, 4582 .hdisplay = 1200, 4583 .hsync_start = 1200 + 62, 4584 .hsync_end = 1200 + 62 + 4, 4585 .htotal = 1200 + 62 + 4 + 62, 4586 .vdisplay = 1920, 4587 .vsync_start = 1920 + 9, 4588 .vsync_end = 1920 + 9 + 2, 4589 .vtotal = 1920 + 9 + 2 + 8, 4590 }; 4591 4592 static const struct panel_desc_dsi auo_b080uan01 = { 4593 .desc = { 4594 .modes = &auo_b080uan01_mode, 4595 .num_modes = 1, 4596 .bpc = 8, 4597 .size = { 4598 .width = 108, 4599 .height = 272, 4600 }, 4601 .connector_type = DRM_MODE_CONNECTOR_DSI, 4602 }, 4603 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4604 .format = MIPI_DSI_FMT_RGB888, 4605 .lanes = 4, 4606 }; 4607 4608 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4609 .clock = 160000, 4610 .hdisplay = 1200, 4611 .hsync_start = 1200 + 120, 4612 .hsync_end = 1200 + 120 + 20, 4613 .htotal = 1200 + 120 + 20 + 21, 4614 .vdisplay = 1920, 4615 .vsync_start = 1920 + 21, 4616 .vsync_end = 1920 + 21 + 3, 4617 .vtotal = 1920 + 21 + 3 + 18, 4618 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4619 }; 4620 4621 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4622 .desc = { 4623 .modes = &boe_tv080wum_nl0_mode, 4624 .num_modes = 1, 4625 .size = { 4626 .width = 107, 4627 .height = 172, 4628 }, 4629 .connector_type = DRM_MODE_CONNECTOR_DSI, 4630 }, 4631 .flags = MIPI_DSI_MODE_VIDEO | 4632 MIPI_DSI_MODE_VIDEO_BURST | 4633 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4634 .format = MIPI_DSI_FMT_RGB888, 4635 .lanes = 4, 4636 }; 4637 4638 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4639 .clock = 71000, 4640 .hdisplay = 800, 4641 .hsync_start = 800 + 32, 4642 .hsync_end = 800 + 32 + 1, 4643 .htotal = 800 + 32 + 1 + 57, 4644 .vdisplay = 1280, 4645 .vsync_start = 1280 + 28, 4646 .vsync_end = 1280 + 28 + 1, 4647 .vtotal = 1280 + 28 + 1 + 14, 4648 }; 4649 4650 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4651 .desc = { 4652 .modes = &lg_ld070wx3_sl01_mode, 4653 .num_modes = 1, 4654 .bpc = 8, 4655 .size = { 4656 .width = 94, 4657 .height = 151, 4658 }, 4659 .connector_type = DRM_MODE_CONNECTOR_DSI, 4660 }, 4661 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4662 .format = MIPI_DSI_FMT_RGB888, 4663 .lanes = 4, 4664 }; 4665 4666 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4667 .clock = 67000, 4668 .hdisplay = 720, 4669 .hsync_start = 720 + 12, 4670 .hsync_end = 720 + 12 + 4, 4671 .htotal = 720 + 12 + 4 + 112, 4672 .vdisplay = 1280, 4673 .vsync_start = 1280 + 8, 4674 .vsync_end = 1280 + 8 + 4, 4675 .vtotal = 1280 + 8 + 4 + 12, 4676 }; 4677 4678 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4679 .desc = { 4680 .modes = &lg_lh500wx1_sd03_mode, 4681 .num_modes = 1, 4682 .bpc = 8, 4683 .size = { 4684 .width = 62, 4685 .height = 110, 4686 }, 4687 .connector_type = DRM_MODE_CONNECTOR_DSI, 4688 }, 4689 .flags = MIPI_DSI_MODE_VIDEO, 4690 .format = MIPI_DSI_FMT_RGB888, 4691 .lanes = 4, 4692 }; 4693 4694 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4695 .clock = 157200, 4696 .hdisplay = 1920, 4697 .hsync_start = 1920 + 154, 4698 .hsync_end = 1920 + 154 + 16, 4699 .htotal = 1920 + 154 + 16 + 32, 4700 .vdisplay = 1200, 4701 .vsync_start = 1200 + 17, 4702 .vsync_end = 1200 + 17 + 2, 4703 .vtotal = 1200 + 17 + 2 + 16, 4704 }; 4705 4706 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4707 .desc = { 4708 .modes = &panasonic_vvx10f004b00_mode, 4709 .num_modes = 1, 4710 .bpc = 8, 4711 .size = { 4712 .width = 217, 4713 .height = 136, 4714 }, 4715 .connector_type = DRM_MODE_CONNECTOR_DSI, 4716 }, 4717 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4718 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4719 .format = MIPI_DSI_FMT_RGB888, 4720 .lanes = 4, 4721 }; 4722 4723 static const struct drm_display_mode lg_acx467akm_7_mode = { 4724 .clock = 150000, 4725 .hdisplay = 1080, 4726 .hsync_start = 1080 + 2, 4727 .hsync_end = 1080 + 2 + 2, 4728 .htotal = 1080 + 2 + 2 + 2, 4729 .vdisplay = 1920, 4730 .vsync_start = 1920 + 2, 4731 .vsync_end = 1920 + 2 + 2, 4732 .vtotal = 1920 + 2 + 2 + 2, 4733 }; 4734 4735 static const struct panel_desc_dsi lg_acx467akm_7 = { 4736 .desc = { 4737 .modes = &lg_acx467akm_7_mode, 4738 .num_modes = 1, 4739 .bpc = 8, 4740 .size = { 4741 .width = 62, 4742 .height = 110, 4743 }, 4744 .connector_type = DRM_MODE_CONNECTOR_DSI, 4745 }, 4746 .flags = 0, 4747 .format = MIPI_DSI_FMT_RGB888, 4748 .lanes = 4, 4749 }; 4750 4751 static const struct drm_display_mode osd101t2045_53ts_mode = { 4752 .clock = 154500, 4753 .hdisplay = 1920, 4754 .hsync_start = 1920 + 112, 4755 .hsync_end = 1920 + 112 + 16, 4756 .htotal = 1920 + 112 + 16 + 32, 4757 .vdisplay = 1200, 4758 .vsync_start = 1200 + 16, 4759 .vsync_end = 1200 + 16 + 2, 4760 .vtotal = 1200 + 16 + 2 + 16, 4761 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4762 }; 4763 4764 static const struct panel_desc_dsi osd101t2045_53ts = { 4765 .desc = { 4766 .modes = &osd101t2045_53ts_mode, 4767 .num_modes = 1, 4768 .bpc = 8, 4769 .size = { 4770 .width = 217, 4771 .height = 136, 4772 }, 4773 .connector_type = DRM_MODE_CONNECTOR_DSI, 4774 }, 4775 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4776 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4777 MIPI_DSI_MODE_NO_EOT_PACKET, 4778 .format = MIPI_DSI_FMT_RGB888, 4779 .lanes = 4, 4780 }; 4781 4782 static const struct of_device_id dsi_of_match[] = { 4783 { 4784 .compatible = "auo,b080uan01", 4785 .data = &auo_b080uan01 4786 }, { 4787 .compatible = "boe,tv080wum-nl0", 4788 .data = &boe_tv080wum_nl0 4789 }, { 4790 .compatible = "lg,ld070wx3-sl01", 4791 .data = &lg_ld070wx3_sl01 4792 }, { 4793 .compatible = "lg,lh500wx1-sd03", 4794 .data = &lg_lh500wx1_sd03 4795 }, { 4796 .compatible = "panasonic,vvx10f004b00", 4797 .data = &panasonic_vvx10f004b00 4798 }, { 4799 .compatible = "lg,acx467akm-7", 4800 .data = &lg_acx467akm_7 4801 }, { 4802 .compatible = "osddisplays,osd101t2045-53ts", 4803 .data = &osd101t2045_53ts 4804 }, { 4805 /* sentinel */ 4806 } 4807 }; 4808 MODULE_DEVICE_TABLE(of, dsi_of_match); 4809 4810 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4811 { 4812 const struct panel_desc_dsi *desc; 4813 int err; 4814 4815 desc = of_device_get_match_data(&dsi->dev); 4816 if (!desc) 4817 return -ENODEV; 4818 4819 err = panel_simple_probe(&dsi->dev, &desc->desc); 4820 if (err < 0) 4821 return err; 4822 4823 dsi->mode_flags = desc->flags; 4824 dsi->format = desc->format; 4825 dsi->lanes = desc->lanes; 4826 4827 err = mipi_dsi_attach(dsi); 4828 if (err) { 4829 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4830 4831 drm_panel_remove(&panel->base); 4832 } 4833 4834 return err; 4835 } 4836 4837 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4838 { 4839 int err; 4840 4841 err = mipi_dsi_detach(dsi); 4842 if (err < 0) 4843 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4844 4845 panel_simple_remove(&dsi->dev); 4846 } 4847 4848 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4849 { 4850 panel_simple_shutdown(&dsi->dev); 4851 } 4852 4853 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4854 .driver = { 4855 .name = "panel-simple-dsi", 4856 .of_match_table = dsi_of_match, 4857 .pm = &panel_simple_pm_ops, 4858 }, 4859 .probe = panel_simple_dsi_probe, 4860 .remove = panel_simple_dsi_remove, 4861 .shutdown = panel_simple_dsi_shutdown, 4862 }; 4863 4864 static int __init panel_simple_init(void) 4865 { 4866 int err; 4867 4868 err = platform_driver_register(&panel_simple_platform_driver); 4869 if (err < 0) 4870 return err; 4871 4872 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4873 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4874 if (err < 0) 4875 goto err_did_platform_register; 4876 } 4877 4878 return 0; 4879 4880 err_did_platform_register: 4881 platform_driver_unregister(&panel_simple_platform_driver); 4882 4883 return err; 4884 } 4885 module_init(panel_simple_init); 4886 4887 static void __exit panel_simple_exit(void) 4888 { 4889 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4890 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4891 4892 platform_driver_unregister(&panel_simple_platform_driver); 4893 } 4894 module_exit(panel_simple_exit); 4895 4896 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4897 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4898 MODULE_LICENSE("GPL and additional rights"); 4899