1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, 167 drm_mode_vrefresh(m)); 168 continue; 169 } 170 171 mode->type |= DRM_MODE_TYPE_DRIVER; 172 173 if (panel->desc->num_modes == 1) 174 mode->type |= DRM_MODE_TYPE_PREFERRED; 175 176 drm_mode_set_name(mode); 177 178 drm_mode_probed_add(connector, mode); 179 num++; 180 } 181 182 return num; 183 } 184 185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 186 struct drm_connector *connector) 187 { 188 struct drm_display_mode *mode; 189 bool has_override = panel->override_mode.type; 190 unsigned int num = 0; 191 192 if (!panel->desc) 193 return 0; 194 195 if (has_override) { 196 mode = drm_mode_duplicate(connector->dev, 197 &panel->override_mode); 198 if (mode) { 199 drm_mode_probed_add(connector, mode); 200 num = 1; 201 } else { 202 dev_err(panel->base.dev, "failed to add override mode\n"); 203 } 204 } 205 206 /* Only add timings if override was not there or failed to validate */ 207 if (num == 0 && panel->desc->num_timings) 208 num = panel_simple_get_timings_modes(panel, connector); 209 210 /* 211 * Only add fixed modes if timings/override added no mode. 212 * 213 * We should only ever have either the display timings specified 214 * or a fixed mode. Anything else is rather bogus. 215 */ 216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 217 if (num == 0) 218 num = panel_simple_get_display_modes(panel, connector); 219 220 connector->display_info.bpc = panel->desc->bpc; 221 connector->display_info.width_mm = panel->desc->size.width; 222 connector->display_info.height_mm = panel->desc->size.height; 223 if (panel->desc->bus_format) 224 drm_display_info_set_bus_formats(&connector->display_info, 225 &panel->desc->bus_format, 1); 226 connector->display_info.bus_flags = panel->desc->bus_flags; 227 228 return num; 229 } 230 231 static int panel_simple_disable(struct drm_panel *panel) 232 { 233 struct panel_simple *p = to_panel_simple(panel); 234 235 if (!p->enabled) 236 return 0; 237 238 if (p->desc->delay.disable) 239 msleep(p->desc->delay.disable); 240 241 p->enabled = false; 242 243 return 0; 244 } 245 246 static int panel_simple_unprepare(struct drm_panel *panel) 247 { 248 struct panel_simple *p = to_panel_simple(panel); 249 250 if (!p->prepared) 251 return 0; 252 253 gpiod_set_value_cansleep(p->enable_gpio, 0); 254 255 regulator_disable(p->supply); 256 257 if (p->desc->delay.unprepare) 258 msleep(p->desc->delay.unprepare); 259 260 p->prepared = false; 261 262 return 0; 263 } 264 265 static int panel_simple_get_hpd_gpio(struct device *dev, 266 struct panel_simple *p, bool from_probe) 267 { 268 int err; 269 270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 271 if (IS_ERR(p->hpd_gpio)) { 272 err = PTR_ERR(p->hpd_gpio); 273 274 /* 275 * If we're called from probe we won't consider '-EPROBE_DEFER' 276 * to be an error--we'll leave the error code in "hpd_gpio". 277 * When we try to use it we'll try again. This allows for 278 * circular dependencies where the component providing the 279 * hpd gpio needs the panel to init before probing. 280 */ 281 if (err != -EPROBE_DEFER || !from_probe) { 282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 283 return err; 284 } 285 } 286 287 return 0; 288 } 289 290 static int panel_simple_prepare(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 unsigned int delay; 294 int err; 295 int hpd_asserted; 296 297 if (p->prepared) 298 return 0; 299 300 err = regulator_enable(p->supply); 301 if (err < 0) { 302 dev_err(panel->dev, "failed to enable supply: %d\n", err); 303 return err; 304 } 305 306 gpiod_set_value_cansleep(p->enable_gpio, 1); 307 308 delay = p->desc->delay.prepare; 309 if (p->no_hpd) 310 delay += p->desc->delay.hpd_absent_delay; 311 if (delay) 312 msleep(delay); 313 314 if (p->hpd_gpio) { 315 if (IS_ERR(p->hpd_gpio)) { 316 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 317 if (err) 318 return err; 319 } 320 321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 322 hpd_asserted, hpd_asserted, 323 1000, 2000000); 324 if (hpd_asserted < 0) 325 err = hpd_asserted; 326 327 if (err) { 328 dev_err(panel->dev, 329 "error waiting for hpd GPIO: %d\n", err); 330 return err; 331 } 332 } 333 334 p->prepared = true; 335 336 return 0; 337 } 338 339 static int panel_simple_enable(struct drm_panel *panel) 340 { 341 struct panel_simple *p = to_panel_simple(panel); 342 343 if (p->enabled) 344 return 0; 345 346 if (p->desc->delay.enable) 347 msleep(p->desc->delay.enable); 348 349 p->enabled = true; 350 351 return 0; 352 } 353 354 static int panel_simple_get_modes(struct drm_panel *panel, 355 struct drm_connector *connector) 356 { 357 struct panel_simple *p = to_panel_simple(panel); 358 int num = 0; 359 360 /* probe EDID if a DDC bus is available */ 361 if (p->ddc) { 362 struct edid *edid = drm_get_edid(connector, p->ddc); 363 364 drm_connector_update_edid_property(connector, edid); 365 if (edid) { 366 num += drm_add_edid_modes(connector, edid); 367 kfree(edid); 368 } 369 } 370 371 /* add hard-coded panel modes */ 372 num += panel_simple_get_non_edid_modes(p, connector); 373 374 return num; 375 } 376 377 static int panel_simple_get_timings(struct drm_panel *panel, 378 unsigned int num_timings, 379 struct display_timing *timings) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 unsigned int i; 383 384 if (p->desc->num_timings < num_timings) 385 num_timings = p->desc->num_timings; 386 387 if (timings) 388 for (i = 0; i < num_timings; i++) 389 timings[i] = p->desc->timings[i]; 390 391 return p->desc->num_timings; 392 } 393 394 static const struct drm_panel_funcs panel_simple_funcs = { 395 .disable = panel_simple_disable, 396 .unprepare = panel_simple_unprepare, 397 .prepare = panel_simple_prepare, 398 .enable = panel_simple_enable, 399 .get_modes = panel_simple_get_modes, 400 .get_timings = panel_simple_get_timings, 401 }; 402 403 static struct panel_desc panel_dpi; 404 405 static int panel_dpi_probe(struct device *dev, 406 struct panel_simple *panel) 407 { 408 struct display_timing *timing; 409 const struct device_node *np; 410 struct panel_desc *desc; 411 unsigned int bus_flags; 412 struct videomode vm; 413 int ret; 414 415 np = dev->of_node; 416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 417 if (!desc) 418 return -ENOMEM; 419 420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 421 if (!timing) 422 return -ENOMEM; 423 424 ret = of_get_display_timing(np, "panel-timing", timing); 425 if (ret < 0) { 426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 427 np); 428 return ret; 429 } 430 431 desc->timings = timing; 432 desc->num_timings = 1; 433 434 of_property_read_u32(np, "width-mm", &desc->size.width); 435 of_property_read_u32(np, "height-mm", &desc->size.height); 436 437 /* Extract bus_flags from display_timing */ 438 bus_flags = 0; 439 vm.flags = timing->flags; 440 drm_bus_flags_from_videomode(&vm, &bus_flags); 441 desc->bus_flags = bus_flags; 442 443 /* We do not know the connector for the DT node, so guess it */ 444 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 445 446 panel->desc = desc; 447 448 return 0; 449 } 450 451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 452 (to_check->field.typ >= bounds->field.min && \ 453 to_check->field.typ <= bounds->field.max) 454 static void panel_simple_parse_panel_timing_node(struct device *dev, 455 struct panel_simple *panel, 456 const struct display_timing *ot) 457 { 458 const struct panel_desc *desc = panel->desc; 459 struct videomode vm; 460 unsigned int i; 461 462 if (WARN_ON(desc->num_modes)) { 463 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 464 return; 465 } 466 if (WARN_ON(!desc->num_timings)) { 467 dev_err(dev, "Reject override mode: no timings specified\n"); 468 return; 469 } 470 471 for (i = 0; i < panel->desc->num_timings; i++) { 472 const struct display_timing *dt = &panel->desc->timings[i]; 473 474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 482 continue; 483 484 if (ot->flags != dt->flags) 485 continue; 486 487 videomode_from_timing(ot, &vm); 488 drm_display_mode_from_videomode(&vm, &panel->override_mode); 489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 490 DRM_MODE_TYPE_PREFERRED; 491 break; 492 } 493 494 if (WARN_ON(!panel->override_mode.type)) 495 dev_err(dev, "Reject override mode: No display_timing found\n"); 496 } 497 498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 499 { 500 struct panel_simple *panel; 501 struct display_timing dt; 502 struct device_node *ddc; 503 int err; 504 505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 506 if (!panel) 507 return -ENOMEM; 508 509 panel->enabled = false; 510 panel->prepared = false; 511 panel->desc = desc; 512 513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 514 if (!panel->no_hpd) { 515 err = panel_simple_get_hpd_gpio(dev, panel, true); 516 if (err) 517 return err; 518 } 519 520 panel->supply = devm_regulator_get(dev, "power"); 521 if (IS_ERR(panel->supply)) 522 return PTR_ERR(panel->supply); 523 524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 525 GPIOD_OUT_LOW); 526 if (IS_ERR(panel->enable_gpio)) { 527 err = PTR_ERR(panel->enable_gpio); 528 if (err != -EPROBE_DEFER) 529 dev_err(dev, "failed to request GPIO: %d\n", err); 530 return err; 531 } 532 533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 534 if (ddc) { 535 panel->ddc = of_find_i2c_adapter_by_node(ddc); 536 of_node_put(ddc); 537 538 if (!panel->ddc) 539 return -EPROBE_DEFER; 540 } 541 542 if (desc == &panel_dpi) { 543 /* Handle the generic panel-dpi binding */ 544 err = panel_dpi_probe(dev, panel); 545 if (err) 546 goto free_ddc; 547 } else { 548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 549 panel_simple_parse_panel_timing_node(dev, panel, &dt); 550 } 551 552 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 553 desc->connector_type); 554 555 err = drm_panel_of_backlight(&panel->base); 556 if (err) 557 goto free_ddc; 558 559 err = drm_panel_add(&panel->base); 560 if (err < 0) 561 goto free_ddc; 562 563 dev_set_drvdata(dev, panel); 564 565 return 0; 566 567 free_ddc: 568 if (panel->ddc) 569 put_device(&panel->ddc->dev); 570 571 return err; 572 } 573 574 static int panel_simple_remove(struct device *dev) 575 { 576 struct panel_simple *panel = dev_get_drvdata(dev); 577 578 drm_panel_remove(&panel->base); 579 drm_panel_disable(&panel->base); 580 drm_panel_unprepare(&panel->base); 581 582 if (panel->ddc) 583 put_device(&panel->ddc->dev); 584 585 return 0; 586 } 587 588 static void panel_simple_shutdown(struct device *dev) 589 { 590 struct panel_simple *panel = dev_get_drvdata(dev); 591 592 drm_panel_disable(&panel->base); 593 drm_panel_unprepare(&panel->base); 594 } 595 596 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 597 .clock = 9000, 598 .hdisplay = 480, 599 .hsync_start = 480 + 2, 600 .hsync_end = 480 + 2 + 41, 601 .htotal = 480 + 2 + 41 + 2, 602 .vdisplay = 272, 603 .vsync_start = 272 + 2, 604 .vsync_end = 272 + 2 + 10, 605 .vtotal = 272 + 2 + 10 + 2, 606 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 607 }; 608 609 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 610 .modes = &ire_am_480272h3tmqw_t01h_mode, 611 .num_modes = 1, 612 .bpc = 8, 613 .size = { 614 .width = 105, 615 .height = 67, 616 }, 617 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 618 }; 619 620 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 621 .clock = 33333, 622 .hdisplay = 800, 623 .hsync_start = 800 + 0, 624 .hsync_end = 800 + 0 + 255, 625 .htotal = 800 + 0 + 255 + 0, 626 .vdisplay = 480, 627 .vsync_start = 480 + 2, 628 .vsync_end = 480 + 2 + 45, 629 .vtotal = 480 + 2 + 45 + 0, 630 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 631 }; 632 633 static const struct panel_desc ampire_am800480r3tmqwa1h = { 634 .modes = &ire_am800480r3tmqwa1h_mode, 635 .num_modes = 1, 636 .bpc = 6, 637 .size = { 638 .width = 152, 639 .height = 91, 640 }, 641 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 642 }; 643 644 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 645 .pixelclock = { 26400000, 33300000, 46800000 }, 646 .hactive = { 800, 800, 800 }, 647 .hfront_porch = { 16, 210, 354 }, 648 .hback_porch = { 45, 36, 6 }, 649 .hsync_len = { 1, 10, 40 }, 650 .vactive = { 480, 480, 480 }, 651 .vfront_porch = { 7, 22, 147 }, 652 .vback_porch = { 22, 13, 3 }, 653 .vsync_len = { 1, 10, 20 }, 654 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 655 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 656 }; 657 658 static const struct panel_desc armadeus_st0700_adapt = { 659 .timings = &santek_st0700i5y_rbslw_f_timing, 660 .num_timings = 1, 661 .bpc = 6, 662 .size = { 663 .width = 154, 664 .height = 86, 665 }, 666 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 667 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 668 }; 669 670 static const struct drm_display_mode auo_b101aw03_mode = { 671 .clock = 51450, 672 .hdisplay = 1024, 673 .hsync_start = 1024 + 156, 674 .hsync_end = 1024 + 156 + 8, 675 .htotal = 1024 + 156 + 8 + 156, 676 .vdisplay = 600, 677 .vsync_start = 600 + 16, 678 .vsync_end = 600 + 16 + 6, 679 .vtotal = 600 + 16 + 6 + 16, 680 }; 681 682 static const struct panel_desc auo_b101aw03 = { 683 .modes = &auo_b101aw03_mode, 684 .num_modes = 1, 685 .bpc = 6, 686 .size = { 687 .width = 223, 688 .height = 125, 689 }, 690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 691 }; 692 693 static const struct display_timing auo_b101ean01_timing = { 694 .pixelclock = { 65300000, 72500000, 75000000 }, 695 .hactive = { 1280, 1280, 1280 }, 696 .hfront_porch = { 18, 119, 119 }, 697 .hback_porch = { 21, 21, 21 }, 698 .hsync_len = { 32, 32, 32 }, 699 .vactive = { 800, 800, 800 }, 700 .vfront_porch = { 4, 4, 4 }, 701 .vback_porch = { 8, 8, 8 }, 702 .vsync_len = { 18, 20, 20 }, 703 }; 704 705 static const struct panel_desc auo_b101ean01 = { 706 .timings = &auo_b101ean01_timing, 707 .num_timings = 1, 708 .bpc = 6, 709 .size = { 710 .width = 217, 711 .height = 136, 712 }, 713 }; 714 715 static const struct drm_display_mode auo_b101xtn01_mode = { 716 .clock = 72000, 717 .hdisplay = 1366, 718 .hsync_start = 1366 + 20, 719 .hsync_end = 1366 + 20 + 70, 720 .htotal = 1366 + 20 + 70, 721 .vdisplay = 768, 722 .vsync_start = 768 + 14, 723 .vsync_end = 768 + 14 + 42, 724 .vtotal = 768 + 14 + 42, 725 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 726 }; 727 728 static const struct panel_desc auo_b101xtn01 = { 729 .modes = &auo_b101xtn01_mode, 730 .num_modes = 1, 731 .bpc = 6, 732 .size = { 733 .width = 223, 734 .height = 125, 735 }, 736 }; 737 738 static const struct drm_display_mode auo_b116xak01_mode = { 739 .clock = 69300, 740 .hdisplay = 1366, 741 .hsync_start = 1366 + 48, 742 .hsync_end = 1366 + 48 + 32, 743 .htotal = 1366 + 48 + 32 + 10, 744 .vdisplay = 768, 745 .vsync_start = 768 + 4, 746 .vsync_end = 768 + 4 + 6, 747 .vtotal = 768 + 4 + 6 + 15, 748 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 749 }; 750 751 static const struct panel_desc auo_b116xak01 = { 752 .modes = &auo_b116xak01_mode, 753 .num_modes = 1, 754 .bpc = 6, 755 .size = { 756 .width = 256, 757 .height = 144, 758 }, 759 .delay = { 760 .hpd_absent_delay = 200, 761 }, 762 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 763 .connector_type = DRM_MODE_CONNECTOR_eDP, 764 }; 765 766 static const struct drm_display_mode auo_b116xw03_mode = { 767 .clock = 70589, 768 .hdisplay = 1366, 769 .hsync_start = 1366 + 40, 770 .hsync_end = 1366 + 40 + 40, 771 .htotal = 1366 + 40 + 40 + 32, 772 .vdisplay = 768, 773 .vsync_start = 768 + 10, 774 .vsync_end = 768 + 10 + 12, 775 .vtotal = 768 + 10 + 12 + 6, 776 }; 777 778 static const struct panel_desc auo_b116xw03 = { 779 .modes = &auo_b116xw03_mode, 780 .num_modes = 1, 781 .bpc = 6, 782 .size = { 783 .width = 256, 784 .height = 144, 785 }, 786 }; 787 788 static const struct drm_display_mode auo_b133xtn01_mode = { 789 .clock = 69500, 790 .hdisplay = 1366, 791 .hsync_start = 1366 + 48, 792 .hsync_end = 1366 + 48 + 32, 793 .htotal = 1366 + 48 + 32 + 20, 794 .vdisplay = 768, 795 .vsync_start = 768 + 3, 796 .vsync_end = 768 + 3 + 6, 797 .vtotal = 768 + 3 + 6 + 13, 798 }; 799 800 static const struct panel_desc auo_b133xtn01 = { 801 .modes = &auo_b133xtn01_mode, 802 .num_modes = 1, 803 .bpc = 6, 804 .size = { 805 .width = 293, 806 .height = 165, 807 }, 808 }; 809 810 static const struct drm_display_mode auo_b133htn01_mode = { 811 .clock = 150660, 812 .hdisplay = 1920, 813 .hsync_start = 1920 + 172, 814 .hsync_end = 1920 + 172 + 80, 815 .htotal = 1920 + 172 + 80 + 60, 816 .vdisplay = 1080, 817 .vsync_start = 1080 + 25, 818 .vsync_end = 1080 + 25 + 10, 819 .vtotal = 1080 + 25 + 10 + 10, 820 }; 821 822 static const struct panel_desc auo_b133htn01 = { 823 .modes = &auo_b133htn01_mode, 824 .num_modes = 1, 825 .bpc = 6, 826 .size = { 827 .width = 293, 828 .height = 165, 829 }, 830 .delay = { 831 .prepare = 105, 832 .enable = 20, 833 .unprepare = 50, 834 }, 835 }; 836 837 static const struct display_timing auo_g070vvn01_timings = { 838 .pixelclock = { 33300000, 34209000, 45000000 }, 839 .hactive = { 800, 800, 800 }, 840 .hfront_porch = { 20, 40, 200 }, 841 .hback_porch = { 87, 40, 1 }, 842 .hsync_len = { 1, 48, 87 }, 843 .vactive = { 480, 480, 480 }, 844 .vfront_porch = { 5, 13, 200 }, 845 .vback_porch = { 31, 31, 29 }, 846 .vsync_len = { 1, 1, 3 }, 847 }; 848 849 static const struct panel_desc auo_g070vvn01 = { 850 .timings = &auo_g070vvn01_timings, 851 .num_timings = 1, 852 .bpc = 8, 853 .size = { 854 .width = 152, 855 .height = 91, 856 }, 857 .delay = { 858 .prepare = 200, 859 .enable = 50, 860 .disable = 50, 861 .unprepare = 1000, 862 }, 863 }; 864 865 static const struct drm_display_mode auo_g101evn010_mode = { 866 .clock = 68930, 867 .hdisplay = 1280, 868 .hsync_start = 1280 + 82, 869 .hsync_end = 1280 + 82 + 2, 870 .htotal = 1280 + 82 + 2 + 84, 871 .vdisplay = 800, 872 .vsync_start = 800 + 8, 873 .vsync_end = 800 + 8 + 2, 874 .vtotal = 800 + 8 + 2 + 6, 875 }; 876 877 static const struct panel_desc auo_g101evn010 = { 878 .modes = &auo_g101evn010_mode, 879 .num_modes = 1, 880 .bpc = 6, 881 .size = { 882 .width = 216, 883 .height = 135, 884 }, 885 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 886 .connector_type = DRM_MODE_CONNECTOR_LVDS, 887 }; 888 889 static const struct drm_display_mode auo_g104sn02_mode = { 890 .clock = 40000, 891 .hdisplay = 800, 892 .hsync_start = 800 + 40, 893 .hsync_end = 800 + 40 + 216, 894 .htotal = 800 + 40 + 216 + 128, 895 .vdisplay = 600, 896 .vsync_start = 600 + 10, 897 .vsync_end = 600 + 10 + 35, 898 .vtotal = 600 + 10 + 35 + 2, 899 }; 900 901 static const struct panel_desc auo_g104sn02 = { 902 .modes = &auo_g104sn02_mode, 903 .num_modes = 1, 904 .bpc = 8, 905 .size = { 906 .width = 211, 907 .height = 158, 908 }, 909 }; 910 911 static const struct drm_display_mode auo_g121ean01_mode = { 912 .clock = 66700, 913 .hdisplay = 1280, 914 .hsync_start = 1280 + 58, 915 .hsync_end = 1280 + 58 + 8, 916 .htotal = 1280 + 58 + 8 + 70, 917 .vdisplay = 800, 918 .vsync_start = 800 + 6, 919 .vsync_end = 800 + 6 + 4, 920 .vtotal = 800 + 6 + 4 + 10, 921 }; 922 923 static const struct panel_desc auo_g121ean01 = { 924 .modes = &auo_g121ean01_mode, 925 .num_modes = 1, 926 .bpc = 8, 927 .size = { 928 .width = 261, 929 .height = 163, 930 }, 931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 933 }; 934 935 static const struct display_timing auo_g133han01_timings = { 936 .pixelclock = { 134000000, 141200000, 149000000 }, 937 .hactive = { 1920, 1920, 1920 }, 938 .hfront_porch = { 39, 58, 77 }, 939 .hback_porch = { 59, 88, 117 }, 940 .hsync_len = { 28, 42, 56 }, 941 .vactive = { 1080, 1080, 1080 }, 942 .vfront_porch = { 3, 8, 11 }, 943 .vback_porch = { 5, 14, 19 }, 944 .vsync_len = { 4, 14, 19 }, 945 }; 946 947 static const struct panel_desc auo_g133han01 = { 948 .timings = &auo_g133han01_timings, 949 .num_timings = 1, 950 .bpc = 8, 951 .size = { 952 .width = 293, 953 .height = 165, 954 }, 955 .delay = { 956 .prepare = 200, 957 .enable = 50, 958 .disable = 50, 959 .unprepare = 1000, 960 }, 961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 962 .connector_type = DRM_MODE_CONNECTOR_LVDS, 963 }; 964 965 static const struct drm_display_mode auo_g156xtn01_mode = { 966 .clock = 76000, 967 .hdisplay = 1366, 968 .hsync_start = 1366 + 33, 969 .hsync_end = 1366 + 33 + 67, 970 .htotal = 1560, 971 .vdisplay = 768, 972 .vsync_start = 768 + 4, 973 .vsync_end = 768 + 4 + 4, 974 .vtotal = 806, 975 }; 976 977 static const struct panel_desc auo_g156xtn01 = { 978 .modes = &auo_g156xtn01_mode, 979 .num_modes = 1, 980 .bpc = 8, 981 .size = { 982 .width = 344, 983 .height = 194, 984 }, 985 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 986 .connector_type = DRM_MODE_CONNECTOR_LVDS, 987 }; 988 989 static const struct display_timing auo_g185han01_timings = { 990 .pixelclock = { 120000000, 144000000, 175000000 }, 991 .hactive = { 1920, 1920, 1920 }, 992 .hfront_porch = { 36, 120, 148 }, 993 .hback_porch = { 24, 88, 108 }, 994 .hsync_len = { 20, 48, 64 }, 995 .vactive = { 1080, 1080, 1080 }, 996 .vfront_porch = { 6, 10, 40 }, 997 .vback_porch = { 2, 5, 20 }, 998 .vsync_len = { 2, 5, 20 }, 999 }; 1000 1001 static const struct panel_desc auo_g185han01 = { 1002 .timings = &auo_g185han01_timings, 1003 .num_timings = 1, 1004 .bpc = 8, 1005 .size = { 1006 .width = 409, 1007 .height = 230, 1008 }, 1009 .delay = { 1010 .prepare = 50, 1011 .enable = 200, 1012 .disable = 110, 1013 .unprepare = 1000, 1014 }, 1015 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1016 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1017 }; 1018 1019 static const struct display_timing auo_g190ean01_timings = { 1020 .pixelclock = { 90000000, 108000000, 135000000 }, 1021 .hactive = { 1280, 1280, 1280 }, 1022 .hfront_porch = { 126, 184, 1266 }, 1023 .hback_porch = { 84, 122, 844 }, 1024 .hsync_len = { 70, 102, 704 }, 1025 .vactive = { 1024, 1024, 1024 }, 1026 .vfront_porch = { 4, 26, 76 }, 1027 .vback_porch = { 2, 8, 25 }, 1028 .vsync_len = { 2, 8, 25 }, 1029 }; 1030 1031 static const struct panel_desc auo_g190ean01 = { 1032 .timings = &auo_g190ean01_timings, 1033 .num_timings = 1, 1034 .bpc = 8, 1035 .size = { 1036 .width = 376, 1037 .height = 301, 1038 }, 1039 .delay = { 1040 .prepare = 50, 1041 .enable = 200, 1042 .disable = 110, 1043 .unprepare = 1000, 1044 }, 1045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1047 }; 1048 1049 static const struct display_timing auo_p320hvn03_timings = { 1050 .pixelclock = { 106000000, 148500000, 164000000 }, 1051 .hactive = { 1920, 1920, 1920 }, 1052 .hfront_porch = { 25, 50, 130 }, 1053 .hback_porch = { 25, 50, 130 }, 1054 .hsync_len = { 20, 40, 105 }, 1055 .vactive = { 1080, 1080, 1080 }, 1056 .vfront_porch = { 8, 17, 150 }, 1057 .vback_porch = { 8, 17, 150 }, 1058 .vsync_len = { 4, 11, 100 }, 1059 }; 1060 1061 static const struct panel_desc auo_p320hvn03 = { 1062 .timings = &auo_p320hvn03_timings, 1063 .num_timings = 1, 1064 .bpc = 8, 1065 .size = { 1066 .width = 698, 1067 .height = 393, 1068 }, 1069 .delay = { 1070 .prepare = 1, 1071 .enable = 450, 1072 .unprepare = 500, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_t215hvn01_mode = { 1079 .clock = 148800, 1080 .hdisplay = 1920, 1081 .hsync_start = 1920 + 88, 1082 .hsync_end = 1920 + 88 + 44, 1083 .htotal = 1920 + 88 + 44 + 148, 1084 .vdisplay = 1080, 1085 .vsync_start = 1080 + 4, 1086 .vsync_end = 1080 + 4 + 5, 1087 .vtotal = 1080 + 4 + 5 + 36, 1088 }; 1089 1090 static const struct panel_desc auo_t215hvn01 = { 1091 .modes = &auo_t215hvn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 430, 1096 .height = 270, 1097 }, 1098 .delay = { 1099 .disable = 5, 1100 .unprepare = 1000, 1101 } 1102 }; 1103 1104 static const struct drm_display_mode avic_tm070ddh03_mode = { 1105 .clock = 51200, 1106 .hdisplay = 1024, 1107 .hsync_start = 1024 + 160, 1108 .hsync_end = 1024 + 160 + 4, 1109 .htotal = 1024 + 160 + 4 + 156, 1110 .vdisplay = 600, 1111 .vsync_start = 600 + 17, 1112 .vsync_end = 600 + 17 + 1, 1113 .vtotal = 600 + 17 + 1 + 17, 1114 }; 1115 1116 static const struct panel_desc avic_tm070ddh03 = { 1117 .modes = &avic_tm070ddh03_mode, 1118 .num_modes = 1, 1119 .bpc = 8, 1120 .size = { 1121 .width = 154, 1122 .height = 90, 1123 }, 1124 .delay = { 1125 .prepare = 20, 1126 .enable = 200, 1127 .disable = 200, 1128 }, 1129 }; 1130 1131 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1132 .clock = 30000, 1133 .hdisplay = 800, 1134 .hsync_start = 800 + 40, 1135 .hsync_end = 800 + 40 + 48, 1136 .htotal = 800 + 40 + 48 + 40, 1137 .vdisplay = 480, 1138 .vsync_start = 480 + 13, 1139 .vsync_end = 480 + 13 + 3, 1140 .vtotal = 480 + 13 + 3 + 29, 1141 }; 1142 1143 static const struct panel_desc bananapi_s070wv20_ct16 = { 1144 .modes = &bananapi_s070wv20_ct16_mode, 1145 .num_modes = 1, 1146 .bpc = 6, 1147 .size = { 1148 .width = 154, 1149 .height = 86, 1150 }, 1151 }; 1152 1153 static const struct drm_display_mode boe_hv070wsa_mode = { 1154 .clock = 42105, 1155 .hdisplay = 1024, 1156 .hsync_start = 1024 + 30, 1157 .hsync_end = 1024 + 30 + 30, 1158 .htotal = 1024 + 30 + 30 + 30, 1159 .vdisplay = 600, 1160 .vsync_start = 600 + 10, 1161 .vsync_end = 600 + 10 + 10, 1162 .vtotal = 600 + 10 + 10 + 10, 1163 }; 1164 1165 static const struct panel_desc boe_hv070wsa = { 1166 .modes = &boe_hv070wsa_mode, 1167 .num_modes = 1, 1168 .size = { 1169 .width = 154, 1170 .height = 90, 1171 }, 1172 }; 1173 1174 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1175 { 1176 .clock = 71900, 1177 .hdisplay = 1280, 1178 .hsync_start = 1280 + 48, 1179 .hsync_end = 1280 + 48 + 32, 1180 .htotal = 1280 + 48 + 32 + 80, 1181 .vdisplay = 800, 1182 .vsync_start = 800 + 3, 1183 .vsync_end = 800 + 3 + 5, 1184 .vtotal = 800 + 3 + 5 + 24, 1185 }, 1186 { 1187 .clock = 57500, 1188 .hdisplay = 1280, 1189 .hsync_start = 1280 + 48, 1190 .hsync_end = 1280 + 48 + 32, 1191 .htotal = 1280 + 48 + 32 + 80, 1192 .vdisplay = 800, 1193 .vsync_start = 800 + 3, 1194 .vsync_end = 800 + 3 + 5, 1195 .vtotal = 800 + 3 + 5 + 24, 1196 }, 1197 }; 1198 1199 static const struct panel_desc boe_nv101wxmn51 = { 1200 .modes = boe_nv101wxmn51_modes, 1201 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1202 .bpc = 8, 1203 .size = { 1204 .width = 217, 1205 .height = 136, 1206 }, 1207 .delay = { 1208 .prepare = 210, 1209 .enable = 50, 1210 .unprepare = 160, 1211 }, 1212 }; 1213 1214 /* Also used for boe_nv133fhm_n62 */ 1215 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1216 .clock = 147840, 1217 .hdisplay = 1920, 1218 .hsync_start = 1920 + 48, 1219 .hsync_end = 1920 + 48 + 32, 1220 .htotal = 1920 + 48 + 32 + 200, 1221 .vdisplay = 1080, 1222 .vsync_start = 1080 + 3, 1223 .vsync_end = 1080 + 3 + 6, 1224 .vtotal = 1080 + 3 + 6 + 31, 1225 }; 1226 1227 /* Also used for boe_nv133fhm_n62 */ 1228 static const struct panel_desc boe_nv133fhm_n61 = { 1229 .modes = &boe_nv133fhm_n61_modes, 1230 .num_modes = 1, 1231 .bpc = 6, 1232 .size = { 1233 .width = 294, 1234 .height = 165, 1235 }, 1236 .delay = { 1237 .hpd_absent_delay = 200, 1238 .unprepare = 500, 1239 }, 1240 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1241 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1242 .connector_type = DRM_MODE_CONNECTOR_eDP, 1243 }; 1244 1245 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1246 { 1247 .clock = 148500, 1248 .hdisplay = 1920, 1249 .hsync_start = 1920 + 48, 1250 .hsync_end = 1920 + 48 + 32, 1251 .htotal = 2200, 1252 .vdisplay = 1080, 1253 .vsync_start = 1080 + 3, 1254 .vsync_end = 1080 + 3 + 5, 1255 .vtotal = 1125, 1256 }, 1257 }; 1258 1259 static const struct panel_desc boe_nv140fhmn49 = { 1260 .modes = boe_nv140fhmn49_modes, 1261 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1262 .bpc = 6, 1263 .size = { 1264 .width = 309, 1265 .height = 174, 1266 }, 1267 .delay = { 1268 .prepare = 210, 1269 .enable = 50, 1270 .unprepare = 160, 1271 }, 1272 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1273 .connector_type = DRM_MODE_CONNECTOR_eDP, 1274 }; 1275 1276 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1277 .clock = 9000, 1278 .hdisplay = 480, 1279 .hsync_start = 480 + 5, 1280 .hsync_end = 480 + 5 + 5, 1281 .htotal = 480 + 5 + 5 + 40, 1282 .vdisplay = 272, 1283 .vsync_start = 272 + 8, 1284 .vsync_end = 272 + 8 + 8, 1285 .vtotal = 272 + 8 + 8 + 8, 1286 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1287 }; 1288 1289 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1290 .modes = &cdtech_s043wq26h_ct7_mode, 1291 .num_modes = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 95, 1295 .height = 54, 1296 }, 1297 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1298 }; 1299 1300 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1301 .clock = 35000, 1302 .hdisplay = 800, 1303 .hsync_start = 800 + 40, 1304 .hsync_end = 800 + 40 + 40, 1305 .htotal = 800 + 40 + 40 + 48, 1306 .vdisplay = 480, 1307 .vsync_start = 480 + 29, 1308 .vsync_end = 480 + 29 + 13, 1309 .vtotal = 480 + 29 + 13 + 3, 1310 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1311 }; 1312 1313 static const struct panel_desc cdtech_s070wv95_ct16 = { 1314 .modes = &cdtech_s070wv95_ct16_mode, 1315 .num_modes = 1, 1316 .bpc = 8, 1317 .size = { 1318 .width = 154, 1319 .height = 85, 1320 }, 1321 }; 1322 1323 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1324 .clock = 66770, 1325 .hdisplay = 800, 1326 .hsync_start = 800 + 49, 1327 .hsync_end = 800 + 49 + 33, 1328 .htotal = 800 + 49 + 33 + 17, 1329 .vdisplay = 1280, 1330 .vsync_start = 1280 + 1, 1331 .vsync_end = 1280 + 1 + 7, 1332 .vtotal = 1280 + 1 + 7 + 15, 1333 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1334 }; 1335 1336 static const struct panel_desc chunghwa_claa070wp03xg = { 1337 .modes = &chunghwa_claa070wp03xg_mode, 1338 .num_modes = 1, 1339 .bpc = 6, 1340 .size = { 1341 .width = 94, 1342 .height = 150, 1343 }, 1344 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1345 }; 1346 1347 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1348 .clock = 72070, 1349 .hdisplay = 1366, 1350 .hsync_start = 1366 + 58, 1351 .hsync_end = 1366 + 58 + 58, 1352 .htotal = 1366 + 58 + 58 + 58, 1353 .vdisplay = 768, 1354 .vsync_start = 768 + 4, 1355 .vsync_end = 768 + 4 + 4, 1356 .vtotal = 768 + 4 + 4 + 4, 1357 }; 1358 1359 static const struct panel_desc chunghwa_claa101wa01a = { 1360 .modes = &chunghwa_claa101wa01a_mode, 1361 .num_modes = 1, 1362 .bpc = 6, 1363 .size = { 1364 .width = 220, 1365 .height = 120, 1366 }, 1367 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1368 }; 1369 1370 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1371 .clock = 69300, 1372 .hdisplay = 1366, 1373 .hsync_start = 1366 + 48, 1374 .hsync_end = 1366 + 48 + 32, 1375 .htotal = 1366 + 48 + 32 + 20, 1376 .vdisplay = 768, 1377 .vsync_start = 768 + 16, 1378 .vsync_end = 768 + 16 + 8, 1379 .vtotal = 768 + 16 + 8 + 16, 1380 }; 1381 1382 static const struct panel_desc chunghwa_claa101wb01 = { 1383 .modes = &chunghwa_claa101wb01_mode, 1384 .num_modes = 1, 1385 .bpc = 6, 1386 .size = { 1387 .width = 223, 1388 .height = 125, 1389 }, 1390 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1391 }; 1392 1393 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1394 .clock = 33260, 1395 .hdisplay = 800, 1396 .hsync_start = 800 + 40, 1397 .hsync_end = 800 + 40 + 128, 1398 .htotal = 800 + 40 + 128 + 88, 1399 .vdisplay = 480, 1400 .vsync_start = 480 + 10, 1401 .vsync_end = 480 + 10 + 2, 1402 .vtotal = 480 + 10 + 2 + 33, 1403 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1404 }; 1405 1406 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1407 .modes = &dataimage_scf0700c48ggu18_mode, 1408 .num_modes = 1, 1409 .bpc = 8, 1410 .size = { 1411 .width = 152, 1412 .height = 91, 1413 }, 1414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1416 }; 1417 1418 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1419 .pixelclock = { 45000000, 51200000, 57000000 }, 1420 .hactive = { 1024, 1024, 1024 }, 1421 .hfront_porch = { 100, 106, 113 }, 1422 .hback_porch = { 100, 106, 113 }, 1423 .hsync_len = { 100, 108, 114 }, 1424 .vactive = { 600, 600, 600 }, 1425 .vfront_porch = { 8, 11, 15 }, 1426 .vback_porch = { 8, 11, 15 }, 1427 .vsync_len = { 9, 13, 15 }, 1428 .flags = DISPLAY_FLAGS_DE_HIGH, 1429 }; 1430 1431 static const struct panel_desc dlc_dlc0700yzg_1 = { 1432 .timings = &dlc_dlc0700yzg_1_timing, 1433 .num_timings = 1, 1434 .bpc = 6, 1435 .size = { 1436 .width = 154, 1437 .height = 86, 1438 }, 1439 .delay = { 1440 .prepare = 30, 1441 .enable = 200, 1442 .disable = 200, 1443 }, 1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1445 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1446 }; 1447 1448 static const struct display_timing dlc_dlc1010gig_timing = { 1449 .pixelclock = { 68900000, 71100000, 73400000 }, 1450 .hactive = { 1280, 1280, 1280 }, 1451 .hfront_porch = { 43, 53, 63 }, 1452 .hback_porch = { 43, 53, 63 }, 1453 .hsync_len = { 44, 54, 64 }, 1454 .vactive = { 800, 800, 800 }, 1455 .vfront_porch = { 5, 8, 11 }, 1456 .vback_porch = { 5, 8, 11 }, 1457 .vsync_len = { 5, 7, 11 }, 1458 .flags = DISPLAY_FLAGS_DE_HIGH, 1459 }; 1460 1461 static const struct panel_desc dlc_dlc1010gig = { 1462 .timings = &dlc_dlc1010gig_timing, 1463 .num_timings = 1, 1464 .bpc = 8, 1465 .size = { 1466 .width = 216, 1467 .height = 135, 1468 }, 1469 .delay = { 1470 .prepare = 60, 1471 .enable = 150, 1472 .disable = 100, 1473 .unprepare = 60, 1474 }, 1475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1477 }; 1478 1479 static const struct drm_display_mode edt_et035012dm6_mode = { 1480 .clock = 6500, 1481 .hdisplay = 320, 1482 .hsync_start = 320 + 20, 1483 .hsync_end = 320 + 20 + 30, 1484 .htotal = 320 + 20 + 68, 1485 .vdisplay = 240, 1486 .vsync_start = 240 + 4, 1487 .vsync_end = 240 + 4 + 4, 1488 .vtotal = 240 + 4 + 4 + 14, 1489 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1490 }; 1491 1492 static const struct panel_desc edt_et035012dm6 = { 1493 .modes = &edt_et035012dm6_mode, 1494 .num_modes = 1, 1495 .bpc = 8, 1496 .size = { 1497 .width = 70, 1498 .height = 52, 1499 }, 1500 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1501 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1502 }; 1503 1504 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1505 .clock = 10870, 1506 .hdisplay = 480, 1507 .hsync_start = 480 + 8, 1508 .hsync_end = 480 + 8 + 4, 1509 .htotal = 480 + 8 + 4 + 41, 1510 1511 /* 1512 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1513 * fb_align 1514 */ 1515 1516 .vdisplay = 288, 1517 .vsync_start = 288 + 2, 1518 .vsync_end = 288 + 2 + 4, 1519 .vtotal = 288 + 2 + 4 + 10, 1520 }; 1521 1522 static const struct panel_desc edt_etm043080dh6gp = { 1523 .modes = &edt_etm043080dh6gp_mode, 1524 .num_modes = 1, 1525 .bpc = 8, 1526 .size = { 1527 .width = 100, 1528 .height = 65, 1529 }, 1530 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1531 .connector_type = DRM_MODE_CONNECTOR_DPI, 1532 }; 1533 1534 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1535 .clock = 9000, 1536 .hdisplay = 480, 1537 .hsync_start = 480 + 2, 1538 .hsync_end = 480 + 2 + 41, 1539 .htotal = 480 + 2 + 41 + 2, 1540 .vdisplay = 272, 1541 .vsync_start = 272 + 2, 1542 .vsync_end = 272 + 2 + 10, 1543 .vtotal = 272 + 2 + 10 + 2, 1544 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1545 }; 1546 1547 static const struct panel_desc edt_etm0430g0dh6 = { 1548 .modes = &edt_etm0430g0dh6_mode, 1549 .num_modes = 1, 1550 .bpc = 6, 1551 .size = { 1552 .width = 95, 1553 .height = 54, 1554 }, 1555 }; 1556 1557 static const struct drm_display_mode edt_et057090dhu_mode = { 1558 .clock = 25175, 1559 .hdisplay = 640, 1560 .hsync_start = 640 + 16, 1561 .hsync_end = 640 + 16 + 30, 1562 .htotal = 640 + 16 + 30 + 114, 1563 .vdisplay = 480, 1564 .vsync_start = 480 + 10, 1565 .vsync_end = 480 + 10 + 3, 1566 .vtotal = 480 + 10 + 3 + 32, 1567 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1568 }; 1569 1570 static const struct panel_desc edt_et057090dhu = { 1571 .modes = &edt_et057090dhu_mode, 1572 .num_modes = 1, 1573 .bpc = 6, 1574 .size = { 1575 .width = 115, 1576 .height = 86, 1577 }, 1578 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1580 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1581 }; 1582 1583 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1584 .clock = 33260, 1585 .hdisplay = 800, 1586 .hsync_start = 800 + 40, 1587 .hsync_end = 800 + 40 + 128, 1588 .htotal = 800 + 40 + 128 + 88, 1589 .vdisplay = 480, 1590 .vsync_start = 480 + 10, 1591 .vsync_end = 480 + 10 + 2, 1592 .vtotal = 480 + 10 + 2 + 33, 1593 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1594 }; 1595 1596 static const struct panel_desc edt_etm0700g0dh6 = { 1597 .modes = &edt_etm0700g0dh6_mode, 1598 .num_modes = 1, 1599 .bpc = 6, 1600 .size = { 1601 .width = 152, 1602 .height = 91, 1603 }, 1604 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1606 }; 1607 1608 static const struct panel_desc edt_etm0700g0bdh6 = { 1609 .modes = &edt_etm0700g0dh6_mode, 1610 .num_modes = 1, 1611 .bpc = 6, 1612 .size = { 1613 .width = 152, 1614 .height = 91, 1615 }, 1616 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1617 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1618 }; 1619 1620 static const struct display_timing evervision_vgg804821_timing = { 1621 .pixelclock = { 27600000, 33300000, 50000000 }, 1622 .hactive = { 800, 800, 800 }, 1623 .hfront_porch = { 40, 66, 70 }, 1624 .hback_porch = { 40, 67, 70 }, 1625 .hsync_len = { 40, 67, 70 }, 1626 .vactive = { 480, 480, 480 }, 1627 .vfront_porch = { 6, 10, 10 }, 1628 .vback_porch = { 7, 11, 11 }, 1629 .vsync_len = { 7, 11, 11 }, 1630 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1631 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1632 DISPLAY_FLAGS_SYNC_NEGEDGE, 1633 }; 1634 1635 static const struct panel_desc evervision_vgg804821 = { 1636 .timings = &evervision_vgg804821_timing, 1637 .num_timings = 1, 1638 .bpc = 8, 1639 .size = { 1640 .width = 108, 1641 .height = 64, 1642 }, 1643 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1644 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1645 }; 1646 1647 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1648 .clock = 32260, 1649 .hdisplay = 800, 1650 .hsync_start = 800 + 168, 1651 .hsync_end = 800 + 168 + 64, 1652 .htotal = 800 + 168 + 64 + 88, 1653 .vdisplay = 480, 1654 .vsync_start = 480 + 37, 1655 .vsync_end = 480 + 37 + 2, 1656 .vtotal = 480 + 37 + 2 + 8, 1657 }; 1658 1659 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1660 .modes = &foxlink_fl500wvr00_a0t_mode, 1661 .num_modes = 1, 1662 .bpc = 8, 1663 .size = { 1664 .width = 108, 1665 .height = 65, 1666 }, 1667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1668 }; 1669 1670 static const struct drm_display_mode frida_frd350h54004_mode = { 1671 .clock = 6000, 1672 .hdisplay = 320, 1673 .hsync_start = 320 + 44, 1674 .hsync_end = 320 + 44 + 16, 1675 .htotal = 320 + 44 + 16 + 20, 1676 .vdisplay = 240, 1677 .vsync_start = 240 + 2, 1678 .vsync_end = 240 + 2 + 6, 1679 .vtotal = 240 + 2 + 6 + 2, 1680 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1681 }; 1682 1683 static const struct panel_desc frida_frd350h54004 = { 1684 .modes = &frida_frd350h54004_mode, 1685 .num_modes = 1, 1686 .bpc = 8, 1687 .size = { 1688 .width = 77, 1689 .height = 64, 1690 }, 1691 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1692 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1693 .connector_type = DRM_MODE_CONNECTOR_DPI, 1694 }; 1695 1696 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1697 .clock = 67185, 1698 .hdisplay = 800, 1699 .hsync_start = 800 + 20, 1700 .hsync_end = 800 + 20 + 24, 1701 .htotal = 800 + 20 + 24 + 20, 1702 .vdisplay = 1280, 1703 .vsync_start = 1280 + 4, 1704 .vsync_end = 1280 + 4 + 8, 1705 .vtotal = 1280 + 4 + 8 + 4, 1706 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1707 }; 1708 1709 static const struct panel_desc friendlyarm_hd702e = { 1710 .modes = &friendlyarm_hd702e_mode, 1711 .num_modes = 1, 1712 .size = { 1713 .width = 94, 1714 .height = 151, 1715 }, 1716 }; 1717 1718 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1719 .clock = 9000, 1720 .hdisplay = 480, 1721 .hsync_start = 480 + 5, 1722 .hsync_end = 480 + 5 + 1, 1723 .htotal = 480 + 5 + 1 + 40, 1724 .vdisplay = 272, 1725 .vsync_start = 272 + 8, 1726 .vsync_end = 272 + 8 + 1, 1727 .vtotal = 272 + 8 + 1 + 8, 1728 }; 1729 1730 static const struct panel_desc giantplus_gpg482739qs5 = { 1731 .modes = &giantplus_gpg482739qs5_mode, 1732 .num_modes = 1, 1733 .bpc = 8, 1734 .size = { 1735 .width = 95, 1736 .height = 54, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1739 }; 1740 1741 static const struct display_timing giantplus_gpm940b0_timing = { 1742 .pixelclock = { 13500000, 27000000, 27500000 }, 1743 .hactive = { 320, 320, 320 }, 1744 .hfront_porch = { 14, 686, 718 }, 1745 .hback_porch = { 50, 70, 255 }, 1746 .hsync_len = { 1, 1, 1 }, 1747 .vactive = { 240, 240, 240 }, 1748 .vfront_porch = { 1, 1, 179 }, 1749 .vback_porch = { 1, 21, 31 }, 1750 .vsync_len = { 1, 1, 6 }, 1751 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1752 }; 1753 1754 static const struct panel_desc giantplus_gpm940b0 = { 1755 .timings = &giantplus_gpm940b0_timing, 1756 .num_timings = 1, 1757 .bpc = 8, 1758 .size = { 1759 .width = 60, 1760 .height = 45, 1761 }, 1762 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1763 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1764 }; 1765 1766 static const struct display_timing hannstar_hsd070pww1_timing = { 1767 .pixelclock = { 64300000, 71100000, 82000000 }, 1768 .hactive = { 1280, 1280, 1280 }, 1769 .hfront_porch = { 1, 1, 10 }, 1770 .hback_porch = { 1, 1, 10 }, 1771 /* 1772 * According to the data sheet, the minimum horizontal blanking interval 1773 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1774 * minimum working horizontal blanking interval to be 60 clocks. 1775 */ 1776 .hsync_len = { 58, 158, 661 }, 1777 .vactive = { 800, 800, 800 }, 1778 .vfront_porch = { 1, 1, 10 }, 1779 .vback_porch = { 1, 1, 10 }, 1780 .vsync_len = { 1, 21, 203 }, 1781 .flags = DISPLAY_FLAGS_DE_HIGH, 1782 }; 1783 1784 static const struct panel_desc hannstar_hsd070pww1 = { 1785 .timings = &hannstar_hsd070pww1_timing, 1786 .num_timings = 1, 1787 .bpc = 6, 1788 .size = { 1789 .width = 151, 1790 .height = 94, 1791 }, 1792 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1794 }; 1795 1796 static const struct display_timing hannstar_hsd100pxn1_timing = { 1797 .pixelclock = { 55000000, 65000000, 75000000 }, 1798 .hactive = { 1024, 1024, 1024 }, 1799 .hfront_porch = { 40, 40, 40 }, 1800 .hback_porch = { 220, 220, 220 }, 1801 .hsync_len = { 20, 60, 100 }, 1802 .vactive = { 768, 768, 768 }, 1803 .vfront_porch = { 7, 7, 7 }, 1804 .vback_porch = { 21, 21, 21 }, 1805 .vsync_len = { 10, 10, 10 }, 1806 .flags = DISPLAY_FLAGS_DE_HIGH, 1807 }; 1808 1809 static const struct panel_desc hannstar_hsd100pxn1 = { 1810 .timings = &hannstar_hsd100pxn1_timing, 1811 .num_timings = 1, 1812 .bpc = 6, 1813 .size = { 1814 .width = 203, 1815 .height = 152, 1816 }, 1817 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1818 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1819 }; 1820 1821 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1822 .clock = 33333, 1823 .hdisplay = 800, 1824 .hsync_start = 800 + 85, 1825 .hsync_end = 800 + 85 + 86, 1826 .htotal = 800 + 85 + 86 + 85, 1827 .vdisplay = 480, 1828 .vsync_start = 480 + 16, 1829 .vsync_end = 480 + 16 + 13, 1830 .vtotal = 480 + 16 + 13 + 16, 1831 }; 1832 1833 static const struct panel_desc hitachi_tx23d38vm0caa = { 1834 .modes = &hitachi_tx23d38vm0caa_mode, 1835 .num_modes = 1, 1836 .bpc = 6, 1837 .size = { 1838 .width = 195, 1839 .height = 117, 1840 }, 1841 .delay = { 1842 .enable = 160, 1843 .disable = 160, 1844 }, 1845 }; 1846 1847 static const struct drm_display_mode innolux_at043tn24_mode = { 1848 .clock = 9000, 1849 .hdisplay = 480, 1850 .hsync_start = 480 + 2, 1851 .hsync_end = 480 + 2 + 41, 1852 .htotal = 480 + 2 + 41 + 2, 1853 .vdisplay = 272, 1854 .vsync_start = 272 + 2, 1855 .vsync_end = 272 + 2 + 10, 1856 .vtotal = 272 + 2 + 10 + 2, 1857 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1858 }; 1859 1860 static const struct panel_desc innolux_at043tn24 = { 1861 .modes = &innolux_at043tn24_mode, 1862 .num_modes = 1, 1863 .bpc = 8, 1864 .size = { 1865 .width = 95, 1866 .height = 54, 1867 }, 1868 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1869 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1870 }; 1871 1872 static const struct drm_display_mode innolux_at070tn92_mode = { 1873 .clock = 33333, 1874 .hdisplay = 800, 1875 .hsync_start = 800 + 210, 1876 .hsync_end = 800 + 210 + 20, 1877 .htotal = 800 + 210 + 20 + 46, 1878 .vdisplay = 480, 1879 .vsync_start = 480 + 22, 1880 .vsync_end = 480 + 22 + 10, 1881 .vtotal = 480 + 22 + 23 + 10, 1882 }; 1883 1884 static const struct panel_desc innolux_at070tn92 = { 1885 .modes = &innolux_at070tn92_mode, 1886 .num_modes = 1, 1887 .size = { 1888 .width = 154, 1889 .height = 86, 1890 }, 1891 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1892 }; 1893 1894 static const struct display_timing innolux_g070y2_l01_timing = { 1895 .pixelclock = { 28000000, 29500000, 32000000 }, 1896 .hactive = { 800, 800, 800 }, 1897 .hfront_porch = { 61, 91, 141 }, 1898 .hback_porch = { 60, 90, 140 }, 1899 .hsync_len = { 12, 12, 12 }, 1900 .vactive = { 480, 480, 480 }, 1901 .vfront_porch = { 4, 9, 30 }, 1902 .vback_porch = { 4, 8, 28 }, 1903 .vsync_len = { 2, 2, 2 }, 1904 .flags = DISPLAY_FLAGS_DE_HIGH, 1905 }; 1906 1907 static const struct panel_desc innolux_g070y2_l01 = { 1908 .timings = &innolux_g070y2_l01_timing, 1909 .num_timings = 1, 1910 .bpc = 6, 1911 .size = { 1912 .width = 152, 1913 .height = 91, 1914 }, 1915 .delay = { 1916 .prepare = 10, 1917 .enable = 100, 1918 .disable = 100, 1919 .unprepare = 800, 1920 }, 1921 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1922 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1923 }; 1924 1925 static const struct display_timing innolux_g101ice_l01_timing = { 1926 .pixelclock = { 60400000, 71100000, 74700000 }, 1927 .hactive = { 1280, 1280, 1280 }, 1928 .hfront_porch = { 41, 80, 100 }, 1929 .hback_porch = { 40, 79, 99 }, 1930 .hsync_len = { 1, 1, 1 }, 1931 .vactive = { 800, 800, 800 }, 1932 .vfront_porch = { 5, 11, 14 }, 1933 .vback_porch = { 4, 11, 14 }, 1934 .vsync_len = { 1, 1, 1 }, 1935 .flags = DISPLAY_FLAGS_DE_HIGH, 1936 }; 1937 1938 static const struct panel_desc innolux_g101ice_l01 = { 1939 .timings = &innolux_g101ice_l01_timing, 1940 .num_timings = 1, 1941 .bpc = 8, 1942 .size = { 1943 .width = 217, 1944 .height = 135, 1945 }, 1946 .delay = { 1947 .enable = 200, 1948 .disable = 200, 1949 }, 1950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1952 }; 1953 1954 static const struct display_timing innolux_g121i1_l01_timing = { 1955 .pixelclock = { 67450000, 71000000, 74550000 }, 1956 .hactive = { 1280, 1280, 1280 }, 1957 .hfront_porch = { 40, 80, 160 }, 1958 .hback_porch = { 39, 79, 159 }, 1959 .hsync_len = { 1, 1, 1 }, 1960 .vactive = { 800, 800, 800 }, 1961 .vfront_porch = { 5, 11, 100 }, 1962 .vback_porch = { 4, 11, 99 }, 1963 .vsync_len = { 1, 1, 1 }, 1964 }; 1965 1966 static const struct panel_desc innolux_g121i1_l01 = { 1967 .timings = &innolux_g121i1_l01_timing, 1968 .num_timings = 1, 1969 .bpc = 6, 1970 .size = { 1971 .width = 261, 1972 .height = 163, 1973 }, 1974 .delay = { 1975 .enable = 200, 1976 .disable = 20, 1977 }, 1978 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1980 }; 1981 1982 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1983 .clock = 65000, 1984 .hdisplay = 1024, 1985 .hsync_start = 1024 + 0, 1986 .hsync_end = 1024 + 1, 1987 .htotal = 1024 + 0 + 1 + 320, 1988 .vdisplay = 768, 1989 .vsync_start = 768 + 38, 1990 .vsync_end = 768 + 38 + 1, 1991 .vtotal = 768 + 38 + 1 + 0, 1992 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1993 }; 1994 1995 static const struct panel_desc innolux_g121x1_l03 = { 1996 .modes = &innolux_g121x1_l03_mode, 1997 .num_modes = 1, 1998 .bpc = 6, 1999 .size = { 2000 .width = 246, 2001 .height = 185, 2002 }, 2003 .delay = { 2004 .enable = 200, 2005 .unprepare = 200, 2006 .disable = 400, 2007 }, 2008 }; 2009 2010 /* 2011 * Datasheet specifies that at 60 Hz refresh rate: 2012 * - total horizontal time: { 1506, 1592, 1716 } 2013 * - total vertical time: { 788, 800, 868 } 2014 * 2015 * ...but doesn't go into exactly how that should be split into a front 2016 * porch, back porch, or sync length. For now we'll leave a single setting 2017 * here which allows a bit of tweaking of the pixel clock at the expense of 2018 * refresh rate. 2019 */ 2020 static const struct display_timing innolux_n116bge_timing = { 2021 .pixelclock = { 72600000, 76420000, 80240000 }, 2022 .hactive = { 1366, 1366, 1366 }, 2023 .hfront_porch = { 136, 136, 136 }, 2024 .hback_porch = { 60, 60, 60 }, 2025 .hsync_len = { 30, 30, 30 }, 2026 .vactive = { 768, 768, 768 }, 2027 .vfront_porch = { 8, 8, 8 }, 2028 .vback_porch = { 12, 12, 12 }, 2029 .vsync_len = { 12, 12, 12 }, 2030 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2031 }; 2032 2033 static const struct panel_desc innolux_n116bge = { 2034 .timings = &innolux_n116bge_timing, 2035 .num_timings = 1, 2036 .bpc = 6, 2037 .size = { 2038 .width = 256, 2039 .height = 144, 2040 }, 2041 }; 2042 2043 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2044 .clock = 69300, 2045 .hdisplay = 1366, 2046 .hsync_start = 1366 + 16, 2047 .hsync_end = 1366 + 16 + 34, 2048 .htotal = 1366 + 16 + 34 + 50, 2049 .vdisplay = 768, 2050 .vsync_start = 768 + 2, 2051 .vsync_end = 768 + 2 + 6, 2052 .vtotal = 768 + 2 + 6 + 12, 2053 }; 2054 2055 static const struct panel_desc innolux_n156bge_l21 = { 2056 .modes = &innolux_n156bge_l21_mode, 2057 .num_modes = 1, 2058 .bpc = 6, 2059 .size = { 2060 .width = 344, 2061 .height = 193, 2062 }, 2063 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2064 }; 2065 2066 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2067 .clock = 206016, 2068 .hdisplay = 2160, 2069 .hsync_start = 2160 + 48, 2070 .hsync_end = 2160 + 48 + 32, 2071 .htotal = 2160 + 48 + 32 + 80, 2072 .vdisplay = 1440, 2073 .vsync_start = 1440 + 3, 2074 .vsync_end = 1440 + 3 + 10, 2075 .vtotal = 1440 + 3 + 10 + 27, 2076 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2077 }; 2078 2079 static const struct panel_desc innolux_p120zdg_bf1 = { 2080 .modes = &innolux_p120zdg_bf1_mode, 2081 .num_modes = 1, 2082 .bpc = 8, 2083 .size = { 2084 .width = 254, 2085 .height = 169, 2086 }, 2087 .delay = { 2088 .hpd_absent_delay = 200, 2089 .unprepare = 500, 2090 }, 2091 }; 2092 2093 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2094 .clock = 51501, 2095 .hdisplay = 1024, 2096 .hsync_start = 1024 + 128, 2097 .hsync_end = 1024 + 128 + 64, 2098 .htotal = 1024 + 128 + 64 + 128, 2099 .vdisplay = 600, 2100 .vsync_start = 600 + 16, 2101 .vsync_end = 600 + 16 + 4, 2102 .vtotal = 600 + 16 + 4 + 16, 2103 }; 2104 2105 static const struct panel_desc innolux_zj070na_01p = { 2106 .modes = &innolux_zj070na_01p_mode, 2107 .num_modes = 1, 2108 .bpc = 6, 2109 .size = { 2110 .width = 154, 2111 .height = 90, 2112 }, 2113 }; 2114 2115 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2116 .clock = 138778, 2117 .hdisplay = 1920, 2118 .hsync_start = 1920 + 24, 2119 .hsync_end = 1920 + 24 + 48, 2120 .htotal = 1920 + 24 + 48 + 88, 2121 .vdisplay = 1080, 2122 .vsync_start = 1080 + 3, 2123 .vsync_end = 1080 + 3 + 12, 2124 .vtotal = 1080 + 3 + 12 + 17, 2125 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2126 }; 2127 2128 static const struct panel_desc ivo_m133nwf4_r0 = { 2129 .modes = &ivo_m133nwf4_r0_mode, 2130 .num_modes = 1, 2131 .bpc = 8, 2132 .size = { 2133 .width = 294, 2134 .height = 165, 2135 }, 2136 .delay = { 2137 .hpd_absent_delay = 200, 2138 .unprepare = 500, 2139 }, 2140 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2141 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2142 .connector_type = DRM_MODE_CONNECTOR_eDP, 2143 }; 2144 2145 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2146 .pixelclock = { 5580000, 5850000, 6200000 }, 2147 .hactive = { 320, 320, 320 }, 2148 .hfront_porch = { 30, 30, 30 }, 2149 .hback_porch = { 30, 30, 30 }, 2150 .hsync_len = { 1, 5, 17 }, 2151 .vactive = { 240, 240, 240 }, 2152 .vfront_porch = { 6, 6, 6 }, 2153 .vback_porch = { 5, 5, 5 }, 2154 .vsync_len = { 1, 2, 11 }, 2155 .flags = DISPLAY_FLAGS_DE_HIGH, 2156 }; 2157 2158 static const struct panel_desc koe_tx14d24vm1bpa = { 2159 .timings = &koe_tx14d24vm1bpa_timing, 2160 .num_timings = 1, 2161 .bpc = 6, 2162 .size = { 2163 .width = 115, 2164 .height = 86, 2165 }, 2166 }; 2167 2168 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2169 .pixelclock = { 151820000, 156720000, 159780000 }, 2170 .hactive = { 1920, 1920, 1920 }, 2171 .hfront_porch = { 105, 130, 142 }, 2172 .hback_porch = { 45, 70, 82 }, 2173 .hsync_len = { 30, 30, 30 }, 2174 .vactive = { 1200, 1200, 1200}, 2175 .vfront_porch = { 3, 5, 10 }, 2176 .vback_porch = { 2, 5, 10 }, 2177 .vsync_len = { 5, 5, 5 }, 2178 }; 2179 2180 static const struct panel_desc koe_tx26d202vm0bwa = { 2181 .timings = &koe_tx26d202vm0bwa_timing, 2182 .num_timings = 1, 2183 .bpc = 8, 2184 .size = { 2185 .width = 217, 2186 .height = 136, 2187 }, 2188 .delay = { 2189 .prepare = 1000, 2190 .enable = 1000, 2191 .unprepare = 1000, 2192 .disable = 1000, 2193 }, 2194 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2195 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2196 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2197 }; 2198 2199 static const struct display_timing koe_tx31d200vm0baa_timing = { 2200 .pixelclock = { 39600000, 43200000, 48000000 }, 2201 .hactive = { 1280, 1280, 1280 }, 2202 .hfront_porch = { 16, 36, 56 }, 2203 .hback_porch = { 16, 36, 56 }, 2204 .hsync_len = { 8, 8, 8 }, 2205 .vactive = { 480, 480, 480 }, 2206 .vfront_porch = { 6, 21, 33 }, 2207 .vback_porch = { 6, 21, 33 }, 2208 .vsync_len = { 8, 8, 8 }, 2209 .flags = DISPLAY_FLAGS_DE_HIGH, 2210 }; 2211 2212 static const struct panel_desc koe_tx31d200vm0baa = { 2213 .timings = &koe_tx31d200vm0baa_timing, 2214 .num_timings = 1, 2215 .bpc = 6, 2216 .size = { 2217 .width = 292, 2218 .height = 109, 2219 }, 2220 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2221 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2222 }; 2223 2224 static const struct display_timing kyo_tcg121xglp_timing = { 2225 .pixelclock = { 52000000, 65000000, 71000000 }, 2226 .hactive = { 1024, 1024, 1024 }, 2227 .hfront_porch = { 2, 2, 2 }, 2228 .hback_porch = { 2, 2, 2 }, 2229 .hsync_len = { 86, 124, 244 }, 2230 .vactive = { 768, 768, 768 }, 2231 .vfront_porch = { 2, 2, 2 }, 2232 .vback_porch = { 2, 2, 2 }, 2233 .vsync_len = { 6, 34, 73 }, 2234 .flags = DISPLAY_FLAGS_DE_HIGH, 2235 }; 2236 2237 static const struct panel_desc kyo_tcg121xglp = { 2238 .timings = &kyo_tcg121xglp_timing, 2239 .num_timings = 1, 2240 .bpc = 8, 2241 .size = { 2242 .width = 246, 2243 .height = 184, 2244 }, 2245 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2246 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2247 }; 2248 2249 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2250 .clock = 7000, 2251 .hdisplay = 320, 2252 .hsync_start = 320 + 20, 2253 .hsync_end = 320 + 20 + 30, 2254 .htotal = 320 + 20 + 30 + 38, 2255 .vdisplay = 240, 2256 .vsync_start = 240 + 4, 2257 .vsync_end = 240 + 4 + 3, 2258 .vtotal = 240 + 4 + 3 + 15, 2259 }; 2260 2261 static const struct panel_desc lemaker_bl035_rgb_002 = { 2262 .modes = &lemaker_bl035_rgb_002_mode, 2263 .num_modes = 1, 2264 .size = { 2265 .width = 70, 2266 .height = 52, 2267 }, 2268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2269 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2270 }; 2271 2272 static const struct drm_display_mode lg_lb070wv8_mode = { 2273 .clock = 33246, 2274 .hdisplay = 800, 2275 .hsync_start = 800 + 88, 2276 .hsync_end = 800 + 88 + 80, 2277 .htotal = 800 + 88 + 80 + 88, 2278 .vdisplay = 480, 2279 .vsync_start = 480 + 10, 2280 .vsync_end = 480 + 10 + 25, 2281 .vtotal = 480 + 10 + 25 + 10, 2282 }; 2283 2284 static const struct panel_desc lg_lb070wv8 = { 2285 .modes = &lg_lb070wv8_mode, 2286 .num_modes = 1, 2287 .bpc = 16, 2288 .size = { 2289 .width = 151, 2290 .height = 91, 2291 }, 2292 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2293 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2294 }; 2295 2296 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2297 .clock = 200000, 2298 .hdisplay = 1536, 2299 .hsync_start = 1536 + 12, 2300 .hsync_end = 1536 + 12 + 16, 2301 .htotal = 1536 + 12 + 16 + 48, 2302 .vdisplay = 2048, 2303 .vsync_start = 2048 + 8, 2304 .vsync_end = 2048 + 8 + 4, 2305 .vtotal = 2048 + 8 + 4 + 8, 2306 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2307 }; 2308 2309 static const struct panel_desc lg_lp079qx1_sp0v = { 2310 .modes = &lg_lp079qx1_sp0v_mode, 2311 .num_modes = 1, 2312 .size = { 2313 .width = 129, 2314 .height = 171, 2315 }, 2316 }; 2317 2318 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2319 .clock = 205210, 2320 .hdisplay = 2048, 2321 .hsync_start = 2048 + 150, 2322 .hsync_end = 2048 + 150 + 5, 2323 .htotal = 2048 + 150 + 5 + 5, 2324 .vdisplay = 1536, 2325 .vsync_start = 1536 + 3, 2326 .vsync_end = 1536 + 3 + 1, 2327 .vtotal = 1536 + 3 + 1 + 9, 2328 }; 2329 2330 static const struct panel_desc lg_lp097qx1_spa1 = { 2331 .modes = &lg_lp097qx1_spa1_mode, 2332 .num_modes = 1, 2333 .size = { 2334 .width = 208, 2335 .height = 147, 2336 }, 2337 }; 2338 2339 static const struct drm_display_mode lg_lp120up1_mode = { 2340 .clock = 162300, 2341 .hdisplay = 1920, 2342 .hsync_start = 1920 + 40, 2343 .hsync_end = 1920 + 40 + 40, 2344 .htotal = 1920 + 40 + 40+ 80, 2345 .vdisplay = 1280, 2346 .vsync_start = 1280 + 4, 2347 .vsync_end = 1280 + 4 + 4, 2348 .vtotal = 1280 + 4 + 4 + 12, 2349 }; 2350 2351 static const struct panel_desc lg_lp120up1 = { 2352 .modes = &lg_lp120up1_mode, 2353 .num_modes = 1, 2354 .bpc = 8, 2355 .size = { 2356 .width = 267, 2357 .height = 183, 2358 }, 2359 .connector_type = DRM_MODE_CONNECTOR_eDP, 2360 }; 2361 2362 static const struct drm_display_mode lg_lp129qe_mode = { 2363 .clock = 285250, 2364 .hdisplay = 2560, 2365 .hsync_start = 2560 + 48, 2366 .hsync_end = 2560 + 48 + 32, 2367 .htotal = 2560 + 48 + 32 + 80, 2368 .vdisplay = 1700, 2369 .vsync_start = 1700 + 3, 2370 .vsync_end = 1700 + 3 + 10, 2371 .vtotal = 1700 + 3 + 10 + 36, 2372 }; 2373 2374 static const struct panel_desc lg_lp129qe = { 2375 .modes = &lg_lp129qe_mode, 2376 .num_modes = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 272, 2380 .height = 181, 2381 }, 2382 }; 2383 2384 static const struct display_timing logictechno_lt161010_2nh_timing = { 2385 .pixelclock = { 26400000, 33300000, 46800000 }, 2386 .hactive = { 800, 800, 800 }, 2387 .hfront_porch = { 16, 210, 354 }, 2388 .hback_porch = { 46, 46, 46 }, 2389 .hsync_len = { 1, 20, 40 }, 2390 .vactive = { 480, 480, 480 }, 2391 .vfront_porch = { 7, 22, 147 }, 2392 .vback_porch = { 23, 23, 23 }, 2393 .vsync_len = { 1, 10, 20 }, 2394 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2395 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2396 DISPLAY_FLAGS_SYNC_POSEDGE, 2397 }; 2398 2399 static const struct panel_desc logictechno_lt161010_2nh = { 2400 .timings = &logictechno_lt161010_2nh_timing, 2401 .num_timings = 1, 2402 .size = { 2403 .width = 154, 2404 .height = 86, 2405 }, 2406 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2407 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2408 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2409 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2410 .connector_type = DRM_MODE_CONNECTOR_DPI, 2411 }; 2412 2413 static const struct display_timing logictechno_lt170410_2whc_timing = { 2414 .pixelclock = { 68900000, 71100000, 73400000 }, 2415 .hactive = { 1280, 1280, 1280 }, 2416 .hfront_porch = { 23, 60, 71 }, 2417 .hback_porch = { 23, 60, 71 }, 2418 .hsync_len = { 15, 40, 47 }, 2419 .vactive = { 800, 800, 800 }, 2420 .vfront_porch = { 5, 7, 10 }, 2421 .vback_porch = { 5, 7, 10 }, 2422 .vsync_len = { 6, 9, 12 }, 2423 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2424 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2425 DISPLAY_FLAGS_SYNC_POSEDGE, 2426 }; 2427 2428 static const struct panel_desc logictechno_lt170410_2whc = { 2429 .timings = &logictechno_lt170410_2whc_timing, 2430 .num_timings = 1, 2431 .size = { 2432 .width = 217, 2433 .height = 136, 2434 }, 2435 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2436 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2437 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2438 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2439 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2440 }; 2441 2442 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2443 .clock = 30400, 2444 .hdisplay = 800, 2445 .hsync_start = 800 + 0, 2446 .hsync_end = 800 + 1, 2447 .htotal = 800 + 0 + 1 + 160, 2448 .vdisplay = 480, 2449 .vsync_start = 480 + 0, 2450 .vsync_end = 480 + 48 + 1, 2451 .vtotal = 480 + 48 + 1 + 0, 2452 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2453 }; 2454 2455 static const struct drm_display_mode logicpd_type_28_mode = { 2456 .clock = 9107, 2457 .hdisplay = 480, 2458 .hsync_start = 480 + 3, 2459 .hsync_end = 480 + 3 + 42, 2460 .htotal = 480 + 3 + 42 + 2, 2461 2462 .vdisplay = 272, 2463 .vsync_start = 272 + 2, 2464 .vsync_end = 272 + 2 + 11, 2465 .vtotal = 272 + 2 + 11 + 3, 2466 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2467 }; 2468 2469 static const struct panel_desc logicpd_type_28 = { 2470 .modes = &logicpd_type_28_mode, 2471 .num_modes = 1, 2472 .bpc = 8, 2473 .size = { 2474 .width = 105, 2475 .height = 67, 2476 }, 2477 .delay = { 2478 .prepare = 200, 2479 .enable = 200, 2480 .unprepare = 200, 2481 .disable = 200, 2482 }, 2483 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2484 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2485 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2486 }; 2487 2488 static const struct panel_desc mitsubishi_aa070mc01 = { 2489 .modes = &mitsubishi_aa070mc01_mode, 2490 .num_modes = 1, 2491 .bpc = 8, 2492 .size = { 2493 .width = 152, 2494 .height = 91, 2495 }, 2496 2497 .delay = { 2498 .enable = 200, 2499 .unprepare = 200, 2500 .disable = 400, 2501 }, 2502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2503 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2504 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2505 }; 2506 2507 static const struct display_timing nec_nl12880bc20_05_timing = { 2508 .pixelclock = { 67000000, 71000000, 75000000 }, 2509 .hactive = { 1280, 1280, 1280 }, 2510 .hfront_porch = { 2, 30, 30 }, 2511 .hback_porch = { 6, 100, 100 }, 2512 .hsync_len = { 2, 30, 30 }, 2513 .vactive = { 800, 800, 800 }, 2514 .vfront_porch = { 5, 5, 5 }, 2515 .vback_porch = { 11, 11, 11 }, 2516 .vsync_len = { 7, 7, 7 }, 2517 }; 2518 2519 static const struct panel_desc nec_nl12880bc20_05 = { 2520 .timings = &nec_nl12880bc20_05_timing, 2521 .num_timings = 1, 2522 .bpc = 8, 2523 .size = { 2524 .width = 261, 2525 .height = 163, 2526 }, 2527 .delay = { 2528 .enable = 50, 2529 .disable = 50, 2530 }, 2531 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2532 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2533 }; 2534 2535 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2536 .clock = 10870, 2537 .hdisplay = 480, 2538 .hsync_start = 480 + 2, 2539 .hsync_end = 480 + 2 + 41, 2540 .htotal = 480 + 2 + 41 + 2, 2541 .vdisplay = 272, 2542 .vsync_start = 272 + 2, 2543 .vsync_end = 272 + 2 + 4, 2544 .vtotal = 272 + 2 + 4 + 2, 2545 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2546 }; 2547 2548 static const struct panel_desc nec_nl4827hc19_05b = { 2549 .modes = &nec_nl4827hc19_05b_mode, 2550 .num_modes = 1, 2551 .bpc = 8, 2552 .size = { 2553 .width = 95, 2554 .height = 54, 2555 }, 2556 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2557 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2558 }; 2559 2560 static const struct drm_display_mode netron_dy_e231732_mode = { 2561 .clock = 66000, 2562 .hdisplay = 1024, 2563 .hsync_start = 1024 + 160, 2564 .hsync_end = 1024 + 160 + 70, 2565 .htotal = 1024 + 160 + 70 + 90, 2566 .vdisplay = 600, 2567 .vsync_start = 600 + 127, 2568 .vsync_end = 600 + 127 + 20, 2569 .vtotal = 600 + 127 + 20 + 3, 2570 }; 2571 2572 static const struct panel_desc netron_dy_e231732 = { 2573 .modes = &netron_dy_e231732_mode, 2574 .num_modes = 1, 2575 .size = { 2576 .width = 154, 2577 .height = 87, 2578 }, 2579 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2580 }; 2581 2582 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2583 { 2584 .clock = 138500, 2585 .hdisplay = 1920, 2586 .hsync_start = 1920 + 48, 2587 .hsync_end = 1920 + 48 + 32, 2588 .htotal = 1920 + 48 + 32 + 80, 2589 .vdisplay = 1080, 2590 .vsync_start = 1080 + 3, 2591 .vsync_end = 1080 + 3 + 5, 2592 .vtotal = 1080 + 3 + 5 + 23, 2593 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2594 }, { 2595 .clock = 110920, 2596 .hdisplay = 1920, 2597 .hsync_start = 1920 + 48, 2598 .hsync_end = 1920 + 48 + 32, 2599 .htotal = 1920 + 48 + 32 + 80, 2600 .vdisplay = 1080, 2601 .vsync_start = 1080 + 3, 2602 .vsync_end = 1080 + 3 + 5, 2603 .vtotal = 1080 + 3 + 5 + 23, 2604 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2605 } 2606 }; 2607 2608 static const struct panel_desc neweast_wjfh116008a = { 2609 .modes = neweast_wjfh116008a_modes, 2610 .num_modes = 2, 2611 .bpc = 6, 2612 .size = { 2613 .width = 260, 2614 .height = 150, 2615 }, 2616 .delay = { 2617 .prepare = 110, 2618 .enable = 20, 2619 .unprepare = 500, 2620 }, 2621 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2622 .connector_type = DRM_MODE_CONNECTOR_eDP, 2623 }; 2624 2625 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2626 .clock = 9000, 2627 .hdisplay = 480, 2628 .hsync_start = 480 + 2, 2629 .hsync_end = 480 + 2 + 41, 2630 .htotal = 480 + 2 + 41 + 2, 2631 .vdisplay = 272, 2632 .vsync_start = 272 + 2, 2633 .vsync_end = 272 + 2 + 10, 2634 .vtotal = 272 + 2 + 10 + 2, 2635 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2636 }; 2637 2638 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2639 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2640 .num_modes = 1, 2641 .bpc = 8, 2642 .size = { 2643 .width = 95, 2644 .height = 54, 2645 }, 2646 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2647 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2648 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2649 }; 2650 2651 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2652 .pixelclock = { 130000000, 148350000, 163000000 }, 2653 .hactive = { 1920, 1920, 1920 }, 2654 .hfront_porch = { 80, 100, 100 }, 2655 .hback_porch = { 100, 120, 120 }, 2656 .hsync_len = { 50, 60, 60 }, 2657 .vactive = { 1080, 1080, 1080 }, 2658 .vfront_porch = { 12, 30, 30 }, 2659 .vback_porch = { 4, 10, 10 }, 2660 .vsync_len = { 4, 5, 5 }, 2661 }; 2662 2663 static const struct panel_desc nlt_nl192108ac18_02d = { 2664 .timings = &nlt_nl192108ac18_02d_timing, 2665 .num_timings = 1, 2666 .bpc = 8, 2667 .size = { 2668 .width = 344, 2669 .height = 194, 2670 }, 2671 .delay = { 2672 .unprepare = 500, 2673 }, 2674 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2675 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2676 }; 2677 2678 static const struct drm_display_mode nvd_9128_mode = { 2679 .clock = 29500, 2680 .hdisplay = 800, 2681 .hsync_start = 800 + 130, 2682 .hsync_end = 800 + 130 + 98, 2683 .htotal = 800 + 0 + 130 + 98, 2684 .vdisplay = 480, 2685 .vsync_start = 480 + 10, 2686 .vsync_end = 480 + 10 + 50, 2687 .vtotal = 480 + 0 + 10 + 50, 2688 }; 2689 2690 static const struct panel_desc nvd_9128 = { 2691 .modes = &nvd_9128_mode, 2692 .num_modes = 1, 2693 .bpc = 8, 2694 .size = { 2695 .width = 156, 2696 .height = 88, 2697 }, 2698 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2699 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2700 }; 2701 2702 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2703 .pixelclock = { 30000000, 30000000, 40000000 }, 2704 .hactive = { 800, 800, 800 }, 2705 .hfront_porch = { 40, 40, 40 }, 2706 .hback_porch = { 40, 40, 40 }, 2707 .hsync_len = { 1, 48, 48 }, 2708 .vactive = { 480, 480, 480 }, 2709 .vfront_porch = { 13, 13, 13 }, 2710 .vback_porch = { 29, 29, 29 }, 2711 .vsync_len = { 3, 3, 3 }, 2712 .flags = DISPLAY_FLAGS_DE_HIGH, 2713 }; 2714 2715 static const struct panel_desc okaya_rs800480t_7x0gp = { 2716 .timings = &okaya_rs800480t_7x0gp_timing, 2717 .num_timings = 1, 2718 .bpc = 6, 2719 .size = { 2720 .width = 154, 2721 .height = 87, 2722 }, 2723 .delay = { 2724 .prepare = 41, 2725 .enable = 50, 2726 .unprepare = 41, 2727 .disable = 50, 2728 }, 2729 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2730 }; 2731 2732 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2733 .clock = 9000, 2734 .hdisplay = 480, 2735 .hsync_start = 480 + 5, 2736 .hsync_end = 480 + 5 + 30, 2737 .htotal = 480 + 5 + 30 + 10, 2738 .vdisplay = 272, 2739 .vsync_start = 272 + 8, 2740 .vsync_end = 272 + 8 + 5, 2741 .vtotal = 272 + 8 + 5 + 3, 2742 }; 2743 2744 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2745 .modes = &olimex_lcd_olinuxino_43ts_mode, 2746 .num_modes = 1, 2747 .size = { 2748 .width = 95, 2749 .height = 54, 2750 }, 2751 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2752 }; 2753 2754 /* 2755 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2756 * pixel clocks, but this is the timing that was being used in the Adafruit 2757 * installation instructions. 2758 */ 2759 static const struct drm_display_mode ontat_yx700wv03_mode = { 2760 .clock = 29500, 2761 .hdisplay = 800, 2762 .hsync_start = 824, 2763 .hsync_end = 896, 2764 .htotal = 992, 2765 .vdisplay = 480, 2766 .vsync_start = 483, 2767 .vsync_end = 493, 2768 .vtotal = 500, 2769 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2770 }; 2771 2772 /* 2773 * Specification at: 2774 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2775 */ 2776 static const struct panel_desc ontat_yx700wv03 = { 2777 .modes = &ontat_yx700wv03_mode, 2778 .num_modes = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 154, 2782 .height = 83, 2783 }, 2784 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2785 }; 2786 2787 static const struct drm_display_mode ortustech_com37h3m_mode = { 2788 .clock = 22230, 2789 .hdisplay = 480, 2790 .hsync_start = 480 + 40, 2791 .hsync_end = 480 + 40 + 10, 2792 .htotal = 480 + 40 + 10 + 40, 2793 .vdisplay = 640, 2794 .vsync_start = 640 + 4, 2795 .vsync_end = 640 + 4 + 2, 2796 .vtotal = 640 + 4 + 2 + 4, 2797 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2798 }; 2799 2800 static const struct panel_desc ortustech_com37h3m = { 2801 .modes = &ortustech_com37h3m_mode, 2802 .num_modes = 1, 2803 .bpc = 8, 2804 .size = { 2805 .width = 56, /* 56.16mm */ 2806 .height = 75, /* 74.88mm */ 2807 }, 2808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2809 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2810 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2811 }; 2812 2813 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2814 .clock = 25000, 2815 .hdisplay = 480, 2816 .hsync_start = 480 + 10, 2817 .hsync_end = 480 + 10 + 10, 2818 .htotal = 480 + 10 + 10 + 15, 2819 .vdisplay = 800, 2820 .vsync_start = 800 + 3, 2821 .vsync_end = 800 + 3 + 3, 2822 .vtotal = 800 + 3 + 3 + 3, 2823 }; 2824 2825 static const struct panel_desc ortustech_com43h4m85ulc = { 2826 .modes = &ortustech_com43h4m85ulc_mode, 2827 .num_modes = 1, 2828 .bpc = 8, 2829 .size = { 2830 .width = 56, 2831 .height = 93, 2832 }, 2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2834 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2835 .connector_type = DRM_MODE_CONNECTOR_DPI, 2836 }; 2837 2838 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2839 .clock = 33000, 2840 .hdisplay = 800, 2841 .hsync_start = 800 + 210, 2842 .hsync_end = 800 + 210 + 30, 2843 .htotal = 800 + 210 + 30 + 16, 2844 .vdisplay = 480, 2845 .vsync_start = 480 + 22, 2846 .vsync_end = 480 + 22 + 13, 2847 .vtotal = 480 + 22 + 13 + 10, 2848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2849 }; 2850 2851 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2852 .modes = &osddisplays_osd070t1718_19ts_mode, 2853 .num_modes = 1, 2854 .bpc = 8, 2855 .size = { 2856 .width = 152, 2857 .height = 91, 2858 }, 2859 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2860 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2861 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2862 .connector_type = DRM_MODE_CONNECTOR_DPI, 2863 }; 2864 2865 static const struct drm_display_mode pda_91_00156_a0_mode = { 2866 .clock = 33300, 2867 .hdisplay = 800, 2868 .hsync_start = 800 + 1, 2869 .hsync_end = 800 + 1 + 64, 2870 .htotal = 800 + 1 + 64 + 64, 2871 .vdisplay = 480, 2872 .vsync_start = 480 + 1, 2873 .vsync_end = 480 + 1 + 23, 2874 .vtotal = 480 + 1 + 23 + 22, 2875 }; 2876 2877 static const struct panel_desc pda_91_00156_a0 = { 2878 .modes = &pda_91_00156_a0_mode, 2879 .num_modes = 1, 2880 .size = { 2881 .width = 152, 2882 .height = 91, 2883 }, 2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2885 }; 2886 2887 2888 static const struct drm_display_mode qd43003c0_40_mode = { 2889 .clock = 9000, 2890 .hdisplay = 480, 2891 .hsync_start = 480 + 8, 2892 .hsync_end = 480 + 8 + 4, 2893 .htotal = 480 + 8 + 4 + 39, 2894 .vdisplay = 272, 2895 .vsync_start = 272 + 4, 2896 .vsync_end = 272 + 4 + 10, 2897 .vtotal = 272 + 4 + 10 + 2, 2898 }; 2899 2900 static const struct panel_desc qd43003c0_40 = { 2901 .modes = &qd43003c0_40_mode, 2902 .num_modes = 1, 2903 .bpc = 8, 2904 .size = { 2905 .width = 95, 2906 .height = 53, 2907 }, 2908 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2909 }; 2910 2911 static const struct display_timing rocktech_rk070er9427_timing = { 2912 .pixelclock = { 26400000, 33300000, 46800000 }, 2913 .hactive = { 800, 800, 800 }, 2914 .hfront_porch = { 16, 210, 354 }, 2915 .hback_porch = { 46, 46, 46 }, 2916 .hsync_len = { 1, 1, 1 }, 2917 .vactive = { 480, 480, 480 }, 2918 .vfront_porch = { 7, 22, 147 }, 2919 .vback_porch = { 23, 23, 23 }, 2920 .vsync_len = { 1, 1, 1 }, 2921 .flags = DISPLAY_FLAGS_DE_HIGH, 2922 }; 2923 2924 static const struct panel_desc rocktech_rk070er9427 = { 2925 .timings = &rocktech_rk070er9427_timing, 2926 .num_timings = 1, 2927 .bpc = 6, 2928 .size = { 2929 .width = 154, 2930 .height = 86, 2931 }, 2932 .delay = { 2933 .prepare = 41, 2934 .enable = 50, 2935 .unprepare = 41, 2936 .disable = 50, 2937 }, 2938 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2939 }; 2940 2941 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2942 .clock = 71100, 2943 .hdisplay = 1280, 2944 .hsync_start = 1280 + 48, 2945 .hsync_end = 1280 + 48 + 32, 2946 .htotal = 1280 + 48 + 32 + 80, 2947 .vdisplay = 800, 2948 .vsync_start = 800 + 2, 2949 .vsync_end = 800 + 2 + 5, 2950 .vtotal = 800 + 2 + 5 + 16, 2951 }; 2952 2953 static const struct panel_desc rocktech_rk101ii01d_ct = { 2954 .modes = &rocktech_rk101ii01d_ct_mode, 2955 .num_modes = 1, 2956 .size = { 2957 .width = 217, 2958 .height = 136, 2959 }, 2960 .delay = { 2961 .prepare = 50, 2962 .disable = 50, 2963 }, 2964 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2965 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2966 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2967 }; 2968 2969 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2970 .clock = 271560, 2971 .hdisplay = 2560, 2972 .hsync_start = 2560 + 48, 2973 .hsync_end = 2560 + 48 + 32, 2974 .htotal = 2560 + 48 + 32 + 80, 2975 .vdisplay = 1600, 2976 .vsync_start = 1600 + 2, 2977 .vsync_end = 1600 + 2 + 5, 2978 .vtotal = 1600 + 2 + 5 + 57, 2979 }; 2980 2981 static const struct panel_desc samsung_lsn122dl01_c01 = { 2982 .modes = &samsung_lsn122dl01_c01_mode, 2983 .num_modes = 1, 2984 .size = { 2985 .width = 263, 2986 .height = 164, 2987 }, 2988 }; 2989 2990 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2991 .clock = 54030, 2992 .hdisplay = 1024, 2993 .hsync_start = 1024 + 24, 2994 .hsync_end = 1024 + 24 + 136, 2995 .htotal = 1024 + 24 + 136 + 160, 2996 .vdisplay = 600, 2997 .vsync_start = 600 + 3, 2998 .vsync_end = 600 + 3 + 6, 2999 .vtotal = 600 + 3 + 6 + 61, 3000 }; 3001 3002 static const struct panel_desc samsung_ltn101nt05 = { 3003 .modes = &samsung_ltn101nt05_mode, 3004 .num_modes = 1, 3005 .bpc = 6, 3006 .size = { 3007 .width = 223, 3008 .height = 125, 3009 }, 3010 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3011 }; 3012 3013 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3014 .clock = 76300, 3015 .hdisplay = 1366, 3016 .hsync_start = 1366 + 64, 3017 .hsync_end = 1366 + 64 + 48, 3018 .htotal = 1366 + 64 + 48 + 128, 3019 .vdisplay = 768, 3020 .vsync_start = 768 + 2, 3021 .vsync_end = 768 + 2 + 5, 3022 .vtotal = 768 + 2 + 5 + 17, 3023 }; 3024 3025 static const struct panel_desc samsung_ltn140at29_301 = { 3026 .modes = &samsung_ltn140at29_301_mode, 3027 .num_modes = 1, 3028 .bpc = 6, 3029 .size = { 3030 .width = 320, 3031 .height = 187, 3032 }, 3033 }; 3034 3035 static const struct display_timing satoz_sat050at40h12r2_timing = { 3036 .pixelclock = {33300000, 33300000, 50000000}, 3037 .hactive = {800, 800, 800}, 3038 .hfront_porch = {16, 210, 354}, 3039 .hback_porch = {46, 46, 46}, 3040 .hsync_len = {1, 1, 40}, 3041 .vactive = {480, 480, 480}, 3042 .vfront_porch = {7, 22, 147}, 3043 .vback_porch = {23, 23, 23}, 3044 .vsync_len = {1, 1, 20}, 3045 }; 3046 3047 static const struct panel_desc satoz_sat050at40h12r2 = { 3048 .timings = &satoz_sat050at40h12r2_timing, 3049 .num_timings = 1, 3050 .bpc = 8, 3051 .size = { 3052 .width = 108, 3053 .height = 65, 3054 }, 3055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3057 }; 3058 3059 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3060 .clock = 168480, 3061 .hdisplay = 1920, 3062 .hsync_start = 1920 + 48, 3063 .hsync_end = 1920 + 48 + 32, 3064 .htotal = 1920 + 48 + 32 + 80, 3065 .vdisplay = 1280, 3066 .vsync_start = 1280 + 3, 3067 .vsync_end = 1280 + 3 + 10, 3068 .vtotal = 1280 + 3 + 10 + 57, 3069 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3070 }; 3071 3072 static const struct panel_desc sharp_ld_d5116z01b = { 3073 .modes = &sharp_ld_d5116z01b_mode, 3074 .num_modes = 1, 3075 .bpc = 8, 3076 .size = { 3077 .width = 260, 3078 .height = 120, 3079 }, 3080 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3081 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3082 }; 3083 3084 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3085 .clock = 33260, 3086 .hdisplay = 800, 3087 .hsync_start = 800 + 64, 3088 .hsync_end = 800 + 64 + 128, 3089 .htotal = 800 + 64 + 128 + 64, 3090 .vdisplay = 480, 3091 .vsync_start = 480 + 8, 3092 .vsync_end = 480 + 8 + 2, 3093 .vtotal = 480 + 8 + 2 + 35, 3094 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3095 }; 3096 3097 static const struct panel_desc sharp_lq070y3dg3b = { 3098 .modes = &sharp_lq070y3dg3b_mode, 3099 .num_modes = 1, 3100 .bpc = 8, 3101 .size = { 3102 .width = 152, /* 152.4mm */ 3103 .height = 91, /* 91.4mm */ 3104 }, 3105 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3106 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 3107 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3108 }; 3109 3110 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3111 .clock = 5500, 3112 .hdisplay = 240, 3113 .hsync_start = 240 + 16, 3114 .hsync_end = 240 + 16 + 7, 3115 .htotal = 240 + 16 + 7 + 5, 3116 .vdisplay = 320, 3117 .vsync_start = 320 + 9, 3118 .vsync_end = 320 + 9 + 1, 3119 .vtotal = 320 + 9 + 1 + 7, 3120 }; 3121 3122 static const struct panel_desc sharp_lq035q7db03 = { 3123 .modes = &sharp_lq035q7db03_mode, 3124 .num_modes = 1, 3125 .bpc = 6, 3126 .size = { 3127 .width = 54, 3128 .height = 72, 3129 }, 3130 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3131 }; 3132 3133 static const struct display_timing sharp_lq101k1ly04_timing = { 3134 .pixelclock = { 60000000, 65000000, 80000000 }, 3135 .hactive = { 1280, 1280, 1280 }, 3136 .hfront_porch = { 20, 20, 20 }, 3137 .hback_porch = { 20, 20, 20 }, 3138 .hsync_len = { 10, 10, 10 }, 3139 .vactive = { 800, 800, 800 }, 3140 .vfront_porch = { 4, 4, 4 }, 3141 .vback_porch = { 4, 4, 4 }, 3142 .vsync_len = { 4, 4, 4 }, 3143 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3144 }; 3145 3146 static const struct panel_desc sharp_lq101k1ly04 = { 3147 .timings = &sharp_lq101k1ly04_timing, 3148 .num_timings = 1, 3149 .bpc = 8, 3150 .size = { 3151 .width = 217, 3152 .height = 136, 3153 }, 3154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3155 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3156 }; 3157 3158 static const struct display_timing sharp_lq123p1jx31_timing = { 3159 .pixelclock = { 252750000, 252750000, 266604720 }, 3160 .hactive = { 2400, 2400, 2400 }, 3161 .hfront_porch = { 48, 48, 48 }, 3162 .hback_porch = { 80, 80, 84 }, 3163 .hsync_len = { 32, 32, 32 }, 3164 .vactive = { 1600, 1600, 1600 }, 3165 .vfront_porch = { 3, 3, 3 }, 3166 .vback_porch = { 33, 33, 120 }, 3167 .vsync_len = { 10, 10, 10 }, 3168 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3169 }; 3170 3171 static const struct panel_desc sharp_lq123p1jx31 = { 3172 .timings = &sharp_lq123p1jx31_timing, 3173 .num_timings = 1, 3174 .bpc = 8, 3175 .size = { 3176 .width = 259, 3177 .height = 173, 3178 }, 3179 .delay = { 3180 .prepare = 110, 3181 .enable = 50, 3182 .unprepare = 550, 3183 }, 3184 }; 3185 3186 static const struct display_timing sharp_ls020b1dd01d_timing = { 3187 .pixelclock = { 2000000, 4200000, 5000000 }, 3188 .hactive = { 240, 240, 240 }, 3189 .hfront_porch = { 66, 66, 66 }, 3190 .hback_porch = { 1, 1, 1 }, 3191 .hsync_len = { 1, 1, 1 }, 3192 .vactive = { 160, 160, 160 }, 3193 .vfront_porch = { 52, 52, 52 }, 3194 .vback_porch = { 6, 6, 6 }, 3195 .vsync_len = { 10, 10, 10 }, 3196 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3197 }; 3198 3199 static const struct panel_desc sharp_ls020b1dd01d = { 3200 .timings = &sharp_ls020b1dd01d_timing, 3201 .num_timings = 1, 3202 .bpc = 6, 3203 .size = { 3204 .width = 42, 3205 .height = 28, 3206 }, 3207 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3208 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3209 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3210 | DRM_BUS_FLAG_SHARP_SIGNALS, 3211 }; 3212 3213 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3214 .clock = 33300, 3215 .hdisplay = 800, 3216 .hsync_start = 800 + 1, 3217 .hsync_end = 800 + 1 + 64, 3218 .htotal = 800 + 1 + 64 + 64, 3219 .vdisplay = 480, 3220 .vsync_start = 480 + 1, 3221 .vsync_end = 480 + 1 + 23, 3222 .vtotal = 480 + 1 + 23 + 22, 3223 }; 3224 3225 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3226 .modes = &shelly_sca07010_bfn_lnn_mode, 3227 .num_modes = 1, 3228 .size = { 3229 .width = 152, 3230 .height = 91, 3231 }, 3232 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3233 }; 3234 3235 static const struct drm_display_mode starry_kr070pe2t_mode = { 3236 .clock = 33000, 3237 .hdisplay = 800, 3238 .hsync_start = 800 + 209, 3239 .hsync_end = 800 + 209 + 1, 3240 .htotal = 800 + 209 + 1 + 45, 3241 .vdisplay = 480, 3242 .vsync_start = 480 + 22, 3243 .vsync_end = 480 + 22 + 1, 3244 .vtotal = 480 + 22 + 1 + 22, 3245 }; 3246 3247 static const struct panel_desc starry_kr070pe2t = { 3248 .modes = &starry_kr070pe2t_mode, 3249 .num_modes = 1, 3250 .bpc = 8, 3251 .size = { 3252 .width = 152, 3253 .height = 86, 3254 }, 3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3256 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3257 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3258 }; 3259 3260 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3261 .clock = 147000, 3262 .hdisplay = 1920, 3263 .hsync_start = 1920 + 16, 3264 .hsync_end = 1920 + 16 + 16, 3265 .htotal = 1920 + 16 + 16 + 32, 3266 .vdisplay = 1200, 3267 .vsync_start = 1200 + 15, 3268 .vsync_end = 1200 + 15 + 2, 3269 .vtotal = 1200 + 15 + 2 + 18, 3270 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3271 }; 3272 3273 static const struct panel_desc starry_kr122ea0sra = { 3274 .modes = &starry_kr122ea0sra_mode, 3275 .num_modes = 1, 3276 .size = { 3277 .width = 263, 3278 .height = 164, 3279 }, 3280 .delay = { 3281 .prepare = 10 + 200, 3282 .enable = 50, 3283 .unprepare = 10 + 500, 3284 }, 3285 }; 3286 3287 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3288 .clock = 30000, 3289 .hdisplay = 800, 3290 .hsync_start = 800 + 39, 3291 .hsync_end = 800 + 39 + 47, 3292 .htotal = 800 + 39 + 47 + 39, 3293 .vdisplay = 480, 3294 .vsync_start = 480 + 13, 3295 .vsync_end = 480 + 13 + 2, 3296 .vtotal = 480 + 13 + 2 + 29, 3297 }; 3298 3299 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3300 .modes = &tfc_s9700rtwv43tr_01b_mode, 3301 .num_modes = 1, 3302 .bpc = 8, 3303 .size = { 3304 .width = 155, 3305 .height = 90, 3306 }, 3307 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3308 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3309 }; 3310 3311 static const struct display_timing tianma_tm070jdhg30_timing = { 3312 .pixelclock = { 62600000, 68200000, 78100000 }, 3313 .hactive = { 1280, 1280, 1280 }, 3314 .hfront_porch = { 15, 64, 159 }, 3315 .hback_porch = { 5, 5, 5 }, 3316 .hsync_len = { 1, 1, 256 }, 3317 .vactive = { 800, 800, 800 }, 3318 .vfront_porch = { 3, 40, 99 }, 3319 .vback_porch = { 2, 2, 2 }, 3320 .vsync_len = { 1, 1, 128 }, 3321 .flags = DISPLAY_FLAGS_DE_HIGH, 3322 }; 3323 3324 static const struct panel_desc tianma_tm070jdhg30 = { 3325 .timings = &tianma_tm070jdhg30_timing, 3326 .num_timings = 1, 3327 .bpc = 8, 3328 .size = { 3329 .width = 151, 3330 .height = 95, 3331 }, 3332 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3333 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3334 }; 3335 3336 static const struct display_timing tianma_tm070rvhg71_timing = { 3337 .pixelclock = { 27700000, 29200000, 39600000 }, 3338 .hactive = { 800, 800, 800 }, 3339 .hfront_porch = { 12, 40, 212 }, 3340 .hback_porch = { 88, 88, 88 }, 3341 .hsync_len = { 1, 1, 40 }, 3342 .vactive = { 480, 480, 480 }, 3343 .vfront_porch = { 1, 13, 88 }, 3344 .vback_porch = { 32, 32, 32 }, 3345 .vsync_len = { 1, 1, 3 }, 3346 .flags = DISPLAY_FLAGS_DE_HIGH, 3347 }; 3348 3349 static const struct panel_desc tianma_tm070rvhg71 = { 3350 .timings = &tianma_tm070rvhg71_timing, 3351 .num_timings = 1, 3352 .bpc = 8, 3353 .size = { 3354 .width = 154, 3355 .height = 86, 3356 }, 3357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3358 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3359 }; 3360 3361 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3362 { 3363 .clock = 10000, 3364 .hdisplay = 320, 3365 .hsync_start = 320 + 50, 3366 .hsync_end = 320 + 50 + 6, 3367 .htotal = 320 + 50 + 6 + 38, 3368 .vdisplay = 240, 3369 .vsync_start = 240 + 3, 3370 .vsync_end = 240 + 3 + 1, 3371 .vtotal = 240 + 3 + 1 + 17, 3372 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3373 }, 3374 }; 3375 3376 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3377 .modes = ti_nspire_cx_lcd_mode, 3378 .num_modes = 1, 3379 .bpc = 8, 3380 .size = { 3381 .width = 65, 3382 .height = 49, 3383 }, 3384 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3385 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3386 }; 3387 3388 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3389 { 3390 .clock = 10000, 3391 .hdisplay = 320, 3392 .hsync_start = 320 + 6, 3393 .hsync_end = 320 + 6 + 6, 3394 .htotal = 320 + 6 + 6 + 6, 3395 .vdisplay = 240, 3396 .vsync_start = 240 + 0, 3397 .vsync_end = 240 + 0 + 1, 3398 .vtotal = 240 + 0 + 1 + 0, 3399 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3400 }, 3401 }; 3402 3403 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3404 .modes = ti_nspire_classic_lcd_mode, 3405 .num_modes = 1, 3406 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3407 .bpc = 8, 3408 .size = { 3409 .width = 71, 3410 .height = 53, 3411 }, 3412 /* This is the grayscale bus format */ 3413 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3414 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3415 }; 3416 3417 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3418 .clock = 79500, 3419 .hdisplay = 1280, 3420 .hsync_start = 1280 + 192, 3421 .hsync_end = 1280 + 192 + 128, 3422 .htotal = 1280 + 192 + 128 + 64, 3423 .vdisplay = 768, 3424 .vsync_start = 768 + 20, 3425 .vsync_end = 768 + 20 + 7, 3426 .vtotal = 768 + 20 + 7 + 3, 3427 }; 3428 3429 static const struct panel_desc toshiba_lt089ac29000 = { 3430 .modes = &toshiba_lt089ac29000_mode, 3431 .num_modes = 1, 3432 .size = { 3433 .width = 194, 3434 .height = 116, 3435 }, 3436 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3437 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3438 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3439 }; 3440 3441 static const struct drm_display_mode tpk_f07a_0102_mode = { 3442 .clock = 33260, 3443 .hdisplay = 800, 3444 .hsync_start = 800 + 40, 3445 .hsync_end = 800 + 40 + 128, 3446 .htotal = 800 + 40 + 128 + 88, 3447 .vdisplay = 480, 3448 .vsync_start = 480 + 10, 3449 .vsync_end = 480 + 10 + 2, 3450 .vtotal = 480 + 10 + 2 + 33, 3451 }; 3452 3453 static const struct panel_desc tpk_f07a_0102 = { 3454 .modes = &tpk_f07a_0102_mode, 3455 .num_modes = 1, 3456 .size = { 3457 .width = 152, 3458 .height = 91, 3459 }, 3460 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3461 }; 3462 3463 static const struct drm_display_mode tpk_f10a_0102_mode = { 3464 .clock = 45000, 3465 .hdisplay = 1024, 3466 .hsync_start = 1024 + 176, 3467 .hsync_end = 1024 + 176 + 5, 3468 .htotal = 1024 + 176 + 5 + 88, 3469 .vdisplay = 600, 3470 .vsync_start = 600 + 20, 3471 .vsync_end = 600 + 20 + 5, 3472 .vtotal = 600 + 20 + 5 + 25, 3473 }; 3474 3475 static const struct panel_desc tpk_f10a_0102 = { 3476 .modes = &tpk_f10a_0102_mode, 3477 .num_modes = 1, 3478 .size = { 3479 .width = 223, 3480 .height = 125, 3481 }, 3482 }; 3483 3484 static const struct display_timing urt_umsh_8596md_timing = { 3485 .pixelclock = { 33260000, 33260000, 33260000 }, 3486 .hactive = { 800, 800, 800 }, 3487 .hfront_porch = { 41, 41, 41 }, 3488 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3489 .hsync_len = { 71, 128, 128 }, 3490 .vactive = { 480, 480, 480 }, 3491 .vfront_porch = { 10, 10, 10 }, 3492 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3493 .vsync_len = { 2, 2, 2 }, 3494 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3495 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3496 }; 3497 3498 static const struct panel_desc urt_umsh_8596md_lvds = { 3499 .timings = &urt_umsh_8596md_timing, 3500 .num_timings = 1, 3501 .bpc = 6, 3502 .size = { 3503 .width = 152, 3504 .height = 91, 3505 }, 3506 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3507 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3508 }; 3509 3510 static const struct panel_desc urt_umsh_8596md_parallel = { 3511 .timings = &urt_umsh_8596md_timing, 3512 .num_timings = 1, 3513 .bpc = 6, 3514 .size = { 3515 .width = 152, 3516 .height = 91, 3517 }, 3518 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3519 }; 3520 3521 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3522 .clock = 33333, 3523 .hdisplay = 800, 3524 .hsync_start = 800 + 210, 3525 .hsync_end = 800 + 210 + 20, 3526 .htotal = 800 + 210 + 20 + 46, 3527 .vdisplay = 480, 3528 .vsync_start = 480 + 22, 3529 .vsync_end = 480 + 22 + 10, 3530 .vtotal = 480 + 22 + 10 + 23, 3531 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3532 }; 3533 3534 static const struct panel_desc vl050_8048nt_c01 = { 3535 .modes = &vl050_8048nt_c01_mode, 3536 .num_modes = 1, 3537 .bpc = 8, 3538 .size = { 3539 .width = 120, 3540 .height = 76, 3541 }, 3542 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3543 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3544 }; 3545 3546 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3547 .clock = 6410, 3548 .hdisplay = 320, 3549 .hsync_start = 320 + 20, 3550 .hsync_end = 320 + 20 + 30, 3551 .htotal = 320 + 20 + 30 + 38, 3552 .vdisplay = 240, 3553 .vsync_start = 240 + 4, 3554 .vsync_end = 240 + 4 + 3, 3555 .vtotal = 240 + 4 + 3 + 15, 3556 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3557 }; 3558 3559 static const struct panel_desc winstar_wf35ltiacd = { 3560 .modes = &winstar_wf35ltiacd_mode, 3561 .num_modes = 1, 3562 .bpc = 8, 3563 .size = { 3564 .width = 70, 3565 .height = 53, 3566 }, 3567 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3568 }; 3569 3570 static const struct drm_display_mode arm_rtsm_mode[] = { 3571 { 3572 .clock = 65000, 3573 .hdisplay = 1024, 3574 .hsync_start = 1024 + 24, 3575 .hsync_end = 1024 + 24 + 136, 3576 .htotal = 1024 + 24 + 136 + 160, 3577 .vdisplay = 768, 3578 .vsync_start = 768 + 3, 3579 .vsync_end = 768 + 3 + 6, 3580 .vtotal = 768 + 3 + 6 + 29, 3581 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3582 }, 3583 }; 3584 3585 static const struct panel_desc arm_rtsm = { 3586 .modes = arm_rtsm_mode, 3587 .num_modes = 1, 3588 .bpc = 8, 3589 .size = { 3590 .width = 400, 3591 .height = 300, 3592 }, 3593 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3594 }; 3595 3596 static const struct of_device_id platform_of_match[] = { 3597 { 3598 .compatible = "ampire,am-480272h3tmqw-t01h", 3599 .data = &ire_am_480272h3tmqw_t01h, 3600 }, { 3601 .compatible = "ampire,am800480r3tmqwa1h", 3602 .data = &ire_am800480r3tmqwa1h, 3603 }, { 3604 .compatible = "arm,rtsm-display", 3605 .data = &arm_rtsm, 3606 }, { 3607 .compatible = "armadeus,st0700-adapt", 3608 .data = &armadeus_st0700_adapt, 3609 }, { 3610 .compatible = "auo,b101aw03", 3611 .data = &auo_b101aw03, 3612 }, { 3613 .compatible = "auo,b101ean01", 3614 .data = &auo_b101ean01, 3615 }, { 3616 .compatible = "auo,b101xtn01", 3617 .data = &auo_b101xtn01, 3618 }, { 3619 .compatible = "auo,b116xa01", 3620 .data = &auo_b116xak01, 3621 }, { 3622 .compatible = "auo,b116xw03", 3623 .data = &auo_b116xw03, 3624 }, { 3625 .compatible = "auo,b133htn01", 3626 .data = &auo_b133htn01, 3627 }, { 3628 .compatible = "auo,b133xtn01", 3629 .data = &auo_b133xtn01, 3630 }, { 3631 .compatible = "auo,g070vvn01", 3632 .data = &auo_g070vvn01, 3633 }, { 3634 .compatible = "auo,g101evn010", 3635 .data = &auo_g101evn010, 3636 }, { 3637 .compatible = "auo,g104sn02", 3638 .data = &auo_g104sn02, 3639 }, { 3640 .compatible = "auo,g121ean01", 3641 .data = &auo_g121ean01, 3642 }, { 3643 .compatible = "auo,g133han01", 3644 .data = &auo_g133han01, 3645 }, { 3646 .compatible = "auo,g156xtn01", 3647 .data = &auo_g156xtn01, 3648 }, { 3649 .compatible = "auo,g185han01", 3650 .data = &auo_g185han01, 3651 }, { 3652 .compatible = "auo,g190ean01", 3653 .data = &auo_g190ean01, 3654 }, { 3655 .compatible = "auo,p320hvn03", 3656 .data = &auo_p320hvn03, 3657 }, { 3658 .compatible = "auo,t215hvn01", 3659 .data = &auo_t215hvn01, 3660 }, { 3661 .compatible = "avic,tm070ddh03", 3662 .data = &avic_tm070ddh03, 3663 }, { 3664 .compatible = "bananapi,s070wv20-ct16", 3665 .data = &bananapi_s070wv20_ct16, 3666 }, { 3667 .compatible = "boe,hv070wsa-100", 3668 .data = &boe_hv070wsa 3669 }, { 3670 .compatible = "boe,nv101wxmn51", 3671 .data = &boe_nv101wxmn51, 3672 }, { 3673 .compatible = "boe,nv133fhm-n61", 3674 .data = &boe_nv133fhm_n61, 3675 }, { 3676 .compatible = "boe,nv133fhm-n62", 3677 .data = &boe_nv133fhm_n61, 3678 }, { 3679 .compatible = "boe,nv140fhmn49", 3680 .data = &boe_nv140fhmn49, 3681 }, { 3682 .compatible = "cdtech,s043wq26h-ct7", 3683 .data = &cdtech_s043wq26h_ct7, 3684 }, { 3685 .compatible = "cdtech,s070wv95-ct16", 3686 .data = &cdtech_s070wv95_ct16, 3687 }, { 3688 .compatible = "chunghwa,claa070wp03xg", 3689 .data = &chunghwa_claa070wp03xg, 3690 }, { 3691 .compatible = "chunghwa,claa101wa01a", 3692 .data = &chunghwa_claa101wa01a 3693 }, { 3694 .compatible = "chunghwa,claa101wb01", 3695 .data = &chunghwa_claa101wb01 3696 }, { 3697 .compatible = "dataimage,scf0700c48ggu18", 3698 .data = &dataimage_scf0700c48ggu18, 3699 }, { 3700 .compatible = "dlc,dlc0700yzg-1", 3701 .data = &dlc_dlc0700yzg_1, 3702 }, { 3703 .compatible = "dlc,dlc1010gig", 3704 .data = &dlc_dlc1010gig, 3705 }, { 3706 .compatible = "edt,et035012dm6", 3707 .data = &edt_et035012dm6, 3708 }, { 3709 .compatible = "edt,etm043080dh6gp", 3710 .data = &edt_etm043080dh6gp, 3711 }, { 3712 .compatible = "edt,etm0430g0dh6", 3713 .data = &edt_etm0430g0dh6, 3714 }, { 3715 .compatible = "edt,et057090dhu", 3716 .data = &edt_et057090dhu, 3717 }, { 3718 .compatible = "edt,et070080dh6", 3719 .data = &edt_etm0700g0dh6, 3720 }, { 3721 .compatible = "edt,etm0700g0dh6", 3722 .data = &edt_etm0700g0dh6, 3723 }, { 3724 .compatible = "edt,etm0700g0bdh6", 3725 .data = &edt_etm0700g0bdh6, 3726 }, { 3727 .compatible = "edt,etm0700g0edh6", 3728 .data = &edt_etm0700g0bdh6, 3729 }, { 3730 .compatible = "evervision,vgg804821", 3731 .data = &evervision_vgg804821, 3732 }, { 3733 .compatible = "foxlink,fl500wvr00-a0t", 3734 .data = &foxlink_fl500wvr00_a0t, 3735 }, { 3736 .compatible = "frida,frd350h54004", 3737 .data = &frida_frd350h54004, 3738 }, { 3739 .compatible = "friendlyarm,hd702e", 3740 .data = &friendlyarm_hd702e, 3741 }, { 3742 .compatible = "giantplus,gpg482739qs5", 3743 .data = &giantplus_gpg482739qs5 3744 }, { 3745 .compatible = "giantplus,gpm940b0", 3746 .data = &giantplus_gpm940b0, 3747 }, { 3748 .compatible = "hannstar,hsd070pww1", 3749 .data = &hannstar_hsd070pww1, 3750 }, { 3751 .compatible = "hannstar,hsd100pxn1", 3752 .data = &hannstar_hsd100pxn1, 3753 }, { 3754 .compatible = "hit,tx23d38vm0caa", 3755 .data = &hitachi_tx23d38vm0caa 3756 }, { 3757 .compatible = "innolux,at043tn24", 3758 .data = &innolux_at043tn24, 3759 }, { 3760 .compatible = "innolux,at070tn92", 3761 .data = &innolux_at070tn92, 3762 }, { 3763 .compatible = "innolux,g070y2-l01", 3764 .data = &innolux_g070y2_l01, 3765 }, { 3766 .compatible = "innolux,g101ice-l01", 3767 .data = &innolux_g101ice_l01 3768 }, { 3769 .compatible = "innolux,g121i1-l01", 3770 .data = &innolux_g121i1_l01 3771 }, { 3772 .compatible = "innolux,g121x1-l03", 3773 .data = &innolux_g121x1_l03, 3774 }, { 3775 .compatible = "innolux,n116bge", 3776 .data = &innolux_n116bge, 3777 }, { 3778 .compatible = "innolux,n156bge-l21", 3779 .data = &innolux_n156bge_l21, 3780 }, { 3781 .compatible = "innolux,p120zdg-bf1", 3782 .data = &innolux_p120zdg_bf1, 3783 }, { 3784 .compatible = "innolux,zj070na-01p", 3785 .data = &innolux_zj070na_01p, 3786 }, { 3787 .compatible = "ivo,m133nwf4-r0", 3788 .data = &ivo_m133nwf4_r0, 3789 }, { 3790 .compatible = "koe,tx14d24vm1bpa", 3791 .data = &koe_tx14d24vm1bpa, 3792 }, { 3793 .compatible = "koe,tx26d202vm0bwa", 3794 .data = &koe_tx26d202vm0bwa, 3795 }, { 3796 .compatible = "koe,tx31d200vm0baa", 3797 .data = &koe_tx31d200vm0baa, 3798 }, { 3799 .compatible = "kyo,tcg121xglp", 3800 .data = &kyo_tcg121xglp, 3801 }, { 3802 .compatible = "lemaker,bl035-rgb-002", 3803 .data = &lemaker_bl035_rgb_002, 3804 }, { 3805 .compatible = "lg,lb070wv8", 3806 .data = &lg_lb070wv8, 3807 }, { 3808 .compatible = "lg,lp079qx1-sp0v", 3809 .data = &lg_lp079qx1_sp0v, 3810 }, { 3811 .compatible = "lg,lp097qx1-spa1", 3812 .data = &lg_lp097qx1_spa1, 3813 }, { 3814 .compatible = "lg,lp120up1", 3815 .data = &lg_lp120up1, 3816 }, { 3817 .compatible = "lg,lp129qe", 3818 .data = &lg_lp129qe, 3819 }, { 3820 .compatible = "logicpd,type28", 3821 .data = &logicpd_type_28, 3822 }, { 3823 .compatible = "logictechno,lt161010-2nhc", 3824 .data = &logictechno_lt161010_2nh, 3825 }, { 3826 .compatible = "logictechno,lt161010-2nhr", 3827 .data = &logictechno_lt161010_2nh, 3828 }, { 3829 .compatible = "logictechno,lt170410-2whc", 3830 .data = &logictechno_lt170410_2whc, 3831 }, { 3832 .compatible = "mitsubishi,aa070mc01-ca1", 3833 .data = &mitsubishi_aa070mc01, 3834 }, { 3835 .compatible = "nec,nl12880bc20-05", 3836 .data = &nec_nl12880bc20_05, 3837 }, { 3838 .compatible = "nec,nl4827hc19-05b", 3839 .data = &nec_nl4827hc19_05b, 3840 }, { 3841 .compatible = "netron-dy,e231732", 3842 .data = &netron_dy_e231732, 3843 }, { 3844 .compatible = "neweast,wjfh116008a", 3845 .data = &neweast_wjfh116008a, 3846 }, { 3847 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3848 .data = &newhaven_nhd_43_480272ef_atxl, 3849 }, { 3850 .compatible = "nlt,nl192108ac18-02d", 3851 .data = &nlt_nl192108ac18_02d, 3852 }, { 3853 .compatible = "nvd,9128", 3854 .data = &nvd_9128, 3855 }, { 3856 .compatible = "okaya,rs800480t-7x0gp", 3857 .data = &okaya_rs800480t_7x0gp, 3858 }, { 3859 .compatible = "olimex,lcd-olinuxino-43-ts", 3860 .data = &olimex_lcd_olinuxino_43ts, 3861 }, { 3862 .compatible = "ontat,yx700wv03", 3863 .data = &ontat_yx700wv03, 3864 }, { 3865 .compatible = "ortustech,com37h3m05dtc", 3866 .data = &ortustech_com37h3m, 3867 }, { 3868 .compatible = "ortustech,com37h3m99dtc", 3869 .data = &ortustech_com37h3m, 3870 }, { 3871 .compatible = "ortustech,com43h4m85ulc", 3872 .data = &ortustech_com43h4m85ulc, 3873 }, { 3874 .compatible = "osddisplays,osd070t1718-19ts", 3875 .data = &osddisplays_osd070t1718_19ts, 3876 }, { 3877 .compatible = "pda,91-00156-a0", 3878 .data = &pda_91_00156_a0, 3879 }, { 3880 .compatible = "qiaodian,qd43003c0-40", 3881 .data = &qd43003c0_40, 3882 }, { 3883 .compatible = "rocktech,rk070er9427", 3884 .data = &rocktech_rk070er9427, 3885 }, { 3886 .compatible = "rocktech,rk101ii01d-ct", 3887 .data = &rocktech_rk101ii01d_ct, 3888 }, { 3889 .compatible = "samsung,lsn122dl01-c01", 3890 .data = &samsung_lsn122dl01_c01, 3891 }, { 3892 .compatible = "samsung,ltn101nt05", 3893 .data = &samsung_ltn101nt05, 3894 }, { 3895 .compatible = "samsung,ltn140at29-301", 3896 .data = &samsung_ltn140at29_301, 3897 }, { 3898 .compatible = "satoz,sat050at40h12r2", 3899 .data = &satoz_sat050at40h12r2, 3900 }, { 3901 .compatible = "sharp,ld-d5116z01b", 3902 .data = &sharp_ld_d5116z01b, 3903 }, { 3904 .compatible = "sharp,lq035q7db03", 3905 .data = &sharp_lq035q7db03, 3906 }, { 3907 .compatible = "sharp,lq070y3dg3b", 3908 .data = &sharp_lq070y3dg3b, 3909 }, { 3910 .compatible = "sharp,lq101k1ly04", 3911 .data = &sharp_lq101k1ly04, 3912 }, { 3913 .compatible = "sharp,lq123p1jx31", 3914 .data = &sharp_lq123p1jx31, 3915 }, { 3916 .compatible = "sharp,ls020b1dd01d", 3917 .data = &sharp_ls020b1dd01d, 3918 }, { 3919 .compatible = "shelly,sca07010-bfn-lnn", 3920 .data = &shelly_sca07010_bfn_lnn, 3921 }, { 3922 .compatible = "starry,kr070pe2t", 3923 .data = &starry_kr070pe2t, 3924 }, { 3925 .compatible = "starry,kr122ea0sra", 3926 .data = &starry_kr122ea0sra, 3927 }, { 3928 .compatible = "tfc,s9700rtwv43tr-01b", 3929 .data = &tfc_s9700rtwv43tr_01b, 3930 }, { 3931 .compatible = "tianma,tm070jdhg30", 3932 .data = &tianma_tm070jdhg30, 3933 }, { 3934 .compatible = "tianma,tm070rvhg71", 3935 .data = &tianma_tm070rvhg71, 3936 }, { 3937 .compatible = "ti,nspire-cx-lcd-panel", 3938 .data = &ti_nspire_cx_lcd_panel, 3939 }, { 3940 .compatible = "ti,nspire-classic-lcd-panel", 3941 .data = &ti_nspire_classic_lcd_panel, 3942 }, { 3943 .compatible = "toshiba,lt089ac29000", 3944 .data = &toshiba_lt089ac29000, 3945 }, { 3946 .compatible = "tpk,f07a-0102", 3947 .data = &tpk_f07a_0102, 3948 }, { 3949 .compatible = "tpk,f10a-0102", 3950 .data = &tpk_f10a_0102, 3951 }, { 3952 .compatible = "urt,umsh-8596md-t", 3953 .data = &urt_umsh_8596md_parallel, 3954 }, { 3955 .compatible = "urt,umsh-8596md-1t", 3956 .data = &urt_umsh_8596md_parallel, 3957 }, { 3958 .compatible = "urt,umsh-8596md-7t", 3959 .data = &urt_umsh_8596md_parallel, 3960 }, { 3961 .compatible = "urt,umsh-8596md-11t", 3962 .data = &urt_umsh_8596md_lvds, 3963 }, { 3964 .compatible = "urt,umsh-8596md-19t", 3965 .data = &urt_umsh_8596md_lvds, 3966 }, { 3967 .compatible = "urt,umsh-8596md-20t", 3968 .data = &urt_umsh_8596md_parallel, 3969 }, { 3970 .compatible = "vxt,vl050-8048nt-c01", 3971 .data = &vl050_8048nt_c01, 3972 }, { 3973 .compatible = "winstar,wf35ltiacd", 3974 .data = &winstar_wf35ltiacd, 3975 }, { 3976 /* Must be the last entry */ 3977 .compatible = "panel-dpi", 3978 .data = &panel_dpi, 3979 }, { 3980 /* sentinel */ 3981 } 3982 }; 3983 MODULE_DEVICE_TABLE(of, platform_of_match); 3984 3985 static int panel_simple_platform_probe(struct platform_device *pdev) 3986 { 3987 const struct of_device_id *id; 3988 3989 id = of_match_node(platform_of_match, pdev->dev.of_node); 3990 if (!id) 3991 return -ENODEV; 3992 3993 return panel_simple_probe(&pdev->dev, id->data); 3994 } 3995 3996 static int panel_simple_platform_remove(struct platform_device *pdev) 3997 { 3998 return panel_simple_remove(&pdev->dev); 3999 } 4000 4001 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4002 { 4003 panel_simple_shutdown(&pdev->dev); 4004 } 4005 4006 static struct platform_driver panel_simple_platform_driver = { 4007 .driver = { 4008 .name = "panel-simple", 4009 .of_match_table = platform_of_match, 4010 }, 4011 .probe = panel_simple_platform_probe, 4012 .remove = panel_simple_platform_remove, 4013 .shutdown = panel_simple_platform_shutdown, 4014 }; 4015 4016 struct panel_desc_dsi { 4017 struct panel_desc desc; 4018 4019 unsigned long flags; 4020 enum mipi_dsi_pixel_format format; 4021 unsigned int lanes; 4022 }; 4023 4024 static const struct drm_display_mode auo_b080uan01_mode = { 4025 .clock = 154500, 4026 .hdisplay = 1200, 4027 .hsync_start = 1200 + 62, 4028 .hsync_end = 1200 + 62 + 4, 4029 .htotal = 1200 + 62 + 4 + 62, 4030 .vdisplay = 1920, 4031 .vsync_start = 1920 + 9, 4032 .vsync_end = 1920 + 9 + 2, 4033 .vtotal = 1920 + 9 + 2 + 8, 4034 }; 4035 4036 static const struct panel_desc_dsi auo_b080uan01 = { 4037 .desc = { 4038 .modes = &auo_b080uan01_mode, 4039 .num_modes = 1, 4040 .bpc = 8, 4041 .size = { 4042 .width = 108, 4043 .height = 272, 4044 }, 4045 .connector_type = DRM_MODE_CONNECTOR_DSI, 4046 }, 4047 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4048 .format = MIPI_DSI_FMT_RGB888, 4049 .lanes = 4, 4050 }; 4051 4052 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4053 .clock = 160000, 4054 .hdisplay = 1200, 4055 .hsync_start = 1200 + 120, 4056 .hsync_end = 1200 + 120 + 20, 4057 .htotal = 1200 + 120 + 20 + 21, 4058 .vdisplay = 1920, 4059 .vsync_start = 1920 + 21, 4060 .vsync_end = 1920 + 21 + 3, 4061 .vtotal = 1920 + 21 + 3 + 18, 4062 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4063 }; 4064 4065 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4066 .desc = { 4067 .modes = &boe_tv080wum_nl0_mode, 4068 .num_modes = 1, 4069 .size = { 4070 .width = 107, 4071 .height = 172, 4072 }, 4073 .connector_type = DRM_MODE_CONNECTOR_DSI, 4074 }, 4075 .flags = MIPI_DSI_MODE_VIDEO | 4076 MIPI_DSI_MODE_VIDEO_BURST | 4077 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4078 .format = MIPI_DSI_FMT_RGB888, 4079 .lanes = 4, 4080 }; 4081 4082 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4083 .clock = 71000, 4084 .hdisplay = 800, 4085 .hsync_start = 800 + 32, 4086 .hsync_end = 800 + 32 + 1, 4087 .htotal = 800 + 32 + 1 + 57, 4088 .vdisplay = 1280, 4089 .vsync_start = 1280 + 28, 4090 .vsync_end = 1280 + 28 + 1, 4091 .vtotal = 1280 + 28 + 1 + 14, 4092 }; 4093 4094 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4095 .desc = { 4096 .modes = &lg_ld070wx3_sl01_mode, 4097 .num_modes = 1, 4098 .bpc = 8, 4099 .size = { 4100 .width = 94, 4101 .height = 151, 4102 }, 4103 .connector_type = DRM_MODE_CONNECTOR_DSI, 4104 }, 4105 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4106 .format = MIPI_DSI_FMT_RGB888, 4107 .lanes = 4, 4108 }; 4109 4110 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4111 .clock = 67000, 4112 .hdisplay = 720, 4113 .hsync_start = 720 + 12, 4114 .hsync_end = 720 + 12 + 4, 4115 .htotal = 720 + 12 + 4 + 112, 4116 .vdisplay = 1280, 4117 .vsync_start = 1280 + 8, 4118 .vsync_end = 1280 + 8 + 4, 4119 .vtotal = 1280 + 8 + 4 + 12, 4120 }; 4121 4122 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4123 .desc = { 4124 .modes = &lg_lh500wx1_sd03_mode, 4125 .num_modes = 1, 4126 .bpc = 8, 4127 .size = { 4128 .width = 62, 4129 .height = 110, 4130 }, 4131 .connector_type = DRM_MODE_CONNECTOR_DSI, 4132 }, 4133 .flags = MIPI_DSI_MODE_VIDEO, 4134 .format = MIPI_DSI_FMT_RGB888, 4135 .lanes = 4, 4136 }; 4137 4138 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4139 .clock = 157200, 4140 .hdisplay = 1920, 4141 .hsync_start = 1920 + 154, 4142 .hsync_end = 1920 + 154 + 16, 4143 .htotal = 1920 + 154 + 16 + 32, 4144 .vdisplay = 1200, 4145 .vsync_start = 1200 + 17, 4146 .vsync_end = 1200 + 17 + 2, 4147 .vtotal = 1200 + 17 + 2 + 16, 4148 }; 4149 4150 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4151 .desc = { 4152 .modes = &panasonic_vvx10f004b00_mode, 4153 .num_modes = 1, 4154 .bpc = 8, 4155 .size = { 4156 .width = 217, 4157 .height = 136, 4158 }, 4159 .connector_type = DRM_MODE_CONNECTOR_DSI, 4160 }, 4161 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4162 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4163 .format = MIPI_DSI_FMT_RGB888, 4164 .lanes = 4, 4165 }; 4166 4167 static const struct drm_display_mode lg_acx467akm_7_mode = { 4168 .clock = 150000, 4169 .hdisplay = 1080, 4170 .hsync_start = 1080 + 2, 4171 .hsync_end = 1080 + 2 + 2, 4172 .htotal = 1080 + 2 + 2 + 2, 4173 .vdisplay = 1920, 4174 .vsync_start = 1920 + 2, 4175 .vsync_end = 1920 + 2 + 2, 4176 .vtotal = 1920 + 2 + 2 + 2, 4177 }; 4178 4179 static const struct panel_desc_dsi lg_acx467akm_7 = { 4180 .desc = { 4181 .modes = &lg_acx467akm_7_mode, 4182 .num_modes = 1, 4183 .bpc = 8, 4184 .size = { 4185 .width = 62, 4186 .height = 110, 4187 }, 4188 .connector_type = DRM_MODE_CONNECTOR_DSI, 4189 }, 4190 .flags = 0, 4191 .format = MIPI_DSI_FMT_RGB888, 4192 .lanes = 4, 4193 }; 4194 4195 static const struct drm_display_mode osd101t2045_53ts_mode = { 4196 .clock = 154500, 4197 .hdisplay = 1920, 4198 .hsync_start = 1920 + 112, 4199 .hsync_end = 1920 + 112 + 16, 4200 .htotal = 1920 + 112 + 16 + 32, 4201 .vdisplay = 1200, 4202 .vsync_start = 1200 + 16, 4203 .vsync_end = 1200 + 16 + 2, 4204 .vtotal = 1200 + 16 + 2 + 16, 4205 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4206 }; 4207 4208 static const struct panel_desc_dsi osd101t2045_53ts = { 4209 .desc = { 4210 .modes = &osd101t2045_53ts_mode, 4211 .num_modes = 1, 4212 .bpc = 8, 4213 .size = { 4214 .width = 217, 4215 .height = 136, 4216 }, 4217 .connector_type = DRM_MODE_CONNECTOR_DSI, 4218 }, 4219 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4220 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4221 MIPI_DSI_MODE_EOT_PACKET, 4222 .format = MIPI_DSI_FMT_RGB888, 4223 .lanes = 4, 4224 }; 4225 4226 static const struct of_device_id dsi_of_match[] = { 4227 { 4228 .compatible = "auo,b080uan01", 4229 .data = &auo_b080uan01 4230 }, { 4231 .compatible = "boe,tv080wum-nl0", 4232 .data = &boe_tv080wum_nl0 4233 }, { 4234 .compatible = "lg,ld070wx3-sl01", 4235 .data = &lg_ld070wx3_sl01 4236 }, { 4237 .compatible = "lg,lh500wx1-sd03", 4238 .data = &lg_lh500wx1_sd03 4239 }, { 4240 .compatible = "panasonic,vvx10f004b00", 4241 .data = &panasonic_vvx10f004b00 4242 }, { 4243 .compatible = "lg,acx467akm-7", 4244 .data = &lg_acx467akm_7 4245 }, { 4246 .compatible = "osddisplays,osd101t2045-53ts", 4247 .data = &osd101t2045_53ts 4248 }, { 4249 /* sentinel */ 4250 } 4251 }; 4252 MODULE_DEVICE_TABLE(of, dsi_of_match); 4253 4254 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4255 { 4256 const struct panel_desc_dsi *desc; 4257 const struct of_device_id *id; 4258 int err; 4259 4260 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4261 if (!id) 4262 return -ENODEV; 4263 4264 desc = id->data; 4265 4266 err = panel_simple_probe(&dsi->dev, &desc->desc); 4267 if (err < 0) 4268 return err; 4269 4270 dsi->mode_flags = desc->flags; 4271 dsi->format = desc->format; 4272 dsi->lanes = desc->lanes; 4273 4274 err = mipi_dsi_attach(dsi); 4275 if (err) { 4276 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4277 4278 drm_panel_remove(&panel->base); 4279 } 4280 4281 return err; 4282 } 4283 4284 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4285 { 4286 int err; 4287 4288 err = mipi_dsi_detach(dsi); 4289 if (err < 0) 4290 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4291 4292 return panel_simple_remove(&dsi->dev); 4293 } 4294 4295 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4296 { 4297 panel_simple_shutdown(&dsi->dev); 4298 } 4299 4300 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4301 .driver = { 4302 .name = "panel-simple-dsi", 4303 .of_match_table = dsi_of_match, 4304 }, 4305 .probe = panel_simple_dsi_probe, 4306 .remove = panel_simple_dsi_remove, 4307 .shutdown = panel_simple_dsi_shutdown, 4308 }; 4309 4310 static int __init panel_simple_init(void) 4311 { 4312 int err; 4313 4314 err = platform_driver_register(&panel_simple_platform_driver); 4315 if (err < 0) 4316 return err; 4317 4318 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4319 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4320 if (err < 0) 4321 return err; 4322 } 4323 4324 return 0; 4325 } 4326 module_init(panel_simple_init); 4327 4328 static void __exit panel_simple_exit(void) 4329 { 4330 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4331 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4332 4333 platform_driver_unregister(&panel_simple_platform_driver); 4334 } 4335 module_exit(panel_simple_exit); 4336 4337 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4338 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4339 MODULE_LICENSE("GPL and additional rights"); 4340