1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 60 * Plug Detect isn't used. 61 * @enable: the time (in milliseconds) that it takes for the panel to 62 * display the first valid frame after starting to receive 63 * video data 64 * @disable: the time (in milliseconds) that it takes for the panel to 65 * turn the display off (no content is visible) 66 * @unprepare: the time (in milliseconds) that it takes for the panel 67 * to power itself down completely 68 */ 69 struct { 70 unsigned int prepare; 71 unsigned int hpd_absent_delay; 72 unsigned int enable; 73 unsigned int disable; 74 unsigned int unprepare; 75 } delay; 76 77 u32 bus_format; 78 u32 bus_flags; 79 }; 80 81 struct panel_simple { 82 struct drm_panel base; 83 bool prepared; 84 bool enabled; 85 bool no_hpd; 86 87 const struct panel_desc *desc; 88 89 struct backlight_device *backlight; 90 struct regulator *supply; 91 struct i2c_adapter *ddc; 92 93 struct gpio_desc *enable_gpio; 94 }; 95 96 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 97 { 98 return container_of(panel, struct panel_simple, base); 99 } 100 101 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 102 { 103 struct drm_connector *connector = panel->base.connector; 104 struct drm_device *drm = panel->base.drm; 105 struct drm_display_mode *mode; 106 unsigned int i, num = 0; 107 108 if (!panel->desc) 109 return 0; 110 111 for (i = 0; i < panel->desc->num_timings; i++) { 112 const struct display_timing *dt = &panel->desc->timings[i]; 113 struct videomode vm; 114 115 videomode_from_timing(dt, &vm); 116 mode = drm_mode_create(drm); 117 if (!mode) { 118 dev_err(drm->dev, "failed to add mode %ux%u\n", 119 dt->hactive.typ, dt->vactive.typ); 120 continue; 121 } 122 123 drm_display_mode_from_videomode(&vm, mode); 124 125 mode->type |= DRM_MODE_TYPE_DRIVER; 126 127 if (panel->desc->num_timings == 1) 128 mode->type |= DRM_MODE_TYPE_PREFERRED; 129 130 drm_mode_probed_add(connector, mode); 131 num++; 132 } 133 134 for (i = 0; i < panel->desc->num_modes; i++) { 135 const struct drm_display_mode *m = &panel->desc->modes[i]; 136 137 mode = drm_mode_duplicate(drm, m); 138 if (!mode) { 139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 140 m->hdisplay, m->vdisplay, m->vrefresh); 141 continue; 142 } 143 144 mode->type |= DRM_MODE_TYPE_DRIVER; 145 146 if (panel->desc->num_modes == 1) 147 mode->type |= DRM_MODE_TYPE_PREFERRED; 148 149 drm_mode_set_name(mode); 150 151 drm_mode_probed_add(connector, mode); 152 num++; 153 } 154 155 connector->display_info.bpc = panel->desc->bpc; 156 connector->display_info.width_mm = panel->desc->size.width; 157 connector->display_info.height_mm = panel->desc->size.height; 158 if (panel->desc->bus_format) 159 drm_display_info_set_bus_formats(&connector->display_info, 160 &panel->desc->bus_format, 1); 161 connector->display_info.bus_flags = panel->desc->bus_flags; 162 163 return num; 164 } 165 166 static int panel_simple_disable(struct drm_panel *panel) 167 { 168 struct panel_simple *p = to_panel_simple(panel); 169 170 if (!p->enabled) 171 return 0; 172 173 if (p->backlight) { 174 p->backlight->props.power = FB_BLANK_POWERDOWN; 175 p->backlight->props.state |= BL_CORE_FBBLANK; 176 backlight_update_status(p->backlight); 177 } 178 179 if (p->desc->delay.disable) 180 msleep(p->desc->delay.disable); 181 182 p->enabled = false; 183 184 return 0; 185 } 186 187 static int panel_simple_unprepare(struct drm_panel *panel) 188 { 189 struct panel_simple *p = to_panel_simple(panel); 190 191 if (!p->prepared) 192 return 0; 193 194 gpiod_set_value_cansleep(p->enable_gpio, 0); 195 196 regulator_disable(p->supply); 197 198 if (p->desc->delay.unprepare) 199 msleep(p->desc->delay.unprepare); 200 201 p->prepared = false; 202 203 return 0; 204 } 205 206 static int panel_simple_prepare(struct drm_panel *panel) 207 { 208 struct panel_simple *p = to_panel_simple(panel); 209 unsigned int delay; 210 int err; 211 212 if (p->prepared) 213 return 0; 214 215 err = regulator_enable(p->supply); 216 if (err < 0) { 217 dev_err(panel->dev, "failed to enable supply: %d\n", err); 218 return err; 219 } 220 221 gpiod_set_value_cansleep(p->enable_gpio, 1); 222 223 delay = p->desc->delay.prepare; 224 if (p->no_hpd) 225 delay += p->desc->delay.hpd_absent_delay; 226 if (delay) 227 msleep(delay); 228 229 p->prepared = true; 230 231 return 0; 232 } 233 234 static int panel_simple_enable(struct drm_panel *panel) 235 { 236 struct panel_simple *p = to_panel_simple(panel); 237 238 if (p->enabled) 239 return 0; 240 241 if (p->desc->delay.enable) 242 msleep(p->desc->delay.enable); 243 244 if (p->backlight) { 245 p->backlight->props.state &= ~BL_CORE_FBBLANK; 246 p->backlight->props.power = FB_BLANK_UNBLANK; 247 backlight_update_status(p->backlight); 248 } 249 250 p->enabled = true; 251 252 return 0; 253 } 254 255 static int panel_simple_get_modes(struct drm_panel *panel) 256 { 257 struct panel_simple *p = to_panel_simple(panel); 258 int num = 0; 259 260 /* probe EDID if a DDC bus is available */ 261 if (p->ddc) { 262 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 263 drm_connector_update_edid_property(panel->connector, edid); 264 if (edid) { 265 num += drm_add_edid_modes(panel->connector, edid); 266 kfree(edid); 267 } 268 } 269 270 /* add hard-coded panel modes */ 271 num += panel_simple_get_fixed_modes(p); 272 273 return num; 274 } 275 276 static int panel_simple_get_timings(struct drm_panel *panel, 277 unsigned int num_timings, 278 struct display_timing *timings) 279 { 280 struct panel_simple *p = to_panel_simple(panel); 281 unsigned int i; 282 283 if (p->desc->num_timings < num_timings) 284 num_timings = p->desc->num_timings; 285 286 if (timings) 287 for (i = 0; i < num_timings; i++) 288 timings[i] = p->desc->timings[i]; 289 290 return p->desc->num_timings; 291 } 292 293 static const struct drm_panel_funcs panel_simple_funcs = { 294 .disable = panel_simple_disable, 295 .unprepare = panel_simple_unprepare, 296 .prepare = panel_simple_prepare, 297 .enable = panel_simple_enable, 298 .get_modes = panel_simple_get_modes, 299 .get_timings = panel_simple_get_timings, 300 }; 301 302 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 303 { 304 struct device_node *backlight, *ddc; 305 struct panel_simple *panel; 306 int err; 307 308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 309 if (!panel) 310 return -ENOMEM; 311 312 panel->enabled = false; 313 panel->prepared = false; 314 panel->desc = desc; 315 316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 317 318 panel->supply = devm_regulator_get(dev, "power"); 319 if (IS_ERR(panel->supply)) 320 return PTR_ERR(panel->supply); 321 322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 323 GPIOD_OUT_LOW); 324 if (IS_ERR(panel->enable_gpio)) { 325 err = PTR_ERR(panel->enable_gpio); 326 if (err != -EPROBE_DEFER) 327 dev_err(dev, "failed to request GPIO: %d\n", err); 328 return err; 329 } 330 331 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 332 if (backlight) { 333 panel->backlight = of_find_backlight_by_node(backlight); 334 of_node_put(backlight); 335 336 if (!panel->backlight) 337 return -EPROBE_DEFER; 338 } 339 340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 341 if (ddc) { 342 panel->ddc = of_find_i2c_adapter_by_node(ddc); 343 of_node_put(ddc); 344 345 if (!panel->ddc) { 346 err = -EPROBE_DEFER; 347 goto free_backlight; 348 } 349 } 350 351 drm_panel_init(&panel->base); 352 panel->base.dev = dev; 353 panel->base.funcs = &panel_simple_funcs; 354 355 err = drm_panel_add(&panel->base); 356 if (err < 0) 357 goto free_ddc; 358 359 dev_set_drvdata(dev, panel); 360 361 return 0; 362 363 free_ddc: 364 if (panel->ddc) 365 put_device(&panel->ddc->dev); 366 free_backlight: 367 if (panel->backlight) 368 put_device(&panel->backlight->dev); 369 370 return err; 371 } 372 373 static int panel_simple_remove(struct device *dev) 374 { 375 struct panel_simple *panel = dev_get_drvdata(dev); 376 377 drm_panel_remove(&panel->base); 378 379 panel_simple_disable(&panel->base); 380 panel_simple_unprepare(&panel->base); 381 382 if (panel->ddc) 383 put_device(&panel->ddc->dev); 384 385 if (panel->backlight) 386 put_device(&panel->backlight->dev); 387 388 return 0; 389 } 390 391 static void panel_simple_shutdown(struct device *dev) 392 { 393 struct panel_simple *panel = dev_get_drvdata(dev); 394 395 panel_simple_disable(&panel->base); 396 panel_simple_unprepare(&panel->base); 397 } 398 399 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 400 .clock = 9000, 401 .hdisplay = 480, 402 .hsync_start = 480 + 2, 403 .hsync_end = 480 + 2 + 41, 404 .htotal = 480 + 2 + 41 + 2, 405 .vdisplay = 272, 406 .vsync_start = 272 + 2, 407 .vsync_end = 272 + 2 + 10, 408 .vtotal = 272 + 2 + 10 + 2, 409 .vrefresh = 60, 410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 411 }; 412 413 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 414 .modes = &ire_am_480272h3tmqw_t01h_mode, 415 .num_modes = 1, 416 .bpc = 8, 417 .size = { 418 .width = 105, 419 .height = 67, 420 }, 421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 422 }; 423 424 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 425 .clock = 33333, 426 .hdisplay = 800, 427 .hsync_start = 800 + 0, 428 .hsync_end = 800 + 0 + 255, 429 .htotal = 800 + 0 + 255 + 0, 430 .vdisplay = 480, 431 .vsync_start = 480 + 2, 432 .vsync_end = 480 + 2 + 45, 433 .vtotal = 480 + 2 + 45 + 0, 434 .vrefresh = 60, 435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 436 }; 437 438 static const struct panel_desc ampire_am800480r3tmqwa1h = { 439 .modes = &ire_am800480r3tmqwa1h_mode, 440 .num_modes = 1, 441 .bpc = 6, 442 .size = { 443 .width = 152, 444 .height = 91, 445 }, 446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 447 }; 448 449 static const struct drm_display_mode auo_b101aw03_mode = { 450 .clock = 51450, 451 .hdisplay = 1024, 452 .hsync_start = 1024 + 156, 453 .hsync_end = 1024 + 156 + 8, 454 .htotal = 1024 + 156 + 8 + 156, 455 .vdisplay = 600, 456 .vsync_start = 600 + 16, 457 .vsync_end = 600 + 16 + 6, 458 .vtotal = 600 + 16 + 6 + 16, 459 .vrefresh = 60, 460 }; 461 462 static const struct panel_desc auo_b101aw03 = { 463 .modes = &auo_b101aw03_mode, 464 .num_modes = 1, 465 .bpc = 6, 466 .size = { 467 .width = 223, 468 .height = 125, 469 }, 470 }; 471 472 static const struct drm_display_mode auo_b101ean01_mode = { 473 .clock = 72500, 474 .hdisplay = 1280, 475 .hsync_start = 1280 + 119, 476 .hsync_end = 1280 + 119 + 32, 477 .htotal = 1280 + 119 + 32 + 21, 478 .vdisplay = 800, 479 .vsync_start = 800 + 4, 480 .vsync_end = 800 + 4 + 20, 481 .vtotal = 800 + 4 + 20 + 8, 482 .vrefresh = 60, 483 }; 484 485 static const struct panel_desc auo_b101ean01 = { 486 .modes = &auo_b101ean01_mode, 487 .num_modes = 1, 488 .bpc = 6, 489 .size = { 490 .width = 217, 491 .height = 136, 492 }, 493 }; 494 495 static const struct drm_display_mode auo_b101xtn01_mode = { 496 .clock = 72000, 497 .hdisplay = 1366, 498 .hsync_start = 1366 + 20, 499 .hsync_end = 1366 + 20 + 70, 500 .htotal = 1366 + 20 + 70, 501 .vdisplay = 768, 502 .vsync_start = 768 + 14, 503 .vsync_end = 768 + 14 + 42, 504 .vtotal = 768 + 14 + 42, 505 .vrefresh = 60, 506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 507 }; 508 509 static const struct panel_desc auo_b101xtn01 = { 510 .modes = &auo_b101xtn01_mode, 511 .num_modes = 1, 512 .bpc = 6, 513 .size = { 514 .width = 223, 515 .height = 125, 516 }, 517 }; 518 519 static const struct drm_display_mode auo_b116xw03_mode = { 520 .clock = 70589, 521 .hdisplay = 1366, 522 .hsync_start = 1366 + 40, 523 .hsync_end = 1366 + 40 + 40, 524 .htotal = 1366 + 40 + 40 + 32, 525 .vdisplay = 768, 526 .vsync_start = 768 + 10, 527 .vsync_end = 768 + 10 + 12, 528 .vtotal = 768 + 10 + 12 + 6, 529 .vrefresh = 60, 530 }; 531 532 static const struct panel_desc auo_b116xw03 = { 533 .modes = &auo_b116xw03_mode, 534 .num_modes = 1, 535 .bpc = 6, 536 .size = { 537 .width = 256, 538 .height = 144, 539 }, 540 }; 541 542 static const struct drm_display_mode auo_b133xtn01_mode = { 543 .clock = 69500, 544 .hdisplay = 1366, 545 .hsync_start = 1366 + 48, 546 .hsync_end = 1366 + 48 + 32, 547 .htotal = 1366 + 48 + 32 + 20, 548 .vdisplay = 768, 549 .vsync_start = 768 + 3, 550 .vsync_end = 768 + 3 + 6, 551 .vtotal = 768 + 3 + 6 + 13, 552 .vrefresh = 60, 553 }; 554 555 static const struct panel_desc auo_b133xtn01 = { 556 .modes = &auo_b133xtn01_mode, 557 .num_modes = 1, 558 .bpc = 6, 559 .size = { 560 .width = 293, 561 .height = 165, 562 }, 563 }; 564 565 static const struct drm_display_mode auo_b133htn01_mode = { 566 .clock = 150660, 567 .hdisplay = 1920, 568 .hsync_start = 1920 + 172, 569 .hsync_end = 1920 + 172 + 80, 570 .htotal = 1920 + 172 + 80 + 60, 571 .vdisplay = 1080, 572 .vsync_start = 1080 + 25, 573 .vsync_end = 1080 + 25 + 10, 574 .vtotal = 1080 + 25 + 10 + 10, 575 .vrefresh = 60, 576 }; 577 578 static const struct panel_desc auo_b133htn01 = { 579 .modes = &auo_b133htn01_mode, 580 .num_modes = 1, 581 .bpc = 6, 582 .size = { 583 .width = 293, 584 .height = 165, 585 }, 586 .delay = { 587 .prepare = 105, 588 .enable = 20, 589 .unprepare = 50, 590 }, 591 }; 592 593 static const struct display_timing auo_g070vvn01_timings = { 594 .pixelclock = { 33300000, 34209000, 45000000 }, 595 .hactive = { 800, 800, 800 }, 596 .hfront_porch = { 20, 40, 200 }, 597 .hback_porch = { 87, 40, 1 }, 598 .hsync_len = { 1, 48, 87 }, 599 .vactive = { 480, 480, 480 }, 600 .vfront_porch = { 5, 13, 200 }, 601 .vback_porch = { 31, 31, 29 }, 602 .vsync_len = { 1, 1, 3 }, 603 }; 604 605 static const struct panel_desc auo_g070vvn01 = { 606 .timings = &auo_g070vvn01_timings, 607 .num_timings = 1, 608 .bpc = 8, 609 .size = { 610 .width = 152, 611 .height = 91, 612 }, 613 .delay = { 614 .prepare = 200, 615 .enable = 50, 616 .disable = 50, 617 .unprepare = 1000, 618 }, 619 }; 620 621 static const struct drm_display_mode auo_g104sn02_mode = { 622 .clock = 40000, 623 .hdisplay = 800, 624 .hsync_start = 800 + 40, 625 .hsync_end = 800 + 40 + 216, 626 .htotal = 800 + 40 + 216 + 128, 627 .vdisplay = 600, 628 .vsync_start = 600 + 10, 629 .vsync_end = 600 + 10 + 35, 630 .vtotal = 600 + 10 + 35 + 2, 631 .vrefresh = 60, 632 }; 633 634 static const struct panel_desc auo_g104sn02 = { 635 .modes = &auo_g104sn02_mode, 636 .num_modes = 1, 637 .bpc = 8, 638 .size = { 639 .width = 211, 640 .height = 158, 641 }, 642 }; 643 644 static const struct display_timing auo_g133han01_timings = { 645 .pixelclock = { 134000000, 141200000, 149000000 }, 646 .hactive = { 1920, 1920, 1920 }, 647 .hfront_porch = { 39, 58, 77 }, 648 .hback_porch = { 59, 88, 117 }, 649 .hsync_len = { 28, 42, 56 }, 650 .vactive = { 1080, 1080, 1080 }, 651 .vfront_porch = { 3, 8, 11 }, 652 .vback_porch = { 5, 14, 19 }, 653 .vsync_len = { 4, 14, 19 }, 654 }; 655 656 static const struct panel_desc auo_g133han01 = { 657 .timings = &auo_g133han01_timings, 658 .num_timings = 1, 659 .bpc = 8, 660 .size = { 661 .width = 293, 662 .height = 165, 663 }, 664 .delay = { 665 .prepare = 200, 666 .enable = 50, 667 .disable = 50, 668 .unprepare = 1000, 669 }, 670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 671 }; 672 673 static const struct display_timing auo_g185han01_timings = { 674 .pixelclock = { 120000000, 144000000, 175000000 }, 675 .hactive = { 1920, 1920, 1920 }, 676 .hfront_porch = { 18, 60, 74 }, 677 .hback_porch = { 12, 44, 54 }, 678 .hsync_len = { 10, 24, 32 }, 679 .vactive = { 1080, 1080, 1080 }, 680 .vfront_porch = { 6, 10, 40 }, 681 .vback_porch = { 2, 5, 20 }, 682 .vsync_len = { 2, 5, 20 }, 683 }; 684 685 static const struct panel_desc auo_g185han01 = { 686 .timings = &auo_g185han01_timings, 687 .num_timings = 1, 688 .bpc = 8, 689 .size = { 690 .width = 409, 691 .height = 230, 692 }, 693 .delay = { 694 .prepare = 50, 695 .enable = 200, 696 .disable = 110, 697 .unprepare = 1000, 698 }, 699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 700 }; 701 702 static const struct display_timing auo_p320hvn03_timings = { 703 .pixelclock = { 106000000, 148500000, 164000000 }, 704 .hactive = { 1920, 1920, 1920 }, 705 .hfront_porch = { 25, 50, 130 }, 706 .hback_porch = { 25, 50, 130 }, 707 .hsync_len = { 20, 40, 105 }, 708 .vactive = { 1080, 1080, 1080 }, 709 .vfront_porch = { 8, 17, 150 }, 710 .vback_porch = { 8, 17, 150 }, 711 .vsync_len = { 4, 11, 100 }, 712 }; 713 714 static const struct panel_desc auo_p320hvn03 = { 715 .timings = &auo_p320hvn03_timings, 716 .num_timings = 1, 717 .bpc = 8, 718 .size = { 719 .width = 698, 720 .height = 393, 721 }, 722 .delay = { 723 .prepare = 1, 724 .enable = 450, 725 .unprepare = 500, 726 }, 727 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 728 }; 729 730 static const struct drm_display_mode auo_t215hvn01_mode = { 731 .clock = 148800, 732 .hdisplay = 1920, 733 .hsync_start = 1920 + 88, 734 .hsync_end = 1920 + 88 + 44, 735 .htotal = 1920 + 88 + 44 + 148, 736 .vdisplay = 1080, 737 .vsync_start = 1080 + 4, 738 .vsync_end = 1080 + 4 + 5, 739 .vtotal = 1080 + 4 + 5 + 36, 740 .vrefresh = 60, 741 }; 742 743 static const struct panel_desc auo_t215hvn01 = { 744 .modes = &auo_t215hvn01_mode, 745 .num_modes = 1, 746 .bpc = 8, 747 .size = { 748 .width = 430, 749 .height = 270, 750 }, 751 .delay = { 752 .disable = 5, 753 .unprepare = 1000, 754 } 755 }; 756 757 static const struct drm_display_mode avic_tm070ddh03_mode = { 758 .clock = 51200, 759 .hdisplay = 1024, 760 .hsync_start = 1024 + 160, 761 .hsync_end = 1024 + 160 + 4, 762 .htotal = 1024 + 160 + 4 + 156, 763 .vdisplay = 600, 764 .vsync_start = 600 + 17, 765 .vsync_end = 600 + 17 + 1, 766 .vtotal = 600 + 17 + 1 + 17, 767 .vrefresh = 60, 768 }; 769 770 static const struct panel_desc avic_tm070ddh03 = { 771 .modes = &avic_tm070ddh03_mode, 772 .num_modes = 1, 773 .bpc = 8, 774 .size = { 775 .width = 154, 776 .height = 90, 777 }, 778 .delay = { 779 .prepare = 20, 780 .enable = 200, 781 .disable = 200, 782 }, 783 }; 784 785 static const struct drm_display_mode boe_hv070wsa_mode = { 786 .clock = 40800, 787 .hdisplay = 1024, 788 .hsync_start = 1024 + 90, 789 .hsync_end = 1024 + 90 + 90, 790 .htotal = 1024 + 90 + 90 + 90, 791 .vdisplay = 600, 792 .vsync_start = 600 + 3, 793 .vsync_end = 600 + 3 + 4, 794 .vtotal = 600 + 3 + 4 + 3, 795 .vrefresh = 60, 796 }; 797 798 static const struct panel_desc boe_hv070wsa = { 799 .modes = &boe_hv070wsa_mode, 800 .num_modes = 1, 801 .size = { 802 .width = 154, 803 .height = 90, 804 }, 805 }; 806 807 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 808 { 809 .clock = 71900, 810 .hdisplay = 1280, 811 .hsync_start = 1280 + 48, 812 .hsync_end = 1280 + 48 + 32, 813 .htotal = 1280 + 48 + 32 + 80, 814 .vdisplay = 800, 815 .vsync_start = 800 + 3, 816 .vsync_end = 800 + 3 + 5, 817 .vtotal = 800 + 3 + 5 + 24, 818 .vrefresh = 60, 819 }, 820 { 821 .clock = 57500, 822 .hdisplay = 1280, 823 .hsync_start = 1280 + 48, 824 .hsync_end = 1280 + 48 + 32, 825 .htotal = 1280 + 48 + 32 + 80, 826 .vdisplay = 800, 827 .vsync_start = 800 + 3, 828 .vsync_end = 800 + 3 + 5, 829 .vtotal = 800 + 3 + 5 + 24, 830 .vrefresh = 48, 831 }, 832 }; 833 834 static const struct panel_desc boe_nv101wxmn51 = { 835 .modes = boe_nv101wxmn51_modes, 836 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 837 .bpc = 8, 838 .size = { 839 .width = 217, 840 .height = 136, 841 }, 842 .delay = { 843 .prepare = 210, 844 .enable = 50, 845 .unprepare = 160, 846 }, 847 }; 848 849 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 850 .clock = 66770, 851 .hdisplay = 800, 852 .hsync_start = 800 + 49, 853 .hsync_end = 800 + 49 + 33, 854 .htotal = 800 + 49 + 33 + 17, 855 .vdisplay = 1280, 856 .vsync_start = 1280 + 1, 857 .vsync_end = 1280 + 1 + 7, 858 .vtotal = 1280 + 1 + 7 + 15, 859 .vrefresh = 60, 860 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 861 }; 862 863 static const struct panel_desc chunghwa_claa070wp03xg = { 864 .modes = &chunghwa_claa070wp03xg_mode, 865 .num_modes = 1, 866 .bpc = 6, 867 .size = { 868 .width = 94, 869 .height = 150, 870 }, 871 }; 872 873 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 874 .clock = 72070, 875 .hdisplay = 1366, 876 .hsync_start = 1366 + 58, 877 .hsync_end = 1366 + 58 + 58, 878 .htotal = 1366 + 58 + 58 + 58, 879 .vdisplay = 768, 880 .vsync_start = 768 + 4, 881 .vsync_end = 768 + 4 + 4, 882 .vtotal = 768 + 4 + 4 + 4, 883 .vrefresh = 60, 884 }; 885 886 static const struct panel_desc chunghwa_claa101wa01a = { 887 .modes = &chunghwa_claa101wa01a_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 220, 892 .height = 120, 893 }, 894 }; 895 896 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 897 .clock = 69300, 898 .hdisplay = 1366, 899 .hsync_start = 1366 + 48, 900 .hsync_end = 1366 + 48 + 32, 901 .htotal = 1366 + 48 + 32 + 20, 902 .vdisplay = 768, 903 .vsync_start = 768 + 16, 904 .vsync_end = 768 + 16 + 8, 905 .vtotal = 768 + 16 + 8 + 16, 906 .vrefresh = 60, 907 }; 908 909 static const struct panel_desc chunghwa_claa101wb01 = { 910 .modes = &chunghwa_claa101wb01_mode, 911 .num_modes = 1, 912 .bpc = 6, 913 .size = { 914 .width = 223, 915 .height = 125, 916 }, 917 }; 918 919 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 920 .clock = 33260, 921 .hdisplay = 800, 922 .hsync_start = 800 + 40, 923 .hsync_end = 800 + 40 + 128, 924 .htotal = 800 + 40 + 128 + 88, 925 .vdisplay = 480, 926 .vsync_start = 480 + 10, 927 .vsync_end = 480 + 10 + 2, 928 .vtotal = 480 + 10 + 2 + 33, 929 .vrefresh = 60, 930 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 931 }; 932 933 static const struct panel_desc dataimage_scf0700c48ggu18 = { 934 .modes = &dataimage_scf0700c48ggu18_mode, 935 .num_modes = 1, 936 .bpc = 8, 937 .size = { 938 .width = 152, 939 .height = 91, 940 }, 941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 943 }; 944 945 static const struct display_timing dlc_dlc0700yzg_1_timing = { 946 .pixelclock = { 45000000, 51200000, 57000000 }, 947 .hactive = { 1024, 1024, 1024 }, 948 .hfront_porch = { 100, 106, 113 }, 949 .hback_porch = { 100, 106, 113 }, 950 .hsync_len = { 100, 108, 114 }, 951 .vactive = { 600, 600, 600 }, 952 .vfront_porch = { 8, 11, 15 }, 953 .vback_porch = { 8, 11, 15 }, 954 .vsync_len = { 9, 13, 15 }, 955 .flags = DISPLAY_FLAGS_DE_HIGH, 956 }; 957 958 static const struct panel_desc dlc_dlc0700yzg_1 = { 959 .timings = &dlc_dlc0700yzg_1_timing, 960 .num_timings = 1, 961 .bpc = 6, 962 .size = { 963 .width = 154, 964 .height = 86, 965 }, 966 .delay = { 967 .prepare = 30, 968 .enable = 200, 969 .disable = 200, 970 }, 971 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 972 }; 973 974 static const struct drm_display_mode edt_et057090dhu_mode = { 975 .clock = 25175, 976 .hdisplay = 640, 977 .hsync_start = 640 + 16, 978 .hsync_end = 640 + 16 + 30, 979 .htotal = 640 + 16 + 30 + 114, 980 .vdisplay = 480, 981 .vsync_start = 480 + 10, 982 .vsync_end = 480 + 10 + 3, 983 .vtotal = 480 + 10 + 3 + 32, 984 .vrefresh = 60, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc edt_et057090dhu = { 989 .modes = &edt_et057090dhu_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 115, 994 .height = 86, 995 }, 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 998 }; 999 1000 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1001 .clock = 33260, 1002 .hdisplay = 800, 1003 .hsync_start = 800 + 40, 1004 .hsync_end = 800 + 40 + 128, 1005 .htotal = 800 + 40 + 128 + 88, 1006 .vdisplay = 480, 1007 .vsync_start = 480 + 10, 1008 .vsync_end = 480 + 10 + 2, 1009 .vtotal = 480 + 10 + 2 + 33, 1010 .vrefresh = 60, 1011 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1012 }; 1013 1014 static const struct panel_desc edt_etm0700g0dh6 = { 1015 .modes = &edt_etm0700g0dh6_mode, 1016 .num_modes = 1, 1017 .bpc = 6, 1018 .size = { 1019 .width = 152, 1020 .height = 91, 1021 }, 1022 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1023 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1024 }; 1025 1026 static const struct panel_desc edt_etm0700g0bdh6 = { 1027 .modes = &edt_etm0700g0dh6_mode, 1028 .num_modes = 1, 1029 .bpc = 6, 1030 .size = { 1031 .width = 152, 1032 .height = 91, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1035 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1036 }; 1037 1038 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1039 .clock = 32260, 1040 .hdisplay = 800, 1041 .hsync_start = 800 + 168, 1042 .hsync_end = 800 + 168 + 64, 1043 .htotal = 800 + 168 + 64 + 88, 1044 .vdisplay = 480, 1045 .vsync_start = 480 + 37, 1046 .vsync_end = 480 + 37 + 2, 1047 .vtotal = 480 + 37 + 2 + 8, 1048 .vrefresh = 60, 1049 }; 1050 1051 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1052 .modes = &foxlink_fl500wvr00_a0t_mode, 1053 .num_modes = 1, 1054 .bpc = 8, 1055 .size = { 1056 .width = 108, 1057 .height = 65, 1058 }, 1059 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1060 }; 1061 1062 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1063 .clock = 9000, 1064 .hdisplay = 480, 1065 .hsync_start = 480 + 5, 1066 .hsync_end = 480 + 5 + 1, 1067 .htotal = 480 + 5 + 1 + 40, 1068 .vdisplay = 272, 1069 .vsync_start = 272 + 8, 1070 .vsync_end = 272 + 8 + 1, 1071 .vtotal = 272 + 8 + 1 + 8, 1072 .vrefresh = 60, 1073 }; 1074 1075 static const struct panel_desc giantplus_gpg482739qs5 = { 1076 .modes = &giantplus_gpg482739qs5_mode, 1077 .num_modes = 1, 1078 .bpc = 8, 1079 .size = { 1080 .width = 95, 1081 .height = 54, 1082 }, 1083 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1084 }; 1085 1086 static const struct display_timing hannstar_hsd070pww1_timing = { 1087 .pixelclock = { 64300000, 71100000, 82000000 }, 1088 .hactive = { 1280, 1280, 1280 }, 1089 .hfront_porch = { 1, 1, 10 }, 1090 .hback_porch = { 1, 1, 10 }, 1091 /* 1092 * According to the data sheet, the minimum horizontal blanking interval 1093 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1094 * minimum working horizontal blanking interval to be 60 clocks. 1095 */ 1096 .hsync_len = { 58, 158, 661 }, 1097 .vactive = { 800, 800, 800 }, 1098 .vfront_porch = { 1, 1, 10 }, 1099 .vback_porch = { 1, 1, 10 }, 1100 .vsync_len = { 1, 21, 203 }, 1101 .flags = DISPLAY_FLAGS_DE_HIGH, 1102 }; 1103 1104 static const struct panel_desc hannstar_hsd070pww1 = { 1105 .timings = &hannstar_hsd070pww1_timing, 1106 .num_timings = 1, 1107 .bpc = 6, 1108 .size = { 1109 .width = 151, 1110 .height = 94, 1111 }, 1112 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1113 }; 1114 1115 static const struct display_timing hannstar_hsd100pxn1_timing = { 1116 .pixelclock = { 55000000, 65000000, 75000000 }, 1117 .hactive = { 1024, 1024, 1024 }, 1118 .hfront_porch = { 40, 40, 40 }, 1119 .hback_porch = { 220, 220, 220 }, 1120 .hsync_len = { 20, 60, 100 }, 1121 .vactive = { 768, 768, 768 }, 1122 .vfront_porch = { 7, 7, 7 }, 1123 .vback_porch = { 21, 21, 21 }, 1124 .vsync_len = { 10, 10, 10 }, 1125 .flags = DISPLAY_FLAGS_DE_HIGH, 1126 }; 1127 1128 static const struct panel_desc hannstar_hsd100pxn1 = { 1129 .timings = &hannstar_hsd100pxn1_timing, 1130 .num_timings = 1, 1131 .bpc = 6, 1132 .size = { 1133 .width = 203, 1134 .height = 152, 1135 }, 1136 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1137 }; 1138 1139 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1140 .clock = 33333, 1141 .hdisplay = 800, 1142 .hsync_start = 800 + 85, 1143 .hsync_end = 800 + 85 + 86, 1144 .htotal = 800 + 85 + 86 + 85, 1145 .vdisplay = 480, 1146 .vsync_start = 480 + 16, 1147 .vsync_end = 480 + 16 + 13, 1148 .vtotal = 480 + 16 + 13 + 16, 1149 .vrefresh = 60, 1150 }; 1151 1152 static const struct panel_desc hitachi_tx23d38vm0caa = { 1153 .modes = &hitachi_tx23d38vm0caa_mode, 1154 .num_modes = 1, 1155 .bpc = 6, 1156 .size = { 1157 .width = 195, 1158 .height = 117, 1159 }, 1160 .delay = { 1161 .enable = 160, 1162 .disable = 160, 1163 }, 1164 }; 1165 1166 static const struct drm_display_mode innolux_at043tn24_mode = { 1167 .clock = 9000, 1168 .hdisplay = 480, 1169 .hsync_start = 480 + 2, 1170 .hsync_end = 480 + 2 + 41, 1171 .htotal = 480 + 2 + 41 + 2, 1172 .vdisplay = 272, 1173 .vsync_start = 272 + 2, 1174 .vsync_end = 272 + 2 + 10, 1175 .vtotal = 272 + 2 + 10 + 2, 1176 .vrefresh = 60, 1177 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1178 }; 1179 1180 static const struct panel_desc innolux_at043tn24 = { 1181 .modes = &innolux_at043tn24_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 95, 1186 .height = 54, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1189 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1190 }; 1191 1192 static const struct drm_display_mode innolux_at070tn92_mode = { 1193 .clock = 33333, 1194 .hdisplay = 800, 1195 .hsync_start = 800 + 210, 1196 .hsync_end = 800 + 210 + 20, 1197 .htotal = 800 + 210 + 20 + 46, 1198 .vdisplay = 480, 1199 .vsync_start = 480 + 22, 1200 .vsync_end = 480 + 22 + 10, 1201 .vtotal = 480 + 22 + 23 + 10, 1202 .vrefresh = 60, 1203 }; 1204 1205 static const struct panel_desc innolux_at070tn92 = { 1206 .modes = &innolux_at070tn92_mode, 1207 .num_modes = 1, 1208 .size = { 1209 .width = 154, 1210 .height = 86, 1211 }, 1212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1213 }; 1214 1215 static const struct display_timing innolux_g070y2_l01_timing = { 1216 .pixelclock = { 28000000, 29500000, 32000000 }, 1217 .hactive = { 800, 800, 800 }, 1218 .hfront_porch = { 61, 91, 141 }, 1219 .hback_porch = { 60, 90, 140 }, 1220 .hsync_len = { 12, 12, 12 }, 1221 .vactive = { 480, 480, 480 }, 1222 .vfront_porch = { 4, 9, 30 }, 1223 .vback_porch = { 4, 8, 28 }, 1224 .vsync_len = { 2, 2, 2 }, 1225 .flags = DISPLAY_FLAGS_DE_HIGH, 1226 }; 1227 1228 static const struct panel_desc innolux_g070y2_l01 = { 1229 .timings = &innolux_g070y2_l01_timing, 1230 .num_timings = 1, 1231 .bpc = 6, 1232 .size = { 1233 .width = 152, 1234 .height = 91, 1235 }, 1236 .delay = { 1237 .prepare = 10, 1238 .enable = 100, 1239 .disable = 100, 1240 .unprepare = 800, 1241 }, 1242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1243 }; 1244 1245 static const struct display_timing innolux_g101ice_l01_timing = { 1246 .pixelclock = { 60400000, 71100000, 74700000 }, 1247 .hactive = { 1280, 1280, 1280 }, 1248 .hfront_porch = { 41, 80, 100 }, 1249 .hback_porch = { 40, 79, 99 }, 1250 .hsync_len = { 1, 1, 1 }, 1251 .vactive = { 800, 800, 800 }, 1252 .vfront_porch = { 5, 11, 14 }, 1253 .vback_porch = { 4, 11, 14 }, 1254 .vsync_len = { 1, 1, 1 }, 1255 .flags = DISPLAY_FLAGS_DE_HIGH, 1256 }; 1257 1258 static const struct panel_desc innolux_g101ice_l01 = { 1259 .timings = &innolux_g101ice_l01_timing, 1260 .num_timings = 1, 1261 .bpc = 8, 1262 .size = { 1263 .width = 217, 1264 .height = 135, 1265 }, 1266 .delay = { 1267 .enable = 200, 1268 .disable = 200, 1269 }, 1270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1271 }; 1272 1273 static const struct display_timing innolux_g121i1_l01_timing = { 1274 .pixelclock = { 67450000, 71000000, 74550000 }, 1275 .hactive = { 1280, 1280, 1280 }, 1276 .hfront_porch = { 40, 80, 160 }, 1277 .hback_porch = { 39, 79, 159 }, 1278 .hsync_len = { 1, 1, 1 }, 1279 .vactive = { 800, 800, 800 }, 1280 .vfront_porch = { 5, 11, 100 }, 1281 .vback_porch = { 4, 11, 99 }, 1282 .vsync_len = { 1, 1, 1 }, 1283 }; 1284 1285 static const struct panel_desc innolux_g121i1_l01 = { 1286 .timings = &innolux_g121i1_l01_timing, 1287 .num_timings = 1, 1288 .bpc = 6, 1289 .size = { 1290 .width = 261, 1291 .height = 163, 1292 }, 1293 .delay = { 1294 .enable = 200, 1295 .disable = 20, 1296 }, 1297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1298 }; 1299 1300 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1301 .clock = 65000, 1302 .hdisplay = 1024, 1303 .hsync_start = 1024 + 0, 1304 .hsync_end = 1024 + 1, 1305 .htotal = 1024 + 0 + 1 + 320, 1306 .vdisplay = 768, 1307 .vsync_start = 768 + 38, 1308 .vsync_end = 768 + 38 + 1, 1309 .vtotal = 768 + 38 + 1 + 0, 1310 .vrefresh = 60, 1311 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1312 }; 1313 1314 static const struct panel_desc innolux_g121x1_l03 = { 1315 .modes = &innolux_g121x1_l03_mode, 1316 .num_modes = 1, 1317 .bpc = 6, 1318 .size = { 1319 .width = 246, 1320 .height = 185, 1321 }, 1322 .delay = { 1323 .enable = 200, 1324 .unprepare = 200, 1325 .disable = 400, 1326 }, 1327 }; 1328 1329 static const struct drm_display_mode innolux_n116bge_mode = { 1330 .clock = 76420, 1331 .hdisplay = 1366, 1332 .hsync_start = 1366 + 136, 1333 .hsync_end = 1366 + 136 + 30, 1334 .htotal = 1366 + 136 + 30 + 60, 1335 .vdisplay = 768, 1336 .vsync_start = 768 + 8, 1337 .vsync_end = 768 + 8 + 12, 1338 .vtotal = 768 + 8 + 12 + 12, 1339 .vrefresh = 60, 1340 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1341 }; 1342 1343 static const struct panel_desc innolux_n116bge = { 1344 .modes = &innolux_n116bge_mode, 1345 .num_modes = 1, 1346 .bpc = 6, 1347 .size = { 1348 .width = 256, 1349 .height = 144, 1350 }, 1351 }; 1352 1353 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1354 .clock = 69300, 1355 .hdisplay = 1366, 1356 .hsync_start = 1366 + 16, 1357 .hsync_end = 1366 + 16 + 34, 1358 .htotal = 1366 + 16 + 34 + 50, 1359 .vdisplay = 768, 1360 .vsync_start = 768 + 2, 1361 .vsync_end = 768 + 2 + 6, 1362 .vtotal = 768 + 2 + 6 + 12, 1363 .vrefresh = 60, 1364 }; 1365 1366 static const struct panel_desc innolux_n156bge_l21 = { 1367 .modes = &innolux_n156bge_l21_mode, 1368 .num_modes = 1, 1369 .bpc = 6, 1370 .size = { 1371 .width = 344, 1372 .height = 193, 1373 }, 1374 }; 1375 1376 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1377 .clock = 206016, 1378 .hdisplay = 2160, 1379 .hsync_start = 2160 + 48, 1380 .hsync_end = 2160 + 48 + 32, 1381 .htotal = 2160 + 48 + 32 + 80, 1382 .vdisplay = 1440, 1383 .vsync_start = 1440 + 3, 1384 .vsync_end = 1440 + 3 + 10, 1385 .vtotal = 1440 + 3 + 10 + 27, 1386 .vrefresh = 60, 1387 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1388 }; 1389 1390 static const struct panel_desc innolux_p120zdg_bf1 = { 1391 .modes = &innolux_p120zdg_bf1_mode, 1392 .num_modes = 1, 1393 .bpc = 8, 1394 .size = { 1395 .width = 254, 1396 .height = 169, 1397 }, 1398 .delay = { 1399 .hpd_absent_delay = 200, 1400 .unprepare = 500, 1401 }, 1402 }; 1403 1404 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1405 .clock = 51501, 1406 .hdisplay = 1024, 1407 .hsync_start = 1024 + 128, 1408 .hsync_end = 1024 + 128 + 64, 1409 .htotal = 1024 + 128 + 64 + 128, 1410 .vdisplay = 600, 1411 .vsync_start = 600 + 16, 1412 .vsync_end = 600 + 16 + 4, 1413 .vtotal = 600 + 16 + 4 + 16, 1414 .vrefresh = 60, 1415 }; 1416 1417 static const struct panel_desc innolux_zj070na_01p = { 1418 .modes = &innolux_zj070na_01p_mode, 1419 .num_modes = 1, 1420 .bpc = 6, 1421 .size = { 1422 .width = 154, 1423 .height = 90, 1424 }, 1425 }; 1426 1427 static const struct display_timing koe_tx31d200vm0baa_timing = { 1428 .pixelclock = { 39600000, 43200000, 48000000 }, 1429 .hactive = { 1280, 1280, 1280 }, 1430 .hfront_porch = { 16, 36, 56 }, 1431 .hback_porch = { 16, 36, 56 }, 1432 .hsync_len = { 8, 8, 8 }, 1433 .vactive = { 480, 480, 480 }, 1434 .vfront_porch = { 6, 21, 33 }, 1435 .vback_porch = { 6, 21, 33 }, 1436 .vsync_len = { 8, 8, 8 }, 1437 .flags = DISPLAY_FLAGS_DE_HIGH, 1438 }; 1439 1440 static const struct panel_desc koe_tx31d200vm0baa = { 1441 .timings = &koe_tx31d200vm0baa_timing, 1442 .num_timings = 1, 1443 .bpc = 6, 1444 .size = { 1445 .width = 292, 1446 .height = 109, 1447 }, 1448 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1449 }; 1450 1451 static const struct display_timing kyo_tcg121xglp_timing = { 1452 .pixelclock = { 52000000, 65000000, 71000000 }, 1453 .hactive = { 1024, 1024, 1024 }, 1454 .hfront_porch = { 2, 2, 2 }, 1455 .hback_porch = { 2, 2, 2 }, 1456 .hsync_len = { 86, 124, 244 }, 1457 .vactive = { 768, 768, 768 }, 1458 .vfront_porch = { 2, 2, 2 }, 1459 .vback_porch = { 2, 2, 2 }, 1460 .vsync_len = { 6, 34, 73 }, 1461 .flags = DISPLAY_FLAGS_DE_HIGH, 1462 }; 1463 1464 static const struct panel_desc kyo_tcg121xglp = { 1465 .timings = &kyo_tcg121xglp_timing, 1466 .num_timings = 1, 1467 .bpc = 8, 1468 .size = { 1469 .width = 246, 1470 .height = 184, 1471 }, 1472 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1473 }; 1474 1475 static const struct drm_display_mode lg_lb070wv8_mode = { 1476 .clock = 33246, 1477 .hdisplay = 800, 1478 .hsync_start = 800 + 88, 1479 .hsync_end = 800 + 88 + 80, 1480 .htotal = 800 + 88 + 80 + 88, 1481 .vdisplay = 480, 1482 .vsync_start = 480 + 10, 1483 .vsync_end = 480 + 10 + 25, 1484 .vtotal = 480 + 10 + 25 + 10, 1485 .vrefresh = 60, 1486 }; 1487 1488 static const struct panel_desc lg_lb070wv8 = { 1489 .modes = &lg_lb070wv8_mode, 1490 .num_modes = 1, 1491 .bpc = 16, 1492 .size = { 1493 .width = 151, 1494 .height = 91, 1495 }, 1496 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1497 }; 1498 1499 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1500 .clock = 200000, 1501 .hdisplay = 1536, 1502 .hsync_start = 1536 + 12, 1503 .hsync_end = 1536 + 12 + 16, 1504 .htotal = 1536 + 12 + 16 + 48, 1505 .vdisplay = 2048, 1506 .vsync_start = 2048 + 8, 1507 .vsync_end = 2048 + 8 + 4, 1508 .vtotal = 2048 + 8 + 4 + 8, 1509 .vrefresh = 60, 1510 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1511 }; 1512 1513 static const struct panel_desc lg_lp079qx1_sp0v = { 1514 .modes = &lg_lp079qx1_sp0v_mode, 1515 .num_modes = 1, 1516 .size = { 1517 .width = 129, 1518 .height = 171, 1519 }, 1520 }; 1521 1522 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1523 .clock = 205210, 1524 .hdisplay = 2048, 1525 .hsync_start = 2048 + 150, 1526 .hsync_end = 2048 + 150 + 5, 1527 .htotal = 2048 + 150 + 5 + 5, 1528 .vdisplay = 1536, 1529 .vsync_start = 1536 + 3, 1530 .vsync_end = 1536 + 3 + 1, 1531 .vtotal = 1536 + 3 + 1 + 9, 1532 .vrefresh = 60, 1533 }; 1534 1535 static const struct panel_desc lg_lp097qx1_spa1 = { 1536 .modes = &lg_lp097qx1_spa1_mode, 1537 .num_modes = 1, 1538 .size = { 1539 .width = 208, 1540 .height = 147, 1541 }, 1542 }; 1543 1544 static const struct drm_display_mode lg_lp120up1_mode = { 1545 .clock = 162300, 1546 .hdisplay = 1920, 1547 .hsync_start = 1920 + 40, 1548 .hsync_end = 1920 + 40 + 40, 1549 .htotal = 1920 + 40 + 40+ 80, 1550 .vdisplay = 1280, 1551 .vsync_start = 1280 + 4, 1552 .vsync_end = 1280 + 4 + 4, 1553 .vtotal = 1280 + 4 + 4 + 12, 1554 .vrefresh = 60, 1555 }; 1556 1557 static const struct panel_desc lg_lp120up1 = { 1558 .modes = &lg_lp120up1_mode, 1559 .num_modes = 1, 1560 .bpc = 8, 1561 .size = { 1562 .width = 267, 1563 .height = 183, 1564 }, 1565 }; 1566 1567 static const struct drm_display_mode lg_lp129qe_mode = { 1568 .clock = 285250, 1569 .hdisplay = 2560, 1570 .hsync_start = 2560 + 48, 1571 .hsync_end = 2560 + 48 + 32, 1572 .htotal = 2560 + 48 + 32 + 80, 1573 .vdisplay = 1700, 1574 .vsync_start = 1700 + 3, 1575 .vsync_end = 1700 + 3 + 10, 1576 .vtotal = 1700 + 3 + 10 + 36, 1577 .vrefresh = 60, 1578 }; 1579 1580 static const struct panel_desc lg_lp129qe = { 1581 .modes = &lg_lp129qe_mode, 1582 .num_modes = 1, 1583 .bpc = 8, 1584 .size = { 1585 .width = 272, 1586 .height = 181, 1587 }, 1588 }; 1589 1590 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 1591 .clock = 30400, 1592 .hdisplay = 800, 1593 .hsync_start = 800 + 0, 1594 .hsync_end = 800 + 1, 1595 .htotal = 800 + 0 + 1 + 160, 1596 .vdisplay = 480, 1597 .vsync_start = 480 + 0, 1598 .vsync_end = 480 + 48 + 1, 1599 .vtotal = 480 + 48 + 1 + 0, 1600 .vrefresh = 60, 1601 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1602 }; 1603 1604 static const struct panel_desc mitsubishi_aa070mc01 = { 1605 .modes = &mitsubishi_aa070mc01_mode, 1606 .num_modes = 1, 1607 .bpc = 8, 1608 .size = { 1609 .width = 152, 1610 .height = 91, 1611 }, 1612 1613 .delay = { 1614 .enable = 200, 1615 .unprepare = 200, 1616 .disable = 400, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1620 }; 1621 1622 static const struct display_timing nec_nl12880bc20_05_timing = { 1623 .pixelclock = { 67000000, 71000000, 75000000 }, 1624 .hactive = { 1280, 1280, 1280 }, 1625 .hfront_porch = { 2, 30, 30 }, 1626 .hback_porch = { 6, 100, 100 }, 1627 .hsync_len = { 2, 30, 30 }, 1628 .vactive = { 800, 800, 800 }, 1629 .vfront_porch = { 5, 5, 5 }, 1630 .vback_porch = { 11, 11, 11 }, 1631 .vsync_len = { 7, 7, 7 }, 1632 }; 1633 1634 static const struct panel_desc nec_nl12880bc20_05 = { 1635 .timings = &nec_nl12880bc20_05_timing, 1636 .num_timings = 1, 1637 .bpc = 8, 1638 .size = { 1639 .width = 261, 1640 .height = 163, 1641 }, 1642 .delay = { 1643 .enable = 50, 1644 .disable = 50, 1645 }, 1646 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1647 }; 1648 1649 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1650 .clock = 10870, 1651 .hdisplay = 480, 1652 .hsync_start = 480 + 2, 1653 .hsync_end = 480 + 2 + 41, 1654 .htotal = 480 + 2 + 41 + 2, 1655 .vdisplay = 272, 1656 .vsync_start = 272 + 2, 1657 .vsync_end = 272 + 2 + 4, 1658 .vtotal = 272 + 2 + 4 + 2, 1659 .vrefresh = 74, 1660 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1661 }; 1662 1663 static const struct panel_desc nec_nl4827hc19_05b = { 1664 .modes = &nec_nl4827hc19_05b_mode, 1665 .num_modes = 1, 1666 .bpc = 8, 1667 .size = { 1668 .width = 95, 1669 .height = 54, 1670 }, 1671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1672 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1673 }; 1674 1675 static const struct drm_display_mode netron_dy_e231732_mode = { 1676 .clock = 66000, 1677 .hdisplay = 1024, 1678 .hsync_start = 1024 + 160, 1679 .hsync_end = 1024 + 160 + 70, 1680 .htotal = 1024 + 160 + 70 + 90, 1681 .vdisplay = 600, 1682 .vsync_start = 600 + 127, 1683 .vsync_end = 600 + 127 + 20, 1684 .vtotal = 600 + 127 + 20 + 3, 1685 .vrefresh = 60, 1686 }; 1687 1688 static const struct panel_desc netron_dy_e231732 = { 1689 .modes = &netron_dy_e231732_mode, 1690 .num_modes = 1, 1691 .size = { 1692 .width = 154, 1693 .height = 87, 1694 }, 1695 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1696 }; 1697 1698 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 1699 .clock = 9000, 1700 .hdisplay = 480, 1701 .hsync_start = 480 + 2, 1702 .hsync_end = 480 + 2 + 41, 1703 .htotal = 480 + 2 + 41 + 2, 1704 .vdisplay = 272, 1705 .vsync_start = 272 + 2, 1706 .vsync_end = 272 + 2 + 10, 1707 .vtotal = 272 + 2 + 10 + 2, 1708 .vrefresh = 60, 1709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1710 }; 1711 1712 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 1713 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 1714 .num_modes = 1, 1715 .bpc = 8, 1716 .size = { 1717 .width = 95, 1718 .height = 54, 1719 }, 1720 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1721 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 1722 DRM_BUS_FLAG_SYNC_POSEDGE, 1723 }; 1724 1725 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1726 .pixelclock = { 130000000, 148350000, 163000000 }, 1727 .hactive = { 1920, 1920, 1920 }, 1728 .hfront_porch = { 80, 100, 100 }, 1729 .hback_porch = { 100, 120, 120 }, 1730 .hsync_len = { 50, 60, 60 }, 1731 .vactive = { 1080, 1080, 1080 }, 1732 .vfront_porch = { 12, 30, 30 }, 1733 .vback_porch = { 4, 10, 10 }, 1734 .vsync_len = { 4, 5, 5 }, 1735 }; 1736 1737 static const struct panel_desc nlt_nl192108ac18_02d = { 1738 .timings = &nlt_nl192108ac18_02d_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 344, 1743 .height = 194, 1744 }, 1745 .delay = { 1746 .unprepare = 500, 1747 }, 1748 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1749 }; 1750 1751 static const struct drm_display_mode nvd_9128_mode = { 1752 .clock = 29500, 1753 .hdisplay = 800, 1754 .hsync_start = 800 + 130, 1755 .hsync_end = 800 + 130 + 98, 1756 .htotal = 800 + 0 + 130 + 98, 1757 .vdisplay = 480, 1758 .vsync_start = 480 + 10, 1759 .vsync_end = 480 + 10 + 50, 1760 .vtotal = 480 + 0 + 10 + 50, 1761 }; 1762 1763 static const struct panel_desc nvd_9128 = { 1764 .modes = &nvd_9128_mode, 1765 .num_modes = 1, 1766 .bpc = 8, 1767 .size = { 1768 .width = 156, 1769 .height = 88, 1770 }, 1771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1772 }; 1773 1774 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1775 .pixelclock = { 30000000, 30000000, 40000000 }, 1776 .hactive = { 800, 800, 800 }, 1777 .hfront_porch = { 40, 40, 40 }, 1778 .hback_porch = { 40, 40, 40 }, 1779 .hsync_len = { 1, 48, 48 }, 1780 .vactive = { 480, 480, 480 }, 1781 .vfront_porch = { 13, 13, 13 }, 1782 .vback_porch = { 29, 29, 29 }, 1783 .vsync_len = { 3, 3, 3 }, 1784 .flags = DISPLAY_FLAGS_DE_HIGH, 1785 }; 1786 1787 static const struct panel_desc okaya_rs800480t_7x0gp = { 1788 .timings = &okaya_rs800480t_7x0gp_timing, 1789 .num_timings = 1, 1790 .bpc = 6, 1791 .size = { 1792 .width = 154, 1793 .height = 87, 1794 }, 1795 .delay = { 1796 .prepare = 41, 1797 .enable = 50, 1798 .unprepare = 41, 1799 .disable = 50, 1800 }, 1801 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1802 }; 1803 1804 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1805 .clock = 9000, 1806 .hdisplay = 480, 1807 .hsync_start = 480 + 5, 1808 .hsync_end = 480 + 5 + 30, 1809 .htotal = 480 + 5 + 30 + 10, 1810 .vdisplay = 272, 1811 .vsync_start = 272 + 8, 1812 .vsync_end = 272 + 8 + 5, 1813 .vtotal = 272 + 8 + 5 + 3, 1814 .vrefresh = 60, 1815 }; 1816 1817 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1818 .modes = &olimex_lcd_olinuxino_43ts_mode, 1819 .num_modes = 1, 1820 .size = { 1821 .width = 95, 1822 .height = 54, 1823 }, 1824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1825 }; 1826 1827 /* 1828 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1829 * pixel clocks, but this is the timing that was being used in the Adafruit 1830 * installation instructions. 1831 */ 1832 static const struct drm_display_mode ontat_yx700wv03_mode = { 1833 .clock = 29500, 1834 .hdisplay = 800, 1835 .hsync_start = 824, 1836 .hsync_end = 896, 1837 .htotal = 992, 1838 .vdisplay = 480, 1839 .vsync_start = 483, 1840 .vsync_end = 493, 1841 .vtotal = 500, 1842 .vrefresh = 60, 1843 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1844 }; 1845 1846 /* 1847 * Specification at: 1848 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1849 */ 1850 static const struct panel_desc ontat_yx700wv03 = { 1851 .modes = &ontat_yx700wv03_mode, 1852 .num_modes = 1, 1853 .bpc = 8, 1854 .size = { 1855 .width = 154, 1856 .height = 83, 1857 }, 1858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1859 }; 1860 1861 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1862 .clock = 25000, 1863 .hdisplay = 480, 1864 .hsync_start = 480 + 10, 1865 .hsync_end = 480 + 10 + 10, 1866 .htotal = 480 + 10 + 10 + 15, 1867 .vdisplay = 800, 1868 .vsync_start = 800 + 3, 1869 .vsync_end = 800 + 3 + 3, 1870 .vtotal = 800 + 3 + 3 + 3, 1871 .vrefresh = 60, 1872 }; 1873 1874 static const struct panel_desc ortustech_com43h4m85ulc = { 1875 .modes = &ortustech_com43h4m85ulc_mode, 1876 .num_modes = 1, 1877 .bpc = 8, 1878 .size = { 1879 .width = 56, 1880 .height = 93, 1881 }, 1882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1883 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1884 }; 1885 1886 static const struct drm_display_mode qd43003c0_40_mode = { 1887 .clock = 9000, 1888 .hdisplay = 480, 1889 .hsync_start = 480 + 8, 1890 .hsync_end = 480 + 8 + 4, 1891 .htotal = 480 + 8 + 4 + 39, 1892 .vdisplay = 272, 1893 .vsync_start = 272 + 4, 1894 .vsync_end = 272 + 4 + 10, 1895 .vtotal = 272 + 4 + 10 + 2, 1896 .vrefresh = 60, 1897 }; 1898 1899 static const struct panel_desc qd43003c0_40 = { 1900 .modes = &qd43003c0_40_mode, 1901 .num_modes = 1, 1902 .bpc = 8, 1903 .size = { 1904 .width = 95, 1905 .height = 53, 1906 }, 1907 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1908 }; 1909 1910 static const struct display_timing rocktech_rk070er9427_timing = { 1911 .pixelclock = { 26400000, 33300000, 46800000 }, 1912 .hactive = { 800, 800, 800 }, 1913 .hfront_porch = { 16, 210, 354 }, 1914 .hback_porch = { 46, 46, 46 }, 1915 .hsync_len = { 1, 1, 1 }, 1916 .vactive = { 480, 480, 480 }, 1917 .vfront_porch = { 7, 22, 147 }, 1918 .vback_porch = { 23, 23, 23 }, 1919 .vsync_len = { 1, 1, 1 }, 1920 .flags = DISPLAY_FLAGS_DE_HIGH, 1921 }; 1922 1923 static const struct panel_desc rocktech_rk070er9427 = { 1924 .timings = &rocktech_rk070er9427_timing, 1925 .num_timings = 1, 1926 .bpc = 6, 1927 .size = { 1928 .width = 154, 1929 .height = 86, 1930 }, 1931 .delay = { 1932 .prepare = 41, 1933 .enable = 50, 1934 .unprepare = 41, 1935 .disable = 50, 1936 }, 1937 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1938 }; 1939 1940 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1941 .clock = 271560, 1942 .hdisplay = 2560, 1943 .hsync_start = 2560 + 48, 1944 .hsync_end = 2560 + 48 + 32, 1945 .htotal = 2560 + 48 + 32 + 80, 1946 .vdisplay = 1600, 1947 .vsync_start = 1600 + 2, 1948 .vsync_end = 1600 + 2 + 5, 1949 .vtotal = 1600 + 2 + 5 + 57, 1950 .vrefresh = 60, 1951 }; 1952 1953 static const struct panel_desc samsung_lsn122dl01_c01 = { 1954 .modes = &samsung_lsn122dl01_c01_mode, 1955 .num_modes = 1, 1956 .size = { 1957 .width = 263, 1958 .height = 164, 1959 }, 1960 }; 1961 1962 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1963 .clock = 54030, 1964 .hdisplay = 1024, 1965 .hsync_start = 1024 + 24, 1966 .hsync_end = 1024 + 24 + 136, 1967 .htotal = 1024 + 24 + 136 + 160, 1968 .vdisplay = 600, 1969 .vsync_start = 600 + 3, 1970 .vsync_end = 600 + 3 + 6, 1971 .vtotal = 600 + 3 + 6 + 61, 1972 .vrefresh = 60, 1973 }; 1974 1975 static const struct panel_desc samsung_ltn101nt05 = { 1976 .modes = &samsung_ltn101nt05_mode, 1977 .num_modes = 1, 1978 .bpc = 6, 1979 .size = { 1980 .width = 223, 1981 .height = 125, 1982 }, 1983 }; 1984 1985 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1986 .clock = 76300, 1987 .hdisplay = 1366, 1988 .hsync_start = 1366 + 64, 1989 .hsync_end = 1366 + 64 + 48, 1990 .htotal = 1366 + 64 + 48 + 128, 1991 .vdisplay = 768, 1992 .vsync_start = 768 + 2, 1993 .vsync_end = 768 + 2 + 5, 1994 .vtotal = 768 + 2 + 5 + 17, 1995 .vrefresh = 60, 1996 }; 1997 1998 static const struct panel_desc samsung_ltn140at29_301 = { 1999 .modes = &samsung_ltn140at29_301_mode, 2000 .num_modes = 1, 2001 .bpc = 6, 2002 .size = { 2003 .width = 320, 2004 .height = 187, 2005 }, 2006 }; 2007 2008 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2009 .clock = 5500, 2010 .hdisplay = 240, 2011 .hsync_start = 240 + 16, 2012 .hsync_end = 240 + 16 + 7, 2013 .htotal = 240 + 16 + 7 + 5, 2014 .vdisplay = 320, 2015 .vsync_start = 320 + 9, 2016 .vsync_end = 320 + 9 + 1, 2017 .vtotal = 320 + 9 + 1 + 7, 2018 .vrefresh = 60, 2019 }; 2020 2021 static const struct panel_desc sharp_lq035q7db03 = { 2022 .modes = &sharp_lq035q7db03_mode, 2023 .num_modes = 1, 2024 .bpc = 6, 2025 .size = { 2026 .width = 54, 2027 .height = 72, 2028 }, 2029 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2030 }; 2031 2032 static const struct display_timing sharp_lq101k1ly04_timing = { 2033 .pixelclock = { 60000000, 65000000, 80000000 }, 2034 .hactive = { 1280, 1280, 1280 }, 2035 .hfront_porch = { 20, 20, 20 }, 2036 .hback_porch = { 20, 20, 20 }, 2037 .hsync_len = { 10, 10, 10 }, 2038 .vactive = { 800, 800, 800 }, 2039 .vfront_porch = { 4, 4, 4 }, 2040 .vback_porch = { 4, 4, 4 }, 2041 .vsync_len = { 4, 4, 4 }, 2042 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2043 }; 2044 2045 static const struct panel_desc sharp_lq101k1ly04 = { 2046 .timings = &sharp_lq101k1ly04_timing, 2047 .num_timings = 1, 2048 .bpc = 8, 2049 .size = { 2050 .width = 217, 2051 .height = 136, 2052 }, 2053 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2054 }; 2055 2056 static const struct display_timing sharp_lq123p1jx31_timing = { 2057 .pixelclock = { 252750000, 252750000, 266604720 }, 2058 .hactive = { 2400, 2400, 2400 }, 2059 .hfront_porch = { 48, 48, 48 }, 2060 .hback_porch = { 80, 80, 84 }, 2061 .hsync_len = { 32, 32, 32 }, 2062 .vactive = { 1600, 1600, 1600 }, 2063 .vfront_porch = { 3, 3, 3 }, 2064 .vback_porch = { 33, 33, 120 }, 2065 .vsync_len = { 10, 10, 10 }, 2066 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2067 }; 2068 2069 static const struct panel_desc sharp_lq123p1jx31 = { 2070 .timings = &sharp_lq123p1jx31_timing, 2071 .num_timings = 1, 2072 .bpc = 8, 2073 .size = { 2074 .width = 259, 2075 .height = 173, 2076 }, 2077 .delay = { 2078 .prepare = 110, 2079 .enable = 50, 2080 .unprepare = 550, 2081 }, 2082 }; 2083 2084 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2085 .clock = 71100, 2086 .hdisplay = 1024, 2087 .hsync_start = 1024 + 168, 2088 .hsync_end = 1024 + 168 + 64, 2089 .htotal = 1024 + 168 + 64 + 88, 2090 .vdisplay = 768, 2091 .vsync_start = 768 + 37, 2092 .vsync_end = 768 + 37 + 2, 2093 .vtotal = 768 + 37 + 2 + 8, 2094 .vrefresh = 60, 2095 }; 2096 2097 static const struct panel_desc sharp_lq150x1lg11 = { 2098 .modes = &sharp_lq150x1lg11_mode, 2099 .num_modes = 1, 2100 .bpc = 6, 2101 .size = { 2102 .width = 304, 2103 .height = 228, 2104 }, 2105 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2106 }; 2107 2108 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2109 .clock = 33300, 2110 .hdisplay = 800, 2111 .hsync_start = 800 + 1, 2112 .hsync_end = 800 + 1 + 64, 2113 .htotal = 800 + 1 + 64 + 64, 2114 .vdisplay = 480, 2115 .vsync_start = 480 + 1, 2116 .vsync_end = 480 + 1 + 23, 2117 .vtotal = 480 + 1 + 23 + 22, 2118 .vrefresh = 60, 2119 }; 2120 2121 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2122 .modes = &shelly_sca07010_bfn_lnn_mode, 2123 .num_modes = 1, 2124 .size = { 2125 .width = 152, 2126 .height = 91, 2127 }, 2128 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2129 }; 2130 2131 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2132 .clock = 147000, 2133 .hdisplay = 1920, 2134 .hsync_start = 1920 + 16, 2135 .hsync_end = 1920 + 16 + 16, 2136 .htotal = 1920 + 16 + 16 + 32, 2137 .vdisplay = 1200, 2138 .vsync_start = 1200 + 15, 2139 .vsync_end = 1200 + 15 + 2, 2140 .vtotal = 1200 + 15 + 2 + 18, 2141 .vrefresh = 60, 2142 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2143 }; 2144 2145 static const struct panel_desc starry_kr122ea0sra = { 2146 .modes = &starry_kr122ea0sra_mode, 2147 .num_modes = 1, 2148 .size = { 2149 .width = 263, 2150 .height = 164, 2151 }, 2152 .delay = { 2153 .prepare = 10 + 200, 2154 .enable = 50, 2155 .unprepare = 10 + 500, 2156 }, 2157 }; 2158 2159 static const struct display_timing tianma_tm070jdhg30_timing = { 2160 .pixelclock = { 62600000, 68200000, 78100000 }, 2161 .hactive = { 1280, 1280, 1280 }, 2162 .hfront_porch = { 15, 64, 159 }, 2163 .hback_porch = { 5, 5, 5 }, 2164 .hsync_len = { 1, 1, 256 }, 2165 .vactive = { 800, 800, 800 }, 2166 .vfront_porch = { 3, 40, 99 }, 2167 .vback_porch = { 2, 2, 2 }, 2168 .vsync_len = { 1, 1, 128 }, 2169 .flags = DISPLAY_FLAGS_DE_HIGH, 2170 }; 2171 2172 static const struct panel_desc tianma_tm070jdhg30 = { 2173 .timings = &tianma_tm070jdhg30_timing, 2174 .num_timings = 1, 2175 .bpc = 8, 2176 .size = { 2177 .width = 151, 2178 .height = 95, 2179 }, 2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2181 }; 2182 2183 static const struct display_timing tianma_tm070rvhg71_timing = { 2184 .pixelclock = { 27700000, 29200000, 39600000 }, 2185 .hactive = { 800, 800, 800 }, 2186 .hfront_porch = { 12, 40, 212 }, 2187 .hback_porch = { 88, 88, 88 }, 2188 .hsync_len = { 1, 1, 40 }, 2189 .vactive = { 480, 480, 480 }, 2190 .vfront_porch = { 1, 13, 88 }, 2191 .vback_porch = { 32, 32, 32 }, 2192 .vsync_len = { 1, 1, 3 }, 2193 .flags = DISPLAY_FLAGS_DE_HIGH, 2194 }; 2195 2196 static const struct panel_desc tianma_tm070rvhg71 = { 2197 .timings = &tianma_tm070rvhg71_timing, 2198 .num_timings = 1, 2199 .bpc = 8, 2200 .size = { 2201 .width = 154, 2202 .height = 86, 2203 }, 2204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2205 }; 2206 2207 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 2208 .clock = 79500, 2209 .hdisplay = 1280, 2210 .hsync_start = 1280 + 192, 2211 .hsync_end = 1280 + 192 + 128, 2212 .htotal = 1280 + 192 + 128 + 64, 2213 .vdisplay = 768, 2214 .vsync_start = 768 + 20, 2215 .vsync_end = 768 + 20 + 7, 2216 .vtotal = 768 + 20 + 7 + 3, 2217 .vrefresh = 60, 2218 }; 2219 2220 static const struct panel_desc toshiba_lt089ac29000 = { 2221 .modes = &toshiba_lt089ac29000_mode, 2222 .num_modes = 1, 2223 .size = { 2224 .width = 194, 2225 .height = 116, 2226 }, 2227 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2228 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 2229 }; 2230 2231 static const struct drm_display_mode tpk_f07a_0102_mode = { 2232 .clock = 33260, 2233 .hdisplay = 800, 2234 .hsync_start = 800 + 40, 2235 .hsync_end = 800 + 40 + 128, 2236 .htotal = 800 + 40 + 128 + 88, 2237 .vdisplay = 480, 2238 .vsync_start = 480 + 10, 2239 .vsync_end = 480 + 10 + 2, 2240 .vtotal = 480 + 10 + 2 + 33, 2241 .vrefresh = 60, 2242 }; 2243 2244 static const struct panel_desc tpk_f07a_0102 = { 2245 .modes = &tpk_f07a_0102_mode, 2246 .num_modes = 1, 2247 .size = { 2248 .width = 152, 2249 .height = 91, 2250 }, 2251 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 2252 }; 2253 2254 static const struct drm_display_mode tpk_f10a_0102_mode = { 2255 .clock = 45000, 2256 .hdisplay = 1024, 2257 .hsync_start = 1024 + 176, 2258 .hsync_end = 1024 + 176 + 5, 2259 .htotal = 1024 + 176 + 5 + 88, 2260 .vdisplay = 600, 2261 .vsync_start = 600 + 20, 2262 .vsync_end = 600 + 20 + 5, 2263 .vtotal = 600 + 20 + 5 + 25, 2264 .vrefresh = 60, 2265 }; 2266 2267 static const struct panel_desc tpk_f10a_0102 = { 2268 .modes = &tpk_f10a_0102_mode, 2269 .num_modes = 1, 2270 .size = { 2271 .width = 223, 2272 .height = 125, 2273 }, 2274 }; 2275 2276 static const struct display_timing urt_umsh_8596md_timing = { 2277 .pixelclock = { 33260000, 33260000, 33260000 }, 2278 .hactive = { 800, 800, 800 }, 2279 .hfront_porch = { 41, 41, 41 }, 2280 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 2281 .hsync_len = { 71, 128, 128 }, 2282 .vactive = { 480, 480, 480 }, 2283 .vfront_porch = { 10, 10, 10 }, 2284 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 2285 .vsync_len = { 2, 2, 2 }, 2286 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2287 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2288 }; 2289 2290 static const struct panel_desc urt_umsh_8596md_lvds = { 2291 .timings = &urt_umsh_8596md_timing, 2292 .num_timings = 1, 2293 .bpc = 6, 2294 .size = { 2295 .width = 152, 2296 .height = 91, 2297 }, 2298 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2299 }; 2300 2301 static const struct panel_desc urt_umsh_8596md_parallel = { 2302 .timings = &urt_umsh_8596md_timing, 2303 .num_timings = 1, 2304 .bpc = 6, 2305 .size = { 2306 .width = 152, 2307 .height = 91, 2308 }, 2309 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2310 }; 2311 2312 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 2313 .clock = 6410, 2314 .hdisplay = 320, 2315 .hsync_start = 320 + 20, 2316 .hsync_end = 320 + 20 + 30, 2317 .htotal = 320 + 20 + 30 + 38, 2318 .vdisplay = 240, 2319 .vsync_start = 240 + 4, 2320 .vsync_end = 240 + 4 + 3, 2321 .vtotal = 240 + 4 + 3 + 15, 2322 .vrefresh = 60, 2323 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2324 }; 2325 2326 static const struct panel_desc winstar_wf35ltiacd = { 2327 .modes = &winstar_wf35ltiacd_mode, 2328 .num_modes = 1, 2329 .bpc = 8, 2330 .size = { 2331 .width = 70, 2332 .height = 53, 2333 }, 2334 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2335 }; 2336 2337 static const struct of_device_id platform_of_match[] = { 2338 { 2339 .compatible = "ampire,am-480272h3tmqw-t01h", 2340 .data = &ire_am_480272h3tmqw_t01h, 2341 }, { 2342 .compatible = "ampire,am800480r3tmqwa1h", 2343 .data = &ire_am800480r3tmqwa1h, 2344 }, { 2345 .compatible = "auo,b101aw03", 2346 .data = &auo_b101aw03, 2347 }, { 2348 .compatible = "auo,b101ean01", 2349 .data = &auo_b101ean01, 2350 }, { 2351 .compatible = "auo,b101xtn01", 2352 .data = &auo_b101xtn01, 2353 }, { 2354 .compatible = "auo,b116xw03", 2355 .data = &auo_b116xw03, 2356 }, { 2357 .compatible = "auo,b133htn01", 2358 .data = &auo_b133htn01, 2359 }, { 2360 .compatible = "auo,b133xtn01", 2361 .data = &auo_b133xtn01, 2362 }, { 2363 .compatible = "auo,g070vvn01", 2364 .data = &auo_g070vvn01, 2365 }, { 2366 .compatible = "auo,g104sn02", 2367 .data = &auo_g104sn02, 2368 }, { 2369 .compatible = "auo,g133han01", 2370 .data = &auo_g133han01, 2371 }, { 2372 .compatible = "auo,g185han01", 2373 .data = &auo_g185han01, 2374 }, { 2375 .compatible = "auo,p320hvn03", 2376 .data = &auo_p320hvn03, 2377 }, { 2378 .compatible = "auo,t215hvn01", 2379 .data = &auo_t215hvn01, 2380 }, { 2381 .compatible = "avic,tm070ddh03", 2382 .data = &avic_tm070ddh03, 2383 }, { 2384 .compatible = "boe,hv070wsa-100", 2385 .data = &boe_hv070wsa 2386 }, { 2387 .compatible = "boe,nv101wxmn51", 2388 .data = &boe_nv101wxmn51, 2389 }, { 2390 .compatible = "chunghwa,claa070wp03xg", 2391 .data = &chunghwa_claa070wp03xg, 2392 }, { 2393 .compatible = "chunghwa,claa101wa01a", 2394 .data = &chunghwa_claa101wa01a 2395 }, { 2396 .compatible = "chunghwa,claa101wb01", 2397 .data = &chunghwa_claa101wb01 2398 }, { 2399 .compatible = "dataimage,scf0700c48ggu18", 2400 .data = &dataimage_scf0700c48ggu18, 2401 }, { 2402 .compatible = "dlc,dlc0700yzg-1", 2403 .data = &dlc_dlc0700yzg_1, 2404 }, { 2405 .compatible = "edt,et057090dhu", 2406 .data = &edt_et057090dhu, 2407 }, { 2408 .compatible = "edt,et070080dh6", 2409 .data = &edt_etm0700g0dh6, 2410 }, { 2411 .compatible = "edt,etm0700g0dh6", 2412 .data = &edt_etm0700g0dh6, 2413 }, { 2414 .compatible = "edt,etm0700g0bdh6", 2415 .data = &edt_etm0700g0bdh6, 2416 }, { 2417 .compatible = "edt,etm0700g0edh6", 2418 .data = &edt_etm0700g0bdh6, 2419 }, { 2420 .compatible = "foxlink,fl500wvr00-a0t", 2421 .data = &foxlink_fl500wvr00_a0t, 2422 }, { 2423 .compatible = "giantplus,gpg482739qs5", 2424 .data = &giantplus_gpg482739qs5 2425 }, { 2426 .compatible = "hannstar,hsd070pww1", 2427 .data = &hannstar_hsd070pww1, 2428 }, { 2429 .compatible = "hannstar,hsd100pxn1", 2430 .data = &hannstar_hsd100pxn1, 2431 }, { 2432 .compatible = "hit,tx23d38vm0caa", 2433 .data = &hitachi_tx23d38vm0caa 2434 }, { 2435 .compatible = "innolux,at043tn24", 2436 .data = &innolux_at043tn24, 2437 }, { 2438 .compatible = "innolux,at070tn92", 2439 .data = &innolux_at070tn92, 2440 }, { 2441 .compatible = "innolux,g070y2-l01", 2442 .data = &innolux_g070y2_l01, 2443 }, { 2444 .compatible = "innolux,g101ice-l01", 2445 .data = &innolux_g101ice_l01 2446 }, { 2447 .compatible = "innolux,g121i1-l01", 2448 .data = &innolux_g121i1_l01 2449 }, { 2450 .compatible = "innolux,g121x1-l03", 2451 .data = &innolux_g121x1_l03, 2452 }, { 2453 .compatible = "innolux,n116bge", 2454 .data = &innolux_n116bge, 2455 }, { 2456 .compatible = "innolux,n156bge-l21", 2457 .data = &innolux_n156bge_l21, 2458 }, { 2459 .compatible = "innolux,p120zdg-bf1", 2460 .data = &innolux_p120zdg_bf1, 2461 }, { 2462 .compatible = "innolux,zj070na-01p", 2463 .data = &innolux_zj070na_01p, 2464 }, { 2465 .compatible = "koe,tx31d200vm0baa", 2466 .data = &koe_tx31d200vm0baa, 2467 }, { 2468 .compatible = "kyo,tcg121xglp", 2469 .data = &kyo_tcg121xglp, 2470 }, { 2471 .compatible = "lg,lb070wv8", 2472 .data = &lg_lb070wv8, 2473 }, { 2474 .compatible = "lg,lp079qx1-sp0v", 2475 .data = &lg_lp079qx1_sp0v, 2476 }, { 2477 .compatible = "lg,lp097qx1-spa1", 2478 .data = &lg_lp097qx1_spa1, 2479 }, { 2480 .compatible = "lg,lp120up1", 2481 .data = &lg_lp120up1, 2482 }, { 2483 .compatible = "lg,lp129qe", 2484 .data = &lg_lp129qe, 2485 }, { 2486 .compatible = "mitsubishi,aa070mc01-ca1", 2487 .data = &mitsubishi_aa070mc01, 2488 }, { 2489 .compatible = "nec,nl12880bc20-05", 2490 .data = &nec_nl12880bc20_05, 2491 }, { 2492 .compatible = "nec,nl4827hc19-05b", 2493 .data = &nec_nl4827hc19_05b, 2494 }, { 2495 .compatible = "netron-dy,e231732", 2496 .data = &netron_dy_e231732, 2497 }, { 2498 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 2499 .data = &newhaven_nhd_43_480272ef_atxl, 2500 }, { 2501 .compatible = "nlt,nl192108ac18-02d", 2502 .data = &nlt_nl192108ac18_02d, 2503 }, { 2504 .compatible = "nvd,9128", 2505 .data = &nvd_9128, 2506 }, { 2507 .compatible = "okaya,rs800480t-7x0gp", 2508 .data = &okaya_rs800480t_7x0gp, 2509 }, { 2510 .compatible = "olimex,lcd-olinuxino-43-ts", 2511 .data = &olimex_lcd_olinuxino_43ts, 2512 }, { 2513 .compatible = "ontat,yx700wv03", 2514 .data = &ontat_yx700wv03, 2515 }, { 2516 .compatible = "ortustech,com43h4m85ulc", 2517 .data = &ortustech_com43h4m85ulc, 2518 }, { 2519 .compatible = "qiaodian,qd43003c0-40", 2520 .data = &qd43003c0_40, 2521 }, { 2522 .compatible = "rocktech,rk070er9427", 2523 .data = &rocktech_rk070er9427, 2524 }, { 2525 .compatible = "samsung,lsn122dl01-c01", 2526 .data = &samsung_lsn122dl01_c01, 2527 }, { 2528 .compatible = "samsung,ltn101nt05", 2529 .data = &samsung_ltn101nt05, 2530 }, { 2531 .compatible = "samsung,ltn140at29-301", 2532 .data = &samsung_ltn140at29_301, 2533 }, { 2534 .compatible = "sharp,lq035q7db03", 2535 .data = &sharp_lq035q7db03, 2536 }, { 2537 .compatible = "sharp,lq101k1ly04", 2538 .data = &sharp_lq101k1ly04, 2539 }, { 2540 .compatible = "sharp,lq123p1jx31", 2541 .data = &sharp_lq123p1jx31, 2542 }, { 2543 .compatible = "sharp,lq150x1lg11", 2544 .data = &sharp_lq150x1lg11, 2545 }, { 2546 .compatible = "shelly,sca07010-bfn-lnn", 2547 .data = &shelly_sca07010_bfn_lnn, 2548 }, { 2549 .compatible = "starry,kr122ea0sra", 2550 .data = &starry_kr122ea0sra, 2551 }, { 2552 .compatible = "tianma,tm070jdhg30", 2553 .data = &tianma_tm070jdhg30, 2554 }, { 2555 .compatible = "tianma,tm070rvhg71", 2556 .data = &tianma_tm070rvhg71, 2557 }, { 2558 .compatible = "toshiba,lt089ac29000", 2559 .data = &toshiba_lt089ac29000, 2560 }, { 2561 .compatible = "tpk,f07a-0102", 2562 .data = &tpk_f07a_0102, 2563 }, { 2564 .compatible = "tpk,f10a-0102", 2565 .data = &tpk_f10a_0102, 2566 }, { 2567 .compatible = "urt,umsh-8596md-t", 2568 .data = &urt_umsh_8596md_parallel, 2569 }, { 2570 .compatible = "urt,umsh-8596md-1t", 2571 .data = &urt_umsh_8596md_parallel, 2572 }, { 2573 .compatible = "urt,umsh-8596md-7t", 2574 .data = &urt_umsh_8596md_parallel, 2575 }, { 2576 .compatible = "urt,umsh-8596md-11t", 2577 .data = &urt_umsh_8596md_lvds, 2578 }, { 2579 .compatible = "urt,umsh-8596md-19t", 2580 .data = &urt_umsh_8596md_lvds, 2581 }, { 2582 .compatible = "urt,umsh-8596md-20t", 2583 .data = &urt_umsh_8596md_parallel, 2584 }, { 2585 .compatible = "winstar,wf35ltiacd", 2586 .data = &winstar_wf35ltiacd, 2587 }, { 2588 /* sentinel */ 2589 } 2590 }; 2591 MODULE_DEVICE_TABLE(of, platform_of_match); 2592 2593 static int panel_simple_platform_probe(struct platform_device *pdev) 2594 { 2595 const struct of_device_id *id; 2596 2597 id = of_match_node(platform_of_match, pdev->dev.of_node); 2598 if (!id) 2599 return -ENODEV; 2600 2601 return panel_simple_probe(&pdev->dev, id->data); 2602 } 2603 2604 static int panel_simple_platform_remove(struct platform_device *pdev) 2605 { 2606 return panel_simple_remove(&pdev->dev); 2607 } 2608 2609 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2610 { 2611 panel_simple_shutdown(&pdev->dev); 2612 } 2613 2614 static struct platform_driver panel_simple_platform_driver = { 2615 .driver = { 2616 .name = "panel-simple", 2617 .of_match_table = platform_of_match, 2618 }, 2619 .probe = panel_simple_platform_probe, 2620 .remove = panel_simple_platform_remove, 2621 .shutdown = panel_simple_platform_shutdown, 2622 }; 2623 2624 struct panel_desc_dsi { 2625 struct panel_desc desc; 2626 2627 unsigned long flags; 2628 enum mipi_dsi_pixel_format format; 2629 unsigned int lanes; 2630 }; 2631 2632 static const struct drm_display_mode auo_b080uan01_mode = { 2633 .clock = 154500, 2634 .hdisplay = 1200, 2635 .hsync_start = 1200 + 62, 2636 .hsync_end = 1200 + 62 + 4, 2637 .htotal = 1200 + 62 + 4 + 62, 2638 .vdisplay = 1920, 2639 .vsync_start = 1920 + 9, 2640 .vsync_end = 1920 + 9 + 2, 2641 .vtotal = 1920 + 9 + 2 + 8, 2642 .vrefresh = 60, 2643 }; 2644 2645 static const struct panel_desc_dsi auo_b080uan01 = { 2646 .desc = { 2647 .modes = &auo_b080uan01_mode, 2648 .num_modes = 1, 2649 .bpc = 8, 2650 .size = { 2651 .width = 108, 2652 .height = 272, 2653 }, 2654 }, 2655 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2656 .format = MIPI_DSI_FMT_RGB888, 2657 .lanes = 4, 2658 }; 2659 2660 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2661 .clock = 160000, 2662 .hdisplay = 1200, 2663 .hsync_start = 1200 + 120, 2664 .hsync_end = 1200 + 120 + 20, 2665 .htotal = 1200 + 120 + 20 + 21, 2666 .vdisplay = 1920, 2667 .vsync_start = 1920 + 21, 2668 .vsync_end = 1920 + 21 + 3, 2669 .vtotal = 1920 + 21 + 3 + 18, 2670 .vrefresh = 60, 2671 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2672 }; 2673 2674 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2675 .desc = { 2676 .modes = &boe_tv080wum_nl0_mode, 2677 .num_modes = 1, 2678 .size = { 2679 .width = 107, 2680 .height = 172, 2681 }, 2682 }, 2683 .flags = MIPI_DSI_MODE_VIDEO | 2684 MIPI_DSI_MODE_VIDEO_BURST | 2685 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2686 .format = MIPI_DSI_FMT_RGB888, 2687 .lanes = 4, 2688 }; 2689 2690 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2691 .clock = 71000, 2692 .hdisplay = 800, 2693 .hsync_start = 800 + 32, 2694 .hsync_end = 800 + 32 + 1, 2695 .htotal = 800 + 32 + 1 + 57, 2696 .vdisplay = 1280, 2697 .vsync_start = 1280 + 28, 2698 .vsync_end = 1280 + 28 + 1, 2699 .vtotal = 1280 + 28 + 1 + 14, 2700 .vrefresh = 60, 2701 }; 2702 2703 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2704 .desc = { 2705 .modes = &lg_ld070wx3_sl01_mode, 2706 .num_modes = 1, 2707 .bpc = 8, 2708 .size = { 2709 .width = 94, 2710 .height = 151, 2711 }, 2712 }, 2713 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2714 .format = MIPI_DSI_FMT_RGB888, 2715 .lanes = 4, 2716 }; 2717 2718 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2719 .clock = 67000, 2720 .hdisplay = 720, 2721 .hsync_start = 720 + 12, 2722 .hsync_end = 720 + 12 + 4, 2723 .htotal = 720 + 12 + 4 + 112, 2724 .vdisplay = 1280, 2725 .vsync_start = 1280 + 8, 2726 .vsync_end = 1280 + 8 + 4, 2727 .vtotal = 1280 + 8 + 4 + 12, 2728 .vrefresh = 60, 2729 }; 2730 2731 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2732 .desc = { 2733 .modes = &lg_lh500wx1_sd03_mode, 2734 .num_modes = 1, 2735 .bpc = 8, 2736 .size = { 2737 .width = 62, 2738 .height = 110, 2739 }, 2740 }, 2741 .flags = MIPI_DSI_MODE_VIDEO, 2742 .format = MIPI_DSI_FMT_RGB888, 2743 .lanes = 4, 2744 }; 2745 2746 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2747 .clock = 157200, 2748 .hdisplay = 1920, 2749 .hsync_start = 1920 + 154, 2750 .hsync_end = 1920 + 154 + 16, 2751 .htotal = 1920 + 154 + 16 + 32, 2752 .vdisplay = 1200, 2753 .vsync_start = 1200 + 17, 2754 .vsync_end = 1200 + 17 + 2, 2755 .vtotal = 1200 + 17 + 2 + 16, 2756 .vrefresh = 60, 2757 }; 2758 2759 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2760 .desc = { 2761 .modes = &panasonic_vvx10f004b00_mode, 2762 .num_modes = 1, 2763 .bpc = 8, 2764 .size = { 2765 .width = 217, 2766 .height = 136, 2767 }, 2768 }, 2769 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2770 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2771 .format = MIPI_DSI_FMT_RGB888, 2772 .lanes = 4, 2773 }; 2774 2775 static const struct of_device_id dsi_of_match[] = { 2776 { 2777 .compatible = "auo,b080uan01", 2778 .data = &auo_b080uan01 2779 }, { 2780 .compatible = "boe,tv080wum-nl0", 2781 .data = &boe_tv080wum_nl0 2782 }, { 2783 .compatible = "lg,ld070wx3-sl01", 2784 .data = &lg_ld070wx3_sl01 2785 }, { 2786 .compatible = "lg,lh500wx1-sd03", 2787 .data = &lg_lh500wx1_sd03 2788 }, { 2789 .compatible = "panasonic,vvx10f004b00", 2790 .data = &panasonic_vvx10f004b00 2791 }, { 2792 /* sentinel */ 2793 } 2794 }; 2795 MODULE_DEVICE_TABLE(of, dsi_of_match); 2796 2797 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2798 { 2799 const struct panel_desc_dsi *desc; 2800 const struct of_device_id *id; 2801 int err; 2802 2803 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2804 if (!id) 2805 return -ENODEV; 2806 2807 desc = id->data; 2808 2809 err = panel_simple_probe(&dsi->dev, &desc->desc); 2810 if (err < 0) 2811 return err; 2812 2813 dsi->mode_flags = desc->flags; 2814 dsi->format = desc->format; 2815 dsi->lanes = desc->lanes; 2816 2817 return mipi_dsi_attach(dsi); 2818 } 2819 2820 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2821 { 2822 int err; 2823 2824 err = mipi_dsi_detach(dsi); 2825 if (err < 0) 2826 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2827 2828 return panel_simple_remove(&dsi->dev); 2829 } 2830 2831 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2832 { 2833 panel_simple_shutdown(&dsi->dev); 2834 } 2835 2836 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2837 .driver = { 2838 .name = "panel-simple-dsi", 2839 .of_match_table = dsi_of_match, 2840 }, 2841 .probe = panel_simple_dsi_probe, 2842 .remove = panel_simple_dsi_remove, 2843 .shutdown = panel_simple_dsi_shutdown, 2844 }; 2845 2846 static int __init panel_simple_init(void) 2847 { 2848 int err; 2849 2850 err = platform_driver_register(&panel_simple_platform_driver); 2851 if (err < 0) 2852 return err; 2853 2854 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2855 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2856 if (err < 0) 2857 return err; 2858 } 2859 2860 return 0; 2861 } 2862 module_init(panel_simple_init); 2863 2864 static void __exit panel_simple_exit(void) 2865 { 2866 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2867 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2868 2869 platform_driver_unregister(&panel_simple_platform_driver); 2870 } 2871 module_exit(panel_simple_exit); 2872 2873 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2874 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2875 MODULE_LICENSE("GPL and additional rights"); 2876