1 /*
2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the
12  * next paragraph) shall be included in all copies or substantial portions
13  * of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31 
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35 
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40 
41 /**
42  * struct panel_desc - Describes a simple panel.
43  */
44 struct panel_desc {
45 	/**
46 	 * @modes: Pointer to array of fixed modes appropriate for this panel.
47 	 *
48 	 * If only one mode then this can just be the address of the mode.
49 	 * NOTE: cannot be used with "timings" and also if this is specified
50 	 * then you cannot override the mode in the device tree.
51 	 */
52 	const struct drm_display_mode *modes;
53 
54 	/** @num_modes: Number of elements in modes array. */
55 	unsigned int num_modes;
56 
57 	/**
58 	 * @timings: Pointer to array of display timings
59 	 *
60 	 * NOTE: cannot be used with "modes" and also these will be used to
61 	 * validate a device tree override if one is present.
62 	 */
63 	const struct display_timing *timings;
64 
65 	/** @num_timings: Number of elements in timings array. */
66 	unsigned int num_timings;
67 
68 	/** @bpc: Bits per color. */
69 	unsigned int bpc;
70 
71 	/** @size: Structure containing the physical size of this panel. */
72 	struct {
73 		/**
74 		 * @size.width: Width (in mm) of the active display area.
75 		 */
76 		unsigned int width;
77 
78 		/**
79 		 * @size.height: Height (in mm) of the active display area.
80 		 */
81 		unsigned int height;
82 	} size;
83 
84 	/** @delay: Structure containing various delay values for this panel. */
85 	struct {
86 		/**
87 		 * @delay.prepare: Time for the panel to become ready.
88 		 *
89 		 * The time (in milliseconds) that it takes for the panel to
90 		 * become ready and start receiving video data
91 		 */
92 		unsigned int prepare;
93 
94 		/**
95 		 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up.
96 		 *
97 		 * Add this to the prepare delay if we know Hot Plug Detect
98 		 * isn't used.
99 		 */
100 		unsigned int hpd_absent_delay;
101 
102 		/**
103 		 * @delay.prepare_to_enable: Time between prepare and enable.
104 		 *
105 		 * The minimum time, in milliseconds, that needs to have passed
106 		 * between when prepare finished and enable may begin. If at
107 		 * enable time less time has passed since prepare finished,
108 		 * the driver waits for the remaining time.
109 		 *
110 		 * If a fixed enable delay is also specified, we'll start
111 		 * counting before delaying for the fixed delay.
112 		 *
113 		 * If a fixed prepare delay is also specified, we won't start
114 		 * counting until after the fixed delay. We can't overlap this
115 		 * fixed delay with the min time because the fixed delay
116 		 * doesn't happen at the end of the function if a HPD GPIO was
117 		 * specified.
118 		 *
119 		 * In other words:
120 		 *   prepare()
121 		 *     ...
122 		 *     // do fixed prepare delay
123 		 *     // wait for HPD GPIO if applicable
124 		 *     // start counting for prepare_to_enable
125 		 *
126 		 *   enable()
127 		 *     // do fixed enable delay
128 		 *     // enforce prepare_to_enable min time
129 		 */
130 		unsigned int prepare_to_enable;
131 
132 		/**
133 		 * @delay.enable: Time for the panel to display a valid frame.
134 		 *
135 		 * The time (in milliseconds) that it takes for the panel to
136 		 * display the first valid frame after starting to receive
137 		 * video data.
138 		 */
139 		unsigned int enable;
140 
141 		/**
142 		 * @delay.disable: Time for the panel to turn the display off.
143 		 *
144 		 * The time (in milliseconds) that it takes for the panel to
145 		 * turn the display off (no content is visible).
146 		 */
147 		unsigned int disable;
148 
149 		/**
150 		 * @delay.unprepare: Time to power down completely.
151 		 *
152 		 * The time (in milliseconds) that it takes for the panel
153 		 * to power itself down completely.
154 		 *
155 		 * This time is used to prevent a future "prepare" from
156 		 * starting until at least this many milliseconds has passed.
157 		 * If at prepare time less time has passed since unprepare
158 		 * finished, the driver waits for the remaining time.
159 		 */
160 		unsigned int unprepare;
161 	} delay;
162 
163 	/** @bus_format: See MEDIA_BUS_FMT_... defines. */
164 	u32 bus_format;
165 
166 	/** @bus_flags: See DRM_BUS_FLAG_... defines. */
167 	u32 bus_flags;
168 
169 	/** @connector_type: LVDS, eDP, DSI, DPI, etc. */
170 	int connector_type;
171 };
172 
173 struct panel_simple {
174 	struct drm_panel base;
175 	bool enabled;
176 	bool no_hpd;
177 
178 	ktime_t prepared_time;
179 	ktime_t unprepared_time;
180 
181 	const struct panel_desc *desc;
182 
183 	struct regulator *supply;
184 	struct i2c_adapter *ddc;
185 
186 	struct gpio_desc *enable_gpio;
187 	struct gpio_desc *hpd_gpio;
188 
189 	struct drm_display_mode override_mode;
190 
191 	enum drm_panel_orientation orientation;
192 };
193 
194 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
195 {
196 	return container_of(panel, struct panel_simple, base);
197 }
198 
199 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
200 						   struct drm_connector *connector)
201 {
202 	struct drm_display_mode *mode;
203 	unsigned int i, num = 0;
204 
205 	for (i = 0; i < panel->desc->num_timings; i++) {
206 		const struct display_timing *dt = &panel->desc->timings[i];
207 		struct videomode vm;
208 
209 		videomode_from_timing(dt, &vm);
210 		mode = drm_mode_create(connector->dev);
211 		if (!mode) {
212 			dev_err(panel->base.dev, "failed to add mode %ux%u\n",
213 				dt->hactive.typ, dt->vactive.typ);
214 			continue;
215 		}
216 
217 		drm_display_mode_from_videomode(&vm, mode);
218 
219 		mode->type |= DRM_MODE_TYPE_DRIVER;
220 
221 		if (panel->desc->num_timings == 1)
222 			mode->type |= DRM_MODE_TYPE_PREFERRED;
223 
224 		drm_mode_probed_add(connector, mode);
225 		num++;
226 	}
227 
228 	return num;
229 }
230 
231 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
232 						   struct drm_connector *connector)
233 {
234 	struct drm_display_mode *mode;
235 	unsigned int i, num = 0;
236 
237 	for (i = 0; i < panel->desc->num_modes; i++) {
238 		const struct drm_display_mode *m = &panel->desc->modes[i];
239 
240 		mode = drm_mode_duplicate(connector->dev, m);
241 		if (!mode) {
242 			dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
243 				m->hdisplay, m->vdisplay,
244 				drm_mode_vrefresh(m));
245 			continue;
246 		}
247 
248 		mode->type |= DRM_MODE_TYPE_DRIVER;
249 
250 		if (panel->desc->num_modes == 1)
251 			mode->type |= DRM_MODE_TYPE_PREFERRED;
252 
253 		drm_mode_set_name(mode);
254 
255 		drm_mode_probed_add(connector, mode);
256 		num++;
257 	}
258 
259 	return num;
260 }
261 
262 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
263 					   struct drm_connector *connector)
264 {
265 	struct drm_display_mode *mode;
266 	bool has_override = panel->override_mode.type;
267 	unsigned int num = 0;
268 
269 	if (!panel->desc)
270 		return 0;
271 
272 	if (has_override) {
273 		mode = drm_mode_duplicate(connector->dev,
274 					  &panel->override_mode);
275 		if (mode) {
276 			drm_mode_probed_add(connector, mode);
277 			num = 1;
278 		} else {
279 			dev_err(panel->base.dev, "failed to add override mode\n");
280 		}
281 	}
282 
283 	/* Only add timings if override was not there or failed to validate */
284 	if (num == 0 && panel->desc->num_timings)
285 		num = panel_simple_get_timings_modes(panel, connector);
286 
287 	/*
288 	 * Only add fixed modes if timings/override added no mode.
289 	 *
290 	 * We should only ever have either the display timings specified
291 	 * or a fixed mode. Anything else is rather bogus.
292 	 */
293 	WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
294 	if (num == 0)
295 		num = panel_simple_get_display_modes(panel, connector);
296 
297 	connector->display_info.bpc = panel->desc->bpc;
298 	connector->display_info.width_mm = panel->desc->size.width;
299 	connector->display_info.height_mm = panel->desc->size.height;
300 	if (panel->desc->bus_format)
301 		drm_display_info_set_bus_formats(&connector->display_info,
302 						 &panel->desc->bus_format, 1);
303 	connector->display_info.bus_flags = panel->desc->bus_flags;
304 
305 	return num;
306 }
307 
308 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
309 {
310 	ktime_t now_ktime, min_ktime;
311 
312 	if (!min_ms)
313 		return;
314 
315 	min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
316 	now_ktime = ktime_get();
317 
318 	if (ktime_before(now_ktime, min_ktime))
319 		msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
320 }
321 
322 static int panel_simple_disable(struct drm_panel *panel)
323 {
324 	struct panel_simple *p = to_panel_simple(panel);
325 
326 	if (!p->enabled)
327 		return 0;
328 
329 	if (p->desc->delay.disable)
330 		msleep(p->desc->delay.disable);
331 
332 	p->enabled = false;
333 
334 	return 0;
335 }
336 
337 static int panel_simple_unprepare(struct drm_panel *panel)
338 {
339 	struct panel_simple *p = to_panel_simple(panel);
340 
341 	if (p->prepared_time == 0)
342 		return 0;
343 
344 	gpiod_set_value_cansleep(p->enable_gpio, 0);
345 
346 	regulator_disable(p->supply);
347 
348 	p->prepared_time = 0;
349 	p->unprepared_time = ktime_get();
350 
351 	return 0;
352 }
353 
354 static int panel_simple_get_hpd_gpio(struct device *dev,
355 				     struct panel_simple *p, bool from_probe)
356 {
357 	int err;
358 
359 	p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
360 	if (IS_ERR(p->hpd_gpio)) {
361 		err = PTR_ERR(p->hpd_gpio);
362 
363 		/*
364 		 * If we're called from probe we won't consider '-EPROBE_DEFER'
365 		 * to be an error--we'll leave the error code in "hpd_gpio".
366 		 * When we try to use it we'll try again.  This allows for
367 		 * circular dependencies where the component providing the
368 		 * hpd gpio needs the panel to init before probing.
369 		 */
370 		if (err != -EPROBE_DEFER || !from_probe) {
371 			dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
372 			return err;
373 		}
374 	}
375 
376 	return 0;
377 }
378 
379 static int panel_simple_prepare(struct drm_panel *panel)
380 {
381 	struct panel_simple *p = to_panel_simple(panel);
382 	unsigned int delay;
383 	int err;
384 	int hpd_asserted;
385 
386 	if (p->prepared_time != 0)
387 		return 0;
388 
389 	panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
390 
391 	err = regulator_enable(p->supply);
392 	if (err < 0) {
393 		dev_err(panel->dev, "failed to enable supply: %d\n", err);
394 		return err;
395 	}
396 
397 	gpiod_set_value_cansleep(p->enable_gpio, 1);
398 
399 	delay = p->desc->delay.prepare;
400 	if (p->no_hpd)
401 		delay += p->desc->delay.hpd_absent_delay;
402 	if (delay)
403 		msleep(delay);
404 
405 	if (p->hpd_gpio) {
406 		if (IS_ERR(p->hpd_gpio)) {
407 			err = panel_simple_get_hpd_gpio(panel->dev, p, false);
408 			if (err)
409 				return err;
410 		}
411 
412 		err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
413 					 hpd_asserted, hpd_asserted,
414 					 1000, 2000000);
415 		if (hpd_asserted < 0)
416 			err = hpd_asserted;
417 
418 		if (err) {
419 			dev_err(panel->dev,
420 				"error waiting for hpd GPIO: %d\n", err);
421 			return err;
422 		}
423 	}
424 
425 	p->prepared_time = ktime_get();
426 
427 	return 0;
428 }
429 
430 static int panel_simple_enable(struct drm_panel *panel)
431 {
432 	struct panel_simple *p = to_panel_simple(panel);
433 
434 	if (p->enabled)
435 		return 0;
436 
437 	if (p->desc->delay.enable)
438 		msleep(p->desc->delay.enable);
439 
440 	panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable);
441 
442 	p->enabled = true;
443 
444 	return 0;
445 }
446 
447 static int panel_simple_get_modes(struct drm_panel *panel,
448 				  struct drm_connector *connector)
449 {
450 	struct panel_simple *p = to_panel_simple(panel);
451 	int num = 0;
452 
453 	/* probe EDID if a DDC bus is available */
454 	if (p->ddc) {
455 		struct edid *edid = drm_get_edid(connector, p->ddc);
456 
457 		drm_connector_update_edid_property(connector, edid);
458 		if (edid) {
459 			num += drm_add_edid_modes(connector, edid);
460 			kfree(edid);
461 		}
462 	}
463 
464 	/* add hard-coded panel modes */
465 	num += panel_simple_get_non_edid_modes(p, connector);
466 
467 	/* set up connector's "panel orientation" property */
468 	drm_connector_set_panel_orientation(connector, p->orientation);
469 
470 	return num;
471 }
472 
473 static int panel_simple_get_timings(struct drm_panel *panel,
474 				    unsigned int num_timings,
475 				    struct display_timing *timings)
476 {
477 	struct panel_simple *p = to_panel_simple(panel);
478 	unsigned int i;
479 
480 	if (p->desc->num_timings < num_timings)
481 		num_timings = p->desc->num_timings;
482 
483 	if (timings)
484 		for (i = 0; i < num_timings; i++)
485 			timings[i] = p->desc->timings[i];
486 
487 	return p->desc->num_timings;
488 }
489 
490 static const struct drm_panel_funcs panel_simple_funcs = {
491 	.disable = panel_simple_disable,
492 	.unprepare = panel_simple_unprepare,
493 	.prepare = panel_simple_prepare,
494 	.enable = panel_simple_enable,
495 	.get_modes = panel_simple_get_modes,
496 	.get_timings = panel_simple_get_timings,
497 };
498 
499 static struct panel_desc panel_dpi;
500 
501 static int panel_dpi_probe(struct device *dev,
502 			   struct panel_simple *panel)
503 {
504 	struct display_timing *timing;
505 	const struct device_node *np;
506 	struct panel_desc *desc;
507 	unsigned int bus_flags;
508 	struct videomode vm;
509 	int ret;
510 
511 	np = dev->of_node;
512 	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
513 	if (!desc)
514 		return -ENOMEM;
515 
516 	timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
517 	if (!timing)
518 		return -ENOMEM;
519 
520 	ret = of_get_display_timing(np, "panel-timing", timing);
521 	if (ret < 0) {
522 		dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
523 			np);
524 		return ret;
525 	}
526 
527 	desc->timings = timing;
528 	desc->num_timings = 1;
529 
530 	of_property_read_u32(np, "width-mm", &desc->size.width);
531 	of_property_read_u32(np, "height-mm", &desc->size.height);
532 
533 	/* Extract bus_flags from display_timing */
534 	bus_flags = 0;
535 	vm.flags = timing->flags;
536 	drm_bus_flags_from_videomode(&vm, &bus_flags);
537 	desc->bus_flags = bus_flags;
538 
539 	/* We do not know the connector for the DT node, so guess it */
540 	desc->connector_type = DRM_MODE_CONNECTOR_DPI;
541 
542 	panel->desc = desc;
543 
544 	return 0;
545 }
546 
547 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
548 	(to_check->field.typ >= bounds->field.min && \
549 	 to_check->field.typ <= bounds->field.max)
550 static void panel_simple_parse_panel_timing_node(struct device *dev,
551 						 struct panel_simple *panel,
552 						 const struct display_timing *ot)
553 {
554 	const struct panel_desc *desc = panel->desc;
555 	struct videomode vm;
556 	unsigned int i;
557 
558 	if (WARN_ON(desc->num_modes)) {
559 		dev_err(dev, "Reject override mode: panel has a fixed mode\n");
560 		return;
561 	}
562 	if (WARN_ON(!desc->num_timings)) {
563 		dev_err(dev, "Reject override mode: no timings specified\n");
564 		return;
565 	}
566 
567 	for (i = 0; i < panel->desc->num_timings; i++) {
568 		const struct display_timing *dt = &panel->desc->timings[i];
569 
570 		if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
571 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
572 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
573 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
574 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
575 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
576 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
577 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
578 			continue;
579 
580 		if (ot->flags != dt->flags)
581 			continue;
582 
583 		videomode_from_timing(ot, &vm);
584 		drm_display_mode_from_videomode(&vm, &panel->override_mode);
585 		panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
586 					     DRM_MODE_TYPE_PREFERRED;
587 		break;
588 	}
589 
590 	if (WARN_ON(!panel->override_mode.type))
591 		dev_err(dev, "Reject override mode: No display_timing found\n");
592 }
593 
594 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
595 {
596 	struct panel_simple *panel;
597 	struct display_timing dt;
598 	struct device_node *ddc;
599 	int connector_type;
600 	u32 bus_flags;
601 	int err;
602 
603 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
604 	if (!panel)
605 		return -ENOMEM;
606 
607 	panel->enabled = false;
608 	panel->prepared_time = 0;
609 	panel->desc = desc;
610 
611 	panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
612 	if (!panel->no_hpd) {
613 		err = panel_simple_get_hpd_gpio(dev, panel, true);
614 		if (err)
615 			return err;
616 	}
617 
618 	panel->supply = devm_regulator_get(dev, "power");
619 	if (IS_ERR(panel->supply))
620 		return PTR_ERR(panel->supply);
621 
622 	panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
623 						     GPIOD_OUT_LOW);
624 	if (IS_ERR(panel->enable_gpio)) {
625 		err = PTR_ERR(panel->enable_gpio);
626 		if (err != -EPROBE_DEFER)
627 			dev_err(dev, "failed to request GPIO: %d\n", err);
628 		return err;
629 	}
630 
631 	err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
632 	if (err) {
633 		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
634 		return err;
635 	}
636 
637 	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
638 	if (ddc) {
639 		panel->ddc = of_find_i2c_adapter_by_node(ddc);
640 		of_node_put(ddc);
641 
642 		if (!panel->ddc)
643 			return -EPROBE_DEFER;
644 	}
645 
646 	if (desc == &panel_dpi) {
647 		/* Handle the generic panel-dpi binding */
648 		err = panel_dpi_probe(dev, panel);
649 		if (err)
650 			goto free_ddc;
651 	} else {
652 		if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
653 			panel_simple_parse_panel_timing_node(dev, panel, &dt);
654 	}
655 
656 	connector_type = desc->connector_type;
657 	/* Catch common mistakes for panels. */
658 	switch (connector_type) {
659 	case 0:
660 		dev_warn(dev, "Specify missing connector_type\n");
661 		connector_type = DRM_MODE_CONNECTOR_DPI;
662 		break;
663 	case DRM_MODE_CONNECTOR_LVDS:
664 		WARN_ON(desc->bus_flags &
665 			~(DRM_BUS_FLAG_DE_LOW |
666 			  DRM_BUS_FLAG_DE_HIGH |
667 			  DRM_BUS_FLAG_DATA_MSB_TO_LSB |
668 			  DRM_BUS_FLAG_DATA_LSB_TO_MSB));
669 		WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
670 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
671 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
672 		WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
673 			desc->bpc != 6);
674 		WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
675 			 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
676 			desc->bpc != 8);
677 		break;
678 	case DRM_MODE_CONNECTOR_eDP:
679 		if (desc->bus_format == 0)
680 			dev_warn(dev, "Specify missing bus_format\n");
681 		if (desc->bpc != 6 && desc->bpc != 8)
682 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
683 		break;
684 	case DRM_MODE_CONNECTOR_DSI:
685 		if (desc->bpc != 6 && desc->bpc != 8)
686 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
687 		break;
688 	case DRM_MODE_CONNECTOR_DPI:
689 		bus_flags = DRM_BUS_FLAG_DE_LOW |
690 			    DRM_BUS_FLAG_DE_HIGH |
691 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
692 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
693 			    DRM_BUS_FLAG_DATA_MSB_TO_LSB |
694 			    DRM_BUS_FLAG_DATA_LSB_TO_MSB |
695 			    DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
696 			    DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
697 		if (desc->bus_flags & ~bus_flags)
698 			dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
699 		if (!(desc->bus_flags & bus_flags))
700 			dev_warn(dev, "Specify missing bus_flags\n");
701 		if (desc->bus_format == 0)
702 			dev_warn(dev, "Specify missing bus_format\n");
703 		if (desc->bpc != 6 && desc->bpc != 8)
704 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
705 		break;
706 	default:
707 		dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
708 		connector_type = DRM_MODE_CONNECTOR_DPI;
709 		break;
710 	}
711 
712 	drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
713 
714 	err = drm_panel_of_backlight(&panel->base);
715 	if (err)
716 		goto free_ddc;
717 
718 	drm_panel_add(&panel->base);
719 
720 	dev_set_drvdata(dev, panel);
721 
722 	return 0;
723 
724 free_ddc:
725 	if (panel->ddc)
726 		put_device(&panel->ddc->dev);
727 
728 	return err;
729 }
730 
731 static int panel_simple_remove(struct device *dev)
732 {
733 	struct panel_simple *panel = dev_get_drvdata(dev);
734 
735 	drm_panel_remove(&panel->base);
736 	drm_panel_disable(&panel->base);
737 	drm_panel_unprepare(&panel->base);
738 
739 	if (panel->ddc)
740 		put_device(&panel->ddc->dev);
741 
742 	return 0;
743 }
744 
745 static void panel_simple_shutdown(struct device *dev)
746 {
747 	struct panel_simple *panel = dev_get_drvdata(dev);
748 
749 	drm_panel_disable(&panel->base);
750 	drm_panel_unprepare(&panel->base);
751 }
752 
753 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
754 	.clock = 71100,
755 	.hdisplay = 1280,
756 	.hsync_start = 1280 + 40,
757 	.hsync_end = 1280 + 40 + 80,
758 	.htotal = 1280 + 40 + 80 + 40,
759 	.vdisplay = 800,
760 	.vsync_start = 800 + 3,
761 	.vsync_end = 800 + 3 + 10,
762 	.vtotal = 800 + 3 + 10 + 10,
763 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
764 };
765 
766 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
767 	.modes = &ampire_am_1280800n3tzqw_t00h_mode,
768 	.num_modes = 1,
769 	.bpc = 6,
770 	.size = {
771 		.width = 217,
772 		.height = 136,
773 	},
774 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
775 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
776 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
777 };
778 
779 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
780 	.clock = 9000,
781 	.hdisplay = 480,
782 	.hsync_start = 480 + 2,
783 	.hsync_end = 480 + 2 + 41,
784 	.htotal = 480 + 2 + 41 + 2,
785 	.vdisplay = 272,
786 	.vsync_start = 272 + 2,
787 	.vsync_end = 272 + 2 + 10,
788 	.vtotal = 272 + 2 + 10 + 2,
789 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
790 };
791 
792 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
793 	.modes = &ampire_am_480272h3tmqw_t01h_mode,
794 	.num_modes = 1,
795 	.bpc = 8,
796 	.size = {
797 		.width = 105,
798 		.height = 67,
799 	},
800 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
801 };
802 
803 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
804 	.clock = 33333,
805 	.hdisplay = 800,
806 	.hsync_start = 800 + 0,
807 	.hsync_end = 800 + 0 + 255,
808 	.htotal = 800 + 0 + 255 + 0,
809 	.vdisplay = 480,
810 	.vsync_start = 480 + 2,
811 	.vsync_end = 480 + 2 + 45,
812 	.vtotal = 480 + 2 + 45 + 0,
813 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
814 };
815 
816 static const struct panel_desc ampire_am800480r3tmqwa1h = {
817 	.modes = &ampire_am800480r3tmqwa1h_mode,
818 	.num_modes = 1,
819 	.bpc = 6,
820 	.size = {
821 		.width = 152,
822 		.height = 91,
823 	},
824 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
825 };
826 
827 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
828 	.pixelclock = { 26400000, 33300000, 46800000 },
829 	.hactive = { 800, 800, 800 },
830 	.hfront_porch = { 16, 210, 354 },
831 	.hback_porch = { 45, 36, 6 },
832 	.hsync_len = { 1, 10, 40 },
833 	.vactive = { 480, 480, 480 },
834 	.vfront_porch = { 7, 22, 147 },
835 	.vback_porch = { 22, 13, 3 },
836 	.vsync_len = { 1, 10, 20 },
837 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
838 		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
839 };
840 
841 static const struct panel_desc armadeus_st0700_adapt = {
842 	.timings = &santek_st0700i5y_rbslw_f_timing,
843 	.num_timings = 1,
844 	.bpc = 6,
845 	.size = {
846 		.width = 154,
847 		.height = 86,
848 	},
849 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
850 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
851 };
852 
853 static const struct drm_display_mode auo_b101aw03_mode = {
854 	.clock = 51450,
855 	.hdisplay = 1024,
856 	.hsync_start = 1024 + 156,
857 	.hsync_end = 1024 + 156 + 8,
858 	.htotal = 1024 + 156 + 8 + 156,
859 	.vdisplay = 600,
860 	.vsync_start = 600 + 16,
861 	.vsync_end = 600 + 16 + 6,
862 	.vtotal = 600 + 16 + 6 + 16,
863 };
864 
865 static const struct panel_desc auo_b101aw03 = {
866 	.modes = &auo_b101aw03_mode,
867 	.num_modes = 1,
868 	.bpc = 6,
869 	.size = {
870 		.width = 223,
871 		.height = 125,
872 	},
873 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
874 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
875 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
876 };
877 
878 static const struct display_timing auo_b101ean01_timing = {
879 	.pixelclock = { 65300000, 72500000, 75000000 },
880 	.hactive = { 1280, 1280, 1280 },
881 	.hfront_porch = { 18, 119, 119 },
882 	.hback_porch = { 21, 21, 21 },
883 	.hsync_len = { 32, 32, 32 },
884 	.vactive = { 800, 800, 800 },
885 	.vfront_porch = { 4, 4, 4 },
886 	.vback_porch = { 8, 8, 8 },
887 	.vsync_len = { 18, 20, 20 },
888 };
889 
890 static const struct panel_desc auo_b101ean01 = {
891 	.timings = &auo_b101ean01_timing,
892 	.num_timings = 1,
893 	.bpc = 6,
894 	.size = {
895 		.width = 217,
896 		.height = 136,
897 	},
898 };
899 
900 static const struct drm_display_mode auo_b101xtn01_mode = {
901 	.clock = 72000,
902 	.hdisplay = 1366,
903 	.hsync_start = 1366 + 20,
904 	.hsync_end = 1366 + 20 + 70,
905 	.htotal = 1366 + 20 + 70,
906 	.vdisplay = 768,
907 	.vsync_start = 768 + 14,
908 	.vsync_end = 768 + 14 + 42,
909 	.vtotal = 768 + 14 + 42,
910 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
911 };
912 
913 static const struct panel_desc auo_b101xtn01 = {
914 	.modes = &auo_b101xtn01_mode,
915 	.num_modes = 1,
916 	.bpc = 6,
917 	.size = {
918 		.width = 223,
919 		.height = 125,
920 	},
921 };
922 
923 static const struct drm_display_mode auo_b116xak01_mode = {
924 	.clock = 69300,
925 	.hdisplay = 1366,
926 	.hsync_start = 1366 + 48,
927 	.hsync_end = 1366 + 48 + 32,
928 	.htotal = 1366 + 48 + 32 + 10,
929 	.vdisplay = 768,
930 	.vsync_start = 768 + 4,
931 	.vsync_end = 768 + 4 + 6,
932 	.vtotal = 768 + 4 + 6 + 15,
933 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
934 };
935 
936 static const struct panel_desc auo_b116xak01 = {
937 	.modes = &auo_b116xak01_mode,
938 	.num_modes = 1,
939 	.bpc = 6,
940 	.size = {
941 		.width = 256,
942 		.height = 144,
943 	},
944 	.delay = {
945 		.hpd_absent_delay = 200,
946 	},
947 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
948 	.connector_type = DRM_MODE_CONNECTOR_eDP,
949 };
950 
951 static const struct drm_display_mode auo_b116xw03_mode = {
952 	.clock = 70589,
953 	.hdisplay = 1366,
954 	.hsync_start = 1366 + 40,
955 	.hsync_end = 1366 + 40 + 40,
956 	.htotal = 1366 + 40 + 40 + 32,
957 	.vdisplay = 768,
958 	.vsync_start = 768 + 10,
959 	.vsync_end = 768 + 10 + 12,
960 	.vtotal = 768 + 10 + 12 + 6,
961 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
962 };
963 
964 static const struct panel_desc auo_b116xw03 = {
965 	.modes = &auo_b116xw03_mode,
966 	.num_modes = 1,
967 	.bpc = 6,
968 	.size = {
969 		.width = 256,
970 		.height = 144,
971 	},
972 	.delay = {
973 		.enable = 400,
974 	},
975 	.bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
976 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
977 	.connector_type = DRM_MODE_CONNECTOR_eDP,
978 };
979 
980 static const struct drm_display_mode auo_b133xtn01_mode = {
981 	.clock = 69500,
982 	.hdisplay = 1366,
983 	.hsync_start = 1366 + 48,
984 	.hsync_end = 1366 + 48 + 32,
985 	.htotal = 1366 + 48 + 32 + 20,
986 	.vdisplay = 768,
987 	.vsync_start = 768 + 3,
988 	.vsync_end = 768 + 3 + 6,
989 	.vtotal = 768 + 3 + 6 + 13,
990 };
991 
992 static const struct panel_desc auo_b133xtn01 = {
993 	.modes = &auo_b133xtn01_mode,
994 	.num_modes = 1,
995 	.bpc = 6,
996 	.size = {
997 		.width = 293,
998 		.height = 165,
999 	},
1000 };
1001 
1002 static const struct drm_display_mode auo_b133htn01_mode = {
1003 	.clock = 150660,
1004 	.hdisplay = 1920,
1005 	.hsync_start = 1920 + 172,
1006 	.hsync_end = 1920 + 172 + 80,
1007 	.htotal = 1920 + 172 + 80 + 60,
1008 	.vdisplay = 1080,
1009 	.vsync_start = 1080 + 25,
1010 	.vsync_end = 1080 + 25 + 10,
1011 	.vtotal = 1080 + 25 + 10 + 10,
1012 };
1013 
1014 static const struct panel_desc auo_b133htn01 = {
1015 	.modes = &auo_b133htn01_mode,
1016 	.num_modes = 1,
1017 	.bpc = 6,
1018 	.size = {
1019 		.width = 293,
1020 		.height = 165,
1021 	},
1022 	.delay = {
1023 		.prepare = 105,
1024 		.enable = 20,
1025 		.unprepare = 50,
1026 	},
1027 };
1028 
1029 static const struct display_timing auo_g070vvn01_timings = {
1030 	.pixelclock = { 33300000, 34209000, 45000000 },
1031 	.hactive = { 800, 800, 800 },
1032 	.hfront_porch = { 20, 40, 200 },
1033 	.hback_porch = { 87, 40, 1 },
1034 	.hsync_len = { 1, 48, 87 },
1035 	.vactive = { 480, 480, 480 },
1036 	.vfront_porch = { 5, 13, 200 },
1037 	.vback_porch = { 31, 31, 29 },
1038 	.vsync_len = { 1, 1, 3 },
1039 };
1040 
1041 static const struct panel_desc auo_g070vvn01 = {
1042 	.timings = &auo_g070vvn01_timings,
1043 	.num_timings = 1,
1044 	.bpc = 8,
1045 	.size = {
1046 		.width = 152,
1047 		.height = 91,
1048 	},
1049 	.delay = {
1050 		.prepare = 200,
1051 		.enable = 50,
1052 		.disable = 50,
1053 		.unprepare = 1000,
1054 	},
1055 };
1056 
1057 static const struct drm_display_mode auo_g101evn010_mode = {
1058 	.clock = 68930,
1059 	.hdisplay = 1280,
1060 	.hsync_start = 1280 + 82,
1061 	.hsync_end = 1280 + 82 + 2,
1062 	.htotal = 1280 + 82 + 2 + 84,
1063 	.vdisplay = 800,
1064 	.vsync_start = 800 + 8,
1065 	.vsync_end = 800 + 8 + 2,
1066 	.vtotal = 800 + 8 + 2 + 6,
1067 };
1068 
1069 static const struct panel_desc auo_g101evn010 = {
1070 	.modes = &auo_g101evn010_mode,
1071 	.num_modes = 1,
1072 	.bpc = 6,
1073 	.size = {
1074 		.width = 216,
1075 		.height = 135,
1076 	},
1077 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1078 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1079 };
1080 
1081 static const struct drm_display_mode auo_g104sn02_mode = {
1082 	.clock = 40000,
1083 	.hdisplay = 800,
1084 	.hsync_start = 800 + 40,
1085 	.hsync_end = 800 + 40 + 216,
1086 	.htotal = 800 + 40 + 216 + 128,
1087 	.vdisplay = 600,
1088 	.vsync_start = 600 + 10,
1089 	.vsync_end = 600 + 10 + 35,
1090 	.vtotal = 600 + 10 + 35 + 2,
1091 };
1092 
1093 static const struct panel_desc auo_g104sn02 = {
1094 	.modes = &auo_g104sn02_mode,
1095 	.num_modes = 1,
1096 	.bpc = 8,
1097 	.size = {
1098 		.width = 211,
1099 		.height = 158,
1100 	},
1101 };
1102 
1103 static const struct drm_display_mode auo_g121ean01_mode = {
1104 	.clock = 66700,
1105 	.hdisplay = 1280,
1106 	.hsync_start = 1280 + 58,
1107 	.hsync_end = 1280 + 58 + 8,
1108 	.htotal = 1280 + 58 + 8 + 70,
1109 	.vdisplay = 800,
1110 	.vsync_start = 800 + 6,
1111 	.vsync_end = 800 + 6 + 4,
1112 	.vtotal = 800 + 6 + 4 + 10,
1113 };
1114 
1115 static const struct panel_desc auo_g121ean01 = {
1116 	.modes = &auo_g121ean01_mode,
1117 	.num_modes = 1,
1118 	.bpc = 8,
1119 	.size = {
1120 		.width = 261,
1121 		.height = 163,
1122 	},
1123 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1124 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1125 };
1126 
1127 static const struct display_timing auo_g133han01_timings = {
1128 	.pixelclock = { 134000000, 141200000, 149000000 },
1129 	.hactive = { 1920, 1920, 1920 },
1130 	.hfront_porch = { 39, 58, 77 },
1131 	.hback_porch = { 59, 88, 117 },
1132 	.hsync_len = { 28, 42, 56 },
1133 	.vactive = { 1080, 1080, 1080 },
1134 	.vfront_porch = { 3, 8, 11 },
1135 	.vback_porch = { 5, 14, 19 },
1136 	.vsync_len = { 4, 14, 19 },
1137 };
1138 
1139 static const struct panel_desc auo_g133han01 = {
1140 	.timings = &auo_g133han01_timings,
1141 	.num_timings = 1,
1142 	.bpc = 8,
1143 	.size = {
1144 		.width = 293,
1145 		.height = 165,
1146 	},
1147 	.delay = {
1148 		.prepare = 200,
1149 		.enable = 50,
1150 		.disable = 50,
1151 		.unprepare = 1000,
1152 	},
1153 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1154 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1155 };
1156 
1157 static const struct drm_display_mode auo_g156xtn01_mode = {
1158 	.clock = 76000,
1159 	.hdisplay = 1366,
1160 	.hsync_start = 1366 + 33,
1161 	.hsync_end = 1366 + 33 + 67,
1162 	.htotal = 1560,
1163 	.vdisplay = 768,
1164 	.vsync_start = 768 + 4,
1165 	.vsync_end = 768 + 4 + 4,
1166 	.vtotal = 806,
1167 };
1168 
1169 static const struct panel_desc auo_g156xtn01 = {
1170 	.modes = &auo_g156xtn01_mode,
1171 	.num_modes = 1,
1172 	.bpc = 8,
1173 	.size = {
1174 		.width = 344,
1175 		.height = 194,
1176 	},
1177 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1178 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1179 };
1180 
1181 static const struct display_timing auo_g185han01_timings = {
1182 	.pixelclock = { 120000000, 144000000, 175000000 },
1183 	.hactive = { 1920, 1920, 1920 },
1184 	.hfront_porch = { 36, 120, 148 },
1185 	.hback_porch = { 24, 88, 108 },
1186 	.hsync_len = { 20, 48, 64 },
1187 	.vactive = { 1080, 1080, 1080 },
1188 	.vfront_porch = { 6, 10, 40 },
1189 	.vback_porch = { 2, 5, 20 },
1190 	.vsync_len = { 2, 5, 20 },
1191 };
1192 
1193 static const struct panel_desc auo_g185han01 = {
1194 	.timings = &auo_g185han01_timings,
1195 	.num_timings = 1,
1196 	.bpc = 8,
1197 	.size = {
1198 		.width = 409,
1199 		.height = 230,
1200 	},
1201 	.delay = {
1202 		.prepare = 50,
1203 		.enable = 200,
1204 		.disable = 110,
1205 		.unprepare = 1000,
1206 	},
1207 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1208 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1209 };
1210 
1211 static const struct display_timing auo_g190ean01_timings = {
1212 	.pixelclock = { 90000000, 108000000, 135000000 },
1213 	.hactive = { 1280, 1280, 1280 },
1214 	.hfront_porch = { 126, 184, 1266 },
1215 	.hback_porch = { 84, 122, 844 },
1216 	.hsync_len = { 70, 102, 704 },
1217 	.vactive = { 1024, 1024, 1024 },
1218 	.vfront_porch = { 4, 26, 76 },
1219 	.vback_porch = { 2, 8, 25 },
1220 	.vsync_len = { 2, 8, 25 },
1221 };
1222 
1223 static const struct panel_desc auo_g190ean01 = {
1224 	.timings = &auo_g190ean01_timings,
1225 	.num_timings = 1,
1226 	.bpc = 8,
1227 	.size = {
1228 		.width = 376,
1229 		.height = 301,
1230 	},
1231 	.delay = {
1232 		.prepare = 50,
1233 		.enable = 200,
1234 		.disable = 110,
1235 		.unprepare = 1000,
1236 	},
1237 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1239 };
1240 
1241 static const struct display_timing auo_p320hvn03_timings = {
1242 	.pixelclock = { 106000000, 148500000, 164000000 },
1243 	.hactive = { 1920, 1920, 1920 },
1244 	.hfront_porch = { 25, 50, 130 },
1245 	.hback_porch = { 25, 50, 130 },
1246 	.hsync_len = { 20, 40, 105 },
1247 	.vactive = { 1080, 1080, 1080 },
1248 	.vfront_porch = { 8, 17, 150 },
1249 	.vback_porch = { 8, 17, 150 },
1250 	.vsync_len = { 4, 11, 100 },
1251 };
1252 
1253 static const struct panel_desc auo_p320hvn03 = {
1254 	.timings = &auo_p320hvn03_timings,
1255 	.num_timings = 1,
1256 	.bpc = 8,
1257 	.size = {
1258 		.width = 698,
1259 		.height = 393,
1260 	},
1261 	.delay = {
1262 		.prepare = 1,
1263 		.enable = 450,
1264 		.unprepare = 500,
1265 	},
1266 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1267 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1268 };
1269 
1270 static const struct drm_display_mode auo_t215hvn01_mode = {
1271 	.clock = 148800,
1272 	.hdisplay = 1920,
1273 	.hsync_start = 1920 + 88,
1274 	.hsync_end = 1920 + 88 + 44,
1275 	.htotal = 1920 + 88 + 44 + 148,
1276 	.vdisplay = 1080,
1277 	.vsync_start = 1080 + 4,
1278 	.vsync_end = 1080 + 4 + 5,
1279 	.vtotal = 1080 + 4 + 5 + 36,
1280 };
1281 
1282 static const struct panel_desc auo_t215hvn01 = {
1283 	.modes = &auo_t215hvn01_mode,
1284 	.num_modes = 1,
1285 	.bpc = 8,
1286 	.size = {
1287 		.width = 430,
1288 		.height = 270,
1289 	},
1290 	.delay = {
1291 		.disable = 5,
1292 		.unprepare = 1000,
1293 	}
1294 };
1295 
1296 static const struct drm_display_mode avic_tm070ddh03_mode = {
1297 	.clock = 51200,
1298 	.hdisplay = 1024,
1299 	.hsync_start = 1024 + 160,
1300 	.hsync_end = 1024 + 160 + 4,
1301 	.htotal = 1024 + 160 + 4 + 156,
1302 	.vdisplay = 600,
1303 	.vsync_start = 600 + 17,
1304 	.vsync_end = 600 + 17 + 1,
1305 	.vtotal = 600 + 17 + 1 + 17,
1306 };
1307 
1308 static const struct panel_desc avic_tm070ddh03 = {
1309 	.modes = &avic_tm070ddh03_mode,
1310 	.num_modes = 1,
1311 	.bpc = 8,
1312 	.size = {
1313 		.width = 154,
1314 		.height = 90,
1315 	},
1316 	.delay = {
1317 		.prepare = 20,
1318 		.enable = 200,
1319 		.disable = 200,
1320 	},
1321 };
1322 
1323 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1324 	.clock = 30000,
1325 	.hdisplay = 800,
1326 	.hsync_start = 800 + 40,
1327 	.hsync_end = 800 + 40 + 48,
1328 	.htotal = 800 + 40 + 48 + 40,
1329 	.vdisplay = 480,
1330 	.vsync_start = 480 + 13,
1331 	.vsync_end = 480 + 13 + 3,
1332 	.vtotal = 480 + 13 + 3 + 29,
1333 };
1334 
1335 static const struct panel_desc bananapi_s070wv20_ct16 = {
1336 	.modes = &bananapi_s070wv20_ct16_mode,
1337 	.num_modes = 1,
1338 	.bpc = 6,
1339 	.size = {
1340 		.width = 154,
1341 		.height = 86,
1342 	},
1343 };
1344 
1345 static const struct drm_display_mode boe_hv070wsa_mode = {
1346 	.clock = 42105,
1347 	.hdisplay = 1024,
1348 	.hsync_start = 1024 + 30,
1349 	.hsync_end = 1024 + 30 + 30,
1350 	.htotal = 1024 + 30 + 30 + 30,
1351 	.vdisplay = 600,
1352 	.vsync_start = 600 + 10,
1353 	.vsync_end = 600 + 10 + 10,
1354 	.vtotal = 600 + 10 + 10 + 10,
1355 };
1356 
1357 static const struct panel_desc boe_hv070wsa = {
1358 	.modes = &boe_hv070wsa_mode,
1359 	.num_modes = 1,
1360 	.bpc = 8,
1361 	.size = {
1362 		.width = 154,
1363 		.height = 90,
1364 	},
1365 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1366 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1367 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1368 };
1369 
1370 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1371 	{
1372 		.clock = 71900,
1373 		.hdisplay = 1280,
1374 		.hsync_start = 1280 + 48,
1375 		.hsync_end = 1280 + 48 + 32,
1376 		.htotal = 1280 + 48 + 32 + 80,
1377 		.vdisplay = 800,
1378 		.vsync_start = 800 + 3,
1379 		.vsync_end = 800 + 3 + 5,
1380 		.vtotal = 800 + 3 + 5 + 24,
1381 	},
1382 	{
1383 		.clock = 57500,
1384 		.hdisplay = 1280,
1385 		.hsync_start = 1280 + 48,
1386 		.hsync_end = 1280 + 48 + 32,
1387 		.htotal = 1280 + 48 + 32 + 80,
1388 		.vdisplay = 800,
1389 		.vsync_start = 800 + 3,
1390 		.vsync_end = 800 + 3 + 5,
1391 		.vtotal = 800 + 3 + 5 + 24,
1392 	},
1393 };
1394 
1395 static const struct panel_desc boe_nv101wxmn51 = {
1396 	.modes = boe_nv101wxmn51_modes,
1397 	.num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1398 	.bpc = 8,
1399 	.size = {
1400 		.width = 217,
1401 		.height = 136,
1402 	},
1403 	.delay = {
1404 		.prepare = 210,
1405 		.enable = 50,
1406 		.unprepare = 160,
1407 	},
1408 };
1409 
1410 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = {
1411 	{
1412 		.clock = 207800,
1413 		.hdisplay = 2160,
1414 		.hsync_start = 2160 + 48,
1415 		.hsync_end = 2160 + 48 + 32,
1416 		.htotal = 2160 + 48 + 32 + 100,
1417 		.vdisplay = 1440,
1418 		.vsync_start = 1440 + 3,
1419 		.vsync_end = 1440 + 3 + 6,
1420 		.vtotal = 1440 + 3 + 6 + 31,
1421 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1422 	},
1423 	{
1424 		.clock = 138500,
1425 		.hdisplay = 2160,
1426 		.hsync_start = 2160 + 48,
1427 		.hsync_end = 2160 + 48 + 32,
1428 		.htotal = 2160 + 48 + 32 + 100,
1429 		.vdisplay = 1440,
1430 		.vsync_start = 1440 + 3,
1431 		.vsync_end = 1440 + 3 + 6,
1432 		.vtotal = 1440 + 3 + 6 + 31,
1433 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1434 	},
1435 };
1436 
1437 static const struct panel_desc boe_nv110wtm_n61 = {
1438 	.modes = boe_nv110wtm_n61_modes,
1439 	.num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes),
1440 	.bpc = 8,
1441 	.size = {
1442 		.width = 233,
1443 		.height = 155,
1444 	},
1445 	.delay = {
1446 		.hpd_absent_delay = 200,
1447 		.prepare_to_enable = 80,
1448 		.unprepare = 500,
1449 	},
1450 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1451 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1452 	.connector_type = DRM_MODE_CONNECTOR_eDP,
1453 };
1454 
1455 /* Also used for boe_nv133fhm_n62 */
1456 static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1457 	.clock = 147840,
1458 	.hdisplay = 1920,
1459 	.hsync_start = 1920 + 48,
1460 	.hsync_end = 1920 + 48 + 32,
1461 	.htotal = 1920 + 48 + 32 + 200,
1462 	.vdisplay = 1080,
1463 	.vsync_start = 1080 + 3,
1464 	.vsync_end = 1080 + 3 + 6,
1465 	.vtotal = 1080 + 3 + 6 + 31,
1466 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
1467 };
1468 
1469 /* Also used for boe_nv133fhm_n62 */
1470 static const struct panel_desc boe_nv133fhm_n61 = {
1471 	.modes = &boe_nv133fhm_n61_modes,
1472 	.num_modes = 1,
1473 	.bpc = 6,
1474 	.size = {
1475 		.width = 294,
1476 		.height = 165,
1477 	},
1478 	.delay = {
1479 		/*
1480 		 * When power is first given to the panel there's a short
1481 		 * spike on the HPD line.  It was explained that this spike
1482 		 * was until the TCON data download was complete.  On
1483 		 * one system this was measured at 8 ms.  We'll put 15 ms
1484 		 * in the prepare delay just to be safe and take it away
1485 		 * from the hpd_absent_delay (which would otherwise be 200 ms)
1486 		 * to handle this.  That means:
1487 		 * - If HPD isn't hooked up you still have 200 ms delay.
1488 		 * - If HPD is hooked up we won't try to look at it for the
1489 		 *   first 15 ms.
1490 		 */
1491 		.prepare = 15,
1492 		.hpd_absent_delay = 185,
1493 
1494 		.unprepare = 500,
1495 	},
1496 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1497 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1498 	.connector_type = DRM_MODE_CONNECTOR_eDP,
1499 };
1500 
1501 static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1502 	{
1503 		.clock = 148500,
1504 		.hdisplay = 1920,
1505 		.hsync_start = 1920 + 48,
1506 		.hsync_end = 1920 + 48 + 32,
1507 		.htotal = 2200,
1508 		.vdisplay = 1080,
1509 		.vsync_start = 1080 + 3,
1510 		.vsync_end = 1080 + 3 + 5,
1511 		.vtotal = 1125,
1512 	},
1513 };
1514 
1515 static const struct panel_desc boe_nv140fhmn49 = {
1516 	.modes = boe_nv140fhmn49_modes,
1517 	.num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1518 	.bpc = 6,
1519 	.size = {
1520 		.width = 309,
1521 		.height = 174,
1522 	},
1523 	.delay = {
1524 		.prepare = 210,
1525 		.enable = 50,
1526 		.unprepare = 160,
1527 	},
1528 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1529 	.connector_type = DRM_MODE_CONNECTOR_eDP,
1530 };
1531 
1532 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1533 	.clock = 9000,
1534 	.hdisplay = 480,
1535 	.hsync_start = 480 + 5,
1536 	.hsync_end = 480 + 5 + 5,
1537 	.htotal = 480 + 5 + 5 + 40,
1538 	.vdisplay = 272,
1539 	.vsync_start = 272 + 8,
1540 	.vsync_end = 272 + 8 + 8,
1541 	.vtotal = 272 + 8 + 8 + 8,
1542 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1543 };
1544 
1545 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1546 	.modes = &cdtech_s043wq26h_ct7_mode,
1547 	.num_modes = 1,
1548 	.bpc = 8,
1549 	.size = {
1550 		.width = 95,
1551 		.height = 54,
1552 	},
1553 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1554 };
1555 
1556 /* S070PWS19HP-FC21 2017/04/22 */
1557 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1558 	.clock = 51200,
1559 	.hdisplay = 1024,
1560 	.hsync_start = 1024 + 160,
1561 	.hsync_end = 1024 + 160 + 20,
1562 	.htotal = 1024 + 160 + 20 + 140,
1563 	.vdisplay = 600,
1564 	.vsync_start = 600 + 12,
1565 	.vsync_end = 600 + 12 + 3,
1566 	.vtotal = 600 + 12 + 3 + 20,
1567 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1568 };
1569 
1570 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1571 	.modes = &cdtech_s070pws19hp_fc21_mode,
1572 	.num_modes = 1,
1573 	.bpc = 6,
1574 	.size = {
1575 		.width = 154,
1576 		.height = 86,
1577 	},
1578 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1579 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1580 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1581 };
1582 
1583 /* S070SWV29HG-DC44 2017/09/21 */
1584 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1585 	.clock = 33300,
1586 	.hdisplay = 800,
1587 	.hsync_start = 800 + 210,
1588 	.hsync_end = 800 + 210 + 2,
1589 	.htotal = 800 + 210 + 2 + 44,
1590 	.vdisplay = 480,
1591 	.vsync_start = 480 + 22,
1592 	.vsync_end = 480 + 22 + 2,
1593 	.vtotal = 480 + 22 + 2 + 21,
1594 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1595 };
1596 
1597 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1598 	.modes = &cdtech_s070swv29hg_dc44_mode,
1599 	.num_modes = 1,
1600 	.bpc = 6,
1601 	.size = {
1602 		.width = 154,
1603 		.height = 86,
1604 	},
1605 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1606 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1607 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1608 };
1609 
1610 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1611 	.clock = 35000,
1612 	.hdisplay = 800,
1613 	.hsync_start = 800 + 40,
1614 	.hsync_end = 800 + 40 + 40,
1615 	.htotal = 800 + 40 + 40 + 48,
1616 	.vdisplay = 480,
1617 	.vsync_start = 480 + 29,
1618 	.vsync_end = 480 + 29 + 13,
1619 	.vtotal = 480 + 29 + 13 + 3,
1620 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1621 };
1622 
1623 static const struct panel_desc cdtech_s070wv95_ct16 = {
1624 	.modes = &cdtech_s070wv95_ct16_mode,
1625 	.num_modes = 1,
1626 	.bpc = 8,
1627 	.size = {
1628 		.width = 154,
1629 		.height = 85,
1630 	},
1631 };
1632 
1633 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1634 	.pixelclock = { 68900000, 71100000, 73400000 },
1635 	.hactive = { 1280, 1280, 1280 },
1636 	.hfront_porch = { 65, 80, 95 },
1637 	.hback_porch = { 64, 79, 94 },
1638 	.hsync_len = { 1, 1, 1 },
1639 	.vactive = { 800, 800, 800 },
1640 	.vfront_porch = { 7, 11, 14 },
1641 	.vback_porch = { 7, 11, 14 },
1642 	.vsync_len = { 1, 1, 1 },
1643 	.flags = DISPLAY_FLAGS_DE_HIGH,
1644 };
1645 
1646 static const struct panel_desc chefree_ch101olhlwh_002 = {
1647 	.timings = &chefree_ch101olhlwh_002_timing,
1648 	.num_timings = 1,
1649 	.bpc = 8,
1650 	.size = {
1651 		.width = 217,
1652 		.height = 135,
1653 	},
1654 	.delay = {
1655 		.enable = 200,
1656 		.disable = 200,
1657 	},
1658 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1659 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1660 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1661 };
1662 
1663 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1664 	.clock = 66770,
1665 	.hdisplay = 800,
1666 	.hsync_start = 800 + 49,
1667 	.hsync_end = 800 + 49 + 33,
1668 	.htotal = 800 + 49 + 33 + 17,
1669 	.vdisplay = 1280,
1670 	.vsync_start = 1280 + 1,
1671 	.vsync_end = 1280 + 1 + 7,
1672 	.vtotal = 1280 + 1 + 7 + 15,
1673 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1674 };
1675 
1676 static const struct panel_desc chunghwa_claa070wp03xg = {
1677 	.modes = &chunghwa_claa070wp03xg_mode,
1678 	.num_modes = 1,
1679 	.bpc = 6,
1680 	.size = {
1681 		.width = 94,
1682 		.height = 150,
1683 	},
1684 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1685 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1686 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1687 };
1688 
1689 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1690 	.clock = 72070,
1691 	.hdisplay = 1366,
1692 	.hsync_start = 1366 + 58,
1693 	.hsync_end = 1366 + 58 + 58,
1694 	.htotal = 1366 + 58 + 58 + 58,
1695 	.vdisplay = 768,
1696 	.vsync_start = 768 + 4,
1697 	.vsync_end = 768 + 4 + 4,
1698 	.vtotal = 768 + 4 + 4 + 4,
1699 };
1700 
1701 static const struct panel_desc chunghwa_claa101wa01a = {
1702 	.modes = &chunghwa_claa101wa01a_mode,
1703 	.num_modes = 1,
1704 	.bpc = 6,
1705 	.size = {
1706 		.width = 220,
1707 		.height = 120,
1708 	},
1709 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1710 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1711 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1712 };
1713 
1714 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1715 	.clock = 69300,
1716 	.hdisplay = 1366,
1717 	.hsync_start = 1366 + 48,
1718 	.hsync_end = 1366 + 48 + 32,
1719 	.htotal = 1366 + 48 + 32 + 20,
1720 	.vdisplay = 768,
1721 	.vsync_start = 768 + 16,
1722 	.vsync_end = 768 + 16 + 8,
1723 	.vtotal = 768 + 16 + 8 + 16,
1724 };
1725 
1726 static const struct panel_desc chunghwa_claa101wb01 = {
1727 	.modes = &chunghwa_claa101wb01_mode,
1728 	.num_modes = 1,
1729 	.bpc = 6,
1730 	.size = {
1731 		.width = 223,
1732 		.height = 125,
1733 	},
1734 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1735 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1736 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1737 };
1738 
1739 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1740 	.clock = 33260,
1741 	.hdisplay = 800,
1742 	.hsync_start = 800 + 40,
1743 	.hsync_end = 800 + 40 + 128,
1744 	.htotal = 800 + 40 + 128 + 88,
1745 	.vdisplay = 480,
1746 	.vsync_start = 480 + 10,
1747 	.vsync_end = 480 + 10 + 2,
1748 	.vtotal = 480 + 10 + 2 + 33,
1749 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1750 };
1751 
1752 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1753 	.modes = &dataimage_scf0700c48ggu18_mode,
1754 	.num_modes = 1,
1755 	.bpc = 8,
1756 	.size = {
1757 		.width = 152,
1758 		.height = 91,
1759 	},
1760 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1761 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1762 };
1763 
1764 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1765 	.pixelclock = { 45000000, 51200000, 57000000 },
1766 	.hactive = { 1024, 1024, 1024 },
1767 	.hfront_porch = { 100, 106, 113 },
1768 	.hback_porch = { 100, 106, 113 },
1769 	.hsync_len = { 100, 108, 114 },
1770 	.vactive = { 600, 600, 600 },
1771 	.vfront_porch = { 8, 11, 15 },
1772 	.vback_porch = { 8, 11, 15 },
1773 	.vsync_len = { 9, 13, 15 },
1774 	.flags = DISPLAY_FLAGS_DE_HIGH,
1775 };
1776 
1777 static const struct panel_desc dlc_dlc0700yzg_1 = {
1778 	.timings = &dlc_dlc0700yzg_1_timing,
1779 	.num_timings = 1,
1780 	.bpc = 6,
1781 	.size = {
1782 		.width = 154,
1783 		.height = 86,
1784 	},
1785 	.delay = {
1786 		.prepare = 30,
1787 		.enable = 200,
1788 		.disable = 200,
1789 	},
1790 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1791 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1792 };
1793 
1794 static const struct display_timing dlc_dlc1010gig_timing = {
1795 	.pixelclock = { 68900000, 71100000, 73400000 },
1796 	.hactive = { 1280, 1280, 1280 },
1797 	.hfront_porch = { 43, 53, 63 },
1798 	.hback_porch = { 43, 53, 63 },
1799 	.hsync_len = { 44, 54, 64 },
1800 	.vactive = { 800, 800, 800 },
1801 	.vfront_porch = { 5, 8, 11 },
1802 	.vback_porch = { 5, 8, 11 },
1803 	.vsync_len = { 5, 7, 11 },
1804 	.flags = DISPLAY_FLAGS_DE_HIGH,
1805 };
1806 
1807 static const struct panel_desc dlc_dlc1010gig = {
1808 	.timings = &dlc_dlc1010gig_timing,
1809 	.num_timings = 1,
1810 	.bpc = 8,
1811 	.size = {
1812 		.width = 216,
1813 		.height = 135,
1814 	},
1815 	.delay = {
1816 		.prepare = 60,
1817 		.enable = 150,
1818 		.disable = 100,
1819 		.unprepare = 60,
1820 	},
1821 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1822 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1823 };
1824 
1825 static const struct drm_display_mode edt_et035012dm6_mode = {
1826 	.clock = 6500,
1827 	.hdisplay = 320,
1828 	.hsync_start = 320 + 20,
1829 	.hsync_end = 320 + 20 + 30,
1830 	.htotal = 320 + 20 + 68,
1831 	.vdisplay = 240,
1832 	.vsync_start = 240 + 4,
1833 	.vsync_end = 240 + 4 + 4,
1834 	.vtotal = 240 + 4 + 4 + 14,
1835 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1836 };
1837 
1838 static const struct panel_desc edt_et035012dm6 = {
1839 	.modes = &edt_et035012dm6_mode,
1840 	.num_modes = 1,
1841 	.bpc = 8,
1842 	.size = {
1843 		.width = 70,
1844 		.height = 52,
1845 	},
1846 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1847 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1848 };
1849 
1850 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1851 	.clock = 10870,
1852 	.hdisplay = 480,
1853 	.hsync_start = 480 + 8,
1854 	.hsync_end = 480 + 8 + 4,
1855 	.htotal = 480 + 8 + 4 + 41,
1856 
1857 	/*
1858 	 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1859 	 * fb_align
1860 	 */
1861 
1862 	.vdisplay = 288,
1863 	.vsync_start = 288 + 2,
1864 	.vsync_end = 288 + 2 + 4,
1865 	.vtotal = 288 + 2 + 4 + 10,
1866 };
1867 
1868 static const struct panel_desc edt_etm043080dh6gp = {
1869 	.modes = &edt_etm043080dh6gp_mode,
1870 	.num_modes = 1,
1871 	.bpc = 8,
1872 	.size = {
1873 		.width = 100,
1874 		.height = 65,
1875 	},
1876 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1877 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1878 };
1879 
1880 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1881 	.clock = 9000,
1882 	.hdisplay = 480,
1883 	.hsync_start = 480 + 2,
1884 	.hsync_end = 480 + 2 + 41,
1885 	.htotal = 480 + 2 + 41 + 2,
1886 	.vdisplay = 272,
1887 	.vsync_start = 272 + 2,
1888 	.vsync_end = 272 + 2 + 10,
1889 	.vtotal = 272 + 2 + 10 + 2,
1890 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1891 };
1892 
1893 static const struct panel_desc edt_etm0430g0dh6 = {
1894 	.modes = &edt_etm0430g0dh6_mode,
1895 	.num_modes = 1,
1896 	.bpc = 6,
1897 	.size = {
1898 		.width = 95,
1899 		.height = 54,
1900 	},
1901 };
1902 
1903 static const struct drm_display_mode edt_et057090dhu_mode = {
1904 	.clock = 25175,
1905 	.hdisplay = 640,
1906 	.hsync_start = 640 + 16,
1907 	.hsync_end = 640 + 16 + 30,
1908 	.htotal = 640 + 16 + 30 + 114,
1909 	.vdisplay = 480,
1910 	.vsync_start = 480 + 10,
1911 	.vsync_end = 480 + 10 + 3,
1912 	.vtotal = 480 + 10 + 3 + 32,
1913 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1914 };
1915 
1916 static const struct panel_desc edt_et057090dhu = {
1917 	.modes = &edt_et057090dhu_mode,
1918 	.num_modes = 1,
1919 	.bpc = 6,
1920 	.size = {
1921 		.width = 115,
1922 		.height = 86,
1923 	},
1924 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1925 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1926 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1927 };
1928 
1929 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1930 	.clock = 33260,
1931 	.hdisplay = 800,
1932 	.hsync_start = 800 + 40,
1933 	.hsync_end = 800 + 40 + 128,
1934 	.htotal = 800 + 40 + 128 + 88,
1935 	.vdisplay = 480,
1936 	.vsync_start = 480 + 10,
1937 	.vsync_end = 480 + 10 + 2,
1938 	.vtotal = 480 + 10 + 2 + 33,
1939 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1940 };
1941 
1942 static const struct panel_desc edt_etm0700g0dh6 = {
1943 	.modes = &edt_etm0700g0dh6_mode,
1944 	.num_modes = 1,
1945 	.bpc = 6,
1946 	.size = {
1947 		.width = 152,
1948 		.height = 91,
1949 	},
1950 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1951 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1952 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1953 };
1954 
1955 static const struct panel_desc edt_etm0700g0bdh6 = {
1956 	.modes = &edt_etm0700g0dh6_mode,
1957 	.num_modes = 1,
1958 	.bpc = 6,
1959 	.size = {
1960 		.width = 152,
1961 		.height = 91,
1962 	},
1963 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1964 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1965 };
1966 
1967 static const struct display_timing evervision_vgg804821_timing = {
1968 	.pixelclock = { 27600000, 33300000, 50000000 },
1969 	.hactive = { 800, 800, 800 },
1970 	.hfront_porch = { 40, 66, 70 },
1971 	.hback_porch = { 40, 67, 70 },
1972 	.hsync_len = { 40, 67, 70 },
1973 	.vactive = { 480, 480, 480 },
1974 	.vfront_porch = { 6, 10, 10 },
1975 	.vback_porch = { 7, 11, 11 },
1976 	.vsync_len = { 7, 11, 11 },
1977 	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1978 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1979 		 DISPLAY_FLAGS_SYNC_NEGEDGE,
1980 };
1981 
1982 static const struct panel_desc evervision_vgg804821 = {
1983 	.timings = &evervision_vgg804821_timing,
1984 	.num_timings = 1,
1985 	.bpc = 8,
1986 	.size = {
1987 		.width = 108,
1988 		.height = 64,
1989 	},
1990 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1991 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1992 };
1993 
1994 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1995 	.clock = 32260,
1996 	.hdisplay = 800,
1997 	.hsync_start = 800 + 168,
1998 	.hsync_end = 800 + 168 + 64,
1999 	.htotal = 800 + 168 + 64 + 88,
2000 	.vdisplay = 480,
2001 	.vsync_start = 480 + 37,
2002 	.vsync_end = 480 + 37 + 2,
2003 	.vtotal = 480 + 37 + 2 + 8,
2004 };
2005 
2006 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2007 	.modes = &foxlink_fl500wvr00_a0t_mode,
2008 	.num_modes = 1,
2009 	.bpc = 8,
2010 	.size = {
2011 		.width = 108,
2012 		.height = 65,
2013 	},
2014 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2015 };
2016 
2017 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2018 	{ /* 60 Hz */
2019 		.clock = 6000,
2020 		.hdisplay = 320,
2021 		.hsync_start = 320 + 44,
2022 		.hsync_end = 320 + 44 + 16,
2023 		.htotal = 320 + 44 + 16 + 20,
2024 		.vdisplay = 240,
2025 		.vsync_start = 240 + 2,
2026 		.vsync_end = 240 + 2 + 6,
2027 		.vtotal = 240 + 2 + 6 + 2,
2028 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2029 	},
2030 	{ /* 50 Hz */
2031 		.clock = 5400,
2032 		.hdisplay = 320,
2033 		.hsync_start = 320 + 56,
2034 		.hsync_end = 320 + 56 + 16,
2035 		.htotal = 320 + 56 + 16 + 40,
2036 		.vdisplay = 240,
2037 		.vsync_start = 240 + 2,
2038 		.vsync_end = 240 + 2 + 6,
2039 		.vtotal = 240 + 2 + 6 + 2,
2040 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2041 	},
2042 };
2043 
2044 static const struct panel_desc frida_frd350h54004 = {
2045 	.modes = frida_frd350h54004_modes,
2046 	.num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2047 	.bpc = 8,
2048 	.size = {
2049 		.width = 77,
2050 		.height = 64,
2051 	},
2052 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2053 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2054 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2055 };
2056 
2057 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2058 	.clock		= 67185,
2059 	.hdisplay	= 800,
2060 	.hsync_start	= 800 + 20,
2061 	.hsync_end	= 800 + 20 + 24,
2062 	.htotal		= 800 + 20 + 24 + 20,
2063 	.vdisplay	= 1280,
2064 	.vsync_start	= 1280 + 4,
2065 	.vsync_end	= 1280 + 4 + 8,
2066 	.vtotal		= 1280 + 4 + 8 + 4,
2067 	.flags		= DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2068 };
2069 
2070 static const struct panel_desc friendlyarm_hd702e = {
2071 	.modes = &friendlyarm_hd702e_mode,
2072 	.num_modes = 1,
2073 	.size = {
2074 		.width	= 94,
2075 		.height	= 151,
2076 	},
2077 };
2078 
2079 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2080 	.clock = 9000,
2081 	.hdisplay = 480,
2082 	.hsync_start = 480 + 5,
2083 	.hsync_end = 480 + 5 + 1,
2084 	.htotal = 480 + 5 + 1 + 40,
2085 	.vdisplay = 272,
2086 	.vsync_start = 272 + 8,
2087 	.vsync_end = 272 + 8 + 1,
2088 	.vtotal = 272 + 8 + 1 + 8,
2089 };
2090 
2091 static const struct panel_desc giantplus_gpg482739qs5 = {
2092 	.modes = &giantplus_gpg482739qs5_mode,
2093 	.num_modes = 1,
2094 	.bpc = 8,
2095 	.size = {
2096 		.width = 95,
2097 		.height = 54,
2098 	},
2099 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2100 };
2101 
2102 static const struct display_timing giantplus_gpm940b0_timing = {
2103 	.pixelclock = { 13500000, 27000000, 27500000 },
2104 	.hactive = { 320, 320, 320 },
2105 	.hfront_porch = { 14, 686, 718 },
2106 	.hback_porch = { 50, 70, 255 },
2107 	.hsync_len = { 1, 1, 1 },
2108 	.vactive = { 240, 240, 240 },
2109 	.vfront_porch = { 1, 1, 179 },
2110 	.vback_porch = { 1, 21, 31 },
2111 	.vsync_len = { 1, 1, 6 },
2112 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2113 };
2114 
2115 static const struct panel_desc giantplus_gpm940b0 = {
2116 	.timings = &giantplus_gpm940b0_timing,
2117 	.num_timings = 1,
2118 	.bpc = 8,
2119 	.size = {
2120 		.width = 60,
2121 		.height = 45,
2122 	},
2123 	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2124 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2125 };
2126 
2127 static const struct display_timing hannstar_hsd070pww1_timing = {
2128 	.pixelclock = { 64300000, 71100000, 82000000 },
2129 	.hactive = { 1280, 1280, 1280 },
2130 	.hfront_porch = { 1, 1, 10 },
2131 	.hback_porch = { 1, 1, 10 },
2132 	/*
2133 	 * According to the data sheet, the minimum horizontal blanking interval
2134 	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2135 	 * minimum working horizontal blanking interval to be 60 clocks.
2136 	 */
2137 	.hsync_len = { 58, 158, 661 },
2138 	.vactive = { 800, 800, 800 },
2139 	.vfront_porch = { 1, 1, 10 },
2140 	.vback_porch = { 1, 1, 10 },
2141 	.vsync_len = { 1, 21, 203 },
2142 	.flags = DISPLAY_FLAGS_DE_HIGH,
2143 };
2144 
2145 static const struct panel_desc hannstar_hsd070pww1 = {
2146 	.timings = &hannstar_hsd070pww1_timing,
2147 	.num_timings = 1,
2148 	.bpc = 6,
2149 	.size = {
2150 		.width = 151,
2151 		.height = 94,
2152 	},
2153 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2154 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2155 };
2156 
2157 static const struct display_timing hannstar_hsd100pxn1_timing = {
2158 	.pixelclock = { 55000000, 65000000, 75000000 },
2159 	.hactive = { 1024, 1024, 1024 },
2160 	.hfront_porch = { 40, 40, 40 },
2161 	.hback_porch = { 220, 220, 220 },
2162 	.hsync_len = { 20, 60, 100 },
2163 	.vactive = { 768, 768, 768 },
2164 	.vfront_porch = { 7, 7, 7 },
2165 	.vback_porch = { 21, 21, 21 },
2166 	.vsync_len = { 10, 10, 10 },
2167 	.flags = DISPLAY_FLAGS_DE_HIGH,
2168 };
2169 
2170 static const struct panel_desc hannstar_hsd100pxn1 = {
2171 	.timings = &hannstar_hsd100pxn1_timing,
2172 	.num_timings = 1,
2173 	.bpc = 6,
2174 	.size = {
2175 		.width = 203,
2176 		.height = 152,
2177 	},
2178 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2179 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2180 };
2181 
2182 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2183 	.clock = 33333,
2184 	.hdisplay = 800,
2185 	.hsync_start = 800 + 85,
2186 	.hsync_end = 800 + 85 + 86,
2187 	.htotal = 800 + 85 + 86 + 85,
2188 	.vdisplay = 480,
2189 	.vsync_start = 480 + 16,
2190 	.vsync_end = 480 + 16 + 13,
2191 	.vtotal = 480 + 16 + 13 + 16,
2192 };
2193 
2194 static const struct panel_desc hitachi_tx23d38vm0caa = {
2195 	.modes = &hitachi_tx23d38vm0caa_mode,
2196 	.num_modes = 1,
2197 	.bpc = 6,
2198 	.size = {
2199 		.width = 195,
2200 		.height = 117,
2201 	},
2202 	.delay = {
2203 		.enable = 160,
2204 		.disable = 160,
2205 	},
2206 };
2207 
2208 static const struct drm_display_mode innolux_at043tn24_mode = {
2209 	.clock = 9000,
2210 	.hdisplay = 480,
2211 	.hsync_start = 480 + 2,
2212 	.hsync_end = 480 + 2 + 41,
2213 	.htotal = 480 + 2 + 41 + 2,
2214 	.vdisplay = 272,
2215 	.vsync_start = 272 + 2,
2216 	.vsync_end = 272 + 2 + 10,
2217 	.vtotal = 272 + 2 + 10 + 2,
2218 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2219 };
2220 
2221 static const struct panel_desc innolux_at043tn24 = {
2222 	.modes = &innolux_at043tn24_mode,
2223 	.num_modes = 1,
2224 	.bpc = 8,
2225 	.size = {
2226 		.width = 95,
2227 		.height = 54,
2228 	},
2229 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2230 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2231 };
2232 
2233 static const struct drm_display_mode innolux_at070tn92_mode = {
2234 	.clock = 33333,
2235 	.hdisplay = 800,
2236 	.hsync_start = 800 + 210,
2237 	.hsync_end = 800 + 210 + 20,
2238 	.htotal = 800 + 210 + 20 + 46,
2239 	.vdisplay = 480,
2240 	.vsync_start = 480 + 22,
2241 	.vsync_end = 480 + 22 + 10,
2242 	.vtotal = 480 + 22 + 23 + 10,
2243 };
2244 
2245 static const struct panel_desc innolux_at070tn92 = {
2246 	.modes = &innolux_at070tn92_mode,
2247 	.num_modes = 1,
2248 	.size = {
2249 		.width = 154,
2250 		.height = 86,
2251 	},
2252 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2253 };
2254 
2255 static const struct display_timing innolux_g070y2_l01_timing = {
2256 	.pixelclock = { 28000000, 29500000, 32000000 },
2257 	.hactive = { 800, 800, 800 },
2258 	.hfront_porch = { 61, 91, 141 },
2259 	.hback_porch = { 60, 90, 140 },
2260 	.hsync_len = { 12, 12, 12 },
2261 	.vactive = { 480, 480, 480 },
2262 	.vfront_porch = { 4, 9, 30 },
2263 	.vback_porch = { 4, 8, 28 },
2264 	.vsync_len = { 2, 2, 2 },
2265 	.flags = DISPLAY_FLAGS_DE_HIGH,
2266 };
2267 
2268 static const struct panel_desc innolux_g070y2_l01 = {
2269 	.timings = &innolux_g070y2_l01_timing,
2270 	.num_timings = 1,
2271 	.bpc = 6,
2272 	.size = {
2273 		.width = 152,
2274 		.height = 91,
2275 	},
2276 	.delay = {
2277 		.prepare = 10,
2278 		.enable = 100,
2279 		.disable = 100,
2280 		.unprepare = 800,
2281 	},
2282 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2283 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2284 };
2285 
2286 static const struct display_timing innolux_g101ice_l01_timing = {
2287 	.pixelclock = { 60400000, 71100000, 74700000 },
2288 	.hactive = { 1280, 1280, 1280 },
2289 	.hfront_porch = { 41, 80, 100 },
2290 	.hback_porch = { 40, 79, 99 },
2291 	.hsync_len = { 1, 1, 1 },
2292 	.vactive = { 800, 800, 800 },
2293 	.vfront_porch = { 5, 11, 14 },
2294 	.vback_porch = { 4, 11, 14 },
2295 	.vsync_len = { 1, 1, 1 },
2296 	.flags = DISPLAY_FLAGS_DE_HIGH,
2297 };
2298 
2299 static const struct panel_desc innolux_g101ice_l01 = {
2300 	.timings = &innolux_g101ice_l01_timing,
2301 	.num_timings = 1,
2302 	.bpc = 8,
2303 	.size = {
2304 		.width = 217,
2305 		.height = 135,
2306 	},
2307 	.delay = {
2308 		.enable = 200,
2309 		.disable = 200,
2310 	},
2311 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2312 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2313 };
2314 
2315 static const struct display_timing innolux_g121i1_l01_timing = {
2316 	.pixelclock = { 67450000, 71000000, 74550000 },
2317 	.hactive = { 1280, 1280, 1280 },
2318 	.hfront_porch = { 40, 80, 160 },
2319 	.hback_porch = { 39, 79, 159 },
2320 	.hsync_len = { 1, 1, 1 },
2321 	.vactive = { 800, 800, 800 },
2322 	.vfront_porch = { 5, 11, 100 },
2323 	.vback_porch = { 4, 11, 99 },
2324 	.vsync_len = { 1, 1, 1 },
2325 };
2326 
2327 static const struct panel_desc innolux_g121i1_l01 = {
2328 	.timings = &innolux_g121i1_l01_timing,
2329 	.num_timings = 1,
2330 	.bpc = 6,
2331 	.size = {
2332 		.width = 261,
2333 		.height = 163,
2334 	},
2335 	.delay = {
2336 		.enable = 200,
2337 		.disable = 20,
2338 	},
2339 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2340 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2341 };
2342 
2343 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2344 	.clock = 65000,
2345 	.hdisplay = 1024,
2346 	.hsync_start = 1024 + 0,
2347 	.hsync_end = 1024 + 1,
2348 	.htotal = 1024 + 0 + 1 + 320,
2349 	.vdisplay = 768,
2350 	.vsync_start = 768 + 38,
2351 	.vsync_end = 768 + 38 + 1,
2352 	.vtotal = 768 + 38 + 1 + 0,
2353 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2354 };
2355 
2356 static const struct panel_desc innolux_g121x1_l03 = {
2357 	.modes = &innolux_g121x1_l03_mode,
2358 	.num_modes = 1,
2359 	.bpc = 6,
2360 	.size = {
2361 		.width = 246,
2362 		.height = 185,
2363 	},
2364 	.delay = {
2365 		.enable = 200,
2366 		.unprepare = 200,
2367 		.disable = 400,
2368 	},
2369 };
2370 
2371 /*
2372  * Datasheet specifies that at 60 Hz refresh rate:
2373  * - total horizontal time: { 1506, 1592, 1716 }
2374  * - total vertical time: { 788, 800, 868 }
2375  *
2376  * ...but doesn't go into exactly how that should be split into a front
2377  * porch, back porch, or sync length.  For now we'll leave a single setting
2378  * here which allows a bit of tweaking of the pixel clock at the expense of
2379  * refresh rate.
2380  */
2381 static const struct display_timing innolux_n116bge_timing = {
2382 	.pixelclock = { 72600000, 76420000, 80240000 },
2383 	.hactive = { 1366, 1366, 1366 },
2384 	.hfront_porch = { 136, 136, 136 },
2385 	.hback_porch = { 60, 60, 60 },
2386 	.hsync_len = { 30, 30, 30 },
2387 	.vactive = { 768, 768, 768 },
2388 	.vfront_porch = { 8, 8, 8 },
2389 	.vback_porch = { 12, 12, 12 },
2390 	.vsync_len = { 12, 12, 12 },
2391 	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2392 };
2393 
2394 static const struct panel_desc innolux_n116bge = {
2395 	.timings = &innolux_n116bge_timing,
2396 	.num_timings = 1,
2397 	.bpc = 6,
2398 	.size = {
2399 		.width = 256,
2400 		.height = 144,
2401 	},
2402 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2403 	.connector_type = DRM_MODE_CONNECTOR_eDP,
2404 };
2405 
2406 static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2407 	.clock = 162000,
2408 	.hdisplay = 1920,
2409 	.hsync_start = 1920 + 40,
2410 	.hsync_end = 1920 + 40 + 40,
2411 	.htotal = 1920 + 40 + 40 + 80,
2412 	.vdisplay = 1080,
2413 	.vsync_start = 1080 + 4,
2414 	.vsync_end = 1080 + 4 + 4,
2415 	.vtotal = 1080 + 4 + 4 + 24,
2416 };
2417 
2418 static const struct panel_desc innolux_n125hce_gn1 = {
2419 	.modes = &innolux_n125hce_gn1_mode,
2420 	.num_modes = 1,
2421 	.bpc = 8,
2422 	.size = {
2423 		.width = 276,
2424 		.height = 155,
2425 	},
2426 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2427 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2428 	.connector_type = DRM_MODE_CONNECTOR_eDP,
2429 };
2430 
2431 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2432 	.clock = 69300,
2433 	.hdisplay = 1366,
2434 	.hsync_start = 1366 + 16,
2435 	.hsync_end = 1366 + 16 + 34,
2436 	.htotal = 1366 + 16 + 34 + 50,
2437 	.vdisplay = 768,
2438 	.vsync_start = 768 + 2,
2439 	.vsync_end = 768 + 2 + 6,
2440 	.vtotal = 768 + 2 + 6 + 12,
2441 };
2442 
2443 static const struct panel_desc innolux_n156bge_l21 = {
2444 	.modes = &innolux_n156bge_l21_mode,
2445 	.num_modes = 1,
2446 	.bpc = 6,
2447 	.size = {
2448 		.width = 344,
2449 		.height = 193,
2450 	},
2451 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2452 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2453 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2454 };
2455 
2456 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
2457 	.clock = 206016,
2458 	.hdisplay = 2160,
2459 	.hsync_start = 2160 + 48,
2460 	.hsync_end = 2160 + 48 + 32,
2461 	.htotal = 2160 + 48 + 32 + 80,
2462 	.vdisplay = 1440,
2463 	.vsync_start = 1440 + 3,
2464 	.vsync_end = 1440 + 3 + 10,
2465 	.vtotal = 1440 + 3 + 10 + 27,
2466 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2467 };
2468 
2469 static const struct panel_desc innolux_p120zdg_bf1 = {
2470 	.modes = &innolux_p120zdg_bf1_mode,
2471 	.num_modes = 1,
2472 	.bpc = 8,
2473 	.size = {
2474 		.width = 254,
2475 		.height = 169,
2476 	},
2477 	.delay = {
2478 		.hpd_absent_delay = 200,
2479 		.unprepare = 500,
2480 	},
2481 };
2482 
2483 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2484 	.clock = 51501,
2485 	.hdisplay = 1024,
2486 	.hsync_start = 1024 + 128,
2487 	.hsync_end = 1024 + 128 + 64,
2488 	.htotal = 1024 + 128 + 64 + 128,
2489 	.vdisplay = 600,
2490 	.vsync_start = 600 + 16,
2491 	.vsync_end = 600 + 16 + 4,
2492 	.vtotal = 600 + 16 + 4 + 16,
2493 };
2494 
2495 static const struct panel_desc innolux_zj070na_01p = {
2496 	.modes = &innolux_zj070na_01p_mode,
2497 	.num_modes = 1,
2498 	.bpc = 6,
2499 	.size = {
2500 		.width = 154,
2501 		.height = 90,
2502 	},
2503 };
2504 
2505 static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2506 	.clock = 138778,
2507 	.hdisplay = 1920,
2508 	.hsync_start = 1920 + 24,
2509 	.hsync_end = 1920 + 24 + 48,
2510 	.htotal = 1920 + 24 + 48 + 88,
2511 	.vdisplay = 1080,
2512 	.vsync_start = 1080 + 3,
2513 	.vsync_end = 1080 + 3 + 12,
2514 	.vtotal = 1080 + 3 + 12 + 17,
2515 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2516 };
2517 
2518 static const struct panel_desc ivo_m133nwf4_r0 = {
2519 	.modes = &ivo_m133nwf4_r0_mode,
2520 	.num_modes = 1,
2521 	.bpc = 8,
2522 	.size = {
2523 		.width = 294,
2524 		.height = 165,
2525 	},
2526 	.delay = {
2527 		.hpd_absent_delay = 200,
2528 		.unprepare = 500,
2529 	},
2530 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2531 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2532 	.connector_type = DRM_MODE_CONNECTOR_eDP,
2533 };
2534 
2535 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2536 	.clock = 81000,
2537 	.hdisplay = 1366,
2538 	.hsync_start = 1366 + 40,
2539 	.hsync_end = 1366 + 40 + 32,
2540 	.htotal = 1366 + 40 + 32 + 62,
2541 	.vdisplay = 768,
2542 	.vsync_start = 768 + 5,
2543 	.vsync_end = 768 + 5 + 5,
2544 	.vtotal = 768 + 5 + 5 + 122,
2545 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2546 };
2547 
2548 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2549 	.modes = &kingdisplay_kd116n21_30nv_a010_mode,
2550 	.num_modes = 1,
2551 	.bpc = 6,
2552 	.size = {
2553 		.width = 256,
2554 		.height = 144,
2555 	},
2556 	.delay = {
2557 		.hpd_absent_delay = 200,
2558 	},
2559 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2560 	.connector_type = DRM_MODE_CONNECTOR_eDP,
2561 };
2562 
2563 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2564 	.pixelclock = { 5580000, 5850000, 6200000 },
2565 	.hactive = { 320, 320, 320 },
2566 	.hfront_porch = { 30, 30, 30 },
2567 	.hback_porch = { 30, 30, 30 },
2568 	.hsync_len = { 1, 5, 17 },
2569 	.vactive = { 240, 240, 240 },
2570 	.vfront_porch = { 6, 6, 6 },
2571 	.vback_porch = { 5, 5, 5 },
2572 	.vsync_len = { 1, 2, 11 },
2573 	.flags = DISPLAY_FLAGS_DE_HIGH,
2574 };
2575 
2576 static const struct panel_desc koe_tx14d24vm1bpa = {
2577 	.timings = &koe_tx14d24vm1bpa_timing,
2578 	.num_timings = 1,
2579 	.bpc = 6,
2580 	.size = {
2581 		.width = 115,
2582 		.height = 86,
2583 	},
2584 };
2585 
2586 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2587 	.pixelclock = { 151820000, 156720000, 159780000 },
2588 	.hactive = { 1920, 1920, 1920 },
2589 	.hfront_porch = { 105, 130, 142 },
2590 	.hback_porch = { 45, 70, 82 },
2591 	.hsync_len = { 30, 30, 30 },
2592 	.vactive = { 1200, 1200, 1200},
2593 	.vfront_porch = { 3, 5, 10 },
2594 	.vback_porch = { 2, 5, 10 },
2595 	.vsync_len = { 5, 5, 5 },
2596 };
2597 
2598 static const struct panel_desc koe_tx26d202vm0bwa = {
2599 	.timings = &koe_tx26d202vm0bwa_timing,
2600 	.num_timings = 1,
2601 	.bpc = 8,
2602 	.size = {
2603 		.width = 217,
2604 		.height = 136,
2605 	},
2606 	.delay = {
2607 		.prepare = 1000,
2608 		.enable = 1000,
2609 		.unprepare = 1000,
2610 		.disable = 1000,
2611 	},
2612 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2613 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2614 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2615 };
2616 
2617 static const struct display_timing koe_tx31d200vm0baa_timing = {
2618 	.pixelclock = { 39600000, 43200000, 48000000 },
2619 	.hactive = { 1280, 1280, 1280 },
2620 	.hfront_porch = { 16, 36, 56 },
2621 	.hback_porch = { 16, 36, 56 },
2622 	.hsync_len = { 8, 8, 8 },
2623 	.vactive = { 480, 480, 480 },
2624 	.vfront_porch = { 6, 21, 33 },
2625 	.vback_porch = { 6, 21, 33 },
2626 	.vsync_len = { 8, 8, 8 },
2627 	.flags = DISPLAY_FLAGS_DE_HIGH,
2628 };
2629 
2630 static const struct panel_desc koe_tx31d200vm0baa = {
2631 	.timings = &koe_tx31d200vm0baa_timing,
2632 	.num_timings = 1,
2633 	.bpc = 6,
2634 	.size = {
2635 		.width = 292,
2636 		.height = 109,
2637 	},
2638 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2639 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2640 };
2641 
2642 static const struct display_timing kyo_tcg121xglp_timing = {
2643 	.pixelclock = { 52000000, 65000000, 71000000 },
2644 	.hactive = { 1024, 1024, 1024 },
2645 	.hfront_porch = { 2, 2, 2 },
2646 	.hback_porch = { 2, 2, 2 },
2647 	.hsync_len = { 86, 124, 244 },
2648 	.vactive = { 768, 768, 768 },
2649 	.vfront_porch = { 2, 2, 2 },
2650 	.vback_porch = { 2, 2, 2 },
2651 	.vsync_len = { 6, 34, 73 },
2652 	.flags = DISPLAY_FLAGS_DE_HIGH,
2653 };
2654 
2655 static const struct panel_desc kyo_tcg121xglp = {
2656 	.timings = &kyo_tcg121xglp_timing,
2657 	.num_timings = 1,
2658 	.bpc = 8,
2659 	.size = {
2660 		.width = 246,
2661 		.height = 184,
2662 	},
2663 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2664 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2665 };
2666 
2667 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2668 	.clock = 7000,
2669 	.hdisplay = 320,
2670 	.hsync_start = 320 + 20,
2671 	.hsync_end = 320 + 20 + 30,
2672 	.htotal = 320 + 20 + 30 + 38,
2673 	.vdisplay = 240,
2674 	.vsync_start = 240 + 4,
2675 	.vsync_end = 240 + 4 + 3,
2676 	.vtotal = 240 + 4 + 3 + 15,
2677 };
2678 
2679 static const struct panel_desc lemaker_bl035_rgb_002 = {
2680 	.modes = &lemaker_bl035_rgb_002_mode,
2681 	.num_modes = 1,
2682 	.size = {
2683 		.width = 70,
2684 		.height = 52,
2685 	},
2686 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2687 	.bus_flags = DRM_BUS_FLAG_DE_LOW,
2688 };
2689 
2690 static const struct drm_display_mode lg_lb070wv8_mode = {
2691 	.clock = 33246,
2692 	.hdisplay = 800,
2693 	.hsync_start = 800 + 88,
2694 	.hsync_end = 800 + 88 + 80,
2695 	.htotal = 800 + 88 + 80 + 88,
2696 	.vdisplay = 480,
2697 	.vsync_start = 480 + 10,
2698 	.vsync_end = 480 + 10 + 25,
2699 	.vtotal = 480 + 10 + 25 + 10,
2700 };
2701 
2702 static const struct panel_desc lg_lb070wv8 = {
2703 	.modes = &lg_lb070wv8_mode,
2704 	.num_modes = 1,
2705 	.bpc = 8,
2706 	.size = {
2707 		.width = 151,
2708 		.height = 91,
2709 	},
2710 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2711 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2712 };
2713 
2714 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2715 	.clock = 200000,
2716 	.hdisplay = 1536,
2717 	.hsync_start = 1536 + 12,
2718 	.hsync_end = 1536 + 12 + 16,
2719 	.htotal = 1536 + 12 + 16 + 48,
2720 	.vdisplay = 2048,
2721 	.vsync_start = 2048 + 8,
2722 	.vsync_end = 2048 + 8 + 4,
2723 	.vtotal = 2048 + 8 + 4 + 8,
2724 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2725 };
2726 
2727 static const struct panel_desc lg_lp079qx1_sp0v = {
2728 	.modes = &lg_lp079qx1_sp0v_mode,
2729 	.num_modes = 1,
2730 	.size = {
2731 		.width = 129,
2732 		.height = 171,
2733 	},
2734 };
2735 
2736 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2737 	.clock = 205210,
2738 	.hdisplay = 2048,
2739 	.hsync_start = 2048 + 150,
2740 	.hsync_end = 2048 + 150 + 5,
2741 	.htotal = 2048 + 150 + 5 + 5,
2742 	.vdisplay = 1536,
2743 	.vsync_start = 1536 + 3,
2744 	.vsync_end = 1536 + 3 + 1,
2745 	.vtotal = 1536 + 3 + 1 + 9,
2746 };
2747 
2748 static const struct panel_desc lg_lp097qx1_spa1 = {
2749 	.modes = &lg_lp097qx1_spa1_mode,
2750 	.num_modes = 1,
2751 	.size = {
2752 		.width = 208,
2753 		.height = 147,
2754 	},
2755 };
2756 
2757 static const struct drm_display_mode lg_lp120up1_mode = {
2758 	.clock = 162300,
2759 	.hdisplay = 1920,
2760 	.hsync_start = 1920 + 40,
2761 	.hsync_end = 1920 + 40 + 40,
2762 	.htotal = 1920 + 40 + 40+ 80,
2763 	.vdisplay = 1280,
2764 	.vsync_start = 1280 + 4,
2765 	.vsync_end = 1280 + 4 + 4,
2766 	.vtotal = 1280 + 4 + 4 + 12,
2767 };
2768 
2769 static const struct panel_desc lg_lp120up1 = {
2770 	.modes = &lg_lp120up1_mode,
2771 	.num_modes = 1,
2772 	.bpc = 8,
2773 	.size = {
2774 		.width = 267,
2775 		.height = 183,
2776 	},
2777 	.connector_type = DRM_MODE_CONNECTOR_eDP,
2778 };
2779 
2780 static const struct drm_display_mode lg_lp129qe_mode = {
2781 	.clock = 285250,
2782 	.hdisplay = 2560,
2783 	.hsync_start = 2560 + 48,
2784 	.hsync_end = 2560 + 48 + 32,
2785 	.htotal = 2560 + 48 + 32 + 80,
2786 	.vdisplay = 1700,
2787 	.vsync_start = 1700 + 3,
2788 	.vsync_end = 1700 + 3 + 10,
2789 	.vtotal = 1700 + 3 + 10 + 36,
2790 };
2791 
2792 static const struct panel_desc lg_lp129qe = {
2793 	.modes = &lg_lp129qe_mode,
2794 	.num_modes = 1,
2795 	.bpc = 8,
2796 	.size = {
2797 		.width = 272,
2798 		.height = 181,
2799 	},
2800 };
2801 
2802 static const struct display_timing logictechno_lt161010_2nh_timing = {
2803 	.pixelclock = { 26400000, 33300000, 46800000 },
2804 	.hactive = { 800, 800, 800 },
2805 	.hfront_porch = { 16, 210, 354 },
2806 	.hback_porch = { 46, 46, 46 },
2807 	.hsync_len = { 1, 20, 40 },
2808 	.vactive = { 480, 480, 480 },
2809 	.vfront_porch = { 7, 22, 147 },
2810 	.vback_porch = { 23, 23, 23 },
2811 	.vsync_len = { 1, 10, 20 },
2812 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2813 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2814 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2815 };
2816 
2817 static const struct panel_desc logictechno_lt161010_2nh = {
2818 	.timings = &logictechno_lt161010_2nh_timing,
2819 	.num_timings = 1,
2820 	.size = {
2821 		.width = 154,
2822 		.height = 86,
2823 	},
2824 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2825 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2826 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2827 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2828 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2829 };
2830 
2831 static const struct display_timing logictechno_lt170410_2whc_timing = {
2832 	.pixelclock = { 68900000, 71100000, 73400000 },
2833 	.hactive = { 1280, 1280, 1280 },
2834 	.hfront_porch = { 23, 60, 71 },
2835 	.hback_porch = { 23, 60, 71 },
2836 	.hsync_len = { 15, 40, 47 },
2837 	.vactive = { 800, 800, 800 },
2838 	.vfront_porch = { 5, 7, 10 },
2839 	.vback_porch = { 5, 7, 10 },
2840 	.vsync_len = { 6, 9, 12 },
2841 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2842 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2843 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2844 };
2845 
2846 static const struct panel_desc logictechno_lt170410_2whc = {
2847 	.timings = &logictechno_lt170410_2whc_timing,
2848 	.num_timings = 1,
2849 	.size = {
2850 		.width = 217,
2851 		.height = 136,
2852 	},
2853 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2854 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2855 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2856 };
2857 
2858 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2859 	.clock = 30400,
2860 	.hdisplay = 800,
2861 	.hsync_start = 800 + 0,
2862 	.hsync_end = 800 + 1,
2863 	.htotal = 800 + 0 + 1 + 160,
2864 	.vdisplay = 480,
2865 	.vsync_start = 480 + 0,
2866 	.vsync_end = 480 + 48 + 1,
2867 	.vtotal = 480 + 48 + 1 + 0,
2868 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2869 };
2870 
2871 static const struct drm_display_mode logicpd_type_28_mode = {
2872 	.clock = 9107,
2873 	.hdisplay = 480,
2874 	.hsync_start = 480 + 3,
2875 	.hsync_end = 480 + 3 + 42,
2876 	.htotal = 480 + 3 + 42 + 2,
2877 
2878 	.vdisplay = 272,
2879 	.vsync_start = 272 + 2,
2880 	.vsync_end = 272 + 2 + 11,
2881 	.vtotal = 272 + 2 + 11 + 3,
2882 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2883 };
2884 
2885 static const struct panel_desc logicpd_type_28 = {
2886 	.modes = &logicpd_type_28_mode,
2887 	.num_modes = 1,
2888 	.bpc = 8,
2889 	.size = {
2890 		.width = 105,
2891 		.height = 67,
2892 	},
2893 	.delay = {
2894 		.prepare = 200,
2895 		.enable = 200,
2896 		.unprepare = 200,
2897 		.disable = 200,
2898 	},
2899 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2900 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2901 		     DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2902 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2903 };
2904 
2905 static const struct panel_desc mitsubishi_aa070mc01 = {
2906 	.modes = &mitsubishi_aa070mc01_mode,
2907 	.num_modes = 1,
2908 	.bpc = 8,
2909 	.size = {
2910 		.width = 152,
2911 		.height = 91,
2912 	},
2913 
2914 	.delay = {
2915 		.enable = 200,
2916 		.unprepare = 200,
2917 		.disable = 400,
2918 	},
2919 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2920 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2921 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2922 };
2923 
2924 static const struct display_timing nec_nl12880bc20_05_timing = {
2925 	.pixelclock = { 67000000, 71000000, 75000000 },
2926 	.hactive = { 1280, 1280, 1280 },
2927 	.hfront_porch = { 2, 30, 30 },
2928 	.hback_porch = { 6, 100, 100 },
2929 	.hsync_len = { 2, 30, 30 },
2930 	.vactive = { 800, 800, 800 },
2931 	.vfront_porch = { 5, 5, 5 },
2932 	.vback_porch = { 11, 11, 11 },
2933 	.vsync_len = { 7, 7, 7 },
2934 };
2935 
2936 static const struct panel_desc nec_nl12880bc20_05 = {
2937 	.timings = &nec_nl12880bc20_05_timing,
2938 	.num_timings = 1,
2939 	.bpc = 8,
2940 	.size = {
2941 		.width = 261,
2942 		.height = 163,
2943 	},
2944 	.delay = {
2945 		.enable = 50,
2946 		.disable = 50,
2947 	},
2948 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2949 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2950 };
2951 
2952 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2953 	.clock = 10870,
2954 	.hdisplay = 480,
2955 	.hsync_start = 480 + 2,
2956 	.hsync_end = 480 + 2 + 41,
2957 	.htotal = 480 + 2 + 41 + 2,
2958 	.vdisplay = 272,
2959 	.vsync_start = 272 + 2,
2960 	.vsync_end = 272 + 2 + 4,
2961 	.vtotal = 272 + 2 + 4 + 2,
2962 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2963 };
2964 
2965 static const struct panel_desc nec_nl4827hc19_05b = {
2966 	.modes = &nec_nl4827hc19_05b_mode,
2967 	.num_modes = 1,
2968 	.bpc = 8,
2969 	.size = {
2970 		.width = 95,
2971 		.height = 54,
2972 	},
2973 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2974 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2975 };
2976 
2977 static const struct drm_display_mode netron_dy_e231732_mode = {
2978 	.clock = 66000,
2979 	.hdisplay = 1024,
2980 	.hsync_start = 1024 + 160,
2981 	.hsync_end = 1024 + 160 + 70,
2982 	.htotal = 1024 + 160 + 70 + 90,
2983 	.vdisplay = 600,
2984 	.vsync_start = 600 + 127,
2985 	.vsync_end = 600 + 127 + 20,
2986 	.vtotal = 600 + 127 + 20 + 3,
2987 };
2988 
2989 static const struct panel_desc netron_dy_e231732 = {
2990 	.modes = &netron_dy_e231732_mode,
2991 	.num_modes = 1,
2992 	.size = {
2993 		.width = 154,
2994 		.height = 87,
2995 	},
2996 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2997 };
2998 
2999 static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3000 	{
3001 		.clock = 138500,
3002 		.hdisplay = 1920,
3003 		.hsync_start = 1920 + 48,
3004 		.hsync_end = 1920 + 48 + 32,
3005 		.htotal = 1920 + 48 + 32 + 80,
3006 		.vdisplay = 1080,
3007 		.vsync_start = 1080 + 3,
3008 		.vsync_end = 1080 + 3 + 5,
3009 		.vtotal = 1080 + 3 + 5 + 23,
3010 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3011 	}, {
3012 		.clock = 110920,
3013 		.hdisplay = 1920,
3014 		.hsync_start = 1920 + 48,
3015 		.hsync_end = 1920 + 48 + 32,
3016 		.htotal = 1920 + 48 + 32 + 80,
3017 		.vdisplay = 1080,
3018 		.vsync_start = 1080 + 3,
3019 		.vsync_end = 1080 + 3 + 5,
3020 		.vtotal = 1080 + 3 + 5 + 23,
3021 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3022 	}
3023 };
3024 
3025 static const struct panel_desc neweast_wjfh116008a = {
3026 	.modes = neweast_wjfh116008a_modes,
3027 	.num_modes = 2,
3028 	.bpc = 6,
3029 	.size = {
3030 		.width = 260,
3031 		.height = 150,
3032 	},
3033 	.delay = {
3034 		.prepare = 110,
3035 		.enable = 20,
3036 		.unprepare = 500,
3037 	},
3038 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3039 	.connector_type = DRM_MODE_CONNECTOR_eDP,
3040 };
3041 
3042 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3043 	.clock = 9000,
3044 	.hdisplay = 480,
3045 	.hsync_start = 480 + 2,
3046 	.hsync_end = 480 + 2 + 41,
3047 	.htotal = 480 + 2 + 41 + 2,
3048 	.vdisplay = 272,
3049 	.vsync_start = 272 + 2,
3050 	.vsync_end = 272 + 2 + 10,
3051 	.vtotal = 272 + 2 + 10 + 2,
3052 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3053 };
3054 
3055 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3056 	.modes = &newhaven_nhd_43_480272ef_atxl_mode,
3057 	.num_modes = 1,
3058 	.bpc = 8,
3059 	.size = {
3060 		.width = 95,
3061 		.height = 54,
3062 	},
3063 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3064 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3065 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3066 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3067 };
3068 
3069 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3070 	.pixelclock = { 130000000, 148350000, 163000000 },
3071 	.hactive = { 1920, 1920, 1920 },
3072 	.hfront_porch = { 80, 100, 100 },
3073 	.hback_porch = { 100, 120, 120 },
3074 	.hsync_len = { 50, 60, 60 },
3075 	.vactive = { 1080, 1080, 1080 },
3076 	.vfront_porch = { 12, 30, 30 },
3077 	.vback_porch = { 4, 10, 10 },
3078 	.vsync_len = { 4, 5, 5 },
3079 };
3080 
3081 static const struct panel_desc nlt_nl192108ac18_02d = {
3082 	.timings = &nlt_nl192108ac18_02d_timing,
3083 	.num_timings = 1,
3084 	.bpc = 8,
3085 	.size = {
3086 		.width = 344,
3087 		.height = 194,
3088 	},
3089 	.delay = {
3090 		.unprepare = 500,
3091 	},
3092 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3093 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3094 };
3095 
3096 static const struct drm_display_mode nvd_9128_mode = {
3097 	.clock = 29500,
3098 	.hdisplay = 800,
3099 	.hsync_start = 800 + 130,
3100 	.hsync_end = 800 + 130 + 98,
3101 	.htotal = 800 + 0 + 130 + 98,
3102 	.vdisplay = 480,
3103 	.vsync_start = 480 + 10,
3104 	.vsync_end = 480 + 10 + 50,
3105 	.vtotal = 480 + 0 + 10 + 50,
3106 };
3107 
3108 static const struct panel_desc nvd_9128 = {
3109 	.modes = &nvd_9128_mode,
3110 	.num_modes = 1,
3111 	.bpc = 8,
3112 	.size = {
3113 		.width = 156,
3114 		.height = 88,
3115 	},
3116 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3117 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3118 };
3119 
3120 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3121 	.pixelclock = { 30000000, 30000000, 40000000 },
3122 	.hactive = { 800, 800, 800 },
3123 	.hfront_porch = { 40, 40, 40 },
3124 	.hback_porch = { 40, 40, 40 },
3125 	.hsync_len = { 1, 48, 48 },
3126 	.vactive = { 480, 480, 480 },
3127 	.vfront_porch = { 13, 13, 13 },
3128 	.vback_porch = { 29, 29, 29 },
3129 	.vsync_len = { 3, 3, 3 },
3130 	.flags = DISPLAY_FLAGS_DE_HIGH,
3131 };
3132 
3133 static const struct panel_desc okaya_rs800480t_7x0gp = {
3134 	.timings = &okaya_rs800480t_7x0gp_timing,
3135 	.num_timings = 1,
3136 	.bpc = 6,
3137 	.size = {
3138 		.width = 154,
3139 		.height = 87,
3140 	},
3141 	.delay = {
3142 		.prepare = 41,
3143 		.enable = 50,
3144 		.unprepare = 41,
3145 		.disable = 50,
3146 	},
3147 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3148 };
3149 
3150 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3151 	.clock = 9000,
3152 	.hdisplay = 480,
3153 	.hsync_start = 480 + 5,
3154 	.hsync_end = 480 + 5 + 30,
3155 	.htotal = 480 + 5 + 30 + 10,
3156 	.vdisplay = 272,
3157 	.vsync_start = 272 + 8,
3158 	.vsync_end = 272 + 8 + 5,
3159 	.vtotal = 272 + 8 + 5 + 3,
3160 };
3161 
3162 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3163 	.modes = &olimex_lcd_olinuxino_43ts_mode,
3164 	.num_modes = 1,
3165 	.size = {
3166 		.width = 95,
3167 		.height = 54,
3168 	},
3169 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3170 };
3171 
3172 /*
3173  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3174  * pixel clocks, but this is the timing that was being used in the Adafruit
3175  * installation instructions.
3176  */
3177 static const struct drm_display_mode ontat_yx700wv03_mode = {
3178 	.clock = 29500,
3179 	.hdisplay = 800,
3180 	.hsync_start = 824,
3181 	.hsync_end = 896,
3182 	.htotal = 992,
3183 	.vdisplay = 480,
3184 	.vsync_start = 483,
3185 	.vsync_end = 493,
3186 	.vtotal = 500,
3187 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3188 };
3189 
3190 /*
3191  * Specification at:
3192  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3193  */
3194 static const struct panel_desc ontat_yx700wv03 = {
3195 	.modes = &ontat_yx700wv03_mode,
3196 	.num_modes = 1,
3197 	.bpc = 8,
3198 	.size = {
3199 		.width = 154,
3200 		.height = 83,
3201 	},
3202 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3203 };
3204 
3205 static const struct drm_display_mode ortustech_com37h3m_mode  = {
3206 	.clock = 22230,
3207 	.hdisplay = 480,
3208 	.hsync_start = 480 + 40,
3209 	.hsync_end = 480 + 40 + 10,
3210 	.htotal = 480 + 40 + 10 + 40,
3211 	.vdisplay = 640,
3212 	.vsync_start = 640 + 4,
3213 	.vsync_end = 640 + 4 + 2,
3214 	.vtotal = 640 + 4 + 2 + 4,
3215 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3216 };
3217 
3218 static const struct panel_desc ortustech_com37h3m = {
3219 	.modes = &ortustech_com37h3m_mode,
3220 	.num_modes = 1,
3221 	.bpc = 8,
3222 	.size = {
3223 		.width = 56,	/* 56.16mm */
3224 		.height = 75,	/* 74.88mm */
3225 	},
3226 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3227 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3228 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3229 };
3230 
3231 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
3232 	.clock = 25000,
3233 	.hdisplay = 480,
3234 	.hsync_start = 480 + 10,
3235 	.hsync_end = 480 + 10 + 10,
3236 	.htotal = 480 + 10 + 10 + 15,
3237 	.vdisplay = 800,
3238 	.vsync_start = 800 + 3,
3239 	.vsync_end = 800 + 3 + 3,
3240 	.vtotal = 800 + 3 + 3 + 3,
3241 };
3242 
3243 static const struct panel_desc ortustech_com43h4m85ulc = {
3244 	.modes = &ortustech_com43h4m85ulc_mode,
3245 	.num_modes = 1,
3246 	.bpc = 6,
3247 	.size = {
3248 		.width = 56,
3249 		.height = 93,
3250 	},
3251 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3252 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3253 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3254 };
3255 
3256 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
3257 	.clock = 33000,
3258 	.hdisplay = 800,
3259 	.hsync_start = 800 + 210,
3260 	.hsync_end = 800 + 210 + 30,
3261 	.htotal = 800 + 210 + 30 + 16,
3262 	.vdisplay = 480,
3263 	.vsync_start = 480 + 22,
3264 	.vsync_end = 480 + 22 + 13,
3265 	.vtotal = 480 + 22 + 13 + 10,
3266 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3267 };
3268 
3269 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3270 	.modes = &osddisplays_osd070t1718_19ts_mode,
3271 	.num_modes = 1,
3272 	.bpc = 8,
3273 	.size = {
3274 		.width = 152,
3275 		.height = 91,
3276 	},
3277 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3278 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3279 		DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3280 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3281 };
3282 
3283 static const struct drm_display_mode pda_91_00156_a0_mode = {
3284 	.clock = 33300,
3285 	.hdisplay = 800,
3286 	.hsync_start = 800 + 1,
3287 	.hsync_end = 800 + 1 + 64,
3288 	.htotal = 800 + 1 + 64 + 64,
3289 	.vdisplay = 480,
3290 	.vsync_start = 480 + 1,
3291 	.vsync_end = 480 + 1 + 23,
3292 	.vtotal = 480 + 1 + 23 + 22,
3293 };
3294 
3295 static const struct panel_desc pda_91_00156_a0  = {
3296 	.modes = &pda_91_00156_a0_mode,
3297 	.num_modes = 1,
3298 	.size = {
3299 		.width = 152,
3300 		.height = 91,
3301 	},
3302 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3303 };
3304 
3305 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3306 	.clock = 24750,
3307 	.hdisplay = 800,
3308 	.hsync_start = 800 + 54,
3309 	.hsync_end = 800 + 54 + 2,
3310 	.htotal = 800 + 54 + 2 + 44,
3311 	.vdisplay = 480,
3312 	.vsync_start = 480 + 49,
3313 	.vsync_end = 480 + 49 + 2,
3314 	.vtotal = 480 + 49 + 2 + 22,
3315 };
3316 
3317 static const struct panel_desc powertip_ph800480t013_idf02  = {
3318 	.modes = &powertip_ph800480t013_idf02_mode,
3319 	.num_modes = 1,
3320 	.size = {
3321 		.width = 152,
3322 		.height = 91,
3323 	},
3324 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
3325 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3326 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3327 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3328 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3329 };
3330 
3331 static const struct drm_display_mode qd43003c0_40_mode = {
3332 	.clock = 9000,
3333 	.hdisplay = 480,
3334 	.hsync_start = 480 + 8,
3335 	.hsync_end = 480 + 8 + 4,
3336 	.htotal = 480 + 8 + 4 + 39,
3337 	.vdisplay = 272,
3338 	.vsync_start = 272 + 4,
3339 	.vsync_end = 272 + 4 + 10,
3340 	.vtotal = 272 + 4 + 10 + 2,
3341 };
3342 
3343 static const struct panel_desc qd43003c0_40 = {
3344 	.modes = &qd43003c0_40_mode,
3345 	.num_modes = 1,
3346 	.bpc = 8,
3347 	.size = {
3348 		.width = 95,
3349 		.height = 53,
3350 	},
3351 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3352 };
3353 
3354 static const struct display_timing rocktech_rk070er9427_timing = {
3355 	.pixelclock = { 26400000, 33300000, 46800000 },
3356 	.hactive = { 800, 800, 800 },
3357 	.hfront_porch = { 16, 210, 354 },
3358 	.hback_porch = { 46, 46, 46 },
3359 	.hsync_len = { 1, 1, 1 },
3360 	.vactive = { 480, 480, 480 },
3361 	.vfront_porch = { 7, 22, 147 },
3362 	.vback_porch = { 23, 23, 23 },
3363 	.vsync_len = { 1, 1, 1 },
3364 	.flags = DISPLAY_FLAGS_DE_HIGH,
3365 };
3366 
3367 static const struct panel_desc rocktech_rk070er9427 = {
3368 	.timings = &rocktech_rk070er9427_timing,
3369 	.num_timings = 1,
3370 	.bpc = 6,
3371 	.size = {
3372 		.width = 154,
3373 		.height = 86,
3374 	},
3375 	.delay = {
3376 		.prepare = 41,
3377 		.enable = 50,
3378 		.unprepare = 41,
3379 		.disable = 50,
3380 	},
3381 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3382 };
3383 
3384 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3385 	.clock = 71100,
3386 	.hdisplay = 1280,
3387 	.hsync_start = 1280 + 48,
3388 	.hsync_end = 1280 + 48 + 32,
3389 	.htotal = 1280 + 48 + 32 + 80,
3390 	.vdisplay = 800,
3391 	.vsync_start = 800 + 2,
3392 	.vsync_end = 800 + 2 + 5,
3393 	.vtotal = 800 + 2 + 5 + 16,
3394 };
3395 
3396 static const struct panel_desc rocktech_rk101ii01d_ct = {
3397 	.modes = &rocktech_rk101ii01d_ct_mode,
3398 	.num_modes = 1,
3399 	.size = {
3400 		.width = 217,
3401 		.height = 136,
3402 	},
3403 	.delay = {
3404 		.prepare = 50,
3405 		.disable = 50,
3406 	},
3407 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3408 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3409 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3410 };
3411 
3412 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3413 	.clock = 271560,
3414 	.hdisplay = 2560,
3415 	.hsync_start = 2560 + 48,
3416 	.hsync_end = 2560 + 48 + 32,
3417 	.htotal = 2560 + 48 + 32 + 80,
3418 	.vdisplay = 1600,
3419 	.vsync_start = 1600 + 2,
3420 	.vsync_end = 1600 + 2 + 5,
3421 	.vtotal = 1600 + 2 + 5 + 57,
3422 };
3423 
3424 static const struct panel_desc samsung_lsn122dl01_c01 = {
3425 	.modes = &samsung_lsn122dl01_c01_mode,
3426 	.num_modes = 1,
3427 	.size = {
3428 		.width = 263,
3429 		.height = 164,
3430 	},
3431 };
3432 
3433 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3434 	.clock = 54030,
3435 	.hdisplay = 1024,
3436 	.hsync_start = 1024 + 24,
3437 	.hsync_end = 1024 + 24 + 136,
3438 	.htotal = 1024 + 24 + 136 + 160,
3439 	.vdisplay = 600,
3440 	.vsync_start = 600 + 3,
3441 	.vsync_end = 600 + 3 + 6,
3442 	.vtotal = 600 + 3 + 6 + 61,
3443 };
3444 
3445 static const struct panel_desc samsung_ltn101nt05 = {
3446 	.modes = &samsung_ltn101nt05_mode,
3447 	.num_modes = 1,
3448 	.bpc = 6,
3449 	.size = {
3450 		.width = 223,
3451 		.height = 125,
3452 	},
3453 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3454 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3455 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3456 };
3457 
3458 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3459 	.clock = 76300,
3460 	.hdisplay = 1366,
3461 	.hsync_start = 1366 + 64,
3462 	.hsync_end = 1366 + 64 + 48,
3463 	.htotal = 1366 + 64 + 48 + 128,
3464 	.vdisplay = 768,
3465 	.vsync_start = 768 + 2,
3466 	.vsync_end = 768 + 2 + 5,
3467 	.vtotal = 768 + 2 + 5 + 17,
3468 };
3469 
3470 static const struct panel_desc samsung_ltn140at29_301 = {
3471 	.modes = &samsung_ltn140at29_301_mode,
3472 	.num_modes = 1,
3473 	.bpc = 6,
3474 	.size = {
3475 		.width = 320,
3476 		.height = 187,
3477 	},
3478 };
3479 
3480 static const struct display_timing satoz_sat050at40h12r2_timing = {
3481 	.pixelclock = {33300000, 33300000, 50000000},
3482 	.hactive = {800, 800, 800},
3483 	.hfront_porch = {16, 210, 354},
3484 	.hback_porch = {46, 46, 46},
3485 	.hsync_len = {1, 1, 40},
3486 	.vactive = {480, 480, 480},
3487 	.vfront_porch = {7, 22, 147},
3488 	.vback_porch = {23, 23, 23},
3489 	.vsync_len = {1, 1, 20},
3490 };
3491 
3492 static const struct panel_desc satoz_sat050at40h12r2 = {
3493 	.timings = &satoz_sat050at40h12r2_timing,
3494 	.num_timings = 1,
3495 	.bpc = 8,
3496 	.size = {
3497 		.width = 108,
3498 		.height = 65,
3499 	},
3500 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3501 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3502 };
3503 
3504 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3505 	.clock = 168480,
3506 	.hdisplay = 1920,
3507 	.hsync_start = 1920 + 48,
3508 	.hsync_end = 1920 + 48 + 32,
3509 	.htotal = 1920 + 48 + 32 + 80,
3510 	.vdisplay = 1280,
3511 	.vsync_start = 1280 + 3,
3512 	.vsync_end = 1280 + 3 + 10,
3513 	.vtotal = 1280 + 3 + 10 + 57,
3514 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3515 };
3516 
3517 static const struct panel_desc sharp_ld_d5116z01b = {
3518 	.modes = &sharp_ld_d5116z01b_mode,
3519 	.num_modes = 1,
3520 	.bpc = 8,
3521 	.size = {
3522 		.width = 260,
3523 		.height = 120,
3524 	},
3525 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3526 	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3527 };
3528 
3529 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3530 	.clock = 33260,
3531 	.hdisplay = 800,
3532 	.hsync_start = 800 + 64,
3533 	.hsync_end = 800 + 64 + 128,
3534 	.htotal = 800 + 64 + 128 + 64,
3535 	.vdisplay = 480,
3536 	.vsync_start = 480 + 8,
3537 	.vsync_end = 480 + 8 + 2,
3538 	.vtotal = 480 + 8 + 2 + 35,
3539 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3540 };
3541 
3542 static const struct panel_desc sharp_lq070y3dg3b = {
3543 	.modes = &sharp_lq070y3dg3b_mode,
3544 	.num_modes = 1,
3545 	.bpc = 8,
3546 	.size = {
3547 		.width = 152,	/* 152.4mm */
3548 		.height = 91,	/* 91.4mm */
3549 	},
3550 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3551 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3552 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3553 };
3554 
3555 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3556 	.clock = 5500,
3557 	.hdisplay = 240,
3558 	.hsync_start = 240 + 16,
3559 	.hsync_end = 240 + 16 + 7,
3560 	.htotal = 240 + 16 + 7 + 5,
3561 	.vdisplay = 320,
3562 	.vsync_start = 320 + 9,
3563 	.vsync_end = 320 + 9 + 1,
3564 	.vtotal = 320 + 9 + 1 + 7,
3565 };
3566 
3567 static const struct panel_desc sharp_lq035q7db03 = {
3568 	.modes = &sharp_lq035q7db03_mode,
3569 	.num_modes = 1,
3570 	.bpc = 6,
3571 	.size = {
3572 		.width = 54,
3573 		.height = 72,
3574 	},
3575 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3576 };
3577 
3578 static const struct display_timing sharp_lq101k1ly04_timing = {
3579 	.pixelclock = { 60000000, 65000000, 80000000 },
3580 	.hactive = { 1280, 1280, 1280 },
3581 	.hfront_porch = { 20, 20, 20 },
3582 	.hback_porch = { 20, 20, 20 },
3583 	.hsync_len = { 10, 10, 10 },
3584 	.vactive = { 800, 800, 800 },
3585 	.vfront_porch = { 4, 4, 4 },
3586 	.vback_porch = { 4, 4, 4 },
3587 	.vsync_len = { 4, 4, 4 },
3588 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3589 };
3590 
3591 static const struct panel_desc sharp_lq101k1ly04 = {
3592 	.timings = &sharp_lq101k1ly04_timing,
3593 	.num_timings = 1,
3594 	.bpc = 8,
3595 	.size = {
3596 		.width = 217,
3597 		.height = 136,
3598 	},
3599 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3600 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3601 };
3602 
3603 static const struct display_timing sharp_lq123p1jx31_timing = {
3604 	.pixelclock = { 252750000, 252750000, 266604720 },
3605 	.hactive = { 2400, 2400, 2400 },
3606 	.hfront_porch = { 48, 48, 48 },
3607 	.hback_porch = { 80, 80, 84 },
3608 	.hsync_len = { 32, 32, 32 },
3609 	.vactive = { 1600, 1600, 1600 },
3610 	.vfront_porch = { 3, 3, 3 },
3611 	.vback_porch = { 33, 33, 120 },
3612 	.vsync_len = { 10, 10, 10 },
3613 	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
3614 };
3615 
3616 static const struct panel_desc sharp_lq123p1jx31 = {
3617 	.timings = &sharp_lq123p1jx31_timing,
3618 	.num_timings = 1,
3619 	.bpc = 8,
3620 	.size = {
3621 		.width = 259,
3622 		.height = 173,
3623 	},
3624 	.delay = {
3625 		.prepare = 110,
3626 		.enable = 50,
3627 		.unprepare = 550,
3628 	},
3629 };
3630 
3631 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3632 	{ /* 50 Hz */
3633 		.clock = 3000,
3634 		.hdisplay = 240,
3635 		.hsync_start = 240 + 58,
3636 		.hsync_end = 240 + 58 + 1,
3637 		.htotal = 240 + 58 + 1 + 1,
3638 		.vdisplay = 160,
3639 		.vsync_start = 160 + 24,
3640 		.vsync_end = 160 + 24 + 10,
3641 		.vtotal = 160 + 24 + 10 + 6,
3642 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3643 	},
3644 	{ /* 60 Hz */
3645 		.clock = 3000,
3646 		.hdisplay = 240,
3647 		.hsync_start = 240 + 8,
3648 		.hsync_end = 240 + 8 + 1,
3649 		.htotal = 240 + 8 + 1 + 1,
3650 		.vdisplay = 160,
3651 		.vsync_start = 160 + 24,
3652 		.vsync_end = 160 + 24 + 10,
3653 		.vtotal = 160 + 24 + 10 + 6,
3654 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3655 	},
3656 };
3657 
3658 static const struct panel_desc sharp_ls020b1dd01d = {
3659 	.modes = sharp_ls020b1dd01d_modes,
3660 	.num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3661 	.bpc = 6,
3662 	.size = {
3663 		.width = 42,
3664 		.height = 28,
3665 	},
3666 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3667 	.bus_flags = DRM_BUS_FLAG_DE_HIGH
3668 		   | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3669 		   | DRM_BUS_FLAG_SHARP_SIGNALS,
3670 };
3671 
3672 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3673 	.clock = 33300,
3674 	.hdisplay = 800,
3675 	.hsync_start = 800 + 1,
3676 	.hsync_end = 800 + 1 + 64,
3677 	.htotal = 800 + 1 + 64 + 64,
3678 	.vdisplay = 480,
3679 	.vsync_start = 480 + 1,
3680 	.vsync_end = 480 + 1 + 23,
3681 	.vtotal = 480 + 1 + 23 + 22,
3682 };
3683 
3684 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3685 	.modes = &shelly_sca07010_bfn_lnn_mode,
3686 	.num_modes = 1,
3687 	.size = {
3688 		.width = 152,
3689 		.height = 91,
3690 	},
3691 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3692 };
3693 
3694 static const struct drm_display_mode starry_kr070pe2t_mode = {
3695 	.clock = 33000,
3696 	.hdisplay = 800,
3697 	.hsync_start = 800 + 209,
3698 	.hsync_end = 800 + 209 + 1,
3699 	.htotal = 800 + 209 + 1 + 45,
3700 	.vdisplay = 480,
3701 	.vsync_start = 480 + 22,
3702 	.vsync_end = 480 + 22 + 1,
3703 	.vtotal = 480 + 22 + 1 + 22,
3704 };
3705 
3706 static const struct panel_desc starry_kr070pe2t = {
3707 	.modes = &starry_kr070pe2t_mode,
3708 	.num_modes = 1,
3709 	.bpc = 8,
3710 	.size = {
3711 		.width = 152,
3712 		.height = 86,
3713 	},
3714 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3715 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3716 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3717 };
3718 
3719 static const struct drm_display_mode starry_kr122ea0sra_mode = {
3720 	.clock = 147000,
3721 	.hdisplay = 1920,
3722 	.hsync_start = 1920 + 16,
3723 	.hsync_end = 1920 + 16 + 16,
3724 	.htotal = 1920 + 16 + 16 + 32,
3725 	.vdisplay = 1200,
3726 	.vsync_start = 1200 + 15,
3727 	.vsync_end = 1200 + 15 + 2,
3728 	.vtotal = 1200 + 15 + 2 + 18,
3729 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3730 };
3731 
3732 static const struct panel_desc starry_kr122ea0sra = {
3733 	.modes = &starry_kr122ea0sra_mode,
3734 	.num_modes = 1,
3735 	.size = {
3736 		.width = 263,
3737 		.height = 164,
3738 	},
3739 	.delay = {
3740 		.prepare = 10 + 200,
3741 		.enable = 50,
3742 		.unprepare = 10 + 500,
3743 	},
3744 };
3745 
3746 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3747 	.clock = 30000,
3748 	.hdisplay = 800,
3749 	.hsync_start = 800 + 39,
3750 	.hsync_end = 800 + 39 + 47,
3751 	.htotal = 800 + 39 + 47 + 39,
3752 	.vdisplay = 480,
3753 	.vsync_start = 480 + 13,
3754 	.vsync_end = 480 + 13 + 2,
3755 	.vtotal = 480 + 13 + 2 + 29,
3756 };
3757 
3758 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3759 	.modes = &tfc_s9700rtwv43tr_01b_mode,
3760 	.num_modes = 1,
3761 	.bpc = 8,
3762 	.size = {
3763 		.width = 155,
3764 		.height = 90,
3765 	},
3766 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3767 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3768 };
3769 
3770 static const struct display_timing tianma_tm070jdhg30_timing = {
3771 	.pixelclock = { 62600000, 68200000, 78100000 },
3772 	.hactive = { 1280, 1280, 1280 },
3773 	.hfront_porch = { 15, 64, 159 },
3774 	.hback_porch = { 5, 5, 5 },
3775 	.hsync_len = { 1, 1, 256 },
3776 	.vactive = { 800, 800, 800 },
3777 	.vfront_porch = { 3, 40, 99 },
3778 	.vback_porch = { 2, 2, 2 },
3779 	.vsync_len = { 1, 1, 128 },
3780 	.flags = DISPLAY_FLAGS_DE_HIGH,
3781 };
3782 
3783 static const struct panel_desc tianma_tm070jdhg30 = {
3784 	.timings = &tianma_tm070jdhg30_timing,
3785 	.num_timings = 1,
3786 	.bpc = 8,
3787 	.size = {
3788 		.width = 151,
3789 		.height = 95,
3790 	},
3791 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3792 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3793 };
3794 
3795 static const struct panel_desc tianma_tm070jvhg33 = {
3796 	.timings = &tianma_tm070jdhg30_timing,
3797 	.num_timings = 1,
3798 	.bpc = 8,
3799 	.size = {
3800 		.width = 150,
3801 		.height = 94,
3802 	},
3803 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3804 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3805 };
3806 
3807 static const struct display_timing tianma_tm070rvhg71_timing = {
3808 	.pixelclock = { 27700000, 29200000, 39600000 },
3809 	.hactive = { 800, 800, 800 },
3810 	.hfront_porch = { 12, 40, 212 },
3811 	.hback_porch = { 88, 88, 88 },
3812 	.hsync_len = { 1, 1, 40 },
3813 	.vactive = { 480, 480, 480 },
3814 	.vfront_porch = { 1, 13, 88 },
3815 	.vback_porch = { 32, 32, 32 },
3816 	.vsync_len = { 1, 1, 3 },
3817 	.flags = DISPLAY_FLAGS_DE_HIGH,
3818 };
3819 
3820 static const struct panel_desc tianma_tm070rvhg71 = {
3821 	.timings = &tianma_tm070rvhg71_timing,
3822 	.num_timings = 1,
3823 	.bpc = 8,
3824 	.size = {
3825 		.width = 154,
3826 		.height = 86,
3827 	},
3828 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3829 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3830 };
3831 
3832 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3833 	{
3834 		.clock = 10000,
3835 		.hdisplay = 320,
3836 		.hsync_start = 320 + 50,
3837 		.hsync_end = 320 + 50 + 6,
3838 		.htotal = 320 + 50 + 6 + 38,
3839 		.vdisplay = 240,
3840 		.vsync_start = 240 + 3,
3841 		.vsync_end = 240 + 3 + 1,
3842 		.vtotal = 240 + 3 + 1 + 17,
3843 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3844 	},
3845 };
3846 
3847 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3848 	.modes = ti_nspire_cx_lcd_mode,
3849 	.num_modes = 1,
3850 	.bpc = 8,
3851 	.size = {
3852 		.width = 65,
3853 		.height = 49,
3854 	},
3855 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3856 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3857 };
3858 
3859 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3860 	{
3861 		.clock = 10000,
3862 		.hdisplay = 320,
3863 		.hsync_start = 320 + 6,
3864 		.hsync_end = 320 + 6 + 6,
3865 		.htotal = 320 + 6 + 6 + 6,
3866 		.vdisplay = 240,
3867 		.vsync_start = 240 + 0,
3868 		.vsync_end = 240 + 0 + 1,
3869 		.vtotal = 240 + 0 + 1 + 0,
3870 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3871 	},
3872 };
3873 
3874 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3875 	.modes = ti_nspire_classic_lcd_mode,
3876 	.num_modes = 1,
3877 	/* The grayscale panel has 8 bit for the color .. Y (black) */
3878 	.bpc = 8,
3879 	.size = {
3880 		.width = 71,
3881 		.height = 53,
3882 	},
3883 	/* This is the grayscale bus format */
3884 	.bus_format = MEDIA_BUS_FMT_Y8_1X8,
3885 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3886 };
3887 
3888 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3889 	.clock = 79500,
3890 	.hdisplay = 1280,
3891 	.hsync_start = 1280 + 192,
3892 	.hsync_end = 1280 + 192 + 128,
3893 	.htotal = 1280 + 192 + 128 + 64,
3894 	.vdisplay = 768,
3895 	.vsync_start = 768 + 20,
3896 	.vsync_end = 768 + 20 + 7,
3897 	.vtotal = 768 + 20 + 7 + 3,
3898 };
3899 
3900 static const struct panel_desc toshiba_lt089ac29000 = {
3901 	.modes = &toshiba_lt089ac29000_mode,
3902 	.num_modes = 1,
3903 	.size = {
3904 		.width = 194,
3905 		.height = 116,
3906 	},
3907 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3908 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3909 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3910 };
3911 
3912 static const struct drm_display_mode tpk_f07a_0102_mode = {
3913 	.clock = 33260,
3914 	.hdisplay = 800,
3915 	.hsync_start = 800 + 40,
3916 	.hsync_end = 800 + 40 + 128,
3917 	.htotal = 800 + 40 + 128 + 88,
3918 	.vdisplay = 480,
3919 	.vsync_start = 480 + 10,
3920 	.vsync_end = 480 + 10 + 2,
3921 	.vtotal = 480 + 10 + 2 + 33,
3922 };
3923 
3924 static const struct panel_desc tpk_f07a_0102 = {
3925 	.modes = &tpk_f07a_0102_mode,
3926 	.num_modes = 1,
3927 	.size = {
3928 		.width = 152,
3929 		.height = 91,
3930 	},
3931 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3932 };
3933 
3934 static const struct drm_display_mode tpk_f10a_0102_mode = {
3935 	.clock = 45000,
3936 	.hdisplay = 1024,
3937 	.hsync_start = 1024 + 176,
3938 	.hsync_end = 1024 + 176 + 5,
3939 	.htotal = 1024 + 176 + 5 + 88,
3940 	.vdisplay = 600,
3941 	.vsync_start = 600 + 20,
3942 	.vsync_end = 600 + 20 + 5,
3943 	.vtotal = 600 + 20 + 5 + 25,
3944 };
3945 
3946 static const struct panel_desc tpk_f10a_0102 = {
3947 	.modes = &tpk_f10a_0102_mode,
3948 	.num_modes = 1,
3949 	.size = {
3950 		.width = 223,
3951 		.height = 125,
3952 	},
3953 };
3954 
3955 static const struct display_timing urt_umsh_8596md_timing = {
3956 	.pixelclock = { 33260000, 33260000, 33260000 },
3957 	.hactive = { 800, 800, 800 },
3958 	.hfront_porch = { 41, 41, 41 },
3959 	.hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3960 	.hsync_len = { 71, 128, 128 },
3961 	.vactive = { 480, 480, 480 },
3962 	.vfront_porch = { 10, 10, 10 },
3963 	.vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3964 	.vsync_len = { 2, 2, 2 },
3965 	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3966 		DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3967 };
3968 
3969 static const struct panel_desc urt_umsh_8596md_lvds = {
3970 	.timings = &urt_umsh_8596md_timing,
3971 	.num_timings = 1,
3972 	.bpc = 6,
3973 	.size = {
3974 		.width = 152,
3975 		.height = 91,
3976 	},
3977 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3978 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3979 };
3980 
3981 static const struct panel_desc urt_umsh_8596md_parallel = {
3982 	.timings = &urt_umsh_8596md_timing,
3983 	.num_timings = 1,
3984 	.bpc = 6,
3985 	.size = {
3986 		.width = 152,
3987 		.height = 91,
3988 	},
3989 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3990 };
3991 
3992 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3993 	.clock = 33333,
3994 	.hdisplay = 800,
3995 	.hsync_start = 800 + 210,
3996 	.hsync_end = 800 + 210 + 20,
3997 	.htotal = 800 + 210 + 20 + 46,
3998 	.vdisplay =  480,
3999 	.vsync_start = 480 + 22,
4000 	.vsync_end = 480 + 22 + 10,
4001 	.vtotal = 480 + 22 + 10 + 23,
4002 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4003 };
4004 
4005 static const struct panel_desc vl050_8048nt_c01 = {
4006 	.modes = &vl050_8048nt_c01_mode,
4007 	.num_modes = 1,
4008 	.bpc = 8,
4009 	.size = {
4010 		.width = 120,
4011 		.height = 76,
4012 	},
4013 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4014 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4015 };
4016 
4017 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4018 	.clock = 6410,
4019 	.hdisplay = 320,
4020 	.hsync_start = 320 + 20,
4021 	.hsync_end = 320 + 20 + 30,
4022 	.htotal = 320 + 20 + 30 + 38,
4023 	.vdisplay = 240,
4024 	.vsync_start = 240 + 4,
4025 	.vsync_end = 240 + 4 + 3,
4026 	.vtotal = 240 + 4 + 3 + 15,
4027 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4028 };
4029 
4030 static const struct panel_desc winstar_wf35ltiacd = {
4031 	.modes = &winstar_wf35ltiacd_mode,
4032 	.num_modes = 1,
4033 	.bpc = 8,
4034 	.size = {
4035 		.width = 70,
4036 		.height = 53,
4037 	},
4038 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4039 };
4040 
4041 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4042 	.clock = 51200,
4043 	.hdisplay = 1024,
4044 	.hsync_start = 1024 + 100,
4045 	.hsync_end = 1024 + 100 + 100,
4046 	.htotal = 1024 + 100 + 100 + 120,
4047 	.vdisplay = 600,
4048 	.vsync_start = 600 + 10,
4049 	.vsync_end = 600 + 10 + 10,
4050 	.vtotal = 600 + 10 + 10 + 15,
4051 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4052 };
4053 
4054 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4055 	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4056 	.num_modes = 1,
4057 	.bpc = 6,
4058 	.size = {
4059 		.width = 154,
4060 		.height = 90,
4061 	},
4062 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
4063 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4064 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
4065 };
4066 
4067 static const struct drm_display_mode arm_rtsm_mode[] = {
4068 	{
4069 		.clock = 65000,
4070 		.hdisplay = 1024,
4071 		.hsync_start = 1024 + 24,
4072 		.hsync_end = 1024 + 24 + 136,
4073 		.htotal = 1024 + 24 + 136 + 160,
4074 		.vdisplay = 768,
4075 		.vsync_start = 768 + 3,
4076 		.vsync_end = 768 + 3 + 6,
4077 		.vtotal = 768 + 3 + 6 + 29,
4078 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4079 	},
4080 };
4081 
4082 static const struct panel_desc arm_rtsm = {
4083 	.modes = arm_rtsm_mode,
4084 	.num_modes = 1,
4085 	.bpc = 8,
4086 	.size = {
4087 		.width = 400,
4088 		.height = 300,
4089 	},
4090 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4091 };
4092 
4093 static const struct of_device_id platform_of_match[] = {
4094 	{
4095 		.compatible = "ampire,am-1280800n3tzqw-t00h",
4096 		.data = &ampire_am_1280800n3tzqw_t00h,
4097 	}, {
4098 		.compatible = "ampire,am-480272h3tmqw-t01h",
4099 		.data = &ampire_am_480272h3tmqw_t01h,
4100 	}, {
4101 		.compatible = "ampire,am800480r3tmqwa1h",
4102 		.data = &ampire_am800480r3tmqwa1h,
4103 	}, {
4104 		.compatible = "arm,rtsm-display",
4105 		.data = &arm_rtsm,
4106 	}, {
4107 		.compatible = "armadeus,st0700-adapt",
4108 		.data = &armadeus_st0700_adapt,
4109 	}, {
4110 		.compatible = "auo,b101aw03",
4111 		.data = &auo_b101aw03,
4112 	}, {
4113 		.compatible = "auo,b101ean01",
4114 		.data = &auo_b101ean01,
4115 	}, {
4116 		.compatible = "auo,b101xtn01",
4117 		.data = &auo_b101xtn01,
4118 	}, {
4119 		.compatible = "auo,b116xa01",
4120 		.data = &auo_b116xak01,
4121 	}, {
4122 		.compatible = "auo,b116xw03",
4123 		.data = &auo_b116xw03,
4124 	}, {
4125 		.compatible = "auo,b133htn01",
4126 		.data = &auo_b133htn01,
4127 	}, {
4128 		.compatible = "auo,b133xtn01",
4129 		.data = &auo_b133xtn01,
4130 	}, {
4131 		.compatible = "auo,g070vvn01",
4132 		.data = &auo_g070vvn01,
4133 	}, {
4134 		.compatible = "auo,g101evn010",
4135 		.data = &auo_g101evn010,
4136 	}, {
4137 		.compatible = "auo,g104sn02",
4138 		.data = &auo_g104sn02,
4139 	}, {
4140 		.compatible = "auo,g121ean01",
4141 		.data = &auo_g121ean01,
4142 	}, {
4143 		.compatible = "auo,g133han01",
4144 		.data = &auo_g133han01,
4145 	}, {
4146 		.compatible = "auo,g156xtn01",
4147 		.data = &auo_g156xtn01,
4148 	}, {
4149 		.compatible = "auo,g185han01",
4150 		.data = &auo_g185han01,
4151 	}, {
4152 		.compatible = "auo,g190ean01",
4153 		.data = &auo_g190ean01,
4154 	}, {
4155 		.compatible = "auo,p320hvn03",
4156 		.data = &auo_p320hvn03,
4157 	}, {
4158 		.compatible = "auo,t215hvn01",
4159 		.data = &auo_t215hvn01,
4160 	}, {
4161 		.compatible = "avic,tm070ddh03",
4162 		.data = &avic_tm070ddh03,
4163 	}, {
4164 		.compatible = "bananapi,s070wv20-ct16",
4165 		.data = &bananapi_s070wv20_ct16,
4166 	}, {
4167 		.compatible = "boe,hv070wsa-100",
4168 		.data = &boe_hv070wsa
4169 	}, {
4170 		.compatible = "boe,nv101wxmn51",
4171 		.data = &boe_nv101wxmn51,
4172 	}, {
4173 		.compatible = "boe,nv110wtm-n61",
4174 		.data = &boe_nv110wtm_n61,
4175 	}, {
4176 		.compatible = "boe,nv133fhm-n61",
4177 		.data = &boe_nv133fhm_n61,
4178 	}, {
4179 		.compatible = "boe,nv133fhm-n62",
4180 		.data = &boe_nv133fhm_n61,
4181 	}, {
4182 		.compatible = "boe,nv140fhmn49",
4183 		.data = &boe_nv140fhmn49,
4184 	}, {
4185 		.compatible = "cdtech,s043wq26h-ct7",
4186 		.data = &cdtech_s043wq26h_ct7,
4187 	}, {
4188 		.compatible = "cdtech,s070pws19hp-fc21",
4189 		.data = &cdtech_s070pws19hp_fc21,
4190 	}, {
4191 		.compatible = "cdtech,s070swv29hg-dc44",
4192 		.data = &cdtech_s070swv29hg_dc44,
4193 	}, {
4194 		.compatible = "cdtech,s070wv95-ct16",
4195 		.data = &cdtech_s070wv95_ct16,
4196 	}, {
4197 		.compatible = "chefree,ch101olhlwh-002",
4198 		.data = &chefree_ch101olhlwh_002,
4199 	}, {
4200 		.compatible = "chunghwa,claa070wp03xg",
4201 		.data = &chunghwa_claa070wp03xg,
4202 	}, {
4203 		.compatible = "chunghwa,claa101wa01a",
4204 		.data = &chunghwa_claa101wa01a
4205 	}, {
4206 		.compatible = "chunghwa,claa101wb01",
4207 		.data = &chunghwa_claa101wb01
4208 	}, {
4209 		.compatible = "dataimage,scf0700c48ggu18",
4210 		.data = &dataimage_scf0700c48ggu18,
4211 	}, {
4212 		.compatible = "dlc,dlc0700yzg-1",
4213 		.data = &dlc_dlc0700yzg_1,
4214 	}, {
4215 		.compatible = "dlc,dlc1010gig",
4216 		.data = &dlc_dlc1010gig,
4217 	}, {
4218 		.compatible = "edt,et035012dm6",
4219 		.data = &edt_et035012dm6,
4220 	}, {
4221 		.compatible = "edt,etm043080dh6gp",
4222 		.data = &edt_etm043080dh6gp,
4223 	}, {
4224 		.compatible = "edt,etm0430g0dh6",
4225 		.data = &edt_etm0430g0dh6,
4226 	}, {
4227 		.compatible = "edt,et057090dhu",
4228 		.data = &edt_et057090dhu,
4229 	}, {
4230 		.compatible = "edt,et070080dh6",
4231 		.data = &edt_etm0700g0dh6,
4232 	}, {
4233 		.compatible = "edt,etm0700g0dh6",
4234 		.data = &edt_etm0700g0dh6,
4235 	}, {
4236 		.compatible = "edt,etm0700g0bdh6",
4237 		.data = &edt_etm0700g0bdh6,
4238 	}, {
4239 		.compatible = "edt,etm0700g0edh6",
4240 		.data = &edt_etm0700g0bdh6,
4241 	}, {
4242 		.compatible = "evervision,vgg804821",
4243 		.data = &evervision_vgg804821,
4244 	}, {
4245 		.compatible = "foxlink,fl500wvr00-a0t",
4246 		.data = &foxlink_fl500wvr00_a0t,
4247 	}, {
4248 		.compatible = "frida,frd350h54004",
4249 		.data = &frida_frd350h54004,
4250 	}, {
4251 		.compatible = "friendlyarm,hd702e",
4252 		.data = &friendlyarm_hd702e,
4253 	}, {
4254 		.compatible = "giantplus,gpg482739qs5",
4255 		.data = &giantplus_gpg482739qs5
4256 	}, {
4257 		.compatible = "giantplus,gpm940b0",
4258 		.data = &giantplus_gpm940b0,
4259 	}, {
4260 		.compatible = "hannstar,hsd070pww1",
4261 		.data = &hannstar_hsd070pww1,
4262 	}, {
4263 		.compatible = "hannstar,hsd100pxn1",
4264 		.data = &hannstar_hsd100pxn1,
4265 	}, {
4266 		.compatible = "hit,tx23d38vm0caa",
4267 		.data = &hitachi_tx23d38vm0caa
4268 	}, {
4269 		.compatible = "innolux,at043tn24",
4270 		.data = &innolux_at043tn24,
4271 	}, {
4272 		.compatible = "innolux,at070tn92",
4273 		.data = &innolux_at070tn92,
4274 	}, {
4275 		.compatible = "innolux,g070y2-l01",
4276 		.data = &innolux_g070y2_l01,
4277 	}, {
4278 		.compatible = "innolux,g101ice-l01",
4279 		.data = &innolux_g101ice_l01
4280 	}, {
4281 		.compatible = "innolux,g121i1-l01",
4282 		.data = &innolux_g121i1_l01
4283 	}, {
4284 		.compatible = "innolux,g121x1-l03",
4285 		.data = &innolux_g121x1_l03,
4286 	}, {
4287 		.compatible = "innolux,n116bge",
4288 		.data = &innolux_n116bge,
4289 	}, {
4290 		.compatible = "innolux,n125hce-gn1",
4291 		.data = &innolux_n125hce_gn1,
4292 	}, {
4293 		.compatible = "innolux,n156bge-l21",
4294 		.data = &innolux_n156bge_l21,
4295 	}, {
4296 		.compatible = "innolux,p120zdg-bf1",
4297 		.data = &innolux_p120zdg_bf1,
4298 	}, {
4299 		.compatible = "innolux,zj070na-01p",
4300 		.data = &innolux_zj070na_01p,
4301 	}, {
4302 		.compatible = "ivo,m133nwf4-r0",
4303 		.data = &ivo_m133nwf4_r0,
4304 	}, {
4305 		.compatible = "kingdisplay,kd116n21-30nv-a010",
4306 		.data = &kingdisplay_kd116n21_30nv_a010,
4307 	}, {
4308 		.compatible = "koe,tx14d24vm1bpa",
4309 		.data = &koe_tx14d24vm1bpa,
4310 	}, {
4311 		.compatible = "koe,tx26d202vm0bwa",
4312 		.data = &koe_tx26d202vm0bwa,
4313 	}, {
4314 		.compatible = "koe,tx31d200vm0baa",
4315 		.data = &koe_tx31d200vm0baa,
4316 	}, {
4317 		.compatible = "kyo,tcg121xglp",
4318 		.data = &kyo_tcg121xglp,
4319 	}, {
4320 		.compatible = "lemaker,bl035-rgb-002",
4321 		.data = &lemaker_bl035_rgb_002,
4322 	}, {
4323 		.compatible = "lg,lb070wv8",
4324 		.data = &lg_lb070wv8,
4325 	}, {
4326 		.compatible = "lg,lp079qx1-sp0v",
4327 		.data = &lg_lp079qx1_sp0v,
4328 	}, {
4329 		.compatible = "lg,lp097qx1-spa1",
4330 		.data = &lg_lp097qx1_spa1,
4331 	}, {
4332 		.compatible = "lg,lp120up1",
4333 		.data = &lg_lp120up1,
4334 	}, {
4335 		.compatible = "lg,lp129qe",
4336 		.data = &lg_lp129qe,
4337 	}, {
4338 		.compatible = "logicpd,type28",
4339 		.data = &logicpd_type_28,
4340 	}, {
4341 		.compatible = "logictechno,lt161010-2nhc",
4342 		.data = &logictechno_lt161010_2nh,
4343 	}, {
4344 		.compatible = "logictechno,lt161010-2nhr",
4345 		.data = &logictechno_lt161010_2nh,
4346 	}, {
4347 		.compatible = "logictechno,lt170410-2whc",
4348 		.data = &logictechno_lt170410_2whc,
4349 	}, {
4350 		.compatible = "mitsubishi,aa070mc01-ca1",
4351 		.data = &mitsubishi_aa070mc01,
4352 	}, {
4353 		.compatible = "nec,nl12880bc20-05",
4354 		.data = &nec_nl12880bc20_05,
4355 	}, {
4356 		.compatible = "nec,nl4827hc19-05b",
4357 		.data = &nec_nl4827hc19_05b,
4358 	}, {
4359 		.compatible = "netron-dy,e231732",
4360 		.data = &netron_dy_e231732,
4361 	}, {
4362 		.compatible = "neweast,wjfh116008a",
4363 		.data = &neweast_wjfh116008a,
4364 	}, {
4365 		.compatible = "newhaven,nhd-4.3-480272ef-atxl",
4366 		.data = &newhaven_nhd_43_480272ef_atxl,
4367 	}, {
4368 		.compatible = "nlt,nl192108ac18-02d",
4369 		.data = &nlt_nl192108ac18_02d,
4370 	}, {
4371 		.compatible = "nvd,9128",
4372 		.data = &nvd_9128,
4373 	}, {
4374 		.compatible = "okaya,rs800480t-7x0gp",
4375 		.data = &okaya_rs800480t_7x0gp,
4376 	}, {
4377 		.compatible = "olimex,lcd-olinuxino-43-ts",
4378 		.data = &olimex_lcd_olinuxino_43ts,
4379 	}, {
4380 		.compatible = "ontat,yx700wv03",
4381 		.data = &ontat_yx700wv03,
4382 	}, {
4383 		.compatible = "ortustech,com37h3m05dtc",
4384 		.data = &ortustech_com37h3m,
4385 	}, {
4386 		.compatible = "ortustech,com37h3m99dtc",
4387 		.data = &ortustech_com37h3m,
4388 	}, {
4389 		.compatible = "ortustech,com43h4m85ulc",
4390 		.data = &ortustech_com43h4m85ulc,
4391 	}, {
4392 		.compatible = "osddisplays,osd070t1718-19ts",
4393 		.data = &osddisplays_osd070t1718_19ts,
4394 	}, {
4395 		.compatible = "pda,91-00156-a0",
4396 		.data = &pda_91_00156_a0,
4397 	}, {
4398 		.compatible = "powertip,ph800480t013-idf02",
4399 		.data = &powertip_ph800480t013_idf02,
4400 	}, {
4401 		.compatible = "qiaodian,qd43003c0-40",
4402 		.data = &qd43003c0_40,
4403 	}, {
4404 		.compatible = "rocktech,rk070er9427",
4405 		.data = &rocktech_rk070er9427,
4406 	}, {
4407 		.compatible = "rocktech,rk101ii01d-ct",
4408 		.data = &rocktech_rk101ii01d_ct,
4409 	}, {
4410 		.compatible = "samsung,lsn122dl01-c01",
4411 		.data = &samsung_lsn122dl01_c01,
4412 	}, {
4413 		.compatible = "samsung,ltn101nt05",
4414 		.data = &samsung_ltn101nt05,
4415 	}, {
4416 		.compatible = "samsung,ltn140at29-301",
4417 		.data = &samsung_ltn140at29_301,
4418 	}, {
4419 		.compatible = "satoz,sat050at40h12r2",
4420 		.data = &satoz_sat050at40h12r2,
4421 	}, {
4422 		.compatible = "sharp,ld-d5116z01b",
4423 		.data = &sharp_ld_d5116z01b,
4424 	}, {
4425 		.compatible = "sharp,lq035q7db03",
4426 		.data = &sharp_lq035q7db03,
4427 	}, {
4428 		.compatible = "sharp,lq070y3dg3b",
4429 		.data = &sharp_lq070y3dg3b,
4430 	}, {
4431 		.compatible = "sharp,lq101k1ly04",
4432 		.data = &sharp_lq101k1ly04,
4433 	}, {
4434 		.compatible = "sharp,lq123p1jx31",
4435 		.data = &sharp_lq123p1jx31,
4436 	}, {
4437 		.compatible = "sharp,ls020b1dd01d",
4438 		.data = &sharp_ls020b1dd01d,
4439 	}, {
4440 		.compatible = "shelly,sca07010-bfn-lnn",
4441 		.data = &shelly_sca07010_bfn_lnn,
4442 	}, {
4443 		.compatible = "starry,kr070pe2t",
4444 		.data = &starry_kr070pe2t,
4445 	}, {
4446 		.compatible = "starry,kr122ea0sra",
4447 		.data = &starry_kr122ea0sra,
4448 	}, {
4449 		.compatible = "tfc,s9700rtwv43tr-01b",
4450 		.data = &tfc_s9700rtwv43tr_01b,
4451 	}, {
4452 		.compatible = "tianma,tm070jdhg30",
4453 		.data = &tianma_tm070jdhg30,
4454 	}, {
4455 		.compatible = "tianma,tm070jvhg33",
4456 		.data = &tianma_tm070jvhg33,
4457 	}, {
4458 		.compatible = "tianma,tm070rvhg71",
4459 		.data = &tianma_tm070rvhg71,
4460 	}, {
4461 		.compatible = "ti,nspire-cx-lcd-panel",
4462 		.data = &ti_nspire_cx_lcd_panel,
4463 	}, {
4464 		.compatible = "ti,nspire-classic-lcd-panel",
4465 		.data = &ti_nspire_classic_lcd_panel,
4466 	}, {
4467 		.compatible = "toshiba,lt089ac29000",
4468 		.data = &toshiba_lt089ac29000,
4469 	}, {
4470 		.compatible = "tpk,f07a-0102",
4471 		.data = &tpk_f07a_0102,
4472 	}, {
4473 		.compatible = "tpk,f10a-0102",
4474 		.data = &tpk_f10a_0102,
4475 	}, {
4476 		.compatible = "urt,umsh-8596md-t",
4477 		.data = &urt_umsh_8596md_parallel,
4478 	}, {
4479 		.compatible = "urt,umsh-8596md-1t",
4480 		.data = &urt_umsh_8596md_parallel,
4481 	}, {
4482 		.compatible = "urt,umsh-8596md-7t",
4483 		.data = &urt_umsh_8596md_parallel,
4484 	}, {
4485 		.compatible = "urt,umsh-8596md-11t",
4486 		.data = &urt_umsh_8596md_lvds,
4487 	}, {
4488 		.compatible = "urt,umsh-8596md-19t",
4489 		.data = &urt_umsh_8596md_lvds,
4490 	}, {
4491 		.compatible = "urt,umsh-8596md-20t",
4492 		.data = &urt_umsh_8596md_parallel,
4493 	}, {
4494 		.compatible = "vxt,vl050-8048nt-c01",
4495 		.data = &vl050_8048nt_c01,
4496 	}, {
4497 		.compatible = "winstar,wf35ltiacd",
4498 		.data = &winstar_wf35ltiacd,
4499 	}, {
4500 		.compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4501 		.data = &yes_optoelectronics_ytc700tlag_05_201c,
4502 	}, {
4503 		/* Must be the last entry */
4504 		.compatible = "panel-dpi",
4505 		.data = &panel_dpi,
4506 	}, {
4507 		/* sentinel */
4508 	}
4509 };
4510 MODULE_DEVICE_TABLE(of, platform_of_match);
4511 
4512 static int panel_simple_platform_probe(struct platform_device *pdev)
4513 {
4514 	const struct of_device_id *id;
4515 
4516 	id = of_match_node(platform_of_match, pdev->dev.of_node);
4517 	if (!id)
4518 		return -ENODEV;
4519 
4520 	return panel_simple_probe(&pdev->dev, id->data);
4521 }
4522 
4523 static int panel_simple_platform_remove(struct platform_device *pdev)
4524 {
4525 	return panel_simple_remove(&pdev->dev);
4526 }
4527 
4528 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4529 {
4530 	panel_simple_shutdown(&pdev->dev);
4531 }
4532 
4533 static struct platform_driver panel_simple_platform_driver = {
4534 	.driver = {
4535 		.name = "panel-simple",
4536 		.of_match_table = platform_of_match,
4537 	},
4538 	.probe = panel_simple_platform_probe,
4539 	.remove = panel_simple_platform_remove,
4540 	.shutdown = panel_simple_platform_shutdown,
4541 };
4542 
4543 struct panel_desc_dsi {
4544 	struct panel_desc desc;
4545 
4546 	unsigned long flags;
4547 	enum mipi_dsi_pixel_format format;
4548 	unsigned int lanes;
4549 };
4550 
4551 static const struct drm_display_mode auo_b080uan01_mode = {
4552 	.clock = 154500,
4553 	.hdisplay = 1200,
4554 	.hsync_start = 1200 + 62,
4555 	.hsync_end = 1200 + 62 + 4,
4556 	.htotal = 1200 + 62 + 4 + 62,
4557 	.vdisplay = 1920,
4558 	.vsync_start = 1920 + 9,
4559 	.vsync_end = 1920 + 9 + 2,
4560 	.vtotal = 1920 + 9 + 2 + 8,
4561 };
4562 
4563 static const struct panel_desc_dsi auo_b080uan01 = {
4564 	.desc = {
4565 		.modes = &auo_b080uan01_mode,
4566 		.num_modes = 1,
4567 		.bpc = 8,
4568 		.size = {
4569 			.width = 108,
4570 			.height = 272,
4571 		},
4572 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4573 	},
4574 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4575 	.format = MIPI_DSI_FMT_RGB888,
4576 	.lanes = 4,
4577 };
4578 
4579 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4580 	.clock = 160000,
4581 	.hdisplay = 1200,
4582 	.hsync_start = 1200 + 120,
4583 	.hsync_end = 1200 + 120 + 20,
4584 	.htotal = 1200 + 120 + 20 + 21,
4585 	.vdisplay = 1920,
4586 	.vsync_start = 1920 + 21,
4587 	.vsync_end = 1920 + 21 + 3,
4588 	.vtotal = 1920 + 21 + 3 + 18,
4589 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4590 };
4591 
4592 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4593 	.desc = {
4594 		.modes = &boe_tv080wum_nl0_mode,
4595 		.num_modes = 1,
4596 		.size = {
4597 			.width = 107,
4598 			.height = 172,
4599 		},
4600 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4601 	},
4602 	.flags = MIPI_DSI_MODE_VIDEO |
4603 		 MIPI_DSI_MODE_VIDEO_BURST |
4604 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4605 	.format = MIPI_DSI_FMT_RGB888,
4606 	.lanes = 4,
4607 };
4608 
4609 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4610 	.clock = 71000,
4611 	.hdisplay = 800,
4612 	.hsync_start = 800 + 32,
4613 	.hsync_end = 800 + 32 + 1,
4614 	.htotal = 800 + 32 + 1 + 57,
4615 	.vdisplay = 1280,
4616 	.vsync_start = 1280 + 28,
4617 	.vsync_end = 1280 + 28 + 1,
4618 	.vtotal = 1280 + 28 + 1 + 14,
4619 };
4620 
4621 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4622 	.desc = {
4623 		.modes = &lg_ld070wx3_sl01_mode,
4624 		.num_modes = 1,
4625 		.bpc = 8,
4626 		.size = {
4627 			.width = 94,
4628 			.height = 151,
4629 		},
4630 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4631 	},
4632 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4633 	.format = MIPI_DSI_FMT_RGB888,
4634 	.lanes = 4,
4635 };
4636 
4637 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4638 	.clock = 67000,
4639 	.hdisplay = 720,
4640 	.hsync_start = 720 + 12,
4641 	.hsync_end = 720 + 12 + 4,
4642 	.htotal = 720 + 12 + 4 + 112,
4643 	.vdisplay = 1280,
4644 	.vsync_start = 1280 + 8,
4645 	.vsync_end = 1280 + 8 + 4,
4646 	.vtotal = 1280 + 8 + 4 + 12,
4647 };
4648 
4649 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4650 	.desc = {
4651 		.modes = &lg_lh500wx1_sd03_mode,
4652 		.num_modes = 1,
4653 		.bpc = 8,
4654 		.size = {
4655 			.width = 62,
4656 			.height = 110,
4657 		},
4658 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4659 	},
4660 	.flags = MIPI_DSI_MODE_VIDEO,
4661 	.format = MIPI_DSI_FMT_RGB888,
4662 	.lanes = 4,
4663 };
4664 
4665 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4666 	.clock = 157200,
4667 	.hdisplay = 1920,
4668 	.hsync_start = 1920 + 154,
4669 	.hsync_end = 1920 + 154 + 16,
4670 	.htotal = 1920 + 154 + 16 + 32,
4671 	.vdisplay = 1200,
4672 	.vsync_start = 1200 + 17,
4673 	.vsync_end = 1200 + 17 + 2,
4674 	.vtotal = 1200 + 17 + 2 + 16,
4675 };
4676 
4677 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4678 	.desc = {
4679 		.modes = &panasonic_vvx10f004b00_mode,
4680 		.num_modes = 1,
4681 		.bpc = 8,
4682 		.size = {
4683 			.width = 217,
4684 			.height = 136,
4685 		},
4686 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4687 	},
4688 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4689 		 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4690 	.format = MIPI_DSI_FMT_RGB888,
4691 	.lanes = 4,
4692 };
4693 
4694 static const struct drm_display_mode lg_acx467akm_7_mode = {
4695 	.clock = 150000,
4696 	.hdisplay = 1080,
4697 	.hsync_start = 1080 + 2,
4698 	.hsync_end = 1080 + 2 + 2,
4699 	.htotal = 1080 + 2 + 2 + 2,
4700 	.vdisplay = 1920,
4701 	.vsync_start = 1920 + 2,
4702 	.vsync_end = 1920 + 2 + 2,
4703 	.vtotal = 1920 + 2 + 2 + 2,
4704 };
4705 
4706 static const struct panel_desc_dsi lg_acx467akm_7 = {
4707 	.desc = {
4708 		.modes = &lg_acx467akm_7_mode,
4709 		.num_modes = 1,
4710 		.bpc = 8,
4711 		.size = {
4712 			.width = 62,
4713 			.height = 110,
4714 		},
4715 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4716 	},
4717 	.flags = 0,
4718 	.format = MIPI_DSI_FMT_RGB888,
4719 	.lanes = 4,
4720 };
4721 
4722 static const struct drm_display_mode osd101t2045_53ts_mode = {
4723 	.clock = 154500,
4724 	.hdisplay = 1920,
4725 	.hsync_start = 1920 + 112,
4726 	.hsync_end = 1920 + 112 + 16,
4727 	.htotal = 1920 + 112 + 16 + 32,
4728 	.vdisplay = 1200,
4729 	.vsync_start = 1200 + 16,
4730 	.vsync_end = 1200 + 16 + 2,
4731 	.vtotal = 1200 + 16 + 2 + 16,
4732 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4733 };
4734 
4735 static const struct panel_desc_dsi osd101t2045_53ts = {
4736 	.desc = {
4737 		.modes = &osd101t2045_53ts_mode,
4738 		.num_modes = 1,
4739 		.bpc = 8,
4740 		.size = {
4741 			.width = 217,
4742 			.height = 136,
4743 		},
4744 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4745 	},
4746 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4747 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4748 		 MIPI_DSI_MODE_EOT_PACKET,
4749 	.format = MIPI_DSI_FMT_RGB888,
4750 	.lanes = 4,
4751 };
4752 
4753 static const struct of_device_id dsi_of_match[] = {
4754 	{
4755 		.compatible = "auo,b080uan01",
4756 		.data = &auo_b080uan01
4757 	}, {
4758 		.compatible = "boe,tv080wum-nl0",
4759 		.data = &boe_tv080wum_nl0
4760 	}, {
4761 		.compatible = "lg,ld070wx3-sl01",
4762 		.data = &lg_ld070wx3_sl01
4763 	}, {
4764 		.compatible = "lg,lh500wx1-sd03",
4765 		.data = &lg_lh500wx1_sd03
4766 	}, {
4767 		.compatible = "panasonic,vvx10f004b00",
4768 		.data = &panasonic_vvx10f004b00
4769 	}, {
4770 		.compatible = "lg,acx467akm-7",
4771 		.data = &lg_acx467akm_7
4772 	}, {
4773 		.compatible = "osddisplays,osd101t2045-53ts",
4774 		.data = &osd101t2045_53ts
4775 	}, {
4776 		/* sentinel */
4777 	}
4778 };
4779 MODULE_DEVICE_TABLE(of, dsi_of_match);
4780 
4781 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4782 {
4783 	const struct panel_desc_dsi *desc;
4784 	const struct of_device_id *id;
4785 	int err;
4786 
4787 	id = of_match_node(dsi_of_match, dsi->dev.of_node);
4788 	if (!id)
4789 		return -ENODEV;
4790 
4791 	desc = id->data;
4792 
4793 	err = panel_simple_probe(&dsi->dev, &desc->desc);
4794 	if (err < 0)
4795 		return err;
4796 
4797 	dsi->mode_flags = desc->flags;
4798 	dsi->format = desc->format;
4799 	dsi->lanes = desc->lanes;
4800 
4801 	err = mipi_dsi_attach(dsi);
4802 	if (err) {
4803 		struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4804 
4805 		drm_panel_remove(&panel->base);
4806 	}
4807 
4808 	return err;
4809 }
4810 
4811 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4812 {
4813 	int err;
4814 
4815 	err = mipi_dsi_detach(dsi);
4816 	if (err < 0)
4817 		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4818 
4819 	return panel_simple_remove(&dsi->dev);
4820 }
4821 
4822 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4823 {
4824 	panel_simple_shutdown(&dsi->dev);
4825 }
4826 
4827 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4828 	.driver = {
4829 		.name = "panel-simple-dsi",
4830 		.of_match_table = dsi_of_match,
4831 	},
4832 	.probe = panel_simple_dsi_probe,
4833 	.remove = panel_simple_dsi_remove,
4834 	.shutdown = panel_simple_dsi_shutdown,
4835 };
4836 
4837 static int __init panel_simple_init(void)
4838 {
4839 	int err;
4840 
4841 	err = platform_driver_register(&panel_simple_platform_driver);
4842 	if (err < 0)
4843 		return err;
4844 
4845 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4846 		err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4847 		if (err < 0) {
4848 			platform_driver_unregister(&panel_simple_platform_driver);
4849 			return err;
4850 		}
4851 	}
4852 
4853 	return 0;
4854 }
4855 module_init(panel_simple_init);
4856 
4857 static void __exit panel_simple_exit(void)
4858 {
4859 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4860 		mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4861 
4862 	platform_driver_unregister(&panel_simple_platform_driver);
4863 }
4864 module_exit(panel_simple_exit);
4865 
4866 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4867 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4868 MODULE_LICENSE("GPL and additional rights");
4869