1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t unprepared_time; 145 146 const struct panel_desc *desc; 147 148 struct regulator *supply; 149 struct i2c_adapter *ddc; 150 151 struct gpio_desc *enable_gpio; 152 153 struct edid *edid; 154 155 struct drm_display_mode override_mode; 156 157 enum drm_panel_orientation orientation; 158 }; 159 160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 161 { 162 return container_of(panel, struct panel_simple, base); 163 } 164 165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 166 struct drm_connector *connector) 167 { 168 struct drm_display_mode *mode; 169 unsigned int i, num = 0; 170 171 for (i = 0; i < panel->desc->num_timings; i++) { 172 const struct display_timing *dt = &panel->desc->timings[i]; 173 struct videomode vm; 174 175 videomode_from_timing(dt, &vm); 176 mode = drm_mode_create(connector->dev); 177 if (!mode) { 178 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 179 dt->hactive.typ, dt->vactive.typ); 180 continue; 181 } 182 183 drm_display_mode_from_videomode(&vm, mode); 184 185 mode->type |= DRM_MODE_TYPE_DRIVER; 186 187 if (panel->desc->num_timings == 1) 188 mode->type |= DRM_MODE_TYPE_PREFERRED; 189 190 drm_mode_probed_add(connector, mode); 191 num++; 192 } 193 194 return num; 195 } 196 197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 198 struct drm_connector *connector) 199 { 200 struct drm_display_mode *mode; 201 unsigned int i, num = 0; 202 203 for (i = 0; i < panel->desc->num_modes; i++) { 204 const struct drm_display_mode *m = &panel->desc->modes[i]; 205 206 mode = drm_mode_duplicate(connector->dev, m); 207 if (!mode) { 208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 209 m->hdisplay, m->vdisplay, 210 drm_mode_vrefresh(m)); 211 continue; 212 } 213 214 mode->type |= DRM_MODE_TYPE_DRIVER; 215 216 if (panel->desc->num_modes == 1) 217 mode->type |= DRM_MODE_TYPE_PREFERRED; 218 219 drm_mode_set_name(mode); 220 221 drm_mode_probed_add(connector, mode); 222 num++; 223 } 224 225 return num; 226 } 227 228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 229 struct drm_connector *connector) 230 { 231 struct drm_display_mode *mode; 232 bool has_override = panel->override_mode.type; 233 unsigned int num = 0; 234 235 if (!panel->desc) 236 return 0; 237 238 if (has_override) { 239 mode = drm_mode_duplicate(connector->dev, 240 &panel->override_mode); 241 if (mode) { 242 drm_mode_probed_add(connector, mode); 243 num = 1; 244 } else { 245 dev_err(panel->base.dev, "failed to add override mode\n"); 246 } 247 } 248 249 /* Only add timings if override was not there or failed to validate */ 250 if (num == 0 && panel->desc->num_timings) 251 num = panel_simple_get_timings_modes(panel, connector); 252 253 /* 254 * Only add fixed modes if timings/override added no mode. 255 * 256 * We should only ever have either the display timings specified 257 * or a fixed mode. Anything else is rather bogus. 258 */ 259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 260 if (num == 0) 261 num = panel_simple_get_display_modes(panel, connector); 262 263 connector->display_info.bpc = panel->desc->bpc; 264 connector->display_info.width_mm = panel->desc->size.width; 265 connector->display_info.height_mm = panel->desc->size.height; 266 if (panel->desc->bus_format) 267 drm_display_info_set_bus_formats(&connector->display_info, 268 &panel->desc->bus_format, 1); 269 connector->display_info.bus_flags = panel->desc->bus_flags; 270 271 return num; 272 } 273 274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 275 { 276 ktime_t now_ktime, min_ktime; 277 278 if (!min_ms) 279 return; 280 281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 282 now_ktime = ktime_get_boottime(); 283 284 if (ktime_before(now_ktime, min_ktime)) 285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 286 } 287 288 static int panel_simple_disable(struct drm_panel *panel) 289 { 290 struct panel_simple *p = to_panel_simple(panel); 291 292 if (!p->enabled) 293 return 0; 294 295 if (p->desc->delay.disable) 296 msleep(p->desc->delay.disable); 297 298 p->enabled = false; 299 300 return 0; 301 } 302 303 static int panel_simple_suspend(struct device *dev) 304 { 305 struct panel_simple *p = dev_get_drvdata(dev); 306 307 gpiod_set_value_cansleep(p->enable_gpio, 0); 308 regulator_disable(p->supply); 309 p->unprepared_time = ktime_get_boottime(); 310 311 kfree(p->edid); 312 p->edid = NULL; 313 314 return 0; 315 } 316 317 static int panel_simple_unprepare(struct drm_panel *panel) 318 { 319 struct panel_simple *p = to_panel_simple(panel); 320 int ret; 321 322 /* Unpreparing when already unprepared is a no-op */ 323 if (!p->prepared) 324 return 0; 325 326 pm_runtime_mark_last_busy(panel->dev); 327 ret = pm_runtime_put_autosuspend(panel->dev); 328 if (ret < 0) 329 return ret; 330 p->prepared = false; 331 332 return 0; 333 } 334 335 static int panel_simple_resume(struct device *dev) 336 { 337 struct panel_simple *p = dev_get_drvdata(dev); 338 int err; 339 340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 341 342 err = regulator_enable(p->supply); 343 if (err < 0) { 344 dev_err(dev, "failed to enable supply: %d\n", err); 345 return err; 346 } 347 348 gpiod_set_value_cansleep(p->enable_gpio, 1); 349 350 if (p->desc->delay.prepare) 351 msleep(p->desc->delay.prepare); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* 415 * TODO: Remove once all drm drivers call 416 * drm_connector_set_orientation_from_panel() 417 */ 418 drm_connector_set_panel_orientation(connector, p->orientation); 419 420 return num; 421 } 422 423 static int panel_simple_get_timings(struct drm_panel *panel, 424 unsigned int num_timings, 425 struct display_timing *timings) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 unsigned int i; 429 430 if (p->desc->num_timings < num_timings) 431 num_timings = p->desc->num_timings; 432 433 if (timings) 434 for (i = 0; i < num_timings; i++) 435 timings[i] = p->desc->timings[i]; 436 437 return p->desc->num_timings; 438 } 439 440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 441 { 442 struct panel_simple *p = to_panel_simple(panel); 443 444 return p->orientation; 445 } 446 447 static const struct drm_panel_funcs panel_simple_funcs = { 448 .disable = panel_simple_disable, 449 .unprepare = panel_simple_unprepare, 450 .prepare = panel_simple_prepare, 451 .enable = panel_simple_enable, 452 .get_modes = panel_simple_get_modes, 453 .get_orientation = panel_simple_get_orientation, 454 .get_timings = panel_simple_get_timings, 455 }; 456 457 static struct panel_desc panel_dpi; 458 459 static int panel_dpi_probe(struct device *dev, 460 struct panel_simple *panel) 461 { 462 struct display_timing *timing; 463 const struct device_node *np; 464 struct panel_desc *desc; 465 unsigned int bus_flags; 466 struct videomode vm; 467 int ret; 468 469 np = dev->of_node; 470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 471 if (!desc) 472 return -ENOMEM; 473 474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 475 if (!timing) 476 return -ENOMEM; 477 478 ret = of_get_display_timing(np, "panel-timing", timing); 479 if (ret < 0) { 480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 481 np); 482 return ret; 483 } 484 485 desc->timings = timing; 486 desc->num_timings = 1; 487 488 of_property_read_u32(np, "width-mm", &desc->size.width); 489 of_property_read_u32(np, "height-mm", &desc->size.height); 490 491 /* Extract bus_flags from display_timing */ 492 bus_flags = 0; 493 vm.flags = timing->flags; 494 drm_bus_flags_from_videomode(&vm, &bus_flags); 495 desc->bus_flags = bus_flags; 496 497 /* We do not know the connector for the DT node, so guess it */ 498 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 499 500 panel->desc = desc; 501 502 return 0; 503 } 504 505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 506 (to_check->field.typ >= bounds->field.min && \ 507 to_check->field.typ <= bounds->field.max) 508 static void panel_simple_parse_panel_timing_node(struct device *dev, 509 struct panel_simple *panel, 510 const struct display_timing *ot) 511 { 512 const struct panel_desc *desc = panel->desc; 513 struct videomode vm; 514 unsigned int i; 515 516 if (WARN_ON(desc->num_modes)) { 517 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 518 return; 519 } 520 if (WARN_ON(!desc->num_timings)) { 521 dev_err(dev, "Reject override mode: no timings specified\n"); 522 return; 523 } 524 525 for (i = 0; i < panel->desc->num_timings; i++) { 526 const struct display_timing *dt = &panel->desc->timings[i]; 527 528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 536 continue; 537 538 if (ot->flags != dt->flags) 539 continue; 540 541 videomode_from_timing(ot, &vm); 542 drm_display_mode_from_videomode(&vm, &panel->override_mode); 543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 544 DRM_MODE_TYPE_PREFERRED; 545 break; 546 } 547 548 if (WARN_ON(!panel->override_mode.type)) 549 dev_err(dev, "Reject override mode: No display_timing found\n"); 550 } 551 552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 553 { 554 struct panel_simple *panel; 555 struct display_timing dt; 556 struct device_node *ddc; 557 int connector_type; 558 u32 bus_flags; 559 int err; 560 561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 562 if (!panel) 563 return -ENOMEM; 564 565 panel->enabled = false; 566 panel->desc = desc; 567 568 panel->supply = devm_regulator_get(dev, "power"); 569 if (IS_ERR(panel->supply)) 570 return PTR_ERR(panel->supply); 571 572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 573 GPIOD_OUT_LOW); 574 if (IS_ERR(panel->enable_gpio)) 575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 576 "failed to request GPIO\n"); 577 578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 579 if (err) { 580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 581 return err; 582 } 583 584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 585 if (ddc) { 586 panel->ddc = of_find_i2c_adapter_by_node(ddc); 587 of_node_put(ddc); 588 589 if (!panel->ddc) 590 return -EPROBE_DEFER; 591 } 592 593 if (desc == &panel_dpi) { 594 /* Handle the generic panel-dpi binding */ 595 err = panel_dpi_probe(dev, panel); 596 if (err) 597 goto free_ddc; 598 desc = panel->desc; 599 } else { 600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 601 panel_simple_parse_panel_timing_node(dev, panel, &dt); 602 } 603 604 connector_type = desc->connector_type; 605 /* Catch common mistakes for panels. */ 606 switch (connector_type) { 607 case 0: 608 dev_warn(dev, "Specify missing connector_type\n"); 609 connector_type = DRM_MODE_CONNECTOR_DPI; 610 break; 611 case DRM_MODE_CONNECTOR_LVDS: 612 WARN_ON(desc->bus_flags & 613 ~(DRM_BUS_FLAG_DE_LOW | 614 DRM_BUS_FLAG_DE_HIGH | 615 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 616 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 621 desc->bpc != 6); 622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 624 desc->bpc != 8); 625 break; 626 case DRM_MODE_CONNECTOR_eDP: 627 dev_warn(dev, "eDP panels moved to panel-edp\n"); 628 err = -EINVAL; 629 goto free_ddc; 630 case DRM_MODE_CONNECTOR_DSI: 631 if (desc->bpc != 6 && desc->bpc != 8) 632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 633 break; 634 case DRM_MODE_CONNECTOR_DPI: 635 bus_flags = DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 639 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 640 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 643 if (desc->bus_flags & ~bus_flags) 644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 645 if (!(desc->bus_flags & bus_flags)) 646 dev_warn(dev, "Specify missing bus_flags\n"); 647 if (desc->bus_format == 0) 648 dev_warn(dev, "Specify missing bus_format\n"); 649 if (desc->bpc != 6 && desc->bpc != 8) 650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 651 break; 652 default: 653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 654 connector_type = DRM_MODE_CONNECTOR_DPI; 655 break; 656 } 657 658 dev_set_drvdata(dev, panel); 659 660 /* 661 * We use runtime PM for prepare / unprepare since those power the panel 662 * on and off and those can be very slow operations. This is important 663 * to optimize powering the panel on briefly to read the EDID before 664 * fully enabling the panel. 665 */ 666 pm_runtime_enable(dev); 667 pm_runtime_set_autosuspend_delay(dev, 1000); 668 pm_runtime_use_autosuspend(dev); 669 670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 671 672 err = drm_panel_of_backlight(&panel->base); 673 if (err) { 674 dev_err_probe(dev, err, "Could not find backlight\n"); 675 goto disable_pm_runtime; 676 } 677 678 drm_panel_add(&panel->base); 679 680 return 0; 681 682 disable_pm_runtime: 683 pm_runtime_dont_use_autosuspend(dev); 684 pm_runtime_disable(dev); 685 free_ddc: 686 if (panel->ddc) 687 put_device(&panel->ddc->dev); 688 689 return err; 690 } 691 692 static void panel_simple_remove(struct device *dev) 693 { 694 struct panel_simple *panel = dev_get_drvdata(dev); 695 696 drm_panel_remove(&panel->base); 697 drm_panel_disable(&panel->base); 698 drm_panel_unprepare(&panel->base); 699 700 pm_runtime_dont_use_autosuspend(dev); 701 pm_runtime_disable(dev); 702 if (panel->ddc) 703 put_device(&panel->ddc->dev); 704 } 705 706 static void panel_simple_shutdown(struct device *dev) 707 { 708 struct panel_simple *panel = dev_get_drvdata(dev); 709 710 drm_panel_disable(&panel->base); 711 drm_panel_unprepare(&panel->base); 712 } 713 714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 715 .clock = 71100, 716 .hdisplay = 1280, 717 .hsync_start = 1280 + 40, 718 .hsync_end = 1280 + 40 + 80, 719 .htotal = 1280 + 40 + 80 + 40, 720 .vdisplay = 800, 721 .vsync_start = 800 + 3, 722 .vsync_end = 800 + 3 + 10, 723 .vtotal = 800 + 3 + 10 + 10, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 728 .modes = &ire_am_1280800n3tzqw_t00h_mode, 729 .num_modes = 1, 730 .bpc = 8, 731 .size = { 732 .width = 217, 733 .height = 136, 734 }, 735 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 738 }; 739 740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 741 .clock = 9000, 742 .hdisplay = 480, 743 .hsync_start = 480 + 2, 744 .hsync_end = 480 + 2 + 41, 745 .htotal = 480 + 2 + 41 + 2, 746 .vdisplay = 272, 747 .vsync_start = 272 + 2, 748 .vsync_end = 272 + 2 + 10, 749 .vtotal = 272 + 2 + 10 + 2, 750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 751 }; 752 753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 754 .modes = &ire_am_480272h3tmqw_t01h_mode, 755 .num_modes = 1, 756 .bpc = 8, 757 .size = { 758 .width = 99, 759 .height = 58, 760 }, 761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 762 }; 763 764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 765 .clock = 33333, 766 .hdisplay = 800, 767 .hsync_start = 800 + 0, 768 .hsync_end = 800 + 0 + 255, 769 .htotal = 800 + 0 + 255 + 0, 770 .vdisplay = 480, 771 .vsync_start = 480 + 2, 772 .vsync_end = 480 + 2 + 45, 773 .vtotal = 480 + 2 + 45 + 0, 774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 775 }; 776 777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 778 .pixelclock = { 29930000, 33260000, 36590000 }, 779 .hactive = { 800, 800, 800 }, 780 .hfront_porch = { 1, 40, 168 }, 781 .hback_porch = { 88, 88, 88 }, 782 .hsync_len = { 1, 128, 128 }, 783 .vactive = { 480, 480, 480 }, 784 .vfront_porch = { 1, 35, 37 }, 785 .vback_porch = { 8, 8, 8 }, 786 .vsync_len = { 1, 2, 2 }, 787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 789 DISPLAY_FLAGS_SYNC_POSEDGE, 790 }; 791 792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 793 .timings = &ire_am_800480l1tmqw_t00h_timing, 794 .num_timings = 1, 795 .bpc = 8, 796 .size = { 797 .width = 111, 798 .height = 67, 799 }, 800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 804 .connector_type = DRM_MODE_CONNECTOR_DPI, 805 }; 806 807 static const struct panel_desc ampire_am800480r3tmqwa1h = { 808 .modes = &ire_am800480r3tmqwa1h_mode, 809 .num_modes = 1, 810 .bpc = 6, 811 .size = { 812 .width = 152, 813 .height = 91, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 }; 817 818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 819 .pixelclock = { 34500000, 39600000, 50400000 }, 820 .hactive = { 800, 800, 800 }, 821 .hfront_porch = { 12, 112, 312 }, 822 .hback_porch = { 87, 87, 48 }, 823 .hsync_len = { 1, 1, 40 }, 824 .vactive = { 600, 600, 600 }, 825 .vfront_porch = { 1, 21, 61 }, 826 .vback_porch = { 38, 38, 19 }, 827 .vsync_len = { 1, 1, 20 }, 828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 830 DISPLAY_FLAGS_SYNC_POSEDGE, 831 }; 832 833 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 834 .timings = &ire_am800600p5tmqw_tb8h_timing, 835 .num_timings = 1, 836 .bpc = 6, 837 .size = { 838 .width = 162, 839 .height = 122, 840 }, 841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 845 .connector_type = DRM_MODE_CONNECTOR_DPI, 846 }; 847 848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 849 .pixelclock = { 26400000, 33300000, 46800000 }, 850 .hactive = { 800, 800, 800 }, 851 .hfront_porch = { 16, 210, 354 }, 852 .hback_porch = { 45, 36, 6 }, 853 .hsync_len = { 1, 10, 40 }, 854 .vactive = { 480, 480, 480 }, 855 .vfront_porch = { 7, 22, 147 }, 856 .vback_porch = { 22, 13, 3 }, 857 .vsync_len = { 1, 10, 20 }, 858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 860 }; 861 862 static const struct panel_desc armadeus_st0700_adapt = { 863 .timings = &santek_st0700i5y_rbslw_f_timing, 864 .num_timings = 1, 865 .bpc = 6, 866 .size = { 867 .width = 154, 868 .height = 86, 869 }, 870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 872 }; 873 874 static const struct drm_display_mode auo_b101aw03_mode = { 875 .clock = 51450, 876 .hdisplay = 1024, 877 .hsync_start = 1024 + 156, 878 .hsync_end = 1024 + 156 + 8, 879 .htotal = 1024 + 156 + 8 + 156, 880 .vdisplay = 600, 881 .vsync_start = 600 + 16, 882 .vsync_end = 600 + 16 + 6, 883 .vtotal = 600 + 16 + 6 + 16, 884 }; 885 886 static const struct panel_desc auo_b101aw03 = { 887 .modes = &auo_b101aw03_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897 }; 898 899 static const struct drm_display_mode auo_b101xtn01_mode = { 900 .clock = 72000, 901 .hdisplay = 1366, 902 .hsync_start = 1366 + 20, 903 .hsync_end = 1366 + 20 + 70, 904 .htotal = 1366 + 20 + 70, 905 .vdisplay = 768, 906 .vsync_start = 768 + 14, 907 .vsync_end = 768 + 14 + 42, 908 .vtotal = 768 + 14 + 42, 909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 910 }; 911 912 static const struct panel_desc auo_b101xtn01 = { 913 .modes = &auo_b101xtn01_mode, 914 .num_modes = 1, 915 .bpc = 6, 916 .size = { 917 .width = 223, 918 .height = 125, 919 }, 920 }; 921 922 static const struct display_timing auo_g070vvn01_timings = { 923 .pixelclock = { 33300000, 34209000, 45000000 }, 924 .hactive = { 800, 800, 800 }, 925 .hfront_porch = { 20, 40, 200 }, 926 .hback_porch = { 87, 40, 1 }, 927 .hsync_len = { 1, 48, 87 }, 928 .vactive = { 480, 480, 480 }, 929 .vfront_porch = { 5, 13, 200 }, 930 .vback_porch = { 31, 31, 29 }, 931 .vsync_len = { 1, 1, 3 }, 932 }; 933 934 static const struct panel_desc auo_g070vvn01 = { 935 .timings = &auo_g070vvn01_timings, 936 .num_timings = 1, 937 .bpc = 8, 938 .size = { 939 .width = 152, 940 .height = 91, 941 }, 942 .delay = { 943 .prepare = 200, 944 .enable = 50, 945 .disable = 50, 946 .unprepare = 1000, 947 }, 948 }; 949 950 static const struct drm_display_mode auo_g101evn010_mode = { 951 .clock = 68930, 952 .hdisplay = 1280, 953 .hsync_start = 1280 + 82, 954 .hsync_end = 1280 + 82 + 2, 955 .htotal = 1280 + 82 + 2 + 84, 956 .vdisplay = 800, 957 .vsync_start = 800 + 8, 958 .vsync_end = 800 + 8 + 2, 959 .vtotal = 800 + 8 + 2 + 6, 960 }; 961 962 static const struct panel_desc auo_g101evn010 = { 963 .modes = &auo_g101evn010_mode, 964 .num_modes = 1, 965 .bpc = 6, 966 .size = { 967 .width = 216, 968 .height = 135, 969 }, 970 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 972 }; 973 974 static const struct drm_display_mode auo_g104sn02_mode = { 975 .clock = 40000, 976 .hdisplay = 800, 977 .hsync_start = 800 + 40, 978 .hsync_end = 800 + 40 + 216, 979 .htotal = 800 + 40 + 216 + 128, 980 .vdisplay = 600, 981 .vsync_start = 600 + 10, 982 .vsync_end = 600 + 10 + 35, 983 .vtotal = 600 + 10 + 35 + 2, 984 }; 985 986 static const struct panel_desc auo_g104sn02 = { 987 .modes = &auo_g104sn02_mode, 988 .num_modes = 1, 989 .bpc = 8, 990 .size = { 991 .width = 211, 992 .height = 158, 993 }, 994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 995 .connector_type = DRM_MODE_CONNECTOR_LVDS, 996 }; 997 998 static const struct drm_display_mode auo_g121ean01_mode = { 999 .clock = 66700, 1000 .hdisplay = 1280, 1001 .hsync_start = 1280 + 58, 1002 .hsync_end = 1280 + 58 + 8, 1003 .htotal = 1280 + 58 + 8 + 70, 1004 .vdisplay = 800, 1005 .vsync_start = 800 + 6, 1006 .vsync_end = 800 + 6 + 4, 1007 .vtotal = 800 + 6 + 4 + 10, 1008 }; 1009 1010 static const struct panel_desc auo_g121ean01 = { 1011 .modes = &auo_g121ean01_mode, 1012 .num_modes = 1, 1013 .bpc = 8, 1014 .size = { 1015 .width = 261, 1016 .height = 163, 1017 }, 1018 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1019 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1020 }; 1021 1022 static const struct display_timing auo_g133han01_timings = { 1023 .pixelclock = { 134000000, 141200000, 149000000 }, 1024 .hactive = { 1920, 1920, 1920 }, 1025 .hfront_porch = { 39, 58, 77 }, 1026 .hback_porch = { 59, 88, 117 }, 1027 .hsync_len = { 28, 42, 56 }, 1028 .vactive = { 1080, 1080, 1080 }, 1029 .vfront_porch = { 3, 8, 11 }, 1030 .vback_porch = { 5, 14, 19 }, 1031 .vsync_len = { 4, 14, 19 }, 1032 }; 1033 1034 static const struct panel_desc auo_g133han01 = { 1035 .timings = &auo_g133han01_timings, 1036 .num_timings = 1, 1037 .bpc = 8, 1038 .size = { 1039 .width = 293, 1040 .height = 165, 1041 }, 1042 .delay = { 1043 .prepare = 200, 1044 .enable = 50, 1045 .disable = 50, 1046 .unprepare = 1000, 1047 }, 1048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1049 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1050 }; 1051 1052 static const struct drm_display_mode auo_g156xtn01_mode = { 1053 .clock = 76000, 1054 .hdisplay = 1366, 1055 .hsync_start = 1366 + 33, 1056 .hsync_end = 1366 + 33 + 67, 1057 .htotal = 1560, 1058 .vdisplay = 768, 1059 .vsync_start = 768 + 4, 1060 .vsync_end = 768 + 4 + 4, 1061 .vtotal = 806, 1062 }; 1063 1064 static const struct panel_desc auo_g156xtn01 = { 1065 .modes = &auo_g156xtn01_mode, 1066 .num_modes = 1, 1067 .bpc = 8, 1068 .size = { 1069 .width = 344, 1070 .height = 194, 1071 }, 1072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1073 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1074 }; 1075 1076 static const struct display_timing auo_g185han01_timings = { 1077 .pixelclock = { 120000000, 144000000, 175000000 }, 1078 .hactive = { 1920, 1920, 1920 }, 1079 .hfront_porch = { 36, 120, 148 }, 1080 .hback_porch = { 24, 88, 108 }, 1081 .hsync_len = { 20, 48, 64 }, 1082 .vactive = { 1080, 1080, 1080 }, 1083 .vfront_porch = { 6, 10, 40 }, 1084 .vback_porch = { 2, 5, 20 }, 1085 .vsync_len = { 2, 5, 20 }, 1086 }; 1087 1088 static const struct panel_desc auo_g185han01 = { 1089 .timings = &auo_g185han01_timings, 1090 .num_timings = 1, 1091 .bpc = 8, 1092 .size = { 1093 .width = 409, 1094 .height = 230, 1095 }, 1096 .delay = { 1097 .prepare = 50, 1098 .enable = 200, 1099 .disable = 110, 1100 .unprepare = 1000, 1101 }, 1102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1103 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1104 }; 1105 1106 static const struct display_timing auo_g190ean01_timings = { 1107 .pixelclock = { 90000000, 108000000, 135000000 }, 1108 .hactive = { 1280, 1280, 1280 }, 1109 .hfront_porch = { 126, 184, 1266 }, 1110 .hback_porch = { 84, 122, 844 }, 1111 .hsync_len = { 70, 102, 704 }, 1112 .vactive = { 1024, 1024, 1024 }, 1113 .vfront_porch = { 4, 26, 76 }, 1114 .vback_porch = { 2, 8, 25 }, 1115 .vsync_len = { 2, 8, 25 }, 1116 }; 1117 1118 static const struct panel_desc auo_g190ean01 = { 1119 .timings = &auo_g190ean01_timings, 1120 .num_timings = 1, 1121 .bpc = 8, 1122 .size = { 1123 .width = 376, 1124 .height = 301, 1125 }, 1126 .delay = { 1127 .prepare = 50, 1128 .enable = 200, 1129 .disable = 110, 1130 .unprepare = 1000, 1131 }, 1132 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1133 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1134 }; 1135 1136 static const struct display_timing auo_p320hvn03_timings = { 1137 .pixelclock = { 106000000, 148500000, 164000000 }, 1138 .hactive = { 1920, 1920, 1920 }, 1139 .hfront_porch = { 25, 50, 130 }, 1140 .hback_porch = { 25, 50, 130 }, 1141 .hsync_len = { 20, 40, 105 }, 1142 .vactive = { 1080, 1080, 1080 }, 1143 .vfront_porch = { 8, 17, 150 }, 1144 .vback_porch = { 8, 17, 150 }, 1145 .vsync_len = { 4, 11, 100 }, 1146 }; 1147 1148 static const struct panel_desc auo_p320hvn03 = { 1149 .timings = &auo_p320hvn03_timings, 1150 .num_timings = 1, 1151 .bpc = 8, 1152 .size = { 1153 .width = 698, 1154 .height = 393, 1155 }, 1156 .delay = { 1157 .prepare = 1, 1158 .enable = 450, 1159 .unprepare = 500, 1160 }, 1161 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1162 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1163 }; 1164 1165 static const struct drm_display_mode auo_t215hvn01_mode = { 1166 .clock = 148800, 1167 .hdisplay = 1920, 1168 .hsync_start = 1920 + 88, 1169 .hsync_end = 1920 + 88 + 44, 1170 .htotal = 1920 + 88 + 44 + 148, 1171 .vdisplay = 1080, 1172 .vsync_start = 1080 + 4, 1173 .vsync_end = 1080 + 4 + 5, 1174 .vtotal = 1080 + 4 + 5 + 36, 1175 }; 1176 1177 static const struct panel_desc auo_t215hvn01 = { 1178 .modes = &auo_t215hvn01_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 430, 1183 .height = 270, 1184 }, 1185 .delay = { 1186 .disable = 5, 1187 .unprepare = 1000, 1188 } 1189 }; 1190 1191 static const struct drm_display_mode avic_tm070ddh03_mode = { 1192 .clock = 51200, 1193 .hdisplay = 1024, 1194 .hsync_start = 1024 + 160, 1195 .hsync_end = 1024 + 160 + 4, 1196 .htotal = 1024 + 160 + 4 + 156, 1197 .vdisplay = 600, 1198 .vsync_start = 600 + 17, 1199 .vsync_end = 600 + 17 + 1, 1200 .vtotal = 600 + 17 + 1 + 17, 1201 }; 1202 1203 static const struct panel_desc avic_tm070ddh03 = { 1204 .modes = &avic_tm070ddh03_mode, 1205 .num_modes = 1, 1206 .bpc = 8, 1207 .size = { 1208 .width = 154, 1209 .height = 90, 1210 }, 1211 .delay = { 1212 .prepare = 20, 1213 .enable = 200, 1214 .disable = 200, 1215 }, 1216 }; 1217 1218 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1219 .clock = 30000, 1220 .hdisplay = 800, 1221 .hsync_start = 800 + 40, 1222 .hsync_end = 800 + 40 + 48, 1223 .htotal = 800 + 40 + 48 + 40, 1224 .vdisplay = 480, 1225 .vsync_start = 480 + 13, 1226 .vsync_end = 480 + 13 + 3, 1227 .vtotal = 480 + 13 + 3 + 29, 1228 }; 1229 1230 static const struct panel_desc bananapi_s070wv20_ct16 = { 1231 .modes = &bananapi_s070wv20_ct16_mode, 1232 .num_modes = 1, 1233 .bpc = 6, 1234 .size = { 1235 .width = 154, 1236 .height = 86, 1237 }, 1238 }; 1239 1240 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1241 .pixelclock = { 69922000, 71000000, 72293000 }, 1242 .hactive = { 1280, 1280, 1280 }, 1243 .hfront_porch = { 48, 48, 48 }, 1244 .hback_porch = { 80, 80, 80 }, 1245 .hsync_len = { 32, 32, 32 }, 1246 .vactive = { 800, 800, 800 }, 1247 .vfront_porch = { 3, 3, 3 }, 1248 .vback_porch = { 14, 14, 14 }, 1249 .vsync_len = { 6, 6, 6 }, 1250 }; 1251 1252 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1253 .timings = &boe_ev121wxm_n10_1850_timing, 1254 .num_timings = 1, 1255 .bpc = 8, 1256 .size = { 1257 .width = 261, 1258 .height = 163, 1259 }, 1260 .delay = { 1261 .prepare = 9, 1262 .enable = 300, 1263 .unprepare = 300, 1264 .disable = 560, 1265 }, 1266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1267 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1269 }; 1270 1271 static const struct drm_display_mode boe_hv070wsa_mode = { 1272 .clock = 42105, 1273 .hdisplay = 1024, 1274 .hsync_start = 1024 + 30, 1275 .hsync_end = 1024 + 30 + 30, 1276 .htotal = 1024 + 30 + 30 + 30, 1277 .vdisplay = 600, 1278 .vsync_start = 600 + 10, 1279 .vsync_end = 600 + 10 + 10, 1280 .vtotal = 600 + 10 + 10 + 10, 1281 }; 1282 1283 static const struct panel_desc boe_hv070wsa = { 1284 .modes = &boe_hv070wsa_mode, 1285 .num_modes = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 154, 1289 .height = 90, 1290 }, 1291 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1292 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1293 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1294 }; 1295 1296 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1297 .clock = 9000, 1298 .hdisplay = 480, 1299 .hsync_start = 480 + 5, 1300 .hsync_end = 480 + 5 + 5, 1301 .htotal = 480 + 5 + 5 + 40, 1302 .vdisplay = 272, 1303 .vsync_start = 272 + 8, 1304 .vsync_end = 272 + 8 + 8, 1305 .vtotal = 272 + 8 + 8 + 8, 1306 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1307 }; 1308 1309 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1310 .modes = &cdtech_s043wq26h_ct7_mode, 1311 .num_modes = 1, 1312 .bpc = 8, 1313 .size = { 1314 .width = 95, 1315 .height = 54, 1316 }, 1317 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1318 }; 1319 1320 /* S070PWS19HP-FC21 2017/04/22 */ 1321 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1322 .clock = 51200, 1323 .hdisplay = 1024, 1324 .hsync_start = 1024 + 160, 1325 .hsync_end = 1024 + 160 + 20, 1326 .htotal = 1024 + 160 + 20 + 140, 1327 .vdisplay = 600, 1328 .vsync_start = 600 + 12, 1329 .vsync_end = 600 + 12 + 3, 1330 .vtotal = 600 + 12 + 3 + 20, 1331 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1332 }; 1333 1334 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1335 .modes = &cdtech_s070pws19hp_fc21_mode, 1336 .num_modes = 1, 1337 .bpc = 6, 1338 .size = { 1339 .width = 154, 1340 .height = 86, 1341 }, 1342 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1343 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1344 .connector_type = DRM_MODE_CONNECTOR_DPI, 1345 }; 1346 1347 /* S070SWV29HG-DC44 2017/09/21 */ 1348 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1349 .clock = 33300, 1350 .hdisplay = 800, 1351 .hsync_start = 800 + 210, 1352 .hsync_end = 800 + 210 + 2, 1353 .htotal = 800 + 210 + 2 + 44, 1354 .vdisplay = 480, 1355 .vsync_start = 480 + 22, 1356 .vsync_end = 480 + 22 + 2, 1357 .vtotal = 480 + 22 + 2 + 21, 1358 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1359 }; 1360 1361 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1362 .modes = &cdtech_s070swv29hg_dc44_mode, 1363 .num_modes = 1, 1364 .bpc = 6, 1365 .size = { 1366 .width = 154, 1367 .height = 86, 1368 }, 1369 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1370 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1371 .connector_type = DRM_MODE_CONNECTOR_DPI, 1372 }; 1373 1374 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1375 .clock = 35000, 1376 .hdisplay = 800, 1377 .hsync_start = 800 + 40, 1378 .hsync_end = 800 + 40 + 40, 1379 .htotal = 800 + 40 + 40 + 48, 1380 .vdisplay = 480, 1381 .vsync_start = 480 + 29, 1382 .vsync_end = 480 + 29 + 13, 1383 .vtotal = 480 + 29 + 13 + 3, 1384 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1385 }; 1386 1387 static const struct panel_desc cdtech_s070wv95_ct16 = { 1388 .modes = &cdtech_s070wv95_ct16_mode, 1389 .num_modes = 1, 1390 .bpc = 8, 1391 .size = { 1392 .width = 154, 1393 .height = 85, 1394 }, 1395 }; 1396 1397 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1398 .pixelclock = { 68900000, 71100000, 73400000 }, 1399 .hactive = { 1280, 1280, 1280 }, 1400 .hfront_porch = { 65, 80, 95 }, 1401 .hback_porch = { 64, 79, 94 }, 1402 .hsync_len = { 1, 1, 1 }, 1403 .vactive = { 800, 800, 800 }, 1404 .vfront_porch = { 7, 11, 14 }, 1405 .vback_porch = { 7, 11, 14 }, 1406 .vsync_len = { 1, 1, 1 }, 1407 .flags = DISPLAY_FLAGS_DE_HIGH, 1408 }; 1409 1410 static const struct panel_desc chefree_ch101olhlwh_002 = { 1411 .timings = &chefree_ch101olhlwh_002_timing, 1412 .num_timings = 1, 1413 .bpc = 8, 1414 .size = { 1415 .width = 217, 1416 .height = 135, 1417 }, 1418 .delay = { 1419 .enable = 200, 1420 .disable = 200, 1421 }, 1422 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1423 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1425 }; 1426 1427 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1428 .clock = 66770, 1429 .hdisplay = 800, 1430 .hsync_start = 800 + 49, 1431 .hsync_end = 800 + 49 + 33, 1432 .htotal = 800 + 49 + 33 + 17, 1433 .vdisplay = 1280, 1434 .vsync_start = 1280 + 1, 1435 .vsync_end = 1280 + 1 + 7, 1436 .vtotal = 1280 + 1 + 7 + 15, 1437 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1438 }; 1439 1440 static const struct panel_desc chunghwa_claa070wp03xg = { 1441 .modes = &chunghwa_claa070wp03xg_mode, 1442 .num_modes = 1, 1443 .bpc = 6, 1444 .size = { 1445 .width = 94, 1446 .height = 150, 1447 }, 1448 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1449 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1450 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1451 }; 1452 1453 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1454 .clock = 72070, 1455 .hdisplay = 1366, 1456 .hsync_start = 1366 + 58, 1457 .hsync_end = 1366 + 58 + 58, 1458 .htotal = 1366 + 58 + 58 + 58, 1459 .vdisplay = 768, 1460 .vsync_start = 768 + 4, 1461 .vsync_end = 768 + 4 + 4, 1462 .vtotal = 768 + 4 + 4 + 4, 1463 }; 1464 1465 static const struct panel_desc chunghwa_claa101wa01a = { 1466 .modes = &chunghwa_claa101wa01a_mode, 1467 .num_modes = 1, 1468 .bpc = 6, 1469 .size = { 1470 .width = 220, 1471 .height = 120, 1472 }, 1473 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1474 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1475 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1476 }; 1477 1478 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1479 .clock = 69300, 1480 .hdisplay = 1366, 1481 .hsync_start = 1366 + 48, 1482 .hsync_end = 1366 + 48 + 32, 1483 .htotal = 1366 + 48 + 32 + 20, 1484 .vdisplay = 768, 1485 .vsync_start = 768 + 16, 1486 .vsync_end = 768 + 16 + 8, 1487 .vtotal = 768 + 16 + 8 + 16, 1488 }; 1489 1490 static const struct panel_desc chunghwa_claa101wb01 = { 1491 .modes = &chunghwa_claa101wb01_mode, 1492 .num_modes = 1, 1493 .bpc = 6, 1494 .size = { 1495 .width = 223, 1496 .height = 125, 1497 }, 1498 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1499 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1500 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1501 }; 1502 1503 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1504 .pixelclock = { 5000000, 9000000, 12000000 }, 1505 .hactive = { 480, 480, 480 }, 1506 .hfront_porch = { 12, 12, 12 }, 1507 .hback_porch = { 12, 12, 12 }, 1508 .hsync_len = { 21, 21, 21 }, 1509 .vactive = { 272, 272, 272 }, 1510 .vfront_porch = { 4, 4, 4 }, 1511 .vback_porch = { 4, 4, 4 }, 1512 .vsync_len = { 8, 8, 8 }, 1513 }; 1514 1515 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1516 .timings = &dataimage_fg040346dsswbg04_timing, 1517 .num_timings = 1, 1518 .bpc = 8, 1519 .size = { 1520 .width = 95, 1521 .height = 54, 1522 }, 1523 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1525 .connector_type = DRM_MODE_CONNECTOR_DPI, 1526 }; 1527 1528 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1529 .pixelclock = { 68900000, 71110000, 73400000 }, 1530 .hactive = { 1280, 1280, 1280 }, 1531 .vactive = { 800, 800, 800 }, 1532 .hback_porch = { 100, 100, 100 }, 1533 .hfront_porch = { 100, 100, 100 }, 1534 .vback_porch = { 5, 5, 5 }, 1535 .vfront_porch = { 5, 5, 5 }, 1536 .hsync_len = { 24, 24, 24 }, 1537 .vsync_len = { 3, 3, 3 }, 1538 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1539 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1540 }; 1541 1542 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1543 .timings = &dataimage_fg1001l0dsswmg01_timing, 1544 .num_timings = 1, 1545 .bpc = 8, 1546 .size = { 1547 .width = 217, 1548 .height = 136, 1549 }, 1550 }; 1551 1552 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1553 .clock = 33260, 1554 .hdisplay = 800, 1555 .hsync_start = 800 + 40, 1556 .hsync_end = 800 + 40 + 128, 1557 .htotal = 800 + 40 + 128 + 88, 1558 .vdisplay = 480, 1559 .vsync_start = 480 + 10, 1560 .vsync_end = 480 + 10 + 2, 1561 .vtotal = 480 + 10 + 2 + 33, 1562 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1563 }; 1564 1565 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1566 .modes = &dataimage_scf0700c48ggu18_mode, 1567 .num_modes = 1, 1568 .bpc = 8, 1569 .size = { 1570 .width = 152, 1571 .height = 91, 1572 }, 1573 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1574 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1575 }; 1576 1577 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1578 .pixelclock = { 45000000, 51200000, 57000000 }, 1579 .hactive = { 1024, 1024, 1024 }, 1580 .hfront_porch = { 100, 106, 113 }, 1581 .hback_porch = { 100, 106, 113 }, 1582 .hsync_len = { 100, 108, 114 }, 1583 .vactive = { 600, 600, 600 }, 1584 .vfront_porch = { 8, 11, 15 }, 1585 .vback_porch = { 8, 11, 15 }, 1586 .vsync_len = { 9, 13, 15 }, 1587 .flags = DISPLAY_FLAGS_DE_HIGH, 1588 }; 1589 1590 static const struct panel_desc dlc_dlc0700yzg_1 = { 1591 .timings = &dlc_dlc0700yzg_1_timing, 1592 .num_timings = 1, 1593 .bpc = 6, 1594 .size = { 1595 .width = 154, 1596 .height = 86, 1597 }, 1598 .delay = { 1599 .prepare = 30, 1600 .enable = 200, 1601 .disable = 200, 1602 }, 1603 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1604 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1605 }; 1606 1607 static const struct display_timing dlc_dlc1010gig_timing = { 1608 .pixelclock = { 68900000, 71100000, 73400000 }, 1609 .hactive = { 1280, 1280, 1280 }, 1610 .hfront_porch = { 43, 53, 63 }, 1611 .hback_porch = { 43, 53, 63 }, 1612 .hsync_len = { 44, 54, 64 }, 1613 .vactive = { 800, 800, 800 }, 1614 .vfront_porch = { 5, 8, 11 }, 1615 .vback_porch = { 5, 8, 11 }, 1616 .vsync_len = { 5, 7, 11 }, 1617 .flags = DISPLAY_FLAGS_DE_HIGH, 1618 }; 1619 1620 static const struct panel_desc dlc_dlc1010gig = { 1621 .timings = &dlc_dlc1010gig_timing, 1622 .num_timings = 1, 1623 .bpc = 8, 1624 .size = { 1625 .width = 216, 1626 .height = 135, 1627 }, 1628 .delay = { 1629 .prepare = 60, 1630 .enable = 150, 1631 .disable = 100, 1632 .unprepare = 60, 1633 }, 1634 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1635 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1636 }; 1637 1638 static const struct drm_display_mode edt_et035012dm6_mode = { 1639 .clock = 6500, 1640 .hdisplay = 320, 1641 .hsync_start = 320 + 20, 1642 .hsync_end = 320 + 20 + 30, 1643 .htotal = 320 + 20 + 68, 1644 .vdisplay = 240, 1645 .vsync_start = 240 + 4, 1646 .vsync_end = 240 + 4 + 4, 1647 .vtotal = 240 + 4 + 4 + 14, 1648 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1649 }; 1650 1651 static const struct panel_desc edt_et035012dm6 = { 1652 .modes = &edt_et035012dm6_mode, 1653 .num_modes = 1, 1654 .bpc = 8, 1655 .size = { 1656 .width = 70, 1657 .height = 52, 1658 }, 1659 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1660 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1661 }; 1662 1663 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1664 .clock = 6520, 1665 .hdisplay = 320, 1666 .hsync_start = 320 + 20, 1667 .hsync_end = 320 + 20 + 68, 1668 .htotal = 320 + 20 + 68, 1669 .vdisplay = 240, 1670 .vsync_start = 240 + 4, 1671 .vsync_end = 240 + 4 + 18, 1672 .vtotal = 240 + 4 + 18, 1673 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1674 }; 1675 1676 static const struct panel_desc edt_etm0350g0dh6 = { 1677 .modes = &edt_etm0350g0dh6_mode, 1678 .num_modes = 1, 1679 .bpc = 6, 1680 .size = { 1681 .width = 70, 1682 .height = 53, 1683 }, 1684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1685 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1686 .connector_type = DRM_MODE_CONNECTOR_DPI, 1687 }; 1688 1689 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1690 .clock = 10870, 1691 .hdisplay = 480, 1692 .hsync_start = 480 + 8, 1693 .hsync_end = 480 + 8 + 4, 1694 .htotal = 480 + 8 + 4 + 41, 1695 1696 /* 1697 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1698 * fb_align 1699 */ 1700 1701 .vdisplay = 288, 1702 .vsync_start = 288 + 2, 1703 .vsync_end = 288 + 2 + 4, 1704 .vtotal = 288 + 2 + 4 + 10, 1705 }; 1706 1707 static const struct panel_desc edt_etm043080dh6gp = { 1708 .modes = &edt_etm043080dh6gp_mode, 1709 .num_modes = 1, 1710 .bpc = 8, 1711 .size = { 1712 .width = 100, 1713 .height = 65, 1714 }, 1715 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1716 .connector_type = DRM_MODE_CONNECTOR_DPI, 1717 }; 1718 1719 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1720 .clock = 9000, 1721 .hdisplay = 480, 1722 .hsync_start = 480 + 2, 1723 .hsync_end = 480 + 2 + 41, 1724 .htotal = 480 + 2 + 41 + 2, 1725 .vdisplay = 272, 1726 .vsync_start = 272 + 2, 1727 .vsync_end = 272 + 2 + 10, 1728 .vtotal = 272 + 2 + 10 + 2, 1729 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1730 }; 1731 1732 static const struct panel_desc edt_etm0430g0dh6 = { 1733 .modes = &edt_etm0430g0dh6_mode, 1734 .num_modes = 1, 1735 .bpc = 6, 1736 .size = { 1737 .width = 95, 1738 .height = 54, 1739 }, 1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1742 .connector_type = DRM_MODE_CONNECTOR_DPI, 1743 }; 1744 1745 static const struct drm_display_mode edt_et057090dhu_mode = { 1746 .clock = 25175, 1747 .hdisplay = 640, 1748 .hsync_start = 640 + 16, 1749 .hsync_end = 640 + 16 + 30, 1750 .htotal = 640 + 16 + 30 + 114, 1751 .vdisplay = 480, 1752 .vsync_start = 480 + 10, 1753 .vsync_end = 480 + 10 + 3, 1754 .vtotal = 480 + 10 + 3 + 32, 1755 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1756 }; 1757 1758 static const struct panel_desc edt_et057090dhu = { 1759 .modes = &edt_et057090dhu_mode, 1760 .num_modes = 1, 1761 .bpc = 6, 1762 .size = { 1763 .width = 115, 1764 .height = 86, 1765 }, 1766 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1767 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1768 .connector_type = DRM_MODE_CONNECTOR_DPI, 1769 }; 1770 1771 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1772 .clock = 33260, 1773 .hdisplay = 800, 1774 .hsync_start = 800 + 40, 1775 .hsync_end = 800 + 40 + 128, 1776 .htotal = 800 + 40 + 128 + 88, 1777 .vdisplay = 480, 1778 .vsync_start = 480 + 10, 1779 .vsync_end = 480 + 10 + 2, 1780 .vtotal = 480 + 10 + 2 + 33, 1781 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1782 }; 1783 1784 static const struct panel_desc edt_etm0700g0dh6 = { 1785 .modes = &edt_etm0700g0dh6_mode, 1786 .num_modes = 1, 1787 .bpc = 6, 1788 .size = { 1789 .width = 152, 1790 .height = 91, 1791 }, 1792 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1793 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1794 .connector_type = DRM_MODE_CONNECTOR_DPI, 1795 }; 1796 1797 static const struct panel_desc edt_etm0700g0bdh6 = { 1798 .modes = &edt_etm0700g0dh6_mode, 1799 .num_modes = 1, 1800 .bpc = 6, 1801 .size = { 1802 .width = 152, 1803 .height = 91, 1804 }, 1805 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1806 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1807 .connector_type = DRM_MODE_CONNECTOR_DPI, 1808 }; 1809 1810 static const struct display_timing edt_etml0700y5dha_timing = { 1811 .pixelclock = { 40800000, 51200000, 67200000 }, 1812 .hactive = { 1024, 1024, 1024 }, 1813 .hfront_porch = { 30, 106, 125 }, 1814 .hback_porch = { 30, 106, 125 }, 1815 .hsync_len = { 30, 108, 126 }, 1816 .vactive = { 600, 600, 600 }, 1817 .vfront_porch = { 3, 12, 67}, 1818 .vback_porch = { 3, 12, 67 }, 1819 .vsync_len = { 4, 11, 66 }, 1820 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1821 DISPLAY_FLAGS_DE_HIGH, 1822 }; 1823 1824 static const struct panel_desc edt_etml0700y5dha = { 1825 .timings = &edt_etml0700y5dha_timing, 1826 .num_timings = 1, 1827 .bpc = 8, 1828 .size = { 1829 .width = 155, 1830 .height = 86, 1831 }, 1832 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1833 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1834 }; 1835 1836 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1837 .clock = 25175, 1838 .hdisplay = 640, 1839 .hsync_start = 640, 1840 .hsync_end = 640 + 16, 1841 .htotal = 640 + 16 + 30 + 114, 1842 .vdisplay = 480, 1843 .vsync_start = 480 + 10, 1844 .vsync_end = 480 + 10 + 3, 1845 .vtotal = 480 + 10 + 3 + 35, 1846 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1847 }; 1848 1849 static const struct panel_desc edt_etmv570g2dhu = { 1850 .modes = &edt_etmv570g2dhu_mode, 1851 .num_modes = 1, 1852 .bpc = 6, 1853 .size = { 1854 .width = 115, 1855 .height = 86, 1856 }, 1857 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1858 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1859 .connector_type = DRM_MODE_CONNECTOR_DPI, 1860 }; 1861 1862 static const struct display_timing eink_vb3300_kca_timing = { 1863 .pixelclock = { 40000000, 40000000, 40000000 }, 1864 .hactive = { 334, 334, 334 }, 1865 .hfront_porch = { 1, 1, 1 }, 1866 .hback_porch = { 1, 1, 1 }, 1867 .hsync_len = { 1, 1, 1 }, 1868 .vactive = { 1405, 1405, 1405 }, 1869 .vfront_porch = { 1, 1, 1 }, 1870 .vback_porch = { 1, 1, 1 }, 1871 .vsync_len = { 1, 1, 1 }, 1872 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1873 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1874 }; 1875 1876 static const struct panel_desc eink_vb3300_kca = { 1877 .timings = &eink_vb3300_kca_timing, 1878 .num_timings = 1, 1879 .bpc = 6, 1880 .size = { 1881 .width = 157, 1882 .height = 209, 1883 }, 1884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1886 .connector_type = DRM_MODE_CONNECTOR_DPI, 1887 }; 1888 1889 static const struct display_timing evervision_vgg804821_timing = { 1890 .pixelclock = { 27600000, 33300000, 50000000 }, 1891 .hactive = { 800, 800, 800 }, 1892 .hfront_porch = { 40, 66, 70 }, 1893 .hback_porch = { 40, 67, 70 }, 1894 .hsync_len = { 40, 67, 70 }, 1895 .vactive = { 480, 480, 480 }, 1896 .vfront_porch = { 6, 10, 10 }, 1897 .vback_porch = { 7, 11, 11 }, 1898 .vsync_len = { 7, 11, 11 }, 1899 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1900 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1901 DISPLAY_FLAGS_SYNC_NEGEDGE, 1902 }; 1903 1904 static const struct panel_desc evervision_vgg804821 = { 1905 .timings = &evervision_vgg804821_timing, 1906 .num_timings = 1, 1907 .bpc = 8, 1908 .size = { 1909 .width = 108, 1910 .height = 64, 1911 }, 1912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1914 }; 1915 1916 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1917 .clock = 32260, 1918 .hdisplay = 800, 1919 .hsync_start = 800 + 168, 1920 .hsync_end = 800 + 168 + 64, 1921 .htotal = 800 + 168 + 64 + 88, 1922 .vdisplay = 480, 1923 .vsync_start = 480 + 37, 1924 .vsync_end = 480 + 37 + 2, 1925 .vtotal = 480 + 37 + 2 + 8, 1926 }; 1927 1928 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1929 .modes = &foxlink_fl500wvr00_a0t_mode, 1930 .num_modes = 1, 1931 .bpc = 8, 1932 .size = { 1933 .width = 108, 1934 .height = 65, 1935 }, 1936 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1937 }; 1938 1939 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1940 { /* 60 Hz */ 1941 .clock = 6000, 1942 .hdisplay = 320, 1943 .hsync_start = 320 + 44, 1944 .hsync_end = 320 + 44 + 16, 1945 .htotal = 320 + 44 + 16 + 20, 1946 .vdisplay = 240, 1947 .vsync_start = 240 + 2, 1948 .vsync_end = 240 + 2 + 6, 1949 .vtotal = 240 + 2 + 6 + 2, 1950 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1951 }, 1952 { /* 50 Hz */ 1953 .clock = 5400, 1954 .hdisplay = 320, 1955 .hsync_start = 320 + 56, 1956 .hsync_end = 320 + 56 + 16, 1957 .htotal = 320 + 56 + 16 + 40, 1958 .vdisplay = 240, 1959 .vsync_start = 240 + 2, 1960 .vsync_end = 240 + 2 + 6, 1961 .vtotal = 240 + 2 + 6 + 2, 1962 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1963 }, 1964 }; 1965 1966 static const struct panel_desc frida_frd350h54004 = { 1967 .modes = frida_frd350h54004_modes, 1968 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1969 .bpc = 8, 1970 .size = { 1971 .width = 77, 1972 .height = 64, 1973 }, 1974 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1975 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1976 .connector_type = DRM_MODE_CONNECTOR_DPI, 1977 }; 1978 1979 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1980 .clock = 67185, 1981 .hdisplay = 800, 1982 .hsync_start = 800 + 20, 1983 .hsync_end = 800 + 20 + 24, 1984 .htotal = 800 + 20 + 24 + 20, 1985 .vdisplay = 1280, 1986 .vsync_start = 1280 + 4, 1987 .vsync_end = 1280 + 4 + 8, 1988 .vtotal = 1280 + 4 + 8 + 4, 1989 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1990 }; 1991 1992 static const struct panel_desc friendlyarm_hd702e = { 1993 .modes = &friendlyarm_hd702e_mode, 1994 .num_modes = 1, 1995 .size = { 1996 .width = 94, 1997 .height = 151, 1998 }, 1999 }; 2000 2001 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2002 .clock = 9000, 2003 .hdisplay = 480, 2004 .hsync_start = 480 + 5, 2005 .hsync_end = 480 + 5 + 1, 2006 .htotal = 480 + 5 + 1 + 40, 2007 .vdisplay = 272, 2008 .vsync_start = 272 + 8, 2009 .vsync_end = 272 + 8 + 1, 2010 .vtotal = 272 + 8 + 1 + 8, 2011 }; 2012 2013 static const struct panel_desc giantplus_gpg482739qs5 = { 2014 .modes = &giantplus_gpg482739qs5_mode, 2015 .num_modes = 1, 2016 .bpc = 8, 2017 .size = { 2018 .width = 95, 2019 .height = 54, 2020 }, 2021 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2022 }; 2023 2024 static const struct display_timing giantplus_gpm940b0_timing = { 2025 .pixelclock = { 13500000, 27000000, 27500000 }, 2026 .hactive = { 320, 320, 320 }, 2027 .hfront_porch = { 14, 686, 718 }, 2028 .hback_porch = { 50, 70, 255 }, 2029 .hsync_len = { 1, 1, 1 }, 2030 .vactive = { 240, 240, 240 }, 2031 .vfront_porch = { 1, 1, 179 }, 2032 .vback_porch = { 1, 21, 31 }, 2033 .vsync_len = { 1, 1, 6 }, 2034 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2035 }; 2036 2037 static const struct panel_desc giantplus_gpm940b0 = { 2038 .timings = &giantplus_gpm940b0_timing, 2039 .num_timings = 1, 2040 .bpc = 8, 2041 .size = { 2042 .width = 60, 2043 .height = 45, 2044 }, 2045 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2047 }; 2048 2049 static const struct display_timing hannstar_hsd070pww1_timing = { 2050 .pixelclock = { 64300000, 71100000, 82000000 }, 2051 .hactive = { 1280, 1280, 1280 }, 2052 .hfront_porch = { 1, 1, 10 }, 2053 .hback_porch = { 1, 1, 10 }, 2054 /* 2055 * According to the data sheet, the minimum horizontal blanking interval 2056 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2057 * minimum working horizontal blanking interval to be 60 clocks. 2058 */ 2059 .hsync_len = { 58, 158, 661 }, 2060 .vactive = { 800, 800, 800 }, 2061 .vfront_porch = { 1, 1, 10 }, 2062 .vback_porch = { 1, 1, 10 }, 2063 .vsync_len = { 1, 21, 203 }, 2064 .flags = DISPLAY_FLAGS_DE_HIGH, 2065 }; 2066 2067 static const struct panel_desc hannstar_hsd070pww1 = { 2068 .timings = &hannstar_hsd070pww1_timing, 2069 .num_timings = 1, 2070 .bpc = 6, 2071 .size = { 2072 .width = 151, 2073 .height = 94, 2074 }, 2075 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2076 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2077 }; 2078 2079 static const struct display_timing hannstar_hsd100pxn1_timing = { 2080 .pixelclock = { 55000000, 65000000, 75000000 }, 2081 .hactive = { 1024, 1024, 1024 }, 2082 .hfront_porch = { 40, 40, 40 }, 2083 .hback_porch = { 220, 220, 220 }, 2084 .hsync_len = { 20, 60, 100 }, 2085 .vactive = { 768, 768, 768 }, 2086 .vfront_porch = { 7, 7, 7 }, 2087 .vback_porch = { 21, 21, 21 }, 2088 .vsync_len = { 10, 10, 10 }, 2089 .flags = DISPLAY_FLAGS_DE_HIGH, 2090 }; 2091 2092 static const struct panel_desc hannstar_hsd100pxn1 = { 2093 .timings = &hannstar_hsd100pxn1_timing, 2094 .num_timings = 1, 2095 .bpc = 6, 2096 .size = { 2097 .width = 203, 2098 .height = 152, 2099 }, 2100 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2101 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2102 }; 2103 2104 static const struct display_timing hannstar_hsd101pww2_timing = { 2105 .pixelclock = { 64300000, 71100000, 82000000 }, 2106 .hactive = { 1280, 1280, 1280 }, 2107 .hfront_porch = { 1, 1, 10 }, 2108 .hback_porch = { 1, 1, 10 }, 2109 .hsync_len = { 58, 158, 661 }, 2110 .vactive = { 800, 800, 800 }, 2111 .vfront_porch = { 1, 1, 10 }, 2112 .vback_porch = { 1, 1, 10 }, 2113 .vsync_len = { 1, 21, 203 }, 2114 .flags = DISPLAY_FLAGS_DE_HIGH, 2115 }; 2116 2117 static const struct panel_desc hannstar_hsd101pww2 = { 2118 .timings = &hannstar_hsd101pww2_timing, 2119 .num_timings = 1, 2120 .bpc = 8, 2121 .size = { 2122 .width = 217, 2123 .height = 136, 2124 }, 2125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2126 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2127 }; 2128 2129 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2130 .clock = 33333, 2131 .hdisplay = 800, 2132 .hsync_start = 800 + 85, 2133 .hsync_end = 800 + 85 + 86, 2134 .htotal = 800 + 85 + 86 + 85, 2135 .vdisplay = 480, 2136 .vsync_start = 480 + 16, 2137 .vsync_end = 480 + 16 + 13, 2138 .vtotal = 480 + 16 + 13 + 16, 2139 }; 2140 2141 static const struct panel_desc hitachi_tx23d38vm0caa = { 2142 .modes = &hitachi_tx23d38vm0caa_mode, 2143 .num_modes = 1, 2144 .bpc = 6, 2145 .size = { 2146 .width = 195, 2147 .height = 117, 2148 }, 2149 .delay = { 2150 .enable = 160, 2151 .disable = 160, 2152 }, 2153 }; 2154 2155 static const struct drm_display_mode innolux_at043tn24_mode = { 2156 .clock = 9000, 2157 .hdisplay = 480, 2158 .hsync_start = 480 + 2, 2159 .hsync_end = 480 + 2 + 41, 2160 .htotal = 480 + 2 + 41 + 2, 2161 .vdisplay = 272, 2162 .vsync_start = 272 + 2, 2163 .vsync_end = 272 + 2 + 10, 2164 .vtotal = 272 + 2 + 10 + 2, 2165 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2166 }; 2167 2168 static const struct panel_desc innolux_at043tn24 = { 2169 .modes = &innolux_at043tn24_mode, 2170 .num_modes = 1, 2171 .bpc = 8, 2172 .size = { 2173 .width = 95, 2174 .height = 54, 2175 }, 2176 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2177 .connector_type = DRM_MODE_CONNECTOR_DPI, 2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2179 }; 2180 2181 static const struct drm_display_mode innolux_at070tn92_mode = { 2182 .clock = 33333, 2183 .hdisplay = 800, 2184 .hsync_start = 800 + 210, 2185 .hsync_end = 800 + 210 + 20, 2186 .htotal = 800 + 210 + 20 + 46, 2187 .vdisplay = 480, 2188 .vsync_start = 480 + 22, 2189 .vsync_end = 480 + 22 + 10, 2190 .vtotal = 480 + 22 + 23 + 10, 2191 }; 2192 2193 static const struct panel_desc innolux_at070tn92 = { 2194 .modes = &innolux_at070tn92_mode, 2195 .num_modes = 1, 2196 .size = { 2197 .width = 154, 2198 .height = 86, 2199 }, 2200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2201 }; 2202 2203 static const struct display_timing innolux_g070ace_l01_timing = { 2204 .pixelclock = { 25200000, 35000000, 35700000 }, 2205 .hactive = { 800, 800, 800 }, 2206 .hfront_porch = { 30, 32, 87 }, 2207 .hback_porch = { 30, 32, 87 }, 2208 .hsync_len = { 1, 1, 1 }, 2209 .vactive = { 480, 480, 480 }, 2210 .vfront_porch = { 3, 3, 3 }, 2211 .vback_porch = { 13, 13, 13 }, 2212 .vsync_len = { 1, 1, 4 }, 2213 .flags = DISPLAY_FLAGS_DE_HIGH, 2214 }; 2215 2216 static const struct panel_desc innolux_g070ace_l01 = { 2217 .timings = &innolux_g070ace_l01_timing, 2218 .num_timings = 1, 2219 .bpc = 8, 2220 .size = { 2221 .width = 152, 2222 .height = 91, 2223 }, 2224 .delay = { 2225 .prepare = 10, 2226 .enable = 50, 2227 .disable = 50, 2228 .unprepare = 500, 2229 }, 2230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2231 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2232 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2233 }; 2234 2235 static const struct display_timing innolux_g070y2_l01_timing = { 2236 .pixelclock = { 28000000, 29500000, 32000000 }, 2237 .hactive = { 800, 800, 800 }, 2238 .hfront_porch = { 61, 91, 141 }, 2239 .hback_porch = { 60, 90, 140 }, 2240 .hsync_len = { 12, 12, 12 }, 2241 .vactive = { 480, 480, 480 }, 2242 .vfront_porch = { 4, 9, 30 }, 2243 .vback_porch = { 4, 8, 28 }, 2244 .vsync_len = { 2, 2, 2 }, 2245 .flags = DISPLAY_FLAGS_DE_HIGH, 2246 }; 2247 2248 static const struct panel_desc innolux_g070y2_l01 = { 2249 .timings = &innolux_g070y2_l01_timing, 2250 .num_timings = 1, 2251 .bpc = 8, 2252 .size = { 2253 .width = 152, 2254 .height = 91, 2255 }, 2256 .delay = { 2257 .prepare = 10, 2258 .enable = 100, 2259 .disable = 100, 2260 .unprepare = 800, 2261 }, 2262 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2263 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2264 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2265 }; 2266 2267 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2268 .clock = 33333, 2269 .hdisplay = 800, 2270 .hsync_start = 800 + 210, 2271 .hsync_end = 800 + 210 + 20, 2272 .htotal = 800 + 210 + 20 + 46, 2273 .vdisplay = 480, 2274 .vsync_start = 480 + 22, 2275 .vsync_end = 480 + 22 + 10, 2276 .vtotal = 480 + 22 + 23 + 10, 2277 }; 2278 2279 static const struct panel_desc innolux_g070y2_t02 = { 2280 .modes = &innolux_g070y2_t02_mode, 2281 .num_modes = 1, 2282 .bpc = 8, 2283 .size = { 2284 .width = 152, 2285 .height = 92, 2286 }, 2287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2288 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2289 .connector_type = DRM_MODE_CONNECTOR_DPI, 2290 }; 2291 2292 static const struct display_timing innolux_g101ice_l01_timing = { 2293 .pixelclock = { 60400000, 71100000, 74700000 }, 2294 .hactive = { 1280, 1280, 1280 }, 2295 .hfront_porch = { 41, 80, 100 }, 2296 .hback_porch = { 40, 79, 99 }, 2297 .hsync_len = { 1, 1, 1 }, 2298 .vactive = { 800, 800, 800 }, 2299 .vfront_porch = { 5, 11, 14 }, 2300 .vback_porch = { 4, 11, 14 }, 2301 .vsync_len = { 1, 1, 1 }, 2302 .flags = DISPLAY_FLAGS_DE_HIGH, 2303 }; 2304 2305 static const struct panel_desc innolux_g101ice_l01 = { 2306 .timings = &innolux_g101ice_l01_timing, 2307 .num_timings = 1, 2308 .bpc = 8, 2309 .size = { 2310 .width = 217, 2311 .height = 135, 2312 }, 2313 .delay = { 2314 .enable = 200, 2315 .disable = 200, 2316 }, 2317 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2318 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2319 }; 2320 2321 static const struct display_timing innolux_g121i1_l01_timing = { 2322 .pixelclock = { 67450000, 71000000, 74550000 }, 2323 .hactive = { 1280, 1280, 1280 }, 2324 .hfront_porch = { 40, 80, 160 }, 2325 .hback_porch = { 39, 79, 159 }, 2326 .hsync_len = { 1, 1, 1 }, 2327 .vactive = { 800, 800, 800 }, 2328 .vfront_porch = { 5, 11, 100 }, 2329 .vback_porch = { 4, 11, 99 }, 2330 .vsync_len = { 1, 1, 1 }, 2331 }; 2332 2333 static const struct panel_desc innolux_g121i1_l01 = { 2334 .timings = &innolux_g121i1_l01_timing, 2335 .num_timings = 1, 2336 .bpc = 6, 2337 .size = { 2338 .width = 261, 2339 .height = 163, 2340 }, 2341 .delay = { 2342 .enable = 200, 2343 .disable = 20, 2344 }, 2345 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2346 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2347 }; 2348 2349 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2350 .clock = 65000, 2351 .hdisplay = 1024, 2352 .hsync_start = 1024 + 0, 2353 .hsync_end = 1024 + 1, 2354 .htotal = 1024 + 0 + 1 + 320, 2355 .vdisplay = 768, 2356 .vsync_start = 768 + 38, 2357 .vsync_end = 768 + 38 + 1, 2358 .vtotal = 768 + 38 + 1 + 0, 2359 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2360 }; 2361 2362 static const struct panel_desc innolux_g121x1_l03 = { 2363 .modes = &innolux_g121x1_l03_mode, 2364 .num_modes = 1, 2365 .bpc = 6, 2366 .size = { 2367 .width = 246, 2368 .height = 185, 2369 }, 2370 .delay = { 2371 .enable = 200, 2372 .unprepare = 200, 2373 .disable = 400, 2374 }, 2375 }; 2376 2377 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2378 .clock = 69300, 2379 .hdisplay = 1366, 2380 .hsync_start = 1366 + 16, 2381 .hsync_end = 1366 + 16 + 34, 2382 .htotal = 1366 + 16 + 34 + 50, 2383 .vdisplay = 768, 2384 .vsync_start = 768 + 2, 2385 .vsync_end = 768 + 2 + 6, 2386 .vtotal = 768 + 2 + 6 + 12, 2387 }; 2388 2389 static const struct panel_desc innolux_n156bge_l21 = { 2390 .modes = &innolux_n156bge_l21_mode, 2391 .num_modes = 1, 2392 .bpc = 6, 2393 .size = { 2394 .width = 344, 2395 .height = 193, 2396 }, 2397 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2398 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2399 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2400 }; 2401 2402 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2403 .clock = 51501, 2404 .hdisplay = 1024, 2405 .hsync_start = 1024 + 128, 2406 .hsync_end = 1024 + 128 + 64, 2407 .htotal = 1024 + 128 + 64 + 128, 2408 .vdisplay = 600, 2409 .vsync_start = 600 + 16, 2410 .vsync_end = 600 + 16 + 4, 2411 .vtotal = 600 + 16 + 4 + 16, 2412 }; 2413 2414 static const struct panel_desc innolux_zj070na_01p = { 2415 .modes = &innolux_zj070na_01p_mode, 2416 .num_modes = 1, 2417 .bpc = 6, 2418 .size = { 2419 .width = 154, 2420 .height = 90, 2421 }, 2422 }; 2423 2424 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2425 .pixelclock = { 5580000, 5850000, 6200000 }, 2426 .hactive = { 320, 320, 320 }, 2427 .hfront_porch = { 30, 30, 30 }, 2428 .hback_porch = { 30, 30, 30 }, 2429 .hsync_len = { 1, 5, 17 }, 2430 .vactive = { 240, 240, 240 }, 2431 .vfront_porch = { 6, 6, 6 }, 2432 .vback_porch = { 5, 5, 5 }, 2433 .vsync_len = { 1, 2, 11 }, 2434 .flags = DISPLAY_FLAGS_DE_HIGH, 2435 }; 2436 2437 static const struct panel_desc koe_tx14d24vm1bpa = { 2438 .timings = &koe_tx14d24vm1bpa_timing, 2439 .num_timings = 1, 2440 .bpc = 6, 2441 .size = { 2442 .width = 115, 2443 .height = 86, 2444 }, 2445 }; 2446 2447 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2448 .pixelclock = { 151820000, 156720000, 159780000 }, 2449 .hactive = { 1920, 1920, 1920 }, 2450 .hfront_porch = { 105, 130, 142 }, 2451 .hback_porch = { 45, 70, 82 }, 2452 .hsync_len = { 30, 30, 30 }, 2453 .vactive = { 1200, 1200, 1200}, 2454 .vfront_porch = { 3, 5, 10 }, 2455 .vback_porch = { 2, 5, 10 }, 2456 .vsync_len = { 5, 5, 5 }, 2457 }; 2458 2459 static const struct panel_desc koe_tx26d202vm0bwa = { 2460 .timings = &koe_tx26d202vm0bwa_timing, 2461 .num_timings = 1, 2462 .bpc = 8, 2463 .size = { 2464 .width = 217, 2465 .height = 136, 2466 }, 2467 .delay = { 2468 .prepare = 1000, 2469 .enable = 1000, 2470 .unprepare = 1000, 2471 .disable = 1000, 2472 }, 2473 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2474 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2475 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2476 }; 2477 2478 static const struct display_timing koe_tx31d200vm0baa_timing = { 2479 .pixelclock = { 39600000, 43200000, 48000000 }, 2480 .hactive = { 1280, 1280, 1280 }, 2481 .hfront_porch = { 16, 36, 56 }, 2482 .hback_porch = { 16, 36, 56 }, 2483 .hsync_len = { 8, 8, 8 }, 2484 .vactive = { 480, 480, 480 }, 2485 .vfront_porch = { 6, 21, 33 }, 2486 .vback_porch = { 6, 21, 33 }, 2487 .vsync_len = { 8, 8, 8 }, 2488 .flags = DISPLAY_FLAGS_DE_HIGH, 2489 }; 2490 2491 static const struct panel_desc koe_tx31d200vm0baa = { 2492 .timings = &koe_tx31d200vm0baa_timing, 2493 .num_timings = 1, 2494 .bpc = 6, 2495 .size = { 2496 .width = 292, 2497 .height = 109, 2498 }, 2499 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2500 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2501 }; 2502 2503 static const struct display_timing kyo_tcg121xglp_timing = { 2504 .pixelclock = { 52000000, 65000000, 71000000 }, 2505 .hactive = { 1024, 1024, 1024 }, 2506 .hfront_porch = { 2, 2, 2 }, 2507 .hback_porch = { 2, 2, 2 }, 2508 .hsync_len = { 86, 124, 244 }, 2509 .vactive = { 768, 768, 768 }, 2510 .vfront_porch = { 2, 2, 2 }, 2511 .vback_porch = { 2, 2, 2 }, 2512 .vsync_len = { 6, 34, 73 }, 2513 .flags = DISPLAY_FLAGS_DE_HIGH, 2514 }; 2515 2516 static const struct panel_desc kyo_tcg121xglp = { 2517 .timings = &kyo_tcg121xglp_timing, 2518 .num_timings = 1, 2519 .bpc = 8, 2520 .size = { 2521 .width = 246, 2522 .height = 184, 2523 }, 2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2525 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2526 }; 2527 2528 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2529 .clock = 7000, 2530 .hdisplay = 320, 2531 .hsync_start = 320 + 20, 2532 .hsync_end = 320 + 20 + 30, 2533 .htotal = 320 + 20 + 30 + 38, 2534 .vdisplay = 240, 2535 .vsync_start = 240 + 4, 2536 .vsync_end = 240 + 4 + 3, 2537 .vtotal = 240 + 4 + 3 + 15, 2538 }; 2539 2540 static const struct panel_desc lemaker_bl035_rgb_002 = { 2541 .modes = &lemaker_bl035_rgb_002_mode, 2542 .num_modes = 1, 2543 .size = { 2544 .width = 70, 2545 .height = 52, 2546 }, 2547 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2548 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2549 }; 2550 2551 static const struct drm_display_mode lg_lb070wv8_mode = { 2552 .clock = 33246, 2553 .hdisplay = 800, 2554 .hsync_start = 800 + 88, 2555 .hsync_end = 800 + 88 + 80, 2556 .htotal = 800 + 88 + 80 + 88, 2557 .vdisplay = 480, 2558 .vsync_start = 480 + 10, 2559 .vsync_end = 480 + 10 + 25, 2560 .vtotal = 480 + 10 + 25 + 10, 2561 }; 2562 2563 static const struct panel_desc lg_lb070wv8 = { 2564 .modes = &lg_lb070wv8_mode, 2565 .num_modes = 1, 2566 .bpc = 8, 2567 .size = { 2568 .width = 151, 2569 .height = 91, 2570 }, 2571 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2572 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2573 }; 2574 2575 static const struct display_timing logictechno_lt161010_2nh_timing = { 2576 .pixelclock = { 26400000, 33300000, 46800000 }, 2577 .hactive = { 800, 800, 800 }, 2578 .hfront_porch = { 16, 210, 354 }, 2579 .hback_porch = { 46, 46, 46 }, 2580 .hsync_len = { 1, 20, 40 }, 2581 .vactive = { 480, 480, 480 }, 2582 .vfront_porch = { 7, 22, 147 }, 2583 .vback_porch = { 23, 23, 23 }, 2584 .vsync_len = { 1, 10, 20 }, 2585 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2586 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2587 DISPLAY_FLAGS_SYNC_POSEDGE, 2588 }; 2589 2590 static const struct panel_desc logictechno_lt161010_2nh = { 2591 .timings = &logictechno_lt161010_2nh_timing, 2592 .num_timings = 1, 2593 .bpc = 6, 2594 .size = { 2595 .width = 154, 2596 .height = 86, 2597 }, 2598 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2599 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2600 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2601 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2602 .connector_type = DRM_MODE_CONNECTOR_DPI, 2603 }; 2604 2605 static const struct display_timing logictechno_lt170410_2whc_timing = { 2606 .pixelclock = { 68900000, 71100000, 73400000 }, 2607 .hactive = { 1280, 1280, 1280 }, 2608 .hfront_porch = { 23, 60, 71 }, 2609 .hback_porch = { 23, 60, 71 }, 2610 .hsync_len = { 15, 40, 47 }, 2611 .vactive = { 800, 800, 800 }, 2612 .vfront_porch = { 5, 7, 10 }, 2613 .vback_porch = { 5, 7, 10 }, 2614 .vsync_len = { 6, 9, 12 }, 2615 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2616 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2617 DISPLAY_FLAGS_SYNC_POSEDGE, 2618 }; 2619 2620 static const struct panel_desc logictechno_lt170410_2whc = { 2621 .timings = &logictechno_lt170410_2whc_timing, 2622 .num_timings = 1, 2623 .bpc = 8, 2624 .size = { 2625 .width = 217, 2626 .height = 136, 2627 }, 2628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2629 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2630 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2631 }; 2632 2633 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2634 .clock = 33000, 2635 .hdisplay = 800, 2636 .hsync_start = 800 + 112, 2637 .hsync_end = 800 + 112 + 3, 2638 .htotal = 800 + 112 + 3 + 85, 2639 .vdisplay = 480, 2640 .vsync_start = 480 + 38, 2641 .vsync_end = 480 + 38 + 3, 2642 .vtotal = 480 + 38 + 3 + 29, 2643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2644 }; 2645 2646 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2647 .modes = &logictechno_lttd800480070_l2rt_mode, 2648 .num_modes = 1, 2649 .bpc = 8, 2650 .size = { 2651 .width = 154, 2652 .height = 86, 2653 }, 2654 .delay = { 2655 .prepare = 45, 2656 .enable = 100, 2657 .disable = 100, 2658 .unprepare = 45 2659 }, 2660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2661 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2662 .connector_type = DRM_MODE_CONNECTOR_DPI, 2663 }; 2664 2665 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2666 .clock = 33000, 2667 .hdisplay = 800, 2668 .hsync_start = 800 + 154, 2669 .hsync_end = 800 + 154 + 3, 2670 .htotal = 800 + 154 + 3 + 43, 2671 .vdisplay = 480, 2672 .vsync_start = 480 + 47, 2673 .vsync_end = 480 + 47 + 3, 2674 .vtotal = 480 + 47 + 3 + 20, 2675 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2676 }; 2677 2678 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2679 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2680 .num_modes = 1, 2681 .bpc = 8, 2682 .size = { 2683 .width = 154, 2684 .height = 86, 2685 }, 2686 .delay = { 2687 .prepare = 45, 2688 .enable = 100, 2689 .disable = 100, 2690 .unprepare = 45 2691 }, 2692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2693 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2694 .connector_type = DRM_MODE_CONNECTOR_DPI, 2695 }; 2696 2697 static const struct drm_display_mode logicpd_type_28_mode = { 2698 .clock = 9107, 2699 .hdisplay = 480, 2700 .hsync_start = 480 + 3, 2701 .hsync_end = 480 + 3 + 42, 2702 .htotal = 480 + 3 + 42 + 2, 2703 2704 .vdisplay = 272, 2705 .vsync_start = 272 + 2, 2706 .vsync_end = 272 + 2 + 11, 2707 .vtotal = 272 + 2 + 11 + 3, 2708 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2709 }; 2710 2711 static const struct panel_desc logicpd_type_28 = { 2712 .modes = &logicpd_type_28_mode, 2713 .num_modes = 1, 2714 .bpc = 8, 2715 .size = { 2716 .width = 105, 2717 .height = 67, 2718 }, 2719 .delay = { 2720 .prepare = 200, 2721 .enable = 200, 2722 .unprepare = 200, 2723 .disable = 200, 2724 }, 2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2727 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2728 .connector_type = DRM_MODE_CONNECTOR_DPI, 2729 }; 2730 2731 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2732 .clock = 30400, 2733 .hdisplay = 800, 2734 .hsync_start = 800 + 0, 2735 .hsync_end = 800 + 1, 2736 .htotal = 800 + 0 + 1 + 160, 2737 .vdisplay = 480, 2738 .vsync_start = 480 + 0, 2739 .vsync_end = 480 + 48 + 1, 2740 .vtotal = 480 + 48 + 1 + 0, 2741 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2742 }; 2743 2744 static const struct panel_desc mitsubishi_aa070mc01 = { 2745 .modes = &mitsubishi_aa070mc01_mode, 2746 .num_modes = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 152, 2750 .height = 91, 2751 }, 2752 2753 .delay = { 2754 .enable = 200, 2755 .unprepare = 200, 2756 .disable = 400, 2757 }, 2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2760 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2761 }; 2762 2763 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2764 .pixelclock = { 29000000, 33000000, 38000000 }, 2765 .hactive = { 800, 800, 800 }, 2766 .hfront_porch = { 180, 210, 240 }, 2767 .hback_porch = { 16, 16, 16 }, 2768 .hsync_len = { 30, 30, 30 }, 2769 .vactive = { 480, 480, 480 }, 2770 .vfront_porch = { 12, 22, 32 }, 2771 .vback_porch = { 10, 10, 10 }, 2772 .vsync_len = { 13, 13, 13 }, 2773 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2774 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2775 DISPLAY_FLAGS_SYNC_POSEDGE, 2776 }; 2777 2778 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2779 .timings = &multi_inno_mi0700s4t_6_timing, 2780 .num_timings = 1, 2781 .bpc = 8, 2782 .size = { 2783 .width = 154, 2784 .height = 86, 2785 }, 2786 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2787 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2788 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2789 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2790 .connector_type = DRM_MODE_CONNECTOR_DPI, 2791 }; 2792 2793 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2794 .pixelclock = { 32000000, 40000000, 50000000 }, 2795 .hactive = { 800, 800, 800 }, 2796 .hfront_porch = { 16, 210, 354 }, 2797 .hback_porch = { 6, 26, 45 }, 2798 .hsync_len = { 1, 20, 40 }, 2799 .vactive = { 600, 600, 600 }, 2800 .vfront_porch = { 1, 12, 77 }, 2801 .vback_porch = { 3, 13, 22 }, 2802 .vsync_len = { 1, 10, 20 }, 2803 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2804 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2805 DISPLAY_FLAGS_SYNC_POSEDGE, 2806 }; 2807 2808 static const struct panel_desc multi_inno_mi0800ft_9 = { 2809 .timings = &multi_inno_mi0800ft_9_timing, 2810 .num_timings = 1, 2811 .bpc = 8, 2812 .size = { 2813 .width = 162, 2814 .height = 122, 2815 }, 2816 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2817 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2818 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2819 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2820 .connector_type = DRM_MODE_CONNECTOR_DPI, 2821 }; 2822 2823 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2824 .pixelclock = { 68900000, 70000000, 73400000 }, 2825 .hactive = { 1280, 1280, 1280 }, 2826 .hfront_porch = { 30, 60, 71 }, 2827 .hback_porch = { 30, 60, 71 }, 2828 .hsync_len = { 10, 10, 48 }, 2829 .vactive = { 800, 800, 800 }, 2830 .vfront_porch = { 5, 10, 10 }, 2831 .vback_porch = { 5, 10, 10 }, 2832 .vsync_len = { 5, 6, 13 }, 2833 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2834 DISPLAY_FLAGS_DE_HIGH, 2835 }; 2836 2837 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2838 .timings = &multi_inno_mi1010ait_1cp_timing, 2839 .num_timings = 1, 2840 .bpc = 8, 2841 .size = { 2842 .width = 217, 2843 .height = 136, 2844 }, 2845 .delay = { 2846 .enable = 50, 2847 .disable = 50, 2848 }, 2849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2850 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2851 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2852 }; 2853 2854 static const struct display_timing nec_nl12880bc20_05_timing = { 2855 .pixelclock = { 67000000, 71000000, 75000000 }, 2856 .hactive = { 1280, 1280, 1280 }, 2857 .hfront_porch = { 2, 30, 30 }, 2858 .hback_porch = { 6, 100, 100 }, 2859 .hsync_len = { 2, 30, 30 }, 2860 .vactive = { 800, 800, 800 }, 2861 .vfront_porch = { 5, 5, 5 }, 2862 .vback_porch = { 11, 11, 11 }, 2863 .vsync_len = { 7, 7, 7 }, 2864 }; 2865 2866 static const struct panel_desc nec_nl12880bc20_05 = { 2867 .timings = &nec_nl12880bc20_05_timing, 2868 .num_timings = 1, 2869 .bpc = 8, 2870 .size = { 2871 .width = 261, 2872 .height = 163, 2873 }, 2874 .delay = { 2875 .enable = 50, 2876 .disable = 50, 2877 }, 2878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2879 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2880 }; 2881 2882 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2883 .clock = 10870, 2884 .hdisplay = 480, 2885 .hsync_start = 480 + 2, 2886 .hsync_end = 480 + 2 + 41, 2887 .htotal = 480 + 2 + 41 + 2, 2888 .vdisplay = 272, 2889 .vsync_start = 272 + 2, 2890 .vsync_end = 272 + 2 + 4, 2891 .vtotal = 272 + 2 + 4 + 2, 2892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2893 }; 2894 2895 static const struct panel_desc nec_nl4827hc19_05b = { 2896 .modes = &nec_nl4827hc19_05b_mode, 2897 .num_modes = 1, 2898 .bpc = 8, 2899 .size = { 2900 .width = 95, 2901 .height = 54, 2902 }, 2903 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2904 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2905 }; 2906 2907 static const struct drm_display_mode netron_dy_e231732_mode = { 2908 .clock = 66000, 2909 .hdisplay = 1024, 2910 .hsync_start = 1024 + 160, 2911 .hsync_end = 1024 + 160 + 70, 2912 .htotal = 1024 + 160 + 70 + 90, 2913 .vdisplay = 600, 2914 .vsync_start = 600 + 127, 2915 .vsync_end = 600 + 127 + 20, 2916 .vtotal = 600 + 127 + 20 + 3, 2917 }; 2918 2919 static const struct panel_desc netron_dy_e231732 = { 2920 .modes = &netron_dy_e231732_mode, 2921 .num_modes = 1, 2922 .size = { 2923 .width = 154, 2924 .height = 87, 2925 }, 2926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2927 }; 2928 2929 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2930 .clock = 9000, 2931 .hdisplay = 480, 2932 .hsync_start = 480 + 2, 2933 .hsync_end = 480 + 2 + 41, 2934 .htotal = 480 + 2 + 41 + 2, 2935 .vdisplay = 272, 2936 .vsync_start = 272 + 2, 2937 .vsync_end = 272 + 2 + 10, 2938 .vtotal = 272 + 2 + 10 + 2, 2939 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2940 }; 2941 2942 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2943 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2944 .num_modes = 1, 2945 .bpc = 8, 2946 .size = { 2947 .width = 95, 2948 .height = 54, 2949 }, 2950 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2951 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2952 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2953 .connector_type = DRM_MODE_CONNECTOR_DPI, 2954 }; 2955 2956 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2957 .pixelclock = { 130000000, 148350000, 163000000 }, 2958 .hactive = { 1920, 1920, 1920 }, 2959 .hfront_porch = { 80, 100, 100 }, 2960 .hback_porch = { 100, 120, 120 }, 2961 .hsync_len = { 50, 60, 60 }, 2962 .vactive = { 1080, 1080, 1080 }, 2963 .vfront_porch = { 12, 30, 30 }, 2964 .vback_porch = { 4, 10, 10 }, 2965 .vsync_len = { 4, 5, 5 }, 2966 }; 2967 2968 static const struct panel_desc nlt_nl192108ac18_02d = { 2969 .timings = &nlt_nl192108ac18_02d_timing, 2970 .num_timings = 1, 2971 .bpc = 8, 2972 .size = { 2973 .width = 344, 2974 .height = 194, 2975 }, 2976 .delay = { 2977 .unprepare = 500, 2978 }, 2979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2981 }; 2982 2983 static const struct drm_display_mode nvd_9128_mode = { 2984 .clock = 29500, 2985 .hdisplay = 800, 2986 .hsync_start = 800 + 130, 2987 .hsync_end = 800 + 130 + 98, 2988 .htotal = 800 + 0 + 130 + 98, 2989 .vdisplay = 480, 2990 .vsync_start = 480 + 10, 2991 .vsync_end = 480 + 10 + 50, 2992 .vtotal = 480 + 0 + 10 + 50, 2993 }; 2994 2995 static const struct panel_desc nvd_9128 = { 2996 .modes = &nvd_9128_mode, 2997 .num_modes = 1, 2998 .bpc = 8, 2999 .size = { 3000 .width = 156, 3001 .height = 88, 3002 }, 3003 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3005 }; 3006 3007 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3008 .pixelclock = { 30000000, 30000000, 40000000 }, 3009 .hactive = { 800, 800, 800 }, 3010 .hfront_porch = { 40, 40, 40 }, 3011 .hback_porch = { 40, 40, 40 }, 3012 .hsync_len = { 1, 48, 48 }, 3013 .vactive = { 480, 480, 480 }, 3014 .vfront_porch = { 13, 13, 13 }, 3015 .vback_porch = { 29, 29, 29 }, 3016 .vsync_len = { 3, 3, 3 }, 3017 .flags = DISPLAY_FLAGS_DE_HIGH, 3018 }; 3019 3020 static const struct panel_desc okaya_rs800480t_7x0gp = { 3021 .timings = &okaya_rs800480t_7x0gp_timing, 3022 .num_timings = 1, 3023 .bpc = 6, 3024 .size = { 3025 .width = 154, 3026 .height = 87, 3027 }, 3028 .delay = { 3029 .prepare = 41, 3030 .enable = 50, 3031 .unprepare = 41, 3032 .disable = 50, 3033 }, 3034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3035 }; 3036 3037 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3038 .clock = 9000, 3039 .hdisplay = 480, 3040 .hsync_start = 480 + 5, 3041 .hsync_end = 480 + 5 + 30, 3042 .htotal = 480 + 5 + 30 + 10, 3043 .vdisplay = 272, 3044 .vsync_start = 272 + 8, 3045 .vsync_end = 272 + 8 + 5, 3046 .vtotal = 272 + 8 + 5 + 3, 3047 }; 3048 3049 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3050 .modes = &olimex_lcd_olinuxino_43ts_mode, 3051 .num_modes = 1, 3052 .size = { 3053 .width = 95, 3054 .height = 54, 3055 }, 3056 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3057 }; 3058 3059 /* 3060 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3061 * pixel clocks, but this is the timing that was being used in the Adafruit 3062 * installation instructions. 3063 */ 3064 static const struct drm_display_mode ontat_yx700wv03_mode = { 3065 .clock = 29500, 3066 .hdisplay = 800, 3067 .hsync_start = 824, 3068 .hsync_end = 896, 3069 .htotal = 992, 3070 .vdisplay = 480, 3071 .vsync_start = 483, 3072 .vsync_end = 493, 3073 .vtotal = 500, 3074 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3075 }; 3076 3077 /* 3078 * Specification at: 3079 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3080 */ 3081 static const struct panel_desc ontat_yx700wv03 = { 3082 .modes = &ontat_yx700wv03_mode, 3083 .num_modes = 1, 3084 .bpc = 8, 3085 .size = { 3086 .width = 154, 3087 .height = 83, 3088 }, 3089 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3090 }; 3091 3092 static const struct drm_display_mode ortustech_com37h3m_mode = { 3093 .clock = 22230, 3094 .hdisplay = 480, 3095 .hsync_start = 480 + 40, 3096 .hsync_end = 480 + 40 + 10, 3097 .htotal = 480 + 40 + 10 + 40, 3098 .vdisplay = 640, 3099 .vsync_start = 640 + 4, 3100 .vsync_end = 640 + 4 + 2, 3101 .vtotal = 640 + 4 + 2 + 4, 3102 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3103 }; 3104 3105 static const struct panel_desc ortustech_com37h3m = { 3106 .modes = &ortustech_com37h3m_mode, 3107 .num_modes = 1, 3108 .bpc = 8, 3109 .size = { 3110 .width = 56, /* 56.16mm */ 3111 .height = 75, /* 74.88mm */ 3112 }, 3113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3115 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3116 }; 3117 3118 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3119 .clock = 25000, 3120 .hdisplay = 480, 3121 .hsync_start = 480 + 10, 3122 .hsync_end = 480 + 10 + 10, 3123 .htotal = 480 + 10 + 10 + 15, 3124 .vdisplay = 800, 3125 .vsync_start = 800 + 3, 3126 .vsync_end = 800 + 3 + 3, 3127 .vtotal = 800 + 3 + 3 + 3, 3128 }; 3129 3130 static const struct panel_desc ortustech_com43h4m85ulc = { 3131 .modes = &ortustech_com43h4m85ulc_mode, 3132 .num_modes = 1, 3133 .bpc = 6, 3134 .size = { 3135 .width = 56, 3136 .height = 93, 3137 }, 3138 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3139 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3140 .connector_type = DRM_MODE_CONNECTOR_DPI, 3141 }; 3142 3143 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3144 .clock = 33000, 3145 .hdisplay = 800, 3146 .hsync_start = 800 + 210, 3147 .hsync_end = 800 + 210 + 30, 3148 .htotal = 800 + 210 + 30 + 16, 3149 .vdisplay = 480, 3150 .vsync_start = 480 + 22, 3151 .vsync_end = 480 + 22 + 13, 3152 .vtotal = 480 + 22 + 13 + 10, 3153 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3154 }; 3155 3156 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3157 .modes = &osddisplays_osd070t1718_19ts_mode, 3158 .num_modes = 1, 3159 .bpc = 8, 3160 .size = { 3161 .width = 152, 3162 .height = 91, 3163 }, 3164 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3165 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3166 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3167 .connector_type = DRM_MODE_CONNECTOR_DPI, 3168 }; 3169 3170 static const struct drm_display_mode pda_91_00156_a0_mode = { 3171 .clock = 33300, 3172 .hdisplay = 800, 3173 .hsync_start = 800 + 1, 3174 .hsync_end = 800 + 1 + 64, 3175 .htotal = 800 + 1 + 64 + 64, 3176 .vdisplay = 480, 3177 .vsync_start = 480 + 1, 3178 .vsync_end = 480 + 1 + 23, 3179 .vtotal = 480 + 1 + 23 + 22, 3180 }; 3181 3182 static const struct panel_desc pda_91_00156_a0 = { 3183 .modes = &pda_91_00156_a0_mode, 3184 .num_modes = 1, 3185 .size = { 3186 .width = 152, 3187 .height = 91, 3188 }, 3189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3190 }; 3191 3192 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3193 .clock = 24750, 3194 .hdisplay = 800, 3195 .hsync_start = 800 + 54, 3196 .hsync_end = 800 + 54 + 2, 3197 .htotal = 800 + 54 + 2 + 44, 3198 .vdisplay = 480, 3199 .vsync_start = 480 + 49, 3200 .vsync_end = 480 + 49 + 2, 3201 .vtotal = 480 + 49 + 2 + 22, 3202 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3203 }; 3204 3205 static const struct panel_desc powertip_ph800480t013_idf02 = { 3206 .modes = &powertip_ph800480t013_idf02_mode, 3207 .num_modes = 1, 3208 .size = { 3209 .width = 152, 3210 .height = 91, 3211 }, 3212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3213 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3214 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3216 .connector_type = DRM_MODE_CONNECTOR_DPI, 3217 }; 3218 3219 static const struct drm_display_mode qd43003c0_40_mode = { 3220 .clock = 9000, 3221 .hdisplay = 480, 3222 .hsync_start = 480 + 8, 3223 .hsync_end = 480 + 8 + 4, 3224 .htotal = 480 + 8 + 4 + 39, 3225 .vdisplay = 272, 3226 .vsync_start = 272 + 4, 3227 .vsync_end = 272 + 4 + 10, 3228 .vtotal = 272 + 4 + 10 + 2, 3229 }; 3230 3231 static const struct panel_desc qd43003c0_40 = { 3232 .modes = &qd43003c0_40_mode, 3233 .num_modes = 1, 3234 .bpc = 8, 3235 .size = { 3236 .width = 95, 3237 .height = 53, 3238 }, 3239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3240 }; 3241 3242 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3243 { /* 60 Hz */ 3244 .clock = 10800, 3245 .hdisplay = 480, 3246 .hsync_start = 480 + 77, 3247 .hsync_end = 480 + 77 + 41, 3248 .htotal = 480 + 77 + 41 + 2, 3249 .vdisplay = 272, 3250 .vsync_start = 272 + 16, 3251 .vsync_end = 272 + 16 + 10, 3252 .vtotal = 272 + 16 + 10 + 2, 3253 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3254 }, 3255 { /* 50 Hz */ 3256 .clock = 10800, 3257 .hdisplay = 480, 3258 .hsync_start = 480 + 17, 3259 .hsync_end = 480 + 17 + 41, 3260 .htotal = 480 + 17 + 41 + 2, 3261 .vdisplay = 272, 3262 .vsync_start = 272 + 116, 3263 .vsync_end = 272 + 116 + 10, 3264 .vtotal = 272 + 116 + 10 + 2, 3265 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3266 }, 3267 }; 3268 3269 static const struct panel_desc qishenglong_gopher2b_lcd = { 3270 .modes = qishenglong_gopher2b_lcd_modes, 3271 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3272 .bpc = 8, 3273 .size = { 3274 .width = 95, 3275 .height = 54, 3276 }, 3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3278 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3279 .connector_type = DRM_MODE_CONNECTOR_DPI, 3280 }; 3281 3282 static const struct display_timing rocktech_rk043fn48h_timing = { 3283 .pixelclock = { 6000000, 9000000, 12000000 }, 3284 .hactive = { 480, 480, 480 }, 3285 .hback_porch = { 8, 43, 43 }, 3286 .hfront_porch = { 2, 8, 8 }, 3287 .hsync_len = { 1, 1, 1 }, 3288 .vactive = { 272, 272, 272 }, 3289 .vback_porch = { 2, 12, 12 }, 3290 .vfront_porch = { 1, 4, 4 }, 3291 .vsync_len = { 1, 10, 10 }, 3292 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3293 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3294 }; 3295 3296 static const struct panel_desc rocktech_rk043fn48h = { 3297 .timings = &rocktech_rk043fn48h_timing, 3298 .num_timings = 1, 3299 .bpc = 8, 3300 .size = { 3301 .width = 95, 3302 .height = 54, 3303 }, 3304 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3305 .connector_type = DRM_MODE_CONNECTOR_DPI, 3306 }; 3307 3308 static const struct display_timing rocktech_rk070er9427_timing = { 3309 .pixelclock = { 26400000, 33300000, 46800000 }, 3310 .hactive = { 800, 800, 800 }, 3311 .hfront_porch = { 16, 210, 354 }, 3312 .hback_porch = { 46, 46, 46 }, 3313 .hsync_len = { 1, 1, 1 }, 3314 .vactive = { 480, 480, 480 }, 3315 .vfront_porch = { 7, 22, 147 }, 3316 .vback_porch = { 23, 23, 23 }, 3317 .vsync_len = { 1, 1, 1 }, 3318 .flags = DISPLAY_FLAGS_DE_HIGH, 3319 }; 3320 3321 static const struct panel_desc rocktech_rk070er9427 = { 3322 .timings = &rocktech_rk070er9427_timing, 3323 .num_timings = 1, 3324 .bpc = 6, 3325 .size = { 3326 .width = 154, 3327 .height = 86, 3328 }, 3329 .delay = { 3330 .prepare = 41, 3331 .enable = 50, 3332 .unprepare = 41, 3333 .disable = 50, 3334 }, 3335 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3336 }; 3337 3338 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3339 .clock = 71100, 3340 .hdisplay = 1280, 3341 .hsync_start = 1280 + 48, 3342 .hsync_end = 1280 + 48 + 32, 3343 .htotal = 1280 + 48 + 32 + 80, 3344 .vdisplay = 800, 3345 .vsync_start = 800 + 2, 3346 .vsync_end = 800 + 2 + 5, 3347 .vtotal = 800 + 2 + 5 + 16, 3348 }; 3349 3350 static const struct panel_desc rocktech_rk101ii01d_ct = { 3351 .modes = &rocktech_rk101ii01d_ct_mode, 3352 .bpc = 8, 3353 .num_modes = 1, 3354 .size = { 3355 .width = 217, 3356 .height = 136, 3357 }, 3358 .delay = { 3359 .prepare = 50, 3360 .disable = 50, 3361 }, 3362 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3363 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3364 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3365 }; 3366 3367 static const struct display_timing samsung_ltl101al01_timing = { 3368 .pixelclock = { 66663000, 66663000, 66663000 }, 3369 .hactive = { 1280, 1280, 1280 }, 3370 .hfront_porch = { 18, 18, 18 }, 3371 .hback_porch = { 36, 36, 36 }, 3372 .hsync_len = { 16, 16, 16 }, 3373 .vactive = { 800, 800, 800 }, 3374 .vfront_porch = { 4, 4, 4 }, 3375 .vback_porch = { 16, 16, 16 }, 3376 .vsync_len = { 3, 3, 3 }, 3377 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3378 }; 3379 3380 static const struct panel_desc samsung_ltl101al01 = { 3381 .timings = &samsung_ltl101al01_timing, 3382 .num_timings = 1, 3383 .bpc = 8, 3384 .size = { 3385 .width = 217, 3386 .height = 135, 3387 }, 3388 .delay = { 3389 .prepare = 40, 3390 .enable = 300, 3391 .disable = 200, 3392 .unprepare = 600, 3393 }, 3394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3396 }; 3397 3398 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3399 .clock = 54030, 3400 .hdisplay = 1024, 3401 .hsync_start = 1024 + 24, 3402 .hsync_end = 1024 + 24 + 136, 3403 .htotal = 1024 + 24 + 136 + 160, 3404 .vdisplay = 600, 3405 .vsync_start = 600 + 3, 3406 .vsync_end = 600 + 3 + 6, 3407 .vtotal = 600 + 3 + 6 + 61, 3408 }; 3409 3410 static const struct panel_desc samsung_ltn101nt05 = { 3411 .modes = &samsung_ltn101nt05_mode, 3412 .num_modes = 1, 3413 .bpc = 6, 3414 .size = { 3415 .width = 223, 3416 .height = 125, 3417 }, 3418 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3419 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3420 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3421 }; 3422 3423 static const struct display_timing satoz_sat050at40h12r2_timing = { 3424 .pixelclock = {33300000, 33300000, 50000000}, 3425 .hactive = {800, 800, 800}, 3426 .hfront_porch = {16, 210, 354}, 3427 .hback_porch = {46, 46, 46}, 3428 .hsync_len = {1, 1, 40}, 3429 .vactive = {480, 480, 480}, 3430 .vfront_porch = {7, 22, 147}, 3431 .vback_porch = {23, 23, 23}, 3432 .vsync_len = {1, 1, 20}, 3433 }; 3434 3435 static const struct panel_desc satoz_sat050at40h12r2 = { 3436 .timings = &satoz_sat050at40h12r2_timing, 3437 .num_timings = 1, 3438 .bpc = 8, 3439 .size = { 3440 .width = 108, 3441 .height = 65, 3442 }, 3443 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3444 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3445 }; 3446 3447 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3448 .clock = 33260, 3449 .hdisplay = 800, 3450 .hsync_start = 800 + 64, 3451 .hsync_end = 800 + 64 + 128, 3452 .htotal = 800 + 64 + 128 + 64, 3453 .vdisplay = 480, 3454 .vsync_start = 480 + 8, 3455 .vsync_end = 480 + 8 + 2, 3456 .vtotal = 480 + 8 + 2 + 35, 3457 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3458 }; 3459 3460 static const struct panel_desc sharp_lq070y3dg3b = { 3461 .modes = &sharp_lq070y3dg3b_mode, 3462 .num_modes = 1, 3463 .bpc = 8, 3464 .size = { 3465 .width = 152, /* 152.4mm */ 3466 .height = 91, /* 91.4mm */ 3467 }, 3468 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3470 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3471 }; 3472 3473 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3474 .clock = 5500, 3475 .hdisplay = 240, 3476 .hsync_start = 240 + 16, 3477 .hsync_end = 240 + 16 + 7, 3478 .htotal = 240 + 16 + 7 + 5, 3479 .vdisplay = 320, 3480 .vsync_start = 320 + 9, 3481 .vsync_end = 320 + 9 + 1, 3482 .vtotal = 320 + 9 + 1 + 7, 3483 }; 3484 3485 static const struct panel_desc sharp_lq035q7db03 = { 3486 .modes = &sharp_lq035q7db03_mode, 3487 .num_modes = 1, 3488 .bpc = 6, 3489 .size = { 3490 .width = 54, 3491 .height = 72, 3492 }, 3493 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3494 }; 3495 3496 static const struct display_timing sharp_lq101k1ly04_timing = { 3497 .pixelclock = { 60000000, 65000000, 80000000 }, 3498 .hactive = { 1280, 1280, 1280 }, 3499 .hfront_porch = { 20, 20, 20 }, 3500 .hback_porch = { 20, 20, 20 }, 3501 .hsync_len = { 10, 10, 10 }, 3502 .vactive = { 800, 800, 800 }, 3503 .vfront_porch = { 4, 4, 4 }, 3504 .vback_porch = { 4, 4, 4 }, 3505 .vsync_len = { 4, 4, 4 }, 3506 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3507 }; 3508 3509 static const struct panel_desc sharp_lq101k1ly04 = { 3510 .timings = &sharp_lq101k1ly04_timing, 3511 .num_timings = 1, 3512 .bpc = 8, 3513 .size = { 3514 .width = 217, 3515 .height = 136, 3516 }, 3517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3518 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3519 }; 3520 3521 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3522 { /* 50 Hz */ 3523 .clock = 3000, 3524 .hdisplay = 240, 3525 .hsync_start = 240 + 58, 3526 .hsync_end = 240 + 58 + 1, 3527 .htotal = 240 + 58 + 1 + 1, 3528 .vdisplay = 160, 3529 .vsync_start = 160 + 24, 3530 .vsync_end = 160 + 24 + 10, 3531 .vtotal = 160 + 24 + 10 + 6, 3532 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3533 }, 3534 { /* 60 Hz */ 3535 .clock = 3000, 3536 .hdisplay = 240, 3537 .hsync_start = 240 + 8, 3538 .hsync_end = 240 + 8 + 1, 3539 .htotal = 240 + 8 + 1 + 1, 3540 .vdisplay = 160, 3541 .vsync_start = 160 + 24, 3542 .vsync_end = 160 + 24 + 10, 3543 .vtotal = 160 + 24 + 10 + 6, 3544 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3545 }, 3546 }; 3547 3548 static const struct panel_desc sharp_ls020b1dd01d = { 3549 .modes = sharp_ls020b1dd01d_modes, 3550 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3551 .bpc = 6, 3552 .size = { 3553 .width = 42, 3554 .height = 28, 3555 }, 3556 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3557 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3558 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3559 | DRM_BUS_FLAG_SHARP_SIGNALS, 3560 }; 3561 3562 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3563 .clock = 33300, 3564 .hdisplay = 800, 3565 .hsync_start = 800 + 1, 3566 .hsync_end = 800 + 1 + 64, 3567 .htotal = 800 + 1 + 64 + 64, 3568 .vdisplay = 480, 3569 .vsync_start = 480 + 1, 3570 .vsync_end = 480 + 1 + 23, 3571 .vtotal = 480 + 1 + 23 + 22, 3572 }; 3573 3574 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3575 .modes = &shelly_sca07010_bfn_lnn_mode, 3576 .num_modes = 1, 3577 .size = { 3578 .width = 152, 3579 .height = 91, 3580 }, 3581 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3582 }; 3583 3584 static const struct drm_display_mode starry_kr070pe2t_mode = { 3585 .clock = 33000, 3586 .hdisplay = 800, 3587 .hsync_start = 800 + 209, 3588 .hsync_end = 800 + 209 + 1, 3589 .htotal = 800 + 209 + 1 + 45, 3590 .vdisplay = 480, 3591 .vsync_start = 480 + 22, 3592 .vsync_end = 480 + 22 + 1, 3593 .vtotal = 480 + 22 + 1 + 22, 3594 }; 3595 3596 static const struct panel_desc starry_kr070pe2t = { 3597 .modes = &starry_kr070pe2t_mode, 3598 .num_modes = 1, 3599 .bpc = 8, 3600 .size = { 3601 .width = 152, 3602 .height = 86, 3603 }, 3604 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3606 .connector_type = DRM_MODE_CONNECTOR_DPI, 3607 }; 3608 3609 static const struct display_timing startek_kd070wvfpa_mode = { 3610 .pixelclock = { 25200000, 27200000, 30500000 }, 3611 .hactive = { 800, 800, 800 }, 3612 .hfront_porch = { 19, 44, 115 }, 3613 .hback_porch = { 5, 16, 101 }, 3614 .hsync_len = { 1, 2, 100 }, 3615 .vactive = { 480, 480, 480 }, 3616 .vfront_porch = { 5, 43, 67 }, 3617 .vback_porch = { 5, 5, 67 }, 3618 .vsync_len = { 1, 2, 66 }, 3619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3620 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3621 DISPLAY_FLAGS_SYNC_POSEDGE, 3622 }; 3623 3624 static const struct panel_desc startek_kd070wvfpa = { 3625 .timings = &startek_kd070wvfpa_mode, 3626 .num_timings = 1, 3627 .bpc = 8, 3628 .size = { 3629 .width = 152, 3630 .height = 91, 3631 }, 3632 .delay = { 3633 .prepare = 20, 3634 .enable = 200, 3635 .disable = 200, 3636 }, 3637 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3638 .connector_type = DRM_MODE_CONNECTOR_DPI, 3639 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3640 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3641 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3642 }; 3643 3644 static const struct display_timing tsd_tst043015cmhx_timing = { 3645 .pixelclock = { 5000000, 9000000, 12000000 }, 3646 .hactive = { 480, 480, 480 }, 3647 .hfront_porch = { 4, 5, 65 }, 3648 .hback_porch = { 36, 40, 255 }, 3649 .hsync_len = { 1, 1, 1 }, 3650 .vactive = { 272, 272, 272 }, 3651 .vfront_porch = { 2, 8, 97 }, 3652 .vback_porch = { 3, 8, 31 }, 3653 .vsync_len = { 1, 1, 1 }, 3654 3655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3656 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3657 }; 3658 3659 static const struct panel_desc tsd_tst043015cmhx = { 3660 .timings = &tsd_tst043015cmhx_timing, 3661 .num_timings = 1, 3662 .bpc = 8, 3663 .size = { 3664 .width = 105, 3665 .height = 67, 3666 }, 3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3669 }; 3670 3671 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3672 .clock = 30000, 3673 .hdisplay = 800, 3674 .hsync_start = 800 + 39, 3675 .hsync_end = 800 + 39 + 47, 3676 .htotal = 800 + 39 + 47 + 39, 3677 .vdisplay = 480, 3678 .vsync_start = 480 + 13, 3679 .vsync_end = 480 + 13 + 2, 3680 .vtotal = 480 + 13 + 2 + 29, 3681 }; 3682 3683 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3684 .modes = &tfc_s9700rtwv43tr_01b_mode, 3685 .num_modes = 1, 3686 .bpc = 8, 3687 .size = { 3688 .width = 155, 3689 .height = 90, 3690 }, 3691 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3692 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3693 }; 3694 3695 static const struct display_timing tianma_tm070jdhg30_timing = { 3696 .pixelclock = { 62600000, 68200000, 78100000 }, 3697 .hactive = { 1280, 1280, 1280 }, 3698 .hfront_porch = { 15, 64, 159 }, 3699 .hback_porch = { 5, 5, 5 }, 3700 .hsync_len = { 1, 1, 256 }, 3701 .vactive = { 800, 800, 800 }, 3702 .vfront_porch = { 3, 40, 99 }, 3703 .vback_porch = { 2, 2, 2 }, 3704 .vsync_len = { 1, 1, 128 }, 3705 .flags = DISPLAY_FLAGS_DE_HIGH, 3706 }; 3707 3708 static const struct panel_desc tianma_tm070jdhg30 = { 3709 .timings = &tianma_tm070jdhg30_timing, 3710 .num_timings = 1, 3711 .bpc = 8, 3712 .size = { 3713 .width = 151, 3714 .height = 95, 3715 }, 3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3717 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3718 }; 3719 3720 static const struct panel_desc tianma_tm070jvhg33 = { 3721 .timings = &tianma_tm070jdhg30_timing, 3722 .num_timings = 1, 3723 .bpc = 8, 3724 .size = { 3725 .width = 150, 3726 .height = 94, 3727 }, 3728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3729 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3730 }; 3731 3732 static const struct display_timing tianma_tm070rvhg71_timing = { 3733 .pixelclock = { 27700000, 29200000, 39600000 }, 3734 .hactive = { 800, 800, 800 }, 3735 .hfront_porch = { 12, 40, 212 }, 3736 .hback_porch = { 88, 88, 88 }, 3737 .hsync_len = { 1, 1, 40 }, 3738 .vactive = { 480, 480, 480 }, 3739 .vfront_porch = { 1, 13, 88 }, 3740 .vback_porch = { 32, 32, 32 }, 3741 .vsync_len = { 1, 1, 3 }, 3742 .flags = DISPLAY_FLAGS_DE_HIGH, 3743 }; 3744 3745 static const struct panel_desc tianma_tm070rvhg71 = { 3746 .timings = &tianma_tm070rvhg71_timing, 3747 .num_timings = 1, 3748 .bpc = 8, 3749 .size = { 3750 .width = 154, 3751 .height = 86, 3752 }, 3753 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3754 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3755 }; 3756 3757 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3758 { 3759 .clock = 10000, 3760 .hdisplay = 320, 3761 .hsync_start = 320 + 50, 3762 .hsync_end = 320 + 50 + 6, 3763 .htotal = 320 + 50 + 6 + 38, 3764 .vdisplay = 240, 3765 .vsync_start = 240 + 3, 3766 .vsync_end = 240 + 3 + 1, 3767 .vtotal = 240 + 3 + 1 + 17, 3768 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3769 }, 3770 }; 3771 3772 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3773 .modes = ti_nspire_cx_lcd_mode, 3774 .num_modes = 1, 3775 .bpc = 8, 3776 .size = { 3777 .width = 65, 3778 .height = 49, 3779 }, 3780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3781 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3782 }; 3783 3784 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3785 { 3786 .clock = 10000, 3787 .hdisplay = 320, 3788 .hsync_start = 320 + 6, 3789 .hsync_end = 320 + 6 + 6, 3790 .htotal = 320 + 6 + 6 + 6, 3791 .vdisplay = 240, 3792 .vsync_start = 240 + 0, 3793 .vsync_end = 240 + 0 + 1, 3794 .vtotal = 240 + 0 + 1 + 0, 3795 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3796 }, 3797 }; 3798 3799 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3800 .modes = ti_nspire_classic_lcd_mode, 3801 .num_modes = 1, 3802 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3803 .bpc = 8, 3804 .size = { 3805 .width = 71, 3806 .height = 53, 3807 }, 3808 /* This is the grayscale bus format */ 3809 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3810 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3811 }; 3812 3813 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3814 .clock = 79500, 3815 .hdisplay = 1280, 3816 .hsync_start = 1280 + 192, 3817 .hsync_end = 1280 + 192 + 128, 3818 .htotal = 1280 + 192 + 128 + 64, 3819 .vdisplay = 768, 3820 .vsync_start = 768 + 20, 3821 .vsync_end = 768 + 20 + 7, 3822 .vtotal = 768 + 20 + 7 + 3, 3823 }; 3824 3825 static const struct panel_desc toshiba_lt089ac29000 = { 3826 .modes = &toshiba_lt089ac29000_mode, 3827 .num_modes = 1, 3828 .size = { 3829 .width = 194, 3830 .height = 116, 3831 }, 3832 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3833 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3834 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3835 }; 3836 3837 static const struct drm_display_mode tpk_f07a_0102_mode = { 3838 .clock = 33260, 3839 .hdisplay = 800, 3840 .hsync_start = 800 + 40, 3841 .hsync_end = 800 + 40 + 128, 3842 .htotal = 800 + 40 + 128 + 88, 3843 .vdisplay = 480, 3844 .vsync_start = 480 + 10, 3845 .vsync_end = 480 + 10 + 2, 3846 .vtotal = 480 + 10 + 2 + 33, 3847 }; 3848 3849 static const struct panel_desc tpk_f07a_0102 = { 3850 .modes = &tpk_f07a_0102_mode, 3851 .num_modes = 1, 3852 .size = { 3853 .width = 152, 3854 .height = 91, 3855 }, 3856 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3857 }; 3858 3859 static const struct drm_display_mode tpk_f10a_0102_mode = { 3860 .clock = 45000, 3861 .hdisplay = 1024, 3862 .hsync_start = 1024 + 176, 3863 .hsync_end = 1024 + 176 + 5, 3864 .htotal = 1024 + 176 + 5 + 88, 3865 .vdisplay = 600, 3866 .vsync_start = 600 + 20, 3867 .vsync_end = 600 + 20 + 5, 3868 .vtotal = 600 + 20 + 5 + 25, 3869 }; 3870 3871 static const struct panel_desc tpk_f10a_0102 = { 3872 .modes = &tpk_f10a_0102_mode, 3873 .num_modes = 1, 3874 .size = { 3875 .width = 223, 3876 .height = 125, 3877 }, 3878 }; 3879 3880 static const struct display_timing urt_umsh_8596md_timing = { 3881 .pixelclock = { 33260000, 33260000, 33260000 }, 3882 .hactive = { 800, 800, 800 }, 3883 .hfront_porch = { 41, 41, 41 }, 3884 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3885 .hsync_len = { 71, 128, 128 }, 3886 .vactive = { 480, 480, 480 }, 3887 .vfront_porch = { 10, 10, 10 }, 3888 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3889 .vsync_len = { 2, 2, 2 }, 3890 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3891 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3892 }; 3893 3894 static const struct panel_desc urt_umsh_8596md_lvds = { 3895 .timings = &urt_umsh_8596md_timing, 3896 .num_timings = 1, 3897 .bpc = 6, 3898 .size = { 3899 .width = 152, 3900 .height = 91, 3901 }, 3902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3904 }; 3905 3906 static const struct panel_desc urt_umsh_8596md_parallel = { 3907 .timings = &urt_umsh_8596md_timing, 3908 .num_timings = 1, 3909 .bpc = 6, 3910 .size = { 3911 .width = 152, 3912 .height = 91, 3913 }, 3914 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3915 }; 3916 3917 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3918 .clock = 60000, 3919 .hdisplay = 1024, 3920 .hsync_start = 1024 + 160, 3921 .hsync_end = 1024 + 160 + 100, 3922 .htotal = 1024 + 160 + 100 + 60, 3923 .vdisplay = 600, 3924 .vsync_start = 600 + 12, 3925 .vsync_end = 600 + 12 + 10, 3926 .vtotal = 600 + 12 + 10 + 13, 3927 }; 3928 3929 static const struct panel_desc vivax_tpc9150_panel = { 3930 .modes = &vivax_tpc9150_panel_mode, 3931 .num_modes = 1, 3932 .bpc = 6, 3933 .size = { 3934 .width = 200, 3935 .height = 115, 3936 }, 3937 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3938 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3939 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3940 }; 3941 3942 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3943 .clock = 33333, 3944 .hdisplay = 800, 3945 .hsync_start = 800 + 210, 3946 .hsync_end = 800 + 210 + 20, 3947 .htotal = 800 + 210 + 20 + 46, 3948 .vdisplay = 480, 3949 .vsync_start = 480 + 22, 3950 .vsync_end = 480 + 22 + 10, 3951 .vtotal = 480 + 22 + 10 + 23, 3952 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3953 }; 3954 3955 static const struct panel_desc vl050_8048nt_c01 = { 3956 .modes = &vl050_8048nt_c01_mode, 3957 .num_modes = 1, 3958 .bpc = 8, 3959 .size = { 3960 .width = 120, 3961 .height = 76, 3962 }, 3963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3964 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3965 }; 3966 3967 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3968 .clock = 6410, 3969 .hdisplay = 320, 3970 .hsync_start = 320 + 20, 3971 .hsync_end = 320 + 20 + 30, 3972 .htotal = 320 + 20 + 30 + 38, 3973 .vdisplay = 240, 3974 .vsync_start = 240 + 4, 3975 .vsync_end = 240 + 4 + 3, 3976 .vtotal = 240 + 4 + 3 + 15, 3977 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3978 }; 3979 3980 static const struct panel_desc winstar_wf35ltiacd = { 3981 .modes = &winstar_wf35ltiacd_mode, 3982 .num_modes = 1, 3983 .bpc = 8, 3984 .size = { 3985 .width = 70, 3986 .height = 53, 3987 }, 3988 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3989 }; 3990 3991 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3992 .clock = 51200, 3993 .hdisplay = 1024, 3994 .hsync_start = 1024 + 100, 3995 .hsync_end = 1024 + 100 + 100, 3996 .htotal = 1024 + 100 + 100 + 120, 3997 .vdisplay = 600, 3998 .vsync_start = 600 + 10, 3999 .vsync_end = 600 + 10 + 10, 4000 .vtotal = 600 + 10 + 10 + 15, 4001 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4002 }; 4003 4004 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4005 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4006 .num_modes = 1, 4007 .bpc = 8, 4008 .size = { 4009 .width = 154, 4010 .height = 90, 4011 }, 4012 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4013 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4014 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4015 }; 4016 4017 static const struct drm_display_mode arm_rtsm_mode[] = { 4018 { 4019 .clock = 65000, 4020 .hdisplay = 1024, 4021 .hsync_start = 1024 + 24, 4022 .hsync_end = 1024 + 24 + 136, 4023 .htotal = 1024 + 24 + 136 + 160, 4024 .vdisplay = 768, 4025 .vsync_start = 768 + 3, 4026 .vsync_end = 768 + 3 + 6, 4027 .vtotal = 768 + 3 + 6 + 29, 4028 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4029 }, 4030 }; 4031 4032 static const struct panel_desc arm_rtsm = { 4033 .modes = arm_rtsm_mode, 4034 .num_modes = 1, 4035 .bpc = 8, 4036 .size = { 4037 .width = 400, 4038 .height = 300, 4039 }, 4040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4041 }; 4042 4043 static const struct of_device_id platform_of_match[] = { 4044 { 4045 .compatible = "ampire,am-1280800n3tzqw-t00h", 4046 .data = &ire_am_1280800n3tzqw_t00h, 4047 }, { 4048 .compatible = "ampire,am-480272h3tmqw-t01h", 4049 .data = &ire_am_480272h3tmqw_t01h, 4050 }, { 4051 .compatible = "ampire,am-800480l1tmqw-t00h", 4052 .data = &ire_am_800480l1tmqw_t00h, 4053 }, { 4054 .compatible = "ampire,am800480r3tmqwa1h", 4055 .data = &ire_am800480r3tmqwa1h, 4056 }, { 4057 .compatible = "ampire,am800600p5tmqw-tb8h", 4058 .data = &ire_am800600p5tmqwtb8h, 4059 }, { 4060 .compatible = "arm,rtsm-display", 4061 .data = &arm_rtsm, 4062 }, { 4063 .compatible = "armadeus,st0700-adapt", 4064 .data = &armadeus_st0700_adapt, 4065 }, { 4066 .compatible = "auo,b101aw03", 4067 .data = &auo_b101aw03, 4068 }, { 4069 .compatible = "auo,b101xtn01", 4070 .data = &auo_b101xtn01, 4071 }, { 4072 .compatible = "auo,g070vvn01", 4073 .data = &auo_g070vvn01, 4074 }, { 4075 .compatible = "auo,g101evn010", 4076 .data = &auo_g101evn010, 4077 }, { 4078 .compatible = "auo,g104sn02", 4079 .data = &auo_g104sn02, 4080 }, { 4081 .compatible = "auo,g121ean01", 4082 .data = &auo_g121ean01, 4083 }, { 4084 .compatible = "auo,g133han01", 4085 .data = &auo_g133han01, 4086 }, { 4087 .compatible = "auo,g156xtn01", 4088 .data = &auo_g156xtn01, 4089 }, { 4090 .compatible = "auo,g185han01", 4091 .data = &auo_g185han01, 4092 }, { 4093 .compatible = "auo,g190ean01", 4094 .data = &auo_g190ean01, 4095 }, { 4096 .compatible = "auo,p320hvn03", 4097 .data = &auo_p320hvn03, 4098 }, { 4099 .compatible = "auo,t215hvn01", 4100 .data = &auo_t215hvn01, 4101 }, { 4102 .compatible = "avic,tm070ddh03", 4103 .data = &avic_tm070ddh03, 4104 }, { 4105 .compatible = "bananapi,s070wv20-ct16", 4106 .data = &bananapi_s070wv20_ct16, 4107 }, { 4108 .compatible = "boe,ev121wxm-n10-1850", 4109 .data = &boe_ev121wxm_n10_1850, 4110 }, { 4111 .compatible = "boe,hv070wsa-100", 4112 .data = &boe_hv070wsa 4113 }, { 4114 .compatible = "cdtech,s043wq26h-ct7", 4115 .data = &cdtech_s043wq26h_ct7, 4116 }, { 4117 .compatible = "cdtech,s070pws19hp-fc21", 4118 .data = &cdtech_s070pws19hp_fc21, 4119 }, { 4120 .compatible = "cdtech,s070swv29hg-dc44", 4121 .data = &cdtech_s070swv29hg_dc44, 4122 }, { 4123 .compatible = "cdtech,s070wv95-ct16", 4124 .data = &cdtech_s070wv95_ct16, 4125 }, { 4126 .compatible = "chefree,ch101olhlwh-002", 4127 .data = &chefree_ch101olhlwh_002, 4128 }, { 4129 .compatible = "chunghwa,claa070wp03xg", 4130 .data = &chunghwa_claa070wp03xg, 4131 }, { 4132 .compatible = "chunghwa,claa101wa01a", 4133 .data = &chunghwa_claa101wa01a 4134 }, { 4135 .compatible = "chunghwa,claa101wb01", 4136 .data = &chunghwa_claa101wb01 4137 }, { 4138 .compatible = "dataimage,fg040346dsswbg04", 4139 .data = &dataimage_fg040346dsswbg04, 4140 }, { 4141 .compatible = "dataimage,fg1001l0dsswmg01", 4142 .data = &dataimage_fg1001l0dsswmg01, 4143 }, { 4144 .compatible = "dataimage,scf0700c48ggu18", 4145 .data = &dataimage_scf0700c48ggu18, 4146 }, { 4147 .compatible = "dlc,dlc0700yzg-1", 4148 .data = &dlc_dlc0700yzg_1, 4149 }, { 4150 .compatible = "dlc,dlc1010gig", 4151 .data = &dlc_dlc1010gig, 4152 }, { 4153 .compatible = "edt,et035012dm6", 4154 .data = &edt_et035012dm6, 4155 }, { 4156 .compatible = "edt,etm0350g0dh6", 4157 .data = &edt_etm0350g0dh6, 4158 }, { 4159 .compatible = "edt,etm043080dh6gp", 4160 .data = &edt_etm043080dh6gp, 4161 }, { 4162 .compatible = "edt,etm0430g0dh6", 4163 .data = &edt_etm0430g0dh6, 4164 }, { 4165 .compatible = "edt,et057090dhu", 4166 .data = &edt_et057090dhu, 4167 }, { 4168 .compatible = "edt,et070080dh6", 4169 .data = &edt_etm0700g0dh6, 4170 }, { 4171 .compatible = "edt,etm0700g0dh6", 4172 .data = &edt_etm0700g0dh6, 4173 }, { 4174 .compatible = "edt,etm0700g0bdh6", 4175 .data = &edt_etm0700g0bdh6, 4176 }, { 4177 .compatible = "edt,etm0700g0edh6", 4178 .data = &edt_etm0700g0bdh6, 4179 }, { 4180 .compatible = "edt,etml0700y5dha", 4181 .data = &edt_etml0700y5dha, 4182 }, { 4183 .compatible = "edt,etmv570g2dhu", 4184 .data = &edt_etmv570g2dhu, 4185 }, { 4186 .compatible = "eink,vb3300-kca", 4187 .data = &eink_vb3300_kca, 4188 }, { 4189 .compatible = "evervision,vgg804821", 4190 .data = &evervision_vgg804821, 4191 }, { 4192 .compatible = "foxlink,fl500wvr00-a0t", 4193 .data = &foxlink_fl500wvr00_a0t, 4194 }, { 4195 .compatible = "frida,frd350h54004", 4196 .data = &frida_frd350h54004, 4197 }, { 4198 .compatible = "friendlyarm,hd702e", 4199 .data = &friendlyarm_hd702e, 4200 }, { 4201 .compatible = "giantplus,gpg482739qs5", 4202 .data = &giantplus_gpg482739qs5 4203 }, { 4204 .compatible = "giantplus,gpm940b0", 4205 .data = &giantplus_gpm940b0, 4206 }, { 4207 .compatible = "hannstar,hsd070pww1", 4208 .data = &hannstar_hsd070pww1, 4209 }, { 4210 .compatible = "hannstar,hsd100pxn1", 4211 .data = &hannstar_hsd100pxn1, 4212 }, { 4213 .compatible = "hannstar,hsd101pww2", 4214 .data = &hannstar_hsd101pww2, 4215 }, { 4216 .compatible = "hit,tx23d38vm0caa", 4217 .data = &hitachi_tx23d38vm0caa 4218 }, { 4219 .compatible = "innolux,at043tn24", 4220 .data = &innolux_at043tn24, 4221 }, { 4222 .compatible = "innolux,at070tn92", 4223 .data = &innolux_at070tn92, 4224 }, { 4225 .compatible = "innolux,g070ace-l01", 4226 .data = &innolux_g070ace_l01, 4227 }, { 4228 .compatible = "innolux,g070y2-l01", 4229 .data = &innolux_g070y2_l01, 4230 }, { 4231 .compatible = "innolux,g070y2-t02", 4232 .data = &innolux_g070y2_t02, 4233 }, { 4234 .compatible = "innolux,g101ice-l01", 4235 .data = &innolux_g101ice_l01 4236 }, { 4237 .compatible = "innolux,g121i1-l01", 4238 .data = &innolux_g121i1_l01 4239 }, { 4240 .compatible = "innolux,g121x1-l03", 4241 .data = &innolux_g121x1_l03, 4242 }, { 4243 .compatible = "innolux,n156bge-l21", 4244 .data = &innolux_n156bge_l21, 4245 }, { 4246 .compatible = "innolux,zj070na-01p", 4247 .data = &innolux_zj070na_01p, 4248 }, { 4249 .compatible = "koe,tx14d24vm1bpa", 4250 .data = &koe_tx14d24vm1bpa, 4251 }, { 4252 .compatible = "koe,tx26d202vm0bwa", 4253 .data = &koe_tx26d202vm0bwa, 4254 }, { 4255 .compatible = "koe,tx31d200vm0baa", 4256 .data = &koe_tx31d200vm0baa, 4257 }, { 4258 .compatible = "kyo,tcg121xglp", 4259 .data = &kyo_tcg121xglp, 4260 }, { 4261 .compatible = "lemaker,bl035-rgb-002", 4262 .data = &lemaker_bl035_rgb_002, 4263 }, { 4264 .compatible = "lg,lb070wv8", 4265 .data = &lg_lb070wv8, 4266 }, { 4267 .compatible = "logicpd,type28", 4268 .data = &logicpd_type_28, 4269 }, { 4270 .compatible = "logictechno,lt161010-2nhc", 4271 .data = &logictechno_lt161010_2nh, 4272 }, { 4273 .compatible = "logictechno,lt161010-2nhr", 4274 .data = &logictechno_lt161010_2nh, 4275 }, { 4276 .compatible = "logictechno,lt170410-2whc", 4277 .data = &logictechno_lt170410_2whc, 4278 }, { 4279 .compatible = "logictechno,lttd800480070-l2rt", 4280 .data = &logictechno_lttd800480070_l2rt, 4281 }, { 4282 .compatible = "logictechno,lttd800480070-l6wh-rt", 4283 .data = &logictechno_lttd800480070_l6wh_rt, 4284 }, { 4285 .compatible = "mitsubishi,aa070mc01-ca1", 4286 .data = &mitsubishi_aa070mc01, 4287 }, { 4288 .compatible = "multi-inno,mi0700s4t-6", 4289 .data = &multi_inno_mi0700s4t_6, 4290 }, { 4291 .compatible = "multi-inno,mi0800ft-9", 4292 .data = &multi_inno_mi0800ft_9, 4293 }, { 4294 .compatible = "multi-inno,mi1010ait-1cp", 4295 .data = &multi_inno_mi1010ait_1cp, 4296 }, { 4297 .compatible = "nec,nl12880bc20-05", 4298 .data = &nec_nl12880bc20_05, 4299 }, { 4300 .compatible = "nec,nl4827hc19-05b", 4301 .data = &nec_nl4827hc19_05b, 4302 }, { 4303 .compatible = "netron-dy,e231732", 4304 .data = &netron_dy_e231732, 4305 }, { 4306 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4307 .data = &newhaven_nhd_43_480272ef_atxl, 4308 }, { 4309 .compatible = "nlt,nl192108ac18-02d", 4310 .data = &nlt_nl192108ac18_02d, 4311 }, { 4312 .compatible = "nvd,9128", 4313 .data = &nvd_9128, 4314 }, { 4315 .compatible = "okaya,rs800480t-7x0gp", 4316 .data = &okaya_rs800480t_7x0gp, 4317 }, { 4318 .compatible = "olimex,lcd-olinuxino-43-ts", 4319 .data = &olimex_lcd_olinuxino_43ts, 4320 }, { 4321 .compatible = "ontat,yx700wv03", 4322 .data = &ontat_yx700wv03, 4323 }, { 4324 .compatible = "ortustech,com37h3m05dtc", 4325 .data = &ortustech_com37h3m, 4326 }, { 4327 .compatible = "ortustech,com37h3m99dtc", 4328 .data = &ortustech_com37h3m, 4329 }, { 4330 .compatible = "ortustech,com43h4m85ulc", 4331 .data = &ortustech_com43h4m85ulc, 4332 }, { 4333 .compatible = "osddisplays,osd070t1718-19ts", 4334 .data = &osddisplays_osd070t1718_19ts, 4335 }, { 4336 .compatible = "pda,91-00156-a0", 4337 .data = &pda_91_00156_a0, 4338 }, { 4339 .compatible = "powertip,ph800480t013-idf02", 4340 .data = &powertip_ph800480t013_idf02, 4341 }, { 4342 .compatible = "qiaodian,qd43003c0-40", 4343 .data = &qd43003c0_40, 4344 }, { 4345 .compatible = "qishenglong,gopher2b-lcd", 4346 .data = &qishenglong_gopher2b_lcd, 4347 }, { 4348 .compatible = "rocktech,rk043fn48h", 4349 .data = &rocktech_rk043fn48h, 4350 }, { 4351 .compatible = "rocktech,rk070er9427", 4352 .data = &rocktech_rk070er9427, 4353 }, { 4354 .compatible = "rocktech,rk101ii01d-ct", 4355 .data = &rocktech_rk101ii01d_ct, 4356 }, { 4357 .compatible = "samsung,ltl101al01", 4358 .data = &samsung_ltl101al01, 4359 }, { 4360 .compatible = "samsung,ltn101nt05", 4361 .data = &samsung_ltn101nt05, 4362 }, { 4363 .compatible = "satoz,sat050at40h12r2", 4364 .data = &satoz_sat050at40h12r2, 4365 }, { 4366 .compatible = "sharp,lq035q7db03", 4367 .data = &sharp_lq035q7db03, 4368 }, { 4369 .compatible = "sharp,lq070y3dg3b", 4370 .data = &sharp_lq070y3dg3b, 4371 }, { 4372 .compatible = "sharp,lq101k1ly04", 4373 .data = &sharp_lq101k1ly04, 4374 }, { 4375 .compatible = "sharp,ls020b1dd01d", 4376 .data = &sharp_ls020b1dd01d, 4377 }, { 4378 .compatible = "shelly,sca07010-bfn-lnn", 4379 .data = &shelly_sca07010_bfn_lnn, 4380 }, { 4381 .compatible = "starry,kr070pe2t", 4382 .data = &starry_kr070pe2t, 4383 }, { 4384 .compatible = "startek,kd070wvfpa", 4385 .data = &startek_kd070wvfpa, 4386 }, { 4387 .compatible = "team-source-display,tst043015cmhx", 4388 .data = &tsd_tst043015cmhx, 4389 }, { 4390 .compatible = "tfc,s9700rtwv43tr-01b", 4391 .data = &tfc_s9700rtwv43tr_01b, 4392 }, { 4393 .compatible = "tianma,tm070jdhg30", 4394 .data = &tianma_tm070jdhg30, 4395 }, { 4396 .compatible = "tianma,tm070jvhg33", 4397 .data = &tianma_tm070jvhg33, 4398 }, { 4399 .compatible = "tianma,tm070rvhg71", 4400 .data = &tianma_tm070rvhg71, 4401 }, { 4402 .compatible = "ti,nspire-cx-lcd-panel", 4403 .data = &ti_nspire_cx_lcd_panel, 4404 }, { 4405 .compatible = "ti,nspire-classic-lcd-panel", 4406 .data = &ti_nspire_classic_lcd_panel, 4407 }, { 4408 .compatible = "toshiba,lt089ac29000", 4409 .data = &toshiba_lt089ac29000, 4410 }, { 4411 .compatible = "tpk,f07a-0102", 4412 .data = &tpk_f07a_0102, 4413 }, { 4414 .compatible = "tpk,f10a-0102", 4415 .data = &tpk_f10a_0102, 4416 }, { 4417 .compatible = "urt,umsh-8596md-t", 4418 .data = &urt_umsh_8596md_parallel, 4419 }, { 4420 .compatible = "urt,umsh-8596md-1t", 4421 .data = &urt_umsh_8596md_parallel, 4422 }, { 4423 .compatible = "urt,umsh-8596md-7t", 4424 .data = &urt_umsh_8596md_parallel, 4425 }, { 4426 .compatible = "urt,umsh-8596md-11t", 4427 .data = &urt_umsh_8596md_lvds, 4428 }, { 4429 .compatible = "urt,umsh-8596md-19t", 4430 .data = &urt_umsh_8596md_lvds, 4431 }, { 4432 .compatible = "urt,umsh-8596md-20t", 4433 .data = &urt_umsh_8596md_parallel, 4434 }, { 4435 .compatible = "vivax,tpc9150-panel", 4436 .data = &vivax_tpc9150_panel, 4437 }, { 4438 .compatible = "vxt,vl050-8048nt-c01", 4439 .data = &vl050_8048nt_c01, 4440 }, { 4441 .compatible = "winstar,wf35ltiacd", 4442 .data = &winstar_wf35ltiacd, 4443 }, { 4444 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4445 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4446 }, { 4447 /* Must be the last entry */ 4448 .compatible = "panel-dpi", 4449 .data = &panel_dpi, 4450 }, { 4451 /* sentinel */ 4452 } 4453 }; 4454 MODULE_DEVICE_TABLE(of, platform_of_match); 4455 4456 static int panel_simple_platform_probe(struct platform_device *pdev) 4457 { 4458 const struct of_device_id *id; 4459 4460 id = of_match_node(platform_of_match, pdev->dev.of_node); 4461 if (!id) 4462 return -ENODEV; 4463 4464 return panel_simple_probe(&pdev->dev, id->data); 4465 } 4466 4467 static void panel_simple_platform_remove(struct platform_device *pdev) 4468 { 4469 panel_simple_remove(&pdev->dev); 4470 } 4471 4472 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4473 { 4474 panel_simple_shutdown(&pdev->dev); 4475 } 4476 4477 static const struct dev_pm_ops panel_simple_pm_ops = { 4478 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4479 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4480 pm_runtime_force_resume) 4481 }; 4482 4483 static struct platform_driver panel_simple_platform_driver = { 4484 .driver = { 4485 .name = "panel-simple", 4486 .of_match_table = platform_of_match, 4487 .pm = &panel_simple_pm_ops, 4488 }, 4489 .probe = panel_simple_platform_probe, 4490 .remove_new = panel_simple_platform_remove, 4491 .shutdown = panel_simple_platform_shutdown, 4492 }; 4493 4494 struct panel_desc_dsi { 4495 struct panel_desc desc; 4496 4497 unsigned long flags; 4498 enum mipi_dsi_pixel_format format; 4499 unsigned int lanes; 4500 }; 4501 4502 static const struct drm_display_mode auo_b080uan01_mode = { 4503 .clock = 154500, 4504 .hdisplay = 1200, 4505 .hsync_start = 1200 + 62, 4506 .hsync_end = 1200 + 62 + 4, 4507 .htotal = 1200 + 62 + 4 + 62, 4508 .vdisplay = 1920, 4509 .vsync_start = 1920 + 9, 4510 .vsync_end = 1920 + 9 + 2, 4511 .vtotal = 1920 + 9 + 2 + 8, 4512 }; 4513 4514 static const struct panel_desc_dsi auo_b080uan01 = { 4515 .desc = { 4516 .modes = &auo_b080uan01_mode, 4517 .num_modes = 1, 4518 .bpc = 8, 4519 .size = { 4520 .width = 108, 4521 .height = 272, 4522 }, 4523 .connector_type = DRM_MODE_CONNECTOR_DSI, 4524 }, 4525 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4526 .format = MIPI_DSI_FMT_RGB888, 4527 .lanes = 4, 4528 }; 4529 4530 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4531 .clock = 160000, 4532 .hdisplay = 1200, 4533 .hsync_start = 1200 + 120, 4534 .hsync_end = 1200 + 120 + 20, 4535 .htotal = 1200 + 120 + 20 + 21, 4536 .vdisplay = 1920, 4537 .vsync_start = 1920 + 21, 4538 .vsync_end = 1920 + 21 + 3, 4539 .vtotal = 1920 + 21 + 3 + 18, 4540 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4541 }; 4542 4543 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4544 .desc = { 4545 .modes = &boe_tv080wum_nl0_mode, 4546 .num_modes = 1, 4547 .size = { 4548 .width = 107, 4549 .height = 172, 4550 }, 4551 .connector_type = DRM_MODE_CONNECTOR_DSI, 4552 }, 4553 .flags = MIPI_DSI_MODE_VIDEO | 4554 MIPI_DSI_MODE_VIDEO_BURST | 4555 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4556 .format = MIPI_DSI_FMT_RGB888, 4557 .lanes = 4, 4558 }; 4559 4560 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4561 .clock = 71000, 4562 .hdisplay = 800, 4563 .hsync_start = 800 + 32, 4564 .hsync_end = 800 + 32 + 1, 4565 .htotal = 800 + 32 + 1 + 57, 4566 .vdisplay = 1280, 4567 .vsync_start = 1280 + 28, 4568 .vsync_end = 1280 + 28 + 1, 4569 .vtotal = 1280 + 28 + 1 + 14, 4570 }; 4571 4572 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4573 .desc = { 4574 .modes = &lg_ld070wx3_sl01_mode, 4575 .num_modes = 1, 4576 .bpc = 8, 4577 .size = { 4578 .width = 94, 4579 .height = 151, 4580 }, 4581 .connector_type = DRM_MODE_CONNECTOR_DSI, 4582 }, 4583 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4584 .format = MIPI_DSI_FMT_RGB888, 4585 .lanes = 4, 4586 }; 4587 4588 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4589 .clock = 67000, 4590 .hdisplay = 720, 4591 .hsync_start = 720 + 12, 4592 .hsync_end = 720 + 12 + 4, 4593 .htotal = 720 + 12 + 4 + 112, 4594 .vdisplay = 1280, 4595 .vsync_start = 1280 + 8, 4596 .vsync_end = 1280 + 8 + 4, 4597 .vtotal = 1280 + 8 + 4 + 12, 4598 }; 4599 4600 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4601 .desc = { 4602 .modes = &lg_lh500wx1_sd03_mode, 4603 .num_modes = 1, 4604 .bpc = 8, 4605 .size = { 4606 .width = 62, 4607 .height = 110, 4608 }, 4609 .connector_type = DRM_MODE_CONNECTOR_DSI, 4610 }, 4611 .flags = MIPI_DSI_MODE_VIDEO, 4612 .format = MIPI_DSI_FMT_RGB888, 4613 .lanes = 4, 4614 }; 4615 4616 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4617 .clock = 157200, 4618 .hdisplay = 1920, 4619 .hsync_start = 1920 + 154, 4620 .hsync_end = 1920 + 154 + 16, 4621 .htotal = 1920 + 154 + 16 + 32, 4622 .vdisplay = 1200, 4623 .vsync_start = 1200 + 17, 4624 .vsync_end = 1200 + 17 + 2, 4625 .vtotal = 1200 + 17 + 2 + 16, 4626 }; 4627 4628 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4629 .desc = { 4630 .modes = &panasonic_vvx10f004b00_mode, 4631 .num_modes = 1, 4632 .bpc = 8, 4633 .size = { 4634 .width = 217, 4635 .height = 136, 4636 }, 4637 .connector_type = DRM_MODE_CONNECTOR_DSI, 4638 }, 4639 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4640 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4641 .format = MIPI_DSI_FMT_RGB888, 4642 .lanes = 4, 4643 }; 4644 4645 static const struct drm_display_mode lg_acx467akm_7_mode = { 4646 .clock = 150000, 4647 .hdisplay = 1080, 4648 .hsync_start = 1080 + 2, 4649 .hsync_end = 1080 + 2 + 2, 4650 .htotal = 1080 + 2 + 2 + 2, 4651 .vdisplay = 1920, 4652 .vsync_start = 1920 + 2, 4653 .vsync_end = 1920 + 2 + 2, 4654 .vtotal = 1920 + 2 + 2 + 2, 4655 }; 4656 4657 static const struct panel_desc_dsi lg_acx467akm_7 = { 4658 .desc = { 4659 .modes = &lg_acx467akm_7_mode, 4660 .num_modes = 1, 4661 .bpc = 8, 4662 .size = { 4663 .width = 62, 4664 .height = 110, 4665 }, 4666 .connector_type = DRM_MODE_CONNECTOR_DSI, 4667 }, 4668 .flags = 0, 4669 .format = MIPI_DSI_FMT_RGB888, 4670 .lanes = 4, 4671 }; 4672 4673 static const struct drm_display_mode osd101t2045_53ts_mode = { 4674 .clock = 154500, 4675 .hdisplay = 1920, 4676 .hsync_start = 1920 + 112, 4677 .hsync_end = 1920 + 112 + 16, 4678 .htotal = 1920 + 112 + 16 + 32, 4679 .vdisplay = 1200, 4680 .vsync_start = 1200 + 16, 4681 .vsync_end = 1200 + 16 + 2, 4682 .vtotal = 1200 + 16 + 2 + 16, 4683 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4684 }; 4685 4686 static const struct panel_desc_dsi osd101t2045_53ts = { 4687 .desc = { 4688 .modes = &osd101t2045_53ts_mode, 4689 .num_modes = 1, 4690 .bpc = 8, 4691 .size = { 4692 .width = 217, 4693 .height = 136, 4694 }, 4695 .connector_type = DRM_MODE_CONNECTOR_DSI, 4696 }, 4697 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4698 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4699 MIPI_DSI_MODE_NO_EOT_PACKET, 4700 .format = MIPI_DSI_FMT_RGB888, 4701 .lanes = 4, 4702 }; 4703 4704 static const struct of_device_id dsi_of_match[] = { 4705 { 4706 .compatible = "auo,b080uan01", 4707 .data = &auo_b080uan01 4708 }, { 4709 .compatible = "boe,tv080wum-nl0", 4710 .data = &boe_tv080wum_nl0 4711 }, { 4712 .compatible = "lg,ld070wx3-sl01", 4713 .data = &lg_ld070wx3_sl01 4714 }, { 4715 .compatible = "lg,lh500wx1-sd03", 4716 .data = &lg_lh500wx1_sd03 4717 }, { 4718 .compatible = "panasonic,vvx10f004b00", 4719 .data = &panasonic_vvx10f004b00 4720 }, { 4721 .compatible = "lg,acx467akm-7", 4722 .data = &lg_acx467akm_7 4723 }, { 4724 .compatible = "osddisplays,osd101t2045-53ts", 4725 .data = &osd101t2045_53ts 4726 }, { 4727 /* sentinel */ 4728 } 4729 }; 4730 MODULE_DEVICE_TABLE(of, dsi_of_match); 4731 4732 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4733 { 4734 const struct panel_desc_dsi *desc; 4735 const struct of_device_id *id; 4736 int err; 4737 4738 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4739 if (!id) 4740 return -ENODEV; 4741 4742 desc = id->data; 4743 4744 err = panel_simple_probe(&dsi->dev, &desc->desc); 4745 if (err < 0) 4746 return err; 4747 4748 dsi->mode_flags = desc->flags; 4749 dsi->format = desc->format; 4750 dsi->lanes = desc->lanes; 4751 4752 err = mipi_dsi_attach(dsi); 4753 if (err) { 4754 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4755 4756 drm_panel_remove(&panel->base); 4757 } 4758 4759 return err; 4760 } 4761 4762 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4763 { 4764 int err; 4765 4766 err = mipi_dsi_detach(dsi); 4767 if (err < 0) 4768 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4769 4770 panel_simple_remove(&dsi->dev); 4771 } 4772 4773 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4774 { 4775 panel_simple_shutdown(&dsi->dev); 4776 } 4777 4778 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4779 .driver = { 4780 .name = "panel-simple-dsi", 4781 .of_match_table = dsi_of_match, 4782 .pm = &panel_simple_pm_ops, 4783 }, 4784 .probe = panel_simple_dsi_probe, 4785 .remove = panel_simple_dsi_remove, 4786 .shutdown = panel_simple_dsi_shutdown, 4787 }; 4788 4789 static int __init panel_simple_init(void) 4790 { 4791 int err; 4792 4793 err = platform_driver_register(&panel_simple_platform_driver); 4794 if (err < 0) 4795 return err; 4796 4797 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4798 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4799 if (err < 0) 4800 goto err_did_platform_register; 4801 } 4802 4803 return 0; 4804 4805 err_did_platform_register: 4806 platform_driver_unregister(&panel_simple_platform_driver); 4807 4808 return err; 4809 } 4810 module_init(panel_simple_init); 4811 4812 static void __exit panel_simple_exit(void) 4813 { 4814 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4815 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4816 4817 platform_driver_unregister(&panel_simple_platform_driver); 4818 } 4819 module_exit(panel_simple_exit); 4820 4821 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4822 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4823 MODULE_LICENSE("GPL and additional rights"); 4824