1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 15 #include <video/mipi_display.h> 16 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_panel.h> 20 21 /*** Manufacturer Command Set ***/ 22 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */ 23 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */ 24 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */ 25 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */ 26 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */ 27 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */ 28 29 /* CMD2 P0 commands (Display Options and Power) */ 30 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */ 31 #define MCS_SGOPCTR 0x16 /* Source Bias Current */ 32 #define MCS_SDCTR 0x1A /* Source Output Delay Time */ 33 #define MCS_INVCTR 0x1B /* Inversion Type */ 34 #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */ 35 #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */ 36 #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */ 37 #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */ 38 #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */ 39 #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */ 40 #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */ 41 #define MCS_SETVGN 0x52 /* VG M/S N Control */ 42 #define MCS_SETVGP 0x54 /* VG M/S P Control */ 43 #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */ 44 45 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */ 46 #define GOA_VSTV1 0x00 47 #define GOA_VSTV2 0x07 48 #define GOA_VCLK1 0x0E 49 #define GOA_VCLK2 0x17 50 #define GOA_VCLK_OPT1 0x20 51 #define GOA_BICLK1 0x2A 52 #define GOA_BICLK2 0x37 53 #define GOA_BICLK3 0x44 54 #define GOA_BICLK4 0x4F 55 #define GOA_BICLK_OPT1 0x5B 56 #define GOA_BICLK_OPT2 0x60 57 #define MCS_GOA_GPO1 0x6D 58 #define MCS_GOA_GPO2 0x71 59 #define MCS_GOA_EQ 0x74 60 #define MCS_GOA_CLK_GALLON 0x7C 61 #define MCS_GOA_FS_SEL0 0x7E 62 #define MCS_GOA_FS_SEL1 0x87 63 #define MCS_GOA_FS_SEL2 0x91 64 #define MCS_GOA_FS_SEL3 0x9B 65 #define MCS_GOA_BS_SEL0 0xAC 66 #define MCS_GOA_BS_SEL1 0xB5 67 #define MCS_GOA_BS_SEL2 0xBF 68 #define MCS_GOA_BS_SEL3 0xC9 69 #define MCS_GOA_BS_SEL4 0xD3 70 71 /* CMD2 P3 commands (Gamma) */ 72 #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */ 73 #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */ 74 75 struct rm68200 { 76 struct device *dev; 77 struct drm_panel panel; 78 struct gpio_desc *reset_gpio; 79 struct regulator *supply; 80 bool prepared; 81 bool enabled; 82 }; 83 84 static const struct drm_display_mode default_mode = { 85 .clock = 52582, 86 .hdisplay = 720, 87 .hsync_start = 720 + 38, 88 .hsync_end = 720 + 38 + 8, 89 .htotal = 720 + 38 + 8 + 38, 90 .vdisplay = 1280, 91 .vsync_start = 1280 + 12, 92 .vsync_end = 1280 + 12 + 4, 93 .vtotal = 1280 + 12 + 4 + 12, 94 .flags = 0, 95 .width_mm = 68, 96 .height_mm = 122, 97 }; 98 99 static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel) 100 { 101 return container_of(panel, struct rm68200, panel); 102 } 103 104 static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data, 105 size_t len) 106 { 107 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 108 int err; 109 110 err = mipi_dsi_dcs_write_buffer(dsi, data, len); 111 if (err < 0) 112 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err); 113 } 114 115 static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value) 116 { 117 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 118 int err; 119 120 err = mipi_dsi_dcs_write(dsi, cmd, &value, 1); 121 if (err < 0) 122 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err); 123 } 124 125 #define dcs_write_seq(ctx, seq...) \ 126 ({ \ 127 static const u8 d[] = { seq }; \ 128 \ 129 rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 130 }) 131 132 /* 133 * This panel is not able to auto-increment all cmd addresses so for some of 134 * them, we need to send them one by one... 135 */ 136 #define dcs_write_cmd_seq(ctx, cmd, seq...) \ 137 ({ \ 138 static const u8 d[] = { seq }; \ 139 unsigned int i; \ 140 \ 141 for (i = 0; i < ARRAY_SIZE(d) ; i++) \ 142 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \ 143 }) 144 145 static void rm68200_init_sequence(struct rm68200 *ctx) 146 { 147 /* Enter CMD2 with page 0 */ 148 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0); 149 dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00); 150 dcs_write_seq(ctx, MCS_BT2CTR, 0xE5); 151 dcs_write_seq(ctx, MCS_SETAVDD, 0x0A); 152 dcs_write_seq(ctx, MCS_SETAVEE, 0x0A); 153 dcs_write_seq(ctx, MCS_SGOPCTR, 0x52); 154 dcs_write_seq(ctx, MCS_BT3CTR, 0x53); 155 dcs_write_seq(ctx, MCS_BT4CTR, 0x5A); 156 dcs_write_seq(ctx, MCS_INVCTR, 0x00); 157 dcs_write_seq(ctx, MCS_STBCTR, 0x0A); 158 dcs_write_seq(ctx, MCS_SDCTR, 0x06); 159 dcs_write_seq(ctx, MCS_VCMCTR, 0x56); 160 dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00); 161 dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00); 162 dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ 163 164 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2); 165 dcs_write_seq(ctx, GOA_VSTV1, 0x05); 166 dcs_write_seq(ctx, 0x02, 0x0B); 167 dcs_write_seq(ctx, 0x03, 0x0F); 168 dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50); 169 dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00, 170 0x50); 171 dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D, 172 0x00, 0x85, 0x08); 173 dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D, 174 0x00, 0x85, 0x08); 175 dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 176 0x00, 0x00, 0x00, 0x00); 177 dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08); 178 dcs_write_seq(ctx, 0x2D, 0x01); 179 dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D, 180 0x00); 181 dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00); 182 dcs_write_seq(ctx, 0x3D, 0x40); 183 dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00); 184 dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 185 0x00, 0x00, 0x00, 0x00, 0x00); 186 dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 0x00, 0x00); 188 dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00); 189 dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00); 190 dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 192 dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00); 193 dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00); 194 dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 195 0x00, 0x00); 196 dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00); 197 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10, 198 0x16, 0x12, 0x08, 0x3F); 199 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C, 200 0x0A, 0x0E, 0x3F, 0x3F, 0x00); 201 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 202 0x05, 0x01, 0x3F, 0x3F, 0x0F); 203 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F, 204 0x3F); 205 dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15); 206 dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F); 207 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13, 208 0x15, 0x11, 0x0F, 0x3F); 209 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B, 210 0x0D, 0x09, 0x3F, 0x3F, 0x07); 211 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F, 212 0x02, 0x06, 0x3F, 0x3F, 0x08); 213 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F, 214 0x3F, 0x3F, 0x0E, 0x10, 0x14); 215 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F); 216 dcs_write_seq(ctx, 0xDC, 0x02); 217 dcs_write_seq(ctx, 0xDE, 0x12); 218 219 dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */ 220 dcs_write_seq(ctx, 0x01, 0x75); 221 222 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3); 223 dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06, 224 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 225 0x12, 0x0C, 0x00); 226 dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06, 227 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 228 0x12, 0x0C, 0x00); 229 230 /* Exit CMD2 */ 231 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS); 232 } 233 234 static int rm68200_disable(struct drm_panel *panel) 235 { 236 struct rm68200 *ctx = panel_to_rm68200(panel); 237 238 if (!ctx->enabled) 239 return 0; 240 241 ctx->enabled = false; 242 243 return 0; 244 } 245 246 static int rm68200_unprepare(struct drm_panel *panel) 247 { 248 struct rm68200 *ctx = panel_to_rm68200(panel); 249 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 250 int ret; 251 252 if (!ctx->prepared) 253 return 0; 254 255 ret = mipi_dsi_dcs_set_display_off(dsi); 256 if (ret) 257 dev_warn(panel->dev, "failed to set display off: %d\n", ret); 258 259 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 260 if (ret) 261 dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret); 262 263 msleep(120); 264 265 if (ctx->reset_gpio) { 266 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 267 msleep(20); 268 } 269 270 regulator_disable(ctx->supply); 271 272 ctx->prepared = false; 273 274 return 0; 275 } 276 277 static int rm68200_prepare(struct drm_panel *panel) 278 { 279 struct rm68200 *ctx = panel_to_rm68200(panel); 280 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 281 int ret; 282 283 if (ctx->prepared) 284 return 0; 285 286 ret = regulator_enable(ctx->supply); 287 if (ret < 0) { 288 dev_err(ctx->dev, "failed to enable supply: %d\n", ret); 289 return ret; 290 } 291 292 if (ctx->reset_gpio) { 293 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 294 msleep(20); 295 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 296 msleep(100); 297 } 298 299 rm68200_init_sequence(ctx); 300 301 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 302 if (ret) 303 return ret; 304 305 msleep(125); 306 307 ret = mipi_dsi_dcs_set_display_on(dsi); 308 if (ret) 309 return ret; 310 311 msleep(20); 312 313 ctx->prepared = true; 314 315 return 0; 316 } 317 318 static int rm68200_enable(struct drm_panel *panel) 319 { 320 struct rm68200 *ctx = panel_to_rm68200(panel); 321 322 if (ctx->enabled) 323 return 0; 324 325 ctx->enabled = true; 326 327 return 0; 328 } 329 330 static int rm68200_get_modes(struct drm_panel *panel, 331 struct drm_connector *connector) 332 { 333 struct drm_display_mode *mode; 334 335 mode = drm_mode_duplicate(connector->dev, &default_mode); 336 if (!mode) { 337 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", 338 default_mode.hdisplay, default_mode.vdisplay, 339 drm_mode_vrefresh(&default_mode)); 340 return -ENOMEM; 341 } 342 343 drm_mode_set_name(mode); 344 345 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 346 drm_mode_probed_add(connector, mode); 347 348 connector->display_info.width_mm = mode->width_mm; 349 connector->display_info.height_mm = mode->height_mm; 350 351 return 1; 352 } 353 354 static const struct drm_panel_funcs rm68200_drm_funcs = { 355 .disable = rm68200_disable, 356 .unprepare = rm68200_unprepare, 357 .prepare = rm68200_prepare, 358 .enable = rm68200_enable, 359 .get_modes = rm68200_get_modes, 360 }; 361 362 static int rm68200_probe(struct mipi_dsi_device *dsi) 363 { 364 struct device *dev = &dsi->dev; 365 struct rm68200 *ctx; 366 int ret; 367 368 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 369 if (!ctx) 370 return -ENOMEM; 371 372 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 373 if (IS_ERR(ctx->reset_gpio)) { 374 ret = PTR_ERR(ctx->reset_gpio); 375 dev_err(dev, "cannot get reset GPIO: %d\n", ret); 376 return ret; 377 } 378 379 ctx->supply = devm_regulator_get(dev, "power"); 380 if (IS_ERR(ctx->supply)) { 381 ret = PTR_ERR(ctx->supply); 382 if (ret != -EPROBE_DEFER) 383 dev_err(dev, "cannot get regulator: %d\n", ret); 384 return ret; 385 } 386 387 mipi_dsi_set_drvdata(dsi, ctx); 388 389 ctx->dev = dev; 390 391 dsi->lanes = 2; 392 dsi->format = MIPI_DSI_FMT_RGB888; 393 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 394 MIPI_DSI_MODE_LPM; 395 396 drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs, 397 DRM_MODE_CONNECTOR_DSI); 398 399 ret = drm_panel_of_backlight(&ctx->panel); 400 if (ret) 401 return ret; 402 403 drm_panel_add(&ctx->panel); 404 405 ret = mipi_dsi_attach(dsi); 406 if (ret < 0) { 407 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 408 drm_panel_remove(&ctx->panel); 409 return ret; 410 } 411 412 return 0; 413 } 414 415 static int rm68200_remove(struct mipi_dsi_device *dsi) 416 { 417 struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi); 418 419 mipi_dsi_detach(dsi); 420 drm_panel_remove(&ctx->panel); 421 422 return 0; 423 } 424 425 static const struct of_device_id raydium_rm68200_of_match[] = { 426 { .compatible = "raydium,rm68200" }, 427 { } 428 }; 429 MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match); 430 431 static struct mipi_dsi_driver raydium_rm68200_driver = { 432 .probe = rm68200_probe, 433 .remove = rm68200_remove, 434 .driver = { 435 .name = "panel-raydium-rm68200", 436 .of_match_table = raydium_rm68200_of_match, 437 }, 438 }; 439 module_mipi_dsi_driver(raydium_rm68200_driver); 440 441 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 442 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 443 MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel"); 444 MODULE_LICENSE("GPL v2"); 445