1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/backlight.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 15 #include <video/mipi_display.h> 16 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_panel.h> 20 #include <drm/drm_print.h> 21 22 #define OTM8009A_BACKLIGHT_DEFAULT 240 23 #define OTM8009A_BACKLIGHT_MAX 255 24 25 /* Manufacturer Command Set */ 26 #define MCS_ADRSFT 0x0000 /* Address Shift Function */ 27 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */ 28 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ 29 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ 30 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ 31 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ 32 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ 33 #define MCS_NO_DOC1 0xC48A /* Command not documented */ 34 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ 35 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ 36 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ 37 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ 38 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ 39 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ 40 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ 41 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ 42 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ 43 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ 44 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ 45 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ 46 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ 47 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ 48 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ 49 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ 50 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ 51 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */ 52 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ 53 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ 54 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ 55 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */ 56 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ 57 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ 58 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ 59 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ 60 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */ 61 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ 62 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ 63 64 struct otm8009a { 65 struct device *dev; 66 struct drm_panel panel; 67 struct backlight_device *bl_dev; 68 struct gpio_desc *reset_gpio; 69 struct regulator *supply; 70 bool prepared; 71 bool enabled; 72 }; 73 74 static const struct drm_display_mode default_mode = { 75 .clock = 29700, 76 .hdisplay = 480, 77 .hsync_start = 480 + 98, 78 .hsync_end = 480 + 98 + 32, 79 .htotal = 480 + 98 + 32 + 98, 80 .vdisplay = 800, 81 .vsync_start = 800 + 15, 82 .vsync_end = 800 + 15 + 10, 83 .vtotal = 800 + 15 + 10 + 14, 84 .flags = 0, 85 .width_mm = 52, 86 .height_mm = 86, 87 }; 88 89 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) 90 { 91 return container_of(panel, struct otm8009a, panel); 92 } 93 94 static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data, 95 size_t len) 96 { 97 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 98 99 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0) 100 DRM_WARN("mipi dsi dcs write buffer failed\n"); 101 } 102 103 static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data, 104 size_t len) 105 { 106 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 107 108 /* data will be sent in dsi hs mode (ie. no lpm) */ 109 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 110 111 otm8009a_dcs_write_buf(ctx, data, len); 112 113 /* restore back the dsi lpm mode */ 114 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 115 } 116 117 #define dcs_write_seq(ctx, seq...) \ 118 ({ \ 119 static const u8 d[] = { seq }; \ 120 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 121 }) 122 123 #define dcs_write_cmd_at(ctx, cmd, seq...) \ 124 ({ \ 125 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ 126 dcs_write_seq(ctx, (cmd) >> 8, seq); \ 127 }) 128 129 static int otm8009a_init_sequence(struct otm8009a *ctx) 130 { 131 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 132 int ret; 133 134 /* Enter CMD2 */ 135 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); 136 137 /* Enter Orise Command2 */ 138 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09); 139 140 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30); 141 mdelay(10); 142 143 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40); 144 mdelay(10); 145 146 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9); 147 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34); 148 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50); 149 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E); 150 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ 151 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01); 152 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34); 153 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33); 154 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79); 155 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B); 156 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83); 157 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83); 158 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E); 159 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01); 160 161 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); 162 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 163 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); 164 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 165 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); 166 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 167 0x01, 0x02, 0x00, 0x00); 168 169 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00); 170 171 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 172 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 173 0, 0, 0, 0, 0); 174 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 175 0, 0, 0, 0, 0); 176 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 177 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 178 0, 0, 0, 0, 0); 179 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 180 4, 0, 0, 0, 0); 181 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 182 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 183 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); 184 185 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 186 0x00, 0x00, 0x00, 0x00); 187 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); 189 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 191 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 192 0x00, 0x00, 0x00, 0x00); 193 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 194 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); 195 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 197 198 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66); 199 200 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06); 201 202 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 203 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 204 0x01); 205 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 206 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 207 0x01); 208 209 /* Exit CMD2 */ 210 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); 211 212 ret = mipi_dsi_dcs_nop(dsi); 213 if (ret) 214 return ret; 215 216 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 217 if (ret) 218 return ret; 219 220 /* Wait for sleep out exit */ 221 mdelay(120); 222 223 /* Default portrait 480x800 rgb24 */ 224 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 225 226 ret = mipi_dsi_dcs_set_column_address(dsi, 0, 227 default_mode.hdisplay - 1); 228 if (ret) 229 return ret; 230 231 ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1); 232 if (ret) 233 return ret; 234 235 /* See otm8009a driver documentation for pixel format descriptions */ 236 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT | 237 MIPI_DCS_PIXEL_FMT_24BIT << 4); 238 if (ret) 239 return ret; 240 241 /* Disable CABC feature */ 242 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); 243 244 ret = mipi_dsi_dcs_set_display_on(dsi); 245 if (ret) 246 return ret; 247 248 ret = mipi_dsi_dcs_nop(dsi); 249 if (ret) 250 return ret; 251 252 /* Send Command GRAM memory write (no parameters) */ 253 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START); 254 255 /* Wait a short while to let the panel be ready before the 1st frame */ 256 mdelay(10); 257 258 return 0; 259 } 260 261 static int otm8009a_disable(struct drm_panel *panel) 262 { 263 struct otm8009a *ctx = panel_to_otm8009a(panel); 264 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 265 int ret; 266 267 if (!ctx->enabled) 268 return 0; /* This is not an issue so we return 0 here */ 269 270 backlight_disable(ctx->bl_dev); 271 272 ret = mipi_dsi_dcs_set_display_off(dsi); 273 if (ret) 274 return ret; 275 276 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 277 if (ret) 278 return ret; 279 280 msleep(120); 281 282 ctx->enabled = false; 283 284 return 0; 285 } 286 287 static int otm8009a_unprepare(struct drm_panel *panel) 288 { 289 struct otm8009a *ctx = panel_to_otm8009a(panel); 290 291 if (!ctx->prepared) 292 return 0; 293 294 if (ctx->reset_gpio) { 295 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 296 msleep(20); 297 } 298 299 regulator_disable(ctx->supply); 300 301 ctx->prepared = false; 302 303 return 0; 304 } 305 306 static int otm8009a_prepare(struct drm_panel *panel) 307 { 308 struct otm8009a *ctx = panel_to_otm8009a(panel); 309 int ret; 310 311 if (ctx->prepared) 312 return 0; 313 314 ret = regulator_enable(ctx->supply); 315 if (ret < 0) { 316 DRM_ERROR("failed to enable supply: %d\n", ret); 317 return ret; 318 } 319 320 if (ctx->reset_gpio) { 321 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 322 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 323 msleep(20); 324 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 325 msleep(100); 326 } 327 328 ret = otm8009a_init_sequence(ctx); 329 if (ret) 330 return ret; 331 332 ctx->prepared = true; 333 334 return 0; 335 } 336 337 static int otm8009a_enable(struct drm_panel *panel) 338 { 339 struct otm8009a *ctx = panel_to_otm8009a(panel); 340 341 if (ctx->enabled) 342 return 0; 343 344 backlight_enable(ctx->bl_dev); 345 346 ctx->enabled = true; 347 348 return 0; 349 } 350 351 static int otm8009a_get_modes(struct drm_panel *panel, 352 struct drm_connector *connector) 353 { 354 struct drm_display_mode *mode; 355 356 mode = drm_mode_duplicate(connector->dev, &default_mode); 357 if (!mode) { 358 DRM_ERROR("failed to add mode %ux%ux@%u\n", 359 default_mode.hdisplay, default_mode.vdisplay, 360 drm_mode_vrefresh(&default_mode)); 361 return -ENOMEM; 362 } 363 364 drm_mode_set_name(mode); 365 366 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 367 drm_mode_probed_add(connector, mode); 368 369 connector->display_info.width_mm = mode->width_mm; 370 connector->display_info.height_mm = mode->height_mm; 371 372 return 1; 373 } 374 375 static const struct drm_panel_funcs otm8009a_drm_funcs = { 376 .disable = otm8009a_disable, 377 .unprepare = otm8009a_unprepare, 378 .prepare = otm8009a_prepare, 379 .enable = otm8009a_enable, 380 .get_modes = otm8009a_get_modes, 381 }; 382 383 /* 384 * DSI-BASED BACKLIGHT 385 */ 386 387 static int otm8009a_backlight_update_status(struct backlight_device *bd) 388 { 389 struct otm8009a *ctx = bl_get_data(bd); 390 u8 data[2]; 391 392 if (!ctx->prepared) { 393 DRM_DEBUG("lcd not ready yet for setting its backlight!\n"); 394 return -ENXIO; 395 } 396 397 if (bd->props.power <= FB_BLANK_NORMAL) { 398 /* Power on the backlight with the requested brightness 399 * Note We can not use mipi_dsi_dcs_set_display_brightness() 400 * as otm8009a driver support only 8-bit brightness (1 param). 401 */ 402 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; 403 data[1] = bd->props.brightness; 404 otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data)); 405 406 /* set Brightness Control & Backlight on */ 407 data[1] = 0x24; 408 409 } else { 410 /* Power off the backlight: set Brightness Control & Bl off */ 411 data[1] = 0; 412 } 413 414 /* Update Brightness Control & Backlight */ 415 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; 416 otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data)); 417 418 return 0; 419 } 420 421 static const struct backlight_ops otm8009a_backlight_ops = { 422 .update_status = otm8009a_backlight_update_status, 423 }; 424 425 static int otm8009a_probe(struct mipi_dsi_device *dsi) 426 { 427 struct device *dev = &dsi->dev; 428 struct otm8009a *ctx; 429 int ret; 430 431 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 432 if (!ctx) 433 return -ENOMEM; 434 435 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 436 if (IS_ERR(ctx->reset_gpio)) { 437 dev_err(dev, "cannot get reset-gpio\n"); 438 return PTR_ERR(ctx->reset_gpio); 439 } 440 441 ctx->supply = devm_regulator_get(dev, "power"); 442 if (IS_ERR(ctx->supply)) { 443 ret = PTR_ERR(ctx->supply); 444 if (ret != -EPROBE_DEFER) 445 dev_err(dev, "failed to request regulator: %d\n", ret); 446 return ret; 447 } 448 449 mipi_dsi_set_drvdata(dsi, ctx); 450 451 ctx->dev = dev; 452 453 dsi->lanes = 2; 454 dsi->format = MIPI_DSI_FMT_RGB888; 455 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 456 MIPI_DSI_MODE_LPM; 457 458 drm_panel_init(&ctx->panel, dev, &otm8009a_drm_funcs, 459 DRM_MODE_CONNECTOR_DSI); 460 461 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), 462 dsi->host->dev, ctx, 463 &otm8009a_backlight_ops, 464 NULL); 465 if (IS_ERR(ctx->bl_dev)) { 466 ret = PTR_ERR(ctx->bl_dev); 467 dev_err(dev, "failed to register backlight: %d\n", ret); 468 return ret; 469 } 470 471 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; 472 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; 473 ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; 474 ctx->bl_dev->props.type = BACKLIGHT_RAW; 475 476 drm_panel_add(&ctx->panel); 477 478 ret = mipi_dsi_attach(dsi); 479 if (ret < 0) { 480 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n"); 481 drm_panel_remove(&ctx->panel); 482 return ret; 483 } 484 485 return 0; 486 } 487 488 static int otm8009a_remove(struct mipi_dsi_device *dsi) 489 { 490 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi); 491 492 mipi_dsi_detach(dsi); 493 drm_panel_remove(&ctx->panel); 494 495 return 0; 496 } 497 498 static const struct of_device_id orisetech_otm8009a_of_match[] = { 499 { .compatible = "orisetech,otm8009a" }, 500 { } 501 }; 502 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match); 503 504 static struct mipi_dsi_driver orisetech_otm8009a_driver = { 505 .probe = otm8009a_probe, 506 .remove = otm8009a_remove, 507 .driver = { 508 .name = "panel-orisetech-otm8009a", 509 .of_match_table = orisetech_otm8009a_of_match, 510 }, 511 }; 512 module_mipi_dsi_driver(orisetech_otm8009a_driver); 513 514 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 515 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 516 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel"); 517 MODULE_LICENSE("GPL v2"); 518