1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/backlight.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 15 #include <video/mipi_display.h> 16 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_panel.h> 20 21 #define OTM8009A_BACKLIGHT_DEFAULT 240 22 #define OTM8009A_BACKLIGHT_MAX 255 23 24 /* Manufacturer Command Set */ 25 #define MCS_ADRSFT 0x0000 /* Address Shift Function */ 26 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */ 27 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ 28 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ 29 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ 30 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ 31 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ 32 #define MCS_NO_DOC1 0xC48A /* Command not documented */ 33 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ 34 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ 35 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ 36 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ 37 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ 38 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ 39 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ 40 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ 41 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ 42 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ 43 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ 44 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ 45 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ 46 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ 47 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ 48 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ 49 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ 50 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */ 51 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ 52 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ 53 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ 54 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */ 55 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ 56 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ 57 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ 58 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ 59 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */ 60 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ 61 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ 62 63 struct otm8009a { 64 struct device *dev; 65 struct drm_panel panel; 66 struct backlight_device *bl_dev; 67 struct gpio_desc *reset_gpio; 68 struct regulator *supply; 69 bool prepared; 70 bool enabled; 71 }; 72 73 static const struct drm_display_mode default_mode = { 74 .clock = 29700, 75 .hdisplay = 480, 76 .hsync_start = 480 + 98, 77 .hsync_end = 480 + 98 + 32, 78 .htotal = 480 + 98 + 32 + 98, 79 .vdisplay = 800, 80 .vsync_start = 800 + 15, 81 .vsync_end = 800 + 15 + 10, 82 .vtotal = 800 + 15 + 10 + 14, 83 .flags = 0, 84 .width_mm = 52, 85 .height_mm = 86, 86 }; 87 88 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) 89 { 90 return container_of(panel, struct otm8009a, panel); 91 } 92 93 static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data, 94 size_t len) 95 { 96 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 97 98 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0) 99 dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n"); 100 } 101 102 static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data, 103 size_t len) 104 { 105 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 106 107 /* data will be sent in dsi hs mode (ie. no lpm) */ 108 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 109 110 otm8009a_dcs_write_buf(ctx, data, len); 111 112 /* restore back the dsi lpm mode */ 113 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 114 } 115 116 #define dcs_write_seq(ctx, seq...) \ 117 ({ \ 118 static const u8 d[] = { seq }; \ 119 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 120 }) 121 122 #define dcs_write_cmd_at(ctx, cmd, seq...) \ 123 ({ \ 124 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ 125 dcs_write_seq(ctx, (cmd) >> 8, seq); \ 126 }) 127 128 static int otm8009a_init_sequence(struct otm8009a *ctx) 129 { 130 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 131 int ret; 132 133 /* Enter CMD2 */ 134 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); 135 136 /* Enter Orise Command2 */ 137 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09); 138 139 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30); 140 mdelay(10); 141 142 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40); 143 mdelay(10); 144 145 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9); 146 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34); 147 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50); 148 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E); 149 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ 150 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01); 151 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34); 152 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33); 153 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79); 154 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B); 155 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83); 156 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83); 157 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E); 158 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01); 159 160 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); 161 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 162 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); 163 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 164 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); 165 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 166 0x01, 0x02, 0x00, 0x00); 167 168 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00); 169 170 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 171 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 172 0, 0, 0, 0, 0); 173 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174 0, 0, 0, 0, 0); 175 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 176 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 177 0, 0, 0, 0, 0); 178 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 179 4, 0, 0, 0, 0); 180 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 181 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 182 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); 183 184 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 185 0x00, 0x00, 0x00, 0x00); 186 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 187 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); 188 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 190 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 191 0x00, 0x00, 0x00, 0x00); 192 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 193 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); 194 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 196 197 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66); 198 199 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06); 200 201 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 202 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 203 0x01); 204 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 205 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 206 0x01); 207 208 /* Exit CMD2 */ 209 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); 210 211 ret = mipi_dsi_dcs_nop(dsi); 212 if (ret) 213 return ret; 214 215 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 216 if (ret) 217 return ret; 218 219 /* Wait for sleep out exit */ 220 mdelay(120); 221 222 /* Default portrait 480x800 rgb24 */ 223 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 224 225 ret = mipi_dsi_dcs_set_column_address(dsi, 0, 226 default_mode.hdisplay - 1); 227 if (ret) 228 return ret; 229 230 ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1); 231 if (ret) 232 return ret; 233 234 /* See otm8009a driver documentation for pixel format descriptions */ 235 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT | 236 MIPI_DCS_PIXEL_FMT_24BIT << 4); 237 if (ret) 238 return ret; 239 240 /* Disable CABC feature */ 241 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); 242 243 ret = mipi_dsi_dcs_set_display_on(dsi); 244 if (ret) 245 return ret; 246 247 ret = mipi_dsi_dcs_nop(dsi); 248 if (ret) 249 return ret; 250 251 /* Send Command GRAM memory write (no parameters) */ 252 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START); 253 254 /* Wait a short while to let the panel be ready before the 1st frame */ 255 mdelay(10); 256 257 return 0; 258 } 259 260 static int otm8009a_disable(struct drm_panel *panel) 261 { 262 struct otm8009a *ctx = panel_to_otm8009a(panel); 263 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 264 int ret; 265 266 if (!ctx->enabled) 267 return 0; /* This is not an issue so we return 0 here */ 268 269 backlight_disable(ctx->bl_dev); 270 271 ret = mipi_dsi_dcs_set_display_off(dsi); 272 if (ret) 273 return ret; 274 275 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 276 if (ret) 277 return ret; 278 279 msleep(120); 280 281 ctx->enabled = false; 282 283 return 0; 284 } 285 286 static int otm8009a_unprepare(struct drm_panel *panel) 287 { 288 struct otm8009a *ctx = panel_to_otm8009a(panel); 289 290 if (!ctx->prepared) 291 return 0; 292 293 if (ctx->reset_gpio) { 294 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 295 msleep(20); 296 } 297 298 regulator_disable(ctx->supply); 299 300 ctx->prepared = false; 301 302 return 0; 303 } 304 305 static int otm8009a_prepare(struct drm_panel *panel) 306 { 307 struct otm8009a *ctx = panel_to_otm8009a(panel); 308 int ret; 309 310 if (ctx->prepared) 311 return 0; 312 313 ret = regulator_enable(ctx->supply); 314 if (ret < 0) { 315 dev_err(panel->dev, "failed to enable supply: %d\n", ret); 316 return ret; 317 } 318 319 if (ctx->reset_gpio) { 320 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 321 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 322 msleep(20); 323 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 324 msleep(100); 325 } 326 327 ret = otm8009a_init_sequence(ctx); 328 if (ret) 329 return ret; 330 331 ctx->prepared = true; 332 333 return 0; 334 } 335 336 static int otm8009a_enable(struct drm_panel *panel) 337 { 338 struct otm8009a *ctx = panel_to_otm8009a(panel); 339 340 if (ctx->enabled) 341 return 0; 342 343 backlight_enable(ctx->bl_dev); 344 345 ctx->enabled = true; 346 347 return 0; 348 } 349 350 static int otm8009a_get_modes(struct drm_panel *panel, 351 struct drm_connector *connector) 352 { 353 struct drm_display_mode *mode; 354 355 mode = drm_mode_duplicate(connector->dev, &default_mode); 356 if (!mode) { 357 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", 358 default_mode.hdisplay, default_mode.vdisplay, 359 drm_mode_vrefresh(&default_mode)); 360 return -ENOMEM; 361 } 362 363 drm_mode_set_name(mode); 364 365 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 366 drm_mode_probed_add(connector, mode); 367 368 connector->display_info.width_mm = mode->width_mm; 369 connector->display_info.height_mm = mode->height_mm; 370 371 return 1; 372 } 373 374 static const struct drm_panel_funcs otm8009a_drm_funcs = { 375 .disable = otm8009a_disable, 376 .unprepare = otm8009a_unprepare, 377 .prepare = otm8009a_prepare, 378 .enable = otm8009a_enable, 379 .get_modes = otm8009a_get_modes, 380 }; 381 382 /* 383 * DSI-BASED BACKLIGHT 384 */ 385 386 static int otm8009a_backlight_update_status(struct backlight_device *bd) 387 { 388 struct otm8009a *ctx = bl_get_data(bd); 389 u8 data[2]; 390 391 if (!ctx->prepared) { 392 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n"); 393 return -ENXIO; 394 } 395 396 if (bd->props.power <= FB_BLANK_NORMAL) { 397 /* Power on the backlight with the requested brightness 398 * Note We can not use mipi_dsi_dcs_set_display_brightness() 399 * as otm8009a driver support only 8-bit brightness (1 param). 400 */ 401 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; 402 data[1] = bd->props.brightness; 403 otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data)); 404 405 /* set Brightness Control & Backlight on */ 406 data[1] = 0x24; 407 408 } else { 409 /* Power off the backlight: set Brightness Control & Bl off */ 410 data[1] = 0; 411 } 412 413 /* Update Brightness Control & Backlight */ 414 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; 415 otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data)); 416 417 return 0; 418 } 419 420 static const struct backlight_ops otm8009a_backlight_ops = { 421 .update_status = otm8009a_backlight_update_status, 422 }; 423 424 static int otm8009a_probe(struct mipi_dsi_device *dsi) 425 { 426 struct device *dev = &dsi->dev; 427 struct otm8009a *ctx; 428 int ret; 429 430 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 431 if (!ctx) 432 return -ENOMEM; 433 434 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 435 if (IS_ERR(ctx->reset_gpio)) { 436 dev_err(dev, "cannot get reset-gpio\n"); 437 return PTR_ERR(ctx->reset_gpio); 438 } 439 440 ctx->supply = devm_regulator_get(dev, "power"); 441 if (IS_ERR(ctx->supply)) { 442 ret = PTR_ERR(ctx->supply); 443 if (ret != -EPROBE_DEFER) 444 dev_err(dev, "failed to request regulator: %d\n", ret); 445 return ret; 446 } 447 448 mipi_dsi_set_drvdata(dsi, ctx); 449 450 ctx->dev = dev; 451 452 dsi->lanes = 2; 453 dsi->format = MIPI_DSI_FMT_RGB888; 454 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 455 MIPI_DSI_MODE_LPM; 456 457 drm_panel_init(&ctx->panel, dev, &otm8009a_drm_funcs, 458 DRM_MODE_CONNECTOR_DSI); 459 460 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), 461 dsi->host->dev, ctx, 462 &otm8009a_backlight_ops, 463 NULL); 464 if (IS_ERR(ctx->bl_dev)) { 465 ret = PTR_ERR(ctx->bl_dev); 466 dev_err(dev, "failed to register backlight: %d\n", ret); 467 return ret; 468 } 469 470 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; 471 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; 472 ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; 473 ctx->bl_dev->props.type = BACKLIGHT_RAW; 474 475 drm_panel_add(&ctx->panel); 476 477 ret = mipi_dsi_attach(dsi); 478 if (ret < 0) { 479 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n"); 480 drm_panel_remove(&ctx->panel); 481 return ret; 482 } 483 484 return 0; 485 } 486 487 static int otm8009a_remove(struct mipi_dsi_device *dsi) 488 { 489 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi); 490 491 mipi_dsi_detach(dsi); 492 drm_panel_remove(&ctx->panel); 493 494 return 0; 495 } 496 497 static const struct of_device_id orisetech_otm8009a_of_match[] = { 498 { .compatible = "orisetech,otm8009a" }, 499 { } 500 }; 501 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match); 502 503 static struct mipi_dsi_driver orisetech_otm8009a_driver = { 504 .probe = otm8009a_probe, 505 .remove = otm8009a_remove, 506 .driver = { 507 .name = "panel-orisetech-otm8009a", 508 .of_match_table = orisetech_otm8009a_of_match, 509 }, 510 }; 511 module_mipi_dsi_driver(orisetech_otm8009a_driver); 512 513 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 514 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 515 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel"); 516 MODULE_LICENSE("GPL v2"); 517