1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Novatek NT35510 panel driver 4 * Copyright (C) 2020 Linus Walleij <linus.walleij@linaro.org> 5 * Based on code by Robert Teather (C) 2012 Samsung 6 * 7 * This display driver (and I refer to the physical component NT35510, 8 * not this Linux kernel software driver) can handle: 9 * 480x864, 480x854, 480x800, 480x720 and 480x640 pixel displays. 10 * It has 480x840x24bit SRAM embedded for storing a frame. 11 * When powered on the display is by default in 480x800 mode. 12 * 13 * The actual panels using this component have different names, but 14 * the code needed to set up and configure the panel will be similar, 15 * so they should all use the NT35510 driver with appropriate configuration 16 * per-panel, e.g. for physical size. 17 * 18 * This driver is for the DSI interface to panels using the NT35510. 19 * 20 * The NT35510 can also use an RGB (DPI) interface combined with an 21 * I2C or SPI interface for setting up the NT35510. If this is needed 22 * this panel driver should be refactored to also support that use 23 * case. 24 */ 25 #include <linux/backlight.h> 26 #include <linux/bitops.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 33 #include <video/mipi_display.h> 34 35 #include <drm/drm_mipi_dsi.h> 36 #include <drm/drm_modes.h> 37 #include <drm/drm_panel.h> 38 #include <drm/drm_print.h> 39 40 #define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */ 41 #define MCS_CMD_READ_ID1 0xDA 42 #define MCS_CMD_READ_ID2 0xDB 43 #define MCS_CMD_READ_ID3 0xDC 44 #define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */ 45 #define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */ 46 47 /* 48 * These manufacturer commands are available after we enable manufacturer 49 * command set (MCS) for page 0. 50 */ 51 #define NT35510_P0_DOPCTR 0xB1 52 #define NT35510_P0_SDHDTCTR 0xB6 53 #define NT35510_P0_GSEQCTR 0xB7 54 #define NT35510_P0_SDEQCTR 0xB8 55 #define NT35510_P0_SDVPCTR 0xBA 56 #define NT35510_P0_DPFRCTR1 0xBD 57 #define NT35510_P0_DPFRCTR2 0xBE 58 #define NT35510_P0_DPFRCTR3 0xBF 59 #define NT35510_P0_DPMCTR12 0xCC 60 61 #define NT35510_P0_DOPCTR_LEN 2 62 #define NT35510_P0_GSEQCTR_LEN 2 63 #define NT35510_P0_SDEQCTR_LEN 4 64 #define NT35510_P0_SDVPCTR_LEN 1 65 #define NT35510_P0_DPFRCTR1_LEN 5 66 #define NT35510_P0_DPFRCTR2_LEN 5 67 #define NT35510_P0_DPFRCTR3_LEN 5 68 #define NT35510_P0_DPMCTR12_LEN 3 69 70 #define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */ 71 #define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */ 72 #define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */ 73 #define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */ 74 #define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */ 75 #define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */ 76 #define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */ 77 #define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */ 78 #define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */ 79 #define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */ 80 #define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */ 81 #define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */ 82 #define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */ 83 #define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */ 84 #define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */ 85 86 /* 87 * These manufacturer commands are available after we enable manufacturer 88 * command set (MCS) for page 1. 89 */ 90 #define NT35510_P1_SETAVDD 0xB0 91 #define NT35510_P1_SETAVEE 0xB1 92 #define NT35510_P1_SETVCL 0xB2 93 #define NT35510_P1_SETVGH 0xB3 94 #define NT35510_P1_SETVRGH 0xB4 95 #define NT35510_P1_SETVGL 0xB5 96 #define NT35510_P1_BT1CTR 0xB6 97 #define NT35510_P1_BT2CTR 0xB7 98 #define NT35510_P1_BT3CTR 0xB8 99 #define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */ 100 #define NT35510_P1_BT5CTR 0xBA 101 #define NT35510_P1_PFMCTR 0xBB 102 #define NT35510_P1_SETVGP 0xBC 103 #define NT35510_P1_SETVGN 0xBD 104 #define NT35510_P1_SETVCMOFF 0xBE 105 #define NT35510_P1_VGHCTR 0xBF /* VGH output ctrl */ 106 #define NT35510_P1_SET_GAMMA_RED_POS 0xD1 107 #define NT35510_P1_SET_GAMMA_GREEN_POS 0xD2 108 #define NT35510_P1_SET_GAMMA_BLUE_POS 0xD3 109 #define NT35510_P1_SET_GAMMA_RED_NEG 0xD4 110 #define NT35510_P1_SET_GAMMA_GREEN_NEG 0xD5 111 #define NT35510_P1_SET_GAMMA_BLUE_NEG 0xD6 112 113 /* AVDD and AVEE setting 3 bytes */ 114 #define NT35510_P1_AVDD_LEN 3 115 #define NT35510_P1_AVEE_LEN 3 116 #define NT35510_P1_VGH_LEN 3 117 #define NT35510_P1_VGL_LEN 3 118 #define NT35510_P1_VGP_LEN 3 119 #define NT35510_P1_VGN_LEN 3 120 /* BT1CTR thru BT5CTR setting 3 bytes */ 121 #define NT35510_P1_BT1CTR_LEN 3 122 #define NT35510_P1_BT2CTR_LEN 3 123 #define NT35510_P1_BT4CTR_LEN 3 124 #define NT35510_P1_BT5CTR_LEN 3 125 /* 52 gamma parameters times two per color: positive and negative */ 126 #define NT35510_P1_GAMMA_LEN 52 127 128 /** 129 * struct nt35510_config - the display-specific NT35510 configuration 130 * 131 * Some of the settings provide an array of bytes, A, B C which mean: 132 * A = normal / idle off mode 133 * B = idle on mode 134 * C = partial / idle off mode 135 * 136 * Gamma correction arrays are 10bit numbers, two consecutive bytes 137 * makes out one point on the gamma correction curve. The points are 138 * not linearly placed along the X axis, we get points 0, 1, 3, 5 139 * 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232, 140 * 240, 244, 248, 250, 252, 254, 255. The voltages tuples form 141 * V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and 142 * 0x03FF being the highest voltage. 143 * 144 * Each value must be strictly higher than the previous value forming 145 * a rising curve like this: 146 * 147 * ^ 148 * | V255 149 * | V254 150 * | .... 151 * | V5 152 * | V3 153 * | V1 154 * | V0 155 * +-------------------------------------------> 156 * 157 * The details about all settings can be found in the NT35510 Application 158 * Note. 159 */ 160 struct nt35510_config { 161 /** 162 * @width_mm: physical panel width [mm] 163 */ 164 u32 width_mm; 165 /** 166 * @height_mm: physical panel height [mm] 167 */ 168 u32 height_mm; 169 /** 170 * @mode: the display mode. This is only relevant outside the panel 171 * in video mode: in command mode this is configuring the internal 172 * timing in the display controller. 173 */ 174 const struct drm_display_mode mode; 175 /** 176 * @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V 177 * in 0.1V steps the default is 0x05 which means 6.0V 178 */ 179 u8 avdd[NT35510_P1_AVDD_LEN]; 180 /** 181 * @bt1ctr: setting for boost power control for the AVDD step-up 182 * circuit (1) 183 * bits 0..2 in the lower nibble controls PCK, the booster clock 184 * frequency for the step-up circuit: 185 * 0 = Hsync/32 186 * 1 = Hsync/16 187 * 2 = Hsync/8 188 * 3 = Hsync/4 189 * 4 = Hsync/2 190 * 5 = Hsync 191 * 6 = Hsync x 2 192 * 7 = Hsync x 4 193 * bits 4..6 in the upper nibble controls BTP, the boosting 194 * amplification for the the step-up circuit: 195 * 0 = Disable 196 * 1 = 1.5 x VDDB 197 * 2 = 1.66 x VDDB 198 * 3 = 2 x VDDB 199 * 4 = 2.5 x VDDB 200 * 5 = 3 x VDDB 201 * The defaults are 4 and 4 yielding 0x44 202 */ 203 u8 bt1ctr[NT35510_P1_BT1CTR_LEN]; 204 /** 205 * @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V 206 * in 0.1V steps the default is 0x05 which means -6.0V 207 */ 208 u8 avee[NT35510_P1_AVEE_LEN]; 209 /** 210 * @bt2ctr: setting for boost power control for the AVEE step-up 211 * circuit (2) 212 * bits 0..2 in the lower nibble controls NCK, the booster clock 213 * frequency, the values are the same as for PCK in @bt1ctr. 214 * bits 4..5 in the upper nibble controls BTN, the boosting 215 * amplification for the the step-up circuit. 216 * 0 = Disable 217 * 1 = -1.5 x VDDB 218 * 2 = -2 x VDDB 219 * 3 = -2.5 x VDDB 220 * 4 = -3 x VDDB 221 * The defaults are 4 and 3 yielding 0x34 222 */ 223 u8 bt2ctr[NT35510_P1_BT2CTR_LEN]; 224 /** 225 * @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V 226 * in 1V steps, the default is 0x08 which means 15V 227 */ 228 u8 vgh[NT35510_P1_VGH_LEN]; 229 /** 230 * @bt4ctr: setting for boost power control for the VGH step-up 231 * circuit (4) 232 * bits 0..2 in the lower nibble controls HCK, the booster clock 233 * frequency, the values are the same as for PCK in @bt1ctr. 234 * bits 4..5 in the upper nibble controls BTH, the boosting 235 * amplification for the the step-up circuit. 236 * 0 = AVDD + VDDB 237 * 1 = AVDD - AVEE 238 * 2 = AVDD - AVEE + VDDB 239 * 3 = AVDD x 2 - AVEE 240 * The defaults are 4 and 3 yielding 0x34 241 */ 242 u8 bt4ctr[NT35510_P1_BT4CTR_LEN]; 243 /** 244 * @vgl: setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in 245 * 1V steps, the default is 0x08 which means -10V 246 */ 247 u8 vgl[NT35510_P1_VGL_LEN]; 248 /** 249 * @bt5ctr: setting for boost power control for the VGL step-up 250 * circuit (5) 251 * bits 0..2 in the lower nibble controls LCK, the booster clock 252 * frequency, the values are the same as for PCK in @bt1ctr. 253 * bits 4..5 in the upper nibble controls BTL, the boosting 254 * amplification for the the step-up circuit. 255 * 0 = AVEE + VCL 256 * 1 = AVEE - AVDD 257 * 2 = AVEE + VCL - AVDD 258 * 3 = AVEE x 2 - AVDD 259 * The defaults are 3 and 2 yielding 0x32 260 */ 261 u8 bt5ctr[NT35510_P1_BT5CTR_LEN]; 262 /** 263 * @vgp: setting for VGP, the positive gamma divider voltages 264 * VGMP the high voltage and VGSP the low voltage. 265 * The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0 266 * The second byte contains bit 0..7 of VGMP 267 * The third byte contains bit 0..7 of VGSP 268 * VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV 269 * VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV 270 */ 271 u8 vgp[NT35510_P1_VGP_LEN]; 272 /** 273 * @vgn: setting for VGN, the negative gamma divider voltages, 274 * same layout of bytes as @vgp. 275 */ 276 u8 vgn[NT35510_P1_VGN_LEN]; 277 /** 278 * @sdeqctr: Source driver control settings, first byte is 279 * 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and 280 * mode 2 uses three steps meaning EQS3 is not used in mode 281 * 1. Mode 2 is default. The last three parameters are EQS1, EQS2 282 * and EQS3, setting the rise time for each equalizer step: 283 * 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default 284 * is 0x07 = 3.5 us. 285 */ 286 u8 sdeqctr[NT35510_P0_SDEQCTR_LEN]; 287 /** 288 * @sdvpctr: power/voltage behaviour during vertical porch time 289 */ 290 u8 sdvpctr; 291 /** 292 * @t1: the number of pixel clocks on one scanline, range 293 * 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1 294 * clock ticks. 295 */ 296 u16 t1; 297 /** 298 * @vbp: vertical back porch toward the PANEL note: not toward 299 * the DSI host; these are separate interfaces, in from DSI host 300 * and out to the panel. 301 */ 302 u8 vbp; 303 /** 304 * @vfp: vertical front porch toward the PANEL. 305 */ 306 u8 vfp; 307 /** 308 * @psel: pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8. 309 */ 310 u8 psel; 311 /** 312 * @dpmctr12: Display timing control 12 313 * Byte 1 bit 4 selects LVGL voltage level: 0 = VGLX, 1 = VGL_REG 314 * Byte 1 bit 1 selects gate signal mode: 0 = non-overlap, 1 = overlap 315 * Byte 1 bit 0 selects output signal control R/L swap, 0 = normal 316 * 1 = swap all O->E, L->R 317 * Byte 2 is CLW delay clock for CK O/E and CKB O/E signals: 318 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps 319 * Byte 3 is FTI_H0 delay time for STP O/E signals: 320 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps 321 */ 322 u8 dpmctr12[NT35510_P0_DPMCTR12_LEN]; 323 /** 324 * @gamma_corr_pos_r: Red gamma correction parameters, positive 325 */ 326 u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN]; 327 /** 328 * @gamma_corr_pos_g: Green gamma correction parameters, positive 329 */ 330 u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN]; 331 /** 332 * @gamma_corr_pos_b: Blue gamma correction parameters, positive 333 */ 334 u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN]; 335 /** 336 * @gamma_corr_neg_r: Red gamma correction parameters, negative 337 */ 338 u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN]; 339 /** 340 * @gamma_corr_neg_g: Green gamma correction parameters, negative 341 */ 342 u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN]; 343 /** 344 * @gamma_corr_neg_b: Blue gamma correction parameters, negative 345 */ 346 u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN]; 347 }; 348 349 /** 350 * struct nt35510 - state container for the NT35510 panel 351 */ 352 struct nt35510 { 353 /** 354 * @dev: the container device 355 */ 356 struct device *dev; 357 /** 358 * @conf: the specific panel configuration, as the NT35510 359 * can be combined with many physical panels, they can have 360 * different physical dimensions and gamma correction etc, 361 * so this is stored in the config. 362 */ 363 const struct nt35510_config *conf; 364 /** 365 * @panel: the DRM panel object for the instance 366 */ 367 struct drm_panel panel; 368 /** 369 * @supplies: regulators supplying the panel 370 */ 371 struct regulator_bulk_data supplies[2]; 372 /** 373 * @reset_gpio: the reset line 374 */ 375 struct gpio_desc *reset_gpio; 376 }; 377 378 /* Manufacturer command has strictly this byte sequence */ 379 static const u8 nt35510_mauc_select_page_0[] = { 0x55, 0xAA, 0x52, 0x08, 0x00 }; 380 static const u8 nt35510_mauc_select_page_1[] = { 0x55, 0xAA, 0x52, 0x08, 0x01 }; 381 static const u8 nt35510_vgh_on[] = { 0x01 }; 382 383 static inline struct nt35510 *panel_to_nt35510(struct drm_panel *panel) 384 { 385 return container_of(panel, struct nt35510, panel); 386 } 387 388 #define NT35510_ROTATE_0_SETTING 0x02 389 #define NT35510_ROTATE_180_SETTING 0x00 390 391 static int nt35510_send_long(struct nt35510 *nt, struct mipi_dsi_device *dsi, 392 u8 cmd, u8 cmdlen, const u8 *seq) 393 { 394 const u8 *seqp = seq; 395 int cmdwritten = 0; 396 int chunk = cmdlen; 397 int ret; 398 399 if (chunk > 15) 400 chunk = 15; 401 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); 402 if (ret < 0) { 403 DRM_DEV_ERROR(nt->dev, 404 "error sending DCS command seq cmd %02x\n", 405 cmd); 406 return ret; 407 } 408 cmdwritten += chunk; 409 seqp += chunk; 410 411 while (cmdwritten < cmdlen) { 412 chunk = cmdlen - cmdwritten; 413 if (chunk > 15) 414 chunk = 15; 415 ret = mipi_dsi_generic_write(dsi, seqp, chunk); 416 if (ret < 0) { 417 DRM_DEV_ERROR(nt->dev, 418 "error sending generic write seq %02x\n", 419 cmd); 420 return ret; 421 } 422 cmdwritten += chunk; 423 seqp += chunk; 424 } 425 DRM_DEV_DEBUG(nt->dev, "sent command %02x %02x bytes\n", 426 cmd, cmdlen); 427 return 0; 428 } 429 430 static int nt35510_read_id(struct nt35510 *nt) 431 { 432 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 433 u8 id1, id2, id3; 434 int ret; 435 436 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID1, &id1, 1); 437 if (ret < 0) { 438 DRM_DEV_ERROR(nt->dev, "could not read MTP ID1\n"); 439 return ret; 440 } 441 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID2, &id2, 1); 442 if (ret < 0) { 443 DRM_DEV_ERROR(nt->dev, "could not read MTP ID2\n"); 444 return ret; 445 } 446 ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID3, &id3, 1); 447 if (ret < 0) { 448 DRM_DEV_ERROR(nt->dev, "could not read MTP ID3\n"); 449 return ret; 450 } 451 452 /* 453 * Multi-Time Programmable (?) memory contains manufacturer 454 * ID (e.g. Hydis 0x55), driver ID (e.g. NT35510 0xc0) and 455 * version. 456 */ 457 DRM_DEV_INFO(nt->dev, 458 "MTP ID manufacturer: %02x version: %02x driver: %02x\n", 459 id1, id2, id3); 460 461 return 0; 462 } 463 464 /** 465 * nt35510_setup_power() - set up power config in page 1 466 * @nt: the display instance to set up 467 */ 468 static int nt35510_setup_power(struct nt35510 *nt) 469 { 470 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 471 int ret; 472 473 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVDD, 474 NT35510_P1_AVDD_LEN, 475 nt->conf->avdd); 476 if (ret) 477 return ret; 478 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT1CTR, 479 NT35510_P1_BT1CTR_LEN, 480 nt->conf->bt1ctr); 481 if (ret) 482 return ret; 483 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVEE, 484 NT35510_P1_AVEE_LEN, 485 nt->conf->avee); 486 if (ret) 487 return ret; 488 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT2CTR, 489 NT35510_P1_BT2CTR_LEN, 490 nt->conf->bt2ctr); 491 if (ret) 492 return ret; 493 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGH, 494 NT35510_P1_VGH_LEN, 495 nt->conf->vgh); 496 if (ret) 497 return ret; 498 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT4CTR, 499 NT35510_P1_BT4CTR_LEN, 500 nt->conf->bt4ctr); 501 if (ret) 502 return ret; 503 ret = nt35510_send_long(nt, dsi, NT35510_P1_VGHCTR, 504 ARRAY_SIZE(nt35510_vgh_on), 505 nt35510_vgh_on); 506 if (ret) 507 return ret; 508 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGL, 509 NT35510_P1_VGL_LEN, 510 nt->conf->vgl); 511 if (ret) 512 return ret; 513 ret = nt35510_send_long(nt, dsi, NT35510_P1_BT5CTR, 514 NT35510_P1_BT5CTR_LEN, 515 nt->conf->bt5ctr); 516 if (ret) 517 return ret; 518 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGP, 519 NT35510_P1_VGP_LEN, 520 nt->conf->vgp); 521 if (ret) 522 return ret; 523 ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGN, 524 NT35510_P1_VGN_LEN, 525 nt->conf->vgn); 526 if (ret) 527 return ret; 528 529 /* Typically 10 ms */ 530 usleep_range(10000, 20000); 531 532 return 0; 533 } 534 535 /** 536 * nt35510_setup_display() - set up display config in page 0 537 * @nt: the display instance to set up 538 */ 539 static int nt35510_setup_display(struct nt35510 *nt) 540 { 541 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 542 const struct nt35510_config *conf = nt->conf; 543 u8 dopctr[NT35510_P0_DOPCTR_LEN]; 544 u8 gseqctr[NT35510_P0_GSEQCTR_LEN]; 545 u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN]; 546 /* FIXME: set up any rotation (assume none for now) */ 547 u8 addr_mode = NT35510_ROTATE_0_SETTING; 548 u8 val; 549 int ret; 550 551 /* Enable TE, EoTP and RGB pixel format */ 552 dopctr[0] = NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP | 553 NT35510_DOPCTR_0_N565; 554 dopctr[1] = NT35510_DOPCTR_1_CTB; 555 ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR, 556 NT35510_P0_DOPCTR_LEN, 557 dopctr); 558 if (ret) 559 return ret; 560 561 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode, 562 sizeof(addr_mode)); 563 if (ret < 0) 564 return ret; 565 566 /* 567 * Source data hold time, default 0x05 = 2.5us 568 * 0x00..0x3F = 0 .. 31.5us in steps of 0.5us 569 * 0x0A = 5us 570 */ 571 val = 0x0A; 572 ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val, 573 sizeof(val)); 574 if (ret < 0) 575 return ret; 576 577 /* EQ control for gate signals, 0x00 = 0 us */ 578 gseqctr[0] = 0x00; 579 gseqctr[1] = 0x00; 580 ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR, 581 NT35510_P0_GSEQCTR_LEN, 582 gseqctr); 583 if (ret) 584 return ret; 585 586 ret = nt35510_send_long(nt, dsi, NT35510_P0_SDEQCTR, 587 NT35510_P0_SDEQCTR_LEN, 588 conf->sdeqctr); 589 if (ret) 590 return ret; 591 592 ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDVPCTR, 593 &conf->sdvpctr, 1); 594 if (ret < 0) 595 return ret; 596 597 /* 598 * Display timing control for active and idle off mode: 599 * the first byte contains 600 * the two high bits of T1A and second byte the low 8 bits, and 601 * the valid range is 0x100 (257) to 0x3ff (1023) representing 602 * 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel 603 * clock this covers the range of 12.90us .. 51.20us in steps of 604 * 0.05us, the default is 0x184 (388) representing 389 ticks. 605 * The third byte is VBPDA, vertical back porch display active 606 * and the fourth VFPDA, vertical front porch display active, 607 * both given in number of scanlines in the range 0x02..0xff 608 * for 2..255 scanlines. The fifth byte is 2 bits selecting 609 * PSEL for active and idle off mode, how much the 20MHz clock 610 * is divided by 0..3. This needs to be adjusted to get the right 611 * frame rate. 612 */ 613 dpfrctr[0] = (conf->t1 >> 8) & 0xFF; 614 dpfrctr[1] = conf->t1 & 0xFF; 615 /* Vertical back porch */ 616 dpfrctr[2] = conf->vbp; 617 /* Vertical front porch */ 618 dpfrctr[3] = conf->vfp; 619 dpfrctr[4] = conf->psel; 620 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR1, 621 NT35510_P0_DPFRCTR1_LEN, 622 dpfrctr); 623 if (ret) 624 return ret; 625 /* For idle and partial idle off mode we decrease front porch by one */ 626 dpfrctr[3]--; 627 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR2, 628 NT35510_P0_DPFRCTR2_LEN, 629 dpfrctr); 630 if (ret) 631 return ret; 632 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR3, 633 NT35510_P0_DPFRCTR3_LEN, 634 dpfrctr); 635 if (ret) 636 return ret; 637 638 /* Enable TE on vblank */ 639 ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); 640 if (ret) 641 return ret; 642 643 /* Turn on the pads? */ 644 ret = nt35510_send_long(nt, dsi, NT35510_P0_DPMCTR12, 645 NT35510_P0_DPMCTR12_LEN, 646 conf->dpmctr12); 647 if (ret) 648 return ret; 649 650 return 0; 651 } 652 653 static int nt35510_set_brightness(struct backlight_device *bl) 654 { 655 struct nt35510 *nt = bl_get_data(bl); 656 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 657 u8 brightness = bl->props.brightness; 658 int ret; 659 660 DRM_DEV_DEBUG(nt->dev, "set brightness %d\n", brightness); 661 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 662 &brightness, 663 sizeof(brightness)); 664 if (ret < 0) 665 return ret; 666 667 return 0; 668 } 669 670 static const struct backlight_ops nt35510_bl_ops = { 671 .update_status = nt35510_set_brightness, 672 }; 673 674 /* 675 * This power-on sequence 676 */ 677 static int nt35510_power_on(struct nt35510 *nt) 678 { 679 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 680 int ret; 681 682 ret = regulator_bulk_enable(ARRAY_SIZE(nt->supplies), nt->supplies); 683 if (ret < 0) { 684 dev_err(nt->dev, "unable to enable regulators\n"); 685 return ret; 686 } 687 688 /* Toggle RESET in accordance with datasheet page 370 */ 689 if (nt->reset_gpio) { 690 gpiod_set_value(nt->reset_gpio, 1); 691 /* Active min 10 us according to datasheet, let's say 20 */ 692 usleep_range(20, 1000); 693 gpiod_set_value(nt->reset_gpio, 0); 694 /* 695 * 5 ms during sleep mode, 120 ms during sleep out mode 696 * according to datasheet, let's use 120-140 ms. 697 */ 698 usleep_range(120000, 140000); 699 } 700 701 ret = nt35510_read_id(nt); 702 if (ret) 703 return ret; 704 705 /* Set up stuff in manufacturer control, page 1 */ 706 ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, 707 ARRAY_SIZE(nt35510_mauc_select_page_1), 708 nt35510_mauc_select_page_1); 709 if (ret) 710 return ret; 711 712 ret = nt35510_setup_power(nt); 713 if (ret) 714 return ret; 715 716 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS, 717 NT35510_P1_GAMMA_LEN, 718 nt->conf->gamma_corr_pos_r); 719 if (ret) 720 return ret; 721 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS, 722 NT35510_P1_GAMMA_LEN, 723 nt->conf->gamma_corr_pos_g); 724 if (ret) 725 return ret; 726 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS, 727 NT35510_P1_GAMMA_LEN, 728 nt->conf->gamma_corr_pos_b); 729 if (ret) 730 return ret; 731 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG, 732 NT35510_P1_GAMMA_LEN, 733 nt->conf->gamma_corr_neg_r); 734 if (ret) 735 return ret; 736 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG, 737 NT35510_P1_GAMMA_LEN, 738 nt->conf->gamma_corr_neg_g); 739 if (ret) 740 return ret; 741 ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG, 742 NT35510_P1_GAMMA_LEN, 743 nt->conf->gamma_corr_neg_b); 744 if (ret) 745 return ret; 746 747 /* Set up stuff in manufacturer control, page 0 */ 748 ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR, 749 ARRAY_SIZE(nt35510_mauc_select_page_0), 750 nt35510_mauc_select_page_0); 751 if (ret) 752 return ret; 753 754 ret = nt35510_setup_display(nt); 755 if (ret) 756 return ret; 757 758 return 0; 759 } 760 761 static int nt35510_power_off(struct nt35510 *nt) 762 { 763 int ret; 764 765 ret = regulator_bulk_disable(ARRAY_SIZE(nt->supplies), nt->supplies); 766 if (ret) 767 return ret; 768 769 if (nt->reset_gpio) 770 gpiod_set_value(nt->reset_gpio, 1); 771 772 return 0; 773 } 774 775 static int nt35510_unprepare(struct drm_panel *panel) 776 { 777 struct nt35510 *nt = panel_to_nt35510(panel); 778 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 779 int ret; 780 781 ret = mipi_dsi_dcs_set_display_off(dsi); 782 if (ret) { 783 DRM_DEV_ERROR(nt->dev, "failed to turn display off (%d)\n", 784 ret); 785 return ret; 786 } 787 usleep_range(10000, 20000); 788 789 /* Enter sleep mode */ 790 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 791 if (ret) { 792 DRM_DEV_ERROR(nt->dev, "failed to enter sleep mode (%d)\n", 793 ret); 794 return ret; 795 } 796 797 /* Wait 4 frames, how much is that 5ms in the vendor driver */ 798 usleep_range(5000, 10000); 799 800 ret = nt35510_power_off(nt); 801 if (ret) 802 return ret; 803 804 return 0; 805 } 806 807 static int nt35510_prepare(struct drm_panel *panel) 808 { 809 struct nt35510 *nt = panel_to_nt35510(panel); 810 struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev); 811 int ret; 812 813 ret = nt35510_power_on(nt); 814 if (ret) 815 return ret; 816 817 /* Exit sleep mode */ 818 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 819 if (ret) { 820 DRM_DEV_ERROR(nt->dev, "failed to exit sleep mode (%d)\n", 821 ret); 822 return ret; 823 } 824 /* Up to 120 ms */ 825 usleep_range(120000, 150000); 826 827 ret = mipi_dsi_dcs_set_display_on(dsi); 828 if (ret) { 829 DRM_DEV_ERROR(nt->dev, "failed to turn display on (%d)\n", 830 ret); 831 return ret; 832 } 833 /* Some 10 ms */ 834 usleep_range(10000, 20000); 835 836 return 0; 837 } 838 839 static int nt35510_get_modes(struct drm_panel *panel, 840 struct drm_connector *connector) 841 { 842 struct nt35510 *nt = panel_to_nt35510(panel); 843 struct drm_display_mode *mode; 844 struct drm_display_info *info; 845 846 info = &connector->display_info; 847 info->width_mm = nt->conf->width_mm; 848 info->height_mm = nt->conf->height_mm; 849 mode = drm_mode_duplicate(connector->dev, &nt->conf->mode); 850 if (!mode) { 851 DRM_ERROR("bad mode or failed to add mode\n"); 852 return -EINVAL; 853 } 854 drm_mode_set_name(mode); 855 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 856 857 mode->width_mm = nt->conf->width_mm; 858 mode->height_mm = nt->conf->height_mm; 859 drm_mode_probed_add(connector, mode); 860 861 return 1; /* Number of modes */ 862 } 863 864 static const struct drm_panel_funcs nt35510_drm_funcs = { 865 .unprepare = nt35510_unprepare, 866 .prepare = nt35510_prepare, 867 .get_modes = nt35510_get_modes, 868 }; 869 870 static int nt35510_probe(struct mipi_dsi_device *dsi) 871 { 872 struct device *dev = &dsi->dev; 873 struct nt35510 *nt; 874 int ret; 875 876 nt = devm_kzalloc(dev, sizeof(struct nt35510), GFP_KERNEL); 877 if (!nt) 878 return -ENOMEM; 879 mipi_dsi_set_drvdata(dsi, nt); 880 nt->dev = dev; 881 882 dsi->lanes = 2; 883 dsi->format = MIPI_DSI_FMT_RGB888; 884 /* 885 * Datasheet suggests max HS rate for NT35510 is 250 MHz 886 * (period time 4ns, see figure 7.6.4 page 365) and max LP rate is 887 * 20 MHz (period time 50ns, see figure 7.6.6. page 366). 888 * However these frequencies appear in source code for the Hydis 889 * HVA40WV1 panel and setting up the LP frequency makes the panel 890 * not work. 891 * 892 * TODO: if other panels prove to be closer to the datasheet, 893 * maybe make this a per-panel config in struct nt35510_config? 894 */ 895 dsi->hs_rate = 349440000; 896 dsi->lp_rate = 9600000; 897 dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS | 898 MIPI_DSI_MODE_EOT_PACKET; 899 900 /* 901 * Every new incarnation of this display must have a unique 902 * data entry for the system in this driver. 903 */ 904 nt->conf = of_device_get_match_data(dev); 905 if (!nt->conf) { 906 dev_err(dev, "missing device configuration\n"); 907 return -ENODEV; 908 } 909 910 nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */ 911 nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */ 912 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies), 913 nt->supplies); 914 if (ret < 0) 915 return ret; 916 ret = regulator_set_voltage(nt->supplies[0].consumer, 917 2300000, 4800000); 918 if (ret) 919 return ret; 920 ret = regulator_set_voltage(nt->supplies[1].consumer, 921 1650000, 3300000); 922 if (ret) 923 return ret; 924 925 nt->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); 926 if (IS_ERR(nt->reset_gpio)) { 927 dev_err(dev, "error getting RESET GPIO\n"); 928 return PTR_ERR(nt->reset_gpio); 929 } 930 931 drm_panel_init(&nt->panel, dev, &nt35510_drm_funcs, 932 DRM_MODE_CONNECTOR_DSI); 933 934 /* 935 * First, try to locate an external backlight (such as on GPIO) 936 * if this fails, assume we will want to use the internal backlight 937 * control. 938 */ 939 ret = drm_panel_of_backlight(&nt->panel); 940 if (ret) { 941 dev_err(dev, "error getting external backlight %d\n", ret); 942 return ret; 943 } 944 if (!nt->panel.backlight) { 945 struct backlight_device *bl; 946 947 bl = devm_backlight_device_register(dev, "nt35510", dev, nt, 948 &nt35510_bl_ops, NULL); 949 if (IS_ERR(bl)) { 950 DRM_DEV_ERROR(dev, "failed to register backlight device\n"); 951 return PTR_ERR(bl); 952 } 953 bl->props.max_brightness = 255; 954 bl->props.brightness = 255; 955 bl->props.power = FB_BLANK_POWERDOWN; 956 nt->panel.backlight = bl; 957 } 958 959 ret = drm_panel_add(&nt->panel); 960 if (ret < 0) 961 return ret; 962 963 ret = mipi_dsi_attach(dsi); 964 if (ret < 0) 965 drm_panel_remove(&nt->panel); 966 967 return 0; 968 } 969 970 static int nt35510_remove(struct mipi_dsi_device *dsi) 971 { 972 struct nt35510 *nt = mipi_dsi_get_drvdata(dsi); 973 int ret; 974 975 mipi_dsi_detach(dsi); 976 /* Power off */ 977 ret = nt35510_power_off(nt); 978 drm_panel_remove(&nt->panel); 979 980 return ret; 981 } 982 983 /* 984 * These gamma correction values are 10bit tuples, so only bits 0 and 1 is 985 * ever used in the first byte. They form a positive and negative gamma 986 * correction curve for each color, values must be strictly higher for each 987 * step on the curve. As can be seen these default curves goes from 0x0001 988 * to 0x03FE. 989 */ 990 #define NT35510_GAMMA_POS_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \ 991 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \ 992 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \ 993 0x83, 0x02, 0x78, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \ 994 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \ 995 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE 996 997 #define NT35510_GAMMA_NEG_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \ 998 0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \ 999 0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \ 1000 0x43, 0x02, 0x50, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \ 1001 0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \ 1002 0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE 1003 1004 /* 1005 * The Hydis HVA40WV1 panel 1006 */ 1007 static const struct nt35510_config nt35510_hydis_hva40wv1 = { 1008 .width_mm = 52, 1009 .height_mm = 86, 1010 /** 1011 * As the Hydis panel is used in command mode, the porches etc 1012 * are settings programmed internally into the NT35510 controller 1013 * and generated toward the physical display. As the panel is not 1014 * used in video mode, these are not really exposed to the DSI 1015 * host. 1016 * 1017 * Display frame rate control: 1018 * Frame rate = (20 MHz / 1) / (389 * (7 + 50 + 800)) ~= 60 Hz 1019 */ 1020 .mode = { 1021 /* The internal pixel clock of the NT35510 is 20 MHz */ 1022 .clock = 20000, 1023 .hdisplay = 480, 1024 .hsync_start = 480 + 2, /* HFP = 2 */ 1025 .hsync_end = 480 + 2 + 0, /* HSync = 0 */ 1026 .htotal = 480 + 2 + 0 + 5, /* HFP = 5 */ 1027 .vdisplay = 800, 1028 .vsync_start = 800 + 2, /* VFP = 2 */ 1029 .vsync_end = 800 + 2 + 0, /* VSync = 0 */ 1030 .vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */ 1031 .flags = 0, 1032 }, 1033 /* 0x09: AVDD = 5.6V */ 1034 .avdd = { 0x09, 0x09, 0x09 }, 1035 /* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */ 1036 .bt1ctr = { 0x34, 0x34, 0x34 }, 1037 /* 0x09: AVEE = -5.6V */ 1038 .avee = { 0x09, 0x09, 0x09 }, 1039 /* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */ 1040 .bt2ctr = { 0x24, 0x24, 0x24 }, 1041 /* 0x05 = 12V */ 1042 .vgh = { 0x05, 0x05, 0x05 }, 1043 /* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */ 1044 .bt4ctr = { 0x24, 0x24, 0x24 }, 1045 /* 0x0B = -13V */ 1046 .vgl = { 0x0B, 0x0B, 0x0B }, 1047 /* 0x24: LCKA = Hsync, VGL = AVDD + VCL - AVDD */ 1048 .bt5ctr = { 0x24, 0x24, 0x24 }, 1049 /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ 1050 .vgp = { 0x00, 0xA3, 0x00 }, 1051 /* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */ 1052 .vgn = { 0x00, 0xA3, 0x00 }, 1053 /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */ 1054 .sdeqctr = { 0x01, 0x05, 0x05, 0x05 }, 1055 /* SDVPCTR: Normal operation off color during v porch */ 1056 .sdvpctr = 0x01, 1057 /* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */ 1058 .t1 = 0x0184, 1059 /* VBP: vertical back porch toward the panel */ 1060 .vbp = 7, 1061 /* VFP: vertical front porch toward the panel */ 1062 .vfp = 50, 1063 /* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */ 1064 .psel = 0, 1065 /* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */ 1066 .dpmctr12 = { 0x03, 0x00, 0x00, }, 1067 /* Default gamma correction values */ 1068 .gamma_corr_pos_r = { NT35510_GAMMA_POS_DEFAULT }, 1069 .gamma_corr_pos_g = { NT35510_GAMMA_POS_DEFAULT }, 1070 .gamma_corr_pos_b = { NT35510_GAMMA_POS_DEFAULT }, 1071 .gamma_corr_neg_r = { NT35510_GAMMA_NEG_DEFAULT }, 1072 .gamma_corr_neg_g = { NT35510_GAMMA_NEG_DEFAULT }, 1073 .gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT }, 1074 }; 1075 1076 static const struct of_device_id nt35510_of_match[] = { 1077 { 1078 .compatible = "hydis,hva40wv1", 1079 .data = &nt35510_hydis_hva40wv1, 1080 }, 1081 { } 1082 }; 1083 MODULE_DEVICE_TABLE(of, nt35510_of_match); 1084 1085 static struct mipi_dsi_driver nt35510_driver = { 1086 .probe = nt35510_probe, 1087 .remove = nt35510_remove, 1088 .driver = { 1089 .name = "panel-novatek-nt35510", 1090 .of_match_table = nt35510_of_match, 1091 }, 1092 }; 1093 module_mipi_dsi_driver(nt35510_driver); 1094 1095 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1096 MODULE_DESCRIPTION("NT35510-based panel driver"); 1097 MODULE_LICENSE("GPL v2"); 1098