1 /* 2 * drivers/gpu/drm/omapdrm/omap_irq.c 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * Author: Rob Clark <rob.clark@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "omap_drv.h" 21 22 struct omap_irq_wait { 23 struct list_head node; 24 wait_queue_head_t wq; 25 uint32_t irqmask; 26 int count; 27 }; 28 29 /* call with wait_lock and dispc runtime held */ 30 static void omap_irq_update(struct drm_device *dev) 31 { 32 struct omap_drm_private *priv = dev->dev_private; 33 struct omap_irq_wait *wait; 34 uint32_t irqmask = priv->irq_mask; 35 36 assert_spin_locked(&priv->wait_lock); 37 38 list_for_each_entry(wait, &priv->wait_list, node) 39 irqmask |= wait->irqmask; 40 41 DBG("irqmask=%08x", irqmask); 42 43 priv->dispc_ops->write_irqenable(irqmask); 44 priv->dispc_ops->read_irqenable(); /* flush posted write */ 45 } 46 47 static void omap_irq_wait_handler(struct omap_irq_wait *wait) 48 { 49 wait->count--; 50 wake_up(&wait->wq); 51 } 52 53 struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, 54 uint32_t irqmask, int count) 55 { 56 struct omap_drm_private *priv = dev->dev_private; 57 struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); 58 unsigned long flags; 59 60 init_waitqueue_head(&wait->wq); 61 wait->irqmask = irqmask; 62 wait->count = count; 63 64 spin_lock_irqsave(&priv->wait_lock, flags); 65 list_add(&wait->node, &priv->wait_list); 66 omap_irq_update(dev); 67 spin_unlock_irqrestore(&priv->wait_lock, flags); 68 69 return wait; 70 } 71 72 int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, 73 unsigned long timeout) 74 { 75 struct omap_drm_private *priv = dev->dev_private; 76 unsigned long flags; 77 int ret; 78 79 ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout); 80 81 spin_lock_irqsave(&priv->wait_lock, flags); 82 list_del(&wait->node); 83 omap_irq_update(dev); 84 spin_unlock_irqrestore(&priv->wait_lock, flags); 85 86 kfree(wait); 87 88 return ret == 0 ? -1 : 0; 89 } 90 91 /** 92 * enable_vblank - enable vblank interrupt events 93 * @dev: DRM device 94 * @pipe: which irq to enable 95 * 96 * Enable vblank interrupts for @crtc. If the device doesn't have 97 * a hardware vblank counter, this routine should be a no-op, since 98 * interrupts will have to stay on to keep the count accurate. 99 * 100 * RETURNS 101 * Zero on success, appropriate errno if the given @crtc's vblank 102 * interrupt cannot be enabled. 103 */ 104 int omap_irq_enable_vblank(struct drm_crtc *crtc) 105 { 106 struct drm_device *dev = crtc->dev; 107 struct omap_drm_private *priv = dev->dev_private; 108 unsigned long flags; 109 enum omap_channel channel = omap_crtc_channel(crtc); 110 111 DBG("dev=%p, crtc=%u", dev, channel); 112 113 spin_lock_irqsave(&priv->wait_lock, flags); 114 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel); 115 omap_irq_update(dev); 116 spin_unlock_irqrestore(&priv->wait_lock, flags); 117 118 return 0; 119 } 120 121 /** 122 * disable_vblank - disable vblank interrupt events 123 * @dev: DRM device 124 * @pipe: which irq to enable 125 * 126 * Disable vblank interrupts for @crtc. If the device doesn't have 127 * a hardware vblank counter, this routine should be a no-op, since 128 * interrupts will have to stay on to keep the count accurate. 129 */ 130 void omap_irq_disable_vblank(struct drm_crtc *crtc) 131 { 132 struct drm_device *dev = crtc->dev; 133 struct omap_drm_private *priv = dev->dev_private; 134 unsigned long flags; 135 enum omap_channel channel = omap_crtc_channel(crtc); 136 137 DBG("dev=%p, crtc=%u", dev, channel); 138 139 spin_lock_irqsave(&priv->wait_lock, flags); 140 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel); 141 omap_irq_update(dev); 142 spin_unlock_irqrestore(&priv->wait_lock, flags); 143 } 144 145 static void omap_irq_fifo_underflow(struct omap_drm_private *priv, 146 u32 irqstatus) 147 { 148 static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL, 149 DEFAULT_RATELIMIT_BURST); 150 static const struct { 151 const char *name; 152 u32 mask; 153 } sources[] = { 154 { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW }, 155 { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW }, 156 { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW }, 157 { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW }, 158 }; 159 160 const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW 161 | DISPC_IRQ_VID1_FIFO_UNDERFLOW 162 | DISPC_IRQ_VID2_FIFO_UNDERFLOW 163 | DISPC_IRQ_VID3_FIFO_UNDERFLOW; 164 unsigned int i; 165 166 spin_lock(&priv->wait_lock); 167 irqstatus &= priv->irq_mask & mask; 168 spin_unlock(&priv->wait_lock); 169 170 if (!irqstatus) 171 return; 172 173 if (!__ratelimit(&_rs)) 174 return; 175 176 DRM_ERROR("FIFO underflow on "); 177 178 for (i = 0; i < ARRAY_SIZE(sources); ++i) { 179 if (sources[i].mask & irqstatus) 180 pr_cont("%s ", sources[i].name); 181 } 182 183 pr_cont("(0x%08x)\n", irqstatus); 184 } 185 186 static void omap_irq_ocp_error_handler(u32 irqstatus) 187 { 188 if (!(irqstatus & DISPC_IRQ_OCP_ERR)) 189 return; 190 191 DRM_ERROR("OCP error\n"); 192 } 193 194 static irqreturn_t omap_irq_handler(int irq, void *arg) 195 { 196 struct drm_device *dev = (struct drm_device *) arg; 197 struct omap_drm_private *priv = dev->dev_private; 198 struct omap_irq_wait *wait, *n; 199 unsigned long flags; 200 unsigned int id; 201 u32 irqstatus; 202 203 irqstatus = priv->dispc_ops->read_irqstatus(); 204 priv->dispc_ops->clear_irqstatus(irqstatus); 205 priv->dispc_ops->read_irqstatus(); /* flush posted write */ 206 207 VERB("irqs: %08x", irqstatus); 208 209 for (id = 0; id < priv->num_crtcs; id++) { 210 struct drm_crtc *crtc = priv->crtcs[id]; 211 enum omap_channel channel = omap_crtc_channel(crtc); 212 213 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) { 214 drm_handle_vblank(dev, id); 215 omap_crtc_vblank_irq(crtc); 216 } 217 218 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel)) 219 omap_crtc_error_irq(crtc, irqstatus); 220 } 221 222 omap_irq_ocp_error_handler(irqstatus); 223 omap_irq_fifo_underflow(priv, irqstatus); 224 225 spin_lock_irqsave(&priv->wait_lock, flags); 226 list_for_each_entry_safe(wait, n, &priv->wait_list, node) { 227 if (wait->irqmask & irqstatus) 228 omap_irq_wait_handler(wait); 229 } 230 spin_unlock_irqrestore(&priv->wait_lock, flags); 231 232 return IRQ_HANDLED; 233 } 234 235 static const u32 omap_underflow_irqs[] = { 236 [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW, 237 [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW, 238 [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW, 239 [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW, 240 }; 241 242 /* 243 * We need a special version, instead of just using drm_irq_install(), 244 * because we need to register the irq via omapdss. Once omapdss and 245 * omapdrm are merged together we can assign the dispc hwmod data to 246 * ourselves and drop these and just use drm_irq_{install,uninstall}() 247 */ 248 249 int omap_drm_irq_install(struct drm_device *dev) 250 { 251 struct omap_drm_private *priv = dev->dev_private; 252 unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(); 253 unsigned int max_planes; 254 unsigned int i; 255 int ret; 256 257 spin_lock_init(&priv->wait_lock); 258 INIT_LIST_HEAD(&priv->wait_list); 259 260 priv->irq_mask = DISPC_IRQ_OCP_ERR; 261 262 max_planes = min(ARRAY_SIZE(priv->planes), 263 ARRAY_SIZE(omap_underflow_irqs)); 264 for (i = 0; i < max_planes; ++i) { 265 if (priv->planes[i]) 266 priv->irq_mask |= omap_underflow_irqs[i]; 267 } 268 269 for (i = 0; i < num_mgrs; ++i) 270 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i); 271 272 priv->dispc_ops->runtime_get(); 273 priv->dispc_ops->clear_irqstatus(0xffffffff); 274 priv->dispc_ops->runtime_put(); 275 276 ret = priv->dispc_ops->request_irq(omap_irq_handler, dev); 277 if (ret < 0) 278 return ret; 279 280 dev->irq_enabled = true; 281 282 return 0; 283 } 284 285 void omap_drm_irq_uninstall(struct drm_device *dev) 286 { 287 struct omap_drm_private *priv = dev->dev_private; 288 289 if (!dev->irq_enabled) 290 return; 291 292 dev->irq_enabled = false; 293 294 priv->dispc_ops->free_irq(dev); 295 } 296