1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 4 * Author: Rob Clark <rob@ti.com> 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/platform_device.h> 9 #include <linux/sort.h> 10 #include <linux/sys_soc.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_bridge.h> 15 #include <drm/drm_bridge_connector.h> 16 #include <drm/drm_drv.h> 17 #include <drm/drm_fb_helper.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_ioctl.h> 20 #include <drm/drm_panel.h> 21 #include <drm/drm_prime.h> 22 #include <drm/drm_probe_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include "omap_dmm_tiler.h" 26 #include "omap_drv.h" 27 28 #define DRIVER_NAME MODULE_NAME 29 #define DRIVER_DESC "OMAP DRM" 30 #define DRIVER_DATE "20110917" 31 #define DRIVER_MAJOR 1 32 #define DRIVER_MINOR 0 33 #define DRIVER_PATCHLEVEL 0 34 35 /* 36 * mode config funcs 37 */ 38 39 /* Notes about mapping DSS and DRM entities: 40 * CRTC: overlay 41 * encoder: manager.. with some extension to allow one primary CRTC 42 * and zero or more video CRTC's to be mapped to one encoder? 43 * connector: dssdev.. manager can be attached/detached from different 44 * devices 45 */ 46 47 static void omap_atomic_wait_for_completion(struct drm_device *dev, 48 struct drm_atomic_state *old_state) 49 { 50 struct drm_crtc_state *new_crtc_state; 51 struct drm_crtc *crtc; 52 unsigned int i; 53 int ret; 54 55 for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) { 56 if (!new_crtc_state->active) 57 continue; 58 59 ret = omap_crtc_wait_pending(crtc); 60 61 if (!ret) 62 dev_warn(dev->dev, 63 "atomic complete timeout (pipe %u)!\n", i); 64 } 65 } 66 67 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state) 68 { 69 struct drm_device *dev = old_state->dev; 70 struct omap_drm_private *priv = dev->dev_private; 71 72 priv->dispc_ops->runtime_get(priv->dispc); 73 74 /* Apply the atomic update. */ 75 drm_atomic_helper_commit_modeset_disables(dev, old_state); 76 77 if (priv->omaprev != 0x3430) { 78 /* With the current dss dispc implementation we have to enable 79 * the new modeset before we can commit planes. The dispc ovl 80 * configuration relies on the video mode configuration been 81 * written into the HW when the ovl configuration is 82 * calculated. 83 * 84 * This approach is not ideal because after a mode change the 85 * plane update is executed only after the first vblank 86 * interrupt. The dispc implementation should be fixed so that 87 * it is able use uncommitted drm state information. 88 */ 89 drm_atomic_helper_commit_modeset_enables(dev, old_state); 90 omap_atomic_wait_for_completion(dev, old_state); 91 92 drm_atomic_helper_commit_planes(dev, old_state, 0); 93 94 drm_atomic_helper_commit_hw_done(old_state); 95 } else { 96 /* 97 * OMAP3 DSS seems to have issues with the work-around above, 98 * resulting in endless sync losts if a crtc is enabled without 99 * a plane. For now, skip the WA for OMAP3. 100 */ 101 drm_atomic_helper_commit_planes(dev, old_state, 0); 102 103 drm_atomic_helper_commit_modeset_enables(dev, old_state); 104 105 drm_atomic_helper_commit_hw_done(old_state); 106 } 107 108 /* 109 * Wait for completion of the page flips to ensure that old buffers 110 * can't be touched by the hardware anymore before cleaning up planes. 111 */ 112 omap_atomic_wait_for_completion(dev, old_state); 113 114 drm_atomic_helper_cleanup_planes(dev, old_state); 115 116 priv->dispc_ops->runtime_put(priv->dispc); 117 } 118 119 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = { 120 .atomic_commit_tail = omap_atomic_commit_tail, 121 }; 122 123 static const struct drm_mode_config_funcs omap_mode_config_funcs = { 124 .fb_create = omap_framebuffer_create, 125 .output_poll_changed = drm_fb_helper_output_poll_changed, 126 .atomic_check = drm_atomic_helper_check, 127 .atomic_commit = drm_atomic_helper_commit, 128 }; 129 130 static void omap_disconnect_pipelines(struct drm_device *ddev) 131 { 132 struct omap_drm_private *priv = ddev->dev_private; 133 unsigned int i; 134 135 for (i = 0; i < priv->num_pipes; i++) { 136 struct omap_drm_pipeline *pipe = &priv->pipes[i]; 137 138 omapdss_device_disconnect(NULL, pipe->output); 139 140 omapdss_device_put(pipe->output); 141 pipe->output = NULL; 142 } 143 144 memset(&priv->channels, 0, sizeof(priv->channels)); 145 146 priv->num_pipes = 0; 147 } 148 149 static int omap_connect_pipelines(struct drm_device *ddev) 150 { 151 struct omap_drm_private *priv = ddev->dev_private; 152 struct omap_dss_device *output = NULL; 153 int r; 154 155 for_each_dss_output(output) { 156 r = omapdss_device_connect(priv->dss, NULL, output); 157 if (r == -EPROBE_DEFER) { 158 omapdss_device_put(output); 159 return r; 160 } else if (r) { 161 dev_warn(output->dev, "could not connect output %s\n", 162 output->name); 163 } else { 164 struct omap_drm_pipeline *pipe; 165 166 pipe = &priv->pipes[priv->num_pipes++]; 167 pipe->output = omapdss_device_get(output); 168 169 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) { 170 /* To balance the 'for_each_dss_output' loop */ 171 omapdss_device_put(output); 172 break; 173 } 174 } 175 } 176 177 return 0; 178 } 179 180 static int omap_compare_pipelines(const void *a, const void *b) 181 { 182 const struct omap_drm_pipeline *pipe1 = a; 183 const struct omap_drm_pipeline *pipe2 = b; 184 185 if (pipe1->alias_id > pipe2->alias_id) 186 return 1; 187 else if (pipe1->alias_id < pipe2->alias_id) 188 return -1; 189 return 0; 190 } 191 192 static int omap_modeset_init_properties(struct drm_device *dev) 193 { 194 struct omap_drm_private *priv = dev->dev_private; 195 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); 196 197 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 198 num_planes - 1); 199 if (!priv->zorder_prop) 200 return -ENOMEM; 201 202 return 0; 203 } 204 205 static int omap_display_id(struct omap_dss_device *output) 206 { 207 struct device_node *node = NULL; 208 209 if (output->next) { 210 struct omap_dss_device *display = output; 211 212 while (display->next) 213 display = display->next; 214 215 node = display->dev->of_node; 216 } else if (output->bridge) { 217 struct drm_bridge *bridge = output->bridge; 218 219 while (drm_bridge_get_next_bridge(bridge)) 220 bridge = drm_bridge_get_next_bridge(bridge); 221 222 node = bridge->of_node; 223 } 224 225 return node ? of_alias_get_id(node, "display") : -ENODEV; 226 } 227 228 static int omap_modeset_init(struct drm_device *dev) 229 { 230 struct omap_drm_private *priv = dev->dev_private; 231 int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc); 232 int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); 233 unsigned int i; 234 int ret; 235 u32 plane_crtc_mask; 236 237 if (!omapdss_stack_is_ready()) 238 return -EPROBE_DEFER; 239 240 drm_mode_config_init(dev); 241 242 ret = omap_modeset_init_properties(dev); 243 if (ret < 0) 244 return ret; 245 246 /* 247 * This function creates exactly one connector, encoder, crtc, 248 * and primary plane per each connected dss-device. Each 249 * connector->encoder->crtc chain is expected to be separate 250 * and each crtc is connect to a single dss-channel. If the 251 * configuration does not match the expectations or exceeds 252 * the available resources, the configuration is rejected. 253 */ 254 ret = omap_connect_pipelines(dev); 255 if (ret < 0) 256 return ret; 257 258 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) { 259 dev_err(dev->dev, "%s(): Too many connected displays\n", 260 __func__); 261 return -EINVAL; 262 } 263 264 /* Create all planes first. They can all be put to any CRTC. */ 265 plane_crtc_mask = (1 << priv->num_pipes) - 1; 266 267 for (i = 0; i < num_ovls; i++) { 268 enum drm_plane_type type = i < priv->num_pipes 269 ? DRM_PLANE_TYPE_PRIMARY 270 : DRM_PLANE_TYPE_OVERLAY; 271 struct drm_plane *plane; 272 273 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes))) 274 return -EINVAL; 275 276 plane = omap_plane_init(dev, i, type, plane_crtc_mask); 277 if (IS_ERR(plane)) 278 return PTR_ERR(plane); 279 280 priv->planes[priv->num_planes++] = plane; 281 } 282 283 /* 284 * Create the encoders, attach the bridges and get the pipeline alias 285 * IDs. 286 */ 287 for (i = 0; i < priv->num_pipes; i++) { 288 struct omap_drm_pipeline *pipe = &priv->pipes[i]; 289 int id; 290 291 pipe->encoder = omap_encoder_init(dev, pipe->output); 292 if (!pipe->encoder) 293 return -ENOMEM; 294 295 if (pipe->output->bridge) { 296 ret = drm_bridge_attach(pipe->encoder, 297 pipe->output->bridge, NULL, 298 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 299 if (ret < 0) { 300 dev_err(priv->dev, 301 "unable to attach bridge %pOF\n", 302 pipe->output->bridge->of_node); 303 return ret; 304 } 305 } 306 307 id = omap_display_id(pipe->output); 308 pipe->alias_id = id >= 0 ? id : i; 309 } 310 311 /* Sort the pipelines by DT aliases. */ 312 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), 313 omap_compare_pipelines, NULL); 314 315 /* 316 * Populate the pipeline lookup table by DISPC channel. Only one display 317 * is allowed per channel. 318 */ 319 for (i = 0; i < priv->num_pipes; ++i) { 320 struct omap_drm_pipeline *pipe = &priv->pipes[i]; 321 enum omap_channel channel = pipe->output->dispc_channel; 322 323 if (WARN_ON(priv->channels[channel] != NULL)) 324 return -EINVAL; 325 326 priv->channels[channel] = pipe; 327 } 328 329 /* Create the connectors and CRTCs. */ 330 for (i = 0; i < priv->num_pipes; i++) { 331 struct omap_drm_pipeline *pipe = &priv->pipes[i]; 332 struct drm_encoder *encoder = pipe->encoder; 333 struct drm_crtc *crtc; 334 335 if (pipe->output->next) { 336 pipe->connector = omap_connector_init(dev, pipe->output, 337 encoder); 338 if (!pipe->connector) 339 return -ENOMEM; 340 } else { 341 pipe->connector = drm_bridge_connector_init(dev, encoder); 342 if (IS_ERR(pipe->connector)) { 343 dev_err(priv->dev, 344 "unable to create bridge connector for %s\n", 345 pipe->output->name); 346 return PTR_ERR(pipe->connector); 347 } 348 } 349 350 drm_connector_attach_encoder(pipe->connector, encoder); 351 352 crtc = omap_crtc_init(dev, pipe, priv->planes[i]); 353 if (IS_ERR(crtc)) 354 return PTR_ERR(crtc); 355 356 encoder->possible_crtcs = 1 << i; 357 pipe->crtc = crtc; 358 } 359 360 DBG("registered %u planes, %u crtcs/encoders/connectors\n", 361 priv->num_planes, priv->num_pipes); 362 363 dev->mode_config.min_width = 8; 364 dev->mode_config.min_height = 2; 365 366 /* 367 * Note: these values are used for multiple independent things: 368 * connector mode filtering, buffer sizes, crtc sizes... 369 * Use big enough values here to cover all use cases, and do more 370 * specific checking in the respective code paths. 371 */ 372 dev->mode_config.max_width = 8192; 373 dev->mode_config.max_height = 8192; 374 375 /* We want the zpos to be normalized */ 376 dev->mode_config.normalize_zpos = true; 377 378 dev->mode_config.funcs = &omap_mode_config_funcs; 379 dev->mode_config.helper_private = &omap_mode_config_helper_funcs; 380 381 drm_mode_config_reset(dev); 382 383 omap_drm_irq_install(dev); 384 385 return 0; 386 } 387 388 static void omap_modeset_fini(struct drm_device *ddev) 389 { 390 omap_drm_irq_uninstall(ddev); 391 392 drm_mode_config_cleanup(ddev); 393 } 394 395 /* 396 * Enable the HPD in external components if supported 397 */ 398 static void omap_modeset_enable_external_hpd(struct drm_device *ddev) 399 { 400 struct omap_drm_private *priv = ddev->dev_private; 401 unsigned int i; 402 403 for (i = 0; i < priv->num_pipes; i++) { 404 struct drm_connector *connector = priv->pipes[i].connector; 405 406 if (!connector) 407 continue; 408 409 if (priv->pipes[i].output->bridge) 410 drm_bridge_connector_enable_hpd(connector); 411 } 412 } 413 414 /* 415 * Disable the HPD in external components if supported 416 */ 417 static void omap_modeset_disable_external_hpd(struct drm_device *ddev) 418 { 419 struct omap_drm_private *priv = ddev->dev_private; 420 unsigned int i; 421 422 for (i = 0; i < priv->num_pipes; i++) { 423 struct drm_connector *connector = priv->pipes[i].connector; 424 425 if (!connector) 426 continue; 427 428 if (priv->pipes[i].output->bridge) 429 drm_bridge_connector_disable_hpd(connector); 430 } 431 } 432 433 /* 434 * drm ioctl funcs 435 */ 436 437 438 static int ioctl_get_param(struct drm_device *dev, void *data, 439 struct drm_file *file_priv) 440 { 441 struct omap_drm_private *priv = dev->dev_private; 442 struct drm_omap_param *args = data; 443 444 DBG("%p: param=%llu", dev, args->param); 445 446 switch (args->param) { 447 case OMAP_PARAM_CHIPSET_ID: 448 args->value = priv->omaprev; 449 break; 450 default: 451 DBG("unknown parameter %lld", args->param); 452 return -EINVAL; 453 } 454 455 return 0; 456 } 457 458 #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */ 459 460 static int ioctl_gem_new(struct drm_device *dev, void *data, 461 struct drm_file *file_priv) 462 { 463 struct drm_omap_gem_new *args = data; 464 u32 flags = args->flags & OMAP_BO_USER_MASK; 465 466 VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, 467 args->size.bytes, flags); 468 469 return omap_gem_new_handle(dev, file_priv, args->size, flags, 470 &args->handle); 471 } 472 473 static int ioctl_gem_info(struct drm_device *dev, void *data, 474 struct drm_file *file_priv) 475 { 476 struct drm_omap_gem_info *args = data; 477 struct drm_gem_object *obj; 478 int ret = 0; 479 480 VERB("%p:%p: handle=%d", dev, file_priv, args->handle); 481 482 obj = drm_gem_object_lookup(file_priv, args->handle); 483 if (!obj) 484 return -ENOENT; 485 486 args->size = omap_gem_mmap_size(obj); 487 args->offset = omap_gem_mmap_offset(obj); 488 489 drm_gem_object_put(obj); 490 491 return ret; 492 } 493 494 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { 495 DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, 496 DRM_RENDER_ALLOW), 497 DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op, 498 DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY), 499 DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, 500 DRM_RENDER_ALLOW), 501 /* Deprecated, to be removed. */ 502 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop, 503 DRM_RENDER_ALLOW), 504 /* Deprecated, to be removed. */ 505 DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop, 506 DRM_RENDER_ALLOW), 507 DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, 508 DRM_RENDER_ALLOW), 509 }; 510 511 /* 512 * drm driver funcs 513 */ 514 515 static int dev_open(struct drm_device *dev, struct drm_file *file) 516 { 517 file->driver_priv = NULL; 518 519 DBG("open: dev=%p, file=%p", dev, file); 520 521 return 0; 522 } 523 524 static const struct file_operations omapdriver_fops = { 525 .owner = THIS_MODULE, 526 .open = drm_open, 527 .unlocked_ioctl = drm_ioctl, 528 .compat_ioctl = drm_compat_ioctl, 529 .release = drm_release, 530 .mmap = omap_gem_mmap, 531 .poll = drm_poll, 532 .read = drm_read, 533 .llseek = noop_llseek, 534 }; 535 536 static const struct drm_driver omap_drm_driver = { 537 .driver_features = DRIVER_MODESET | DRIVER_GEM | 538 DRIVER_ATOMIC | DRIVER_RENDER, 539 .open = dev_open, 540 .lastclose = drm_fb_helper_lastclose, 541 #ifdef CONFIG_DEBUG_FS 542 .debugfs_init = omap_debugfs_init, 543 #endif 544 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 545 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 546 .gem_prime_import = omap_gem_prime_import, 547 .dumb_create = omap_gem_dumb_create, 548 .dumb_map_offset = omap_gem_dumb_map_offset, 549 .ioctls = ioctls, 550 .num_ioctls = DRM_OMAP_NUM_IOCTLS, 551 .fops = &omapdriver_fops, 552 .name = DRIVER_NAME, 553 .desc = DRIVER_DESC, 554 .date = DRIVER_DATE, 555 .major = DRIVER_MAJOR, 556 .minor = DRIVER_MINOR, 557 .patchlevel = DRIVER_PATCHLEVEL, 558 }; 559 560 static const struct soc_device_attribute omapdrm_soc_devices[] = { 561 { .family = "OMAP3", .data = (void *)0x3430 }, 562 { .family = "OMAP4", .data = (void *)0x4430 }, 563 { .family = "OMAP5", .data = (void *)0x5430 }, 564 { .family = "DRA7", .data = (void *)0x0752 }, 565 { /* sentinel */ } 566 }; 567 568 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) 569 { 570 const struct soc_device_attribute *soc; 571 struct drm_device *ddev; 572 int ret; 573 574 DBG("%s", dev_name(dev)); 575 576 /* Allocate and initialize the DRM device. */ 577 ddev = drm_dev_alloc(&omap_drm_driver, dev); 578 if (IS_ERR(ddev)) 579 return PTR_ERR(ddev); 580 581 priv->ddev = ddev; 582 ddev->dev_private = priv; 583 584 priv->dev = dev; 585 priv->dss = omapdss_get_dss(); 586 priv->dispc = dispc_get_dispc(priv->dss); 587 priv->dispc_ops = dispc_get_ops(priv->dss); 588 589 omap_crtc_pre_init(priv); 590 591 soc = soc_device_match(omapdrm_soc_devices); 592 priv->omaprev = soc ? (unsigned int)soc->data : 0; 593 priv->wq = alloc_ordered_workqueue("omapdrm", 0); 594 595 mutex_init(&priv->list_lock); 596 INIT_LIST_HEAD(&priv->obj_list); 597 598 /* Get memory bandwidth limits */ 599 if (priv->dispc_ops->get_memory_bandwidth_limit) 600 priv->max_bandwidth = 601 priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc); 602 603 omap_gem_init(ddev); 604 605 ret = omap_modeset_init(ddev); 606 if (ret) { 607 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret); 608 goto err_gem_deinit; 609 } 610 611 /* Initialize vblank handling, start with all CRTCs disabled. */ 612 ret = drm_vblank_init(ddev, priv->num_pipes); 613 if (ret) { 614 dev_err(priv->dev, "could not init vblank\n"); 615 goto err_cleanup_modeset; 616 } 617 618 omap_fbdev_init(ddev); 619 620 drm_kms_helper_poll_init(ddev); 621 omap_modeset_enable_external_hpd(ddev); 622 623 /* 624 * Register the DRM device with the core and the connectors with 625 * sysfs. 626 */ 627 ret = drm_dev_register(ddev, 0); 628 if (ret) 629 goto err_cleanup_helpers; 630 631 return 0; 632 633 err_cleanup_helpers: 634 omap_modeset_disable_external_hpd(ddev); 635 drm_kms_helper_poll_fini(ddev); 636 637 omap_fbdev_fini(ddev); 638 err_cleanup_modeset: 639 omap_modeset_fini(ddev); 640 err_gem_deinit: 641 omap_gem_deinit(ddev); 642 destroy_workqueue(priv->wq); 643 omap_disconnect_pipelines(ddev); 644 omap_crtc_pre_uninit(priv); 645 drm_dev_put(ddev); 646 return ret; 647 } 648 649 static void omapdrm_cleanup(struct omap_drm_private *priv) 650 { 651 struct drm_device *ddev = priv->ddev; 652 653 DBG(""); 654 655 drm_dev_unregister(ddev); 656 657 omap_modeset_disable_external_hpd(ddev); 658 drm_kms_helper_poll_fini(ddev); 659 660 omap_fbdev_fini(ddev); 661 662 drm_atomic_helper_shutdown(ddev); 663 664 omap_modeset_fini(ddev); 665 omap_gem_deinit(ddev); 666 667 destroy_workqueue(priv->wq); 668 669 omap_disconnect_pipelines(ddev); 670 omap_crtc_pre_uninit(priv); 671 672 drm_dev_put(ddev); 673 } 674 675 static int pdev_probe(struct platform_device *pdev) 676 { 677 struct omap_drm_private *priv; 678 int ret; 679 680 if (omapdss_is_initialized() == false) 681 return -EPROBE_DEFER; 682 683 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 684 if (ret) { 685 dev_err(&pdev->dev, "Failed to set the DMA mask\n"); 686 return ret; 687 } 688 689 /* Allocate and initialize the driver private structure. */ 690 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 691 if (!priv) 692 return -ENOMEM; 693 694 platform_set_drvdata(pdev, priv); 695 696 ret = omapdrm_init(priv, &pdev->dev); 697 if (ret < 0) 698 kfree(priv); 699 700 return ret; 701 } 702 703 static int pdev_remove(struct platform_device *pdev) 704 { 705 struct omap_drm_private *priv = platform_get_drvdata(pdev); 706 707 omapdrm_cleanup(priv); 708 kfree(priv); 709 710 return 0; 711 } 712 713 #ifdef CONFIG_PM_SLEEP 714 static int omap_drm_suspend(struct device *dev) 715 { 716 struct omap_drm_private *priv = dev_get_drvdata(dev); 717 struct drm_device *drm_dev = priv->ddev; 718 719 return drm_mode_config_helper_suspend(drm_dev); 720 } 721 722 static int omap_drm_resume(struct device *dev) 723 { 724 struct omap_drm_private *priv = dev_get_drvdata(dev); 725 struct drm_device *drm_dev = priv->ddev; 726 727 drm_mode_config_helper_resume(drm_dev); 728 729 return omap_gem_resume(drm_dev); 730 } 731 #endif 732 733 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume); 734 735 static struct platform_driver pdev = { 736 .driver = { 737 .name = "omapdrm", 738 .pm = &omapdrm_pm_ops, 739 }, 740 .probe = pdev_probe, 741 .remove = pdev_remove, 742 }; 743 744 static struct platform_driver * const drivers[] = { 745 &omap_dmm_driver, 746 &pdev, 747 }; 748 749 static int __init omap_drm_init(void) 750 { 751 DBG("init"); 752 753 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 754 } 755 756 static void __exit omap_drm_fini(void) 757 { 758 DBG("fini"); 759 760 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 761 } 762 763 /* need late_initcall() so we load after dss_driver's are loaded */ 764 late_initcall(omap_drm_init); 765 module_exit(omap_drm_fini); 766 767 MODULE_AUTHOR("Rob Clark <rob@ti.com>"); 768 MODULE_DESCRIPTION("OMAP DRM Display Driver"); 769 MODULE_ALIAS("platform:" DRIVER_NAME); 770 MODULE_LICENSE("GPL v2"); 771