1 /* 2 * DMM IOMMU driver support functions for TI OMAP processors. 3 * 4 * Author: Rob Clark <rob@ti.com> 5 * Andy Gross <andy.gross@ti.com> 6 * 7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> /* platform_device() */ 21 #include <linux/errno.h> 22 #include <linux/sched.h> 23 #include <linux/wait.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/slab.h> 27 #include <linux/vmalloc.h> 28 #include <linux/delay.h> 29 #include <linux/mm.h> 30 #include <linux/time.h> 31 #include <linux/list.h> 32 33 #include "omap_dmm_tiler.h" 34 #include "omap_dmm_priv.h" 35 36 #define DMM_DRIVER_NAME "dmm" 37 38 /* mappings for associating views to luts */ 39 static struct tcm *containers[TILFMT_NFORMATS]; 40 static struct dmm *omap_dmm; 41 42 /* global spinlock for protecting lists */ 43 static DEFINE_SPINLOCK(list_lock); 44 45 /* Geometry table */ 46 #define GEOM(xshift, yshift, bytes_per_pixel) { \ 47 .x_shft = (xshift), \ 48 .y_shft = (yshift), \ 49 .cpp = (bytes_per_pixel), \ 50 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \ 51 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \ 52 } 53 54 static const struct { 55 uint32_t x_shft; /* unused X-bits (as part of bpp) */ 56 uint32_t y_shft; /* unused Y-bits (as part of bpp) */ 57 uint32_t cpp; /* bytes/chars per pixel */ 58 uint32_t slot_w; /* width of each slot (in pixels) */ 59 uint32_t slot_h; /* height of each slot (in pixels) */ 60 } geom[TILFMT_NFORMATS] = { 61 [TILFMT_8BIT] = GEOM(0, 0, 1), 62 [TILFMT_16BIT] = GEOM(0, 1, 2), 63 [TILFMT_32BIT] = GEOM(1, 1, 4), 64 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1), 65 }; 66 67 68 /* lookup table for registers w/ per-engine instances */ 69 static const uint32_t reg[][4] = { 70 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, 71 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, 72 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, 73 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3}, 74 }; 75 76 /* simple allocator to grab next 16 byte aligned memory from txn */ 77 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) 78 { 79 void *ptr; 80 struct refill_engine *engine = txn->engine_handle; 81 82 /* dmm programming requires 16 byte aligned addresses */ 83 txn->current_pa = round_up(txn->current_pa, 16); 84 txn->current_va = (void *)round_up((long)txn->current_va, 16); 85 86 ptr = txn->current_va; 87 *pa = txn->current_pa; 88 89 txn->current_pa += sz; 90 txn->current_va += sz; 91 92 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); 93 94 return ptr; 95 } 96 97 /* check status and spin until wait_mask comes true */ 98 static int wait_status(struct refill_engine *engine, uint32_t wait_mask) 99 { 100 struct dmm *dmm = engine->dmm; 101 uint32_t r = 0, err, i; 102 103 i = DMM_FIXED_RETRY_COUNT; 104 while (true) { 105 r = readl(dmm->base + reg[PAT_STATUS][engine->id]); 106 err = r & DMM_PATSTATUS_ERR; 107 if (err) 108 return -EFAULT; 109 110 if ((r & wait_mask) == wait_mask) 111 break; 112 113 if (--i == 0) 114 return -ETIMEDOUT; 115 116 udelay(1); 117 } 118 119 return 0; 120 } 121 122 static void release_engine(struct refill_engine *engine) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&list_lock, flags); 127 list_add(&engine->idle_node, &omap_dmm->idle_head); 128 spin_unlock_irqrestore(&list_lock, flags); 129 130 atomic_inc(&omap_dmm->engine_counter); 131 wake_up_interruptible(&omap_dmm->engine_queue); 132 } 133 134 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) 135 { 136 struct dmm *dmm = arg; 137 uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS); 138 int i; 139 140 /* ack IRQ */ 141 writel(status, dmm->base + DMM_PAT_IRQSTATUS); 142 143 for (i = 0; i < dmm->num_engines; i++) { 144 if (status & DMM_IRQSTAT_LST) { 145 wake_up_interruptible(&dmm->engines[i].wait_for_refill); 146 147 if (dmm->engines[i].async) 148 release_engine(&dmm->engines[i]); 149 } 150 151 status >>= 8; 152 } 153 154 return IRQ_HANDLED; 155 } 156 157 /** 158 * Get a handle for a DMM transaction 159 */ 160 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) 161 { 162 struct dmm_txn *txn = NULL; 163 struct refill_engine *engine = NULL; 164 int ret; 165 unsigned long flags; 166 167 168 /* wait until an engine is available */ 169 ret = wait_event_interruptible(omap_dmm->engine_queue, 170 atomic_add_unless(&omap_dmm->engine_counter, -1, 0)); 171 if (ret) 172 return ERR_PTR(ret); 173 174 /* grab an idle engine */ 175 spin_lock_irqsave(&list_lock, flags); 176 if (!list_empty(&dmm->idle_head)) { 177 engine = list_entry(dmm->idle_head.next, struct refill_engine, 178 idle_node); 179 list_del(&engine->idle_node); 180 } 181 spin_unlock_irqrestore(&list_lock, flags); 182 183 BUG_ON(!engine); 184 185 txn = &engine->txn; 186 engine->tcm = tcm; 187 txn->engine_handle = engine; 188 txn->last_pat = NULL; 189 txn->current_va = engine->refill_va; 190 txn->current_pa = engine->refill_pa; 191 192 return txn; 193 } 194 195 /** 196 * Add region to DMM transaction. If pages or pages[i] is NULL, then the 197 * corresponding slot is cleared (ie. dummy_pa is programmed) 198 */ 199 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, 200 struct page **pages, uint32_t npages, uint32_t roll) 201 { 202 dma_addr_t pat_pa = 0, data_pa = 0; 203 uint32_t *data; 204 struct pat *pat; 205 struct refill_engine *engine = txn->engine_handle; 206 int columns = (1 + area->x1 - area->x0); 207 int rows = (1 + area->y1 - area->y0); 208 int i = columns*rows; 209 210 pat = alloc_dma(txn, sizeof(struct pat), &pat_pa); 211 212 if (txn->last_pat) 213 txn->last_pat->next_pa = (uint32_t)pat_pa; 214 215 pat->area = *area; 216 217 /* adjust Y coordinates based off of container parameters */ 218 pat->area.y0 += engine->tcm->y_offset; 219 pat->area.y1 += engine->tcm->y_offset; 220 221 pat->ctrl = (struct pat_ctrl){ 222 .start = 1, 223 .lut_id = engine->tcm->lut_id, 224 }; 225 226 data = alloc_dma(txn, 4*i, &data_pa); 227 /* FIXME: what if data_pa is more than 32-bit ? */ 228 pat->data_pa = data_pa; 229 230 while (i--) { 231 int n = i + roll; 232 if (n >= npages) 233 n -= npages; 234 data[i] = (pages && pages[n]) ? 235 page_to_phys(pages[n]) : engine->dmm->dummy_pa; 236 } 237 238 txn->last_pat = pat; 239 240 return; 241 } 242 243 /** 244 * Commit the DMM transaction. 245 */ 246 static int dmm_txn_commit(struct dmm_txn *txn, bool wait) 247 { 248 int ret = 0; 249 struct refill_engine *engine = txn->engine_handle; 250 struct dmm *dmm = engine->dmm; 251 252 if (!txn->last_pat) { 253 dev_err(engine->dmm->dev, "need at least one txn\n"); 254 ret = -EINVAL; 255 goto cleanup; 256 } 257 258 txn->last_pat->next_pa = 0; 259 260 /* write to PAT_DESCR to clear out any pending transaction */ 261 writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]); 262 263 /* wait for engine ready: */ 264 ret = wait_status(engine, DMM_PATSTATUS_READY); 265 if (ret) { 266 ret = -EFAULT; 267 goto cleanup; 268 } 269 270 /* mark whether it is async to denote list management in IRQ handler */ 271 engine->async = wait ? false : true; 272 273 /* kick reload */ 274 writel(engine->refill_pa, 275 dmm->base + reg[PAT_DESCR][engine->id]); 276 277 if (wait) { 278 if (wait_event_interruptible_timeout(engine->wait_for_refill, 279 wait_status(engine, DMM_PATSTATUS_READY) == 0, 280 msecs_to_jiffies(1)) <= 0) { 281 dev_err(dmm->dev, "timed out waiting for done\n"); 282 ret = -ETIMEDOUT; 283 } 284 } 285 286 cleanup: 287 /* only place engine back on list if we are done with it */ 288 if (ret || wait) 289 release_engine(engine); 290 291 return ret; 292 } 293 294 /* 295 * DMM programming 296 */ 297 static int fill(struct tcm_area *area, struct page **pages, 298 uint32_t npages, uint32_t roll, bool wait) 299 { 300 int ret = 0; 301 struct tcm_area slice, area_s; 302 struct dmm_txn *txn; 303 304 txn = dmm_txn_init(omap_dmm, area->tcm); 305 if (IS_ERR_OR_NULL(txn)) 306 return -ENOMEM; 307 308 tcm_for_each_slice(slice, *area, area_s) { 309 struct pat_area p_area = { 310 .x0 = slice.p0.x, .y0 = slice.p0.y, 311 .x1 = slice.p1.x, .y1 = slice.p1.y, 312 }; 313 314 dmm_txn_append(txn, &p_area, pages, npages, roll); 315 316 roll += tcm_sizeof(slice); 317 } 318 319 ret = dmm_txn_commit(txn, wait); 320 321 return ret; 322 } 323 324 /* 325 * Pin/unpin 326 */ 327 328 /* note: slots for which pages[i] == NULL are filled w/ dummy page 329 */ 330 int tiler_pin(struct tiler_block *block, struct page **pages, 331 uint32_t npages, uint32_t roll, bool wait) 332 { 333 int ret; 334 335 ret = fill(&block->area, pages, npages, roll, wait); 336 337 if (ret) 338 tiler_unpin(block); 339 340 return ret; 341 } 342 343 int tiler_unpin(struct tiler_block *block) 344 { 345 return fill(&block->area, NULL, 0, 0, false); 346 } 347 348 /* 349 * Reserve/release 350 */ 351 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, 352 uint16_t h, uint16_t align) 353 { 354 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); 355 u32 min_align = 128; 356 int ret; 357 unsigned long flags; 358 359 BUG_ON(!validfmt(fmt)); 360 361 /* convert width/height to slots */ 362 w = DIV_ROUND_UP(w, geom[fmt].slot_w); 363 h = DIV_ROUND_UP(h, geom[fmt].slot_h); 364 365 /* convert alignment to slots */ 366 min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp)); 367 align = ALIGN(align, min_align); 368 align /= geom[fmt].slot_w * geom[fmt].cpp; 369 370 block->fmt = fmt; 371 372 ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area); 373 if (ret) { 374 kfree(block); 375 return ERR_PTR(-ENOMEM); 376 } 377 378 /* add to allocation list */ 379 spin_lock_irqsave(&list_lock, flags); 380 list_add(&block->alloc_node, &omap_dmm->alloc_head); 381 spin_unlock_irqrestore(&list_lock, flags); 382 383 return block; 384 } 385 386 struct tiler_block *tiler_reserve_1d(size_t size) 387 { 388 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); 389 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 390 unsigned long flags; 391 392 if (!block) 393 return ERR_PTR(-ENOMEM); 394 395 block->fmt = TILFMT_PAGE; 396 397 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages, 398 &block->area)) { 399 kfree(block); 400 return ERR_PTR(-ENOMEM); 401 } 402 403 spin_lock_irqsave(&list_lock, flags); 404 list_add(&block->alloc_node, &omap_dmm->alloc_head); 405 spin_unlock_irqrestore(&list_lock, flags); 406 407 return block; 408 } 409 410 /* note: if you have pin'd pages, you should have already unpin'd first! */ 411 int tiler_release(struct tiler_block *block) 412 { 413 int ret = tcm_free(&block->area); 414 unsigned long flags; 415 416 if (block->area.tcm) 417 dev_err(omap_dmm->dev, "failed to release block\n"); 418 419 spin_lock_irqsave(&list_lock, flags); 420 list_del(&block->alloc_node); 421 spin_unlock_irqrestore(&list_lock, flags); 422 423 kfree(block); 424 return ret; 425 } 426 427 /* 428 * Utils 429 */ 430 431 /* calculate the tiler space address of a pixel in a view orientation... 432 * below description copied from the display subsystem section of TRM: 433 * 434 * When the TILER is addressed, the bits: 435 * [28:27] = 0x0 for 8-bit tiled 436 * 0x1 for 16-bit tiled 437 * 0x2 for 32-bit tiled 438 * 0x3 for page mode 439 * [31:29] = 0x0 for 0-degree view 440 * 0x1 for 180-degree view + mirroring 441 * 0x2 for 0-degree view + mirroring 442 * 0x3 for 180-degree view 443 * 0x4 for 270-degree view + mirroring 444 * 0x5 for 270-degree view 445 * 0x6 for 90-degree view 446 * 0x7 for 90-degree view + mirroring 447 * Otherwise the bits indicated the corresponding bit address to access 448 * the SDRAM. 449 */ 450 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y) 451 { 452 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment; 453 454 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft; 455 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft; 456 alignment = geom[fmt].x_shft + geom[fmt].y_shft; 457 458 /* validate coordinate */ 459 x_mask = MASK(x_bits); 460 y_mask = MASK(y_bits); 461 462 if (x < 0 || x > x_mask || y < 0 || y > y_mask) { 463 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u", 464 x, x, x_mask, y, y, y_mask); 465 return 0; 466 } 467 468 /* account for mirroring */ 469 if (orient & MASK_X_INVERT) 470 x ^= x_mask; 471 if (orient & MASK_Y_INVERT) 472 y ^= y_mask; 473 474 /* get coordinate address */ 475 if (orient & MASK_XY_FLIP) 476 tmp = ((x << y_bits) + y); 477 else 478 tmp = ((y << x_bits) + x); 479 480 return TIL_ADDR((tmp << alignment), orient, fmt); 481 } 482 483 dma_addr_t tiler_ssptr(struct tiler_block *block) 484 { 485 BUG_ON(!validfmt(block->fmt)); 486 487 return TILVIEW_8BIT + tiler_get_address(block->fmt, 0, 488 block->area.p0.x * geom[block->fmt].slot_w, 489 block->area.p0.y * geom[block->fmt].slot_h); 490 } 491 492 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, 493 uint32_t x, uint32_t y) 494 { 495 struct tcm_pt *p = &block->area.p0; 496 BUG_ON(!validfmt(block->fmt)); 497 498 return tiler_get_address(block->fmt, orient, 499 (p->x * geom[block->fmt].slot_w) + x, 500 (p->y * geom[block->fmt].slot_h) + y); 501 } 502 503 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h) 504 { 505 BUG_ON(!validfmt(fmt)); 506 *w = round_up(*w, geom[fmt].slot_w); 507 *h = round_up(*h, geom[fmt].slot_h); 508 } 509 510 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) 511 { 512 BUG_ON(!validfmt(fmt)); 513 514 if (orient & MASK_XY_FLIP) 515 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft); 516 else 517 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); 518 } 519 520 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h) 521 { 522 tiler_align(fmt, &w, &h); 523 return geom[fmt].cpp * w * h; 524 } 525 526 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h) 527 { 528 BUG_ON(!validfmt(fmt)); 529 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; 530 } 531 532 bool dmm_is_available(void) 533 { 534 return omap_dmm ? true : false; 535 } 536 537 static int omap_dmm_remove(struct platform_device *dev) 538 { 539 struct tiler_block *block, *_block; 540 int i; 541 unsigned long flags; 542 543 if (omap_dmm) { 544 /* free all area regions */ 545 spin_lock_irqsave(&list_lock, flags); 546 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head, 547 alloc_node) { 548 list_del(&block->alloc_node); 549 kfree(block); 550 } 551 spin_unlock_irqrestore(&list_lock, flags); 552 553 for (i = 0; i < omap_dmm->num_lut; i++) 554 if (omap_dmm->tcm && omap_dmm->tcm[i]) 555 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]); 556 kfree(omap_dmm->tcm); 557 558 kfree(omap_dmm->engines); 559 if (omap_dmm->refill_va) 560 dma_free_writecombine(omap_dmm->dev, 561 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 562 omap_dmm->refill_va, 563 omap_dmm->refill_pa); 564 if (omap_dmm->dummy_page) 565 __free_page(omap_dmm->dummy_page); 566 567 if (omap_dmm->irq > 0) 568 free_irq(omap_dmm->irq, omap_dmm); 569 570 iounmap(omap_dmm->base); 571 kfree(omap_dmm); 572 omap_dmm = NULL; 573 } 574 575 return 0; 576 } 577 578 static int omap_dmm_probe(struct platform_device *dev) 579 { 580 int ret = -EFAULT, i; 581 struct tcm_area area = {0}; 582 u32 hwinfo, pat_geom; 583 struct resource *mem; 584 585 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL); 586 if (!omap_dmm) 587 goto fail; 588 589 /* initialize lists */ 590 INIT_LIST_HEAD(&omap_dmm->alloc_head); 591 INIT_LIST_HEAD(&omap_dmm->idle_head); 592 593 init_waitqueue_head(&omap_dmm->engine_queue); 594 595 /* lookup hwmod data - base address and irq */ 596 mem = platform_get_resource(dev, IORESOURCE_MEM, 0); 597 if (!mem) { 598 dev_err(&dev->dev, "failed to get base address resource\n"); 599 goto fail; 600 } 601 602 omap_dmm->base = ioremap(mem->start, SZ_2K); 603 604 if (!omap_dmm->base) { 605 dev_err(&dev->dev, "failed to get dmm base address\n"); 606 goto fail; 607 } 608 609 omap_dmm->irq = platform_get_irq(dev, 0); 610 if (omap_dmm->irq < 0) { 611 dev_err(&dev->dev, "failed to get IRQ resource\n"); 612 goto fail; 613 } 614 615 omap_dmm->dev = &dev->dev; 616 617 hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO); 618 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; 619 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F; 620 omap_dmm->container_width = 256; 621 omap_dmm->container_height = 128; 622 623 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); 624 625 /* read out actual LUT width and height */ 626 pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY); 627 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5; 628 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5; 629 630 /* increment LUT by one if on OMAP5 */ 631 /* LUT has twice the height, and is split into a separate container */ 632 if (omap_dmm->lut_height != omap_dmm->container_height) 633 omap_dmm->num_lut++; 634 635 /* initialize DMM registers */ 636 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0); 637 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1); 638 writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0); 639 writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE); 640 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0); 641 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1); 642 643 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED, 644 "omap_dmm_irq_handler", omap_dmm); 645 646 if (ret) { 647 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n", 648 omap_dmm->irq, ret); 649 omap_dmm->irq = -1; 650 goto fail; 651 } 652 653 /* Enable all interrupts for each refill engine except 654 * ERR_LUT_MISS<n> (which is just advisory, and we don't care 655 * about because we want to be able to refill live scanout 656 * buffers for accelerated pan/scroll) and FILL_DSC<n> which 657 * we just generally don't care about. 658 */ 659 writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET); 660 661 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32); 662 if (!omap_dmm->dummy_page) { 663 dev_err(&dev->dev, "could not allocate dummy page\n"); 664 ret = -ENOMEM; 665 goto fail; 666 } 667 668 /* set dma mask for device */ 669 ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 670 if (ret) 671 goto fail; 672 673 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page); 674 675 /* alloc refill memory */ 676 omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev, 677 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 678 &omap_dmm->refill_pa, GFP_KERNEL); 679 if (!omap_dmm->refill_va) { 680 dev_err(&dev->dev, "could not allocate refill memory\n"); 681 goto fail; 682 } 683 684 /* alloc engines */ 685 omap_dmm->engines = kcalloc(omap_dmm->num_engines, 686 sizeof(struct refill_engine), GFP_KERNEL); 687 if (!omap_dmm->engines) { 688 ret = -ENOMEM; 689 goto fail; 690 } 691 692 for (i = 0; i < omap_dmm->num_engines; i++) { 693 omap_dmm->engines[i].id = i; 694 omap_dmm->engines[i].dmm = omap_dmm; 695 omap_dmm->engines[i].refill_va = omap_dmm->refill_va + 696 (REFILL_BUFFER_SIZE * i); 697 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + 698 (REFILL_BUFFER_SIZE * i); 699 init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill); 700 701 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); 702 } 703 704 omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm), 705 GFP_KERNEL); 706 if (!omap_dmm->tcm) { 707 ret = -ENOMEM; 708 goto fail; 709 } 710 711 /* init containers */ 712 /* Each LUT is associated with a TCM (container manager). We use the 713 lut_id to denote the lut_id used to identify the correct LUT for 714 programming during reill operations */ 715 for (i = 0; i < omap_dmm->num_lut; i++) { 716 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width, 717 omap_dmm->container_height, 718 NULL); 719 720 if (!omap_dmm->tcm[i]) { 721 dev_err(&dev->dev, "failed to allocate container\n"); 722 ret = -ENOMEM; 723 goto fail; 724 } 725 726 omap_dmm->tcm[i]->lut_id = i; 727 } 728 729 /* assign access mode containers to applicable tcm container */ 730 /* OMAP 4 has 1 container for all 4 views */ 731 /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */ 732 containers[TILFMT_8BIT] = omap_dmm->tcm[0]; 733 containers[TILFMT_16BIT] = omap_dmm->tcm[0]; 734 containers[TILFMT_32BIT] = omap_dmm->tcm[0]; 735 736 if (omap_dmm->container_height != omap_dmm->lut_height) { 737 /* second LUT is used for PAGE mode. Programming must use 738 y offset that is added to all y coordinates. LUT id is still 739 0, because it is the same LUT, just the upper 128 lines */ 740 containers[TILFMT_PAGE] = omap_dmm->tcm[1]; 741 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET; 742 omap_dmm->tcm[1]->lut_id = 0; 743 } else { 744 containers[TILFMT_PAGE] = omap_dmm->tcm[0]; 745 } 746 747 area = (struct tcm_area) { 748 .tcm = NULL, 749 .p1.x = omap_dmm->container_width - 1, 750 .p1.y = omap_dmm->container_height - 1, 751 }; 752 753 /* initialize all LUTs to dummy page entries */ 754 for (i = 0; i < omap_dmm->num_lut; i++) { 755 area.tcm = omap_dmm->tcm[i]; 756 if (fill(&area, NULL, 0, 0, true)) 757 dev_err(omap_dmm->dev, "refill failed"); 758 } 759 760 dev_info(omap_dmm->dev, "initialized all PAT entries\n"); 761 762 return 0; 763 764 fail: 765 if (omap_dmm_remove(dev)) 766 dev_err(&dev->dev, "cleanup failed\n"); 767 return ret; 768 } 769 770 /* 771 * debugfs support 772 */ 773 774 #ifdef CONFIG_DEBUG_FS 775 776 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz" 777 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; 778 static const char *special = ".,:;'\"`~!^-+"; 779 780 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a, 781 char c, bool ovw) 782 { 783 int x, y; 784 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) 785 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) 786 if (map[y][x] == ' ' || ovw) 787 map[y][x] = c; 788 } 789 790 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p, 791 char c) 792 { 793 map[p->y / ydiv][p->x / xdiv] = c; 794 } 795 796 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p) 797 { 798 return map[p->y / ydiv][p->x / xdiv]; 799 } 800 801 static int map_width(int xdiv, int x0, int x1) 802 { 803 return (x1 / xdiv) - (x0 / xdiv) + 1; 804 } 805 806 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1) 807 { 808 char *p = map[yd] + (x0 / xdiv); 809 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2; 810 if (w >= 0) { 811 p += w; 812 while (*nice) 813 *p++ = *nice++; 814 } 815 } 816 817 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice, 818 struct tcm_area *a) 819 { 820 sprintf(nice, "%dK", tcm_sizeof(*a) * 4); 821 if (a->p0.y + 1 < a->p1.y) { 822 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, 823 256 - 1); 824 } else if (a->p0.y < a->p1.y) { 825 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1)) 826 text_map(map, xdiv, nice, a->p0.y / ydiv, 827 a->p0.x + xdiv, 256 - 1); 828 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) 829 text_map(map, xdiv, nice, a->p1.y / ydiv, 830 0, a->p1.y - xdiv); 831 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) { 832 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x); 833 } 834 } 835 836 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice, 837 struct tcm_area *a) 838 { 839 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a)); 840 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) 841 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 842 a->p0.x, a->p1.x); 843 } 844 845 int tiler_map_show(struct seq_file *s, void *arg) 846 { 847 int xdiv = 2, ydiv = 1; 848 char **map = NULL, *global_map; 849 struct tiler_block *block; 850 struct tcm_area a, p; 851 int i; 852 const char *m2d = alphabet; 853 const char *a2d = special; 854 const char *m2dp = m2d, *a2dp = a2d; 855 char nice[128]; 856 int h_adj; 857 int w_adj; 858 unsigned long flags; 859 int lut_idx; 860 861 862 if (!omap_dmm) { 863 /* early return if dmm/tiler device is not initialized */ 864 return 0; 865 } 866 867 h_adj = omap_dmm->container_height / ydiv; 868 w_adj = omap_dmm->container_width / xdiv; 869 870 map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL); 871 global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL); 872 873 if (!map || !global_map) 874 goto error; 875 876 for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) { 877 memset(map, 0, h_adj * sizeof(*map)); 878 memset(global_map, ' ', (w_adj + 1) * h_adj); 879 880 for (i = 0; i < omap_dmm->container_height; i++) { 881 map[i] = global_map + i * (w_adj + 1); 882 map[i][w_adj] = 0; 883 } 884 885 spin_lock_irqsave(&list_lock, flags); 886 887 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) { 888 if (block->area.tcm == omap_dmm->tcm[lut_idx]) { 889 if (block->fmt != TILFMT_PAGE) { 890 fill_map(map, xdiv, ydiv, &block->area, 891 *m2dp, true); 892 if (!*++a2dp) 893 a2dp = a2d; 894 if (!*++m2dp) 895 m2dp = m2d; 896 map_2d_info(map, xdiv, ydiv, nice, 897 &block->area); 898 } else { 899 bool start = read_map_pt(map, xdiv, 900 ydiv, &block->area.p0) == ' '; 901 bool end = read_map_pt(map, xdiv, ydiv, 902 &block->area.p1) == ' '; 903 904 tcm_for_each_slice(a, block->area, p) 905 fill_map(map, xdiv, ydiv, &a, 906 '=', true); 907 fill_map_pt(map, xdiv, ydiv, 908 &block->area.p0, 909 start ? '<' : 'X'); 910 fill_map_pt(map, xdiv, ydiv, 911 &block->area.p1, 912 end ? '>' : 'X'); 913 map_1d_info(map, xdiv, ydiv, nice, 914 &block->area); 915 } 916 } 917 } 918 919 spin_unlock_irqrestore(&list_lock, flags); 920 921 if (s) { 922 seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx); 923 for (i = 0; i < 128; i++) 924 seq_printf(s, "%03d:%s\n", i, map[i]); 925 seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx); 926 } else { 927 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n", 928 lut_idx); 929 for (i = 0; i < 128; i++) 930 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]); 931 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n", 932 lut_idx); 933 } 934 } 935 936 error: 937 kfree(map); 938 kfree(global_map); 939 940 return 0; 941 } 942 #endif 943 944 #ifdef CONFIG_PM 945 static int omap_dmm_resume(struct device *dev) 946 { 947 struct tcm_area area; 948 int i; 949 950 if (!omap_dmm) 951 return -ENODEV; 952 953 area = (struct tcm_area) { 954 .tcm = NULL, 955 .p1.x = omap_dmm->container_width - 1, 956 .p1.y = omap_dmm->container_height - 1, 957 }; 958 959 /* initialize all LUTs to dummy page entries */ 960 for (i = 0; i < omap_dmm->num_lut; i++) { 961 area.tcm = omap_dmm->tcm[i]; 962 if (fill(&area, NULL, 0, 0, true)) 963 dev_err(dev, "refill failed"); 964 } 965 966 return 0; 967 } 968 969 static const struct dev_pm_ops omap_dmm_pm_ops = { 970 .resume = omap_dmm_resume, 971 }; 972 #endif 973 974 #if defined(CONFIG_OF) 975 static const struct of_device_id dmm_of_match[] = { 976 { .compatible = "ti,omap4-dmm", }, 977 { .compatible = "ti,omap5-dmm", }, 978 {}, 979 }; 980 #endif 981 982 struct platform_driver omap_dmm_driver = { 983 .probe = omap_dmm_probe, 984 .remove = omap_dmm_remove, 985 .driver = { 986 .owner = THIS_MODULE, 987 .name = DMM_DRIVER_NAME, 988 .of_match_table = of_match_ptr(dmm_of_match), 989 #ifdef CONFIG_PM 990 .pm = &omap_dmm_pm_ops, 991 #endif 992 }, 993 }; 994 995 MODULE_LICENSE("GPL v2"); 996 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>"); 997 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver"); 998 MODULE_ALIAS("platform:" DMM_DRIVER_NAME); 999