1 /* 2 * DMM IOMMU driver support functions for TI OMAP processors. 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * Author: Rob Clark <rob@ti.com> 6 * Andy Gross <andy.gross@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/completion.h> 19 #include <linux/delay.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/dmaengine.h> 22 #include <linux/errno.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/list.h> 26 #include <linux/mm.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> /* platform_device() */ 29 #include <linux/sched.h> 30 #include <linux/seq_file.h> 31 #include <linux/slab.h> 32 #include <linux/time.h> 33 #include <linux/vmalloc.h> 34 #include <linux/wait.h> 35 36 #include "omap_dmm_tiler.h" 37 #include "omap_dmm_priv.h" 38 39 #define DMM_DRIVER_NAME "dmm" 40 41 /* mappings for associating views to luts */ 42 static struct tcm *containers[TILFMT_NFORMATS]; 43 static struct dmm *omap_dmm; 44 45 #if defined(CONFIG_OF) 46 static const struct of_device_id dmm_of_match[]; 47 #endif 48 49 /* global spinlock for protecting lists */ 50 static DEFINE_SPINLOCK(list_lock); 51 52 /* Geometry table */ 53 #define GEOM(xshift, yshift, bytes_per_pixel) { \ 54 .x_shft = (xshift), \ 55 .y_shft = (yshift), \ 56 .cpp = (bytes_per_pixel), \ 57 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \ 58 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \ 59 } 60 61 static const struct { 62 u32 x_shft; /* unused X-bits (as part of bpp) */ 63 u32 y_shft; /* unused Y-bits (as part of bpp) */ 64 u32 cpp; /* bytes/chars per pixel */ 65 u32 slot_w; /* width of each slot (in pixels) */ 66 u32 slot_h; /* height of each slot (in pixels) */ 67 } geom[TILFMT_NFORMATS] = { 68 [TILFMT_8BIT] = GEOM(0, 0, 1), 69 [TILFMT_16BIT] = GEOM(0, 1, 2), 70 [TILFMT_32BIT] = GEOM(1, 1, 4), 71 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1), 72 }; 73 74 75 /* lookup table for registers w/ per-engine instances */ 76 static const u32 reg[][4] = { 77 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, 78 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, 79 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, 80 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3}, 81 }; 82 83 static int dmm_dma_copy(struct dmm *dmm, dma_addr_t src, dma_addr_t dst) 84 { 85 struct dma_device *dma_dev = dmm->wa_dma_chan->device; 86 struct dma_async_tx_descriptor *tx; 87 enum dma_status status; 88 dma_cookie_t cookie; 89 90 tx = dma_dev->device_prep_dma_memcpy(dmm->wa_dma_chan, dst, src, 4, 0); 91 if (!tx) { 92 dev_err(dmm->dev, "Failed to prepare DMA memcpy\n"); 93 return -EIO; 94 } 95 96 cookie = tx->tx_submit(tx); 97 if (dma_submit_error(cookie)) { 98 dev_err(dmm->dev, "Failed to do DMA tx_submit\n"); 99 return -EIO; 100 } 101 102 dma_async_issue_pending(dmm->wa_dma_chan); 103 status = dma_sync_wait(dmm->wa_dma_chan, cookie); 104 if (status != DMA_COMPLETE) 105 dev_err(dmm->dev, "i878 wa DMA copy failure\n"); 106 107 dmaengine_terminate_all(dmm->wa_dma_chan); 108 return 0; 109 } 110 111 static u32 dmm_read_wa(struct dmm *dmm, u32 reg) 112 { 113 dma_addr_t src, dst; 114 int r; 115 116 src = dmm->phys_base + reg; 117 dst = dmm->wa_dma_handle; 118 119 r = dmm_dma_copy(dmm, src, dst); 120 if (r) { 121 dev_err(dmm->dev, "sDMA read transfer timeout\n"); 122 return readl(dmm->base + reg); 123 } 124 125 /* 126 * As per i878 workaround, the DMA is used to access the DMM registers. 127 * Make sure that the readl is not moved by the compiler or the CPU 128 * earlier than the DMA finished writing the value to memory. 129 */ 130 rmb(); 131 return readl(dmm->wa_dma_data); 132 } 133 134 static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg) 135 { 136 dma_addr_t src, dst; 137 int r; 138 139 writel(val, dmm->wa_dma_data); 140 /* 141 * As per i878 workaround, the DMA is used to access the DMM registers. 142 * Make sure that the writel is not moved by the compiler or the CPU, so 143 * the data will be in place before we start the DMA to do the actual 144 * register write. 145 */ 146 wmb(); 147 148 src = dmm->wa_dma_handle; 149 dst = dmm->phys_base + reg; 150 151 r = dmm_dma_copy(dmm, src, dst); 152 if (r) { 153 dev_err(dmm->dev, "sDMA write transfer timeout\n"); 154 writel(val, dmm->base + reg); 155 } 156 } 157 158 static u32 dmm_read(struct dmm *dmm, u32 reg) 159 { 160 if (dmm->dmm_workaround) { 161 u32 v; 162 unsigned long flags; 163 164 spin_lock_irqsave(&dmm->wa_lock, flags); 165 v = dmm_read_wa(dmm, reg); 166 spin_unlock_irqrestore(&dmm->wa_lock, flags); 167 168 return v; 169 } else { 170 return readl(dmm->base + reg); 171 } 172 } 173 174 static void dmm_write(struct dmm *dmm, u32 val, u32 reg) 175 { 176 if (dmm->dmm_workaround) { 177 unsigned long flags; 178 179 spin_lock_irqsave(&dmm->wa_lock, flags); 180 dmm_write_wa(dmm, val, reg); 181 spin_unlock_irqrestore(&dmm->wa_lock, flags); 182 } else { 183 writel(val, dmm->base + reg); 184 } 185 } 186 187 static int dmm_workaround_init(struct dmm *dmm) 188 { 189 dma_cap_mask_t mask; 190 191 spin_lock_init(&dmm->wa_lock); 192 193 dmm->wa_dma_data = dma_alloc_coherent(dmm->dev, sizeof(u32), 194 &dmm->wa_dma_handle, GFP_KERNEL); 195 if (!dmm->wa_dma_data) 196 return -ENOMEM; 197 198 dma_cap_zero(mask); 199 dma_cap_set(DMA_MEMCPY, mask); 200 201 dmm->wa_dma_chan = dma_request_channel(mask, NULL, NULL); 202 if (!dmm->wa_dma_chan) { 203 dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle); 204 return -ENODEV; 205 } 206 207 return 0; 208 } 209 210 static void dmm_workaround_uninit(struct dmm *dmm) 211 { 212 dma_release_channel(dmm->wa_dma_chan); 213 214 dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle); 215 } 216 217 /* simple allocator to grab next 16 byte aligned memory from txn */ 218 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) 219 { 220 void *ptr; 221 struct refill_engine *engine = txn->engine_handle; 222 223 /* dmm programming requires 16 byte aligned addresses */ 224 txn->current_pa = round_up(txn->current_pa, 16); 225 txn->current_va = (void *)round_up((long)txn->current_va, 16); 226 227 ptr = txn->current_va; 228 *pa = txn->current_pa; 229 230 txn->current_pa += sz; 231 txn->current_va += sz; 232 233 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); 234 235 return ptr; 236 } 237 238 /* check status and spin until wait_mask comes true */ 239 static int wait_status(struct refill_engine *engine, u32 wait_mask) 240 { 241 struct dmm *dmm = engine->dmm; 242 u32 r = 0, err, i; 243 244 i = DMM_FIXED_RETRY_COUNT; 245 while (true) { 246 r = dmm_read(dmm, reg[PAT_STATUS][engine->id]); 247 err = r & DMM_PATSTATUS_ERR; 248 if (err) { 249 dev_err(dmm->dev, 250 "%s: error (engine%d). PAT_STATUS: 0x%08x\n", 251 __func__, engine->id, r); 252 return -EFAULT; 253 } 254 255 if ((r & wait_mask) == wait_mask) 256 break; 257 258 if (--i == 0) { 259 dev_err(dmm->dev, 260 "%s: timeout (engine%d). PAT_STATUS: 0x%08x\n", 261 __func__, engine->id, r); 262 return -ETIMEDOUT; 263 } 264 265 udelay(1); 266 } 267 268 return 0; 269 } 270 271 static void release_engine(struct refill_engine *engine) 272 { 273 unsigned long flags; 274 275 spin_lock_irqsave(&list_lock, flags); 276 list_add(&engine->idle_node, &omap_dmm->idle_head); 277 spin_unlock_irqrestore(&list_lock, flags); 278 279 atomic_inc(&omap_dmm->engine_counter); 280 wake_up_interruptible(&omap_dmm->engine_queue); 281 } 282 283 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) 284 { 285 struct dmm *dmm = arg; 286 u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS); 287 int i; 288 289 /* ack IRQ */ 290 dmm_write(dmm, status, DMM_PAT_IRQSTATUS); 291 292 for (i = 0; i < dmm->num_engines; i++) { 293 if (status & DMM_IRQSTAT_ERR_MASK) 294 dev_err(dmm->dev, 295 "irq error(engine%d): IRQSTAT 0x%02x\n", 296 i, status & 0xff); 297 298 if (status & DMM_IRQSTAT_LST) { 299 if (dmm->engines[i].async) 300 release_engine(&dmm->engines[i]); 301 302 complete(&dmm->engines[i].compl); 303 } 304 305 status >>= 8; 306 } 307 308 return IRQ_HANDLED; 309 } 310 311 /** 312 * Get a handle for a DMM transaction 313 */ 314 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) 315 { 316 struct dmm_txn *txn = NULL; 317 struct refill_engine *engine = NULL; 318 int ret; 319 unsigned long flags; 320 321 322 /* wait until an engine is available */ 323 ret = wait_event_interruptible(omap_dmm->engine_queue, 324 atomic_add_unless(&omap_dmm->engine_counter, -1, 0)); 325 if (ret) 326 return ERR_PTR(ret); 327 328 /* grab an idle engine */ 329 spin_lock_irqsave(&list_lock, flags); 330 if (!list_empty(&dmm->idle_head)) { 331 engine = list_entry(dmm->idle_head.next, struct refill_engine, 332 idle_node); 333 list_del(&engine->idle_node); 334 } 335 spin_unlock_irqrestore(&list_lock, flags); 336 337 BUG_ON(!engine); 338 339 txn = &engine->txn; 340 engine->tcm = tcm; 341 txn->engine_handle = engine; 342 txn->last_pat = NULL; 343 txn->current_va = engine->refill_va; 344 txn->current_pa = engine->refill_pa; 345 346 return txn; 347 } 348 349 /** 350 * Add region to DMM transaction. If pages or pages[i] is NULL, then the 351 * corresponding slot is cleared (ie. dummy_pa is programmed) 352 */ 353 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, 354 struct page **pages, u32 npages, u32 roll) 355 { 356 dma_addr_t pat_pa = 0, data_pa = 0; 357 u32 *data; 358 struct pat *pat; 359 struct refill_engine *engine = txn->engine_handle; 360 int columns = (1 + area->x1 - area->x0); 361 int rows = (1 + area->y1 - area->y0); 362 int i = columns*rows; 363 364 pat = alloc_dma(txn, sizeof(*pat), &pat_pa); 365 366 if (txn->last_pat) 367 txn->last_pat->next_pa = (u32)pat_pa; 368 369 pat->area = *area; 370 371 /* adjust Y coordinates based off of container parameters */ 372 pat->area.y0 += engine->tcm->y_offset; 373 pat->area.y1 += engine->tcm->y_offset; 374 375 pat->ctrl = (struct pat_ctrl){ 376 .start = 1, 377 .lut_id = engine->tcm->lut_id, 378 }; 379 380 data = alloc_dma(txn, 4*i, &data_pa); 381 /* FIXME: what if data_pa is more than 32-bit ? */ 382 pat->data_pa = data_pa; 383 384 while (i--) { 385 int n = i + roll; 386 if (n >= npages) 387 n -= npages; 388 data[i] = (pages && pages[n]) ? 389 page_to_phys(pages[n]) : engine->dmm->dummy_pa; 390 } 391 392 txn->last_pat = pat; 393 394 return; 395 } 396 397 /** 398 * Commit the DMM transaction. 399 */ 400 static int dmm_txn_commit(struct dmm_txn *txn, bool wait) 401 { 402 int ret = 0; 403 struct refill_engine *engine = txn->engine_handle; 404 struct dmm *dmm = engine->dmm; 405 406 if (!txn->last_pat) { 407 dev_err(engine->dmm->dev, "need at least one txn\n"); 408 ret = -EINVAL; 409 goto cleanup; 410 } 411 412 txn->last_pat->next_pa = 0; 413 /* ensure that the written descriptors are visible to DMM */ 414 wmb(); 415 416 /* 417 * NOTE: the wmb() above should be enough, but there seems to be a bug 418 * in OMAP's memory barrier implementation, which in some rare cases may 419 * cause the writes not to be observable after wmb(). 420 */ 421 422 /* read back to ensure the data is in RAM */ 423 readl(&txn->last_pat->next_pa); 424 425 /* write to PAT_DESCR to clear out any pending transaction */ 426 dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]); 427 428 /* wait for engine ready: */ 429 ret = wait_status(engine, DMM_PATSTATUS_READY); 430 if (ret) { 431 ret = -EFAULT; 432 goto cleanup; 433 } 434 435 /* mark whether it is async to denote list management in IRQ handler */ 436 engine->async = wait ? false : true; 437 reinit_completion(&engine->compl); 438 /* verify that the irq handler sees the 'async' and completion value */ 439 smp_mb(); 440 441 /* kick reload */ 442 dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]); 443 444 if (wait) { 445 if (!wait_for_completion_timeout(&engine->compl, 446 msecs_to_jiffies(100))) { 447 dev_err(dmm->dev, "timed out waiting for done\n"); 448 ret = -ETIMEDOUT; 449 goto cleanup; 450 } 451 452 /* Check the engine status before continue */ 453 ret = wait_status(engine, DMM_PATSTATUS_READY | 454 DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE); 455 } 456 457 cleanup: 458 /* only place engine back on list if we are done with it */ 459 if (ret || wait) 460 release_engine(engine); 461 462 return ret; 463 } 464 465 /* 466 * DMM programming 467 */ 468 static int fill(struct tcm_area *area, struct page **pages, 469 u32 npages, u32 roll, bool wait) 470 { 471 int ret = 0; 472 struct tcm_area slice, area_s; 473 struct dmm_txn *txn; 474 475 /* 476 * FIXME 477 * 478 * Asynchronous fill does not work reliably, as the driver does not 479 * handle errors in the async code paths. The fill operation may 480 * silently fail, leading to leaking DMM engines, which may eventually 481 * lead to deadlock if we run out of DMM engines. 482 * 483 * For now, always set 'wait' so that we only use sync fills. Async 484 * fills should be fixed, or alternatively we could decide to only 485 * support sync fills and so the whole async code path could be removed. 486 */ 487 488 wait = true; 489 490 txn = dmm_txn_init(omap_dmm, area->tcm); 491 if (IS_ERR_OR_NULL(txn)) 492 return -ENOMEM; 493 494 tcm_for_each_slice(slice, *area, area_s) { 495 struct pat_area p_area = { 496 .x0 = slice.p0.x, .y0 = slice.p0.y, 497 .x1 = slice.p1.x, .y1 = slice.p1.y, 498 }; 499 500 dmm_txn_append(txn, &p_area, pages, npages, roll); 501 502 roll += tcm_sizeof(slice); 503 } 504 505 ret = dmm_txn_commit(txn, wait); 506 507 return ret; 508 } 509 510 /* 511 * Pin/unpin 512 */ 513 514 /* note: slots for which pages[i] == NULL are filled w/ dummy page 515 */ 516 int tiler_pin(struct tiler_block *block, struct page **pages, 517 u32 npages, u32 roll, bool wait) 518 { 519 int ret; 520 521 ret = fill(&block->area, pages, npages, roll, wait); 522 523 if (ret) 524 tiler_unpin(block); 525 526 return ret; 527 } 528 529 int tiler_unpin(struct tiler_block *block) 530 { 531 return fill(&block->area, NULL, 0, 0, false); 532 } 533 534 /* 535 * Reserve/release 536 */ 537 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w, 538 u16 h, u16 align) 539 { 540 struct tiler_block *block; 541 u32 min_align = 128; 542 int ret; 543 unsigned long flags; 544 u32 slot_bytes; 545 546 block = kzalloc(sizeof(*block), GFP_KERNEL); 547 if (!block) 548 return ERR_PTR(-ENOMEM); 549 550 BUG_ON(!validfmt(fmt)); 551 552 /* convert width/height to slots */ 553 w = DIV_ROUND_UP(w, geom[fmt].slot_w); 554 h = DIV_ROUND_UP(h, geom[fmt].slot_h); 555 556 /* convert alignment to slots */ 557 slot_bytes = geom[fmt].slot_w * geom[fmt].cpp; 558 min_align = max(min_align, slot_bytes); 559 align = (align > min_align) ? ALIGN(align, min_align) : min_align; 560 align /= slot_bytes; 561 562 block->fmt = fmt; 563 564 ret = tcm_reserve_2d(containers[fmt], w, h, align, -1, slot_bytes, 565 &block->area); 566 if (ret) { 567 kfree(block); 568 return ERR_PTR(-ENOMEM); 569 } 570 571 /* add to allocation list */ 572 spin_lock_irqsave(&list_lock, flags); 573 list_add(&block->alloc_node, &omap_dmm->alloc_head); 574 spin_unlock_irqrestore(&list_lock, flags); 575 576 return block; 577 } 578 579 struct tiler_block *tiler_reserve_1d(size_t size) 580 { 581 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); 582 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 583 unsigned long flags; 584 585 if (!block) 586 return ERR_PTR(-ENOMEM); 587 588 block->fmt = TILFMT_PAGE; 589 590 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages, 591 &block->area)) { 592 kfree(block); 593 return ERR_PTR(-ENOMEM); 594 } 595 596 spin_lock_irqsave(&list_lock, flags); 597 list_add(&block->alloc_node, &omap_dmm->alloc_head); 598 spin_unlock_irqrestore(&list_lock, flags); 599 600 return block; 601 } 602 603 /* note: if you have pin'd pages, you should have already unpin'd first! */ 604 int tiler_release(struct tiler_block *block) 605 { 606 int ret = tcm_free(&block->area); 607 unsigned long flags; 608 609 if (block->area.tcm) 610 dev_err(omap_dmm->dev, "failed to release block\n"); 611 612 spin_lock_irqsave(&list_lock, flags); 613 list_del(&block->alloc_node); 614 spin_unlock_irqrestore(&list_lock, flags); 615 616 kfree(block); 617 return ret; 618 } 619 620 /* 621 * Utils 622 */ 623 624 /* calculate the tiler space address of a pixel in a view orientation... 625 * below description copied from the display subsystem section of TRM: 626 * 627 * When the TILER is addressed, the bits: 628 * [28:27] = 0x0 for 8-bit tiled 629 * 0x1 for 16-bit tiled 630 * 0x2 for 32-bit tiled 631 * 0x3 for page mode 632 * [31:29] = 0x0 for 0-degree view 633 * 0x1 for 180-degree view + mirroring 634 * 0x2 for 0-degree view + mirroring 635 * 0x3 for 180-degree view 636 * 0x4 for 270-degree view + mirroring 637 * 0x5 for 270-degree view 638 * 0x6 for 90-degree view 639 * 0x7 for 90-degree view + mirroring 640 * Otherwise the bits indicated the corresponding bit address to access 641 * the SDRAM. 642 */ 643 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y) 644 { 645 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment; 646 647 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft; 648 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft; 649 alignment = geom[fmt].x_shft + geom[fmt].y_shft; 650 651 /* validate coordinate */ 652 x_mask = MASK(x_bits); 653 y_mask = MASK(y_bits); 654 655 if (x < 0 || x > x_mask || y < 0 || y > y_mask) { 656 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u", 657 x, x, x_mask, y, y, y_mask); 658 return 0; 659 } 660 661 /* account for mirroring */ 662 if (orient & MASK_X_INVERT) 663 x ^= x_mask; 664 if (orient & MASK_Y_INVERT) 665 y ^= y_mask; 666 667 /* get coordinate address */ 668 if (orient & MASK_XY_FLIP) 669 tmp = ((x << y_bits) + y); 670 else 671 tmp = ((y << x_bits) + x); 672 673 return TIL_ADDR((tmp << alignment), orient, fmt); 674 } 675 676 dma_addr_t tiler_ssptr(struct tiler_block *block) 677 { 678 BUG_ON(!validfmt(block->fmt)); 679 680 return TILVIEW_8BIT + tiler_get_address(block->fmt, 0, 681 block->area.p0.x * geom[block->fmt].slot_w, 682 block->area.p0.y * geom[block->fmt].slot_h); 683 } 684 685 dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient, 686 u32 x, u32 y) 687 { 688 struct tcm_pt *p = &block->area.p0; 689 BUG_ON(!validfmt(block->fmt)); 690 691 return tiler_get_address(block->fmt, orient, 692 (p->x * geom[block->fmt].slot_w) + x, 693 (p->y * geom[block->fmt].slot_h) + y); 694 } 695 696 void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h) 697 { 698 BUG_ON(!validfmt(fmt)); 699 *w = round_up(*w, geom[fmt].slot_w); 700 *h = round_up(*h, geom[fmt].slot_h); 701 } 702 703 u32 tiler_stride(enum tiler_fmt fmt, u32 orient) 704 { 705 BUG_ON(!validfmt(fmt)); 706 707 if (orient & MASK_XY_FLIP) 708 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft); 709 else 710 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); 711 } 712 713 size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h) 714 { 715 tiler_align(fmt, &w, &h); 716 return geom[fmt].cpp * w * h; 717 } 718 719 size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h) 720 { 721 BUG_ON(!validfmt(fmt)); 722 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; 723 } 724 725 u32 tiler_get_cpu_cache_flags(void) 726 { 727 return omap_dmm->plat_data->cpu_cache_flags; 728 } 729 730 bool dmm_is_available(void) 731 { 732 return omap_dmm ? true : false; 733 } 734 735 static int omap_dmm_remove(struct platform_device *dev) 736 { 737 struct tiler_block *block, *_block; 738 int i; 739 unsigned long flags; 740 741 if (omap_dmm) { 742 /* Disable all enabled interrupts */ 743 dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_CLR); 744 free_irq(omap_dmm->irq, omap_dmm); 745 746 /* free all area regions */ 747 spin_lock_irqsave(&list_lock, flags); 748 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head, 749 alloc_node) { 750 list_del(&block->alloc_node); 751 kfree(block); 752 } 753 spin_unlock_irqrestore(&list_lock, flags); 754 755 for (i = 0; i < omap_dmm->num_lut; i++) 756 if (omap_dmm->tcm && omap_dmm->tcm[i]) 757 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]); 758 kfree(omap_dmm->tcm); 759 760 kfree(omap_dmm->engines); 761 if (omap_dmm->refill_va) 762 dma_free_wc(omap_dmm->dev, 763 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 764 omap_dmm->refill_va, omap_dmm->refill_pa); 765 if (omap_dmm->dummy_page) 766 __free_page(omap_dmm->dummy_page); 767 768 if (omap_dmm->dmm_workaround) 769 dmm_workaround_uninit(omap_dmm); 770 771 iounmap(omap_dmm->base); 772 kfree(omap_dmm); 773 omap_dmm = NULL; 774 } 775 776 return 0; 777 } 778 779 static int omap_dmm_probe(struct platform_device *dev) 780 { 781 int ret = -EFAULT, i; 782 struct tcm_area area = {0}; 783 u32 hwinfo, pat_geom; 784 struct resource *mem; 785 786 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL); 787 if (!omap_dmm) 788 goto fail; 789 790 /* initialize lists */ 791 INIT_LIST_HEAD(&omap_dmm->alloc_head); 792 INIT_LIST_HEAD(&omap_dmm->idle_head); 793 794 init_waitqueue_head(&omap_dmm->engine_queue); 795 796 if (dev->dev.of_node) { 797 const struct of_device_id *match; 798 799 match = of_match_node(dmm_of_match, dev->dev.of_node); 800 if (!match) { 801 dev_err(&dev->dev, "failed to find matching device node\n"); 802 ret = -ENODEV; 803 goto fail; 804 } 805 806 omap_dmm->plat_data = match->data; 807 } 808 809 /* lookup hwmod data - base address and irq */ 810 mem = platform_get_resource(dev, IORESOURCE_MEM, 0); 811 if (!mem) { 812 dev_err(&dev->dev, "failed to get base address resource\n"); 813 goto fail; 814 } 815 816 omap_dmm->phys_base = mem->start; 817 omap_dmm->base = ioremap(mem->start, SZ_2K); 818 819 if (!omap_dmm->base) { 820 dev_err(&dev->dev, "failed to get dmm base address\n"); 821 goto fail; 822 } 823 824 omap_dmm->irq = platform_get_irq(dev, 0); 825 if (omap_dmm->irq < 0) { 826 dev_err(&dev->dev, "failed to get IRQ resource\n"); 827 goto fail; 828 } 829 830 omap_dmm->dev = &dev->dev; 831 832 if (of_machine_is_compatible("ti,dra7")) { 833 /* 834 * DRA7 Errata i878 says that MPU should not be used to access 835 * RAM and DMM at the same time. As it's not possible to prevent 836 * MPU accessing RAM, we need to access DMM via a proxy. 837 */ 838 if (!dmm_workaround_init(omap_dmm)) { 839 omap_dmm->dmm_workaround = true; 840 dev_info(&dev->dev, 841 "workaround for errata i878 in use\n"); 842 } else { 843 dev_warn(&dev->dev, 844 "failed to initialize work-around for i878\n"); 845 } 846 } 847 848 hwinfo = dmm_read(omap_dmm, DMM_PAT_HWINFO); 849 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; 850 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F; 851 omap_dmm->container_width = 256; 852 omap_dmm->container_height = 128; 853 854 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); 855 856 /* read out actual LUT width and height */ 857 pat_geom = dmm_read(omap_dmm, DMM_PAT_GEOMETRY); 858 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5; 859 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5; 860 861 /* increment LUT by one if on OMAP5 */ 862 /* LUT has twice the height, and is split into a separate container */ 863 if (omap_dmm->lut_height != omap_dmm->container_height) 864 omap_dmm->num_lut++; 865 866 /* initialize DMM registers */ 867 dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0); 868 dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1); 869 dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0); 870 dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE); 871 dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0); 872 dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1); 873 874 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32); 875 if (!omap_dmm->dummy_page) { 876 dev_err(&dev->dev, "could not allocate dummy page\n"); 877 ret = -ENOMEM; 878 goto fail; 879 } 880 881 /* set dma mask for device */ 882 ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 883 if (ret) 884 goto fail; 885 886 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page); 887 888 /* alloc refill memory */ 889 omap_dmm->refill_va = dma_alloc_wc(&dev->dev, 890 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 891 &omap_dmm->refill_pa, GFP_KERNEL); 892 if (!omap_dmm->refill_va) { 893 dev_err(&dev->dev, "could not allocate refill memory\n"); 894 goto fail; 895 } 896 897 /* alloc engines */ 898 omap_dmm->engines = kcalloc(omap_dmm->num_engines, 899 sizeof(*omap_dmm->engines), GFP_KERNEL); 900 if (!omap_dmm->engines) { 901 ret = -ENOMEM; 902 goto fail; 903 } 904 905 for (i = 0; i < omap_dmm->num_engines; i++) { 906 omap_dmm->engines[i].id = i; 907 omap_dmm->engines[i].dmm = omap_dmm; 908 omap_dmm->engines[i].refill_va = omap_dmm->refill_va + 909 (REFILL_BUFFER_SIZE * i); 910 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + 911 (REFILL_BUFFER_SIZE * i); 912 init_completion(&omap_dmm->engines[i].compl); 913 914 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); 915 } 916 917 omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm), 918 GFP_KERNEL); 919 if (!omap_dmm->tcm) { 920 ret = -ENOMEM; 921 goto fail; 922 } 923 924 /* init containers */ 925 /* Each LUT is associated with a TCM (container manager). We use the 926 lut_id to denote the lut_id used to identify the correct LUT for 927 programming during reill operations */ 928 for (i = 0; i < omap_dmm->num_lut; i++) { 929 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width, 930 omap_dmm->container_height); 931 932 if (!omap_dmm->tcm[i]) { 933 dev_err(&dev->dev, "failed to allocate container\n"); 934 ret = -ENOMEM; 935 goto fail; 936 } 937 938 omap_dmm->tcm[i]->lut_id = i; 939 } 940 941 /* assign access mode containers to applicable tcm container */ 942 /* OMAP 4 has 1 container for all 4 views */ 943 /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */ 944 containers[TILFMT_8BIT] = omap_dmm->tcm[0]; 945 containers[TILFMT_16BIT] = omap_dmm->tcm[0]; 946 containers[TILFMT_32BIT] = omap_dmm->tcm[0]; 947 948 if (omap_dmm->container_height != omap_dmm->lut_height) { 949 /* second LUT is used for PAGE mode. Programming must use 950 y offset that is added to all y coordinates. LUT id is still 951 0, because it is the same LUT, just the upper 128 lines */ 952 containers[TILFMT_PAGE] = omap_dmm->tcm[1]; 953 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET; 954 omap_dmm->tcm[1]->lut_id = 0; 955 } else { 956 containers[TILFMT_PAGE] = omap_dmm->tcm[0]; 957 } 958 959 area = (struct tcm_area) { 960 .tcm = NULL, 961 .p1.x = omap_dmm->container_width - 1, 962 .p1.y = omap_dmm->container_height - 1, 963 }; 964 965 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED, 966 "omap_dmm_irq_handler", omap_dmm); 967 968 if (ret) { 969 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n", 970 omap_dmm->irq, ret); 971 omap_dmm->irq = -1; 972 goto fail; 973 } 974 975 /* Enable all interrupts for each refill engine except 976 * ERR_LUT_MISS<n> (which is just advisory, and we don't care 977 * about because we want to be able to refill live scanout 978 * buffers for accelerated pan/scroll) and FILL_DSC<n> which 979 * we just generally don't care about. 980 */ 981 dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET); 982 983 /* initialize all LUTs to dummy page entries */ 984 for (i = 0; i < omap_dmm->num_lut; i++) { 985 area.tcm = omap_dmm->tcm[i]; 986 if (fill(&area, NULL, 0, 0, true)) 987 dev_err(omap_dmm->dev, "refill failed"); 988 } 989 990 dev_info(omap_dmm->dev, "initialized all PAT entries\n"); 991 992 return 0; 993 994 fail: 995 if (omap_dmm_remove(dev)) 996 dev_err(&dev->dev, "cleanup failed\n"); 997 return ret; 998 } 999 1000 /* 1001 * debugfs support 1002 */ 1003 1004 #ifdef CONFIG_DEBUG_FS 1005 1006 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz" 1007 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; 1008 static const char *special = ".,:;'\"`~!^-+"; 1009 1010 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a, 1011 char c, bool ovw) 1012 { 1013 int x, y; 1014 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) 1015 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) 1016 if (map[y][x] == ' ' || ovw) 1017 map[y][x] = c; 1018 } 1019 1020 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p, 1021 char c) 1022 { 1023 map[p->y / ydiv][p->x / xdiv] = c; 1024 } 1025 1026 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p) 1027 { 1028 return map[p->y / ydiv][p->x / xdiv]; 1029 } 1030 1031 static int map_width(int xdiv, int x0, int x1) 1032 { 1033 return (x1 / xdiv) - (x0 / xdiv) + 1; 1034 } 1035 1036 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1) 1037 { 1038 char *p = map[yd] + (x0 / xdiv); 1039 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2; 1040 if (w >= 0) { 1041 p += w; 1042 while (*nice) 1043 *p++ = *nice++; 1044 } 1045 } 1046 1047 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice, 1048 struct tcm_area *a) 1049 { 1050 sprintf(nice, "%dK", tcm_sizeof(*a) * 4); 1051 if (a->p0.y + 1 < a->p1.y) { 1052 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, 1053 256 - 1); 1054 } else if (a->p0.y < a->p1.y) { 1055 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1)) 1056 text_map(map, xdiv, nice, a->p0.y / ydiv, 1057 a->p0.x + xdiv, 256 - 1); 1058 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) 1059 text_map(map, xdiv, nice, a->p1.y / ydiv, 1060 0, a->p1.y - xdiv); 1061 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) { 1062 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x); 1063 } 1064 } 1065 1066 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice, 1067 struct tcm_area *a) 1068 { 1069 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a)); 1070 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) 1071 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 1072 a->p0.x, a->p1.x); 1073 } 1074 1075 int tiler_map_show(struct seq_file *s, void *arg) 1076 { 1077 int xdiv = 2, ydiv = 1; 1078 char **map = NULL, *global_map; 1079 struct tiler_block *block; 1080 struct tcm_area a, p; 1081 int i; 1082 const char *m2d = alphabet; 1083 const char *a2d = special; 1084 const char *m2dp = m2d, *a2dp = a2d; 1085 char nice[128]; 1086 int h_adj; 1087 int w_adj; 1088 unsigned long flags; 1089 int lut_idx; 1090 1091 1092 if (!omap_dmm) { 1093 /* early return if dmm/tiler device is not initialized */ 1094 return 0; 1095 } 1096 1097 h_adj = omap_dmm->container_height / ydiv; 1098 w_adj = omap_dmm->container_width / xdiv; 1099 1100 map = kmalloc_array(h_adj, sizeof(*map), GFP_KERNEL); 1101 global_map = kmalloc_array(w_adj + 1, h_adj, GFP_KERNEL); 1102 1103 if (!map || !global_map) 1104 goto error; 1105 1106 for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) { 1107 memset(map, 0, h_adj * sizeof(*map)); 1108 memset(global_map, ' ', (w_adj + 1) * h_adj); 1109 1110 for (i = 0; i < omap_dmm->container_height; i++) { 1111 map[i] = global_map + i * (w_adj + 1); 1112 map[i][w_adj] = 0; 1113 } 1114 1115 spin_lock_irqsave(&list_lock, flags); 1116 1117 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) { 1118 if (block->area.tcm == omap_dmm->tcm[lut_idx]) { 1119 if (block->fmt != TILFMT_PAGE) { 1120 fill_map(map, xdiv, ydiv, &block->area, 1121 *m2dp, true); 1122 if (!*++a2dp) 1123 a2dp = a2d; 1124 if (!*++m2dp) 1125 m2dp = m2d; 1126 map_2d_info(map, xdiv, ydiv, nice, 1127 &block->area); 1128 } else { 1129 bool start = read_map_pt(map, xdiv, 1130 ydiv, &block->area.p0) == ' '; 1131 bool end = read_map_pt(map, xdiv, ydiv, 1132 &block->area.p1) == ' '; 1133 1134 tcm_for_each_slice(a, block->area, p) 1135 fill_map(map, xdiv, ydiv, &a, 1136 '=', true); 1137 fill_map_pt(map, xdiv, ydiv, 1138 &block->area.p0, 1139 start ? '<' : 'X'); 1140 fill_map_pt(map, xdiv, ydiv, 1141 &block->area.p1, 1142 end ? '>' : 'X'); 1143 map_1d_info(map, xdiv, ydiv, nice, 1144 &block->area); 1145 } 1146 } 1147 } 1148 1149 spin_unlock_irqrestore(&list_lock, flags); 1150 1151 if (s) { 1152 seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx); 1153 for (i = 0; i < 128; i++) 1154 seq_printf(s, "%03d:%s\n", i, map[i]); 1155 seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx); 1156 } else { 1157 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n", 1158 lut_idx); 1159 for (i = 0; i < 128; i++) 1160 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]); 1161 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n", 1162 lut_idx); 1163 } 1164 } 1165 1166 error: 1167 kfree(map); 1168 kfree(global_map); 1169 1170 return 0; 1171 } 1172 #endif 1173 1174 #ifdef CONFIG_PM_SLEEP 1175 static int omap_dmm_resume(struct device *dev) 1176 { 1177 struct tcm_area area; 1178 int i; 1179 1180 if (!omap_dmm) 1181 return -ENODEV; 1182 1183 area = (struct tcm_area) { 1184 .tcm = NULL, 1185 .p1.x = omap_dmm->container_width - 1, 1186 .p1.y = omap_dmm->container_height - 1, 1187 }; 1188 1189 /* initialize all LUTs to dummy page entries */ 1190 for (i = 0; i < omap_dmm->num_lut; i++) { 1191 area.tcm = omap_dmm->tcm[i]; 1192 if (fill(&area, NULL, 0, 0, true)) 1193 dev_err(dev, "refill failed"); 1194 } 1195 1196 return 0; 1197 } 1198 #endif 1199 1200 static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume); 1201 1202 #if defined(CONFIG_OF) 1203 static const struct dmm_platform_data dmm_omap4_platform_data = { 1204 .cpu_cache_flags = OMAP_BO_WC, 1205 }; 1206 1207 static const struct dmm_platform_data dmm_omap5_platform_data = { 1208 .cpu_cache_flags = OMAP_BO_UNCACHED, 1209 }; 1210 1211 static const struct of_device_id dmm_of_match[] = { 1212 { 1213 .compatible = "ti,omap4-dmm", 1214 .data = &dmm_omap4_platform_data, 1215 }, 1216 { 1217 .compatible = "ti,omap5-dmm", 1218 .data = &dmm_omap5_platform_data, 1219 }, 1220 {}, 1221 }; 1222 #endif 1223 1224 struct platform_driver omap_dmm_driver = { 1225 .probe = omap_dmm_probe, 1226 .remove = omap_dmm_remove, 1227 .driver = { 1228 .owner = THIS_MODULE, 1229 .name = DMM_DRIVER_NAME, 1230 .of_match_table = of_match_ptr(dmm_of_match), 1231 .pm = &omap_dmm_pm_ops, 1232 }, 1233 }; 1234 1235 MODULE_LICENSE("GPL v2"); 1236 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>"); 1237 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver"); 1238