1*b94b7353SCai Huoqing /* SPDX-License-Identifier: GPL-2.0-only */ 28bb0daffSRob Clark /* 31b409fdaSAlexander A. Klimov * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 48bb0daffSRob Clark * Author: Rob Clark <rob@ti.com> 58bb0daffSRob Clark * Andy Gross <andy.gross@ti.com> 68bb0daffSRob Clark */ 7bb5cdf8dSAndrew F. Davis 88bb0daffSRob Clark #ifndef OMAP_DMM_PRIV_H 98bb0daffSRob Clark #define OMAP_DMM_PRIV_H 108bb0daffSRob Clark 118bb0daffSRob Clark #define DMM_REVISION 0x000 128bb0daffSRob Clark #define DMM_HWINFO 0x004 138bb0daffSRob Clark #define DMM_LISA_HWINFO 0x008 148bb0daffSRob Clark #define DMM_DMM_SYSCONFIG 0x010 158bb0daffSRob Clark #define DMM_LISA_LOCK 0x01C 168bb0daffSRob Clark #define DMM_LISA_MAP__0 0x040 178bb0daffSRob Clark #define DMM_LISA_MAP__1 0x044 188bb0daffSRob Clark #define DMM_TILER_HWINFO 0x208 198bb0daffSRob Clark #define DMM_TILER_OR__0 0x220 208bb0daffSRob Clark #define DMM_TILER_OR__1 0x224 218bb0daffSRob Clark #define DMM_PAT_HWINFO 0x408 228bb0daffSRob Clark #define DMM_PAT_GEOMETRY 0x40C 238bb0daffSRob Clark #define DMM_PAT_CONFIG 0x410 248bb0daffSRob Clark #define DMM_PAT_VIEW__0 0x420 258bb0daffSRob Clark #define DMM_PAT_VIEW__1 0x424 268bb0daffSRob Clark #define DMM_PAT_VIEW_MAP__0 0x440 278bb0daffSRob Clark #define DMM_PAT_VIEW_MAP_BASE 0x460 288bb0daffSRob Clark #define DMM_PAT_IRQ_EOI 0x478 298bb0daffSRob Clark #define DMM_PAT_IRQSTATUS_RAW 0x480 308bb0daffSRob Clark #define DMM_PAT_IRQSTATUS 0x490 318bb0daffSRob Clark #define DMM_PAT_IRQENABLE_SET 0x4A0 328bb0daffSRob Clark #define DMM_PAT_IRQENABLE_CLR 0x4B0 338bb0daffSRob Clark #define DMM_PAT_STATUS__0 0x4C0 348bb0daffSRob Clark #define DMM_PAT_STATUS__1 0x4C4 358bb0daffSRob Clark #define DMM_PAT_STATUS__2 0x4C8 368bb0daffSRob Clark #define DMM_PAT_STATUS__3 0x4CC 378bb0daffSRob Clark #define DMM_PAT_DESCR__0 0x500 388bb0daffSRob Clark #define DMM_PAT_DESCR__1 0x510 398bb0daffSRob Clark #define DMM_PAT_DESCR__2 0x520 408bb0daffSRob Clark #define DMM_PAT_DESCR__3 0x530 418bb0daffSRob Clark #define DMM_PEG_HWINFO 0x608 428bb0daffSRob Clark #define DMM_PEG_PRIO 0x620 438bb0daffSRob Clark #define DMM_PEG_PRIO_PAT 0x640 448bb0daffSRob Clark 458bb0daffSRob Clark #define DMM_IRQSTAT_DST (1<<0) 468bb0daffSRob Clark #define DMM_IRQSTAT_LST (1<<1) 478bb0daffSRob Clark #define DMM_IRQSTAT_ERR_INV_DSC (1<<2) 488bb0daffSRob Clark #define DMM_IRQSTAT_ERR_INV_DATA (1<<3) 498bb0daffSRob Clark #define DMM_IRQSTAT_ERR_UPD_AREA (1<<4) 508bb0daffSRob Clark #define DMM_IRQSTAT_ERR_UPD_CTRL (1<<5) 518bb0daffSRob Clark #define DMM_IRQSTAT_ERR_UPD_DATA (1<<6) 528bb0daffSRob Clark #define DMM_IRQSTAT_ERR_LUT_MISS (1<<7) 538bb0daffSRob Clark 54b3d5a8d7SPeter Ujfalusi #define DMM_IRQSTAT_ERR_MASK (DMM_IRQSTAT_ERR_INV_DSC | \ 55b3d5a8d7SPeter Ujfalusi DMM_IRQSTAT_ERR_INV_DATA | \ 56b3d5a8d7SPeter Ujfalusi DMM_IRQSTAT_ERR_UPD_AREA | \ 57b3d5a8d7SPeter Ujfalusi DMM_IRQSTAT_ERR_UPD_CTRL | \ 58b3d5a8d7SPeter Ujfalusi DMM_IRQSTAT_ERR_UPD_DATA | \ 59b3d5a8d7SPeter Ujfalusi DMM_IRQSTAT_ERR_LUT_MISS) 608bb0daffSRob Clark 618bb0daffSRob Clark #define DMM_PATSTATUS_READY (1<<0) 628bb0daffSRob Clark #define DMM_PATSTATUS_VALID (1<<1) 638bb0daffSRob Clark #define DMM_PATSTATUS_RUN (1<<2) 648bb0daffSRob Clark #define DMM_PATSTATUS_DONE (1<<3) 658bb0daffSRob Clark #define DMM_PATSTATUS_LINKED (1<<4) 668bb0daffSRob Clark #define DMM_PATSTATUS_BYPASSED (1<<7) 678bb0daffSRob Clark #define DMM_PATSTATUS_ERR_INV_DESCR (1<<10) 688bb0daffSRob Clark #define DMM_PATSTATUS_ERR_INV_DATA (1<<11) 698bb0daffSRob Clark #define DMM_PATSTATUS_ERR_UPD_AREA (1<<12) 708bb0daffSRob Clark #define DMM_PATSTATUS_ERR_UPD_CTRL (1<<13) 718bb0daffSRob Clark #define DMM_PATSTATUS_ERR_UPD_DATA (1<<14) 728bb0daffSRob Clark #define DMM_PATSTATUS_ERR_ACCESS (1<<15) 738bb0daffSRob Clark 748bb0daffSRob Clark /* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */ 758bb0daffSRob Clark #define DMM_PATSTATUS_ERR (DMM_PATSTATUS_ERR_INV_DESCR | \ 768bb0daffSRob Clark DMM_PATSTATUS_ERR_INV_DATA | \ 778bb0daffSRob Clark DMM_PATSTATUS_ERR_UPD_AREA | \ 788bb0daffSRob Clark DMM_PATSTATUS_ERR_UPD_CTRL | \ 798bb0daffSRob Clark DMM_PATSTATUS_ERR_UPD_DATA) 808bb0daffSRob Clark 818bb0daffSRob Clark 828bb0daffSRob Clark 838bb0daffSRob Clark enum { 848bb0daffSRob Clark PAT_STATUS, 858bb0daffSRob Clark PAT_DESCR 868bb0daffSRob Clark }; 878bb0daffSRob Clark 888bb0daffSRob Clark struct pat_ctrl { 898bb0daffSRob Clark u32 start:4; 908bb0daffSRob Clark u32 dir:4; 918bb0daffSRob Clark u32 lut_id:8; 928bb0daffSRob Clark u32 sync:12; 938bb0daffSRob Clark u32 ini:4; 948bb0daffSRob Clark }; 958bb0daffSRob Clark 968bb0daffSRob Clark struct pat { 97dfe9cfccSLaurent Pinchart u32 next_pa; 988bb0daffSRob Clark struct pat_area area; 998bb0daffSRob Clark struct pat_ctrl ctrl; 100dfe9cfccSLaurent Pinchart u32 data_pa; 1018bb0daffSRob Clark }; 1028bb0daffSRob Clark 1038bb0daffSRob Clark #define DMM_FIXED_RETRY_COUNT 1000 1048bb0daffSRob Clark 1058bb0daffSRob Clark /* create refill buffer big enough to refill all slots, plus 3 descriptors.. 1068bb0daffSRob Clark * 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area, 1078bb0daffSRob Clark * but I guess you don't hit that worst case at the same time as full area 1088bb0daffSRob Clark * refill 1098bb0daffSRob Clark */ 1108bb0daffSRob Clark #define DESCR_SIZE 128 1118bb0daffSRob Clark #define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE)) 1128bb0daffSRob Clark 1138bb0daffSRob Clark /* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers. 1148bb0daffSRob Clark * This is used in programming to address the upper portion of the LUT 1158bb0daffSRob Clark */ 1168bb0daffSRob Clark #define OMAP5_LUT_OFFSET 128 1178bb0daffSRob Clark 1188bb0daffSRob Clark struct dmm; 1198bb0daffSRob Clark 1208bb0daffSRob Clark struct dmm_txn { 1218bb0daffSRob Clark void *engine_handle; 1228bb0daffSRob Clark struct tcm *tcm; 1238bb0daffSRob Clark 124dfe9cfccSLaurent Pinchart u8 *current_va; 1258bb0daffSRob Clark dma_addr_t current_pa; 1268bb0daffSRob Clark 1278bb0daffSRob Clark struct pat *last_pat; 1288bb0daffSRob Clark }; 1298bb0daffSRob Clark 1308bb0daffSRob Clark struct refill_engine { 1318bb0daffSRob Clark int id; 1328bb0daffSRob Clark struct dmm *dmm; 1338bb0daffSRob Clark struct tcm *tcm; 1348bb0daffSRob Clark 135dfe9cfccSLaurent Pinchart u8 *refill_va; 1368bb0daffSRob Clark dma_addr_t refill_pa; 1378bb0daffSRob Clark 1388bb0daffSRob Clark /* only one trans per engine for now */ 1398bb0daffSRob Clark struct dmm_txn txn; 1408bb0daffSRob Clark 1418bb0daffSRob Clark bool async; 1428bb0daffSRob Clark 1437439507fSTomi Valkeinen struct completion compl; 1448bb0daffSRob Clark 1458bb0daffSRob Clark struct list_head idle_node; 1468bb0daffSRob Clark }; 1478bb0daffSRob Clark 1487cb0d6c1STomi Valkeinen struct dmm_platform_data { 149dfe9cfccSLaurent Pinchart u32 cpu_cache_flags; 1507cb0d6c1STomi Valkeinen }; 1517cb0d6c1STomi Valkeinen 1528bb0daffSRob Clark struct dmm { 1538bb0daffSRob Clark struct device *dev; 154f5b9930bSTomi Valkeinen dma_addr_t phys_base; 1558bb0daffSRob Clark void __iomem *base; 1568bb0daffSRob Clark int irq; 1578bb0daffSRob Clark 1588bb0daffSRob Clark struct page *dummy_page; 1598bb0daffSRob Clark dma_addr_t dummy_pa; 1608bb0daffSRob Clark 1618bb0daffSRob Clark void *refill_va; 1628bb0daffSRob Clark dma_addr_t refill_pa; 1638bb0daffSRob Clark 1648bb0daffSRob Clark /* refill engines */ 1658bb0daffSRob Clark wait_queue_head_t engine_queue; 1668bb0daffSRob Clark struct list_head idle_head; 1678bb0daffSRob Clark struct refill_engine *engines; 1688bb0daffSRob Clark int num_engines; 1698bb0daffSRob Clark atomic_t engine_counter; 1708bb0daffSRob Clark 1718bb0daffSRob Clark /* container information */ 1728bb0daffSRob Clark int container_width; 1738bb0daffSRob Clark int container_height; 1748bb0daffSRob Clark int lut_width; 1758bb0daffSRob Clark int lut_height; 1768bb0daffSRob Clark int num_lut; 1778bb0daffSRob Clark 1788bb0daffSRob Clark /* array of LUT - TCM containers */ 1798bb0daffSRob Clark struct tcm **tcm; 1808bb0daffSRob Clark 1818bb0daffSRob Clark /* allocation list and lock */ 1828bb0daffSRob Clark struct list_head alloc_head; 1837cb0d6c1STomi Valkeinen 1847cb0d6c1STomi Valkeinen const struct dmm_platform_data *plat_data; 185f5b9930bSTomi Valkeinen 186f5b9930bSTomi Valkeinen bool dmm_workaround; 187f5b9930bSTomi Valkeinen spinlock_t wa_lock; 188f5b9930bSTomi Valkeinen u32 *wa_dma_data; 189f5b9930bSTomi Valkeinen dma_addr_t wa_dma_handle; 190f5b9930bSTomi Valkeinen struct dma_chan *wa_dma_chan; 1918bb0daffSRob Clark }; 1928bb0daffSRob Clark 1938bb0daffSRob Clark #endif 194